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authorLudovic Desroches <ludovic.desroches@atmel.com>2013-06-13 04:39:39 -0400
committerVinod Koul <vinod.koul@intel.com>2013-07-05 02:10:54 -0400
commit62971b29825adb06908bad81e7679d1f7904b24d (patch)
tree6b2c29be1793d6c60ac80a4abc8686aee10dcc47 /Documentation/devicetree/bindings/dma/atmel-dma.txt
parent764037c6f55c5c844d0ab6049e6e7c0dc3cb7665 (diff)
dmaengine: at_hdmac: add FIFO configuration parameter to DMA DT binding
For most devices the FIFO configuration is the same i.e. when half FIFO size is available/filled, a source/destination request is serviced. But USART devices have to do it when there is enough space/data available to perform a single AHB access so the ASAP configuration. Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Diffstat (limited to 'Documentation/devicetree/bindings/dma/atmel-dma.txt')
-rw-r--r--Documentation/devicetree/bindings/dma/atmel-dma.txt7
1 files changed, 5 insertions, 2 deletions
diff --git a/Documentation/devicetree/bindings/dma/atmel-dma.txt b/Documentation/devicetree/bindings/dma/atmel-dma.txt
index c80e8a3402f0..c280a0e6f42d 100644
--- a/Documentation/devicetree/bindings/dma/atmel-dma.txt
+++ b/Documentation/devicetree/bindings/dma/atmel-dma.txt
@@ -24,8 +24,11 @@ The three cells in order are:
241. A phandle pointing to the DMA controller. 241. A phandle pointing to the DMA controller.
252. The memory interface (16 most significant bits), the peripheral interface 252. The memory interface (16 most significant bits), the peripheral interface
26(16 less significant bits). 26(16 less significant bits).
273. The peripheral identifier for the hardware handshaking interface. The 273. Parameters for the at91 DMA configuration register which are device
28identifier can be different for tx and rx. 28dependant:
29 - bit 7-0: peripheral identifier for the hardware handshaking interface. The
30 identifier can be different for tx and rx.
31 - bit 11-8: FIFO configuration. 0 for half FIFO, 1 for ALAP, 1 for ASAP.
29 32
30Example: 33Example:
31 34