cpufreq: Add a generic cpufreq-cpu0 driver

It adds a generic cpufreq driver for CPU0 frequency management based on
clk, regulator, OPP and device tree support.  It can support both
uniprocessor (UP) and those symmetric multiprocessor (SMP) systems which
share clock and voltage across all CPUs.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: AnilKumar Ch <anilkumar@ti.com>
Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>

1 files changed, 55 insertions, 0 deletions

diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
new file mode 100644
index 000000000000..4416ccc33472
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-cpu0.txt
@@ -0,0 +1,55 @@
+Generic CPU0 cpufreq driver
+
+It is a generic cpufreq driver for CPU0 frequency management.  It
+supports both uniprocessor (UP) and symmetric multiprocessor (SMP)
+systems which share clock and voltage across all CPUs.
+
+Both required and optional properties listed below must be defined
+under node /cpus/cpu@0.
+
+Required properties:
+- operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt
+  for details
+
+Optional properties:
+- clock-latency: Specify the possible maximum transition latency for clock,
+  in unit of nanoseconds.
+- voltage-tolerance: Specify the CPU voltage tolerance in percentage.
+
+Examples:
+
+cpus {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        cpu@0 {
+                compatible = "arm,cortex-a9";
+                reg = <0>;
+                next-level-cache = <&L2>;
+                operating-points = <
+                        /* kHz    uV */
+                        792000  1100000
+                        396000  950000
+                        198000  850000
+                >;
+                transition-latency = <61036>; /* two CLK32 periods */
+        };
+
+        cpu@1 {
+                compatible = "arm,cortex-a9";
+                reg = <1>;
+                next-level-cache = <&L2>;
+        };
+
+        cpu@2 {
+                compatible = "arm,cortex-a9";
+                reg = <2>;
+                next-level-cache = <&L2>;
+        };
+
+        cpu@3 {
+                compatible = "arm,cortex-a9";
+                reg = <3>;
+                next-level-cache = <&L2>;
+        };
+};