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authorLinus Walleij <linus.walleij@linaro.org>2013-06-04 17:17:21 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-06-20 04:15:30 -0400
commitef6eb322ce574ba73658a677e83e5da3cfab301b (patch)
tree59c5f5610e9c78becb091e44eb3f45f79c7b35e9 /Documentation/devicetree/bindings/clock
parent3fd765a91749b14af7e76bec7f6e0b364f8d99af (diff)
clk: nomadik: implement the Nomadik clocks properly
The Nomadik clock implementation was a stub just using fixed clocks. This implements the clocks properly instead of relying on them all being on at boot and leaving them all on. The PLLs are on the top locking to the main chrystal oscillator, then the HCLK for the peripherals are below PLL2. The gated clocks are implemented with zero cells and given the clock ID as a property of each node, so every gate need to have its own node in the device tree. This is because the gate registers contain both HCLK gates and PCLK gates, where the latter has HCLK as parent. As can be seen from the register layout, this is a complete mixup, which means all these gates need their own node to properly model parent/child relations for PCLKs apart from the HCLKs. This driver also adds a helpful debugfs file to inspect the hardware state of the clock gates. This is the end result in <debugfs>/clk/clk_summary after applying a proper device tree: ulpiclk 0 0 60000000 mxtal 3 3 19200000 pll2 1 1 864000000 clk48 3 3 48000000 rngcclk 1 1 48000000 usbmclk 0 0 48000000 mshcclk 0 0 48000000 mspclk3 0 0 48000000 x3dclk 0 0 48000000 skeclk 0 0 48000000 owmclk 0 0 48000000 mspclk2 0 0 48000000 mspclk1 0 0 48000000 uart2clk 0 0 48000000 ipbmcclk 0 0 48000000 ipi2cclk 0 0 48000000 usbclk 0 0 48000000 mspclk0 0 0 48000000 uart1clk 1 2 48000000 i2c1clk 0 0 48000000 i2c0clk 0 0 48000000 sdiclk 1 1 48000000 uart0clk 0 0 48000000 sspiclk 0 0 48000000 irdaclk 0 0 48000000 clk72 0 0 72000000 difclk 0 0 72000000 clcdclk 0 0 72000000 clk216 0 0 216000000 hsiclkrx 0 0 216000000 clk108 0 0 108000000 hsiclktx 0 0 108000000 clk27 0 0 27000000 pll1 1 1 264000000 hclk 3 3 264000000 hclkrng 1 1 264000000 hclkusbm 0 0 264000000 hclkcryp 0 0 264000000 hclkhash 0 0 264000000 hclk3d 0 0 264000000 hclkhpi 0 0 264000000 hclksva 0 0 264000000 hclksaa 0 0 264000000 hclkdif 0 0 264000000 hclkusb 0 0 264000000 hclkclcd 0 0 264000000 hclkdma1 0 0 264000000 hclksdram 0 0 264000000 hclksmc 1 1 264000000 hclkdma0 0 0 264000000 pclk 7 9 264000000 pclkmsp3 0 0 264000000 pclkmshc 0 0 264000000 pclkhsem 0 0 264000000 pclkske 0 0 264000000 pclkowm 0 0 264000000 pclkmsp2 0 0 264000000 pclkmsp1 0 0 264000000 pclkuart2 0 0 264000000 pclkxti 0 0 264000000 pclkhsi 0 0 264000000 pclkmsp0 0 0 264000000 pclkuart1 1 1 264000000 pclki2c1 0 0 264000000 pclki2c0 0 0 264000000 pclksdi 1 1 264000000 pclkuart0 1 1 264000000 pclkssp 0 0 264000000 pclkirda 0 0 264000000 timclk 1 1 2400000 Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock')
-rw-r--r--Documentation/devicetree/bindings/clock/st,nomadik.txt104
1 files changed, 104 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/st,nomadik.txt b/Documentation/devicetree/bindings/clock/st,nomadik.txt
new file mode 100644
index 000000000000..7fc09773de46
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/st,nomadik.txt
@@ -0,0 +1,104 @@
1ST Microelectronics Nomadik SRC System Reset and Control
2
3This binding uses the common clock binding:
4Documentation/devicetree/bindings/clock/clock-bindings.txt
5
6The Nomadik SRC controller is responsible of controlling chrystals,
7PLLs and clock gates.
8
9Required properties for the SRC node:
10- compatible: must be "stericsson,nomadik-src"
11- reg: must contain the SRC register base and size
12
13Optional properties for the SRC node:
14- disable-sxtalo: if present this will disable the SXTALO
15 i.e. the driver output for the slow 32kHz chrystal, if the
16 board has its own circuitry for providing this oscillator
17- disable-mxtal: if present this will disable the MXTALO,
18 i.e. the driver output for the main (~19.2 MHz) chrystal,
19 if the board has its own circuitry for providing this
20 osciallator
21
22
23PLL nodes: these nodes represent the two PLLs on the system,
24which should both have the main chrystal, represented as a
25fixed frequency clock, as parent.
26
27Required properties for the two PLL nodes:
28- compatible: must be "st,nomadik-pll-clock"
29- clock-cells: must be 0
30- clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
31- clocks: this clock will have main chrystal as parent
32
33
34HCLK nodes: these represent the clock gates on individual
35lines from the HCLK clock tree and the gate for individual
36lines from the PCLK clock tree.
37
38Requires properties for the HCLK nodes:
39- compatible: must be "st,nomadik-hclk-clock"
40- clock-cells: must be 0
41- clock-id: must be the clock ID from 0 to 63 according to
42 this table:
43
44 0: HCLKDMA0
45 1: HCLKSMC
46 2: HCLKSDRAM
47 3: HCLKDMA1
48 4: HCLKCLCD
49 5: PCLKIRDA
50 6: PCLKSSP
51 7: PCLKUART0
52 8: PCLKSDI
53 9: PCLKI2C0
54 10: PCLKI2C1
55 11: PCLKUART1
56 12: PCLMSP0
57 13: HCLKUSB
58 14: HCLKDIF
59 15: HCLKSAA
60 16: HCLKSVA
61 17: PCLKHSI
62 18: PCLKXTI
63 19: PCLKUART2
64 20: PCLKMSP1
65 21: PCLKMSP2
66 22: PCLKOWM
67 23: HCLKHPI
68 24: PCLKSKE
69 25: PCLKHSEM
70 26: HCLK3D
71 27: HCLKHASH
72 28: HCLKCRYP
73 29: PCLKMSHC
74 30: HCLKUSBM
75 31: HCLKRNG
76 (32, 33, 34, 35 RESERVED)
77 36: CLDCLK
78 37: IRDACLK
79 38: SSPICLK
80 39: UART0CLK
81 40: SDICLK
82 41: I2C0CLK
83 42: I2C1CLK
84 43: UART1CLK
85 44: MSPCLK0
86 45: USBCLK
87 46: DIFCLK
88 47: IPI2CCLK
89 48: IPBMCCLK
90 49: HSICLKRX
91 50: HSICLKTX
92 51: UART2CLK
93 52: MSPCLK1
94 53: MSPCLK2
95 54: OWMCLK
96 (55 RESERVED)
97 56: SKECLK
98 (57 RESERVED)
99 58: 3DCLK
100 59: PCLKMSP3
101 60: MSPCLK3
102 61: MSHCCLK
103 62: USBMCLK
104 63: RNGCCLK
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 02:41:52 -0500