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authorHiroshi DOYU <hdoyu@nvidia.com>2012-05-10 03:42:32 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-05-10 17:46:09 -0400
commitaf4681097b23fe9c63a03d774de7c742fa3a920e (patch)
tree326ef53d1fa28d46410896f866f5e4ff9ddf792e /Documentation/devicetree/bindings/arm/tegra
parentc542fb79fba4c63aa6e2a27f90373b0516614eca (diff)
ARM: tegra30: Add Tegra Memory Controller(MC) driver
Tegra Memory Controller(MC) driver for Tegra30 Added to support MC General interrupts, mainly for IOMMU(SMMU). Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'Documentation/devicetree/bindings/arm/tegra')
-rw-r--r--Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt18
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diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra30-mc.txt
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1NVIDIA Tegra30 MC(Memory Controller)
2
3Required properties:
4- compatible : "nvidia,tegra30-mc"
5- reg : Should contain 4 register ranges(address and length); see the
6 example below. Note that the MC registers are interleaved with the
7 SMMU registers, and hence must be represented as multiple ranges.
8- interrupts : Should contain MC General interrupt.
9
10Example:
11 mc {
12 compatible = "nvidia,tegra30-mc";
13 reg = <0x7000f000 0x010
14 0x7000f03c 0x1b4
15 0x7000f200 0x028
16 0x7000f284 0x17c>;
17 interrupts = <0 77 0x04>;
18 };