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authorDan Williams <dan.j.williams@intel.com>2009-01-05 19:14:31 -0500
committerDan Williams <dan.j.williams@intel.com>2009-01-05 20:10:19 -0500
commit28405d8d9ce05f5bd869ef8b48da5086f9527d73 (patch)
treef3e68349cc38b4dc0a437455ba9513be78f620ae /Documentation/crypto
parentfe0bdec68b77020281dc814805edfe594ae89e0f (diff)
async_tx, dmaengine: document channel allocation and api rework
"Wouldn't it be better if the dmaengine layer made sure it didn't pass the same channel several times to a client? I mean, you seem concerned that the memcpy() API should be transparent and easy to use, but the whole registration interface is just ridiculously complicated..." - Haavard The dmaengine and async_tx registration/allocation interface is indeed needlessly complicated. This redesign has the following goals: 1/ Simplify reference counting: dma channels are not something one would expect to be hotplugged, it should be an exceptional event handled by drivers not something clients should be mandated to handle in a callback. The common case channel removal event is 'rmmod <dma driver>', which for simplicity should be disallowed if the channel is in use. 2/ Add an interface for requesting exclusive access to a channel suitable to device-to-memory users. 3/ Convert all memory-to-memory users over to a common allocator, the goal here is to not have competing channel allocation schemes. The only competition should be between device-to-memory exclusive allocations and the memory-to-memory usage case where channels are shared between multiple "clients". Cc: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> Cc: Neil Brown <neilb@suse.de> Cc: Jeff Garzik <jeff@garzik.org> Reviewed-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Diffstat (limited to 'Documentation/crypto')
-rw-r--r--Documentation/crypto/async-tx-api.txt96
1 files changed, 44 insertions, 52 deletions
diff --git a/Documentation/crypto/async-tx-api.txt b/Documentation/crypto/async-tx-api.txt
index c1e9545c59bd..9f59fcbf5d82 100644
--- a/Documentation/crypto/async-tx-api.txt
+++ b/Documentation/crypto/async-tx-api.txt
@@ -13,9 +13,9 @@
133.6 Constraints 133.6 Constraints
143.7 Example 143.7 Example
15 15
164 DRIVER DEVELOPER NOTES 164 DMAENGINE DRIVER DEVELOPER NOTES
174.1 Conformance points 174.1 Conformance points
184.2 "My application needs finer control of hardware channels" 184.2 "My application needs exclusive control of hardware channels"
19 19
205 SOURCE 205 SOURCE
21 21
@@ -150,6 +150,7 @@ ops_run_* and ops_complete_* routines in drivers/md/raid5.c for more
150implementation examples. 150implementation examples.
151 151
1524 DRIVER DEVELOPMENT NOTES 1524 DRIVER DEVELOPMENT NOTES
153
1534.1 Conformance points: 1544.1 Conformance points:
154There are a few conformance points required in dmaengine drivers to 155There are a few conformance points required in dmaengine drivers to
155accommodate assumptions made by applications using the async_tx API: 156accommodate assumptions made by applications using the async_tx API:
@@ -158,58 +159,49 @@ accommodate assumptions made by applications using the async_tx API:
1583/ Use async_tx_run_dependencies() in the descriptor clean up path to 1593/ Use async_tx_run_dependencies() in the descriptor clean up path to
159 handle submission of dependent operations 160 handle submission of dependent operations
160 161
1614.2 "My application needs finer control of hardware channels" 1624.2 "My application needs exclusive control of hardware channels"
162This requirement seems to arise from cases where a DMA engine driver is 163Primarily this requirement arises from cases where a DMA engine driver
163trying to support device-to-memory DMA. The dmaengine and async_tx 164is being used to support device-to-memory operations. A channel that is
164implementations were designed for offloading memory-to-memory 165performing these operations cannot, for many platform specific reasons,
165operations; however, there are some capabilities of the dmaengine layer 166be shared. For these cases the dma_request_channel() interface is
166that can be used for platform-specific channel management. 167provided.
167Platform-specific constraints can be handled by registering the 168
168application as a 'dma_client' and implementing a 'dma_event_callback' to 169The interface is:
169apply a filter to the available channels in the system. Before showing 170struct dma_chan *dma_request_channel(dma_cap_mask_t mask,
170how to implement a custom dma_event callback some background of 171 dma_filter_fn filter_fn,
171dmaengine's client support is required. 172 void *filter_param);
172 173
173The following routines in dmaengine support multiple clients requesting 174Where dma_filter_fn is defined as:
174use of a channel: 175typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
175- dma_async_client_register(struct dma_client *client) 176
176- dma_async_client_chan_request(struct dma_client *client) 177When the optional 'filter_fn' parameter is set to NULL
177 178dma_request_channel simply returns the first channel that satisfies the
178dma_async_client_register takes a pointer to an initialized dma_client 179capability mask. Otherwise, when the mask parameter is insufficient for
179structure. It expects that the 'event_callback' and 'cap_mask' fields 180specifying the necessary channel, the filter_fn routine can be used to
180are already initialized. 181disposition the available channels in the system. The filter_fn routine
181 182is called once for each free channel in the system. Upon seeing a
182dma_async_client_chan_request triggers dmaengine to notify the client of 183suitable channel filter_fn returns DMA_ACK which flags that channel to
183all channels that satisfy the capability mask. It is up to the client's 184be the return value from dma_request_channel. A channel allocated via
184event_callback routine to track how many channels the client needs and 185this interface is exclusive to the caller, until dma_release_channel()
185how many it is currently using. The dma_event_callback routine returns a 186is called.
186dma_state_client code to let dmaengine know the status of the 187
187allocation. 188The DMA_PRIVATE capability flag is used to tag dma devices that should
188 189not be used by the general-purpose allocator. It can be set at
189Below is the example of how to extend this functionality for 190initialization time if it is known that a channel will always be
190platform-specific filtering of the available channels beyond the 191private. Alternatively, it is set when dma_request_channel() finds an
191standard capability mask: 192unused "public" channel.
192 193
193static enum dma_state_client 194A couple caveats to note when implementing a driver and consumer:
194my_dma_client_callback(struct dma_client *client, 1951/ Once a channel has been privately allocated it will no longer be
195 struct dma_chan *chan, enum dma_state state) 196 considered by the general-purpose allocator even after a call to
196{ 197 dma_release_channel().
197 struct dma_device *dma_dev; 1982/ Since capabilities are specified at the device level a dma_device
198 struct my_platform_specific_dma *plat_dma_dev; 199 with multiple channels will either have all channels public, or all
199 200 channels private.
200 dma_dev = chan->device;
201 plat_dma_dev = container_of(dma_dev,
202 struct my_platform_specific_dma,
203 dma_dev);
204
205 if (!plat_dma_dev->platform_specific_capability)
206 return DMA_DUP;
207
208 . . .
209}
210 201
2115 SOURCE 2025 SOURCE
212include/linux/dmaengine.h: core header file for DMA drivers and clients 203
204include/linux/dmaengine.h: core header file for DMA drivers and api users
213drivers/dma/dmaengine.c: offload engine channel management routines 205drivers/dma/dmaengine.c: offload engine channel management routines
214drivers/dma/: location for offload engine drivers 206drivers/dma/: location for offload engine drivers
215include/linux/async_tx.h: core header file for the async_tx api 207include/linux/async_tx.h: core header file for the async_tx api