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authorJungseok Lee <jays.lee@samsung.com>2014-05-12 05:40:44 -0400
committerCatalin Marinas <catalin.marinas@arm.com>2014-07-23 10:27:28 -0400
commit4edae01e89100821d167076dec6ecdd40318b7c1 (patch)
treed8a982c4bde5a8ad8fca6900d44ff90bcb5686cf /Documentation/arm64
parente41ceed035966d593ae34c3de33924965a6b9fba (diff)
arm64: Add a description on 48-bit address space with 4KB pages
This patch adds memory layout and translation lookup information about 48-bit address space with 4K pages. The description is based on 4 levels of translation tables. Signed-off-by: Jungseok Lee <jays.lee@samsung.com> Reviewed-by: Sungjinn Chung <sungjinn.chung@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Jungseok Lee <jungseoklee85@gmail.com>
Diffstat (limited to 'Documentation/arm64')
-rw-r--r--Documentation/arm64/memory.txt59
1 files changed, 51 insertions, 8 deletions
diff --git a/Documentation/arm64/memory.txt b/Documentation/arm64/memory.txt
index d50fa618371b..4c720d698e8e 100644
--- a/Documentation/arm64/memory.txt
+++ b/Documentation/arm64/memory.txt
@@ -8,10 +8,11 @@ This document describes the virtual memory layout used by the AArch64
8Linux kernel. The architecture allows up to 4 levels of translation 8Linux kernel. The architecture allows up to 4 levels of translation
9tables with a 4KB page size and up to 3 levels with a 64KB page size. 9tables with a 4KB page size and up to 3 levels with a 64KB page size.
10 10
11AArch64 Linux uses 3 levels of translation tables with the 4KB page 11AArch64 Linux uses either 3 levels or 4 levels of translation tables with
12configuration, allowing 39-bit (512GB) virtual addresses for both user 12the 4KB page configuration, allowing 39-bit (512GB) or 48-bit (256TB)
13and kernel. With 64KB pages, only 2 levels of translation tables are 13virtual addresses, respectively, for both user and kernel. With 64KB
14used but the memory layout is the same. 14pages, only 2 levels of translation tables, allowing 42-bit (4TB)
15virtual address, are used but the memory layout is the same.
15 16
16User addresses have bits 63:39 set to 0 while the kernel addresses have 17User addresses have bits 63:39 set to 0 while the kernel addresses have
17the same bits set to 1. TTBRx selection is given by bit 63 of the 18the same bits set to 1. TTBRx selection is given by bit 63 of the
@@ -21,7 +22,7 @@ The swapper_pgd_dir address is written to TTBR1 and never written to
21TTBR0. 22TTBR0.
22 23
23 24
24AArch64 Linux memory layout with 4KB pages: 25AArch64 Linux memory layout with 4KB pages + 3 levels:
25 26
26Start End Size Use 27Start End Size Use
27----------------------------------------------------------------------- 28-----------------------------------------------------------------------
@@ -48,7 +49,34 @@ ffffffbffc000000 ffffffbfffffffff 64MB modules
48ffffffc000000000 ffffffffffffffff 256GB kernel logical memory map 49ffffffc000000000 ffffffffffffffff 256GB kernel logical memory map
49 50
50 51
51AArch64 Linux memory layout with 64KB pages: 52AArch64 Linux memory layout with 4KB pages + 4 levels:
53
54Start End Size Use
55-----------------------------------------------------------------------
560000000000000000 0000ffffffffffff 256TB user
57
58ffff000000000000 ffff7bfffffeffff ~124TB vmalloc
59
60ffff7bffffff0000 ffff7bffffffffff 64KB [guard page]
61
62ffff7c0000000000 ffff7dffffffffff 2TB vmemmap
63
64ffff7e0000000000 ffff7ffffbbfffff ~2TB [guard, future vmmemap]
65
66ffff7ffffa000000 ffff7ffffaffffff 16MB PCI I/O space
67
68ffff7ffffb000000 ffff7ffffbbfffff 12MB [guard]
69
70ffff7ffffbc00000 ffff7ffffbdfffff 2MB fixed mappings
71
72ffff7ffffbe00000 ffff7ffffbffffff 2MB [guard]
73
74ffff7ffffc000000 ffff7fffffffffff 64MB modules
75
76ffff800000000000 ffffffffffffffff 128TB kernel logical memory map
77
78
79AArch64 Linux memory layout with 64KB pages + 2 levels:
52 80
53Start End Size Use 81Start End Size Use
54----------------------------------------------------------------------- 82-----------------------------------------------------------------------
@@ -75,7 +103,7 @@ fffffdfffc000000 fffffdffffffffff 64MB modules
75fffffe0000000000 ffffffffffffffff 2TB kernel logical memory map 103fffffe0000000000 ffffffffffffffff 2TB kernel logical memory map
76 104
77 105
78Translation table lookup with 4KB pages: 106Translation table lookup with 4KB pages + 3 levels:
79 107
80+--------+--------+--------+--------+--------+--------+--------+--------+ 108+--------+--------+--------+--------+--------+--------+--------+--------+
81|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0| 109|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
@@ -90,7 +118,22 @@ Translation table lookup with 4KB pages:
90 +-------------------------------------------------> [63] TTBR0/1 118 +-------------------------------------------------> [63] TTBR0/1
91 119
92 120
93Translation table lookup with 64KB pages: 121Translation table lookup with 4KB pages + 4 levels:
122
123+--------+--------+--------+--------+--------+--------+--------+--------+
124|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|
125+--------+--------+--------+--------+--------+--------+--------+--------+
126 | | | | | |
127 | | | | | v
128 | | | | | [11:0] in-page offset
129 | | | | +-> [20:12] L3 index
130 | | | +-----------> [29:21] L2 index
131 | | +---------------------> [38:30] L1 index
132 | +-------------------------------> [47:39] L0 index
133 +-------------------------------------------------> [63] TTBR0/1
134
135
136Translation table lookup with 64KB pages + 2 levels:
94 137
95+--------+--------+--------+--------+--------+--------+--------+--------+ 138+--------+--------+--------+--------+--------+--------+--------+--------+
96|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0| 139|63 56|55 48|47 40|39 32|31 24|23 16|15 8|7 0|