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authorNicolas Ferre <nicolas.ferre@atmel.com>2010-10-22 12:55:39 -0400
committerNicolas Ferre <nicolas.ferre@atmel.com>2010-10-26 05:32:48 -0400
commita2a571b74a3881963d8d09deb272d13afe5b49e3 (patch)
tree491cf5ff56293287906f9cfec785345f24cd2180 /Documentation/RCU
parent8aeeda822fbfe7da2d4ea391a9757e9532796598 (diff)
AT91: pm: make sure that r0 is 0 when dealing with cache operations
When using CP15 cache operations (c7), we make sure that Rd (r0) is actually 0 as ARM 926 TRM is saying. Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
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