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authorHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com>2010-04-15 00:21:27 -0400
committerJesse Barnes <jbarnes@virtuousgeek.org>2010-05-11 15:01:38 -0400
commit89713422a768458a0d375f0c2f3586cd5ccde6a1 (patch)
treec446440123602cdb5320617ac7a8c2dbf514ff41 /Documentation/PCI/pcieaer-howto.txt
parent517cae3829ae8cc3033c24f60e64eb251b2f0d14 (diff)
PCI: aerdrv: introduce default_downstream_reset_link
I noticed that when I inject a fatal error to an endpoint via aer-inject, aer_root_reset() is called as reset_link for a downstream port at upstream of the endpoint: pcieport 0000:00:06.0: AER: Uncorrected (Fatal) error received: id=5401 : pcieport 0000:52:02.0: Root Port link has been reset It externally appears to be working, but internally issues some accesses to PCI_ERR_ROOT_COMMAND/STATUS registers that is for root port so not available on downstream port. This patch introduces default_downstream_reset_link that is a version of aer_root_reset() with no accesses to root port's register. It is used for downstream ports that has no reset_link function its specific. This patch also updates related description in pcieaer-howto.txt. Some minor fixes are included. Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Diffstat (limited to 'Documentation/PCI/pcieaer-howto.txt')
-rw-r--r--Documentation/PCI/pcieaer-howto.txt15
1 files changed, 8 insertions, 7 deletions
diff --git a/Documentation/PCI/pcieaer-howto.txt b/Documentation/PCI/pcieaer-howto.txt
index 8c406a496799..26d3d945c3c2 100644
--- a/Documentation/PCI/pcieaer-howto.txt
+++ b/Documentation/PCI/pcieaer-howto.txt
@@ -13,7 +13,7 @@ Reporting (AER) driver and provides information on how to use it, as
13well as how to enable the drivers of endpoint devices to conform with 13well as how to enable the drivers of endpoint devices to conform with
14PCI Express AER driver. 14PCI Express AER driver.
15 15
161.2 Copyright © Intel Corporation 2006. 161.2 Copyright (C) Intel Corporation 2006.
17 17
181.3 What is the PCI Express AER Driver? 181.3 What is the PCI Express AER Driver?
19 19
@@ -108,7 +108,7 @@ but the PCI Express link itself is fully functional. Fatal errors, on
108the other hand, cause the link to be unreliable. 108the other hand, cause the link to be unreliable.
109 109
110When AER is enabled, a PCI Express device will automatically send an 110When AER is enabled, a PCI Express device will automatically send an
111error message to the PCIE root port above it when the device captures 111error message to the PCIe root port above it when the device captures
112an error. The Root Port, upon receiving an error reporting message, 112an error. The Root Port, upon receiving an error reporting message,
113internally processes and logs the error message in its PCI Express 113internally processes and logs the error message in its PCI Express
114capability structure. Error information being logged includes storing 114capability structure. Error information being logged includes storing
@@ -194,8 +194,9 @@ to reset link, AER port service driver is required to provide the
194function to reset link. Firstly, kernel looks for if the upstream 194function to reset link. Firstly, kernel looks for if the upstream
195component has an aer driver. If it has, kernel uses the reset_link 195component has an aer driver. If it has, kernel uses the reset_link
196callback of the aer driver. If the upstream component has no aer driver 196callback of the aer driver. If the upstream component has no aer driver
197and the port is downstream port, we will use the aer driver of the 197and the port is downstream port, we will perform a hot reset as the
198root port who reports the AER error. As for upstream ports, 198default by setting the Secondary Bus Reset bit of the Bridge Control
199register associated with the downstream port. As for upstream ports,
199they should provide their own aer service drivers with reset_link 200they should provide their own aer service drivers with reset_link
200function. If error_detected returns PCI_ERS_RESULT_CAN_RECOVER and 201function. If error_detected returns PCI_ERS_RESULT_CAN_RECOVER and
201reset_link returns PCI_ERS_RESULT_RECOVERED, the error handling goes 202reset_link returns PCI_ERS_RESULT_RECOVERED, the error handling goes
@@ -249,11 +250,11 @@ cleanup uncorrectable status register. Pls. refer to section 3.3.
249 250
2504. Software error injection 2514. Software error injection
251 252
252Debugging PCIE AER error recovery code is quite difficult because it 253Debugging PCIe AER error recovery code is quite difficult because it
253is hard to trigger real hardware errors. Software based error 254is hard to trigger real hardware errors. Software based error
254injection can be used to fake various kinds of PCIE errors. 255injection can be used to fake various kinds of PCIe errors.
255 256
256First you should enable PCIE AER software error injection in kernel 257First you should enable PCIe AER software error injection in kernel
257configuration, that is, following item should be in your .config. 258configuration, that is, following item should be in your .config.
258 259
259CONFIG_PCIEAER_INJECT=y or CONFIG_PCIEAER_INJECT=m 260CONFIG_PCIEAER_INJECT=y or CONFIG_PCIEAER_INJECT=m