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authorKeshavamurthy, Anil S <anil.s.keshavamurthy@intel.com>2007-10-21 19:41:54 -0400
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-10-22 11:13:19 -0400
commit3460a6d9cef9ac2aa997da7eff7ff1c8291b361c (patch)
tree3cf7eb916456d781d2edb135f9069f7c94d10085 /Documentation/Intel-IOMMU.txt
parent7d3b03ce7bff9d39ebaee1bb8de1968c4434b883 (diff)
Intel IOMMU: DMAR fault handling support
MSI interrupt handler registrations and fault handling support for Intel-IOMMU hadrware. This patch enables the MSI interrupts for the DMA remapping units and in the interrupt handler read the fault cause and outputs the same on to the console. Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'Documentation/Intel-IOMMU.txt')
-rw-r--r--Documentation/Intel-IOMMU.txt17
1 files changed, 17 insertions, 0 deletions
diff --git a/Documentation/Intel-IOMMU.txt b/Documentation/Intel-IOMMU.txt
index cbb4dbaef761..aba7722c2935 100644
--- a/Documentation/Intel-IOMMU.txt
+++ b/Documentation/Intel-IOMMU.txt
@@ -63,6 +63,15 @@ Interrupt ranges are not address translated, (0xfee00000 - 0xfeefffff).
63The same is true for peer to peer transactions. Hence we reserve the 63The same is true for peer to peer transactions. Hence we reserve the
64address from PCI MMIO ranges so they are not allocated for IOVA addresses. 64address from PCI MMIO ranges so they are not allocated for IOVA addresses.
65 65
66
67Fault reporting
68---------------
69When errors are reported, the DMA engine signals via an interrupt. The fault
70reason and device that caused it with fault reason is printed on console.
71
72See below for sample.
73
74
66Boot Message Sample 75Boot Message Sample
67------------------- 76-------------------
68 77
@@ -85,6 +94,14 @@ When DMAR is enabled for use, you will notice..
85 94
86PCI-DMA: Using DMAR IOMMU 95PCI-DMA: Using DMAR IOMMU
87 96
97Fault reporting
98---------------
99
100DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
101DMAR:[fault reason 05] PTE Write access is not set
102DMAR:[DMA Write] Request device [00:02.0] fault addr 6df084000
103DMAR:[fault reason 05] PTE Write access is not set
104
88TBD 105TBD
89---- 106----
90 107