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authorMaxime Hadjinlian <maxime.hadjinlian@gmail.com>2013-12-24 07:53:18 -0500
committerJason Cooper <jason@lakedaemon.net>2013-12-24 21:03:36 -0500
commite38cd3ae6e6f2bd5d376bc146d9f129402b82158 (patch)
tree0d3ff1ce71d969599792b41db39a49276a715e33
parent72c3e2295c1955b9d188dbaf910bc67a4dc2e3e5 (diff)
ARM: Kirkwood: Add 6192 DTSI file
This file is mainly a copy of kirkwood-6281.dtsi. The pinctrl seems to be the same. These platforms differs only with their CPU, memory capabilities and the number of GPIO available (36 on 6192, 50 on 6281). Signed-off-by: Maxime Hadjinlian <maxime.hadjinlian@gmail.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
-rw-r--r--arch/arm/boot/dts/kirkwood-6192.dtsi107
1 files changed, 107 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/kirkwood-6192.dtsi b/arch/arm/boot/dts/kirkwood-6192.dtsi
new file mode 100644
index 000000000000..3916937d6818
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-6192.dtsi
@@ -0,0 +1,107 @@
1/ {
2 mbus {
3 pcie-controller {
4 compatible = "marvell,kirkwood-pcie";
5 status = "disabled";
6 device_type = "pci";
7
8 #address-cells = <3>;
9 #size-cells = <2>;
10
11 bus-range = <0x00 0xff>;
12
13 ranges =
14 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
15 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
16 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>;
17
18 pcie@1,0 {
19 device_type = "pci";
20 assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>;
21 reg = <0x0800 0 0 0 0>;
22 #address-cells = <3>;
23 #size-cells = <2>;
24 #interrupt-cells = <1>;
25 ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
26 0x81000000 0 0 0x81000000 0x1 0 1 0>;
27 interrupt-map-mask = <0 0 0 0>;
28 interrupt-map = <0 0 0 0 &intc 9>;
29 marvell,pcie-port = <0>;
30 marvell,pcie-lane = <0>;
31 clocks = <&gate_clk 2>;
32 status = "disabled";
33 };
34 };
35 };
36
37 ocp@f1000000 {
38 pinctrl: pinctrl@10000 {
39 compatible = "marvell,88f6192-pinctrl";
40 reg = <0x10000 0x20>;
41
42 pmx_nand: pmx-nand {
43 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3",
44 "mpp4", "mpp5", "mpp18",
45 "mpp19";
46 marvell,function = "nand";
47 };
48 pmx_sata0: pmx-sata0 {
49 marvell,pins = "mpp5", "mpp21", "mpp23";
50 marvell,function = "sata0";
51 };
52 pmx_sata1: pmx-sata1 {
53 marvell,pins = "mpp4", "mpp20", "mpp22";
54 marvell,function = "sata1";
55 };
56 pmx_spi: pmx-spi {
57 marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3";
58 marvell,function = "spi";
59 };
60 pmx_twsi0: pmx-twsi0 {
61 marvell,pins = "mpp8", "mpp9";
62 marvell,function = "twsi0";
63 };
64 pmx_uart0: pmx-uart0 {
65 marvell,pins = "mpp10", "mpp11";
66 marvell,function = "uart0";
67 };
68 pmx_uart1: pmx-uart1 {
69 marvell,pins = "mpp13", "mpp14";
70 marvell,function = "uart1";
71 };
72 pmx_sdio: pmx-sdio {
73 marvell,pins = "mpp12", "mpp13", "mpp14",
74 "mpp15", "mpp16", "mpp17";
75 marvell,function = "sdio";
76 };
77 };
78
79 rtc@10300 {
80 compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc";
81 reg = <0x10300 0x20>;
82 interrupts = <53>;
83 clocks = <&gate_clk 7>;
84 };
85
86 sata@80000 {
87 compatible = "marvell,orion-sata";
88 reg = <0x80000 0x5000>;
89 interrupts = <21>;
90 clocks = <&gate_clk 14>, <&gate_clk 15>;
91 clock-names = "0", "1";
92 status = "disabled";
93 };
94
95 mvsdio@90000 {
96 compatible = "marvell,orion-sdio";
97 reg = <0x90000 0x200>;
98 interrupts = <28>;
99 clocks = <&gate_clk 4>;
100 bus-width = <4>;
101 cap-sdio-irq;
102 cap-sd-highspeed;
103 cap-mmc-highspeed;
104 status = "disabled";
105 };
106 };
107};