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authorOlof Johansson <olof@lixom.net>2013-04-03 02:06:48 -0400
committerOlof Johansson <olof@lixom.net>2013-04-03 02:06:57 -0400
commite382328a811fd6ffdb77ee16ff6a9e92e07561c5 (patch)
tree0f88d2b72d13842924570e1019e320e1e57d36b9
parent2f7053e0ecbe8908a130207bc01b7b3f9f854ef8 (diff)
parent202ac6a21a79500ef5aab4cd8665be2597e9345c (diff)
Merge tag 'renesas-pinmux2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc2
Second round of Renesas ARM and SH based SoC pinmux updates for v3.10 Highlights: * Compilation fixes for sh7269 and for when CONFIG_BUG is not set * sh-pfc Support for r8a73a4 SoC * Move GPIOs handling from the PFC device to separate GPIO devices on the r8a7779 SoC This pull request is based on a merge of: git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-pinmux-for-v3.10 git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas renesas-soc2-for-v3.10 * tag 'renesas-pinmux2-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (185 commits) sh-pfc: r8a73a4: Remove unused GPIO bias data ARM: shmobile: r8a73a4: Remove all GPIO enums sh-pfc: r8a73a4: Remove function GPIOs ARM: shmobile: r8a73a4: Remove IRQC function GPIOs ARM: shmobile: r8a73a4: Remove SCIF function GPIOs sh-pfc: r8a73a4: Remove IRQC function GPIOS sh-pfc: r8a73a4: Remove SCIF function GPIOS sh-pfc: r8a73a4: Add IRQC pin groups and functions sh-pfc: r8a73a4: Add SCIF pin groups and functions sh-pfc: r8a73a4: Add bias (pull-up/down) pinconf support sh-pfc: r8a73a4: GPIO IRQ support sh-pfc: r8a73a4: Support sparse GPIO numbers sh-pfc: Add r8a73a4 pinmux support sh-pfc: r8a7779: Split DU input and output pixel clocks sh-pfc: r8a7779: Remove GPIO data ARM: shmobile: r8a7779: Register GPIO devices sh-pfc: Configure pins as GPIOs at request time when handled externally sh-pfc: Skip gpiochip registration when no GPIO resource is found sh-pfc: Make GPIO support optional sh-pfc: Make function GPIOs support optional ... Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/gpio/gpio.txt6
-rw-r--r--Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt107
-rw-r--r--arch/arm/boot/dts/spear1310.dtsi4
-rw-r--r--arch/arm/boot/dts/spear1340.dtsi4
-rw-r--r--arch/arm/boot/dts/spear310.dtsi4
-rw-r--r--arch/arm/boot/dts/spear320.dtsi4
-rw-r--r--arch/arm/mach-shmobile/board-ag5evm.c172
-rw-r--r--arch/arm/mach-shmobile/board-ap4evb.c91
-rw-r--r--arch/arm/mach-shmobile/board-armadillo800eva.c160
-rw-r--r--arch/arm/mach-shmobile/board-bonito.c52
-rw-r--r--arch/arm/mach-shmobile/board-kota2.c208
-rw-r--r--arch/arm/mach-shmobile/board-kzm9g.c152
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c102
-rw-r--r--arch/arm/mach-shmobile/board-marzen.c107
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7740.h74
-rw-r--r--arch/arm/mach-shmobile/include/mach/r8a7779.h321
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh7372.h29
-rw-r--r--arch/arm/mach-shmobile/include/mach/sh73a0.h363
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7779.c58
-rw-r--r--arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c13
-rw-r--r--arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c13
-rw-r--r--arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c13
-rw-r--r--arch/sh/kernel/cpu/sh3/pinmux-sh7720.c14
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c14
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c14
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c13
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c13
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c14
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c14
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-shx3.c17
-rw-r--r--drivers/gpio/Kconfig6
-rw-r--r--drivers/gpio/Makefile1
-rw-r--r--drivers/gpio/gpio-pl061.c117
-rw-r--r--drivers/gpio/gpio-rcar.c396
-rw-r--r--drivers/gpio/gpiolib-of.c15
-rw-r--r--drivers/pinctrl/Kconfig1
-rw-r--r--drivers/pinctrl/core.c39
-rw-r--r--drivers/pinctrl/devicetree.c4
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-mvebu.c6
-rw-r--r--drivers/pinctrl/pinconf-generic.c14
-rw-r--r--drivers/pinctrl/pinconf.c2
-rw-r--r--drivers/pinctrl/pinconf.h8
-rw-r--r--drivers/pinctrl/pinctrl-abx500.c7
-rw-r--r--drivers/pinctrl/pinctrl-at91.c6
-rw-r--r--drivers/pinctrl/pinctrl-bcm2835.c6
-rw-r--r--drivers/pinctrl/pinctrl-exynos5440.c6
-rw-r--r--drivers/pinctrl/pinctrl-falcon.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx.c6
-rw-r--r--drivers/pinctrl/pinctrl-lantiq.c4
-rw-r--r--drivers/pinctrl/pinctrl-mxs.c6
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c6
-rw-r--r--drivers/pinctrl/pinctrl-pxa3xx.c4
-rw-r--r--drivers/pinctrl/pinctrl-samsung.c6
-rw-r--r--drivers/pinctrl/pinctrl-single.c515
-rw-r--r--drivers/pinctrl/pinctrl-sirf.c4
-rw-r--r--drivers/pinctrl/pinctrl-sunxi.c978
-rw-r--r--drivers/pinctrl/pinctrl-tegra.c6
-rw-r--r--drivers/pinctrl/pinctrl-u300.c6
-rw-r--r--drivers/pinctrl/pinctrl-xway.c2
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig6
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile1
-rw-r--r--drivers/pinctrl/sh-pfc/core.c302
-rw-r--r--drivers/pinctrl/sh-pfc/core.h55
-rw-r--r--drivers/pinctrl/sh-pfc/gpio.c372
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a73a4.c2587
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c626
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7779.c1695
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7203.c488
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7264.c460
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7269.c624
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7372.c323
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c2656
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7720.c333
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7722.c480
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7723.c642
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7724.c638
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7734.c55
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7757.c620
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7785.c354
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7786.c296
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-shx3.c148
-rw-r--r--drivers/pinctrl/sh-pfc/pinctrl.c491
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h135
-rw-r--r--drivers/pinctrl/spear/pinctrl-spear.c4
-rw-r--r--include/linux/pinctrl/pinctrl.h6
-rw-r--r--include/linux/platform_data/gpio-rcar.h26
86 files changed, 12760 insertions, 6012 deletions
diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt
index a33628759d36..d933af370697 100644
--- a/Documentation/devicetree/bindings/gpio/gpio.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio.txt
@@ -98,7 +98,7 @@ announce the pinrange to the pin ctrl subsystem. For example,
98 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; 98 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
99 reg = <0x1460 0x18>; 99 reg = <0x1460 0x18>;
100 gpio-controller; 100 gpio-controller;
101 gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>; 101 gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
102 102
103 } 103 }
104 104
@@ -107,8 +107,8 @@ where,
107 107
108 Next values specify the base pin and number of pins for the range 108 Next values specify the base pin and number of pins for the range
109 handled by 'qe_pio_e' gpio. In the given example from base pin 20 to 109 handled by 'qe_pio_e' gpio. In the given example from base pin 20 to
110 pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled 110 pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under
111 by this gpio controller. 111 pinctrl2 with gpio offset 10 is handled by this gpio controller.
112 112
113The pinctrl node must have "#gpio-range-cells" property to show number of 113The pinctrl node must have "#gpio-range-cells" property to show number of
114arguments to pass with phandle from gpio controllers node. 114arguments to pass with phandle from gpio controllers node.
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
index 2c81e45f1374..fa1746b639b9 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
@@ -1,7 +1,9 @@
1One-register-per-pin type device tree based pinctrl driver 1One-register-per-pin type device tree based pinctrl driver
2 2
3Required properties: 3Required properties:
4- compatible : "pinctrl-single" 4- compatible : "pinctrl-single" or "pinconf-single".
5 "pinctrl-single" means that pinconf isn't supported.
6 "pinconf-single" means that generic pinconf is supported.
5 7
6- reg : offset and length of the register set for the mux registers 8- reg : offset and length of the register set for the mux registers
7 9
@@ -14,9 +16,61 @@ Optional properties:
14- pinctrl-single,function-off : function off mode for disabled state if 16- pinctrl-single,function-off : function off mode for disabled state if
15 available and same for all registers; if not specified, disabling of 17 available and same for all registers; if not specified, disabling of
16 pin functions is ignored 18 pin functions is ignored
19
17- pinctrl-single,bit-per-mux : boolean to indicate that one register controls 20- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
18 more than one pin 21 more than one pin
19 22
23- pinctrl-single,drive-strength : array of value that are used to configure
24 drive strength in the pinmux register. They're value of drive strength
25 current and drive strength mask.
26
27 /* drive strength current, mask */
28 pinctrl-single,power-source = <0x30 0xf0>;
29
30- pinctrl-single,bias-pullup : array of value that are used to configure the
31 input bias pullup in the pinmux register.
32
33 /* input, enabled pullup bits, disabled pullup bits, mask */
34 pinctrl-single,bias-pullup = <0 1 0 1>;
35
36- pinctrl-single,bias-pulldown : array of value that are used to configure the
37 input bias pulldown in the pinmux register.
38
39 /* input, enabled pulldown bits, disabled pulldown bits, mask */
40 pinctrl-single,bias-pulldown = <2 2 0 2>;
41
42 * Two bits to control input bias pullup and pulldown: User should use
43 pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
44 pullup, and the other one bit means pulldown.
45 * Three bits to control input bias enable, pullup and pulldown. User should
46 use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
47 enable bit should be included in pullup or pulldown bits.
48 * Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
49 pinctrl-single,bias-disable. Because pinctrl single driver could implement
50 it by calling pulldown, pullup disabled.
51
52- pinctrl-single,input-schmitt : array of value that are used to configure
53 input schmitt in the pinmux register. In some silicons, there're two input
54 schmitt value (rising-edge & falling-edge) in the pinmux register.
55
56 /* input schmitt value, mask */
57 pinctrl-single,input-schmitt = <0x30 0x70>;
58
59- pinctrl-single,input-schmitt-enable : array of value that are used to
60 configure input schmitt enable or disable in the pinmux register.
61
62 /* input, enable bits, disable bits, mask */
63 pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
64
65- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
66 range. They're value of subnode phandle, pin base in pinctrl device, pin
67 number in this range, GPIO function value of this GPIO range.
68 The number of parameters is depend on #pinctrl-single,gpio-range-cells
69 property.
70
71 /* pin base, nr pins & gpio function */
72 pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
73
20This driver assumes that there is only one register for each pin (unless the 74This driver assumes that there is only one register for each pin (unless the
21pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as 75pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
22specified in the pinctrl-bindings.txt document in this directory. 76specified in the pinctrl-bindings.txt document in this directory.
@@ -42,6 +96,20 @@ Where 0xdc is the offset from the pinctrl register base address for the
42device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to 96device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
43be used when applying this change to the register. 97be used when applying this change to the register.
44 98
99
100Optional sub-node: In case some pins could be configured as GPIO in the pinmux
101register, those pins could be defined as a GPIO range. This sub-node is required
102by pinctrl-single,gpio-range property.
103
104Required properties in sub-node:
105- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
106 pinctrl-single,gpio-range property.
107
108 range: gpio-range {
109 #pinctrl-single,gpio-range-cells = <3>;
110 };
111
112
45Example: 113Example:
46 114
47/* SoC common file */ 115/* SoC common file */
@@ -76,6 +144,29 @@ control_devconf0: pinmux@48002274 {
76 pinctrl-single,function-mask = <0x5F>; 144 pinctrl-single,function-mask = <0x5F>;
77}; 145};
78 146
147/* third controller instance for pins in gpio domain */
148pmx_gpio: pinmux@d401e000 {
149 compatible = "pinconf-single";
150 reg = <0xd401e000 0x0330>;
151 #address-cells = <1>;
152 #size-cells = <1>;
153 ranges;
154
155 pinctrl-single,register-width = <32>;
156 pinctrl-single,function-mask = <7>;
157
158 /* sparse GPIO range could be supported */
159 pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
160 &range 12 1 0 &range 13 29 1
161 &range 43 1 0 &range 44 49 1
162 &range 94 1 1 &range 96 2 1>;
163
164 range: gpio-range {
165 #pinctrl-single,gpio-range-cells = <3>;
166 };
167};
168
169
79/* board specific .dts file */ 170/* board specific .dts file */
80 171
81&pmx_core { 172&pmx_core {
@@ -96,6 +187,15 @@ control_devconf0: pinmux@48002274 {
96 >; 187 >;
97 }; 188 };
98 189
190 uart0_pins: pinmux_uart0_pins {
191 pinctrl-single,pins = <
192 0x208 0 /* UART0_RXD (IOCFG138) */
193 0x20c 0 /* UART0_TXD (IOCFG139) */
194 >;
195 pinctrl-single,bias-pulldown = <0 2 2>;
196 pinctrl-single,bias-pullup = <0 1 1>;
197 };
198
99 /* map uart2 pins */ 199 /* map uart2 pins */
100 uart2_pins: pinmux_uart2_pins { 200 uart2_pins: pinmux_uart2_pins {
101 pinctrl-single,pins = < 201 pinctrl-single,pins = <
@@ -122,6 +222,11 @@ control_devconf0: pinmux@48002274 {
122 222
123}; 223};
124 224
225&uart1 {
226 pinctrl-names = "default";
227 pinctrl-0 = <&uart0_pins>;
228};
229
125&uart2 { 230&uart2 {
126 pinctrl-names = "default"; 231 pinctrl-names = "default";
127 pinctrl-0 = <&uart2_pins>; 232 pinctrl-0 = <&uart2_pins>;
diff --git a/arch/arm/boot/dts/spear1310.dtsi b/arch/arm/boot/dts/spear1310.dtsi
index 1513c1927cc8..122ae94076c8 100644
--- a/arch/arm/boot/dts/spear1310.dtsi
+++ b/arch/arm/boot/dts/spear1310.dtsi
@@ -89,7 +89,7 @@
89 pinmux: pinmux@e0700000 { 89 pinmux: pinmux@e0700000 {
90 compatible = "st,spear1310-pinmux"; 90 compatible = "st,spear1310-pinmux";
91 reg = <0xe0700000 0x1000>; 91 reg = <0xe0700000 0x1000>;
92 #gpio-range-cells = <2>; 92 #gpio-range-cells = <3>;
93 }; 93 };
94 94
95 apb { 95 apb {
@@ -212,7 +212,7 @@
212 interrupt-controller; 212 interrupt-controller;
213 gpio-controller; 213 gpio-controller;
214 #gpio-cells = <2>; 214 #gpio-cells = <2>;
215 gpio-ranges = <&pinmux 0 246>; 215 gpio-ranges = <&pinmux 0 0 246>;
216 status = "disabled"; 216 status = "disabled";
217 217
218 st-plgpio,ngpio = <246>; 218 st-plgpio,ngpio = <246>;
diff --git a/arch/arm/boot/dts/spear1340.dtsi b/arch/arm/boot/dts/spear1340.dtsi
index 34da11aa6795..c511c4772efd 100644
--- a/arch/arm/boot/dts/spear1340.dtsi
+++ b/arch/arm/boot/dts/spear1340.dtsi
@@ -63,7 +63,7 @@
63 pinmux: pinmux@e0700000 { 63 pinmux: pinmux@e0700000 {
64 compatible = "st,spear1340-pinmux"; 64 compatible = "st,spear1340-pinmux";
65 reg = <0xe0700000 0x1000>; 65 reg = <0xe0700000 0x1000>;
66 #gpio-range-cells = <2>; 66 #gpio-range-cells = <3>;
67 }; 67 };
68 68
69 pwm: pwm@e0180000 { 69 pwm: pwm@e0180000 {
@@ -127,7 +127,7 @@
127 interrupt-controller; 127 interrupt-controller;
128 gpio-controller; 128 gpio-controller;
129 #gpio-cells = <2>; 129 #gpio-cells = <2>;
130 gpio-ranges = <&pinmux 0 252>; 130 gpio-ranges = <&pinmux 0 0 252>;
131 status = "disabled"; 131 status = "disabled";
132 132
133 st-plgpio,ngpio = <250>; 133 st-plgpio,ngpio = <250>;
diff --git a/arch/arm/boot/dts/spear310.dtsi b/arch/arm/boot/dts/spear310.dtsi
index ab45b8c81982..95372080eea6 100644
--- a/arch/arm/boot/dts/spear310.dtsi
+++ b/arch/arm/boot/dts/spear310.dtsi
@@ -25,7 +25,7 @@
25 pinmux: pinmux@b4000000 { 25 pinmux: pinmux@b4000000 {
26 compatible = "st,spear310-pinmux"; 26 compatible = "st,spear310-pinmux";
27 reg = <0xb4000000 0x1000>; 27 reg = <0xb4000000 0x1000>;
28 #gpio-range-cells = <2>; 28 #gpio-range-cells = <3>;
29 }; 29 };
30 30
31 fsmc: flash@44000000 { 31 fsmc: flash@44000000 {
@@ -102,7 +102,7 @@
102 interrupt-controller; 102 interrupt-controller;
103 gpio-controller; 103 gpio-controller;
104 #gpio-cells = <2>; 104 #gpio-cells = <2>;
105 gpio-ranges = <&pinmux 0 102>; 105 gpio-ranges = <&pinmux 0 0 102>;
106 status = "disabled"; 106 status = "disabled";
107 107
108 st-plgpio,ngpio = <102>; 108 st-plgpio,ngpio = <102>;
diff --git a/arch/arm/boot/dts/spear320.dtsi b/arch/arm/boot/dts/spear320.dtsi
index caa5520b1fd4..ffea342aeec9 100644
--- a/arch/arm/boot/dts/spear320.dtsi
+++ b/arch/arm/boot/dts/spear320.dtsi
@@ -24,7 +24,7 @@
24 pinmux: pinmux@b3000000 { 24 pinmux: pinmux@b3000000 {
25 compatible = "st,spear320-pinmux"; 25 compatible = "st,spear320-pinmux";
26 reg = <0xb3000000 0x1000>; 26 reg = <0xb3000000 0x1000>;
27 #gpio-range-cells = <2>; 27 #gpio-range-cells = <3>;
28 }; 28 };
29 29
30 clcd@90000000 { 30 clcd@90000000 {
@@ -130,7 +130,7 @@
130 interrupt-controller; 130 interrupt-controller;
131 gpio-controller; 131 gpio-controller;
132 #gpio-cells = <2>; 132 #gpio-cells = <2>;
133 gpio-ranges = <&pinmux 0 102>; 133 gpio-ranges = <&pinmux 0 0 102>;
134 status = "disabled"; 134 status = "disabled";
135 135
136 st-plgpio,ngpio = <102>; 136 st-plgpio,ngpio = <102>;
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 8ff53a19c48c..c7540710906f 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -23,6 +23,8 @@
23#include <linux/init.h> 23#include <linux/init.h>
24#include <linux/interrupt.h> 24#include <linux/interrupt.h>
25#include <linux/irq.h> 25#include <linux/irq.h>
26#include <linux/pinctrl/machine.h>
27#include <linux/pinctrl/pinconf-generic.h>
26#include <linux/platform_device.h> 28#include <linux/platform_device.h>
27#include <linux/delay.h> 29#include <linux/delay.h>
28#include <linux/io.h> 30#include <linux/io.h>
@@ -304,9 +306,9 @@ static int lcd_backlight_set_brightness(int brightness)
304 306
305 if (brightness == 0) { 307 if (brightness == 0) {
306 /* Reset the chip */ 308 /* Reset the chip */
307 gpio_set_value(GPIO_PORT235, 0); 309 gpio_set_value(235, 0);
308 mdelay(24); 310 mdelay(24);
309 gpio_set_value(GPIO_PORT235, 1); 311 gpio_set_value(235, 1);
310 return 0; 312 return 0;
311 } 313 }
312 314
@@ -406,7 +408,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
406 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD, 408 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
407 .tmio_caps = MMC_CAP_SD_HIGHSPEED, 409 .tmio_caps = MMC_CAP_SD_HIGHSPEED,
408 .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, 410 .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
409 .cd_gpio = GPIO_PORT251, 411 .cd_gpio = 251,
410}; 412};
411 413
412static struct resource sdhi0_resources[] = { 414static struct resource sdhi0_resources[] = {
@@ -461,7 +463,7 @@ static struct regulator_init_data cn4_power_init_data = {
461static struct fixed_voltage_config cn4_power_info = { 463static struct fixed_voltage_config cn4_power_info = {
462 .supply_name = "CN4 SD/MMC Vdd", 464 .supply_name = "CN4 SD/MMC Vdd",
463 .microvolts = 3300000, 465 .microvolts = 3300000,
464 .gpio = GPIO_PORT114, 466 .gpio = 114,
465 .enable_high = 1, 467 .enable_high = 1,
466 .init_data = &cn4_power_init_data, 468 .init_data = &cn4_power_init_data,
467}; 469};
@@ -479,10 +481,10 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
479 static int power_gpio = -EINVAL; 481 static int power_gpio = -EINVAL;
480 482
481 if (power_gpio < 0) { 483 if (power_gpio < 0) {
482 int ret = gpio_request_one(GPIO_PORT114, GPIOF_OUT_INIT_LOW, 484 int ret = gpio_request_one(114, GPIOF_OUT_INIT_LOW,
483 "sdhi1_power"); 485 "sdhi1_power");
484 if (!ret) 486 if (!ret)
485 power_gpio = GPIO_PORT114; 487 power_gpio = 114;
486 } 488 }
487 489
488 /* 490 /*
@@ -493,7 +495,7 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
493 * regulator driver. We have to live with the race in case the driver 495 * regulator driver. We have to live with the race in case the driver
494 * gets unloaded and the GPIO freed between these two steps. 496 * gets unloaded and the GPIO freed between these two steps.
495 */ 497 */
496 gpio_set_value(GPIO_PORT114, state); 498 gpio_set_value(114, state);
497} 499}
498 500
499static struct sh_mobile_sdhi_info sh_sdhi1_info = { 501static struct sh_mobile_sdhi_info sh_sdhi1_info = {
@@ -550,6 +552,77 @@ static struct platform_device *ag5evm_devices[] __initdata = {
550 &sdhi1_device, 552 &sdhi1_device,
551}; 553};
552 554
555static unsigned long pin_pullup_conf[] = {
556 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
557};
558
559static const struct pinctrl_map ag5evm_pinctrl_map[] = {
560 /* FSIA */
561 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
562 "fsia_mclk_in", "fsia"),
563 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
564 "fsia_sclk_in", "fsia"),
565 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
566 "fsia_data_in", "fsia"),
567 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
568 "fsia_data_out", "fsia"),
569 /* I2C2 & I2C3 */
570 PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.2", "pfc-sh73a0",
571 "i2c2_0", "i2c2"),
572 PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
573 "i2c3_0", "i2c3"),
574 /* IrDA */
575 PIN_MAP_MUX_GROUP_DEFAULT("sh_irda.0", "pfc-sh73a0",
576 "irda_0", "irda"),
577 /* KEYSC */
578 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
579 "keysc_in8", "keysc"),
580 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
581 "keysc_out04", "keysc"),
582 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
583 "keysc_out5", "keysc"),
584 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
585 "keysc_out6_0", "keysc"),
586 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
587 "keysc_out7_0", "keysc"),
588 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
589 "keysc_out8_0", "keysc"),
590 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
591 "keysc_out9_2", "keysc"),
592 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
593 "keysc_in8", pin_pullup_conf),
594 /* MMCIF */
595 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
596 "mmc0_data8_0", "mmc0"),
597 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
598 "mmc0_ctrl_0", "mmc0"),
599 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
600 "PORT279", pin_pullup_conf),
601 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
602 "mmc0_data8_0", pin_pullup_conf),
603 /* SCIFA2 */
604 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
605 "scifa2_data_0", "scifa2"),
606 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
607 "scifa2_ctrl_0", "scifa2"),
608 /* SDHI0 (CN15 [SD I/F]) */
609 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
610 "sdhi0_data4", "sdhi0"),
611 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
612 "sdhi0_ctrl", "sdhi0"),
613 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
614 "sdhi0_wp", "sdhi0"),
615 /* SDHI1 (CN4 [WLAN I/F]) */
616 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
617 "sdhi1_data4", "sdhi1"),
618 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
619 "sdhi1_ctrl", "sdhi1"),
620 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
621 "sdhi1_data4", pin_pullup_conf),
622 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
623 "PORT263", pin_pullup_conf),
624};
625
553static void __init ag5evm_init(void) 626static void __init ag5evm_init(void)
554{ 627{
555 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers, 628 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
@@ -558,96 +631,27 @@ static void __init ag5evm_init(void)
558 ARRAY_SIZE(fixed2v8_power_consumers), 3300000); 631 ARRAY_SIZE(fixed2v8_power_consumers), 3300000);
559 regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies)); 632 regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
560 633
634 pinctrl_register_mappings(ag5evm_pinctrl_map,
635 ARRAY_SIZE(ag5evm_pinctrl_map));
561 sh73a0_pinmux_init(); 636 sh73a0_pinmux_init();
562 637
563 /* enable SCIFA2 */
564 gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
565 gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
566 gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
567 gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
568
569 /* enable KEYSC */
570 gpio_request(GPIO_FN_KEYIN0_PU, NULL);
571 gpio_request(GPIO_FN_KEYIN1_PU, NULL);
572 gpio_request(GPIO_FN_KEYIN2_PU, NULL);
573 gpio_request(GPIO_FN_KEYIN3_PU, NULL);
574 gpio_request(GPIO_FN_KEYIN4_PU, NULL);
575 gpio_request(GPIO_FN_KEYIN5_PU, NULL);
576 gpio_request(GPIO_FN_KEYIN6_PU, NULL);
577 gpio_request(GPIO_FN_KEYIN7_PU, NULL);
578 gpio_request(GPIO_FN_KEYOUT0, NULL);
579 gpio_request(GPIO_FN_KEYOUT1, NULL);
580 gpio_request(GPIO_FN_KEYOUT2, NULL);
581 gpio_request(GPIO_FN_KEYOUT3, NULL);
582 gpio_request(GPIO_FN_KEYOUT4, NULL);
583 gpio_request(GPIO_FN_KEYOUT5, NULL);
584 gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
585 gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
586 gpio_request(GPIO_FN_KEYOUT8, NULL);
587 gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL);
588
589 /* enable I2C channel 2 and 3 */
590 gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
591 gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
592 gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL);
593 gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL);
594
595 /* enable MMCIF */ 638 /* enable MMCIF */
596 gpio_request(GPIO_FN_MMCCLK0, NULL); 639 gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
597 gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
598 gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
599 gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
600 gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
601 gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
602 gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
603 gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
604 gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
605 gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
606 gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
607 640
608 /* enable SMSC911X */ 641 /* enable SMSC911X */
609 gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */ 642 gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
610 gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */ 643 gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
611
612 /* FSI A */
613 gpio_request(GPIO_FN_FSIACK, NULL);
614 gpio_request(GPIO_FN_FSIAILR, NULL);
615 gpio_request(GPIO_FN_FSIAIBT, NULL);
616 gpio_request(GPIO_FN_FSIAISLD, NULL);
617 gpio_request(GPIO_FN_FSIAOSLD, NULL);
618
619 /* IrDA */
620 gpio_request(GPIO_FN_PORT241_IRDA_OUT, NULL);
621 gpio_request(GPIO_FN_PORT242_IRDA_IN, NULL);
622 gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL);
623 644
624 /* LCD panel */ 645 /* LCD panel */
625 gpio_request_one(GPIO_PORT217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */ 646 gpio_request_one(217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
626 mdelay(1); 647 mdelay(1);
627 gpio_set_value(GPIO_PORT217, 1); 648 gpio_set_value(217, 1);
628 mdelay(100); 649 mdelay(100);
629 650
630 /* LCD backlight controller */ 651 /* LCD backlight controller */
631 gpio_request_one(GPIO_PORT235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */ 652 gpio_request_one(235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
632 lcd_backlight_set_brightness(0); 653 lcd_backlight_set_brightness(0);
633 654
634 /* enable SDHI0 on CN15 [SD I/F] */
635 gpio_request(GPIO_FN_SDHIWP0, NULL);
636 gpio_request(GPIO_FN_SDHICMD0, NULL);
637 gpio_request(GPIO_FN_SDHICLK0, NULL);
638 gpio_request(GPIO_FN_SDHID0_3, NULL);
639 gpio_request(GPIO_FN_SDHID0_2, NULL);
640 gpio_request(GPIO_FN_SDHID0_1, NULL);
641 gpio_request(GPIO_FN_SDHID0_0, NULL);
642
643 /* enable SDHI1 on CN4 [WLAN I/F] */
644 gpio_request(GPIO_FN_SDHICLK1, NULL);
645 gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
646 gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
647 gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
648 gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
649 gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
650
651#ifdef CONFIG_CACHE_L2X0 655#ifdef CONFIG_CACHE_L2X0
652 /* Shared attribute override enable, 64K*8way */ 656 /* Shared attribute override enable, 64K*8way */
653 l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff); 657 l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 38f1259a0daf..45f78cadec1d 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -34,6 +34,7 @@
34#include <linux/i2c.h> 34#include <linux/i2c.h>
35#include <linux/i2c/tsc2007.h> 35#include <linux/i2c/tsc2007.h>
36#include <linux/io.h> 36#include <linux/io.h>
37#include <linux/pinctrl/machine.h>
37#include <linux/regulator/fixed.h> 38#include <linux/regulator/fixed.h>
38#include <linux/regulator/machine.h> 39#include <linux/regulator/machine.h>
39#include <linux/smsc911x.h> 40#include <linux/smsc911x.h>
@@ -273,11 +274,11 @@ static struct platform_device smc911x_device = {
273 274
274/* 275/*
275 * The card detect pin of the top SD/MMC slot (CN7) is active low and is 276 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
276 * connected to GPIO A22 of SH7372 (GPIO_PORT41). 277 * connected to GPIO A22 of SH7372 (GPIO 41).
277 */ 278 */
278static int slot_cn7_get_cd(struct platform_device *pdev) 279static int slot_cn7_get_cd(struct platform_device *pdev)
279{ 280{
280 return !gpio_get_value(GPIO_PORT41); 281 return !gpio_get_value(41);
281} 282}
282/* MERAM */ 283/* MERAM */
283static struct sh_mobile_meram_info meram_info = { 284static struct sh_mobile_meram_info meram_info = {
@@ -838,22 +839,22 @@ static struct platform_device fsi_hdmi_device = {
838static struct gpio_led ap4evb_leds[] = { 839static struct gpio_led ap4evb_leds[] = {
839 { 840 {
840 .name = "led4", 841 .name = "led4",
841 .gpio = GPIO_PORT185, 842 .gpio = 185,
842 .default_state = LEDS_GPIO_DEFSTATE_ON, 843 .default_state = LEDS_GPIO_DEFSTATE_ON,
843 }, 844 },
844 { 845 {
845 .name = "led2", 846 .name = "led2",
846 .gpio = GPIO_PORT186, 847 .gpio = 186,
847 .default_state = LEDS_GPIO_DEFSTATE_ON, 848 .default_state = LEDS_GPIO_DEFSTATE_ON,
848 }, 849 },
849 { 850 {
850 .name = "led3", 851 .name = "led3",
851 .gpio = GPIO_PORT187, 852 .gpio = 187,
852 .default_state = LEDS_GPIO_DEFSTATE_ON, 853 .default_state = LEDS_GPIO_DEFSTATE_ON,
853 }, 854 },
854 { 855 {
855 .name = "led1", 856 .name = "led1",
856 .gpio = GPIO_PORT188, 857 .gpio = 188,
857 .default_state = LEDS_GPIO_DEFSTATE_ON, 858 .default_state = LEDS_GPIO_DEFSTATE_ON,
858 } 859 }
859}; 860};
@@ -1026,10 +1027,10 @@ out:
1026/* TouchScreen */ 1027/* TouchScreen */
1027#ifdef CONFIG_AP4EVB_QHD 1028#ifdef CONFIG_AP4EVB_QHD
1028# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123 1029# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
1029# define GPIO_TSC_PORT GPIO_PORT123 1030# define GPIO_TSC_PORT 123
1030#else /* WVGA */ 1031#else /* WVGA */
1031# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40 1032# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
1032# define GPIO_TSC_PORT GPIO_PORT40 1033# define GPIO_TSC_PORT 40
1033#endif 1034#endif
1034 1035
1035#define IRQ28 evt2irq(0x3380) /* IRQ28A */ 1036#define IRQ28 evt2irq(0x3380) /* IRQ28A */
@@ -1084,6 +1085,28 @@ static struct i2c_board_info i2c1_devices[] = {
1084}; 1085};
1085 1086
1086 1087
1088static const struct pinctrl_map ap4evb_pinctrl_map[] = {
1089 /* MMCIF */
1090 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1091 "mmc0_data8_0", "mmc0"),
1092 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1093 "mmc0_ctrl_0", "mmc0"),
1094 /* SDHI0 */
1095 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1096 "sdhi0_data4", "sdhi0"),
1097 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1098 "sdhi0_ctrl", "sdhi0"),
1099 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1100 "sdhi0_cd", "sdhi0"),
1101 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1102 "sdhi0_wp", "sdhi0"),
1103 /* SDHI1 */
1104 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
1105 "sdhi1_data4", "sdhi1"),
1106 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
1107 "sdhi1_ctrl", "sdhi1"),
1108};
1109
1087#define GPIO_PORT9CR IOMEM(0xE6051009) 1110#define GPIO_PORT9CR IOMEM(0xE6051009)
1088#define GPIO_PORT10CR IOMEM(0xE605100A) 1111#define GPIO_PORT10CR IOMEM(0xE605100A)
1089#define USCCR1 IOMEM(0xE6058144) 1112#define USCCR1 IOMEM(0xE6058144)
@@ -1110,6 +1133,8 @@ static void __init ap4evb_init(void)
1110 /* External clock source */ 1133 /* External clock source */
1111 clk_set_rate(&sh7372_dv_clki_clk, 27000000); 1134 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
1112 1135
1136 pinctrl_register_mappings(ap4evb_pinctrl_map,
1137 ARRAY_SIZE(ap4evb_pinctrl_map));
1113 sh7372_pinmux_init(); 1138 sh7372_pinmux_init();
1114 1139
1115 /* enable SCIFA0 */ 1140 /* enable SCIFA0 */
@@ -1121,40 +1146,10 @@ static void __init ap4evb_init(void)
1121 gpio_request(GPIO_FN_IRQ6_39, NULL); 1146 gpio_request(GPIO_FN_IRQ6_39, NULL);
1122 1147
1123 /* enable Debug switch (S6) */ 1148 /* enable Debug switch (S6) */
1124 gpio_request_one(GPIO_PORT32, GPIOF_IN | GPIOF_EXPORT, NULL); 1149 gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
1125 gpio_request_one(GPIO_PORT33, GPIOF_IN | GPIOF_EXPORT, NULL); 1150 gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
1126 gpio_request_one(GPIO_PORT34, GPIOF_IN | GPIOF_EXPORT, NULL); 1151 gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
1127 gpio_request_one(GPIO_PORT35, GPIOF_IN | GPIOF_EXPORT, NULL); 1152 gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
1128
1129 /* SDHI0 */
1130 gpio_request(GPIO_FN_SDHICD0, NULL);
1131 gpio_request(GPIO_FN_SDHIWP0, NULL);
1132 gpio_request(GPIO_FN_SDHICMD0, NULL);
1133 gpio_request(GPIO_FN_SDHICLK0, NULL);
1134 gpio_request(GPIO_FN_SDHID0_3, NULL);
1135 gpio_request(GPIO_FN_SDHID0_2, NULL);
1136 gpio_request(GPIO_FN_SDHID0_1, NULL);
1137 gpio_request(GPIO_FN_SDHID0_0, NULL);
1138
1139 /* SDHI1 */
1140 gpio_request(GPIO_FN_SDHICMD1, NULL);
1141 gpio_request(GPIO_FN_SDHICLK1, NULL);
1142 gpio_request(GPIO_FN_SDHID1_3, NULL);
1143 gpio_request(GPIO_FN_SDHID1_2, NULL);
1144 gpio_request(GPIO_FN_SDHID1_1, NULL);
1145 gpio_request(GPIO_FN_SDHID1_0, NULL);
1146
1147 /* MMCIF */
1148 gpio_request(GPIO_FN_MMCD0_0, NULL);
1149 gpio_request(GPIO_FN_MMCD0_1, NULL);
1150 gpio_request(GPIO_FN_MMCD0_2, NULL);
1151 gpio_request(GPIO_FN_MMCD0_3, NULL);
1152 gpio_request(GPIO_FN_MMCD0_4, NULL);
1153 gpio_request(GPIO_FN_MMCD0_5, NULL);
1154 gpio_request(GPIO_FN_MMCD0_6, NULL);
1155 gpio_request(GPIO_FN_MMCD0_7, NULL);
1156 gpio_request(GPIO_FN_MMCCMD0, NULL);
1157 gpio_request(GPIO_FN_MMCCLK0, NULL);
1158 1153
1159 /* USB enable */ 1154 /* USB enable */
1160 gpio_request(GPIO_FN_VBUS0_1, NULL); 1155 gpio_request(GPIO_FN_VBUS0_1, NULL);
@@ -1172,15 +1167,15 @@ static void __init ap4evb_init(void)
1172 gpio_request(GPIO_FN_FSIAILR, NULL); 1167 gpio_request(GPIO_FN_FSIAILR, NULL);
1173 gpio_request(GPIO_FN_FSIAISLD, NULL); 1168 gpio_request(GPIO_FN_FSIAISLD, NULL);
1174 gpio_request(GPIO_FN_FSIAOSLD, NULL); 1169 gpio_request(GPIO_FN_FSIAOSLD, NULL);
1175 gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ 1170 gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
1176 1171
1177 gpio_request(GPIO_PORT9, NULL); 1172 gpio_request(9, NULL);
1178 gpio_request(GPIO_PORT10, NULL); 1173 gpio_request(10, NULL);
1179 gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */ 1174 gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
1180 gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */ 1175 gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
1181 1176
1182 /* card detect pin for MMC slot (CN7) */ 1177 /* card detect pin for MMC slot (CN7) */
1183 gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL); 1178 gpio_request_one(41, GPIOF_IN, NULL);
1184 1179
1185 /* setup FSI2 port B (HDMI) */ 1180 /* setup FSI2 port B (HDMI) */
1186 gpio_request(GPIO_FN_FSIBCK, NULL); 1181 gpio_request(GPIO_FN_FSIBCK, NULL);
@@ -1268,8 +1263,8 @@ static void __init ap4evb_init(void)
1268 gpio_request(GPIO_FN_LCDDISP, NULL); 1263 gpio_request(GPIO_FN_LCDDISP, NULL);
1269 gpio_request(GPIO_FN_LCDDCK, NULL); 1264 gpio_request(GPIO_FN_LCDDCK, NULL);
1270 1265
1271 gpio_request_one(GPIO_PORT189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */ 1266 gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
1272 gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ 1267 gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
1273 1268
1274 lcdc_info.clock_source = LCDC_CLK_BUS; 1269 lcdc_info.clock_source = LCDC_CLK_BUS;
1275 lcdc_info.ch[0].interface_type = RGB18; 1270 lcdc_info.ch[0].interface_type = RGB18;
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c
index e451327278af..9415cb4e6199 100644
--- a/arch/arm/mach-shmobile/board-armadillo800eva.c
+++ b/arch/arm/mach-shmobile/board-armadillo800eva.c
@@ -28,6 +28,7 @@
28#include <linux/platform_device.h> 28#include <linux/platform_device.h>
29#include <linux/gpio.h> 29#include <linux/gpio.h>
30#include <linux/gpio_keys.h> 30#include <linux/gpio_keys.h>
31#include <linux/pinctrl/machine.h>
31#include <linux/regulator/fixed.h> 32#include <linux/regulator/fixed.h>
32#include <linux/regulator/machine.h> 33#include <linux/regulator/machine.h>
33#include <linux/sh_eth.h> 34#include <linux/sh_eth.h>
@@ -227,7 +228,7 @@ static void usbhsf_power_ctrl(struct platform_device *pdev,
227 228
228static int usbhsf_get_vbus(struct platform_device *pdev) 229static int usbhsf_get_vbus(struct platform_device *pdev)
229{ 230{
230 return gpio_get_value(GPIO_PORT209); 231 return gpio_get_value(209);
231} 232}
232 233
233static irqreturn_t usbhsf_interrupt(int irq, void *data) 234static irqreturn_t usbhsf_interrupt(int irq, void *data)
@@ -535,10 +536,10 @@ static struct platform_device hdmi_lcdc_device = {
535 { .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ } 536 { .code = c, .gpio = g, .desc = d, .active_low = 1, __VA_ARGS__ }
536 537
537static struct gpio_keys_button gpio_buttons[] = { 538static struct gpio_keys_button gpio_buttons[] = {
538 GPIO_KEY(KEY_POWER, GPIO_PORT99, "SW3", .wakeup = 1), 539 GPIO_KEY(KEY_POWER, 99, "SW3", .wakeup = 1),
539 GPIO_KEY(KEY_BACK, GPIO_PORT100, "SW4"), 540 GPIO_KEY(KEY_BACK, 100, "SW4"),
540 GPIO_KEY(KEY_MENU, GPIO_PORT97, "SW5"), 541 GPIO_KEY(KEY_MENU, 97, "SW5"),
541 GPIO_KEY(KEY_HOME, GPIO_PORT98, "SW6"), 542 GPIO_KEY(KEY_HOME, 98, "SW6"),
542}; 543};
543 544
544static struct gpio_keys_platform_data gpio_key_info = { 545static struct gpio_keys_platform_data gpio_key_info = {
@@ -656,6 +657,17 @@ static struct platform_device sdhi1_device = {
656 .resource = sdhi1_resources, 657 .resource = sdhi1_resources,
657}; 658};
658 659
660static const struct pinctrl_map eva_sdhi1_pinctrl_map[] = {
661 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
662 "sdhi1_data4", "sdhi1"),
663 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
664 "sdhi1_ctrl", "sdhi1"),
665 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
666 "sdhi1_cd", "sdhi1"),
667 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-r8a7740",
668 "sdhi1_wp", "sdhi1"),
669};
670
659/* MMCIF */ 671/* MMCIF */
660static struct sh_mmcif_plat_data sh_mmcif_plat = { 672static struct sh_mmcif_plat_data sh_mmcif_plat = {
661 .sup_pclk = 0, 673 .sup_pclk = 0,
@@ -708,9 +720,9 @@ static int mt9t111_power(struct device *dev, int mode)
708 /* video1 (= CON1 camera) expect 24MHz */ 720 /* video1 (= CON1 camera) expect 24MHz */
709 clk_set_rate(mclk, clk_round_rate(mclk, 24000000)); 721 clk_set_rate(mclk, clk_round_rate(mclk, 24000000));
710 clk_enable(mclk); 722 clk_enable(mclk);
711 gpio_set_value(GPIO_PORT158, 1); 723 gpio_set_value(158, 1);
712 } else { 724 } else {
713 gpio_set_value(GPIO_PORT158, 0); 725 gpio_set_value(158, 0);
714 clk_disable(mclk); 726 clk_disable(mclk);
715 } 727 }
716 728
@@ -864,8 +876,8 @@ static struct platform_device fsi_hdmi_device = {
864 876
865/* RTC: RTC connects i2c-gpio. */ 877/* RTC: RTC connects i2c-gpio. */
866static struct i2c_gpio_platform_data i2c_gpio_data = { 878static struct i2c_gpio_platform_data i2c_gpio_data = {
867 .sda_pin = GPIO_PORT208, 879 .sda_pin = 208,
868 .scl_pin = GPIO_PORT91, 880 .scl_pin = 91,
869 .udelay = 5, /* 100 kHz */ 881 .udelay = 5, /* 100 kHz */
870}; 882};
871 883
@@ -914,6 +926,28 @@ static struct platform_device *eva_devices[] __initdata = {
914 &i2c_gpio_device, 926 &i2c_gpio_device,
915}; 927};
916 928
929static const struct pinctrl_map eva_pinctrl_map[] = {
930 /* LCD0 */
931 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
932 "lcd0_data24_0", "lcd0"),
933 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
934 "lcd0_lclk_1", "lcd0"),
935 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
936 "lcd0_sync", "lcd0"),
937 /* MMCIF */
938 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
939 "mmc0_data8_1", "mmc0"),
940 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-r8a7740",
941 "mmc0_ctrl_1", "mmc0"),
942 /* SDHI0 */
943 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
944 "sdhi0_data4", "sdhi0"),
945 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
946 "sdhi0_ctrl", "sdhi0"),
947 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7740",
948 "sdhi0_wp", "sdhi0"),
949};
950
917static void __init eva_clock_init(void) 951static void __init eva_clock_init(void)
918{ 952{
919 struct clk *system = clk_get(NULL, "system_clk"); 953 struct clk *system = clk_get(NULL, "system_clk");
@@ -961,6 +995,8 @@ static void __init eva_init(void)
961 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, 995 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
962 ARRAY_SIZE(fixed3v3_power_consumers), 3300000); 996 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
963 997
998 pinctrl_register_mappings(eva_pinctrl_map, ARRAY_SIZE(eva_pinctrl_map));
999
964 r8a7740_pinmux_init(); 1000 r8a7740_pinmux_init();
965 r8a7740_meram_workaround(); 1001 r8a7740_meram_workaround();
966 1002
@@ -970,42 +1006,13 @@ static void __init eva_init(void)
970 1006
971 /* LCDC0 */ 1007 /* LCDC0 */
972 gpio_request(GPIO_FN_LCDC0_SELECT, NULL); 1008 gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
973 gpio_request(GPIO_FN_LCD0_D0, NULL); 1009
974 gpio_request(GPIO_FN_LCD0_D1, NULL); 1010 gpio_request_one(61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
975 gpio_request(GPIO_FN_LCD0_D2, NULL); 1011 gpio_request_one(202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
976 gpio_request(GPIO_FN_LCD0_D3, NULL);
977 gpio_request(GPIO_FN_LCD0_D4, NULL);
978 gpio_request(GPIO_FN_LCD0_D5, NULL);
979 gpio_request(GPIO_FN_LCD0_D6, NULL);
980 gpio_request(GPIO_FN_LCD0_D7, NULL);
981 gpio_request(GPIO_FN_LCD0_D8, NULL);
982 gpio_request(GPIO_FN_LCD0_D9, NULL);
983 gpio_request(GPIO_FN_LCD0_D10, NULL);
984 gpio_request(GPIO_FN_LCD0_D11, NULL);
985 gpio_request(GPIO_FN_LCD0_D12, NULL);
986 gpio_request(GPIO_FN_LCD0_D13, NULL);
987 gpio_request(GPIO_FN_LCD0_D14, NULL);
988 gpio_request(GPIO_FN_LCD0_D15, NULL);
989 gpio_request(GPIO_FN_LCD0_D16, NULL);
990 gpio_request(GPIO_FN_LCD0_D17, NULL);
991 gpio_request(GPIO_FN_LCD0_D18_PORT40, NULL);
992 gpio_request(GPIO_FN_LCD0_D19_PORT4, NULL);
993 gpio_request(GPIO_FN_LCD0_D20_PORT3, NULL);
994 gpio_request(GPIO_FN_LCD0_D21_PORT2, NULL);
995 gpio_request(GPIO_FN_LCD0_D22_PORT0, NULL);
996 gpio_request(GPIO_FN_LCD0_D23_PORT1, NULL);
997 gpio_request(GPIO_FN_LCD0_DCK, NULL);
998 gpio_request(GPIO_FN_LCD0_VSYN, NULL);
999 gpio_request(GPIO_FN_LCD0_HSYN, NULL);
1000 gpio_request(GPIO_FN_LCD0_DISP, NULL);
1001 gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
1002
1003 gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
1004 gpio_request_one(GPIO_PORT202, GPIOF_OUT_INIT_LOW, NULL); /* LCD0_LED_CONT */
1005 1012
1006 /* Touchscreen */ 1013 /* Touchscreen */
1007 gpio_request(GPIO_FN_IRQ10, NULL); /* TP_INT */ 1014 gpio_request(GPIO_FN_IRQ10, NULL); /* TP_INT */
1008 gpio_request_one(GPIO_PORT166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */ 1015 gpio_request_one(166, GPIOF_OUT_INIT_HIGH, NULL); /* TP_RST_B */
1009 1016
1010 /* GETHER */ 1017 /* GETHER */
1011 gpio_request(GPIO_FN_ET_CRS, NULL); 1018 gpio_request(GPIO_FN_ET_CRS, NULL);
@@ -1028,12 +1035,12 @@ static void __init eva_init(void)
1028 gpio_request(GPIO_FN_ET_RX_DV, NULL); 1035 gpio_request(GPIO_FN_ET_RX_DV, NULL);
1029 gpio_request(GPIO_FN_ET_RX_CLK, NULL); 1036 gpio_request(GPIO_FN_ET_RX_CLK, NULL);
1030 1037
1031 gpio_request_one(GPIO_PORT18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */ 1038 gpio_request_one(18, GPIOF_OUT_INIT_HIGH, NULL); /* PHY_RST */
1032 1039
1033 /* USB */ 1040 /* USB */
1034 gpio_request_one(GPIO_PORT159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */ 1041 gpio_request_one(159, GPIOF_IN, NULL); /* USB_DEVICE_MODE */
1035 1042
1036 if (gpio_get_value(GPIO_PORT159)) { 1043 if (gpio_get_value(159)) {
1037 /* USB Host */ 1044 /* USB Host */
1038 } else { 1045 } else {
1039 /* USB Func */ 1046 /* USB Func */
@@ -1042,47 +1049,22 @@ static void __init eva_init(void)
1042 * OTOH, usbhs interrupt needs its value (HI/LOW) to decide 1049 * OTOH, usbhs interrupt needs its value (HI/LOW) to decide
1043 * USB connection/disconnection (usbhsf_get_vbus()). 1050 * USB connection/disconnection (usbhsf_get_vbus()).
1044 * This means we needs to select GPIO_FN_IRQ7_PORT209 first, 1051 * This means we needs to select GPIO_FN_IRQ7_PORT209 first,
1045 * and select GPIO_PORT209 here 1052 * and select GPIO 209 here
1046 */ 1053 */
1047 gpio_request(GPIO_FN_IRQ7_PORT209, NULL); 1054 gpio_request(GPIO_FN_IRQ7_PORT209, NULL);
1048 gpio_request_one(GPIO_PORT209, GPIOF_IN, NULL); 1055 gpio_request_one(209, GPIOF_IN, NULL);
1049 1056
1050 platform_device_register(&usbhsf_device); 1057 platform_device_register(&usbhsf_device);
1051 usb = &usbhsf_device; 1058 usb = &usbhsf_device;
1052 } 1059 }
1053 1060
1054 /* SDHI0 */ 1061 /* SDHI0 */
1055 gpio_request(GPIO_FN_SDHI0_CMD, NULL); 1062 gpio_request_one(17, GPIOF_OUT_INIT_LOW, NULL); /* SDHI0_18/33_B */
1056 gpio_request(GPIO_FN_SDHI0_CLK, NULL); 1063 gpio_request_one(74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */
1057 gpio_request(GPIO_FN_SDHI0_D0, NULL); 1064 gpio_request_one(75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */
1058 gpio_request(GPIO_FN_SDHI0_D1, NULL);
1059 gpio_request(GPIO_FN_SDHI0_D2, NULL);
1060 gpio_request(GPIO_FN_SDHI0_D3, NULL);
1061 gpio_request(GPIO_FN_SDHI0_WP, NULL);
1062
1063 gpio_request_one(GPIO_PORT17, GPIOF_OUT_INIT_LOW, NULL); /* SDHI0_18/33_B */
1064 gpio_request_one(GPIO_PORT74, GPIOF_OUT_INIT_HIGH, NULL); /* SDHI0_PON */
1065 gpio_request_one(GPIO_PORT75, GPIOF_OUT_INIT_HIGH, NULL); /* SDSLOT1_PON */
1066 1065
1067 /* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */ 1066 /* we can use GPIO_FN_IRQ31_PORT167 here for SDHI0 CD irq */
1068 1067
1069 /*
1070 * MMCIF
1071 *
1072 * Here doesn't care SW1.4 status,
1073 * since CON2 is not mounted.
1074 */
1075 gpio_request(GPIO_FN_MMC1_CLK_PORT103, NULL);
1076 gpio_request(GPIO_FN_MMC1_CMD_PORT104, NULL);
1077 gpio_request(GPIO_FN_MMC1_D0_PORT149, NULL);
1078 gpio_request(GPIO_FN_MMC1_D1_PORT148, NULL);
1079 gpio_request(GPIO_FN_MMC1_D2_PORT147, NULL);
1080 gpio_request(GPIO_FN_MMC1_D3_PORT146, NULL);
1081 gpio_request(GPIO_FN_MMC1_D4_PORT145, NULL);
1082 gpio_request(GPIO_FN_MMC1_D5_PORT144, NULL);
1083 gpio_request(GPIO_FN_MMC1_D6_PORT143, NULL);
1084 gpio_request(GPIO_FN_MMC1_D7_PORT142, NULL);
1085
1086 /* CEU0 */ 1068 /* CEU0 */
1087 gpio_request(GPIO_FN_VIO0_D7, NULL); 1069 gpio_request(GPIO_FN_VIO0_D7, NULL);
1088 gpio_request(GPIO_FN_VIO0_D6, NULL); 1070 gpio_request(GPIO_FN_VIO0_D6, NULL);
@@ -1099,10 +1081,10 @@ static void __init eva_init(void)
1099 gpio_request(GPIO_FN_VIO_CKO, NULL); 1081 gpio_request(GPIO_FN_VIO_CKO, NULL);
1100 1082
1101 /* CON1/CON15 Camera */ 1083 /* CON1/CON15 Camera */
1102 gpio_request_one(GPIO_PORT173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */ 1084 gpio_request_one(173, GPIOF_OUT_INIT_LOW, NULL); /* STANDBY */
1103 gpio_request_one(GPIO_PORT172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */ 1085 gpio_request_one(172, GPIOF_OUT_INIT_HIGH, NULL); /* RST */
1104 /* see mt9t111_power() */ 1086 /* see mt9t111_power() */
1105 gpio_request_one(GPIO_PORT158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */ 1087 gpio_request_one(158, GPIOF_OUT_INIT_LOW, NULL); /* CAM_PON */
1106 1088
1107 /* FSI-WM8978 */ 1089 /* FSI-WM8978 */
1108 gpio_request(GPIO_FN_FSIAIBT, NULL); 1090 gpio_request(GPIO_FN_FSIAIBT, NULL);
@@ -1111,8 +1093,8 @@ static void __init eva_init(void)
1111 gpio_request(GPIO_FN_FSIAOSLD, NULL); 1093 gpio_request(GPIO_FN_FSIAOSLD, NULL);
1112 gpio_request(GPIO_FN_FSIAISLD_PORT5, NULL); 1094 gpio_request(GPIO_FN_FSIAISLD_PORT5, NULL);
1113 1095
1114 gpio_request(GPIO_PORT7, NULL); 1096 gpio_request(7, NULL);
1115 gpio_request(GPIO_PORT8, NULL); 1097 gpio_request(8, NULL);
1116 gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */ 1098 gpio_direction_none(GPIO_PORT7CR); /* FSIAOBT needs no direction */
1117 gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */ 1099 gpio_direction_none(GPIO_PORT8CR); /* FSIAOLR needs no direction */
1118 1100
@@ -1129,28 +1111,22 @@ static void __init eva_init(void)
1129 * DBGMD/LCDC0/FSIA MUX 1111 * DBGMD/LCDC0/FSIA MUX
1130 * DBGMD_SELECT_B should be set after setting PFC Function. 1112 * DBGMD_SELECT_B should be set after setting PFC Function.
1131 */ 1113 */
1132 gpio_request_one(GPIO_PORT176, GPIOF_OUT_INIT_HIGH, NULL); 1114 gpio_request_one(176, GPIOF_OUT_INIT_HIGH, NULL);
1133 1115
1134 /* 1116 /*
1135 * We can switch CON8/CON14 by SW1.5, 1117 * We can switch CON8/CON14 by SW1.5,
1136 * but it needs after DBGMD_SELECT_B 1118 * but it needs after DBGMD_SELECT_B
1137 */ 1119 */
1138 gpio_request_one(GPIO_PORT6, GPIOF_IN, NULL); 1120 gpio_request_one(6, GPIOF_IN, NULL);
1139 if (gpio_get_value(GPIO_PORT6)) { 1121 if (gpio_get_value(6)) {
1140 /* CON14 enable */ 1122 /* CON14 enable */
1141 } else { 1123 } else {
1142 /* CON8 (SDHI1) enable */ 1124 /* CON8 (SDHI1) enable */
1143 gpio_request(GPIO_FN_SDHI1_CLK, NULL); 1125 pinctrl_register_mappings(eva_sdhi1_pinctrl_map,
1144 gpio_request(GPIO_FN_SDHI1_CMD, NULL); 1126 ARRAY_SIZE(eva_sdhi1_pinctrl_map));
1145 gpio_request(GPIO_FN_SDHI1_D0, NULL);
1146 gpio_request(GPIO_FN_SDHI1_D1, NULL);
1147 gpio_request(GPIO_FN_SDHI1_D2, NULL);
1148 gpio_request(GPIO_FN_SDHI1_D3, NULL);
1149 gpio_request(GPIO_FN_SDHI1_CD, NULL);
1150 gpio_request(GPIO_FN_SDHI1_WP, NULL);
1151 1127
1152 /* SDSLOT2_PON */ 1128 /* SDSLOT2_PON */
1153 gpio_request_one(GPIO_PORT16, GPIOF_OUT_INIT_HIGH, NULL); 1129 gpio_request_one(16, GPIOF_OUT_INIT_HIGH, NULL);
1154 1130
1155 platform_device_register(&sdhi1_device); 1131 platform_device_register(&sdhi1_device);
1156 } 1132 }
diff --git a/arch/arm/mach-shmobile/board-bonito.c b/arch/arm/mach-shmobile/board-bonito.c
index e50f86691539..70d992c540ae 100644
--- a/arch/arm/mach-shmobile/board-bonito.c
+++ b/arch/arm/mach-shmobile/board-bonito.c
@@ -24,6 +24,7 @@
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/interrupt.h> 25#include <linux/interrupt.h>
26#include <linux/irq.h> 26#include <linux/irq.h>
27#include <linux/pinctrl/machine.h>
27#include <linux/platform_device.h> 28#include <linux/platform_device.h>
28#include <linux/gpio.h> 29#include <linux/gpio.h>
29#include <linux/regulator/fixed.h> 30#include <linux/regulator/fixed.h>
@@ -288,6 +289,16 @@ static struct platform_device lcdc0_device = {
288 }, 289 },
289}; 290};
290 291
292static const struct pinctrl_map lcdc0_pinctrl_map[] = {
293 /* LCD0 */
294 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
295 "lcd0_data24_1", "lcd0"),
296 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
297 "lcd0_lclk_1", "lcd0"),
298 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
299 "lcd0_sync", "lcd0"),
300};
301
291/* 302/*
292 * SMSC 9221 303 * SMSC 9221
293 */ 304 */
@@ -392,8 +403,8 @@ static void __init bonito_init(void)
392 /* 403 /*
393 * base board settings 404 * base board settings
394 */ 405 */
395 gpio_request_one(GPIO_PORT176, GPIOF_IN, NULL); 406 gpio_request_one(176, GPIOF_IN, NULL);
396 if (!gpio_get_value(GPIO_PORT176)) { 407 if (!gpio_get_value(176)) {
397 u16 bsw2; 408 u16 bsw2;
398 u16 bsw3; 409 u16 bsw3;
399 u16 bsw4; 410 u16 bsw4;
@@ -430,38 +441,11 @@ static void __init bonito_init(void)
430 */ 441 */
431 if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */ 442 if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
432 BIT_ON(bsw2, 2)) { /* S38.2 = OFF */ 443 BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
433 gpio_request(GPIO_FN_LCDC0_SELECT, NULL); 444 pinctrl_register_mappings(lcdc0_pinctrl_map,
434 gpio_request(GPIO_FN_LCD0_D0, NULL); 445 ARRAY_SIZE(lcdc0_pinctrl_map));
435 gpio_request(GPIO_FN_LCD0_D1, NULL); 446 gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
436 gpio_request(GPIO_FN_LCD0_D2, NULL); 447
437 gpio_request(GPIO_FN_LCD0_D3, NULL); 448 gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
438 gpio_request(GPIO_FN_LCD0_D4, NULL);
439 gpio_request(GPIO_FN_LCD0_D5, NULL);
440 gpio_request(GPIO_FN_LCD0_D6, NULL);
441 gpio_request(GPIO_FN_LCD0_D7, NULL);
442 gpio_request(GPIO_FN_LCD0_D8, NULL);
443 gpio_request(GPIO_FN_LCD0_D9, NULL);
444 gpio_request(GPIO_FN_LCD0_D10, NULL);
445 gpio_request(GPIO_FN_LCD0_D11, NULL);
446 gpio_request(GPIO_FN_LCD0_D12, NULL);
447 gpio_request(GPIO_FN_LCD0_D13, NULL);
448 gpio_request(GPIO_FN_LCD0_D14, NULL);
449 gpio_request(GPIO_FN_LCD0_D15, NULL);
450 gpio_request(GPIO_FN_LCD0_D16, NULL);
451 gpio_request(GPIO_FN_LCD0_D17, NULL);
452 gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
453 gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
454 gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
455 gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
456 gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
457 gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
458 gpio_request(GPIO_FN_LCD0_DCK, NULL);
459 gpio_request(GPIO_FN_LCD0_VSYN, NULL);
460 gpio_request(GPIO_FN_LCD0_HSYN, NULL);
461 gpio_request(GPIO_FN_LCD0_DISP, NULL);
462 gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
463
464 gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH,
465 NULL); /* LCDDON */ 449 NULL); /* LCDDON */
466 450
467 /* backlight on */ 451 /* backlight on */
diff --git a/arch/arm/mach-shmobile/board-kota2.c b/arch/arm/mach-shmobile/board-kota2.c
index 2ccc860403ef..ef5ca0ef0cb5 100644
--- a/arch/arm/mach-shmobile/board-kota2.c
+++ b/arch/arm/mach-shmobile/board-kota2.c
@@ -24,6 +24,8 @@
24#include <linux/init.h> 24#include <linux/init.h>
25#include <linux/interrupt.h> 25#include <linux/interrupt.h>
26#include <linux/irq.h> 26#include <linux/irq.h>
27#include <linux/pinctrl/machine.h>
28#include <linux/pinctrl/pinconf-generic.h>
27#include <linux/platform_device.h> 29#include <linux/platform_device.h>
28#include <linux/delay.h> 30#include <linux/delay.h>
29#include <linux/io.h> 31#include <linux/io.h>
@@ -135,17 +137,17 @@ static struct platform_device keysc_device = {
135#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 } 137#define GPIO_KEY(c, g, d) { .code = c, .gpio = g, .desc = d, .active_low = 1 }
136 138
137static struct gpio_keys_button gpio_buttons[] = { 139static struct gpio_keys_button gpio_buttons[] = {
138 GPIO_KEY(KEY_VOLUMEUP, GPIO_PORT56, "+"), /* S2: VOL+ [IRQ9] */ 140 GPIO_KEY(KEY_VOLUMEUP, 56, "+"), /* S2: VOL+ [IRQ9] */
139 GPIO_KEY(KEY_VOLUMEDOWN, GPIO_PORT54, "-"), /* S3: VOL- [IRQ10] */ 141 GPIO_KEY(KEY_VOLUMEDOWN, 54, "-"), /* S3: VOL- [IRQ10] */
140 GPIO_KEY(KEY_MENU, GPIO_PORT27, "Menu"), /* S4: MENU [IRQ30] */ 142 GPIO_KEY(KEY_MENU, 27, "Menu"), /* S4: MENU [IRQ30] */
141 GPIO_KEY(KEY_HOMEPAGE, GPIO_PORT26, "Home"), /* S5: HOME [IRQ31] */ 143 GPIO_KEY(KEY_HOMEPAGE, 26, "Home"), /* S5: HOME [IRQ31] */
142 GPIO_KEY(KEY_BACK, GPIO_PORT11, "Back"), /* S6: BACK [IRQ0] */ 144 GPIO_KEY(KEY_BACK, 11, "Back"), /* S6: BACK [IRQ0] */
143 GPIO_KEY(KEY_PHONE, GPIO_PORT238, "Tel"), /* S7: TEL [IRQ11] */ 145 GPIO_KEY(KEY_PHONE, 238, "Tel"), /* S7: TEL [IRQ11] */
144 GPIO_KEY(KEY_POWER, GPIO_PORT239, "C1"), /* S8: CAM [IRQ13] */ 146 GPIO_KEY(KEY_POWER, 239, "C1"), /* S8: CAM [IRQ13] */
145 GPIO_KEY(KEY_MAIL, GPIO_PORT224, "Mail"), /* S9: MAIL [IRQ3] */ 147 GPIO_KEY(KEY_MAIL, 224, "Mail"), /* S9: MAIL [IRQ3] */
146 /* Omitted button "C3?": GPIO_PORT223 - S10: CUST [IRQ8] */ 148 /* Omitted button "C3?": 223 - S10: CUST [IRQ8] */
147 GPIO_KEY(KEY_CAMERA, GPIO_PORT164, "C2"), /* S11: CAM_HALF [IRQ25] */ 149 GPIO_KEY(KEY_CAMERA, 164, "C2"), /* S11: CAM_HALF [IRQ25] */
148 /* Omitted button "?": GPIO_PORT152 - S12: CAM_FULL [No IRQ] */ 150 /* Omitted button "?": 152 - S12: CAM_FULL [No IRQ] */
149}; 151};
150 152
151static struct gpio_keys_platform_data gpio_key_info = { 153static struct gpio_keys_platform_data gpio_key_info = {
@@ -165,9 +167,9 @@ static struct platform_device gpio_keys_device = {
165#define GPIO_LED(n, g) { .name = n, .gpio = g } 167#define GPIO_LED(n, g) { .name = n, .gpio = g }
166 168
167static struct gpio_led gpio_leds[] = { 169static struct gpio_led gpio_leds[] = {
168 GPIO_LED("G", GPIO_PORT20), /* PORT20 [GPO0] -> LED7 -> "G" */ 170 GPIO_LED("G", 20), /* PORT20 [GPO0] -> LED7 -> "G" */
169 GPIO_LED("H", GPIO_PORT21), /* PORT21 [GPO1] -> LED8 -> "H" */ 171 GPIO_LED("H", 21), /* PORT21 [GPO1] -> LED8 -> "H" */
170 GPIO_LED("J", GPIO_PORT22), /* PORT22 [GPO2] -> LED9 -> "J" */ 172 GPIO_LED("J", 22), /* PORT22 [GPO2] -> LED9 -> "J" */
171}; 173};
172 174
173static struct gpio_led_platform_data gpio_leds_info = { 175static struct gpio_led_platform_data gpio_leds_info = {
@@ -187,7 +189,7 @@ static struct platform_device gpio_leds_device = {
187static struct led_renesas_tpu_config led_renesas_tpu12_pdata = { 189static struct led_renesas_tpu_config led_renesas_tpu12_pdata = {
188 .name = "V2513", 190 .name = "V2513",
189 .pin_gpio_fn = GPIO_FN_TPU1TO2, 191 .pin_gpio_fn = GPIO_FN_TPU1TO2,
190 .pin_gpio = GPIO_PORT153, 192 .pin_gpio = 153,
191 .channel_offset = 0x90, 193 .channel_offset = 0x90,
192 .timer_bit = 2, 194 .timer_bit = 2,
193 .max_brightness = 1000, 195 .max_brightness = 1000,
@@ -215,7 +217,7 @@ static struct platform_device leds_tpu12_device = {
215static struct led_renesas_tpu_config led_renesas_tpu41_pdata = { 217static struct led_renesas_tpu_config led_renesas_tpu41_pdata = {
216 .name = "V2514", 218 .name = "V2514",
217 .pin_gpio_fn = GPIO_FN_TPU4TO1, 219 .pin_gpio_fn = GPIO_FN_TPU4TO1,
218 .pin_gpio = GPIO_PORT199, 220 .pin_gpio = 199,
219 .channel_offset = 0x50, 221 .channel_offset = 0x50,
220 .timer_bit = 1, 222 .timer_bit = 1,
221 .max_brightness = 1000, 223 .max_brightness = 1000,
@@ -243,7 +245,7 @@ static struct platform_device leds_tpu41_device = {
243static struct led_renesas_tpu_config led_renesas_tpu21_pdata = { 245static struct led_renesas_tpu_config led_renesas_tpu21_pdata = {
244 .name = "V2515", 246 .name = "V2515",
245 .pin_gpio_fn = GPIO_FN_TPU2TO1, 247 .pin_gpio_fn = GPIO_FN_TPU2TO1,
246 .pin_gpio = GPIO_PORT197, 248 .pin_gpio = 197,
247 .channel_offset = 0x50, 249 .channel_offset = 0x50,
248 .timer_bit = 1, 250 .timer_bit = 1,
249 .max_brightness = 1000, 251 .max_brightness = 1000,
@@ -271,7 +273,7 @@ static struct platform_device leds_tpu21_device = {
271static struct led_renesas_tpu_config led_renesas_tpu30_pdata = { 273static struct led_renesas_tpu_config led_renesas_tpu30_pdata = {
272 .name = "KEYLED", 274 .name = "KEYLED",
273 .pin_gpio_fn = GPIO_FN_TPU3TO0, 275 .pin_gpio_fn = GPIO_FN_TPU3TO0,
274 .pin_gpio = GPIO_PORT163, 276 .pin_gpio = 163,
275 .channel_offset = 0x10, 277 .channel_offset = 0x10,
276 .timer_bit = 0, 278 .timer_bit = 0,
277 .max_brightness = 1000, 279 .max_brightness = 1000,
@@ -433,6 +435,85 @@ static struct platform_device *kota2_devices[] __initdata = {
433 &sdhi1_device, 435 &sdhi1_device,
434}; 436};
435 437
438static unsigned long pin_pullup_conf[] = {
439 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
440};
441
442static const struct pinctrl_map kota2_pinctrl_map[] = {
443 /* KEYSC */
444 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
445 "keysc_in8", "keysc"),
446 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
447 "keysc_out04", "keysc"),
448 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
449 "keysc_out5", "keysc"),
450 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
451 "keysc_out6_0", "keysc"),
452 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
453 "keysc_out7_0", "keysc"),
454 PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
455 "keysc_out8_0", "keysc"),
456 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
457 "keysc_in8", pin_pullup_conf),
458 /* MMCIF */
459 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
460 "mmc0_data8_0", "mmc0"),
461 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
462 "mmc0_ctrl_0", "mmc0"),
463 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
464 "PORT279", pin_pullup_conf),
465 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
466 "mmc0_data8_0", pin_pullup_conf),
467 /* SCIFA2 (UART2) */
468 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
469 "scifa2_data_0", "scifa2"),
470 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
471 "scifa2_ctrl_0", "scifa2"),
472 /* SCIFA4 (UART1) */
473 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
474 "scifa4_data", "scifa4"),
475 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
476 "scifa4_ctrl", "scifa4"),
477 /* SCIFB (BT) */
478 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
479 "scifb_data_0", "scifb"),
480 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
481 "scifb_clk_0", "scifb"),
482 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.8", "pfc-sh73a0",
483 "scifb_ctrl_0", "scifb"),
484 /* SDHI0 (microSD) */
485 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
486 "sdhi0_data4", "sdhi0"),
487 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
488 "sdhi0_ctrl", "sdhi0"),
489 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
490 "sdhi0_cd", "sdhi0"),
491 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
492 "sdhi0_data4", pin_pullup_conf),
493 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
494 "PORT256", pin_pullup_conf),
495 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
496 "PORT251", pin_pullup_conf),
497 /* SDHI1 (BCM4330) */
498 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
499 "sdhi1_data4", "sdhi1"),
500 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
501 "sdhi1_ctrl", "sdhi1"),
502 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
503 "sdhi1_data4", pin_pullup_conf),
504 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
505 "PORT263", pin_pullup_conf),
506 /* SMSC911X */
507 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
508 "bsc_data_0_7", "bsc"),
509 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
510 "bsc_data_8_15", "bsc"),
511 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
512 "bsc_cs5_a", "bsc"),
513 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
514 "bsc_we0", "bsc"),
515};
516
436static void __init kota2_init(void) 517static void __init kota2_init(void)
437{ 518{
438 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers, 519 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
@@ -441,97 +522,16 @@ static void __init kota2_init(void)
441 ARRAY_SIZE(fixed3v3_power_consumers), 3300000); 522 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
442 regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies)); 523 regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
443 524
525 pinctrl_register_mappings(kota2_pinctrl_map,
526 ARRAY_SIZE(kota2_pinctrl_map));
444 sh73a0_pinmux_init(); 527 sh73a0_pinmux_init();
445 528
446 /* SCIFA2 (UART2) */
447 gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
448 gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
449 gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
450 gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
451
452 /* SCIFA4 (UART1) */
453 gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
454 gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
455 gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
456 gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
457
458 /* SMSC911X */ 529 /* SMSC911X */
459 gpio_request(GPIO_FN_D0_NAF0, NULL); 530 gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
460 gpio_request(GPIO_FN_D1_NAF1, NULL); 531 gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
461 gpio_request(GPIO_FN_D2_NAF2, NULL);
462 gpio_request(GPIO_FN_D3_NAF3, NULL);
463 gpio_request(GPIO_FN_D4_NAF4, NULL);
464 gpio_request(GPIO_FN_D5_NAF5, NULL);
465 gpio_request(GPIO_FN_D6_NAF6, NULL);
466 gpio_request(GPIO_FN_D7_NAF7, NULL);
467 gpio_request(GPIO_FN_D8_NAF8, NULL);
468 gpio_request(GPIO_FN_D9_NAF9, NULL);
469 gpio_request(GPIO_FN_D10_NAF10, NULL);
470 gpio_request(GPIO_FN_D11_NAF11, NULL);
471 gpio_request(GPIO_FN_D12_NAF12, NULL);
472 gpio_request(GPIO_FN_D13_NAF13, NULL);
473 gpio_request(GPIO_FN_D14_NAF14, NULL);
474 gpio_request(GPIO_FN_D15_NAF15, NULL);
475 gpio_request(GPIO_FN_CS5A_, NULL);
476 gpio_request(GPIO_FN_WE0__FWE, NULL);
477 gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
478 gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
479
480 /* KEYSC */
481 gpio_request(GPIO_FN_KEYIN0_PU, NULL);
482 gpio_request(GPIO_FN_KEYIN1_PU, NULL);
483 gpio_request(GPIO_FN_KEYIN2_PU, NULL);
484 gpio_request(GPIO_FN_KEYIN3_PU, NULL);
485 gpio_request(GPIO_FN_KEYIN4_PU, NULL);
486 gpio_request(GPIO_FN_KEYIN5_PU, NULL);
487 gpio_request(GPIO_FN_KEYIN6_PU, NULL);
488 gpio_request(GPIO_FN_KEYIN7_PU, NULL);
489 gpio_request(GPIO_FN_KEYOUT0, NULL);
490 gpio_request(GPIO_FN_KEYOUT1, NULL);
491 gpio_request(GPIO_FN_KEYOUT2, NULL);
492 gpio_request(GPIO_FN_KEYOUT3, NULL);
493 gpio_request(GPIO_FN_KEYOUT4, NULL);
494 gpio_request(GPIO_FN_KEYOUT5, NULL);
495 gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
496 gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
497 gpio_request(GPIO_FN_KEYOUT8, NULL);
498 532
499 /* MMCIF */ 533 /* MMCIF */
500 gpio_request(GPIO_FN_MMCCLK0, NULL); 534 gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
501 gpio_request(GPIO_FN_MMCD0_0, NULL);
502 gpio_request(GPIO_FN_MMCD0_1, NULL);
503 gpio_request(GPIO_FN_MMCD0_2, NULL);
504 gpio_request(GPIO_FN_MMCD0_3, NULL);
505 gpio_request(GPIO_FN_MMCD0_4, NULL);
506 gpio_request(GPIO_FN_MMCD0_5, NULL);
507 gpio_request(GPIO_FN_MMCD0_6, NULL);
508 gpio_request(GPIO_FN_MMCD0_7, NULL);
509 gpio_request(GPIO_FN_MMCCMD0, NULL);
510 gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
511
512 /* SDHI0 (microSD) */
513 gpio_request(GPIO_FN_SDHICD0_PU, NULL);
514 gpio_request(GPIO_FN_SDHICMD0_PU, NULL);
515 gpio_request(GPIO_FN_SDHICLK0, NULL);
516 gpio_request(GPIO_FN_SDHID0_3_PU, NULL);
517 gpio_request(GPIO_FN_SDHID0_2_PU, NULL);
518 gpio_request(GPIO_FN_SDHID0_1_PU, NULL);
519 gpio_request(GPIO_FN_SDHID0_0_PU, NULL);
520
521 /* SCIFB (BT) */
522 gpio_request(GPIO_FN_PORT159_SCIFB_SCK, NULL);
523 gpio_request(GPIO_FN_PORT160_SCIFB_TXD, NULL);
524 gpio_request(GPIO_FN_PORT161_SCIFB_CTS_, NULL);
525 gpio_request(GPIO_FN_PORT162_SCIFB_RXD, NULL);
526 gpio_request(GPIO_FN_PORT163_SCIFB_RTS_, NULL);
527
528 /* SDHI1 (BCM4330) */
529 gpio_request(GPIO_FN_SDHICLK1, NULL);
530 gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
531 gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
532 gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
533 gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
534 gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
535 535
536#ifdef CONFIG_CACHE_L2X0 536#ifdef CONFIG_CACHE_L2X0
537 /* Early BRESP enable, Shared attribute override enable, 64K*8way */ 537 /* Early BRESP enable, Shared attribute override enable, 64K*8way */
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index d34d12ae496b..446d04db404f 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -30,6 +30,8 @@
30#include <linux/mmc/sh_mmcif.h> 30#include <linux/mmc/sh_mmcif.h>
31#include <linux/mmc/sh_mobile_sdhi.h> 31#include <linux/mmc/sh_mobile_sdhi.h>
32#include <linux/mfd/tmio.h> 32#include <linux/mfd/tmio.h>
33#include <linux/pinctrl/machine.h>
34#include <linux/pinctrl/pinconf-generic.h>
33#include <linux/platform_device.h> 35#include <linux/platform_device.h>
34#include <linux/regulator/fixed.h> 36#include <linux/regulator/fixed.h>
35#include <linux/regulator/machine.h> 37#include <linux/regulator/machine.h>
@@ -433,7 +435,7 @@ static struct sh_mobile_sdhi_info sdhi2_info = {
433 TMIO_MMC_WRPROTECT_DISABLE, 435 TMIO_MMC_WRPROTECT_DISABLE,
434 .tmio_caps = MMC_CAP_SD_HIGHSPEED, 436 .tmio_caps = MMC_CAP_SD_HIGHSPEED,
435 .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29, 437 .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
436 .cd_gpio = GPIO_PORT13, 438 .cd_gpio = 13,
437}; 439};
438 440
439static struct resource sdhi2_resources[] = { 441static struct resource sdhi2_resources[] = {
@@ -599,6 +601,64 @@ static struct platform_device *kzm_devices[] __initdata = {
599 &fsi_ak4648_device, 601 &fsi_ak4648_device,
600}; 602};
601 603
604static unsigned long pin_pullup_conf[] = {
605 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
606};
607
608static const struct pinctrl_map kzm_pinctrl_map[] = {
609 /* FSIA (AK4648) */
610 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
611 "fsia_mclk_in", "fsia"),
612 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
613 "fsia_sclk_in", "fsia"),
614 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
615 "fsia_data_in", "fsia"),
616 PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
617 "fsia_data_out", "fsia"),
618 /* I2C3 */
619 PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
620 "i2c3_1", "i2c3"),
621 /* LCD */
622 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
623 "lcd_data24", "lcd"),
624 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
625 "lcd_sync", "lcd"),
626 /* MMCIF */
627 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
628 "mmc0_data8_0", "mmc0"),
629 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
630 "mmc0_ctrl_0", "mmc0"),
631 PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
632 "PORT279", pin_pullup_conf),
633 PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
634 "mmc0_data8_0", pin_pullup_conf),
635 /* SCIFA4 */
636 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
637 "scifa4_data", "scifa4"),
638 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
639 "scifa4_ctrl", "scifa4"),
640 /* SDHI0 */
641 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
642 "sdhi0_data4", "sdhi0"),
643 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
644 "sdhi0_ctrl", "sdhi0"),
645 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
646 "sdhi0_cd", "sdhi0"),
647 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
648 "sdhi0_wp", "sdhi0"),
649 /* SDHI2 */
650 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
651 "sdhi2_data4", "sdhi2"),
652 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
653 "sdhi2_ctrl", "sdhi2"),
654 /* SMSC */
655 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
656 "bsc_cs4", "bsc"),
657 /* USB */
658 PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-sh73a0",
659 "usb_vbus", "usb"),
660};
661
602/* 662/*
603 * FIXME 663 * FIXME
604 * 664 *
@@ -660,100 +720,26 @@ static void __init kzm_init(void)
660 ARRAY_SIZE(fixed2v8_power_consumers), 2800000); 720 ARRAY_SIZE(fixed2v8_power_consumers), 2800000);
661 regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies)); 721 regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
662 722
663 sh73a0_pinmux_init(); 723 pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
664
665 /* enable SCIFA4 */
666 gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
667 gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
668 gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
669 gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
670 724
671 /* CS4 for SMSC/USB */ 725 sh73a0_pinmux_init();
672 gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */
673 726
674 /* SMSC */ 727 /* SMSC */
675 gpio_request_one(GPIO_PORT224, GPIOF_IN, NULL); /* IRQ3 */ 728 gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */
676 729
677 /* LCDC */ 730 /* LCDC */
678 gpio_request(GPIO_FN_LCDD23, NULL); 731 gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
679 gpio_request(GPIO_FN_LCDD22, NULL); 732 gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
680 gpio_request(GPIO_FN_LCDD21, NULL);
681 gpio_request(GPIO_FN_LCDD20, NULL);
682 gpio_request(GPIO_FN_LCDD19, NULL);
683 gpio_request(GPIO_FN_LCDD18, NULL);
684 gpio_request(GPIO_FN_LCDD17, NULL);
685 gpio_request(GPIO_FN_LCDD16, NULL);
686 gpio_request(GPIO_FN_LCDD15, NULL);
687 gpio_request(GPIO_FN_LCDD14, NULL);
688 gpio_request(GPIO_FN_LCDD13, NULL);
689 gpio_request(GPIO_FN_LCDD12, NULL);
690 gpio_request(GPIO_FN_LCDD11, NULL);
691 gpio_request(GPIO_FN_LCDD10, NULL);
692 gpio_request(GPIO_FN_LCDD9, NULL);
693 gpio_request(GPIO_FN_LCDD8, NULL);
694 gpio_request(GPIO_FN_LCDD7, NULL);
695 gpio_request(GPIO_FN_LCDD6, NULL);
696 gpio_request(GPIO_FN_LCDD5, NULL);
697 gpio_request(GPIO_FN_LCDD4, NULL);
698 gpio_request(GPIO_FN_LCDD3, NULL);
699 gpio_request(GPIO_FN_LCDD2, NULL);
700 gpio_request(GPIO_FN_LCDD1, NULL);
701 gpio_request(GPIO_FN_LCDD0, NULL);
702 gpio_request(GPIO_FN_LCDDISP, NULL);
703 gpio_request(GPIO_FN_LCDDCK, NULL);
704
705 gpio_request_one(GPIO_PORT222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
706 gpio_request_one(GPIO_PORT226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
707 733
708 /* Touchscreen */ 734 /* Touchscreen */
709 gpio_request_one(GPIO_PORT223, GPIOF_IN, NULL); /* IRQ8 */ 735 gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
710
711 /* enable MMCIF */
712 gpio_request(GPIO_FN_MMCCLK0, NULL);
713 gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
714 gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
715 gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
716 gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
717 gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
718 gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
719 gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
720 gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
721 gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
722 736
723 /* enable SD */ 737 /* enable SD */
724 gpio_request(GPIO_FN_SDHIWP0, NULL);
725 gpio_request(GPIO_FN_SDHICD0, NULL);
726 gpio_request(GPIO_FN_SDHICMD0, NULL);
727 gpio_request(GPIO_FN_SDHICLK0, NULL);
728 gpio_request(GPIO_FN_SDHID0_3, NULL);
729 gpio_request(GPIO_FN_SDHID0_2, NULL);
730 gpio_request(GPIO_FN_SDHID0_1, NULL);
731 gpio_request(GPIO_FN_SDHID0_0, NULL);
732 gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL); 738 gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
733 gpio_request_one(GPIO_PORT15, GPIOF_OUT_INIT_HIGH, NULL); /* power */ 739 gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
734 740
735 /* enable Micro SD */ 741 /* enable Micro SD */
736 gpio_request(GPIO_FN_SDHID2_0, NULL); 742 gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
737 gpio_request(GPIO_FN_SDHID2_1, NULL);
738 gpio_request(GPIO_FN_SDHID2_2, NULL);
739 gpio_request(GPIO_FN_SDHID2_3, NULL);
740 gpio_request(GPIO_FN_SDHICMD2, NULL);
741 gpio_request(GPIO_FN_SDHICLK2, NULL);
742 gpio_request_one(GPIO_PORT14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
743
744 /* I2C 3 */
745 gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
746 gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
747
748 /* enable FSI2 port A (ak4648) */
749 gpio_request(GPIO_FN_FSIACK, NULL);
750 gpio_request(GPIO_FN_FSIAILR, NULL);
751 gpio_request(GPIO_FN_FSIAIBT, NULL);
752 gpio_request(GPIO_FN_FSIAISLD, NULL);
753 gpio_request(GPIO_FN_FSIAOSLD, NULL);
754
755 /* enable USB */
756 gpio_request(GPIO_FN_VBUS_0, NULL);
757 743
758#ifdef CONFIG_CACHE_L2X0 744#ifdef CONFIG_CACHE_L2X0
759 /* Early BRESP enable, Shared attribute override enable, 64K*8way */ 745 /* Early BRESP enable, Shared attribute override enable, 64K*8way */
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index db968a585ff0..336ccb4a0f2a 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -40,6 +40,7 @@
40#include <linux/mtd/partitions.h> 40#include <linux/mtd/partitions.h>
41#include <linux/mtd/physmap.h> 41#include <linux/mtd/physmap.h>
42#include <linux/mtd/sh_flctl.h> 42#include <linux/mtd/sh_flctl.h>
43#include <linux/pinctrl/machine.h>
43#include <linux/pm_clock.h> 44#include <linux/pm_clock.h>
44#include <linux/regulator/fixed.h> 45#include <linux/regulator/fixed.h>
45#include <linux/regulator/machine.h> 46#include <linux/regulator/machine.h>
@@ -363,7 +364,7 @@ static struct fb_videomode mackerel_lcdc_modes[] = {
363 364
364static int mackerel_set_brightness(int brightness) 365static int mackerel_set_brightness(int brightness)
365{ 366{
366 gpio_set_value(GPIO_PORT31, brightness); 367 gpio_set_value(31, brightness);
367 368
368 return 0; 369 return 0;
369} 370}
@@ -819,22 +820,22 @@ static struct platform_device usbhs1_device = {
819static struct gpio_led mackerel_leds[] = { 820static struct gpio_led mackerel_leds[] = {
820 { 821 {
821 .name = "led0", 822 .name = "led0",
822 .gpio = GPIO_PORT0, 823 .gpio = 0,
823 .default_state = LEDS_GPIO_DEFSTATE_ON, 824 .default_state = LEDS_GPIO_DEFSTATE_ON,
824 }, 825 },
825 { 826 {
826 .name = "led1", 827 .name = "led1",
827 .gpio = GPIO_PORT1, 828 .gpio = 1,
828 .default_state = LEDS_GPIO_DEFSTATE_ON, 829 .default_state = LEDS_GPIO_DEFSTATE_ON,
829 }, 830 },
830 { 831 {
831 .name = "led2", 832 .name = "led2",
832 .gpio = GPIO_PORT2, 833 .gpio = 2,
833 .default_state = LEDS_GPIO_DEFSTATE_ON, 834 .default_state = LEDS_GPIO_DEFSTATE_ON,
834 }, 835 },
835 { 836 {
836 .name = "led3", 837 .name = "led3",
837 .gpio = GPIO_PORT159, 838 .gpio = 159,
838 .default_state = LEDS_GPIO_DEFSTATE_ON, 839 .default_state = LEDS_GPIO_DEFSTATE_ON,
839 } 840 }
840}; 841};
@@ -964,11 +965,11 @@ static struct platform_device nand_flash_device = {
964 965
965/* 966/*
966 * The card detect pin of the top SD/MMC slot (CN7) is active low and is 967 * The card detect pin of the top SD/MMC slot (CN7) is active low and is
967 * connected to GPIO A22 of SH7372 (GPIO_PORT41). 968 * connected to GPIO A22 of SH7372 (GPIO 41).
968 */ 969 */
969static int slot_cn7_get_cd(struct platform_device *pdev) 970static int slot_cn7_get_cd(struct platform_device *pdev)
970{ 971{
971 return !gpio_get_value(GPIO_PORT41); 972 return !gpio_get_value(41);
972} 973}
973 974
974/* SDHI0 */ 975/* SDHI0 */
@@ -977,7 +978,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
977 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX, 978 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
978 .tmio_flags = TMIO_MMC_USE_GPIO_CD, 979 .tmio_flags = TMIO_MMC_USE_GPIO_CD,
979 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ, 980 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
980 .cd_gpio = GPIO_PORT172, 981 .cd_gpio = 172,
981}; 982};
982 983
983static struct resource sdhi0_resources[] = { 984static struct resource sdhi0_resources[] = {
@@ -1060,11 +1061,11 @@ static struct platform_device sdhi1_device = {
1060 1061
1061/* 1062/*
1062 * The card detect pin of the top SD/MMC slot (CN23) is active low and is 1063 * The card detect pin of the top SD/MMC slot (CN23) is active low and is
1063 * connected to GPIO SCIFB_SCK of SH7372 (GPIO_PORT162). 1064 * connected to GPIO SCIFB_SCK of SH7372 (162).
1064 */ 1065 */
1065static int slot_cn23_get_cd(struct platform_device *pdev) 1066static int slot_cn23_get_cd(struct platform_device *pdev)
1066{ 1067{
1067 return !gpio_get_value(GPIO_PORT162); 1068 return !gpio_get_value(162);
1068} 1069}
1069 1070
1070/* SDHI2 */ 1071/* SDHI2 */
@@ -1328,6 +1329,33 @@ static struct i2c_board_info i2c1_devices[] = {
1328 }, 1329 },
1329}; 1330};
1330 1331
1332static const struct pinctrl_map mackerel_pinctrl_map[] = {
1333 /* MMCIF */
1334 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1335 "mmc0_data8_0", "mmc0"),
1336 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1337 "mmc0_ctrl_0", "mmc0"),
1338 /* SDHI0 */
1339 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1340 "sdhi0_data4", "sdhi0"),
1341 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1342 "sdhi0_ctrl", "sdhi0"),
1343 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1344 "sdhi0_wp", "sdhi0"),
1345 /* SDHI1 */
1346#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
1347 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
1348 "sdhi1_data4", "sdhi1"),
1349 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
1350 "sdhi1_ctrl", "sdhi1"),
1351#endif
1352 /* SDHI2 */
1353 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
1354 "sdhi2_data4", "sdhi2"),
1355 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
1356 "sdhi2_ctrl", "sdhi2"),
1357};
1358
1331#define GPIO_PORT9CR IOMEM(0xE6051009) 1359#define GPIO_PORT9CR IOMEM(0xE6051009)
1332#define GPIO_PORT10CR IOMEM(0xE605100A) 1360#define GPIO_PORT10CR IOMEM(0xE605100A)
1333#define GPIO_PORT167CR IOMEM(0xE60520A7) 1361#define GPIO_PORT167CR IOMEM(0xE60520A7)
@@ -1364,6 +1392,8 @@ static void __init mackerel_init(void)
1364 /* External clock source */ 1392 /* External clock source */
1365 clk_set_rate(&sh7372_dv_clki_clk, 27000000); 1393 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
1366 1394
1395 pinctrl_register_mappings(mackerel_pinctrl_map,
1396 ARRAY_SIZE(mackerel_pinctrl_map));
1367 sh7372_pinmux_init(); 1397 sh7372_pinmux_init();
1368 1398
1369 /* enable SCIFA0 */ 1399 /* enable SCIFA0 */
@@ -1403,9 +1433,9 @@ static void __init mackerel_init(void)
1403 gpio_request(GPIO_FN_LCDDCK, NULL); 1433 gpio_request(GPIO_FN_LCDDCK, NULL);
1404 1434
1405 /* backlight, off by default */ 1435 /* backlight, off by default */
1406 gpio_request_one(GPIO_PORT31, GPIOF_OUT_INIT_LOW, NULL); 1436 gpio_request_one(31, GPIOF_OUT_INIT_LOW, NULL);
1407 1437
1408 gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */ 1438 gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
1409 1439
1410 /* USBHS0 */ 1440 /* USBHS0 */
1411 gpio_request(GPIO_FN_VBUS0_0, NULL); 1441 gpio_request(GPIO_FN_VBUS0_0, NULL);
@@ -1421,10 +1451,10 @@ static void __init mackerel_init(void)
1421 gpio_request(GPIO_FN_FSIAILR, NULL); 1451 gpio_request(GPIO_FN_FSIAILR, NULL);
1422 gpio_request(GPIO_FN_FSIAISLD, NULL); 1452 gpio_request(GPIO_FN_FSIAISLD, NULL);
1423 gpio_request(GPIO_FN_FSIAOSLD, NULL); 1453 gpio_request(GPIO_FN_FSIAOSLD, NULL);
1424 gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */ 1454 gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
1425 1455
1426 gpio_request(GPIO_PORT9, NULL); 1456 gpio_request(9, NULL);
1427 gpio_request(GPIO_PORT10, NULL); 1457 gpio_request(10, NULL);
1428 gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */ 1458 gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
1429 gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */ 1459 gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
1430 1460
@@ -1453,52 +1483,14 @@ static void __init mackerel_init(void)
1453 gpio_request(GPIO_FN_IRQ21, NULL); 1483 gpio_request(GPIO_FN_IRQ21, NULL);
1454 irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH); 1484 irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
1455 1485
1456 /* enable SDHI0 */
1457 gpio_request(GPIO_FN_SDHIWP0, NULL);
1458 gpio_request(GPIO_FN_SDHICMD0, NULL);
1459 gpio_request(GPIO_FN_SDHICLK0, NULL);
1460 gpio_request(GPIO_FN_SDHID0_3, NULL);
1461 gpio_request(GPIO_FN_SDHID0_2, NULL);
1462 gpio_request(GPIO_FN_SDHID0_1, NULL);
1463 gpio_request(GPIO_FN_SDHID0_0, NULL);
1464
1465 /* SDHI0 PORT172 card-detect IRQ26 */ 1486 /* SDHI0 PORT172 card-detect IRQ26 */
1466 gpio_request(GPIO_FN_IRQ26_172, NULL); 1487 gpio_request(GPIO_FN_IRQ26_172, NULL);
1467 1488
1468#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
1469 /* enable SDHI1 */
1470 gpio_request(GPIO_FN_SDHICMD1, NULL);
1471 gpio_request(GPIO_FN_SDHICLK1, NULL);
1472 gpio_request(GPIO_FN_SDHID1_3, NULL);
1473 gpio_request(GPIO_FN_SDHID1_2, NULL);
1474 gpio_request(GPIO_FN_SDHID1_1, NULL);
1475 gpio_request(GPIO_FN_SDHID1_0, NULL);
1476#endif
1477 /* card detect pin for MMC slot (CN7) */ 1489 /* card detect pin for MMC slot (CN7) */
1478 gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL); 1490 gpio_request_one(41, GPIOF_IN, NULL);
1479
1480 /* enable SDHI2 */
1481 gpio_request(GPIO_FN_SDHICMD2, NULL);
1482 gpio_request(GPIO_FN_SDHICLK2, NULL);
1483 gpio_request(GPIO_FN_SDHID2_3, NULL);
1484 gpio_request(GPIO_FN_SDHID2_2, NULL);
1485 gpio_request(GPIO_FN_SDHID2_1, NULL);
1486 gpio_request(GPIO_FN_SDHID2_0, NULL);
1487 1491
1488 /* card detect pin for microSD slot (CN23) */ 1492 /* card detect pin for microSD slot (CN23) */
1489 gpio_request_one(GPIO_PORT162, GPIOF_IN, NULL); 1493 gpio_request_one(162, GPIOF_IN, NULL);
1490
1491 /* MMCIF */
1492 gpio_request(GPIO_FN_MMCD0_0, NULL);
1493 gpio_request(GPIO_FN_MMCD0_1, NULL);
1494 gpio_request(GPIO_FN_MMCD0_2, NULL);
1495 gpio_request(GPIO_FN_MMCD0_3, NULL);
1496 gpio_request(GPIO_FN_MMCD0_4, NULL);
1497 gpio_request(GPIO_FN_MMCD0_5, NULL);
1498 gpio_request(GPIO_FN_MMCD0_6, NULL);
1499 gpio_request(GPIO_FN_MMCD0_7, NULL);
1500 gpio_request(GPIO_FN_MMCCMD0, NULL);
1501 gpio_request(GPIO_FN_MMCCLK0, NULL);
1502 1494
1503 /* FLCTL */ 1495 /* FLCTL */
1504 gpio_request(GPIO_FN_D0_NAF0, NULL); 1496 gpio_request(GPIO_FN_D0_NAF0, NULL);
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c
index fec49ebc359a..a88f7f3594c7 100644
--- a/arch/arm/mach-shmobile/board-marzen.c
+++ b/arch/arm/mach-shmobile/board-marzen.c
@@ -25,8 +25,9 @@
25#include <linux/platform_device.h> 25#include <linux/platform_device.h>
26#include <linux/delay.h> 26#include <linux/delay.h>
27#include <linux/io.h> 27#include <linux/io.h>
28#include <linux/gpio.h> 28#include <linux/leds.h>
29#include <linux/dma-mapping.h> 29#include <linux/dma-mapping.h>
30#include <linux/pinctrl/machine.h>
30#include <linux/regulator/fixed.h> 31#include <linux/regulator/fixed.h>
31#include <linux/regulator/machine.h> 32#include <linux/regulator/machine.h>
32#include <linux/smsc911x.h> 33#include <linux/smsc911x.h>
@@ -168,12 +169,43 @@ static struct platform_device usb_phy_device = {
168 .num_resources = ARRAY_SIZE(usb_phy_resources), 169 .num_resources = ARRAY_SIZE(usb_phy_resources),
169}; 170};
170 171
172/* LEDS */
173static struct gpio_led marzen_leds[] = {
174 {
175 .name = "led2",
176 .gpio = 157,
177 .default_state = LEDS_GPIO_DEFSTATE_ON,
178 }, {
179 .name = "led3",
180 .gpio = 158,
181 .default_state = LEDS_GPIO_DEFSTATE_ON,
182 }, {
183 .name = "led4",
184 .gpio = 159,
185 .default_state = LEDS_GPIO_DEFSTATE_ON,
186 },
187};
188
189static struct gpio_led_platform_data marzen_leds_pdata = {
190 .leds = marzen_leds,
191 .num_leds = ARRAY_SIZE(marzen_leds),
192};
193
194static struct platform_device leds_device = {
195 .name = "leds-gpio",
196 .id = 0,
197 .dev = {
198 .platform_data = &marzen_leds_pdata,
199 },
200};
201
171static struct platform_device *marzen_devices[] __initdata = { 202static struct platform_device *marzen_devices[] __initdata = {
172 &eth_device, 203 &eth_device,
173 &sdhi0_device, 204 &sdhi0_device,
174 &thermal_device, 205 &thermal_device,
175 &hspi_device, 206 &hspi_device,
176 &usb_phy_device, 207 &usb_phy_device,
208 &leds_device,
177}; 209};
178 210
179/* USB */ 211/* USB */
@@ -327,6 +359,41 @@ void __init marzen_init_late(void)
327 ARRAY_SIZE(marzen_late_devices)); 359 ARRAY_SIZE(marzen_late_devices));
328} 360}
329 361
362static const struct pinctrl_map marzen_pinctrl_map[] = {
363 /* HSPI0 */
364 PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779",
365 "hspi0", "hspi0"),
366 /* SCIF2 (CN18: DEBUG0) */
367 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
368 "scif2_data_c", "scif2"),
369 /* SCIF4 (CN19: DEBUG1) */
370 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
371 "scif4_data", "scif4"),
372 /* SDHI0 */
373 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
374 "sdhi0_data4", "sdhi0"),
375 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
376 "sdhi0_ctrl", "sdhi0"),
377 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
378 "sdhi0_cd", "sdhi0"),
379 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
380 "sdhi0_wp", "sdhi0"),
381 /* SMSC */
382 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
383 "intc_irq1_b", "intc"),
384 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
385 "lbsc_ex_cs0", "lbsc"),
386 /* USB0 */
387 PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
388 "usb0", "usb0"),
389 /* USB1 */
390 PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
391 "usb1", "usb1"),
392 /* USB2 */
393 PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779",
394 "usb2", "usb2"),
395};
396
330static void __init marzen_init(void) 397static void __init marzen_init(void)
331{ 398{
332 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers, 399 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
@@ -334,44 +401,10 @@ static void __init marzen_init(void)
334 regulator_register_fixed(1, dummy_supplies, 401 regulator_register_fixed(1, dummy_supplies,
335 ARRAY_SIZE(dummy_supplies)); 402 ARRAY_SIZE(dummy_supplies));
336 403
404 pinctrl_register_mappings(marzen_pinctrl_map,
405 ARRAY_SIZE(marzen_pinctrl_map));
337 r8a7779_pinmux_init(); 406 r8a7779_pinmux_init();
338 407
339 /* SCIF2 (CN18: DEBUG0) */
340 gpio_request(GPIO_FN_TX2_C, NULL);
341 gpio_request(GPIO_FN_RX2_C, NULL);
342
343 /* SCIF4 (CN19: DEBUG1) */
344 gpio_request(GPIO_FN_TX4, NULL);
345 gpio_request(GPIO_FN_RX4, NULL);
346
347 /* LAN89218 */
348 gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
349 gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
350
351 /* SD0 (CN20) */
352 gpio_request(GPIO_FN_SD0_CLK, NULL);
353 gpio_request(GPIO_FN_SD0_CMD, NULL);
354 gpio_request(GPIO_FN_SD0_DAT0, NULL);
355 gpio_request(GPIO_FN_SD0_DAT1, NULL);
356 gpio_request(GPIO_FN_SD0_DAT2, NULL);
357 gpio_request(GPIO_FN_SD0_DAT3, NULL);
358 gpio_request(GPIO_FN_SD0_CD, NULL);
359 gpio_request(GPIO_FN_SD0_WP, NULL);
360
361 /* HSPI 0 */
362 gpio_request(GPIO_FN_HSPI_CLK0, NULL);
363 gpio_request(GPIO_FN_HSPI_CS0, NULL);
364 gpio_request(GPIO_FN_HSPI_TX0, NULL);
365 gpio_request(GPIO_FN_HSPI_RX0, NULL);
366
367 /* USB (CN21) */
368 gpio_request(GPIO_FN_USB_OVC0, NULL);
369 gpio_request(GPIO_FN_USB_OVC1, NULL);
370 gpio_request(GPIO_FN_USB_OVC2, NULL);
371
372 /* USB (CN22) */
373 gpio_request(GPIO_FN_USB_PENC2, NULL);
374
375 r8a7779_add_standard_devices(); 408 r8a7779_add_standard_devices();
376 platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices)); 409 platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
377} 410}
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/include/mach/r8a7740.h
index 5a879bbe145f..abdc4d4efa28 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7740.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7740.h
@@ -241,48 +241,9 @@ enum {
241 241
242 /* LCD0 */ 242 /* LCD0 */
243 GPIO_FN_LCDC0_SELECT, 243 GPIO_FN_LCDC0_SELECT,
244 GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
245 GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
246 GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
247 GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
248 GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
249 GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
250 GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
251
252 GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
253 GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
254
255 GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
256 GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
257
258 GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
259 GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
260 GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
261 GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
262
263 GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
264 GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
265 GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
266 GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
267 244
268 /* LCD1 */ 245 /* LCD1 */
269 GPIO_FN_LCDC1_SELECT, 246 GPIO_FN_LCDC1_SELECT,
270 GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
271 GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
272 GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
273 GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
274 GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
275 GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
276 GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
277 GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
278 GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
279 GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
280
281 GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
282 GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
283
284 GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
285 GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
286 247
287 /* RSPI */ 248 /* RSPI */
288 GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A, 249 GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
@@ -346,26 +307,6 @@ enum {
346 GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */ 307 GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
347 GPIO_FN_SIM_D_PORT199, 308 GPIO_FN_SIM_D_PORT199,
348 309
349 /* SDHI0 */
350 GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
351 GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
352 GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
353
354 /* SDHI1 */
355 GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
356 GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
357 GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
358
359 /* SDHI2 */
360 GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
361 GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
362
363 GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
364 GPIO_FN_SDHI2_WP_PORT25,
365
366 GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
367 GPIO_FN_SDHI2_CD_PORT202,
368
369 /* MSIOF2 */ 310 /* MSIOF2 */
370 GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK, 311 GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
371 GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1, 312 GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
@@ -417,21 +358,6 @@ enum {
417 GPIO_FN_MEMC_DREQ1, 358 GPIO_FN_MEMC_DREQ1,
418 GPIO_FN_MEMC_A0, 359 GPIO_FN_MEMC_A0,
419 360
420 /* MMC */
421 GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
422 GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
423 GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
424 GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
425 GPIO_FN_MMC0_CLK_PORT66,
426 GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
427
428 GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
429 GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
430 GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
431 GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
432 GPIO_FN_MMC1_CLK_PORT103,
433 GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
434
435 /* MSIOF0 */ 361 /* MSIOF0 */
436 GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2, 362 GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
437 GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD, 363 GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h
index af38750f38f7..945299ed1638 100644
--- a/arch/arm/mach-shmobile/include/mach/r8a7779.h
+++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h
@@ -4,327 +4,6 @@
4#include <linux/sh_clk.h> 4#include <linux/sh_clk.h>
5#include <linux/pm_domain.h> 5#include <linux/pm_domain.h>
6 6
7/* Pin Function Controller:
8 * GPIO_FN_xx - GPIO used to select pin function
9 * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU
10 */
11enum {
12 GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3,
13 GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7,
14 GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11,
15 GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15,
16 GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19,
17 GPIO_GP_0_20, GPIO_GP_0_21, GPIO_GP_0_22, GPIO_GP_0_23,
18 GPIO_GP_0_24, GPIO_GP_0_25, GPIO_GP_0_26, GPIO_GP_0_27,
19 GPIO_GP_0_28, GPIO_GP_0_29, GPIO_GP_0_30, GPIO_GP_0_31,
20
21 GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3,
22 GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7,
23 GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11,
24 GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15,
25 GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19,
26 GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23,
27 GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27,
28 GPIO_GP_1_28, GPIO_GP_1_29, GPIO_GP_1_30, GPIO_GP_1_31,
29
30 GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3,
31 GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7,
32 GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11,
33 GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15,
34 GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19,
35 GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23,
36 GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27,
37 GPIO_GP_2_28, GPIO_GP_2_29, GPIO_GP_2_30, GPIO_GP_2_31,
38
39 GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3,
40 GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7,
41 GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11,
42 GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15,
43 GPIO_GP_3_16, GPIO_GP_3_17, GPIO_GP_3_18, GPIO_GP_3_19,
44 GPIO_GP_3_20, GPIO_GP_3_21, GPIO_GP_3_22, GPIO_GP_3_23,
45 GPIO_GP_3_24, GPIO_GP_3_25, GPIO_GP_3_26, GPIO_GP_3_27,
46 GPIO_GP_3_28, GPIO_GP_3_29, GPIO_GP_3_30, GPIO_GP_3_31,
47
48 GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3,
49 GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7,
50 GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11,
51 GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15,
52 GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19,
53 GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23,
54 GPIO_GP_4_24, GPIO_GP_4_25, GPIO_GP_4_26, GPIO_GP_4_27,
55 GPIO_GP_4_28, GPIO_GP_4_29, GPIO_GP_4_30, GPIO_GP_4_31,
56
57 GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3,
58 GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7,
59 GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11,
60 GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, GPIO_GP_5_15,
61 GPIO_GP_5_16, GPIO_GP_5_17, GPIO_GP_5_18, GPIO_GP_5_19,
62 GPIO_GP_5_20, GPIO_GP_5_21, GPIO_GP_5_22, GPIO_GP_5_23,
63 GPIO_GP_5_24, GPIO_GP_5_25, GPIO_GP_5_26, GPIO_GP_5_27,
64 GPIO_GP_5_28, GPIO_GP_5_29, GPIO_GP_5_30, GPIO_GP_5_31,
65
66 GPIO_GP_6_0, GPIO_GP_6_1, GPIO_GP_6_2, GPIO_GP_6_3,
67 GPIO_GP_6_4, GPIO_GP_6_5, GPIO_GP_6_6, GPIO_GP_6_7,
68 GPIO_GP_6_8,
69
70 GPIO_FN_AVS1, GPIO_FN_AVS2, GPIO_FN_A17, GPIO_FN_A18,
71 GPIO_FN_A19,
72
73 /* IPSR0 */
74 GPIO_FN_USB_PENC2, GPIO_FN_SCK0, GPIO_FN_PWM1, GPIO_FN_PWMFSW0,
75 GPIO_FN_SCIF_CLK, GPIO_FN_TCLK0_C, GPIO_FN_BS, GPIO_FN_SD1_DAT2,
76 GPIO_FN_MMC0_D2, GPIO_FN_FD2, GPIO_FN_ATADIR0, GPIO_FN_SDSELF,
77 GPIO_FN_HCTS1, GPIO_FN_TX4_C, GPIO_FN_A0, GPIO_FN_SD1_DAT3,
78 GPIO_FN_MMC0_D3, GPIO_FN_FD3, GPIO_FN_A20, GPIO_FN_TX5_D,
79 GPIO_FN_HSPI_TX2_B, GPIO_FN_A21, GPIO_FN_SCK5_D, GPIO_FN_HSPI_CLK2_B,
80 GPIO_FN_A22, GPIO_FN_RX5_D, GPIO_FN_HSPI_RX2_B, GPIO_FN_VI1_R0,
81 GPIO_FN_A23, GPIO_FN_FCLE, GPIO_FN_HSPI_CLK2, GPIO_FN_VI1_R1,
82 GPIO_FN_A24, GPIO_FN_SD1_CD, GPIO_FN_MMC0_D4, GPIO_FN_FD4,
83 GPIO_FN_HSPI_CS2, GPIO_FN_VI1_R2, GPIO_FN_SSI_WS78_B, GPIO_FN_A25,
84 GPIO_FN_SD1_WP, GPIO_FN_MMC0_D5, GPIO_FN_FD5, GPIO_FN_HSPI_RX2,
85 GPIO_FN_VI1_R3, GPIO_FN_TX5_B, GPIO_FN_SSI_SDATA7_B, GPIO_FN_CTS0_B,
86 GPIO_FN_CLKOUT, GPIO_FN_TX3C_IRDA_TX_C, GPIO_FN_PWM0_B, GPIO_FN_CS0,
87 GPIO_FN_HSPI_CS2_B, GPIO_FN_CS1_A26, GPIO_FN_HSPI_TX2,
88 GPIO_FN_SDSELF_B, GPIO_FN_RD_WR, GPIO_FN_FWE, GPIO_FN_ATAG0,
89 GPIO_FN_VI1_R7, GPIO_FN_HRTS1, GPIO_FN_RX4_C,
90
91 /* IPSR1 */
92 GPIO_FN_EX_CS0, GPIO_FN_RX3_C_IRDA_RX_C, GPIO_FN_MMC0_D6,
93 GPIO_FN_FD6, GPIO_FN_EX_CS1, GPIO_FN_MMC0_D7, GPIO_FN_FD7,
94 GPIO_FN_EX_CS2, GPIO_FN_SD1_CLK, GPIO_FN_MMC0_CLK, GPIO_FN_FALE,
95 GPIO_FN_ATACS00, GPIO_FN_EX_CS3, GPIO_FN_SD1_CMD, GPIO_FN_MMC0_CMD,
96 GPIO_FN_FRE, GPIO_FN_ATACS10, GPIO_FN_VI1_R4, GPIO_FN_RX5_B,
97 GPIO_FN_HSCK1, GPIO_FN_SSI_SDATA8_B, GPIO_FN_RTS0_B_TANS_B,
98 GPIO_FN_SSI_SDATA9, GPIO_FN_EX_CS4, GPIO_FN_SD1_DAT0, GPIO_FN_MMC0_D0,
99 GPIO_FN_FD0, GPIO_FN_ATARD0, GPIO_FN_VI1_R5, GPIO_FN_SCK5_B,
100 GPIO_FN_HTX1, GPIO_FN_TX2_E, GPIO_FN_TX0_B, GPIO_FN_SSI_SCK9,
101 GPIO_FN_EX_CS5, GPIO_FN_SD1_DAT1, GPIO_FN_MMC0_D1, GPIO_FN_FD1,
102 GPIO_FN_ATAWR0, GPIO_FN_VI1_R6, GPIO_FN_HRX1, GPIO_FN_RX2_E,
103 GPIO_FN_RX0_B, GPIO_FN_SSI_WS9, GPIO_FN_MLB_CLK, GPIO_FN_PWM2,
104 GPIO_FN_SCK4, GPIO_FN_MLB_SIG, GPIO_FN_PWM3, GPIO_FN_TX4,
105 GPIO_FN_MLB_DAT, GPIO_FN_PWM4, GPIO_FN_RX4, GPIO_FN_HTX0,
106 GPIO_FN_TX1, GPIO_FN_SDATA, GPIO_FN_CTS0_C, GPIO_FN_SUB_TCK,
107 GPIO_FN_CC5_STATE2, GPIO_FN_CC5_STATE10, GPIO_FN_CC5_STATE18,
108 GPIO_FN_CC5_STATE26, GPIO_FN_CC5_STATE34,
109
110 /* IPSR2 */
111 GPIO_FN_HRX0, GPIO_FN_RX1, GPIO_FN_SCKZ, GPIO_FN_RTS0_C_TANS_C,
112 GPIO_FN_SUB_TDI, GPIO_FN_CC5_STATE3, GPIO_FN_CC5_STATE11,
113 GPIO_FN_CC5_STATE19, GPIO_FN_CC5_STATE27, GPIO_FN_CC5_STATE35,
114 GPIO_FN_HSCK0, GPIO_FN_SCK1, GPIO_FN_MTS, GPIO_FN_PWM5,
115 GPIO_FN_SCK0_C, GPIO_FN_SSI_SDATA9_B, GPIO_FN_SUB_TDO,
116 GPIO_FN_CC5_STATE0, GPIO_FN_CC5_STATE8, GPIO_FN_CC5_STATE16,
117 GPIO_FN_CC5_STATE24, GPIO_FN_CC5_STATE32, GPIO_FN_HCTS0, GPIO_FN_CTS1,
118 GPIO_FN_STM, GPIO_FN_PWM0_D, GPIO_FN_RX0_C, GPIO_FN_SCIF_CLK_C,
119 GPIO_FN_SUB_TRST, GPIO_FN_TCLK1_B, GPIO_FN_CC5_OSCOUT, GPIO_FN_HRTS0,
120 GPIO_FN_RTS1_TANS, GPIO_FN_MDATA, GPIO_FN_TX0_C, GPIO_FN_SUB_TMS,
121 GPIO_FN_CC5_STATE1, GPIO_FN_CC5_STATE9, GPIO_FN_CC5_STATE17,
122 GPIO_FN_CC5_STATE25, GPIO_FN_CC5_STATE33, GPIO_FN_DU0_DR0,
123 GPIO_FN_LCDOUT0, GPIO_FN_DREQ0, GPIO_FN_GPS_CLK_B, GPIO_FN_AUDATA0,
124 GPIO_FN_TX5_C, GPIO_FN_DU0_DR1, GPIO_FN_LCDOUT1, GPIO_FN_DACK0,
125 GPIO_FN_DRACK0, GPIO_FN_GPS_SIGN_B, GPIO_FN_AUDATA1, GPIO_FN_RX5_C,
126 GPIO_FN_DU0_DR2, GPIO_FN_LCDOUT2, GPIO_FN_DU0_DR3, GPIO_FN_LCDOUT3,
127 GPIO_FN_DU0_DR4, GPIO_FN_LCDOUT4, GPIO_FN_DU0_DR5, GPIO_FN_LCDOUT5,
128 GPIO_FN_DU0_DR6, GPIO_FN_LCDOUT6, GPIO_FN_DU0_DR7, GPIO_FN_LCDOUT7,
129 GPIO_FN_DU0_DG0, GPIO_FN_LCDOUT8, GPIO_FN_DREQ1, GPIO_FN_SCL2,
130 GPIO_FN_AUDATA2,
131
132 /* IPSR3 */
133 GPIO_FN_DU0_DG1, GPIO_FN_LCDOUT9, GPIO_FN_DACK1, GPIO_FN_SDA2,
134 GPIO_FN_AUDATA3, GPIO_FN_DU0_DG2, GPIO_FN_LCDOUT10, GPIO_FN_DU0_DG3,
135 GPIO_FN_LCDOUT11, GPIO_FN_DU0_DG4, GPIO_FN_LCDOUT12, GPIO_FN_DU0_DG5,
136 GPIO_FN_LCDOUT13, GPIO_FN_DU0_DG6, GPIO_FN_LCDOUT14, GPIO_FN_DU0_DG7,
137 GPIO_FN_LCDOUT15, GPIO_FN_DU0_DB0, GPIO_FN_LCDOUT16, GPIO_FN_EX_WAIT1,
138 GPIO_FN_SCL1, GPIO_FN_TCLK1, GPIO_FN_AUDATA4, GPIO_FN_DU0_DB1,
139 GPIO_FN_LCDOUT17, GPIO_FN_EX_WAIT2, GPIO_FN_SDA1, GPIO_FN_GPS_MAG_B,
140 GPIO_FN_AUDATA5, GPIO_FN_SCK5_C, GPIO_FN_DU0_DB2, GPIO_FN_LCDOUT18,
141 GPIO_FN_DU0_DB3, GPIO_FN_LCDOUT19, GPIO_FN_DU0_DB4, GPIO_FN_LCDOUT20,
142 GPIO_FN_DU0_DB5, GPIO_FN_LCDOUT21, GPIO_FN_DU0_DB6, GPIO_FN_LCDOUT22,
143 GPIO_FN_DU0_DB7, GPIO_FN_LCDOUT23, GPIO_FN_DU0_DOTCLKIN,
144 GPIO_FN_QSTVA_QVS, GPIO_FN_TX3_D_IRDA_TX_D, GPIO_FN_SCL3_B,
145 GPIO_FN_DU0_DOTCLKOUT0, GPIO_FN_QCLK, GPIO_FN_DU0_DOTCLKOUT1,
146 GPIO_FN_QSTVB_QVE, GPIO_FN_RX3_D_IRDA_RX_D, GPIO_FN_SDA3_B,
147 GPIO_FN_SDA2_C, GPIO_FN_DACK0_B, GPIO_FN_DRACK0_B,
148 GPIO_FN_DU0_EXHSYNC_DU0_HSYNC, GPIO_FN_QSTH_QHS,
149 GPIO_FN_DU0_EXVSYNC_DU0_VSYNC, GPIO_FN_QSTB_QHE,
150 GPIO_FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, GPIO_FN_QCPV_QDE,
151 GPIO_FN_CAN1_TX, GPIO_FN_TX2_C, GPIO_FN_SCL2_C, GPIO_FN_REMOCON,
152
153 /* IPSR4 */
154 GPIO_FN_DU0_DISP, GPIO_FN_QPOLA, GPIO_FN_CAN_CLK_C, GPIO_FN_SCK2_C,
155 GPIO_FN_DU0_CDE, GPIO_FN_QPOLB, GPIO_FN_CAN1_RX, GPIO_FN_RX2_C,
156 GPIO_FN_DREQ0_B, GPIO_FN_SSI_SCK78_B, GPIO_FN_SCK0_B, GPIO_FN_DU1_DR0,
157 GPIO_FN_VI2_DATA0_VI2_B0, GPIO_FN_PWM6, GPIO_FN_SD3_CLK,
158 GPIO_FN_TX3_E_IRDA_TX_E, GPIO_FN_AUDCK, GPIO_FN_PWMFSW0_B,
159 GPIO_FN_DU1_DR1, GPIO_FN_VI2_DATA1_VI2_B1, GPIO_FN_PWM0,
160 GPIO_FN_SD3_CMD, GPIO_FN_RX3_E_IRDA_RX_E, GPIO_FN_AUDSYNC,
161 GPIO_FN_CTS0_D, GPIO_FN_DU1_DR2, GPIO_FN_VI2_G0, GPIO_FN_DU1_DR3,
162 GPIO_FN_VI2_G1, GPIO_FN_DU1_DR4, GPIO_FN_VI2_G2, GPIO_FN_DU1_DR5,
163 GPIO_FN_VI2_G3, GPIO_FN_DU1_DR6, GPIO_FN_VI2_G4, GPIO_FN_DU1_DR7,
164 GPIO_FN_VI2_G5, GPIO_FN_DU1_DG0, GPIO_FN_VI2_DATA2_VI2_B2,
165 GPIO_FN_SCL1_B, GPIO_FN_SD3_DAT2, GPIO_FN_SCK3_E, GPIO_FN_AUDATA6,
166 GPIO_FN_TX0_D, GPIO_FN_DU1_DG1, GPIO_FN_VI2_DATA3_VI2_B3,
167 GPIO_FN_SDA1_B, GPIO_FN_SD3_DAT3, GPIO_FN_SCK5, GPIO_FN_AUDATA7,
168 GPIO_FN_RX0_D, GPIO_FN_DU1_DG2, GPIO_FN_VI2_G6, GPIO_FN_DU1_DG3,
169 GPIO_FN_VI2_G7, GPIO_FN_DU1_DG4, GPIO_FN_VI2_R0, GPIO_FN_DU1_DG5,
170 GPIO_FN_VI2_R1, GPIO_FN_DU1_DG6, GPIO_FN_VI2_R2, GPIO_FN_DU1_DG7,
171 GPIO_FN_VI2_R3, GPIO_FN_DU1_DB0, GPIO_FN_VI2_DATA4_VI2_B4,
172 GPIO_FN_SCL2_B, GPIO_FN_SD3_DAT0, GPIO_FN_TX5, GPIO_FN_SCK0_D,
173
174 /* IPSR5 */
175 GPIO_FN_DU1_DB1, GPIO_FN_VI2_DATA5_VI2_B5, GPIO_FN_SDA2_B,
176 GPIO_FN_SD3_DAT1, GPIO_FN_RX5, GPIO_FN_RTS0_D_TANS_D,
177 GPIO_FN_DU1_DB2, GPIO_FN_VI2_R4, GPIO_FN_DU1_DB3, GPIO_FN_VI2_R5,
178 GPIO_FN_DU1_DB4, GPIO_FN_VI2_R6, GPIO_FN_DU1_DB5, GPIO_FN_VI2_R7,
179 GPIO_FN_DU1_DB6, GPIO_FN_SCL2_D, GPIO_FN_DU1_DB7, GPIO_FN_SDA2_D,
180 GPIO_FN_DU1_DOTCLKIN, GPIO_FN_VI2_CLKENB, GPIO_FN_HSPI_CS1,
181 GPIO_FN_SCL1_D, GPIO_FN_DU1_DOTCLKOUT, GPIO_FN_VI2_FIELD,
182 GPIO_FN_SDA1_D, GPIO_FN_DU1_EXHSYNC_DU1_HSYNC, GPIO_FN_VI2_HSYNC,
183 GPIO_FN_VI3_HSYNC, GPIO_FN_DU1_EXVSYNC_DU1_VSYNC, GPIO_FN_VI2_VSYNC,
184 GPIO_FN_VI3_VSYNC, GPIO_FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
185 GPIO_FN_VI2_CLK, GPIO_FN_TX3_B_IRDA_TX_B, GPIO_FN_SD3_CD,
186 GPIO_FN_HSPI_TX1, GPIO_FN_VI1_CLKENB, GPIO_FN_VI3_CLKENB,
187 GPIO_FN_AUDIO_CLKC, GPIO_FN_TX2_D, GPIO_FN_SPEEDIN,
188 GPIO_FN_GPS_SIGN_D, GPIO_FN_DU1_DISP, GPIO_FN_VI2_DATA6_VI2_B6,
189 GPIO_FN_TCLK0, GPIO_FN_QSTVA_B_QVS_B, GPIO_FN_HSPI_CLK1,
190 GPIO_FN_SCK2_D, GPIO_FN_AUDIO_CLKOUT_B, GPIO_FN_GPS_MAG_D,
191 GPIO_FN_DU1_CDE, GPIO_FN_VI2_DATA7_VI2_B7, GPIO_FN_RX3_B_IRDA_RX_B,
192 GPIO_FN_SD3_WP, GPIO_FN_HSPI_RX1, GPIO_FN_VI1_FIELD, GPIO_FN_VI3_FIELD,
193 GPIO_FN_AUDIO_CLKOUT, GPIO_FN_RX2_D, GPIO_FN_GPS_CLK_C,
194 GPIO_FN_GPS_CLK_D, GPIO_FN_AUDIO_CLKA, GPIO_FN_CAN_TXCLK,
195 GPIO_FN_AUDIO_CLKB, GPIO_FN_USB_OVC2, GPIO_FN_CAN_DEBUGOUT0,
196 GPIO_FN_MOUT0,
197
198 /* IPSR6 */
199 GPIO_FN_SSI_SCK0129, GPIO_FN_CAN_DEBUGOUT1, GPIO_FN_MOUT1,
200 GPIO_FN_SSI_WS0129, GPIO_FN_CAN_DEBUGOUT2, GPIO_FN_MOUT2,
201 GPIO_FN_SSI_SDATA0, GPIO_FN_CAN_DEBUGOUT3, GPIO_FN_MOUT5,
202 GPIO_FN_SSI_SDATA1, GPIO_FN_CAN_DEBUGOUT4, GPIO_FN_MOUT6,
203 GPIO_FN_SSI_SDATA2, GPIO_FN_CAN_DEBUGOUT5, GPIO_FN_SSI_SCK34,
204 GPIO_FN_CAN_DEBUGOUT6, GPIO_FN_CAN0_TX_B, GPIO_FN_IERX,
205 GPIO_FN_SSI_SCK9_C, GPIO_FN_SSI_WS34, GPIO_FN_CAN_DEBUGOUT7,
206 GPIO_FN_CAN0_RX_B, GPIO_FN_IETX, GPIO_FN_SSI_WS9_C,
207 GPIO_FN_SSI_SDATA3, GPIO_FN_PWM0_C, GPIO_FN_CAN_DEBUGOUT8,
208 GPIO_FN_CAN_CLK_B, GPIO_FN_IECLK, GPIO_FN_SCIF_CLK_B, GPIO_FN_TCLK0_B,
209 GPIO_FN_SSI_SDATA4, GPIO_FN_CAN_DEBUGOUT9, GPIO_FN_SSI_SDATA9_C,
210 GPIO_FN_SSI_SCK5, GPIO_FN_ADICLK, GPIO_FN_CAN_DEBUGOUT10,
211 GPIO_FN_SCK3, GPIO_FN_TCLK0_D, GPIO_FN_SSI_WS5, GPIO_FN_ADICS_SAMP,
212 GPIO_FN_CAN_DEBUGOUT11, GPIO_FN_TX3_IRDA_TX, GPIO_FN_SSI_SDATA5,
213 GPIO_FN_ADIDATA, GPIO_FN_CAN_DEBUGOUT12, GPIO_FN_RX3_IRDA_RX,
214 GPIO_FN_SSI_SCK6, GPIO_FN_ADICHS0, GPIO_FN_CAN0_TX, GPIO_FN_IERX_B,
215
216 /* IPSR7 */
217 GPIO_FN_SSI_WS6, GPIO_FN_ADICHS1, GPIO_FN_CAN0_RX, GPIO_FN_IETX_B,
218 GPIO_FN_SSI_SDATA6, GPIO_FN_ADICHS2, GPIO_FN_CAN_CLK, GPIO_FN_IECLK_B,
219 GPIO_FN_SSI_SCK78, GPIO_FN_CAN_DEBUGOUT13, GPIO_FN_IRQ0_B,
220 GPIO_FN_SSI_SCK9_B, GPIO_FN_HSPI_CLK1_C, GPIO_FN_SSI_WS78,
221 GPIO_FN_CAN_DEBUGOUT14, GPIO_FN_IRQ1_B, GPIO_FN_SSI_WS9_B,
222 GPIO_FN_HSPI_CS1_C, GPIO_FN_SSI_SDATA7, GPIO_FN_CAN_DEBUGOUT15,
223 GPIO_FN_IRQ2_B, GPIO_FN_TCLK1_C, GPIO_FN_HSPI_TX1_C,
224 GPIO_FN_SSI_SDATA8, GPIO_FN_VSP, GPIO_FN_IRQ3_B, GPIO_FN_HSPI_RX1_C,
225 GPIO_FN_SD0_CLK, GPIO_FN_ATACS01, GPIO_FN_SCK1_B, GPIO_FN_SD0_CMD,
226 GPIO_FN_ATACS11, GPIO_FN_TX1_B, GPIO_FN_CC5_TDO, GPIO_FN_SD0_DAT0,
227 GPIO_FN_ATADIR1, GPIO_FN_RX1_B, GPIO_FN_CC5_TRST, GPIO_FN_SD0_DAT1,
228 GPIO_FN_ATAG1, GPIO_FN_SCK2_B, GPIO_FN_CC5_TMS, GPIO_FN_SD0_DAT2,
229 GPIO_FN_ATARD1, GPIO_FN_TX2_B, GPIO_FN_CC5_TCK, GPIO_FN_SD0_DAT3,
230 GPIO_FN_ATAWR1, GPIO_FN_RX2_B, GPIO_FN_CC5_TDI, GPIO_FN_SD0_CD,
231 GPIO_FN_DREQ2, GPIO_FN_RTS1_B_TANS_B, GPIO_FN_SD0_WP, GPIO_FN_DACK2,
232 GPIO_FN_CTS1_B,
233
234 /* IPSR8 */
235 GPIO_FN_HSPI_CLK0, GPIO_FN_CTS0, GPIO_FN_USB_OVC0, GPIO_FN_AD_CLK,
236 GPIO_FN_CC5_STATE4, GPIO_FN_CC5_STATE12, GPIO_FN_CC5_STATE20,
237 GPIO_FN_CC5_STATE28, GPIO_FN_CC5_STATE36, GPIO_FN_HSPI_CS0,
238 GPIO_FN_RTS0_TANS, GPIO_FN_USB_OVC1, GPIO_FN_AD_DI,
239 GPIO_FN_CC5_STATE5, GPIO_FN_CC5_STATE13, GPIO_FN_CC5_STATE21,
240 GPIO_FN_CC5_STATE29, GPIO_FN_CC5_STATE37, GPIO_FN_HSPI_TX0,
241 GPIO_FN_TX0, GPIO_FN_CAN_DEBUG_HW_TRIGGER, GPIO_FN_AD_DO,
242 GPIO_FN_CC5_STATE6, GPIO_FN_CC5_STATE14, GPIO_FN_CC5_STATE22,
243 GPIO_FN_CC5_STATE30, GPIO_FN_CC5_STATE38, GPIO_FN_HSPI_RX0,
244 GPIO_FN_RX0, GPIO_FN_CAN_STEP0, GPIO_FN_AD_NCS, GPIO_FN_CC5_STATE7,
245 GPIO_FN_CC5_STATE15, GPIO_FN_CC5_STATE23, GPIO_FN_CC5_STATE31,
246 GPIO_FN_CC5_STATE39, GPIO_FN_FMCLK, GPIO_FN_RDS_CLK, GPIO_FN_PCMOE,
247 GPIO_FN_BPFCLK, GPIO_FN_PCMWE, GPIO_FN_FMIN, GPIO_FN_RDS_DATA,
248 GPIO_FN_VI0_CLK, GPIO_FN_MMC1_CLK, GPIO_FN_VI0_CLKENB, GPIO_FN_TX1_C,
249 GPIO_FN_HTX1_B, GPIO_FN_MT1_SYNC, GPIO_FN_VI0_FIELD, GPIO_FN_RX1_C,
250 GPIO_FN_HRX1_B, GPIO_FN_VI0_HSYNC, GPIO_FN_VI0_DATA0_B_VI0_B0_B,
251 GPIO_FN_CTS1_C, GPIO_FN_TX4_D, GPIO_FN_MMC1_CMD, GPIO_FN_HSCK1_B,
252 GPIO_FN_VI0_VSYNC, GPIO_FN_VI0_DATA1_B_VI0_B1_B,
253 GPIO_FN_RTS1_C_TANS_C, GPIO_FN_RX4_D, GPIO_FN_PWMFSW0_C,
254
255 /* IPSR9 */
256 GPIO_FN_VI0_DATA0_VI0_B0, GPIO_FN_HRTS1_B, GPIO_FN_MT1_VCXO,
257 GPIO_FN_VI0_DATA1_VI0_B1, GPIO_FN_HCTS1_B, GPIO_FN_MT1_PWM,
258 GPIO_FN_VI0_DATA2_VI0_B2, GPIO_FN_MMC1_D0, GPIO_FN_VI0_DATA3_VI0_B3,
259 GPIO_FN_MMC1_D1, GPIO_FN_VI0_DATA4_VI0_B4, GPIO_FN_MMC1_D2,
260 GPIO_FN_VI0_DATA5_VI0_B5, GPIO_FN_MMC1_D3, GPIO_FN_VI0_DATA6_VI0_B6,
261 GPIO_FN_MMC1_D4, GPIO_FN_ARM_TRACEDATA_0, GPIO_FN_VI0_DATA7_VI0_B7,
262 GPIO_FN_MMC1_D5, GPIO_FN_ARM_TRACEDATA_1, GPIO_FN_VI0_G0,
263 GPIO_FN_SSI_SCK78_C, GPIO_FN_IRQ0, GPIO_FN_ARM_TRACEDATA_2,
264 GPIO_FN_VI0_G1, GPIO_FN_SSI_WS78_C, GPIO_FN_IRQ1,
265 GPIO_FN_ARM_TRACEDATA_3, GPIO_FN_VI0_G2, GPIO_FN_ETH_TXD1,
266 GPIO_FN_MMC1_D6, GPIO_FN_ARM_TRACEDATA_4, GPIO_FN_TS_SPSYNC0,
267 GPIO_FN_VI0_G3, GPIO_FN_ETH_CRS_DV, GPIO_FN_MMC1_D7,
268 GPIO_FN_ARM_TRACEDATA_5, GPIO_FN_TS_SDAT0, GPIO_FN_VI0_G4,
269 GPIO_FN_ETH_TX_EN, GPIO_FN_SD2_DAT0_B, GPIO_FN_ARM_TRACEDATA_6,
270 GPIO_FN_VI0_G5, GPIO_FN_ETH_RX_ER, GPIO_FN_SD2_DAT1_B,
271 GPIO_FN_ARM_TRACEDATA_7, GPIO_FN_VI0_G6, GPIO_FN_ETH_RXD0,
272 GPIO_FN_SD2_DAT2_B, GPIO_FN_ARM_TRACEDATA_8, GPIO_FN_VI0_G7,
273 GPIO_FN_ETH_RXD1, GPIO_FN_SD2_DAT3_B, GPIO_FN_ARM_TRACEDATA_9,
274
275 /* IPSR10 */
276 GPIO_FN_VI0_R0, GPIO_FN_SSI_SDATA7_C, GPIO_FN_SCK1_C, GPIO_FN_DREQ1_B,
277 GPIO_FN_ARM_TRACEDATA_10, GPIO_FN_DREQ0_C, GPIO_FN_VI0_R1,
278 GPIO_FN_SSI_SDATA8_C, GPIO_FN_DACK1_B, GPIO_FN_ARM_TRACEDATA_11,
279 GPIO_FN_DACK0_C, GPIO_FN_DRACK0_C, GPIO_FN_VI0_R2, GPIO_FN_ETH_LINK,
280 GPIO_FN_SD2_CLK_B, GPIO_FN_IRQ2, GPIO_FN_ARM_TRACEDATA_12,
281 GPIO_FN_VI0_R3, GPIO_FN_ETH_MAGIC, GPIO_FN_SD2_CMD_B, GPIO_FN_IRQ3,
282 GPIO_FN_ARM_TRACEDATA_13, GPIO_FN_VI0_R4, GPIO_FN_ETH_REFCLK,
283 GPIO_FN_SD2_CD_B, GPIO_FN_HSPI_CLK1_B, GPIO_FN_ARM_TRACEDATA_14,
284 GPIO_FN_MT1_CLK, GPIO_FN_TS_SCK0, GPIO_FN_VI0_R5, GPIO_FN_ETH_TXD0,
285 GPIO_FN_SD2_WP_B, GPIO_FN_HSPI_CS1_B, GPIO_FN_ARM_TRACEDATA_15,
286 GPIO_FN_MT1_D, GPIO_FN_TS_SDEN0, GPIO_FN_VI0_R6, GPIO_FN_ETH_MDC,
287 GPIO_FN_DREQ2_C, GPIO_FN_HSPI_TX1_B, GPIO_FN_TRACECLK,
288 GPIO_FN_MT1_BEN, GPIO_FN_PWMFSW0_D, GPIO_FN_VI0_R7, GPIO_FN_ETH_MDIO,
289 GPIO_FN_DACK2_C, GPIO_FN_HSPI_RX1_B, GPIO_FN_SCIF_CLK_D,
290 GPIO_FN_TRACECTL, GPIO_FN_MT1_PEN, GPIO_FN_VI1_CLK, GPIO_FN_SIM_D,
291 GPIO_FN_SDA3, GPIO_FN_VI1_HSYNC, GPIO_FN_VI3_CLK, GPIO_FN_SSI_SCK4,
292 GPIO_FN_GPS_SIGN_C, GPIO_FN_PWMFSW0_E, GPIO_FN_VI1_VSYNC,
293 GPIO_FN_AUDIO_CLKOUT_C, GPIO_FN_SSI_WS4, GPIO_FN_SIM_CLK,
294 GPIO_FN_GPS_MAG_C, GPIO_FN_SPV_TRST, GPIO_FN_SCL3,
295
296 /* IPSR11 */
297 GPIO_FN_VI1_DATA0_VI1_B0, GPIO_FN_SD2_DAT0, GPIO_FN_SIM_RST,
298 GPIO_FN_SPV_TCK, GPIO_FN_ADICLK_B, GPIO_FN_VI1_DATA1_VI1_B1,
299 GPIO_FN_SD2_DAT1, GPIO_FN_MT0_CLK, GPIO_FN_SPV_TMS,
300 GPIO_FN_ADICS_B_SAMP_B, GPIO_FN_VI1_DATA2_VI1_B2, GPIO_FN_SD2_DAT2,
301 GPIO_FN_MT0_D, GPIO_FN_SPVTDI, GPIO_FN_ADIDATA_B,
302 GPIO_FN_VI1_DATA3_VI1_B3, GPIO_FN_SD2_DAT3, GPIO_FN_MT0_BEN,
303 GPIO_FN_SPV_TDO, GPIO_FN_ADICHS0_B, GPIO_FN_VI1_DATA4_VI1_B4,
304 GPIO_FN_SD2_CLK, GPIO_FN_MT0_PEN, GPIO_FN_SPA_TRST,
305 GPIO_FN_HSPI_CLK1_D, GPIO_FN_ADICHS1_B, GPIO_FN_VI1_DATA5_VI1_B5,
306 GPIO_FN_SD2_CMD, GPIO_FN_MT0_SYNC, GPIO_FN_SPA_TCK,
307 GPIO_FN_HSPI_CS1_D, GPIO_FN_ADICHS2_B, GPIO_FN_VI1_DATA6_VI1_B6,
308 GPIO_FN_SD2_CD, GPIO_FN_MT0_VCXO, GPIO_FN_SPA_TMS, GPIO_FN_HSPI_TX1_D,
309 GPIO_FN_VI1_DATA7_VI1_B7, GPIO_FN_SD2_WP, GPIO_FN_MT0_PWM,
310 GPIO_FN_SPA_TDI, GPIO_FN_HSPI_RX1_D, GPIO_FN_VI1_G0, GPIO_FN_VI3_DATA0,
311 GPIO_FN_DU1_DOTCLKOUT1, GPIO_FN_TS_SCK1, GPIO_FN_DREQ2_B, GPIO_FN_TX2,
312 GPIO_FN_SPA_TDO, GPIO_FN_HCTS0_B, GPIO_FN_VI1_G1, GPIO_FN_VI3_DATA1,
313 GPIO_FN_SSI_SCK1, GPIO_FN_TS_SDEN1, GPIO_FN_DACK2_B, GPIO_FN_RX2,
314 GPIO_FN_HRTS0_B,
315
316 /* IPSR12 */
317 GPIO_FN_VI1_G2, GPIO_FN_VI3_DATA2, GPIO_FN_SSI_WS1, GPIO_FN_TS_SPSYNC1,
318 GPIO_FN_SCK2, GPIO_FN_HSCK0_B, GPIO_FN_VI1_G3, GPIO_FN_VI3_DATA3,
319 GPIO_FN_SSI_SCK2, GPIO_FN_TS_SDAT1, GPIO_FN_SCL1_C, GPIO_FN_HTX0_B,
320 GPIO_FN_VI1_G4, GPIO_FN_VI3_DATA4, GPIO_FN_SSI_WS2, GPIO_FN_SDA1_C,
321 GPIO_FN_SIM_RST_B, GPIO_FN_HRX0_B, GPIO_FN_VI1_G5, GPIO_FN_VI3_DATA5,
322 GPIO_FN_GPS_CLK, GPIO_FN_FSE, GPIO_FN_TX4_B, GPIO_FN_SIM_D_B,
323 GPIO_FN_VI1_G6, GPIO_FN_VI3_DATA6, GPIO_FN_GPS_SIGN, GPIO_FN_FRB,
324 GPIO_FN_RX4_B, GPIO_FN_SIM_CLK_B, GPIO_FN_VI1_G7, GPIO_FN_VI3_DATA7,
325 GPIO_FN_GPS_MAG, GPIO_FN_FCE, GPIO_FN_SCK4_B,
326};
327
328struct platform_device; 7struct platform_device;
329 8
330struct r8a7779_pm_ch { 9struct r8a7779_pm_ch {
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index f0ea60d6648a..fd7cba024c39 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -294,21 +294,6 @@ enum {
294 GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14, 294 GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14,
295 GPIO_FN_D15_NAF15, 295 GPIO_FN_D15_NAF15,
296 296
297 /*
298 * MMCIF(1) (PORT 84, 85, 86, 87, 88, 89,
299 * 90, 91, 92, 99)
300 */
301 GPIO_FN_MMCD0_0, GPIO_FN_MMCD0_1, GPIO_FN_MMCD0_2,
302 GPIO_FN_MMCD0_3, GPIO_FN_MMCD0_4, GPIO_FN_MMCD0_5,
303 GPIO_FN_MMCD0_6, GPIO_FN_MMCD0_7,
304 GPIO_FN_MMCCMD0, GPIO_FN_MMCCLK0,
305
306 /* MMCIF(2) (PORT 54, 55, 56, 57, 58, 59, 60, 61, 66, 67) */
307 GPIO_FN_MMCD1_0, GPIO_FN_MMCD1_1, GPIO_FN_MMCD1_2,
308 GPIO_FN_MMCD1_3, GPIO_FN_MMCD1_4, GPIO_FN_MMCD1_5,
309 GPIO_FN_MMCD1_6, GPIO_FN_MMCD1_7,
310 GPIO_FN_MMCCLK1, GPIO_FN_MMCCMD1,
311
312 /* SPU2 (PORT 65) */ 297 /* SPU2 (PORT 65) */
313 GPIO_FN_VINT_I, 298 GPIO_FN_VINT_I,
314 299
@@ -416,20 +401,6 @@ enum {
416 /* HDMI (PORT 169, 170) */ 401 /* HDMI (PORT 169, 170) */
417 GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC, 402 GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC,
418 403
419 /* SDHI0 (PORT 171, 172, 173, 174, 175, 176, 177, 178) */
420 GPIO_FN_SDHICLK0, GPIO_FN_SDHICD0,
421 GPIO_FN_SDHICMD0, GPIO_FN_SDHIWP0,
422 GPIO_FN_SDHID0_0, GPIO_FN_SDHID0_1,
423 GPIO_FN_SDHID0_2, GPIO_FN_SDHID0_3,
424
425 /* SDHI1 (PORT 179, 180, 181, 182, 183, 184) */
426 GPIO_FN_SDHICLK1, GPIO_FN_SDHICMD1, GPIO_FN_SDHID1_0,
427 GPIO_FN_SDHID1_1, GPIO_FN_SDHID1_2, GPIO_FN_SDHID1_3,
428
429 /* SDHI2 (PORT 185, 186, 187, 188, 189, 190) */
430 GPIO_FN_SDHICLK2, GPIO_FN_SDHICMD2, GPIO_FN_SDHID2_0,
431 GPIO_FN_SDHID2_1, GPIO_FN_SDHID2_2, GPIO_FN_SDHID2_3,
432
433 /* SDENC see MSEL4CR 19 */ 404 /* SDENC see MSEL4CR 19 */
434 GPIO_FN_SDENC_CPG, 405 GPIO_FN_SDENC_CPG,
435 GPIO_FN_SDENC_DV_CLKI, 406 GPIO_FN_SDENC_DV_CLKI,
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index 936da1b4a9c5..eb7a4320d487 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -94,8 +94,7 @@ enum {
94 GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309, 94 GPIO_PORT305, GPIO_PORT306, GPIO_PORT307, GPIO_PORT308, GPIO_PORT309,
95 95
96 /* Table 25-1 (Function 0-7) */ 96 /* Table 25-1 (Function 0-7) */
97 GPIO_FN_VBUS_0, 97 GPIO_FN_GPI0 = 310,
98 GPIO_FN_GPI0,
99 GPIO_FN_GPI1, 98 GPIO_FN_GPI1,
100 GPIO_FN_GPI2, 99 GPIO_FN_GPI2,
101 GPIO_FN_GPI3, 100 GPIO_FN_GPI3,
@@ -103,15 +102,11 @@ enum {
103 GPIO_FN_GPI5, 102 GPIO_FN_GPI5,
104 GPIO_FN_GPI6, 103 GPIO_FN_GPI6,
105 GPIO_FN_GPI7, 104 GPIO_FN_GPI7,
106 GPIO_FN_SCIFA7_RXD,
107 GPIO_FN_SCIFA7_CTS_,
108 GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2, 105 GPIO_FN_GPO7, GPIO_FN_MFG0_OUT2,
109 GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2, 106 GPIO_FN_GPO6, GPIO_FN_MFG1_OUT2,
110 GPIO_FN_GPO5, GPIO_FN_SCIFA0_SCK, GPIO_FN_FSICOSLDT3, \ 107 GPIO_FN_GPO5,
111 GPIO_FN_PORT16_VIO_CKOR, 108 GPIO_FN_PORT16_VIO_CKOR,
112 GPIO_FN_SCIFA0_TXD, 109 GPIO_FN_PORT19_VIO_CKO2,
113 GPIO_FN_SCIFA7_TXD,
114 GPIO_FN_SCIFA7_RTS_, GPIO_FN_PORT19_VIO_CKO2,
115 GPIO_FN_GPO0, 110 GPIO_FN_GPO0,
116 GPIO_FN_GPO1, 111 GPIO_FN_GPO1,
117 GPIO_FN_GPO2, GPIO_FN_STATUS0, 112 GPIO_FN_GPO2, GPIO_FN_STATUS0,
@@ -119,83 +114,44 @@ enum {
119 GPIO_FN_GPO4, GPIO_FN_STATUS2, 114 GPIO_FN_GPO4, GPIO_FN_STATUS2,
120 GPIO_FN_VINT, 115 GPIO_FN_VINT,
121 GPIO_FN_TCKON, 116 GPIO_FN_TCKON,
122 GPIO_FN_XDVFS1, GPIO_FN_PORT27_I2C_SCL2, GPIO_FN_PORT27_I2C_SCL3, \ 117 GPIO_FN_XDVFS1,
123 GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT, 118 GPIO_FN_MFG0_OUT1, GPIO_FN_PORT27_IROUT,
124 GPIO_FN_XDVFS2, GPIO_FN_PORT28_I2C_SDA2, GPIO_FN_PORT28_I2C_SDA3, \ 119 GPIO_FN_XDVFS2,
125 GPIO_FN_PORT28_TPU1TO1, 120 GPIO_FN_PORT28_TPU1TO1,
126 GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1, 121 GPIO_FN_SIM_RST, GPIO_FN_PORT29_TPU1TO1,
127 GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR, 122 GPIO_FN_SIM_CLK, GPIO_FN_PORT30_VIO_CKOR,
128 GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT, 123 GPIO_FN_SIM_D, GPIO_FN_PORT31_IROUT,
129 GPIO_FN_SCIFA4_TXD, 124 GPIO_FN_XWUP,
130 GPIO_FN_SCIFA4_RXD, GPIO_FN_XWUP,
131 GPIO_FN_SCIFA4_RTS_,
132 GPIO_FN_SCIFA4_CTS_,
133 GPIO_FN_FSIBOBT, GPIO_FN_FSIBIBT,
134 GPIO_FN_FSIBOLR, GPIO_FN_FSIBILR,
135 GPIO_FN_FSIBOSLD,
136 GPIO_FN_FSIBISLD,
137 GPIO_FN_VACK, 125 GPIO_FN_VACK,
138 GPIO_FN_XTAL1L, 126 GPIO_FN_XTAL1L,
139 GPIO_FN_SCIFA0_RTS_, GPIO_FN_FSICOSLDT2, 127 GPIO_FN_PORT49_IROUT,
140 GPIO_FN_SCIFA0_RXD, 128 GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2,
141 GPIO_FN_SCIFA0_CTS_, GPIO_FN_FSICOSLDT1, 129
142 GPIO_FN_FSICOBT, GPIO_FN_FSICIBT, GPIO_FN_FSIDOBT, GPIO_FN_FSIDIBT, 130 GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3,
143 GPIO_FN_FSICOLR, GPIO_FN_FSICILR, GPIO_FN_FSIDOLR, GPIO_FN_FSIDILR, 131 GPIO_FN_BBIF2_TXD2,
144 GPIO_FN_FSICOSLD, GPIO_FN_PORT47_FSICSPDIF, 132 GPIO_FN_TPU3TO3,
145 GPIO_FN_FSICISLD, GPIO_FN_FSIDISLD, 133 GPIO_FN_TPU3TO2,
146 GPIO_FN_FSIACK, GPIO_FN_PORT49_IRDA_OUT, GPIO_FN_PORT49_IROUT, \ 134 GPIO_FN_TPU0TO0,
147 GPIO_FN_FSIAOMC,
148 GPIO_FN_FSIAOLR, GPIO_FN_BBIF2_TSYNC2, GPIO_FN_TPU2TO2, GPIO_FN_FSIAILR,
149
150 GPIO_FN_FSIAOBT, GPIO_FN_BBIF2_TSCK2, GPIO_FN_TPU2TO3, GPIO_FN_FSIAIBT,
151 GPIO_FN_FSIAOSLD, GPIO_FN_BBIF2_TXD2,
152 GPIO_FN_FSIASPDIF, GPIO_FN_PORT53_IRDA_IN, GPIO_FN_TPU3TO3, \
153 GPIO_FN_FSIBSPDIF, GPIO_FN_PORT53_FSICSPDIF,
154 GPIO_FN_FSIBCK, GPIO_FN_PORT54_IRDA_FIRSEL, GPIO_FN_TPU3TO2, \
155 GPIO_FN_FSIBOMC, GPIO_FN_FSICCK, GPIO_FN_FSICOMC,
156 GPIO_FN_FSIAISLD, GPIO_FN_TPU0TO0,
157 GPIO_FN_A0, GPIO_FN_BS_, 135 GPIO_FN_A0, GPIO_FN_BS_,
158 GPIO_FN_A12, GPIO_FN_PORT58_KEYOUT7, GPIO_FN_TPU4TO2, 136 GPIO_FN_A12, GPIO_FN_TPU4TO2,
159 GPIO_FN_A13, GPIO_FN_PORT59_KEYOUT6, GPIO_FN_TPU0TO1, 137 GPIO_FN_A13, GPIO_FN_TPU0TO1,
160 GPIO_FN_A14, GPIO_FN_KEYOUT5, 138 GPIO_FN_A14,
161 GPIO_FN_A15, GPIO_FN_KEYOUT4, 139 GPIO_FN_A15,
162 GPIO_FN_A16, GPIO_FN_KEYOUT3, GPIO_FN_MSIOF0_SS1, 140 GPIO_FN_A16, GPIO_FN_MSIOF0_SS1,
163 GPIO_FN_A17, GPIO_FN_KEYOUT2, GPIO_FN_MSIOF0_TSYNC, 141 GPIO_FN_A17, GPIO_FN_MSIOF0_TSYNC,
164 GPIO_FN_A18, GPIO_FN_KEYOUT1, GPIO_FN_MSIOF0_TSCK, 142 GPIO_FN_A18, GPIO_FN_MSIOF0_TSCK,
165 GPIO_FN_A19, GPIO_FN_KEYOUT0, GPIO_FN_MSIOF0_TXD, 143 GPIO_FN_A19, GPIO_FN_MSIOF0_TXD,
166 GPIO_FN_A20, GPIO_FN_KEYIN0, GPIO_FN_MSIOF0_RSCK, 144 GPIO_FN_A20, GPIO_FN_MSIOF0_RSCK,
167 GPIO_FN_A21, GPIO_FN_KEYIN1, GPIO_FN_MSIOF0_RSYNC, 145 GPIO_FN_A21, GPIO_FN_MSIOF0_RSYNC,
168 GPIO_FN_A22, GPIO_FN_KEYIN2, GPIO_FN_MSIOF0_MCK0, 146 GPIO_FN_A22, GPIO_FN_MSIOF0_MCK0,
169 GPIO_FN_A23, GPIO_FN_KEYIN3, GPIO_FN_MSIOF0_MCK1, 147 GPIO_FN_A23, GPIO_FN_MSIOF0_MCK1,
170 GPIO_FN_A24, GPIO_FN_KEYIN4, GPIO_FN_MSIOF0_RXD, 148 GPIO_FN_A24, GPIO_FN_MSIOF0_RXD,
171 GPIO_FN_A25, GPIO_FN_KEYIN5, GPIO_FN_MSIOF0_SS2, 149 GPIO_FN_A25, GPIO_FN_MSIOF0_SS2,
172 GPIO_FN_A26, GPIO_FN_KEYIN6, 150 GPIO_FN_A26,
173 GPIO_FN_KEYIN7, 151 GPIO_FN_FCE1_,
174 GPIO_FN_D0_NAF0, 152 GPIO_FN_DACK0,
175 GPIO_FN_D1_NAF1, 153 GPIO_FN_FCE0_,
176 GPIO_FN_D2_NAF2,
177 GPIO_FN_D3_NAF3,
178 GPIO_FN_D4_NAF4,
179 GPIO_FN_D5_NAF5,
180 GPIO_FN_D6_NAF6,
181 GPIO_FN_D7_NAF7,
182 GPIO_FN_D8_NAF8,
183 GPIO_FN_D9_NAF9,
184 GPIO_FN_D10_NAF10,
185 GPIO_FN_D11_NAF11,
186 GPIO_FN_D12_NAF12,
187 GPIO_FN_D13_NAF13,
188 GPIO_FN_D14_NAF14,
189 GPIO_FN_D15_NAF15,
190 GPIO_FN_CS4_,
191 GPIO_FN_CS5A_, GPIO_FN_PORT91_RDWR,
192 GPIO_FN_CS5B_, GPIO_FN_FCE1_,
193 GPIO_FN_CS6B_, GPIO_FN_DACK0,
194 GPIO_FN_FCE0_, GPIO_FN_CS6A_,
195 GPIO_FN_WAIT_, GPIO_FN_DREQ0, 154 GPIO_FN_WAIT_, GPIO_FN_DREQ0,
196 GPIO_FN_RD__FSC,
197 GPIO_FN_WE0__FWE, GPIO_FN_RDWR_FWE,
198 GPIO_FN_WE1_,
199 GPIO_FN_FRB, 155 GPIO_FN_FRB,
200 GPIO_FN_CKO, 156 GPIO_FN_CKO,
201 GPIO_FN_NBRSTOUT_, 157 GPIO_FN_NBRSTOUT_,
@@ -204,145 +160,118 @@ enum {
204 GPIO_FN_BBIF2_RXD, 160 GPIO_FN_BBIF2_RXD,
205 GPIO_FN_BBIF2_SYNC, 161 GPIO_FN_BBIF2_SYNC,
206 GPIO_FN_BBIF2_SCK, 162 GPIO_FN_BBIF2_SCK,
207 GPIO_FN_SCIFA3_CTS_, GPIO_FN_MFG3_IN2, 163 GPIO_FN_MFG3_IN2,
208 GPIO_FN_SCIFA3_RXD, GPIO_FN_MFG3_IN1, 164 GPIO_FN_MFG3_IN1,
209 GPIO_FN_BBIF1_SS2, GPIO_FN_SCIFA3_RTS_, GPIO_FN_MFG3_OUT1, 165 GPIO_FN_BBIF1_SS2, GPIO_FN_MFG3_OUT1,
210 GPIO_FN_SCIFA3_TXD,
211 GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD, 166 GPIO_FN_HSI_RX_DATA, GPIO_FN_BBIF1_RXD,
212 GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK, 167 GPIO_FN_HSI_TX_WAKE, GPIO_FN_BBIF1_TSCK,
213 GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC, 168 GPIO_FN_HSI_TX_DATA, GPIO_FN_BBIF1_TSYNC,
214 GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD, 169 GPIO_FN_HSI_TX_READY, GPIO_FN_BBIF1_TXD,
215 GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK, GPIO_FN_PORT115_I2C_SCL2, \ 170 GPIO_FN_HSI_RX_READY, GPIO_FN_BBIF1_RSCK,
216 GPIO_FN_PORT115_I2C_SCL3, 171 GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC,
217 GPIO_FN_HSI_RX_WAKE, GPIO_FN_BBIF1_RSYNC, GPIO_FN_PORT116_I2C_SDA2, \
218 GPIO_FN_PORT116_I2C_SDA3,
219 GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW, 172 GPIO_FN_HSI_RX_FLAG, GPIO_FN_BBIF1_SS1, GPIO_FN_BBIF1_FLOW,
220 GPIO_FN_HSI_TX_FLAG, 173 GPIO_FN_HSI_TX_FLAG,
221 GPIO_FN_VIO_VD, GPIO_FN_PORT128_LCD2VSYN, GPIO_FN_VIO2_VD, \ 174 GPIO_FN_VIO_VD, GPIO_FN_VIO2_VD,
222 GPIO_FN_LCD2D0, 175
223 176 GPIO_FN_VIO_HD,
224 GPIO_FN_VIO_HD, GPIO_FN_PORT129_LCD2HSYN, GPIO_FN_PORT129_LCD2CS_, \ 177 GPIO_FN_VIO2_HD,
225 GPIO_FN_VIO2_HD, GPIO_FN_LCD2D1, 178 GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD,
226 GPIO_FN_VIO_D0, GPIO_FN_PORT130_MSIOF2_RXD, GPIO_FN_LCD2D10, 179 GPIO_FN_VIO_D1, GPIO_FN_PORT131_MSIOF2_SS1,
227 GPIO_FN_VIO_D1, GPIO_FN_PORT131_KEYOUT6, GPIO_FN_PORT131_MSIOF2_SS1, \ 180 GPIO_FN_VIO_D2, GPIO_FN_PORT132_MSIOF2_SS2,
228 GPIO_FN_PORT131_KEYOUT11, GPIO_FN_LCD2D11, 181 GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC,
229 GPIO_FN_VIO_D2, GPIO_FN_PORT132_KEYOUT7, GPIO_FN_PORT132_MSIOF2_SS2, \ 182 GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD,
230 GPIO_FN_PORT132_KEYOUT10, GPIO_FN_LCD2D12, 183 GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK,
231 GPIO_FN_VIO_D3, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_LCD2D13, 184 GPIO_FN_VIO_D6,
232 GPIO_FN_VIO_D4, GPIO_FN_MSIOF2_TXD, GPIO_FN_LCD2D14, 185 GPIO_FN_VIO_D7,
233 GPIO_FN_VIO_D5, GPIO_FN_MSIOF2_TSCK, GPIO_FN_LCD2D15, 186 GPIO_FN_VIO_D8, GPIO_FN_VIO2_D0,
234 GPIO_FN_VIO_D6, GPIO_FN_PORT136_KEYOUT8, GPIO_FN_LCD2D16, 187 GPIO_FN_VIO_D9, GPIO_FN_VIO2_D1,
235 GPIO_FN_VIO_D7, GPIO_FN_PORT137_KEYOUT9, GPIO_FN_LCD2D17, 188 GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2,
236 GPIO_FN_VIO_D8, GPIO_FN_PORT138_KEYOUT8, GPIO_FN_VIO2_D0, \ 189 GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3,
237 GPIO_FN_LCD2D6, 190 GPIO_FN_VIO_D12, GPIO_FN_VIO2_D4,
238 GPIO_FN_VIO_D9, GPIO_FN_PORT139_KEYOUT9, GPIO_FN_VIO2_D1, \ 191 GPIO_FN_VIO_D13,
239 GPIO_FN_LCD2D7, 192 GPIO_FN_VIO2_D5,
240 GPIO_FN_VIO_D10, GPIO_FN_TPU0TO2, GPIO_FN_VIO2_D2, GPIO_FN_LCD2D8, 193 GPIO_FN_VIO_D14, GPIO_FN_VIO2_D6,
241 GPIO_FN_VIO_D11, GPIO_FN_TPU0TO3, GPIO_FN_VIO2_D3, GPIO_FN_LCD2D9, 194 GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3,
242 GPIO_FN_VIO_D12, GPIO_FN_PORT142_KEYOUT10, GPIO_FN_VIO2_D4, \ 195 GPIO_FN_VIO2_D7,
243 GPIO_FN_LCD2D2, 196 GPIO_FN_VIO_CLK,
244 GPIO_FN_VIO_D13, GPIO_FN_PORT143_KEYOUT11, GPIO_FN_PORT143_KEYOUT6, \ 197 GPIO_FN_VIO2_CLK,
245 GPIO_FN_VIO2_D5, GPIO_FN_LCD2D3, 198 GPIO_FN_VIO_FIELD, GPIO_FN_VIO2_FIELD,
246 GPIO_FN_VIO_D14, GPIO_FN_PORT144_KEYOUT7, GPIO_FN_VIO2_D6, \
247 GPIO_FN_LCD2D4,
248 GPIO_FN_VIO_D15, GPIO_FN_TPU1TO3, GPIO_FN_PORT145_LCD2DISP, \
249 GPIO_FN_PORT145_LCD2RS, GPIO_FN_VIO2_D7, GPIO_FN_LCD2D5,
250 GPIO_FN_VIO_CLK, GPIO_FN_LCD2DCK, GPIO_FN_PORT146_LCD2WR_, \
251 GPIO_FN_VIO2_CLK, GPIO_FN_LCD2D18,
252 GPIO_FN_VIO_FIELD, GPIO_FN_LCD2RD_, GPIO_FN_VIO2_FIELD, GPIO_FN_LCD2D19,
253 GPIO_FN_VIO_CKO, 199 GPIO_FN_VIO_CKO,
254 GPIO_FN_A27, GPIO_FN_PORT149_RDWR, GPIO_FN_MFG0_IN1, \ 200 GPIO_FN_A27, GPIO_FN_MFG0_IN1,
255 GPIO_FN_PORT149_KEYOUT9,
256 GPIO_FN_MFG0_IN2, 201 GPIO_FN_MFG0_IN2,
257 GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK, 202 GPIO_FN_TS_SPSYNC3, GPIO_FN_MSIOF2_RSCK,
258 GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC, 203 GPIO_FN_TS_SDAT3, GPIO_FN_MSIOF2_RSYNC,
259 GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1, 204 GPIO_FN_TPU1TO2, GPIO_FN_TS_SDEN3, GPIO_FN_PORT153_MSIOF2_SS1,
260 GPIO_FN_SCIFA2_TXD1, GPIO_FN_MSIOF2_MCK0, 205 GPIO_FN_MSIOF2_MCK0,
261 GPIO_FN_SCIFA2_RXD1, GPIO_FN_MSIOF2_MCK1, 206 GPIO_FN_MSIOF2_MCK1,
262 GPIO_FN_SCIFA2_RTS1_, GPIO_FN_PORT156_MSIOF2_SS2, 207 GPIO_FN_PORT156_MSIOF2_SS2,
263 GPIO_FN_SCIFA2_CTS1_, GPIO_FN_PORT157_MSIOF2_RXD, 208 GPIO_FN_PORT157_MSIOF2_RXD,
264 GPIO_FN_DINT_, GPIO_FN_SCIFA2_SCK1, GPIO_FN_TS_SCK3, 209 GPIO_FN_DINT_, GPIO_FN_TS_SCK3,
265 GPIO_FN_PORT159_SCIFB_SCK, GPIO_FN_PORT159_SCIFA5_SCK, GPIO_FN_NMI, 210 GPIO_FN_NMI,
266 GPIO_FN_PORT160_SCIFB_TXD, GPIO_FN_PORT160_SCIFA5_TXD,
267 GPIO_FN_PORT161_SCIFB_CTS_, GPIO_FN_PORT161_SCIFA5_CTS_,
268 GPIO_FN_PORT162_SCIFB_RXD, GPIO_FN_PORT162_SCIFA5_RXD,
269 GPIO_FN_PORT163_SCIFB_RTS_, GPIO_FN_PORT163_SCIFA5_RTS_, \
270 GPIO_FN_TPU3TO0, 211 GPIO_FN_TPU3TO0,
271 GPIO_FN_LCDD0, 212 GPIO_FN_BBIF2_TSYNC1,
272 GPIO_FN_LCDD1, GPIO_FN_PORT193_SCIFA5_CTS_, GPIO_FN_BBIF2_TSYNC1, 213 GPIO_FN_BBIF2_TSCK1,
273 GPIO_FN_LCDD2, GPIO_FN_PORT194_SCIFA5_RTS_, GPIO_FN_BBIF2_TSCK1, 214 GPIO_FN_BBIF2_TXD1,
274 GPIO_FN_LCDD3, GPIO_FN_PORT195_SCIFA5_RXD, GPIO_FN_BBIF2_TXD1, 215 GPIO_FN_MFG2_OUT2,
275 GPIO_FN_LCDD4, GPIO_FN_PORT196_SCIFA5_TXD,
276 GPIO_FN_LCDD5, GPIO_FN_PORT197_SCIFA5_SCK, GPIO_FN_MFG2_OUT2, \
277 GPIO_FN_TPU2TO1, 216 GPIO_FN_TPU2TO1,
278 GPIO_FN_LCDD6, 217 GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2,
279 GPIO_FN_LCDD7, GPIO_FN_TPU4TO1, GPIO_FN_MFG4_OUT2, 218 GPIO_FN_D16,
280 GPIO_FN_LCDD8, GPIO_FN_D16, 219 GPIO_FN_D17,
281 GPIO_FN_LCDD9, GPIO_FN_D17, 220 GPIO_FN_D18,
282 GPIO_FN_LCDD10, GPIO_FN_D18, 221 GPIO_FN_D19,
283 GPIO_FN_LCDD11, GPIO_FN_D19, 222 GPIO_FN_D20,
284 GPIO_FN_LCDD12, GPIO_FN_D20, 223 GPIO_FN_D21,
285 GPIO_FN_LCDD13, GPIO_FN_D21, 224 GPIO_FN_D22,
286 GPIO_FN_LCDD14, GPIO_FN_D22, 225 GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23,
287 GPIO_FN_LCDD15, GPIO_FN_PORT207_MSIOF0L_SS1, GPIO_FN_D23, 226 GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24,
288 GPIO_FN_LCDD16, GPIO_FN_PORT208_MSIOF0L_SS2, GPIO_FN_D24, 227 GPIO_FN_D25,
289 GPIO_FN_LCDD17, GPIO_FN_D25, 228 GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26,
290 GPIO_FN_LCDD18, GPIO_FN_DREQ2, GPIO_FN_PORT210_MSIOF0L_SS1, GPIO_FN_D26, 229 GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27,
291 GPIO_FN_LCDD19, GPIO_FN_PORT211_MSIOF0L_SS2, GPIO_FN_D27, 230 GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28,
292 GPIO_FN_LCDD20, GPIO_FN_TS_SPSYNC1, GPIO_FN_MSIOF0L_MCK0, GPIO_FN_D28, 231 GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29,
293 GPIO_FN_LCDD21, GPIO_FN_TS_SDAT1, GPIO_FN_MSIOF0L_MCK1, GPIO_FN_D29, 232 GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30,
294 GPIO_FN_LCDD22, GPIO_FN_TS_SDEN1, GPIO_FN_MSIOF0L_RSCK, GPIO_FN_D30, 233 GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31,
295 GPIO_FN_LCDD23, GPIO_FN_TS_SCK1, GPIO_FN_MSIOF0L_RSYNC, GPIO_FN_D31, 234 GPIO_FN_DACK2,
296 GPIO_FN_LCDDCK, GPIO_FN_LCDWR_, 235 GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3,
297 GPIO_FN_LCDRD_, GPIO_FN_DACK2, GPIO_FN_PORT217_LCD2RS, \ 236 GPIO_FN_DACK3,
298 GPIO_FN_MSIOF0L_TSYNC, GPIO_FN_VIO2_FIELD3, GPIO_FN_PORT217_LCD2DISP,
299 GPIO_FN_LCDHSYN, GPIO_FN_LCDCS_, GPIO_FN_LCDCS2_, GPIO_FN_DACK3, \
300 GPIO_FN_PORT218_VIO_CKOR, 237 GPIO_FN_PORT218_VIO_CKOR,
301 GPIO_FN_LCDDISP, GPIO_FN_LCDRS, GPIO_FN_PORT219_LCD2WR_, \
302 GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \ 238 GPIO_FN_DREQ3, GPIO_FN_MSIOF0L_TSCK, GPIO_FN_VIO2_CLK3, \
303 GPIO_FN_LCD2DCK_2, 239 GPIO_FN_DREQ1,
304 GPIO_FN_LCDVSYN, GPIO_FN_LCDVSYN2,
305 GPIO_FN_LCDLCLK, GPIO_FN_DREQ1, GPIO_FN_PORT221_LCD2CS_, \
306 GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \ 240 GPIO_FN_PWEN, GPIO_FN_MSIOF0L_RXD, GPIO_FN_VIO2_HD3, \
307 GPIO_FN_PORT221_LCD2HSYN, 241 GPIO_FN_DACK1, GPIO_FN_OVCN,
308 GPIO_FN_LCDDON, GPIO_FN_LCDDON2, GPIO_FN_DACK1, GPIO_FN_OVCN, \ 242 GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3,
309 GPIO_FN_MSIOF0L_TXD, GPIO_FN_VIO2_VD3, GPIO_FN_PORT222_LCD2VSYN, 243
310 244 GPIO_FN_OVCN2,
311 GPIO_FN_SCIFA1_TXD, GPIO_FN_OVCN2, 245 GPIO_FN_EXTLP, GPIO_FN_PORT226_VIO_CKO2,
312 GPIO_FN_EXTLP, GPIO_FN_SCIFA1_SCK, GPIO_FN_PORT226_VIO_CKO2, 246 GPIO_FN_IDIN,
313 GPIO_FN_SCIFA1_RTS_, GPIO_FN_IDIN, 247 GPIO_FN_MFG1_IN1,
314 GPIO_FN_SCIFA1_RXD, 248 GPIO_FN_MSIOF1_TXD,
315 GPIO_FN_SCIFA1_CTS_, GPIO_FN_MFG1_IN1, 249 GPIO_FN_MSIOF1_TSYNC,
316 GPIO_FN_MSIOF1_TXD, GPIO_FN_SCIFA2_TXD2, 250 GPIO_FN_MSIOF1_TSCK,
317 GPIO_FN_MSIOF1_TSYNC, GPIO_FN_SCIFA2_CTS2_, 251 GPIO_FN_MSIOF1_RXD,
318 GPIO_FN_MSIOF1_TSCK, GPIO_FN_SCIFA2_SCK2, 252 GPIO_FN_MSIOF1_RSCK, GPIO_FN_VIO2_CLK2,
319 GPIO_FN_MSIOF1_RXD, GPIO_FN_SCIFA2_RXD2,
320 GPIO_FN_MSIOF1_RSCK, GPIO_FN_SCIFA2_RTS2_, GPIO_FN_VIO2_CLK2, \
321 GPIO_FN_LCD2D20,
322 GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \ 253 GPIO_FN_MSIOF1_RSYNC, GPIO_FN_MFG1_IN2, GPIO_FN_VIO2_VD2, \
323 GPIO_FN_LCD2D21, 254 GPIO_FN_MSIOF1_MCK0,
324 GPIO_FN_MSIOF1_MCK0, GPIO_FN_PORT236_I2C_SDA2, 255 GPIO_FN_MSIOF1_MCK1,
325 GPIO_FN_MSIOF1_MCK1, GPIO_FN_PORT237_I2C_SCL2, 256 GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2,
326 GPIO_FN_MSIOF1_SS1, GPIO_FN_VIO2_FIELD2, GPIO_FN_LCD2D22, 257 GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2,
327 GPIO_FN_MSIOF1_SS2, GPIO_FN_VIO2_HD2, GPIO_FN_LCD2D23, 258 GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
328 GPIO_FN_SCIFA6_TXD,
329 GPIO_FN_PORT241_IRDA_OUT, GPIO_FN_PORT241_IROUT, GPIO_FN_MFG4_OUT1, \
330 GPIO_FN_TPU4TO0, 259 GPIO_FN_TPU4TO0,
331 GPIO_FN_PORT242_IRDA_IN, GPIO_FN_MFG4_IN2, 260 GPIO_FN_MFG4_IN2,
332 GPIO_FN_PORT243_IRDA_FIRSEL, GPIO_FN_PORT243_VIO_CKO2, 261 GPIO_FN_PORT243_VIO_CKO2,
333 GPIO_FN_PORT244_SCIFA5_CTS_, GPIO_FN_MFG2_IN1, \ 262 GPIO_FN_MFG2_IN1,
334 GPIO_FN_PORT244_SCIFB_CTS_, GPIO_FN_MSIOF2R_RXD, 263 GPIO_FN_MSIOF2R_RXD,
335 GPIO_FN_PORT245_SCIFA5_RTS_, GPIO_FN_MFG2_IN2, \ 264 GPIO_FN_MFG2_IN2,
336 GPIO_FN_PORT245_SCIFB_RTS_, GPIO_FN_MSIOF2R_TXD, 265 GPIO_FN_MSIOF2R_TXD,
337 GPIO_FN_PORT246_SCIFA5_RXD, GPIO_FN_MFG1_OUT1, \ 266 GPIO_FN_MFG1_OUT1,
338 GPIO_FN_PORT246_SCIFB_RXD, GPIO_FN_TPU1TO0, 267 GPIO_FN_TPU1TO0,
339 GPIO_FN_PORT247_SCIFA5_TXD, GPIO_FN_MFG3_OUT2, \ 268 GPIO_FN_MFG3_OUT2,
340 GPIO_FN_PORT247_SCIFB_TXD, GPIO_FN_TPU3TO1, 269 GPIO_FN_TPU3TO1,
341 GPIO_FN_PORT248_SCIFA5_SCK, GPIO_FN_MFG2_OUT1, \ 270 GPIO_FN_MFG2_OUT1,
342 GPIO_FN_PORT248_SCIFB_SCK, GPIO_FN_TPU2TO0, \ 271 GPIO_FN_TPU2TO0,
343 GPIO_FN_PORT248_I2C_SCL3, GPIO_FN_MSIOF2R_TSCK, 272 GPIO_FN_MSIOF2R_TSCK,
344 GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \ 273 GPIO_FN_PORT249_IROUT, GPIO_FN_MFG4_IN1, \
345 GPIO_FN_PORT249_I2C_SDA3, GPIO_FN_MSIOF2R_TSYNC, 274 GPIO_FN_MSIOF2R_TSYNC,
346 GPIO_FN_SDHICLK0, 275 GPIO_FN_SDHICLK0,
347 GPIO_FN_SDHICD0, 276 GPIO_FN_SDHICD0,
348 GPIO_FN_SDHID0_0, 277 GPIO_FN_SDHID0_0,
@@ -435,54 +364,12 @@ enum {
435 GPIO_FN_IRQ9_MEM_INT, 364 GPIO_FN_IRQ9_MEM_INT,
436 GPIO_FN_IRQ9_MCP_INT, 365 GPIO_FN_IRQ9_MCP_INT,
437 GPIO_FN_A11, 366 GPIO_FN_A11,
438 GPIO_FN_KEYOUT8,
439 GPIO_FN_TPU4TO3, 367 GPIO_FN_TPU4TO3,
440 GPIO_FN_RESETA_N_PU_ON, 368 GPIO_FN_RESETA_N_PU_ON,
441 GPIO_FN_RESETA_N_PU_OFF, 369 GPIO_FN_RESETA_N_PU_OFF,
442 GPIO_FN_EDBGREQ_PD, 370 GPIO_FN_EDBGREQ_PD,
443 GPIO_FN_EDBGREQ_PU, 371 GPIO_FN_EDBGREQ_PU,
444 372
445 /* Functions with pull-ups */
446 GPIO_FN_KEYIN0_PU,
447 GPIO_FN_KEYIN1_PU,
448 GPIO_FN_KEYIN2_PU,
449 GPIO_FN_KEYIN3_PU,
450 GPIO_FN_KEYIN4_PU,
451 GPIO_FN_KEYIN5_PU,
452 GPIO_FN_KEYIN6_PU,
453 GPIO_FN_KEYIN7_PU,
454 GPIO_FN_SDHICD0_PU,
455 GPIO_FN_SDHID0_0_PU,
456 GPIO_FN_SDHID0_1_PU,
457 GPIO_FN_SDHID0_2_PU,
458 GPIO_FN_SDHID0_3_PU,
459 GPIO_FN_SDHICMD0_PU,
460 GPIO_FN_SDHIWP0_PU,
461 GPIO_FN_SDHID1_0_PU,
462 GPIO_FN_SDHID1_1_PU,
463 GPIO_FN_SDHID1_2_PU,
464 GPIO_FN_SDHID1_3_PU,
465 GPIO_FN_SDHICMD1_PU,
466 GPIO_FN_SDHID2_0_PU,
467 GPIO_FN_SDHID2_1_PU,
468 GPIO_FN_SDHID2_2_PU,
469 GPIO_FN_SDHID2_3_PU,
470 GPIO_FN_SDHICMD2_PU,
471 GPIO_FN_MMCCMD0_PU,
472 GPIO_FN_MMCCMD1_PU,
473 GPIO_FN_MMCD0_0_PU,
474 GPIO_FN_MMCD0_1_PU,
475 GPIO_FN_MMCD0_2_PU,
476 GPIO_FN_MMCD0_3_PU,
477 GPIO_FN_MMCD0_4_PU,
478 GPIO_FN_MMCD0_5_PU,
479 GPIO_FN_MMCD0_6_PU,
480 GPIO_FN_MMCD0_7_PU,
481 GPIO_FN_FSIACK_PU,
482 GPIO_FN_FSIAILR_PU,
483 GPIO_FN_FSIAIBT_PU,
484 GPIO_FN_FSIAISLD_PU,
485
486 /* end of GPIO */ 373 /* end of GPIO */
487 GPIO_NR, 374 GPIO_NR,
488}; 375};
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c
index 042df35e71a0..a460ba3dedcb 100644
--- a/arch/arm/mach-shmobile/setup-r8a7779.c
+++ b/arch/arm/mach-shmobile/setup-r8a7779.c
@@ -22,6 +22,7 @@
22#include <linux/interrupt.h> 22#include <linux/interrupt.h>
23#include <linux/irq.h> 23#include <linux/irq.h>
24#include <linux/of_platform.h> 24#include <linux/of_platform.h>
25#include <linux/platform_data/gpio-rcar.h>
25#include <linux/platform_device.h> 26#include <linux/platform_device.h>
26#include <linux/delay.h> 27#include <linux/delay.h>
27#include <linux/input.h> 28#include <linux/input.h>
@@ -68,11 +69,6 @@ static struct resource r8a7779_pfc_resources[] = {
68 .end = 0xfffc023b, 69 .end = 0xfffc023b,
69 .flags = IORESOURCE_MEM, 70 .flags = IORESOURCE_MEM,
70 }, 71 },
71 [1] = {
72 .start = 0xffc40000,
73 .end = 0xffc46fff,
74 .flags = IORESOURCE_MEM,
75 }
76}; 72};
77 73
78static struct platform_device r8a7779_pfc_device = { 74static struct platform_device r8a7779_pfc_device = {
@@ -82,9 +78,59 @@ static struct platform_device r8a7779_pfc_device = {
82 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources), 78 .num_resources = ARRAY_SIZE(r8a7779_pfc_resources),
83}; 79};
84 80
81#define R8A7779_GPIO(idx, npins) \
82static struct resource r8a7779_gpio##idx##_resources[] = { \
83 [0] = { \
84 .start = 0xffc40000 + 0x1000 * (idx), \
85 .end = 0xffc4002b + 0x1000 * (idx), \
86 .flags = IORESOURCE_MEM, \
87 }, \
88 [1] = { \
89 .start = gic_iid(0xad + (idx)), \
90 .flags = IORESOURCE_IRQ, \
91 } \
92}; \
93 \
94static struct gpio_rcar_config r8a7779_gpio##idx##_platform_data = { \
95 .gpio_base = 32 * (idx), \
96 .irq_base = 0, \
97 .number_of_pins = npins, \
98 .pctl_name = "pfc-r8a7779", \
99}; \
100 \
101static struct platform_device r8a7779_gpio##idx##_device = { \
102 .name = "gpio_rcar", \
103 .id = idx, \
104 .resource = r8a7779_gpio##idx##_resources, \
105 .num_resources = ARRAY_SIZE(r8a7779_gpio##idx##_resources), \
106 .dev = { \
107 .platform_data = &r8a7779_gpio##idx##_platform_data, \
108 }, \
109}
110
111R8A7779_GPIO(0, 32);
112R8A7779_GPIO(1, 32);
113R8A7779_GPIO(2, 32);
114R8A7779_GPIO(3, 32);
115R8A7779_GPIO(4, 32);
116R8A7779_GPIO(5, 32);
117R8A7779_GPIO(6, 9);
118
119static struct platform_device *r8a7779_pinctrl_devices[] __initdata = {
120 &r8a7779_pfc_device,
121 &r8a7779_gpio0_device,
122 &r8a7779_gpio1_device,
123 &r8a7779_gpio2_device,
124 &r8a7779_gpio3_device,
125 &r8a7779_gpio4_device,
126 &r8a7779_gpio5_device,
127 &r8a7779_gpio6_device,
128};
129
85void __init r8a7779_pinmux_init(void) 130void __init r8a7779_pinmux_init(void)
86{ 131{
87 platform_device_register(&r8a7779_pfc_device); 132 platform_add_devices(r8a7779_pinctrl_devices,
133 ARRAY_SIZE(r8a7779_pinctrl_devices));
88} 134}
89 135
90static struct plat_sci_port scif0_platform_data = { 136static struct plat_sci_port scif0_platform_data = {
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
index 96c6c2634cb4..eef17dcc3a41 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
@@ -8,12 +8,23 @@
8 * for more details. 8 * for more details.
9 */ 9 */
10 10
11#include <linux/bug.h>
11#include <linux/init.h> 12#include <linux/init.h>
12#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/ioport.h>
13#include <cpu/pfc.h> 15#include <cpu/pfc.h>
14 16
17static struct resource sh7203_pfc_resources[] = {
18 [0] = {
19 .start = 0xfffe3800,
20 .end = 0xfffe3a9f,
21 .flags = IORESOURCE_MEM,
22 },
23};
24
15static int __init plat_pinmux_setup(void) 25static int __init plat_pinmux_setup(void)
16{ 26{
17 return sh_pfc_register("pfc-sh7203", NULL, 0); 27 return sh_pfc_register("pfc-sh7203", sh7203_pfc_resources,
28 ARRAY_SIZE(sh7203_pfc_resources));
18} 29}
19arch_initcall(plat_pinmux_setup); 30arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
index b1b7c1bae127..569decbd6d93 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
@@ -8,12 +8,23 @@
8 * for more details. 8 * for more details.
9 */ 9 */
10 10
11#include <linux/bug.h>
11#include <linux/init.h> 12#include <linux/init.h>
12#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/ioport.h>
13#include <cpu/pfc.h> 15#include <cpu/pfc.h>
14 16
17static struct resource sh7264_pfc_resources[] = {
18 [0] = {
19 .start = 0xfffe3800,
20 .end = 0xfffe393f,
21 .flags = IORESOURCE_MEM,
22 },
23};
24
15static int __init plat_pinmux_setup(void) 25static int __init plat_pinmux_setup(void)
16{ 26{
17 return sh_pfc_register("pfc-sh7264", NULL, 0); 27 return sh_pfc_register("pfc-sh7264", sh7264_pfc_resources,
28 ARRAY_SIZE(sh7264_pfc_resources));
18} 29}
19arch_initcall(plat_pinmux_setup); 30arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
index dc2a86830456..4c17fb6970b1 100644
--- a/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
+++ b/arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
@@ -9,12 +9,23 @@
9 * for more details. 9 * for more details.
10 */ 10 */
11 11
12#include <linux/bug.h>
12#include <linux/init.h> 13#include <linux/init.h>
14#include <linux/ioport.h>
13#include <linux/kernel.h> 15#include <linux/kernel.h>
14#include <cpu/pfc.h> 16#include <cpu/pfc.h>
15 17
18static struct resource sh7269_pfc_resources[] = {
19 [0] = {
20 .start = 0xfffe3800,
21 .end = 0xfffe391f,
22 .flags = IORESOURCE_MEM,
23 },
24};
25
16static int __init plat_pinmux_setup(void) 26static int __init plat_pinmux_setup(void)
17{ 27{
18 return sh_pfc_register("pfc-sh7269", NULL, 0); 28 return sh_pfc_register("pfc-sh7269", sh7269_pfc_resources,
29 ARRAY_SIZE(sh7269_pfc_resources));
19} 30}
20arch_initcall(plat_pinmux_setup); 31arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
index 7d3744ac7b08..26e90a66ebb7 100644
--- a/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
@@ -8,13 +8,23 @@
8 * for more details. 8 * for more details.
9 */ 9 */
10 10
11#include <linux/bug.h>
11#include <linux/init.h> 12#include <linux/init.h>
12#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/ioport.h>
13#include <cpu/pfc.h> 15#include <cpu/pfc.h>
14 16
17static struct resource sh7720_pfc_resources[] = {
18 [0] = {
19 .start = 0xa4050100,
20 .end = 0xa405016f,
21 .flags = IORESOURCE_MEM,
22 },
23};
24
15static int __init plat_pinmux_setup(void) 25static int __init plat_pinmux_setup(void)
16{ 26{
17 return sh_pfc_register("pfc-sh7720", NULL, 0); 27 return sh_pfc_register("pfc-sh7720", sh7720_pfc_resources,
28 ARRAY_SIZE(sh7720_pfc_resources));
18} 29}
19
20arch_initcall(plat_pinmux_setup); 30arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
index d9bcc4290997..271bbc864929 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
@@ -1,10 +1,20 @@
1#include <linux/bug.h>
1#include <linux/init.h> 2#include <linux/init.h>
2#include <linux/kernel.h> 3#include <linux/kernel.h>
4#include <linux/ioport.h>
3#include <cpu/pfc.h> 5#include <cpu/pfc.h>
4 6
7static struct resource sh7722_pfc_resources[] = {
8 [0] = {
9 .start = 0xa4050100,
10 .end = 0xa405018f,
11 .flags = IORESOURCE_MEM,
12 },
13};
14
5static int __init plat_pinmux_setup(void) 15static int __init plat_pinmux_setup(void)
6{ 16{
7 return sh_pfc_register("pfc-sh7722", NULL, 0); 17 return sh_pfc_register("pfc-sh7722", sh7722_pfc_resources,
18 ARRAY_SIZE(sh7722_pfc_resources));
8} 19}
9
10arch_initcall(plat_pinmux_setup); 20arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
index bcec7ad7f783..99c637d5bf7a 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
@@ -8,13 +8,23 @@
8 * for more details. 8 * for more details.
9 */ 9 */
10 10
11#include <linux/bug.h>
11#include <linux/init.h> 12#include <linux/init.h>
12#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/ioport.h>
13#include <cpu/pfc.h> 15#include <cpu/pfc.h>
14 16
17static struct resource sh7723_pfc_resources[] = {
18 [0] = {
19 .start = 0xa4050100,
20 .end = 0xa405016f,
21 .flags = IORESOURCE_MEM,
22 },
23};
24
15static int __init plat_pinmux_setup(void) 25static int __init plat_pinmux_setup(void)
16{ 26{
17 return sh_pfc_register("pfc-sh7723", NULL, 0); 27 return sh_pfc_register("pfc-sh7723", sh7723_pfc_resources,
28 ARRAY_SIZE(sh7723_pfc_resources));
18} 29}
19
20arch_initcall(plat_pinmux_setup); 30arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
index 5c3541d6aed8..63be4749e341 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
@@ -13,12 +13,23 @@
13 * for more details. 13 * for more details.
14 */ 14 */
15 15
16#include <linux/bug.h>
16#include <linux/init.h> 17#include <linux/init.h>
17#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/ioport.h>
18#include <cpu/pfc.h> 20#include <cpu/pfc.h>
19 21
22static struct resource sh7724_pfc_resources[] = {
23 [0] = {
24 .start = 0xa4050100,
25 .end = 0xa405016f,
26 .flags = IORESOURCE_MEM,
27 },
28};
29
20static int __init plat_pinmux_setup(void) 30static int __init plat_pinmux_setup(void)
21{ 31{
22 return sh_pfc_register("pfc-sh7724", NULL, 0); 32 return sh_pfc_register("pfc-sh7724", sh7724_pfc_resources,
33 ARRAY_SIZE(sh7724_pfc_resources));
23} 34}
24arch_initcall(plat_pinmux_setup); 35arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
index cda6bd177b8c..567745d44221 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
@@ -13,12 +13,23 @@
13 * for more details. 13 * for more details.
14 */ 14 */
15 15
16#include <linux/bug.h>
16#include <linux/init.h> 17#include <linux/init.h>
17#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/ioport.h>
18#include <cpu/pfc.h> 20#include <cpu/pfc.h>
19 21
22static struct resource sh7757_pfc_resources[] = {
23 [0] = {
24 .start = 0xffec0000,
25 .end = 0xffec008f,
26 .flags = IORESOURCE_MEM,
27 },
28};
29
20static int __init plat_pinmux_setup(void) 30static int __init plat_pinmux_setup(void)
21{ 31{
22 return sh_pfc_register("pfc-sh7757", NULL, 0); 32 return sh_pfc_register("pfc-sh7757", sh7757_pfc_resources,
33 ARRAY_SIZE(sh7757_pfc_resources));
23} 34}
24arch_initcall(plat_pinmux_setup); 35arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
index 01055b809f64..e336ab8b5125 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
@@ -8,13 +8,23 @@
8 * for more details. 8 * for more details.
9 */ 9 */
10 10
11#include <linux/bug.h>
11#include <linux/init.h> 12#include <linux/init.h>
12#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/ioport.h>
13#include <cpu/pfc.h> 15#include <cpu/pfc.h>
14 16
17static struct resource sh7785_pfc_resources[] = {
18 [0] = {
19 .start = 0xffe70000,
20 .end = 0xffe7008f,
21 .flags = IORESOURCE_MEM,
22 },
23};
24
15static int __init plat_pinmux_setup(void) 25static int __init plat_pinmux_setup(void)
16{ 26{
17 return sh_pfc_register("pfc-sh7785", NULL, 0); 27 return sh_pfc_register("pfc-sh7785", sh7785_pfc_resources,
28 ARRAY_SIZE(sh7785_pfc_resources));
18} 29}
19
20arch_initcall(plat_pinmux_setup); 30arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
index 3061778d55da..9a459556a2f7 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
@@ -13,13 +13,23 @@
13 * for more details. 13 * for more details.
14 */ 14 */
15 15
16#include <linux/bug.h>
16#include <linux/init.h> 17#include <linux/init.h>
17#include <linux/kernel.h> 18#include <linux/kernel.h>
19#include <linux/ioport.h>
18#include <cpu/pfc.h> 20#include <cpu/pfc.h>
19 21
22static struct resource sh7786_pfc_resources[] = {
23 [0] = {
24 .start = 0xffcc0000,
25 .end = 0xffcc008f,
26 .flags = IORESOURCE_MEM,
27 },
28};
29
20static int __init plat_pinmux_setup(void) 30static int __init plat_pinmux_setup(void)
21{ 31{
22 return sh_pfc_register("pfc-sh7786", NULL, 0); 32 return sh_pfc_register("pfc-sh7786", sh7786_pfc_resources,
33 ARRAY_SIZE(sh7786_pfc_resources));
23} 34}
24
25arch_initcall(plat_pinmux_setup); 35arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
index ace84acc55ea..444bf25c60fa 100644
--- a/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
@@ -7,12 +7,23 @@
7 * License. See the file "COPYING" in the main directory of this archive 7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details. 8 * for more details.
9 */ 9 */
10#include <linux/bug.h>
10#include <linux/init.h> 11#include <linux/init.h>
11#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/ioport.h>
12#include <cpu/pfc.h> 14#include <cpu/pfc.h>
13 15
14static int __init shx3_pinmux_setup(void) 16static struct resource shx3_pfc_resources[] = {
17 [0] = {
18 .start = 0xffc70000,
19 .end = 0xffc7001f,
20 .flags = IORESOURCE_MEM,
21 },
22};
23
24static int __init plat_pinmux_setup(void)
15{ 25{
16 return sh_pfc_register("pfc-shx3", NULL, 0); 26 return sh_pfc_register("pfc-shx3", shx3_pfc_resources,
27 ARRAY_SIZE(shx3_pfc_resources));
17} 28}
18arch_initcall(shx3_pinmux_setup); 29arch_initcall(plat_pinmux_setup);
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 93aaadf99f28..d766e3cbef18 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -204,6 +204,12 @@ config GPIO_PXA
204 help 204 help
205 Say yes here to support the PXA GPIO device 205 Say yes here to support the PXA GPIO device
206 206
207config GPIO_RCAR
208 tristate "Renesas R-Car GPIO"
209 depends on ARM
210 help
211 Say yes here to support GPIO on Renesas R-Car SoCs.
212
207config GPIO_SPEAR_SPICS 213config GPIO_SPEAR_SPICS
208 bool "ST SPEAr13xx SPI Chip Select as GPIO support" 214 bool "ST SPEAr13xx SPI Chip Select as GPIO support"
209 depends on PLAT_SPEAR 215 depends on PLAT_SPEAR
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 22e07bc9fcb5..b41c74d45287 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -57,6 +57,7 @@ obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
57obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o 57obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
58obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o 58obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
59obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o 59obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
60obj-$(CONFIG_GPIO_RCAR) += gpio-rcar.o
60obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o 61obj-$(CONFIG_PLAT_SAMSUNG) += gpio-samsung.o
61obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o 62obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
62obj-$(CONFIG_GPIO_SCH) += gpio-sch.o 63obj-$(CONFIG_GPIO_SCH) += gpio-sch.o
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index b820869ca93c..06ed257c5d31 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -15,6 +15,7 @@
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/ioport.h> 16#include <linux/ioport.h>
17#include <linux/irq.h> 17#include <linux/irq.h>
18#include <linux/irqdomain.h>
18#include <linux/bitops.h> 19#include <linux/bitops.h>
19#include <linux/workqueue.h> 20#include <linux/workqueue.h>
20#include <linux/gpio.h> 21#include <linux/gpio.h>
@@ -22,6 +23,7 @@
22#include <linux/amba/bus.h> 23#include <linux/amba/bus.h>
23#include <linux/amba/pl061.h> 24#include <linux/amba/pl061.h>
24#include <linux/slab.h> 25#include <linux/slab.h>
26#include <linux/pinctrl/consumer.h>
25#include <linux/pm.h> 27#include <linux/pm.h>
26#include <asm/mach/irq.h> 28#include <asm/mach/irq.h>
27 29
@@ -51,8 +53,7 @@ struct pl061_gpio {
51 spinlock_t lock; 53 spinlock_t lock;
52 54
53 void __iomem *base; 55 void __iomem *base;
54 int irq_base; 56 struct irq_domain *domain;
55 struct irq_chip_generic *irq_gc;
56 struct gpio_chip gc; 57 struct gpio_chip gc;
57 58
58#ifdef CONFIG_PM 59#ifdef CONFIG_PM
@@ -60,6 +61,17 @@ struct pl061_gpio {
60#endif 61#endif
61}; 62};
62 63
64static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset)
65{
66 /*
67 * Map back to global GPIO space and request muxing, the direction
68 * parameter does not matter for this controller.
69 */
70 int gpio = chip->base + offset;
71
72 return pinctrl_request_gpio(gpio);
73}
74
63static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) 75static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
64{ 76{
65 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); 77 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
@@ -122,24 +134,20 @@ static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
122{ 134{
123 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc); 135 struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
124 136
125 if (chip->irq_base <= 0) 137 return irq_create_mapping(chip->domain, offset);
126 return -EINVAL;
127
128 return chip->irq_base + offset;
129} 138}
130 139
131static int pl061_irq_type(struct irq_data *d, unsigned trigger) 140static int pl061_irq_type(struct irq_data *d, unsigned trigger)
132{ 141{
133 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 142 struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
134 struct pl061_gpio *chip = gc->private; 143 int offset = irqd_to_hwirq(d);
135 int offset = d->irq - chip->irq_base;
136 unsigned long flags; 144 unsigned long flags;
137 u8 gpiois, gpioibe, gpioiev; 145 u8 gpiois, gpioibe, gpioiev;
138 146
139 if (offset < 0 || offset >= PL061_GPIO_NR) 147 if (offset < 0 || offset >= PL061_GPIO_NR)
140 return -EINVAL; 148 return -EINVAL;
141 149
142 raw_spin_lock_irqsave(&gc->lock, flags); 150 spin_lock_irqsave(&chip->lock, flags);
143 151
144 gpioiev = readb(chip->base + GPIOIEV); 152 gpioiev = readb(chip->base + GPIOIEV);
145 153
@@ -168,7 +176,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
168 176
169 writeb(gpioiev, chip->base + GPIOIEV); 177 writeb(gpioiev, chip->base + GPIOIEV);
170 178
171 raw_spin_unlock_irqrestore(&gc->lock, flags); 179 spin_unlock_irqrestore(&chip->lock, flags);
172 180
173 return 0; 181 return 0;
174} 182}
@@ -192,31 +200,61 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
192 chained_irq_exit(irqchip, desc); 200 chained_irq_exit(irqchip, desc);
193} 201}
194 202
195static void __init pl061_init_gc(struct pl061_gpio *chip, int irq_base) 203static void pl061_irq_mask(struct irq_data *d)
196{ 204{
197 struct irq_chip_type *ct; 205 struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
206 u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
207 u8 gpioie;
208
209 spin_lock(&chip->lock);
210 gpioie = readb(chip->base + GPIOIE) & ~mask;
211 writeb(gpioie, chip->base + GPIOIE);
212 spin_unlock(&chip->lock);
213}
214
215static void pl061_irq_unmask(struct irq_data *d)
216{
217 struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
218 u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
219 u8 gpioie;
220
221 spin_lock(&chip->lock);
222 gpioie = readb(chip->base + GPIOIE) | mask;
223 writeb(gpioie, chip->base + GPIOIE);
224 spin_unlock(&chip->lock);
225}
198 226
199 chip->irq_gc = irq_alloc_generic_chip("gpio-pl061", 1, irq_base, 227static struct irq_chip pl061_irqchip = {
200 chip->base, handle_simple_irq); 228 .name = "pl061 gpio",
201 chip->irq_gc->private = chip; 229 .irq_mask = pl061_irq_mask,
230 .irq_unmask = pl061_irq_unmask,
231 .irq_set_type = pl061_irq_type,
232};
233
234static int pl061_irq_map(struct irq_domain *d, unsigned int virq,
235 irq_hw_number_t hw)
236{
237 struct pl061_gpio *chip = d->host_data;
202 238
203 ct = chip->irq_gc->chip_types; 239 irq_set_chip_and_handler_name(virq, &pl061_irqchip, handle_simple_irq,
204 ct->chip.irq_mask = irq_gc_mask_clr_bit; 240 "pl061");
205 ct->chip.irq_unmask = irq_gc_mask_set_bit; 241 irq_set_chip_data(virq, chip);
206 ct->chip.irq_set_type = pl061_irq_type; 242 irq_set_irq_type(virq, IRQ_TYPE_NONE);
207 ct->chip.irq_set_wake = irq_gc_set_wake;
208 ct->regs.mask = GPIOIE;
209 243
210 irq_setup_generic_chip(chip->irq_gc, IRQ_MSK(PL061_GPIO_NR), 244 return 0;
211 IRQ_GC_INIT_NESTED_LOCK, IRQ_NOREQUEST, 0);
212} 245}
213 246
247static const struct irq_domain_ops pl061_domain_ops = {
248 .map = pl061_irq_map,
249 .xlate = irq_domain_xlate_twocell,
250};
251
214static int pl061_probe(struct amba_device *adev, const struct amba_id *id) 252static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
215{ 253{
216 struct device *dev = &adev->dev; 254 struct device *dev = &adev->dev;
217 struct pl061_platform_data *pdata = dev->platform_data; 255 struct pl061_platform_data *pdata = dev->platform_data;
218 struct pl061_gpio *chip; 256 struct pl061_gpio *chip;
219 int ret, irq, i; 257 int ret, irq, i, irq_base;
220 258
221 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 259 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
222 if (chip == NULL) 260 if (chip == NULL)
@@ -224,24 +262,31 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
224 262
225 if (pdata) { 263 if (pdata) {
226 chip->gc.base = pdata->gpio_base; 264 chip->gc.base = pdata->gpio_base;
227 chip->irq_base = pdata->irq_base; 265 irq_base = pdata->irq_base;
228 } else if (adev->dev.of_node) { 266 if (irq_base <= 0)
267 return -ENODEV;
268 } else {
229 chip->gc.base = -1; 269 chip->gc.base = -1;
230 chip->irq_base = 0; 270 irq_base = 0;
231 } else 271 }
232 return -ENODEV;
233 272
234 if (!devm_request_mem_region(dev, adev->res.start, 273 if (!devm_request_mem_region(dev, adev->res.start,
235 resource_size(&adev->res), "pl061")) 274 resource_size(&adev->res), "pl061"))
236 return -EBUSY; 275 return -EBUSY;
237 276
238 chip->base = devm_ioremap(dev, adev->res.start, 277 chip->base = devm_ioremap(dev, adev->res.start,
239 resource_size(&adev->res)); 278 resource_size(&adev->res));
240 if (chip->base == NULL) 279 if (!chip->base)
241 return -ENOMEM; 280 return -ENOMEM;
242 281
282 chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR,
283 irq_base, &pl061_domain_ops, chip);
284 if (!chip->domain)
285 return -ENODEV;
286
243 spin_lock_init(&chip->lock); 287 spin_lock_init(&chip->lock);
244 288
289 chip->gc.request = pl061_gpio_request;
245 chip->gc.direction_input = pl061_direction_input; 290 chip->gc.direction_input = pl061_direction_input;
246 chip->gc.direction_output = pl061_direction_output; 291 chip->gc.direction_output = pl061_direction_output;
247 chip->gc.get = pl061_get_value; 292 chip->gc.get = pl061_get_value;
@@ -259,12 +304,6 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
259 /* 304 /*
260 * irq_chip support 305 * irq_chip support
261 */ 306 */
262
263 if (chip->irq_base <= 0)
264 return 0;
265
266 pl061_init_gc(chip, chip->irq_base);
267
268 writeb(0, chip->base + GPIOIE); /* disable irqs */ 307 writeb(0, chip->base + GPIOIE); /* disable irqs */
269 irq = adev->irq[0]; 308 irq = adev->irq[0];
270 if (irq < 0) 309 if (irq < 0)
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
new file mode 100644
index 000000000000..b4ca450947b8
--- /dev/null
+++ b/drivers/gpio/gpio-rcar.c
@@ -0,0 +1,396 @@
1/*
2 * Renesas R-Car GPIO Support
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/err.h>
17#include <linux/gpio.h>
18#include <linux/init.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/ioport.h>
22#include <linux/irq.h>
23#include <linux/irqdomain.h>
24#include <linux/module.h>
25#include <linux/pinctrl/consumer.h>
26#include <linux/platform_data/gpio-rcar.h>
27#include <linux/platform_device.h>
28#include <linux/spinlock.h>
29#include <linux/slab.h>
30
31struct gpio_rcar_priv {
32 void __iomem *base;
33 spinlock_t lock;
34 struct gpio_rcar_config config;
35 struct platform_device *pdev;
36 struct gpio_chip gpio_chip;
37 struct irq_chip irq_chip;
38 struct irq_domain *irq_domain;
39};
40
41#define IOINTSEL 0x00
42#define INOUTSEL 0x04
43#define OUTDT 0x08
44#define INDT 0x0c
45#define INTDT 0x10
46#define INTCLR 0x14
47#define INTMSK 0x18
48#define MSKCLR 0x1c
49#define POSNEG 0x20
50#define EDGLEVEL 0x24
51#define FILONOFF 0x28
52
53static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
54{
55 return ioread32(p->base + offs);
56}
57
58static inline void gpio_rcar_write(struct gpio_rcar_priv *p, int offs,
59 u32 value)
60{
61 iowrite32(value, p->base + offs);
62}
63
64static void gpio_rcar_modify_bit(struct gpio_rcar_priv *p, int offs,
65 int bit, bool value)
66{
67 u32 tmp = gpio_rcar_read(p, offs);
68
69 if (value)
70 tmp |= BIT(bit);
71 else
72 tmp &= ~BIT(bit);
73
74 gpio_rcar_write(p, offs, tmp);
75}
76
77static void gpio_rcar_irq_disable(struct irq_data *d)
78{
79 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
80
81 gpio_rcar_write(p, INTMSK, ~BIT(irqd_to_hwirq(d)));
82}
83
84static void gpio_rcar_irq_enable(struct irq_data *d)
85{
86 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
87
88 gpio_rcar_write(p, MSKCLR, BIT(irqd_to_hwirq(d)));
89}
90
91static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
92 unsigned int hwirq,
93 bool active_high_rising_edge,
94 bool level_trigger)
95{
96 unsigned long flags;
97
98 /* follow steps in the GPIO documentation for
99 * "Setting Edge-Sensitive Interrupt Input Mode" and
100 * "Setting Level-Sensitive Interrupt Input Mode"
101 */
102
103 spin_lock_irqsave(&p->lock, flags);
104
105 /* Configure postive or negative logic in POSNEG */
106 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge);
107
108 /* Configure edge or level trigger in EDGLEVEL */
109 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
110
111 /* Select "Interrupt Input Mode" in IOINTSEL */
112 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
113
114 /* Write INTCLR in case of edge trigger */
115 if (!level_trigger)
116 gpio_rcar_write(p, INTCLR, BIT(hwirq));
117
118 spin_unlock_irqrestore(&p->lock, flags);
119}
120
121static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
122{
123 struct gpio_rcar_priv *p = irq_data_get_irq_chip_data(d);
124 unsigned int hwirq = irqd_to_hwirq(d);
125
126 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type);
127
128 switch (type & IRQ_TYPE_SENSE_MASK) {
129 case IRQ_TYPE_LEVEL_HIGH:
130 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true);
131 break;
132 case IRQ_TYPE_LEVEL_LOW:
133 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true);
134 break;
135 case IRQ_TYPE_EDGE_RISING:
136 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false);
137 break;
138 case IRQ_TYPE_EDGE_FALLING:
139 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false);
140 break;
141 default:
142 return -EINVAL;
143 }
144 return 0;
145}
146
147static irqreturn_t gpio_rcar_irq_handler(int irq, void *dev_id)
148{
149 struct gpio_rcar_priv *p = dev_id;
150 u32 pending;
151 unsigned int offset, irqs_handled = 0;
152
153 while ((pending = gpio_rcar_read(p, INTDT))) {
154 offset = __ffs(pending);
155 gpio_rcar_write(p, INTCLR, BIT(offset));
156 generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
157 irqs_handled++;
158 }
159
160 return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
161}
162
163static inline struct gpio_rcar_priv *gpio_to_priv(struct gpio_chip *chip)
164{
165 return container_of(chip, struct gpio_rcar_priv, gpio_chip);
166}
167
168static void gpio_rcar_config_general_input_output_mode(struct gpio_chip *chip,
169 unsigned int gpio,
170 bool output)
171{
172 struct gpio_rcar_priv *p = gpio_to_priv(chip);
173 unsigned long flags;
174
175 /* follow steps in the GPIO documentation for
176 * "Setting General Output Mode" and
177 * "Setting General Input Mode"
178 */
179
180 spin_lock_irqsave(&p->lock, flags);
181
182 /* Configure postive logic in POSNEG */
183 gpio_rcar_modify_bit(p, POSNEG, gpio, false);
184
185 /* Select "General Input/Output Mode" in IOINTSEL */
186 gpio_rcar_modify_bit(p, IOINTSEL, gpio, false);
187
188 /* Select Input Mode or Output Mode in INOUTSEL */
189 gpio_rcar_modify_bit(p, INOUTSEL, gpio, output);
190
191 spin_unlock_irqrestore(&p->lock, flags);
192}
193
194static int gpio_rcar_request(struct gpio_chip *chip, unsigned offset)
195{
196 return pinctrl_request_gpio(chip->base + offset);
197}
198
199static void gpio_rcar_free(struct gpio_chip *chip, unsigned offset)
200{
201 pinctrl_free_gpio(chip->base + offset);
202
203 /* Set the GPIO as an input to ensure that the next GPIO request won't
204 * drive the GPIO pin as an output.
205 */
206 gpio_rcar_config_general_input_output_mode(chip, offset, false);
207}
208
209static int gpio_rcar_direction_input(struct gpio_chip *chip, unsigned offset)
210{
211 gpio_rcar_config_general_input_output_mode(chip, offset, false);
212 return 0;
213}
214
215static int gpio_rcar_get(struct gpio_chip *chip, unsigned offset)
216{
217 return (int)(gpio_rcar_read(gpio_to_priv(chip), INDT) & BIT(offset));
218}
219
220static void gpio_rcar_set(struct gpio_chip *chip, unsigned offset, int value)
221{
222 struct gpio_rcar_priv *p = gpio_to_priv(chip);
223 unsigned long flags;
224
225 spin_lock_irqsave(&p->lock, flags);
226 gpio_rcar_modify_bit(p, OUTDT, offset, value);
227 spin_unlock_irqrestore(&p->lock, flags);
228}
229
230static int gpio_rcar_direction_output(struct gpio_chip *chip, unsigned offset,
231 int value)
232{
233 /* write GPIO value to output before selecting output mode of pin */
234 gpio_rcar_set(chip, offset, value);
235 gpio_rcar_config_general_input_output_mode(chip, offset, true);
236 return 0;
237}
238
239static int gpio_rcar_to_irq(struct gpio_chip *chip, unsigned offset)
240{
241 return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
242}
243
244static int gpio_rcar_irq_domain_map(struct irq_domain *h, unsigned int virq,
245 irq_hw_number_t hw)
246{
247 struct gpio_rcar_priv *p = h->host_data;
248
249 dev_dbg(&p->pdev->dev, "map hw irq = %d, virq = %d\n", (int)hw, virq);
250
251 irq_set_chip_data(virq, h->host_data);
252 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
253 set_irq_flags(virq, IRQF_VALID); /* kill me now */
254 return 0;
255}
256
257static struct irq_domain_ops gpio_rcar_irq_domain_ops = {
258 .map = gpio_rcar_irq_domain_map,
259};
260
261static int gpio_rcar_probe(struct platform_device *pdev)
262{
263 struct gpio_rcar_config *pdata = pdev->dev.platform_data;
264 struct gpio_rcar_priv *p;
265 struct resource *io, *irq;
266 struct gpio_chip *gpio_chip;
267 struct irq_chip *irq_chip;
268 const char *name = dev_name(&pdev->dev);
269 int ret;
270
271 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
272 if (!p) {
273 dev_err(&pdev->dev, "failed to allocate driver data\n");
274 ret = -ENOMEM;
275 goto err0;
276 }
277
278 /* deal with driver instance configuration */
279 if (pdata)
280 p->config = *pdata;
281
282 p->pdev = pdev;
283 platform_set_drvdata(pdev, p);
284 spin_lock_init(&p->lock);
285
286 io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
287 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
288
289 if (!io || !irq) {
290 dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
291 ret = -EINVAL;
292 goto err0;
293 }
294
295 p->base = devm_ioremap_nocache(&pdev->dev, io->start,
296 resource_size(io));
297 if (!p->base) {
298 dev_err(&pdev->dev, "failed to remap I/O memory\n");
299 ret = -ENXIO;
300 goto err0;
301 }
302
303 gpio_chip = &p->gpio_chip;
304 gpio_chip->request = gpio_rcar_request;
305 gpio_chip->free = gpio_rcar_free;
306 gpio_chip->direction_input = gpio_rcar_direction_input;
307 gpio_chip->get = gpio_rcar_get;
308 gpio_chip->direction_output = gpio_rcar_direction_output;
309 gpio_chip->set = gpio_rcar_set;
310 gpio_chip->to_irq = gpio_rcar_to_irq;
311 gpio_chip->label = name;
312 gpio_chip->owner = THIS_MODULE;
313 gpio_chip->base = p->config.gpio_base;
314 gpio_chip->ngpio = p->config.number_of_pins;
315
316 irq_chip = &p->irq_chip;
317 irq_chip->name = name;
318 irq_chip->irq_mask = gpio_rcar_irq_disable;
319 irq_chip->irq_unmask = gpio_rcar_irq_enable;
320 irq_chip->irq_enable = gpio_rcar_irq_enable;
321 irq_chip->irq_disable = gpio_rcar_irq_disable;
322 irq_chip->irq_set_type = gpio_rcar_irq_set_type;
323 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_SET_TYPE_MASKED;
324
325 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node,
326 p->config.number_of_pins,
327 p->config.irq_base,
328 &gpio_rcar_irq_domain_ops, p);
329 if (!p->irq_domain) {
330 ret = -ENXIO;
331 dev_err(&pdev->dev, "cannot initialize irq domain\n");
332 goto err1;
333 }
334
335 if (devm_request_irq(&pdev->dev, irq->start,
336 gpio_rcar_irq_handler, 0, name, p)) {
337 dev_err(&pdev->dev, "failed to request IRQ\n");
338 ret = -ENOENT;
339 goto err1;
340 }
341
342 ret = gpiochip_add(gpio_chip);
343 if (ret) {
344 dev_err(&pdev->dev, "failed to add GPIO controller\n");
345 goto err1;
346 }
347
348 dev_info(&pdev->dev, "driving %d GPIOs\n", p->config.number_of_pins);
349
350 /* warn in case of mismatch if irq base is specified */
351 if (p->config.irq_base) {
352 ret = irq_find_mapping(p->irq_domain, 0);
353 if (p->config.irq_base != ret)
354 dev_warn(&pdev->dev, "irq base mismatch (%u/%u)\n",
355 p->config.irq_base, ret);
356 }
357
358 ret = gpiochip_add_pin_range(gpio_chip, p->config.pctl_name, 0,
359 gpio_chip->base, gpio_chip->ngpio);
360 if (ret < 0)
361 dev_warn(&pdev->dev, "failed to add pin range\n");
362
363 return 0;
364
365err1:
366 irq_domain_remove(p->irq_domain);
367err0:
368 return ret;
369}
370
371static int gpio_rcar_remove(struct platform_device *pdev)
372{
373 struct gpio_rcar_priv *p = platform_get_drvdata(pdev);
374 int ret;
375
376 ret = gpiochip_remove(&p->gpio_chip);
377 if (ret)
378 return ret;
379
380 irq_domain_remove(p->irq_domain);
381 return 0;
382}
383
384static struct platform_driver gpio_rcar_device_driver = {
385 .probe = gpio_rcar_probe,
386 .remove = gpio_rcar_remove,
387 .driver = {
388 .name = "gpio_rcar",
389 }
390};
391
392module_platform_driver(gpio_rcar_device_driver);
393
394MODULE_AUTHOR("Magnus Damm");
395MODULE_DESCRIPTION("Renesas R-Car GPIO Driver");
396MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
index 5150df6cba08..465f4ca57e80 100644
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -203,22 +203,11 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
203 if (!pctldev) 203 if (!pctldev)
204 break; 204 break;
205 205
206 /*
207 * This assumes that the n GPIO pins are consecutive in the
208 * GPIO number space, and that the pins are also consecutive
209 * in their local number space. Currently it is not possible
210 * to add different ranges for one and the same GPIO chip,
211 * as the code assumes that we have one consecutive range
212 * on both, mapping 1-to-1.
213 *
214 * TODO: make the OF bindings handle multiple sparse ranges
215 * on the same GPIO chip.
216 */
217 ret = gpiochip_add_pin_range(chip, 206 ret = gpiochip_add_pin_range(chip,
218 pinctrl_dev_get_devname(pctldev), 207 pinctrl_dev_get_devname(pctldev),
219 0, /* offset in gpiochip */
220 pinspec.args[0], 208 pinspec.args[0],
221 pinspec.args[1]); 209 pinspec.args[1],
210 pinspec.args[2]);
222 211
223 if (ret) 212 if (ret)
224 break; 213 break;
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 34f51d2d90d2..5a690ce6d60d 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -166,6 +166,7 @@ config PINCTRL_SINGLE
166 depends on OF 166 depends on OF
167 select PINMUX 167 select PINMUX
168 select PINCONF 168 select PINCONF
169 select GENERIC_PINCONF
169 help 170 help
170 This selects the device tree based generic pinctrl driver. 171 This selects the device tree based generic pinctrl driver.
171 172
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index b0de6e7f1fdb..f8a632dc877b 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -27,6 +27,7 @@
27#include <linux/pinctrl/consumer.h> 27#include <linux/pinctrl/consumer.h>
28#include <linux/pinctrl/pinctrl.h> 28#include <linux/pinctrl/pinctrl.h>
29#include <linux/pinctrl/machine.h> 29#include <linux/pinctrl/machine.h>
30#include <asm-generic/gpio.h>
30#include "core.h" 31#include "core.h"
31#include "devicetree.h" 32#include "devicetree.h"
32#include "pinmux.h" 33#include "pinmux.h"
@@ -277,6 +278,39 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
277} 278}
278 279
279/** 280/**
281 * pinctrl_ready_for_gpio_range() - check if other GPIO pins of
282 * the same GPIO chip are in range
283 * @gpio: gpio pin to check taken from the global GPIO pin space
284 *
285 * This function is complement of pinctrl_match_gpio_range(). If the return
286 * value of pinctrl_match_gpio_range() is NULL, this function could be used
287 * to check whether pinctrl device is ready or not. Maybe some GPIO pins
288 * of the same GPIO chip don't have back-end pinctrl interface.
289 * If the return value is true, it means that pinctrl device is ready & the
290 * certain GPIO pin doesn't have back-end pinctrl device. If the return value
291 * is false, it means that pinctrl device may not be ready.
292 */
293static bool pinctrl_ready_for_gpio_range(unsigned gpio)
294{
295 struct pinctrl_dev *pctldev;
296 struct pinctrl_gpio_range *range = NULL;
297 struct gpio_chip *chip = gpio_to_chip(gpio);
298
299 /* Loop over the pin controllers */
300 list_for_each_entry(pctldev, &pinctrldev_list, node) {
301 /* Loop over the ranges */
302 list_for_each_entry(range, &pctldev->gpio_ranges, node) {
303 /* Check if any gpio range overlapped with gpio chip */
304 if (range->base + range->npins - 1 < chip->base ||
305 range->base > chip->base + chip->ngpio - 1)
306 continue;
307 return true;
308 }
309 }
310 return false;
311}
312
313/**
280 * pinctrl_get_device_gpio_range() - find device for GPIO range 314 * pinctrl_get_device_gpio_range() - find device for GPIO range
281 * @gpio: the pin to locate the pin controller for 315 * @gpio: the pin to locate the pin controller for
282 * @outdev: the pin control device if found 316 * @outdev: the pin control device if found
@@ -443,6 +477,8 @@ int pinctrl_request_gpio(unsigned gpio)
443 477
444 ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); 478 ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
445 if (ret) { 479 if (ret) {
480 if (pinctrl_ready_for_gpio_range(gpio))
481 ret = 0;
446 mutex_unlock(&pinctrl_mutex); 482 mutex_unlock(&pinctrl_mutex);
447 return ret; 483 return ret;
448 } 484 }
@@ -979,9 +1015,8 @@ static int devm_pinctrl_match(struct device *dev, void *res, void *data)
979 */ 1015 */
980void devm_pinctrl_put(struct pinctrl *p) 1016void devm_pinctrl_put(struct pinctrl *p)
981{ 1017{
982 WARN_ON(devres_destroy(p->dev, devm_pinctrl_release, 1018 WARN_ON(devres_release(p->dev, devm_pinctrl_release,
983 devm_pinctrl_match, p)); 1019 devm_pinctrl_match, p));
984 pinctrl_put(p);
985} 1020}
986EXPORT_SYMBOL_GPL(devm_pinctrl_put); 1021EXPORT_SYMBOL_GPL(devm_pinctrl_put);
987 1022
diff --git a/drivers/pinctrl/devicetree.c b/drivers/pinctrl/devicetree.c
index fd40a11ad645..c7b7cb477129 100644
--- a/drivers/pinctrl/devicetree.c
+++ b/drivers/pinctrl/devicetree.c
@@ -41,7 +41,7 @@ static void dt_free_map(struct pinctrl_dev *pctldev,
41 struct pinctrl_map *map, unsigned num_maps) 41 struct pinctrl_map *map, unsigned num_maps)
42{ 42{
43 if (pctldev) { 43 if (pctldev) {
44 struct pinctrl_ops *ops = pctldev->desc->pctlops; 44 const struct pinctrl_ops *ops = pctldev->desc->pctlops;
45 ops->dt_free_map(pctldev, map, num_maps); 45 ops->dt_free_map(pctldev, map, num_maps);
46 } else { 46 } else {
47 /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */ 47 /* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
@@ -122,7 +122,7 @@ static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
122{ 122{
123 struct device_node *np_pctldev; 123 struct device_node *np_pctldev;
124 struct pinctrl_dev *pctldev; 124 struct pinctrl_dev *pctldev;
125 struct pinctrl_ops *ops; 125 const struct pinctrl_ops *ops;
126 int ret; 126 int ret;
127 struct pinctrl_map *map; 127 struct pinctrl_map *map;
128 unsigned num_maps; 128 unsigned num_maps;
diff --git a/drivers/pinctrl/mvebu/pinctrl-mvebu.c b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
index 2d2f0a43d36b..7f34a2b212d2 100644
--- a/drivers/pinctrl/mvebu/pinctrl-mvebu.c
+++ b/drivers/pinctrl/mvebu/pinctrl-mvebu.c
@@ -263,7 +263,7 @@ static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
263 return; 263 return;
264} 264}
265 265
266static struct pinconf_ops mvebu_pinconf_ops = { 266static const struct pinconf_ops mvebu_pinconf_ops = {
267 .pin_config_group_get = mvebu_pinconf_group_get, 267 .pin_config_group_get = mvebu_pinconf_group_get,
268 .pin_config_group_set = mvebu_pinconf_group_set, 268 .pin_config_group_set = mvebu_pinconf_group_set,
269 .pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show, 269 .pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show,
@@ -369,7 +369,7 @@ static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
369 return -ENOTSUPP; 369 return -ENOTSUPP;
370} 370}
371 371
372static struct pinmux_ops mvebu_pinmux_ops = { 372static const struct pinmux_ops mvebu_pinmux_ops = {
373 .get_functions_count = mvebu_pinmux_get_funcs_count, 373 .get_functions_count = mvebu_pinmux_get_funcs_count,
374 .get_function_name = mvebu_pinmux_get_func_name, 374 .get_function_name = mvebu_pinmux_get_func_name,
375 .get_function_groups = mvebu_pinmux_get_groups, 375 .get_function_groups = mvebu_pinmux_get_groups,
@@ -470,7 +470,7 @@ static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
470 kfree(map); 470 kfree(map);
471} 471}
472 472
473static struct pinctrl_ops mvebu_pinctrl_ops = { 473static const struct pinctrl_ops mvebu_pinctrl_ops = {
474 .get_groups_count = mvebu_pinctrl_get_groups_count, 474 .get_groups_count = mvebu_pinctrl_get_groups_count,
475 .get_group_name = mvebu_pinctrl_get_group_name, 475 .get_group_name = mvebu_pinctrl_get_group_name,
476 .get_group_pins = mvebu_pinctrl_get_group_pins, 476 .get_group_pins = mvebu_pinctrl_get_group_pins,
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
index 06c304ac6f7d..9c436858812c 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -12,6 +12,7 @@
12#define pr_fmt(fmt) "generic pinconfig core: " fmt 12#define pr_fmt(fmt) "generic pinconfig core: " fmt
13 13
14#include <linux/kernel.h> 14#include <linux/kernel.h>
15#include <linux/module.h>
15#include <linux/init.h> 16#include <linux/init.h>
16#include <linux/device.h> 17#include <linux/device.h>
17#include <linux/slab.h> 18#include <linux/slab.h>
@@ -120,4 +121,17 @@ void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
120 } 121 }
121} 122}
122 123
124void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
125 struct seq_file *s, unsigned long config)
126{
127 int i;
128
129 for(i = 0; i < ARRAY_SIZE(conf_items); i++) {
130 if (pinconf_to_config_param(config) != conf_items[i].param)
131 continue;
132 seq_printf(s, "%s: 0x%x", conf_items[i].display,
133 pinconf_to_config_argument(config));
134 }
135}
136EXPORT_SYMBOL_GPL(pinconf_generic_dump_config);
123#endif 137#endif
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index d611ecfcbf70..dae927f91088 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -670,7 +670,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
670 struct pinctrl_maps *maps_node; 670 struct pinctrl_maps *maps_node;
671 struct pinctrl_map const *map; 671 struct pinctrl_map const *map;
672 struct pinctrl_dev *pctldev = NULL; 672 struct pinctrl_dev *pctldev = NULL;
673 struct pinconf_ops *confops = NULL; 673 const struct pinconf_ops *confops = NULL;
674 int i, j; 674 int i, j;
675 bool found = false; 675 bool found = false;
676 676
diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h
index bfda73d64eed..92c7267244d2 100644
--- a/drivers/pinctrl/pinconf.h
+++ b/drivers/pinctrl/pinconf.h
@@ -98,6 +98,8 @@ void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
98void pinconf_generic_dump_group(struct pinctrl_dev *pctldev, 98void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
99 struct seq_file *s, const char *gname); 99 struct seq_file *s, const char *gname);
100 100
101void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
102 struct seq_file *s, unsigned long config);
101#else 103#else
102 104
103static inline void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev, 105static inline void pinconf_generic_dump_pin(struct pinctrl_dev *pctldev,
@@ -114,4 +116,10 @@ static inline void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
114 return; 116 return;
115} 117}
116 118
119static inline void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
120 struct seq_file *s,
121 unsigned long config)
122{
123 return;
124}
117#endif 125#endif
diff --git a/drivers/pinctrl/pinctrl-abx500.c b/drivers/pinctrl/pinctrl-abx500.c
index c542a97c82f3..0cf3fa4a21ae 100644
--- a/drivers/pinctrl/pinctrl-abx500.c
+++ b/drivers/pinctrl/pinctrl-abx500.c
@@ -656,7 +656,7 @@ static void abx500_gpio_disable_free(struct pinctrl_dev *pctldev,
656{ 656{
657} 657}
658 658
659static struct pinmux_ops abx500_pinmux_ops = { 659static const struct pinmux_ops abx500_pinmux_ops = {
660 .get_functions_count = abx500_pmx_get_funcs_cnt, 660 .get_functions_count = abx500_pmx_get_funcs_cnt,
661 .get_function_name = abx500_pmx_get_func_name, 661 .get_function_name = abx500_pmx_get_func_name,
662 .get_function_groups = abx500_pmx_get_func_groups, 662 .get_function_groups = abx500_pmx_get_func_groups,
@@ -704,7 +704,7 @@ static void abx500_pin_dbg_show(struct pinctrl_dev *pctldev,
704 chip->base + offset - 1); 704 chip->base + offset - 1);
705} 705}
706 706
707static struct pinctrl_ops abx500_pinctrl_ops = { 707static const struct pinctrl_ops abx500_pinctrl_ops = {
708 .get_groups_count = abx500_get_groups_cnt, 708 .get_groups_count = abx500_get_groups_cnt,
709 .get_group_name = abx500_get_group_name, 709 .get_group_name = abx500_get_group_name,
710 .get_group_pins = abx500_get_group_pins, 710 .get_group_pins = abx500_get_group_pins,
@@ -778,7 +778,7 @@ int abx500_pin_config_set(struct pinctrl_dev *pctldev,
778 return ret; 778 return ret;
779} 779}
780 780
781static struct pinconf_ops abx500_pinconf_ops = { 781static const struct pinconf_ops abx500_pinconf_ops = {
782 .pin_config_get = abx500_pin_config_get, 782 .pin_config_get = abx500_pin_config_get,
783 .pin_config_set = abx500_pin_config_set, 783 .pin_config_set = abx500_pin_config_set,
784}; 784};
@@ -834,6 +834,7 @@ static const struct of_device_id abx500_gpio_match[] = {
834 { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, }, 834 { .compatible = "stericsson,ab8505-gpio", .data = (void *)PINCTRL_AB8505, },
835 { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, }, 835 { .compatible = "stericsson,ab8540-gpio", .data = (void *)PINCTRL_AB8540, },
836 { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, }, 836 { .compatible = "stericsson,ab9540-gpio", .data = (void *)PINCTRL_AB9540, },
837 { }
837}; 838};
838 839
839static int abx500_gpio_probe(struct platform_device *pdev) 840static int abx500_gpio_probe(struct platform_device *pdev)
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index efb7f10e902a..bddd1dd9efdf 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -294,7 +294,7 @@ static void at91_dt_free_map(struct pinctrl_dev *pctldev,
294{ 294{
295} 295}
296 296
297static struct pinctrl_ops at91_pctrl_ops = { 297static const struct pinctrl_ops at91_pctrl_ops = {
298 .get_groups_count = at91_get_groups_count, 298 .get_groups_count = at91_get_groups_count,
299 .get_group_name = at91_get_group_name, 299 .get_group_name = at91_get_group_name,
300 .get_group_pins = at91_get_group_pins, 300 .get_group_pins = at91_get_group_pins,
@@ -696,7 +696,7 @@ static void at91_gpio_disable_free(struct pinctrl_dev *pctldev,
696 /* Set the pin to some default state, GPIO is usually default */ 696 /* Set the pin to some default state, GPIO is usually default */
697} 697}
698 698
699static struct pinmux_ops at91_pmx_ops = { 699static const struct pinmux_ops at91_pmx_ops = {
700 .get_functions_count = at91_pmx_get_funcs_count, 700 .get_functions_count = at91_pmx_get_funcs_count,
701 .get_function_name = at91_pmx_get_func_name, 701 .get_function_name = at91_pmx_get_func_name,
702 .get_function_groups = at91_pmx_get_groups, 702 .get_function_groups = at91_pmx_get_groups,
@@ -776,7 +776,7 @@ static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
776{ 776{
777} 777}
778 778
779static struct pinconf_ops at91_pinconf_ops = { 779static const struct pinconf_ops at91_pinconf_ops = {
780 .pin_config_get = at91_pinconf_get, 780 .pin_config_get = at91_pinconf_get,
781 .pin_config_set = at91_pinconf_set, 781 .pin_config_set = at91_pinconf_set,
782 .pin_config_dbg_show = at91_pinconf_dbg_show, 782 .pin_config_dbg_show = at91_pinconf_dbg_show,
diff --git a/drivers/pinctrl/pinctrl-bcm2835.c b/drivers/pinctrl/pinctrl-bcm2835.c
index 4eb6d2c4e4df..f28d4b08771a 100644
--- a/drivers/pinctrl/pinctrl-bcm2835.c
+++ b/drivers/pinctrl/pinctrl-bcm2835.c
@@ -795,7 +795,7 @@ out:
795 return err; 795 return err;
796} 796}
797 797
798static struct pinctrl_ops bcm2835_pctl_ops = { 798static const struct pinctrl_ops bcm2835_pctl_ops = {
799 .get_groups_count = bcm2835_pctl_get_groups_count, 799 .get_groups_count = bcm2835_pctl_get_groups_count,
800 .get_group_name = bcm2835_pctl_get_group_name, 800 .get_group_name = bcm2835_pctl_get_group_name,
801 .get_group_pins = bcm2835_pctl_get_group_pins, 801 .get_group_pins = bcm2835_pctl_get_group_pins,
@@ -872,7 +872,7 @@ static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
872 return 0; 872 return 0;
873} 873}
874 874
875static struct pinmux_ops bcm2835_pmx_ops = { 875static const struct pinmux_ops bcm2835_pmx_ops = {
876 .get_functions_count = bcm2835_pmx_get_functions_count, 876 .get_functions_count = bcm2835_pmx_get_functions_count,
877 .get_function_name = bcm2835_pmx_get_function_name, 877 .get_function_name = bcm2835_pmx_get_function_name,
878 .get_function_groups = bcm2835_pmx_get_function_groups, 878 .get_function_groups = bcm2835_pmx_get_function_groups,
@@ -916,7 +916,7 @@ static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
916 return 0; 916 return 0;
917} 917}
918 918
919static struct pinconf_ops bcm2835_pinconf_ops = { 919static const struct pinconf_ops bcm2835_pinconf_ops = {
920 .pin_config_get = bcm2835_pinconf_get, 920 .pin_config_get = bcm2835_pinconf_get,
921 .pin_config_set = bcm2835_pinconf_set, 921 .pin_config_set = bcm2835_pinconf_set,
922}; 922};
diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c
index 1376eb7305db..169ea3e5f777 100644
--- a/drivers/pinctrl/pinctrl-exynos5440.c
+++ b/drivers/pinctrl/pinctrl-exynos5440.c
@@ -286,7 +286,7 @@ static void exynos5440_dt_free_map(struct pinctrl_dev *pctldev,
286} 286}
287 287
288/* list of pinctrl callbacks for the pinctrl core */ 288/* list of pinctrl callbacks for the pinctrl core */
289static struct pinctrl_ops exynos5440_pctrl_ops = { 289static const struct pinctrl_ops exynos5440_pctrl_ops = {
290 .get_groups_count = exynos5440_get_group_count, 290 .get_groups_count = exynos5440_get_group_count,
291 .get_group_name = exynos5440_get_group_name, 291 .get_group_name = exynos5440_get_group_name,
292 .get_group_pins = exynos5440_get_group_pins, 292 .get_group_pins = exynos5440_get_group_pins,
@@ -374,7 +374,7 @@ static int exynos5440_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
374} 374}
375 375
376/* list of pinmux callbacks for the pinmux vertical in pinctrl core */ 376/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
377static struct pinmux_ops exynos5440_pinmux_ops = { 377static const struct pinmux_ops exynos5440_pinmux_ops = {
378 .get_functions_count = exynos5440_get_functions_count, 378 .get_functions_count = exynos5440_get_functions_count,
379 .get_function_name = exynos5440_pinmux_get_fname, 379 .get_function_name = exynos5440_pinmux_get_fname,
380 .get_function_groups = exynos5440_pinmux_get_groups, 380 .get_function_groups = exynos5440_pinmux_get_groups,
@@ -523,7 +523,7 @@ static int exynos5440_pinconf_group_get(struct pinctrl_dev *pctldev,
523} 523}
524 524
525/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */ 525/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
526static struct pinconf_ops exynos5440_pinconf_ops = { 526static const struct pinconf_ops exynos5440_pinconf_ops = {
527 .pin_config_get = exynos5440_pinconf_get, 527 .pin_config_get = exynos5440_pinconf_get,
528 .pin_config_set = exynos5440_pinconf_set, 528 .pin_config_set = exynos5440_pinconf_set,
529 .pin_config_group_get = exynos5440_pinconf_group_get, 529 .pin_config_group_get = exynos5440_pinconf_group_get,
diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
index af97a1f90007..f9b2a1d4854f 100644
--- a/drivers/pinctrl/pinctrl-falcon.c
+++ b/drivers/pinctrl/pinctrl-falcon.c
@@ -353,7 +353,7 @@ static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
353{ 353{
354} 354}
355 355
356static struct pinconf_ops falcon_pinconf_ops = { 356static const struct pinconf_ops falcon_pinconf_ops = {
357 .pin_config_get = falcon_pinconf_get, 357 .pin_config_get = falcon_pinconf_get,
358 .pin_config_set = falcon_pinconf_set, 358 .pin_config_set = falcon_pinconf_set,
359 .pin_config_group_get = falcon_pinconf_group_get, 359 .pin_config_group_get = falcon_pinconf_group_get,
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
index 4cebb9c6c5c5..0ef190449eab 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -207,7 +207,7 @@ static void imx_dt_free_map(struct pinctrl_dev *pctldev,
207 kfree(map); 207 kfree(map);
208} 208}
209 209
210static struct pinctrl_ops imx_pctrl_ops = { 210static const struct pinctrl_ops imx_pctrl_ops = {
211 .get_groups_count = imx_get_groups_count, 211 .get_groups_count = imx_get_groups_count,
212 .get_group_name = imx_get_group_name, 212 .get_group_name = imx_get_group_name,
213 .get_group_pins = imx_get_group_pins, 213 .get_group_pins = imx_get_group_pins,
@@ -299,7 +299,7 @@ static int imx_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
299 return 0; 299 return 0;
300} 300}
301 301
302static struct pinmux_ops imx_pmx_ops = { 302static const struct pinmux_ops imx_pmx_ops = {
303 .get_functions_count = imx_pmx_get_funcs_count, 303 .get_functions_count = imx_pmx_get_funcs_count,
304 .get_function_name = imx_pmx_get_func_name, 304 .get_function_name = imx_pmx_get_func_name,
305 .get_function_groups = imx_pmx_get_groups, 305 .get_function_groups = imx_pmx_get_groups,
@@ -397,7 +397,7 @@ static void imx_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
397 } 397 }
398} 398}
399 399
400static struct pinconf_ops imx_pinconf_ops = { 400static const struct pinconf_ops imx_pinconf_ops = {
401 .pin_config_get = imx_pinconf_get, 401 .pin_config_get = imx_pinconf_get,
402 .pin_config_set = imx_pinconf_set, 402 .pin_config_set = imx_pinconf_set,
403 .pin_config_dbg_show = imx_pinconf_dbg_show, 403 .pin_config_dbg_show = imx_pinconf_dbg_show,
diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c
index a70384611351..615c5002b757 100644
--- a/drivers/pinctrl/pinctrl-lantiq.c
+++ b/drivers/pinctrl/pinctrl-lantiq.c
@@ -169,7 +169,7 @@ static int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
169 return 0; 169 return 0;
170} 170}
171 171
172static struct pinctrl_ops ltq_pctrl_ops = { 172static const struct pinctrl_ops ltq_pctrl_ops = {
173 .get_groups_count = ltq_get_group_count, 173 .get_groups_count = ltq_get_group_count,
174 .get_group_name = ltq_get_group_name, 174 .get_group_name = ltq_get_group_name,
175 .get_group_pins = ltq_get_group_pins, 175 .get_group_pins = ltq_get_group_pins,
@@ -311,7 +311,7 @@ static int ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev,
311 return info->apply_mux(pctrldev, mfp, pin_func); 311 return info->apply_mux(pctrldev, mfp, pin_func);
312} 312}
313 313
314static struct pinmux_ops ltq_pmx_ops = { 314static const struct pinmux_ops ltq_pmx_ops = {
315 .get_functions_count = ltq_pmx_func_count, 315 .get_functions_count = ltq_pmx_func_count,
316 .get_function_name = ltq_pmx_func_name, 316 .get_function_name = ltq_pmx_func_name,
317 .get_function_groups = ltq_pmx_get_groups, 317 .get_function_groups = ltq_pmx_get_groups,
diff --git a/drivers/pinctrl/pinctrl-mxs.c b/drivers/pinctrl/pinctrl-mxs.c
index 23af9f1f9c35..b45c4eb35798 100644
--- a/drivers/pinctrl/pinctrl-mxs.c
+++ b/drivers/pinctrl/pinctrl-mxs.c
@@ -158,7 +158,7 @@ static void mxs_dt_free_map(struct pinctrl_dev *pctldev,
158 kfree(map); 158 kfree(map);
159} 159}
160 160
161static struct pinctrl_ops mxs_pinctrl_ops = { 161static const struct pinctrl_ops mxs_pinctrl_ops = {
162 .get_groups_count = mxs_get_groups_count, 162 .get_groups_count = mxs_get_groups_count,
163 .get_group_name = mxs_get_group_name, 163 .get_group_name = mxs_get_group_name,
164 .get_group_pins = mxs_get_group_pins, 164 .get_group_pins = mxs_get_group_pins,
@@ -219,7 +219,7 @@ static int mxs_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned selector,
219 return 0; 219 return 0;
220} 220}
221 221
222static struct pinmux_ops mxs_pinmux_ops = { 222static const struct pinmux_ops mxs_pinmux_ops = {
223 .get_functions_count = mxs_pinctrl_get_funcs_count, 223 .get_functions_count = mxs_pinctrl_get_funcs_count,
224 .get_function_name = mxs_pinctrl_get_func_name, 224 .get_function_name = mxs_pinctrl_get_func_name,
225 .get_function_groups = mxs_pinctrl_get_func_groups, 225 .get_function_groups = mxs_pinctrl_get_func_groups,
@@ -319,7 +319,7 @@ static void mxs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
319 seq_printf(s, "0x%lx", config); 319 seq_printf(s, "0x%lx", config);
320} 320}
321 321
322static struct pinconf_ops mxs_pinconf_ops = { 322static const struct pinconf_ops mxs_pinconf_ops = {
323 .pin_config_get = mxs_pinconf_get, 323 .pin_config_get = mxs_pinconf_get,
324 .pin_config_set = mxs_pinconf_set, 324 .pin_config_set = mxs_pinconf_set,
325 .pin_config_group_get = mxs_pinconf_group_get, 325 .pin_config_group_get = mxs_pinconf_group_get,
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 36d20293de5c..2328baaa86bf 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -1764,7 +1764,7 @@ int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
1764 return 0; 1764 return 0;
1765} 1765}
1766 1766
1767static struct pinctrl_ops nmk_pinctrl_ops = { 1767static const struct pinctrl_ops nmk_pinctrl_ops = {
1768 .get_groups_count = nmk_get_groups_cnt, 1768 .get_groups_count = nmk_get_groups_cnt,
1769 .get_group_name = nmk_get_group_name, 1769 .get_group_name = nmk_get_group_name,
1770 .get_group_pins = nmk_get_group_pins, 1770 .get_group_pins = nmk_get_group_pins,
@@ -1975,7 +1975,7 @@ static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1975 /* Set the pin to some default state, GPIO is usually default */ 1975 /* Set the pin to some default state, GPIO is usually default */
1976} 1976}
1977 1977
1978static struct pinmux_ops nmk_pinmux_ops = { 1978static const struct pinmux_ops nmk_pinmux_ops = {
1979 .get_functions_count = nmk_pmx_get_funcs_cnt, 1979 .get_functions_count = nmk_pmx_get_funcs_cnt,
1980 .get_function_name = nmk_pmx_get_func_name, 1980 .get_function_name = nmk_pmx_get_func_name,
1981 .get_function_groups = nmk_pmx_get_func_groups, 1981 .get_function_groups = nmk_pmx_get_func_groups,
@@ -2089,7 +2089,7 @@ static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
2089 return 0; 2089 return 0;
2090} 2090}
2091 2091
2092static struct pinconf_ops nmk_pinconf_ops = { 2092static const struct pinconf_ops nmk_pinconf_ops = {
2093 .pin_config_get = nmk_pin_config_get, 2093 .pin_config_get = nmk_pin_config_get,
2094 .pin_config_set = nmk_pin_config_set, 2094 .pin_config_set = nmk_pin_config_set,
2095}; 2095};
diff --git a/drivers/pinctrl/pinctrl-pxa3xx.c b/drivers/pinctrl/pinctrl-pxa3xx.c
index 1f49bb02a6af..05e11de1d144 100644
--- a/drivers/pinctrl/pinctrl-pxa3xx.c
+++ b/drivers/pinctrl/pinctrl-pxa3xx.c
@@ -53,7 +53,7 @@ static int pxa3xx_get_group_pins(struct pinctrl_dev *pctrldev,
53 return 0; 53 return 0;
54} 54}
55 55
56static struct pinctrl_ops pxa3xx_pctrl_ops = { 56static const struct pinctrl_ops pxa3xx_pctrl_ops = {
57 .get_groups_count = pxa3xx_get_groups_count, 57 .get_groups_count = pxa3xx_get_groups_count,
58 .get_group_name = pxa3xx_get_group_name, 58 .get_group_name = pxa3xx_get_group_name,
59 .get_group_pins = pxa3xx_get_group_pins, 59 .get_group_pins = pxa3xx_get_group_pins,
@@ -161,7 +161,7 @@ static int pxa3xx_pmx_request_gpio(struct pinctrl_dev *pctrldev,
161 return 0; 161 return 0;
162} 162}
163 163
164static struct pinmux_ops pxa3xx_pmx_ops = { 164static const struct pinmux_ops pxa3xx_pmx_ops = {
165 .get_functions_count = pxa3xx_pmx_get_funcs_count, 165 .get_functions_count = pxa3xx_pmx_get_funcs_count,
166 .get_function_name = pxa3xx_pmx_get_func_name, 166 .get_function_name = pxa3xx_pmx_get_func_name,
167 .get_function_groups = pxa3xx_pmx_get_groups, 167 .get_function_groups = pxa3xx_pmx_get_groups,
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index f206df175656..3475b92b24a4 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -214,7 +214,7 @@ static void samsung_dt_free_map(struct pinctrl_dev *pctldev,
214} 214}
215 215
216/* list of pinctrl callbacks for the pinctrl core */ 216/* list of pinctrl callbacks for the pinctrl core */
217static struct pinctrl_ops samsung_pctrl_ops = { 217static const struct pinctrl_ops samsung_pctrl_ops = {
218 .get_groups_count = samsung_get_group_count, 218 .get_groups_count = samsung_get_group_count,
219 .get_group_name = samsung_get_group_name, 219 .get_group_name = samsung_get_group_name,
220 .get_group_pins = samsung_get_group_pins, 220 .get_group_pins = samsung_get_group_pins,
@@ -357,7 +357,7 @@ static int samsung_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
357} 357}
358 358
359/* list of pinmux callbacks for the pinmux vertical in pinctrl core */ 359/* list of pinmux callbacks for the pinmux vertical in pinctrl core */
360static struct pinmux_ops samsung_pinmux_ops = { 360static const struct pinmux_ops samsung_pinmux_ops = {
361 .get_functions_count = samsung_get_functions_count, 361 .get_functions_count = samsung_get_functions_count,
362 .get_function_name = samsung_pinmux_get_fname, 362 .get_function_name = samsung_pinmux_get_fname,
363 .get_function_groups = samsung_pinmux_get_groups, 363 .get_function_groups = samsung_pinmux_get_groups,
@@ -468,7 +468,7 @@ static int samsung_pinconf_group_get(struct pinctrl_dev *pctldev,
468} 468}
469 469
470/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */ 470/* list of pinconfig callbacks for pinconfig vertical in the pinctrl code */
471static struct pinconf_ops samsung_pinconf_ops = { 471static const struct pinconf_ops samsung_pinconf_ops = {
472 .pin_config_get = samsung_pinconf_get, 472 .pin_config_get = samsung_pinconf_get,
473 .pin_config_set = samsung_pinconf_set, 473 .pin_config_set = samsung_pinconf_set,
474 .pin_config_group_get = samsung_pinconf_group_get, 474 .pin_config_group_get = samsung_pinconf_group_get,
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 5c32e880bcb2..e35dabd3135d 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -22,8 +22,10 @@
22 22
23#include <linux/pinctrl/pinctrl.h> 23#include <linux/pinctrl/pinctrl.h>
24#include <linux/pinctrl/pinmux.h> 24#include <linux/pinctrl/pinmux.h>
25#include <linux/pinctrl/pinconf-generic.h>
25 26
26#include "core.h" 27#include "core.h"
28#include "pinconf.h"
27 29
28#define DRIVER_NAME "pinctrl-single" 30#define DRIVER_NAME "pinctrl-single"
29#define PCS_MUX_PINS_NAME "pinctrl-single,pins" 31#define PCS_MUX_PINS_NAME "pinctrl-single,pins"
@@ -59,6 +61,33 @@ struct pcs_func_vals {
59}; 61};
60 62
61/** 63/**
64 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
65 * and value, enable, disable, mask
66 * @param: config parameter
67 * @val: user input bits in the pinconf register
68 * @enable: enable bits in the pinconf register
69 * @disable: disable bits in the pinconf register
70 * @mask: mask bits in the register value
71 */
72struct pcs_conf_vals {
73 enum pin_config_param param;
74 unsigned val;
75 unsigned enable;
76 unsigned disable;
77 unsigned mask;
78};
79
80/**
81 * struct pcs_conf_type - pinconf property name, pinconf param pair
82 * @name: property name in DTS file
83 * @param: config parameter
84 */
85struct pcs_conf_type {
86 const char *name;
87 enum pin_config_param param;
88};
89
90/**
62 * struct pcs_function - pinctrl function 91 * struct pcs_function - pinctrl function
63 * @name: pinctrl function name 92 * @name: pinctrl function name
64 * @vals: register and vals array 93 * @vals: register and vals array
@@ -73,6 +102,22 @@ struct pcs_function {
73 unsigned nvals; 102 unsigned nvals;
74 const char **pgnames; 103 const char **pgnames;
75 int npgnames; 104 int npgnames;
105 struct pcs_conf_vals *conf;
106 int nconfs;
107 struct list_head node;
108};
109
110/**
111 * struct pcs_gpiofunc_range - pin ranges with same mux value of gpio function
112 * @offset: offset base of pins
113 * @npins: number pins with the same mux value of gpio function
114 * @gpiofunc: mux value of gpio function
115 * @node: list node
116 */
117struct pcs_gpiofunc_range {
118 unsigned offset;
119 unsigned npins;
120 unsigned gpiofunc;
76 struct list_head node; 121 struct list_head node;
77}; 122};
78 123
@@ -117,12 +162,14 @@ struct pcs_name {
117 * @fshift: function register shift 162 * @fshift: function register shift
118 * @foff: value to turn mux off 163 * @foff: value to turn mux off
119 * @fmax: max number of functions in fmask 164 * @fmax: max number of functions in fmask
165 * @is_pinconf: whether supports pinconf
120 * @names: array of register names for pins 166 * @names: array of register names for pins
121 * @pins: physical pins on the SoC 167 * @pins: physical pins on the SoC
122 * @pgtree: pingroup index radix tree 168 * @pgtree: pingroup index radix tree
123 * @ftree: function index radix tree 169 * @ftree: function index radix tree
124 * @pingroups: list of pingroups 170 * @pingroups: list of pingroups
125 * @functions: list of functions 171 * @functions: list of functions
172 * @gpiofuncs: list of gpio functions
126 * @ngroups: number of pingroups 173 * @ngroups: number of pingroups
127 * @nfuncs: number of functions 174 * @nfuncs: number of functions
128 * @desc: pin controller descriptor 175 * @desc: pin controller descriptor
@@ -142,12 +189,14 @@ struct pcs_device {
142 unsigned foff; 189 unsigned foff;
143 unsigned fmax; 190 unsigned fmax;
144 bool bits_per_mux; 191 bool bits_per_mux;
192 bool is_pinconf;
145 struct pcs_name *names; 193 struct pcs_name *names;
146 struct pcs_data pins; 194 struct pcs_data pins;
147 struct radix_tree_root pgtree; 195 struct radix_tree_root pgtree;
148 struct radix_tree_root ftree; 196 struct radix_tree_root ftree;
149 struct list_head pingroups; 197 struct list_head pingroups;
150 struct list_head functions; 198 struct list_head functions;
199 struct list_head gpiofuncs;
151 unsigned ngroups; 200 unsigned ngroups;
152 unsigned nfuncs; 201 unsigned nfuncs;
153 struct pinctrl_desc desc; 202 struct pinctrl_desc desc;
@@ -155,6 +204,16 @@ struct pcs_device {
155 void (*write)(unsigned val, void __iomem *reg); 204 void (*write)(unsigned val, void __iomem *reg);
156}; 205};
157 206
207static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
208 unsigned long *config);
209static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
210 unsigned long config);
211
212static enum pin_config_param pcs_bias[] = {
213 PIN_CONFIG_BIAS_PULL_DOWN,
214 PIN_CONFIG_BIAS_PULL_UP,
215};
216
158/* 217/*
159 * REVISIT: Reads and writes could eventually use regmap or something 218 * REVISIT: Reads and writes could eventually use regmap or something
160 * generic. But at least on omaps, some mux registers are performance 219 * generic. But at least on omaps, some mux registers are performance
@@ -270,7 +329,7 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
270 struct device_node *np_config, 329 struct device_node *np_config,
271 struct pinctrl_map **map, unsigned *num_maps); 330 struct pinctrl_map **map, unsigned *num_maps);
272 331
273static struct pinctrl_ops pcs_pinctrl_ops = { 332static const struct pinctrl_ops pcs_pinctrl_ops = {
274 .get_groups_count = pcs_get_groups_count, 333 .get_groups_count = pcs_get_groups_count,
275 .get_group_name = pcs_get_group_name, 334 .get_group_name = pcs_get_group_name,
276 .get_group_pins = pcs_get_group_pins, 335 .get_group_pins = pcs_get_group_pins,
@@ -326,6 +385,28 @@ static int pcs_get_function_groups(struct pinctrl_dev *pctldev,
326 return 0; 385 return 0;
327} 386}
328 387
388static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
389 struct pcs_function **func)
390{
391 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
392 struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
393 const struct pinctrl_setting_mux *setting;
394 unsigned fselector;
395
396 /* If pin is not described in DTS & enabled, mux_setting is NULL. */
397 setting = pdesc->mux_setting;
398 if (!setting)
399 return -ENOTSUPP;
400 fselector = setting->func;
401 *func = radix_tree_lookup(&pcs->ftree, fselector);
402 if (!(*func)) {
403 dev_err(pcs->dev, "%s could not find function%i\n",
404 __func__, fselector);
405 return -ENOTSUPP;
406 }
407 return 0;
408}
409
329static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector, 410static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
330 unsigned group) 411 unsigned group)
331{ 412{
@@ -334,6 +415,9 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
334 int i; 415 int i;
335 416
336 pcs = pinctrl_dev_get_drvdata(pctldev); 417 pcs = pinctrl_dev_get_drvdata(pctldev);
418 /* If function mask is null, needn't enable it. */
419 if (!pcs->fmask)
420 return 0;
337 func = radix_tree_lookup(&pcs->ftree, fselector); 421 func = radix_tree_lookup(&pcs->ftree, fselector);
338 if (!func) 422 if (!func)
339 return -EINVAL; 423 return -EINVAL;
@@ -368,6 +452,10 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
368 int i; 452 int i;
369 453
370 pcs = pinctrl_dev_get_drvdata(pctldev); 454 pcs = pinctrl_dev_get_drvdata(pctldev);
455 /* If function mask is null, needn't disable it. */
456 if (!pcs->fmask)
457 return;
458
371 func = radix_tree_lookup(&pcs->ftree, fselector); 459 func = radix_tree_lookup(&pcs->ftree, fselector);
372 if (!func) { 460 if (!func) {
373 dev_err(pcs->dev, "%s could not find function%i\n", 461 dev_err(pcs->dev, "%s could not find function%i\n",
@@ -403,12 +491,33 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
403} 491}
404 492
405static int pcs_request_gpio(struct pinctrl_dev *pctldev, 493static int pcs_request_gpio(struct pinctrl_dev *pctldev,
406 struct pinctrl_gpio_range *range, unsigned offset) 494 struct pinctrl_gpio_range *range, unsigned pin)
407{ 495{
408 return -ENOTSUPP; 496 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
497 struct pcs_gpiofunc_range *frange = NULL;
498 struct list_head *pos, *tmp;
499 int mux_bytes = 0;
500 unsigned data;
501
502 /* If function mask is null, return directly. */
503 if (!pcs->fmask)
504 return -ENOTSUPP;
505
506 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
507 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
508 if (pin >= frange->offset + frange->npins
509 || pin < frange->offset)
510 continue;
511 mux_bytes = pcs->width / BITS_PER_BYTE;
512 data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
513 data |= frange->gpiofunc;
514 pcs->write(data, pcs->base + pin * mux_bytes);
515 break;
516 }
517 return 0;
409} 518}
410 519
411static struct pinmux_ops pcs_pinmux_ops = { 520static const struct pinmux_ops pcs_pinmux_ops = {
412 .get_functions_count = pcs_get_functions_count, 521 .get_functions_count = pcs_get_functions_count,
413 .get_function_name = pcs_get_function_name, 522 .get_function_name = pcs_get_function_name,
414 .get_function_groups = pcs_get_function_groups, 523 .get_function_groups = pcs_get_function_groups,
@@ -417,32 +526,191 @@ static struct pinmux_ops pcs_pinmux_ops = {
417 .gpio_request_enable = pcs_request_gpio, 526 .gpio_request_enable = pcs_request_gpio,
418}; 527};
419 528
529/* Clear BIAS value */
530static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
531{
532 unsigned long config;
533 int i;
534 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
535 config = pinconf_to_config_packed(pcs_bias[i], 0);
536 pcs_pinconf_set(pctldev, pin, config);
537 }
538}
539
540/*
541 * Check whether PIN_CONFIG_BIAS_DISABLE is valid.
542 * It's depend on that PULL_DOWN & PULL_UP configs are all invalid.
543 */
544static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
545{
546 unsigned long config;
547 int i;
548
549 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
550 config = pinconf_to_config_packed(pcs_bias[i], 0);
551 if (!pcs_pinconf_get(pctldev, pin, &config))
552 goto out;
553 }
554 return true;
555out:
556 return false;
557}
558
420static int pcs_pinconf_get(struct pinctrl_dev *pctldev, 559static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
421 unsigned pin, unsigned long *config) 560 unsigned pin, unsigned long *config)
422{ 561{
562 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
563 struct pcs_function *func;
564 enum pin_config_param param;
565 unsigned offset = 0, data = 0, i, j, ret;
566
567 ret = pcs_get_function(pctldev, pin, &func);
568 if (ret)
569 return ret;
570
571 for (i = 0; i < func->nconfs; i++) {
572 param = pinconf_to_config_param(*config);
573 if (param == PIN_CONFIG_BIAS_DISABLE) {
574 if (pcs_pinconf_bias_disable(pctldev, pin)) {
575 *config = 0;
576 return 0;
577 } else {
578 return -ENOTSUPP;
579 }
580 } else if (param != func->conf[i].param) {
581 continue;
582 }
583
584 offset = pin * (pcs->width / BITS_PER_BYTE);
585 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
586 switch (func->conf[i].param) {
587 /* 4 parameters */
588 case PIN_CONFIG_BIAS_PULL_DOWN:
589 case PIN_CONFIG_BIAS_PULL_UP:
590 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
591 if ((data != func->conf[i].enable) ||
592 (data == func->conf[i].disable))
593 return -ENOTSUPP;
594 *config = 0;
595 break;
596 /* 2 parameters */
597 case PIN_CONFIG_INPUT_SCHMITT:
598 for (j = 0; j < func->nconfs; j++) {
599 switch (func->conf[j].param) {
600 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
601 if (data != func->conf[j].enable)
602 return -ENOTSUPP;
603 break;
604 default:
605 break;
606 }
607 }
608 *config = data;
609 break;
610 case PIN_CONFIG_DRIVE_STRENGTH:
611 case PIN_CONFIG_SLEW_RATE:
612 default:
613 *config = data;
614 break;
615 }
616 return 0;
617 }
423 return -ENOTSUPP; 618 return -ENOTSUPP;
424} 619}
425 620
426static int pcs_pinconf_set(struct pinctrl_dev *pctldev, 621static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
427 unsigned pin, unsigned long config) 622 unsigned pin, unsigned long config)
428{ 623{
624 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
625 struct pcs_function *func;
626 unsigned offset = 0, shift = 0, arg = 0, i, data, ret;
627 u16 argument;
628
629 ret = pcs_get_function(pctldev, pin, &func);
630 if (ret)
631 return ret;
632
633 for (i = 0; i < func->nconfs; i++) {
634 if (pinconf_to_config_param(config) == func->conf[i].param) {
635 offset = pin * (pcs->width / BITS_PER_BYTE);
636 data = pcs->read(pcs->base + offset);
637 argument = pinconf_to_config_argument(config);
638 switch (func->conf[i].param) {
639 /* 2 parameters */
640 case PIN_CONFIG_INPUT_SCHMITT:
641 case PIN_CONFIG_DRIVE_STRENGTH:
642 case PIN_CONFIG_SLEW_RATE:
643 shift = ffs(func->conf[i].mask) - 1;
644 arg = pinconf_to_config_argument(config);
645 data &= ~func->conf[i].mask;
646 data |= (arg << shift) & func->conf[i].mask;
647 break;
648 /* 4 parameters */
649 case PIN_CONFIG_BIAS_DISABLE:
650 pcs_pinconf_clear_bias(pctldev, pin);
651 break;
652 case PIN_CONFIG_BIAS_PULL_DOWN:
653 case PIN_CONFIG_BIAS_PULL_UP:
654 if (argument)
655 pcs_pinconf_clear_bias(pctldev, pin);
656 /* fall through */
657 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
658 data &= ~func->conf[i].mask;
659 if (argument)
660 data |= func->conf[i].enable;
661 else
662 data |= func->conf[i].disable;
663 break;
664 default:
665 return -ENOTSUPP;
666 }
667 pcs->write(data, pcs->base + offset);
668 return 0;
669 }
670 }
429 return -ENOTSUPP; 671 return -ENOTSUPP;
430} 672}
431 673
432static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev, 674static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
433 unsigned group, unsigned long *config) 675 unsigned group, unsigned long *config)
434{ 676{
435 return -ENOTSUPP; 677 const unsigned *pins;
678 unsigned npins, old = 0;
679 int i, ret;
680
681 ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
682 if (ret)
683 return ret;
684 for (i = 0; i < npins; i++) {
685 if (pcs_pinconf_get(pctldev, pins[i], config))
686 return -ENOTSUPP;
687 /* configs do not match between two pins */
688 if (i && (old != *config))
689 return -ENOTSUPP;
690 old = *config;
691 }
692 return 0;
436} 693}
437 694
438static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev, 695static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
439 unsigned group, unsigned long config) 696 unsigned group, unsigned long config)
440{ 697{
441 return -ENOTSUPP; 698 const unsigned *pins;
699 unsigned npins;
700 int i, ret;
701
702 ret = pcs_get_group_pins(pctldev, group, &pins, &npins);
703 if (ret)
704 return ret;
705 for (i = 0; i < npins; i++) {
706 if (pcs_pinconf_set(pctldev, pins[i], config))
707 return -ENOTSUPP;
708 }
709 return 0;
442} 710}
443 711
444static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev, 712static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
445 struct seq_file *s, unsigned offset) 713 struct seq_file *s, unsigned pin)
446{ 714{
447} 715}
448 716
@@ -451,13 +719,22 @@ static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
451{ 719{
452} 720}
453 721
454static struct pinconf_ops pcs_pinconf_ops = { 722static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
723 struct seq_file *s,
724 unsigned long config)
725{
726 pinconf_generic_dump_config(pctldev, s, config);
727}
728
729static const struct pinconf_ops pcs_pinconf_ops = {
455 .pin_config_get = pcs_pinconf_get, 730 .pin_config_get = pcs_pinconf_get,
456 .pin_config_set = pcs_pinconf_set, 731 .pin_config_set = pcs_pinconf_set,
457 .pin_config_group_get = pcs_pinconf_group_get, 732 .pin_config_group_get = pcs_pinconf_group_get,
458 .pin_config_group_set = pcs_pinconf_group_set, 733 .pin_config_group_set = pcs_pinconf_group_set,
459 .pin_config_dbg_show = pcs_pinconf_dbg_show, 734 .pin_config_dbg_show = pcs_pinconf_dbg_show,
460 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show, 735 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
736 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
737 .is_generic = true,
461}; 738};
462 739
463/** 740/**
@@ -648,11 +925,157 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
648 return index; 925 return index;
649} 926}
650 927
928/*
929 * check whether data matches enable bits or disable bits
930 * Return value: 1 for matching enable bits, 0 for matching disable bits,
931 * and negative value for matching failure.
932 */
933static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
934{
935 int ret = -EINVAL;
936
937 if (data == enable)
938 ret = 1;
939 else if (data == disable)
940 ret = 0;
941 return ret;
942}
943
944static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
945 unsigned value, unsigned enable, unsigned disable,
946 unsigned mask)
947{
948 (*conf)->param = param;
949 (*conf)->val = value;
950 (*conf)->enable = enable;
951 (*conf)->disable = disable;
952 (*conf)->mask = mask;
953 (*conf)++;
954}
955
956static void add_setting(unsigned long **setting, enum pin_config_param param,
957 unsigned arg)
958{
959 **setting = pinconf_to_config_packed(param, arg);
960 (*setting)++;
961}
962
963/* add pinconf setting with 2 parameters */
964static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
965 const char *name, enum pin_config_param param,
966 struct pcs_conf_vals **conf, unsigned long **settings)
967{
968 unsigned value[2];
969 int ret;
970
971 ret = of_property_read_u32_array(np, name, value, 2);
972 if (ret)
973 return;
974 /* set value & mask */
975 value[0] &= value[1];
976 /* skip enable & disable */
977 add_config(conf, param, value[0], 0, 0, value[1]);
978 add_setting(settings, param, value[0]);
979}
980
981/* add pinconf setting with 4 parameters */
982static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
983 const char *name, enum pin_config_param param,
984 struct pcs_conf_vals **conf, unsigned long **settings)
985{
986 unsigned value[4];
987 int ret;
988
989 /* value to set, enable, disable, mask */
990 ret = of_property_read_u32_array(np, name, value, 4);
991 if (ret)
992 return;
993 if (!value[3]) {
994 dev_err(pcs->dev, "mask field of the property can't be 0\n");
995 return;
996 }
997 value[0] &= value[3];
998 value[1] &= value[3];
999 value[2] &= value[3];
1000 ret = pcs_config_match(value[0], value[1], value[2]);
1001 if (ret < 0)
1002 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
1003 add_config(conf, param, value[0], value[1], value[2], value[3]);
1004 add_setting(settings, param, ret);
1005}
1006
1007static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
1008 struct pcs_function *func,
1009 struct pinctrl_map **map)
1010
1011{
1012 struct pinctrl_map *m = *map;
1013 int i = 0, nconfs = 0;
1014 unsigned long *settings = NULL, *s = NULL;
1015 struct pcs_conf_vals *conf = NULL;
1016 struct pcs_conf_type prop2[] = {
1017 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
1018 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
1019 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
1020 };
1021 struct pcs_conf_type prop4[] = {
1022 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
1023 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
1024 { "pinctrl-single,input-schmitt-enable",
1025 PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
1026 };
1027
1028 /* If pinconf isn't supported, don't parse properties in below. */
1029 if (!pcs->is_pinconf)
1030 return 0;
1031
1032 /* cacluate how much properties are supported in current node */
1033 for (i = 0; i < ARRAY_SIZE(prop2); i++) {
1034 if (of_find_property(np, prop2[i].name, NULL))
1035 nconfs++;
1036 }
1037 for (i = 0; i < ARRAY_SIZE(prop4); i++) {
1038 if (of_find_property(np, prop4[i].name, NULL))
1039 nconfs++;
1040 }
1041 if (!nconfs)
1042 return 0;
1043
1044 func->conf = devm_kzalloc(pcs->dev,
1045 sizeof(struct pcs_conf_vals) * nconfs,
1046 GFP_KERNEL);
1047 if (!func->conf)
1048 return -ENOMEM;
1049 func->nconfs = nconfs;
1050 conf = &(func->conf[0]);
1051 m++;
1052 settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
1053 GFP_KERNEL);
1054 if (!settings)
1055 return -ENOMEM;
1056 s = &settings[0];
1057
1058 for (i = 0; i < ARRAY_SIZE(prop2); i++)
1059 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
1060 &conf, &s);
1061 for (i = 0; i < ARRAY_SIZE(prop4); i++)
1062 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
1063 &conf, &s);
1064 m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
1065 m->data.configs.group_or_pin = np->name;
1066 m->data.configs.configs = settings;
1067 m->data.configs.num_configs = nconfs;
1068 return 0;
1069}
1070
1071static void pcs_free_pingroups(struct pcs_device *pcs);
1072
651/** 1073/**
652 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry 1074 * smux_parse_one_pinctrl_entry() - parses a device tree mux entry
653 * @pcs: pinctrl driver instance 1075 * @pcs: pinctrl driver instance
654 * @np: device node of the mux entry 1076 * @np: device node of the mux entry
655 * @map: map entry 1077 * @map: map entry
1078 * @num_maps: number of map
656 * @pgnames: pingroup names 1079 * @pgnames: pingroup names
657 * 1080 *
658 * Note that this binding currently supports only sets of one register + value. 1081 * Note that this binding currently supports only sets of one register + value.
@@ -669,6 +1092,7 @@ static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
669static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs, 1092static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
670 struct device_node *np, 1093 struct device_node *np,
671 struct pinctrl_map **map, 1094 struct pinctrl_map **map,
1095 unsigned *num_maps,
672 const char **pgnames) 1096 const char **pgnames)
673{ 1097{
674 struct pcs_func_vals *vals; 1098 struct pcs_func_vals *vals;
@@ -741,8 +1165,18 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
741 (*map)->data.mux.group = np->name; 1165 (*map)->data.mux.group = np->name;
742 (*map)->data.mux.function = np->name; 1166 (*map)->data.mux.function = np->name;
743 1167
1168 if (pcs->is_pinconf) {
1169 if (pcs_parse_pinconf(pcs, np, function, map))
1170 goto free_pingroups;
1171 *num_maps = 2;
1172 } else {
1173 *num_maps = 1;
1174 }
744 return 0; 1175 return 0;
745 1176
1177free_pingroups:
1178 pcs_free_pingroups(pcs);
1179 *num_maps = 1;
746free_function: 1180free_function:
747 pcs_remove_function(pcs, function); 1181 pcs_remove_function(pcs, function);
748 1182
@@ -771,7 +1205,8 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
771 1205
772 pcs = pinctrl_dev_get_drvdata(pctldev); 1206 pcs = pinctrl_dev_get_drvdata(pctldev);
773 1207
774 *map = devm_kzalloc(pcs->dev, sizeof(**map), GFP_KERNEL); 1208 /* create 2 maps. One is for pinmux, and the other is for pinconf. */
1209 *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
775 if (!*map) 1210 if (!*map)
776 return -ENOMEM; 1211 return -ENOMEM;
777 1212
@@ -783,13 +1218,13 @@ static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
783 goto free_map; 1218 goto free_map;
784 } 1219 }
785 1220
786 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, pgnames); 1221 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map, num_maps,
1222 pgnames);
787 if (ret < 0) { 1223 if (ret < 0) {
788 dev_err(pcs->dev, "no pins entries for %s\n", 1224 dev_err(pcs->dev, "no pins entries for %s\n",
789 np_config->name); 1225 np_config->name);
790 goto free_pgnames; 1226 goto free_pgnames;
791 } 1227 }
792 *num_maps = 1;
793 1228
794 return 0; 1229 return 0;
795 1230
@@ -879,6 +1314,37 @@ static void pcs_free_resources(struct pcs_device *pcs)
879 1314
880static struct of_device_id pcs_of_match[]; 1315static struct of_device_id pcs_of_match[];
881 1316
1317static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1318{
1319 const char *propname = "pinctrl-single,gpio-range";
1320 const char *cellname = "#pinctrl-single,gpio-range-cells";
1321 struct of_phandle_args gpiospec;
1322 struct pcs_gpiofunc_range *range;
1323 int ret, i;
1324
1325 for (i = 0; ; i++) {
1326 ret = of_parse_phandle_with_args(node, propname, cellname,
1327 i, &gpiospec);
1328 /* Do not treat it as error. Only treat it as end condition. */
1329 if (ret) {
1330 ret = 0;
1331 break;
1332 }
1333 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1334 if (!range) {
1335 ret = -ENOMEM;
1336 break;
1337 }
1338 range->offset = gpiospec.args[0];
1339 range->npins = gpiospec.args[1];
1340 range->gpiofunc = gpiospec.args[2];
1341 mutex_lock(&pcs->mutex);
1342 list_add_tail(&range->node, &pcs->gpiofuncs);
1343 mutex_unlock(&pcs->mutex);
1344 }
1345 return ret;
1346}
1347
882static int pcs_probe(struct platform_device *pdev) 1348static int pcs_probe(struct platform_device *pdev)
883{ 1349{
884 struct device_node *np = pdev->dev.of_node; 1350 struct device_node *np = pdev->dev.of_node;
@@ -900,14 +1366,23 @@ static int pcs_probe(struct platform_device *pdev)
900 mutex_init(&pcs->mutex); 1366 mutex_init(&pcs->mutex);
901 INIT_LIST_HEAD(&pcs->pingroups); 1367 INIT_LIST_HEAD(&pcs->pingroups);
902 INIT_LIST_HEAD(&pcs->functions); 1368 INIT_LIST_HEAD(&pcs->functions);
1369 INIT_LIST_HEAD(&pcs->gpiofuncs);
1370 pcs->is_pinconf = match->data;
903 1371
904 PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width, 1372 PCS_GET_PROP_U32("pinctrl-single,register-width", &pcs->width,
905 "register width not specified\n"); 1373 "register width not specified\n");
906 1374
907 PCS_GET_PROP_U32("pinctrl-single,function-mask", &pcs->fmask, 1375 ret = of_property_read_u32(np, "pinctrl-single,function-mask",
908 "function register mask not specified\n"); 1376 &pcs->fmask);
909 pcs->fshift = ffs(pcs->fmask) - 1; 1377 if (!ret) {
910 pcs->fmax = pcs->fmask >> pcs->fshift; 1378 pcs->fshift = ffs(pcs->fmask) - 1;
1379 pcs->fmax = pcs->fmask >> pcs->fshift;
1380 } else {
1381 /* If mask property doesn't exist, function mux is invalid. */
1382 pcs->fmask = 0;
1383 pcs->fshift = 0;
1384 pcs->fmax = 0;
1385 }
911 1386
912 ret = of_property_read_u32(np, "pinctrl-single,function-off", 1387 ret = of_property_read_u32(np, "pinctrl-single,function-off",
913 &pcs->foff); 1388 &pcs->foff);
@@ -961,7 +1436,8 @@ static int pcs_probe(struct platform_device *pdev)
961 pcs->desc.name = DRIVER_NAME; 1436 pcs->desc.name = DRIVER_NAME;
962 pcs->desc.pctlops = &pcs_pinctrl_ops; 1437 pcs->desc.pctlops = &pcs_pinctrl_ops;
963 pcs->desc.pmxops = &pcs_pinmux_ops; 1438 pcs->desc.pmxops = &pcs_pinmux_ops;
964 pcs->desc.confops = &pcs_pinconf_ops; 1439 if (pcs->is_pinconf)
1440 pcs->desc.confops = &pcs_pinconf_ops;
965 pcs->desc.owner = THIS_MODULE; 1441 pcs->desc.owner = THIS_MODULE;
966 1442
967 ret = pcs_allocate_pin_table(pcs); 1443 ret = pcs_allocate_pin_table(pcs);
@@ -975,6 +1451,10 @@ static int pcs_probe(struct platform_device *pdev)
975 goto free; 1451 goto free;
976 } 1452 }
977 1453
1454 ret = pcs_add_gpio_func(np, pcs);
1455 if (ret < 0)
1456 goto free;
1457
978 dev_info(pcs->dev, "%i pins at pa %p size %u\n", 1458 dev_info(pcs->dev, "%i pins at pa %p size %u\n",
979 pcs->desc.npins, pcs->base, pcs->size); 1459 pcs->desc.npins, pcs->base, pcs->size);
980 1460
@@ -999,7 +1479,8 @@ static int pcs_remove(struct platform_device *pdev)
999} 1479}
1000 1480
1001static struct of_device_id pcs_of_match[] = { 1481static struct of_device_id pcs_of_match[] = {
1002 { .compatible = DRIVER_NAME, }, 1482 { .compatible = "pinctrl-single", .data = (void *)false },
1483 { .compatible = "pinconf-single", .data = (void *)true },
1003 { }, 1484 { },
1004}; 1485};
1005MODULE_DEVICE_TABLE(of, pcs_of_match); 1486MODULE_DEVICE_TABLE(of, pcs_of_match);
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index d02498b30c6e..0990a721758e 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -979,7 +979,7 @@ static void sirfsoc_dt_free_map(struct pinctrl_dev *pctldev,
979 kfree(map); 979 kfree(map);
980} 980}
981 981
982static struct pinctrl_ops sirfsoc_pctrl_ops = { 982static const struct pinctrl_ops sirfsoc_pctrl_ops = {
983 .get_groups_count = sirfsoc_get_groups_count, 983 .get_groups_count = sirfsoc_get_groups_count,
984 .get_group_name = sirfsoc_get_group_name, 984 .get_group_name = sirfsoc_get_group_name,
985 .get_group_pins = sirfsoc_get_group_pins, 985 .get_group_pins = sirfsoc_get_group_pins,
@@ -1181,7 +1181,7 @@ static int sirfsoc_pinmux_request_gpio(struct pinctrl_dev *pmxdev,
1181 return 0; 1181 return 0;
1182} 1182}
1183 1183
1184static struct pinmux_ops sirfsoc_pinmux_ops = { 1184static const struct pinmux_ops sirfsoc_pinmux_ops = {
1185 .enable = sirfsoc_pinmux_enable, 1185 .enable = sirfsoc_pinmux_enable,
1186 .disable = sirfsoc_pinmux_disable, 1186 .disable = sirfsoc_pinmux_disable,
1187 .get_functions_count = sirfsoc_pinmux_get_funcs_count, 1187 .get_functions_count = sirfsoc_pinmux_get_funcs_count,
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 80b11e3415bc..cb491d6ba601 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -30,482 +30,856 @@
30static const struct sunxi_desc_pin sun4i_a10_pins[] = { 30static const struct sunxi_desc_pin sun4i_a10_pins[] = {
31 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0, 31 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA0,
32 SUNXI_FUNCTION(0x0, "gpio_in"), 32 SUNXI_FUNCTION(0x0, "gpio_in"),
33 SUNXI_FUNCTION(0x1, "gpio_out")), 33 SUNXI_FUNCTION(0x1, "gpio_out"),
34 SUNXI_FUNCTION(0x2, "wemac"), /* ERXD3 */
35 SUNXI_FUNCTION(0x3, "spi1"), /* CS0 */
36 SUNXI_FUNCTION(0x4, "uart2")), /* RTS */
34 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1, 37 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA1,
35 SUNXI_FUNCTION(0x0, "gpio_in"), 38 SUNXI_FUNCTION(0x0, "gpio_in"),
36 SUNXI_FUNCTION(0x1, "gpio_out")), 39 SUNXI_FUNCTION(0x1, "gpio_out"),
40 SUNXI_FUNCTION(0x2, "wemac"), /* ERXD2 */
41 SUNXI_FUNCTION(0x3, "spi1"), /* CLK */
42 SUNXI_FUNCTION(0x4, "uart2")), /* CTS */
37 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2, 43 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA2,
38 SUNXI_FUNCTION(0x0, "gpio_in"), 44 SUNXI_FUNCTION(0x0, "gpio_in"),
39 SUNXI_FUNCTION(0x1, "gpio_out")), 45 SUNXI_FUNCTION(0x1, "gpio_out"),
46 SUNXI_FUNCTION(0x2, "wemac"), /* ERXD1 */
47 SUNXI_FUNCTION(0x3, "spi1"), /* MOSI */
48 SUNXI_FUNCTION(0x4, "uart2")), /* TX */
40 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3, 49 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA3,
41 SUNXI_FUNCTION(0x0, "gpio_in"), 50 SUNXI_FUNCTION(0x0, "gpio_in"),
42 SUNXI_FUNCTION(0x1, "gpio_out")), 51 SUNXI_FUNCTION(0x1, "gpio_out"),
52 SUNXI_FUNCTION(0x2, "wemac"), /* ERXD0 */
53 SUNXI_FUNCTION(0x3, "spi1"), /* MISO */
54 SUNXI_FUNCTION(0x4, "uart2")), /* RX */
43 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4, 55 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA4,
44 SUNXI_FUNCTION(0x0, "gpio_in"), 56 SUNXI_FUNCTION(0x0, "gpio_in"),
45 SUNXI_FUNCTION(0x1, "gpio_out")), 57 SUNXI_FUNCTION(0x1, "gpio_out"),
58 SUNXI_FUNCTION(0x2, "wemac"), /* ETXD3 */
59 SUNXI_FUNCTION(0x3, "spi1")), /* CS1 */
46 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5, 60 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA5,
47 SUNXI_FUNCTION(0x0, "gpio_in"), 61 SUNXI_FUNCTION(0x0, "gpio_in"),
48 SUNXI_FUNCTION(0x1, "gpio_out")), 62 SUNXI_FUNCTION(0x1, "gpio_out"),
63 SUNXI_FUNCTION(0x2, "wemac"), /* ETXD2 */
64 SUNXI_FUNCTION(0x3, "spi3")), /* CS0 */
49 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6, 65 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA6,
50 SUNXI_FUNCTION(0x0, "gpio_in"), 66 SUNXI_FUNCTION(0x0, "gpio_in"),
51 SUNXI_FUNCTION(0x1, "gpio_out")), 67 SUNXI_FUNCTION(0x1, "gpio_out"),
68 SUNXI_FUNCTION(0x2, "wemac"), /* ETXD1 */
69 SUNXI_FUNCTION(0x3, "spi3")), /* CLK */
52 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7, 70 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA7,
53 SUNXI_FUNCTION(0x0, "gpio_in"), 71 SUNXI_FUNCTION(0x0, "gpio_in"),
54 SUNXI_FUNCTION(0x1, "gpio_out")), 72 SUNXI_FUNCTION(0x1, "gpio_out"),
73 SUNXI_FUNCTION(0x2, "wemac"), /* ETXD0 */
74 SUNXI_FUNCTION(0x3, "spi3")), /* MOSI */
55 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8, 75 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA8,
56 SUNXI_FUNCTION(0x0, "gpio_in"), 76 SUNXI_FUNCTION(0x0, "gpio_in"),
57 SUNXI_FUNCTION(0x1, "gpio_out")), 77 SUNXI_FUNCTION(0x1, "gpio_out"),
78 SUNXI_FUNCTION(0x2, "wemac"), /* ERXCK */
79 SUNXI_FUNCTION(0x3, "spi3")), /* MISO */
58 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9, 80 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA9,
59 SUNXI_FUNCTION(0x0, "gpio_in"), 81 SUNXI_FUNCTION(0x0, "gpio_in"),
60 SUNXI_FUNCTION(0x1, "gpio_out")), 82 SUNXI_FUNCTION(0x1, "gpio_out"),
83 SUNXI_FUNCTION(0x2, "wemac"), /* ERXERR */
84 SUNXI_FUNCTION(0x3, "spi3")), /* CS1 */
61 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10, 85 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA10,
62 SUNXI_FUNCTION(0x0, "gpio_in"), 86 SUNXI_FUNCTION(0x0, "gpio_in"),
63 SUNXI_FUNCTION(0x1, "gpio_out"), 87 SUNXI_FUNCTION(0x1, "gpio_out"),
88 SUNXI_FUNCTION(0x2, "wemac"), /* ERXDV */
64 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 89 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
65 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11, 90 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA11,
66 SUNXI_FUNCTION(0x0, "gpio_in"), 91 SUNXI_FUNCTION(0x0, "gpio_in"),
67 SUNXI_FUNCTION(0x1, "gpio_out"), 92 SUNXI_FUNCTION(0x1, "gpio_out"),
93 SUNXI_FUNCTION(0x2, "wemac"), /* EMDC */
68 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 94 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
69 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12, 95 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA12,
70 SUNXI_FUNCTION(0x0, "gpio_in"), 96 SUNXI_FUNCTION(0x0, "gpio_in"),
71 SUNXI_FUNCTION(0x1, "gpio_out"), 97 SUNXI_FUNCTION(0x1, "gpio_out"),
98 SUNXI_FUNCTION(0x2, "wemac"), /* EMDIO */
99 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
72 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */ 100 SUNXI_FUNCTION(0x4, "uart1")), /* RTS */
73 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13, 101 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA13,
74 SUNXI_FUNCTION(0x0, "gpio_in"), 102 SUNXI_FUNCTION(0x0, "gpio_in"),
75 SUNXI_FUNCTION(0x1, "gpio_out"), 103 SUNXI_FUNCTION(0x1, "gpio_out"),
104 SUNXI_FUNCTION(0x2, "wemac"), /* ETXEN */
105 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
76 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */ 106 SUNXI_FUNCTION(0x4, "uart1")), /* CTS */
77 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14, 107 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA14,
78 SUNXI_FUNCTION(0x0, "gpio_in"), 108 SUNXI_FUNCTION(0x0, "gpio_in"),
79 SUNXI_FUNCTION(0x1, "gpio_out"), 109 SUNXI_FUNCTION(0x1, "gpio_out"),
110 SUNXI_FUNCTION(0x2, "wemac"), /* ETXCK */
111 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
80 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */ 112 SUNXI_FUNCTION(0x4, "uart1")), /* DTR */
81 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15, 113 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA15,
82 SUNXI_FUNCTION(0x0, "gpio_in"), 114 SUNXI_FUNCTION(0x0, "gpio_in"),
83 SUNXI_FUNCTION(0x1, "gpio_out"), 115 SUNXI_FUNCTION(0x1, "gpio_out"),
116 SUNXI_FUNCTION(0x2, "wemac"), /* ECRS */
117 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
84 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */ 118 SUNXI_FUNCTION(0x4, "uart1")), /* DSR */
85 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16, 119 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA16,
86 SUNXI_FUNCTION(0x0, "gpio_in"), 120 SUNXI_FUNCTION(0x0, "gpio_in"),
87 SUNXI_FUNCTION(0x1, "gpio_out"), 121 SUNXI_FUNCTION(0x1, "gpio_out"),
122 SUNXI_FUNCTION(0x2, "wemac"), /* ECOL */
123 SUNXI_FUNCTION(0x3, "can"), /* TX */
88 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */ 124 SUNXI_FUNCTION(0x4, "uart1")), /* DCD */
89 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17, 125 SUNXI_PIN(SUNXI_PINCTRL_PIN_PA17,
90 SUNXI_FUNCTION(0x0, "gpio_in"), 126 SUNXI_FUNCTION(0x0, "gpio_in"),
91 SUNXI_FUNCTION(0x1, "gpio_out"), 127 SUNXI_FUNCTION(0x1, "gpio_out"),
128 SUNXI_FUNCTION(0x2, "wemac"), /* ETXERR */
129 SUNXI_FUNCTION(0x3, "can"), /* RX */
92 SUNXI_FUNCTION(0x4, "uart1")), /* RING */ 130 SUNXI_FUNCTION(0x4, "uart1")), /* RING */
93 /* Hole */ 131 /* Hole */
94 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, 132 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
95 SUNXI_FUNCTION(0x0, "gpio_in"), 133 SUNXI_FUNCTION(0x0, "gpio_in"),
96 SUNXI_FUNCTION(0x1, "gpio_out")), 134 SUNXI_FUNCTION(0x1, "gpio_out"),
135 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
97 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, 136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
98 SUNXI_FUNCTION(0x0, "gpio_in"), 137 SUNXI_FUNCTION(0x0, "gpio_in"),
99 SUNXI_FUNCTION(0x1, "gpio_out")), 138 SUNXI_FUNCTION(0x1, "gpio_out"),
139 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
100 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, 140 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
101 SUNXI_FUNCTION(0x0, "gpio_in"), 141 SUNXI_FUNCTION(0x0, "gpio_in"),
102 SUNXI_FUNCTION(0x1, "gpio_out")), 142 SUNXI_FUNCTION(0x1, "gpio_out"),
143 SUNXI_FUNCTION(0x2, "pwm")), /* PWM0 */
103 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, 144 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
104 SUNXI_FUNCTION(0x0, "gpio_in"), 145 SUNXI_FUNCTION(0x0, "gpio_in"),
105 SUNXI_FUNCTION(0x1, "gpio_out")), 146 SUNXI_FUNCTION(0x1, "gpio_out"),
147 SUNXI_FUNCTION(0x2, "ir0")), /* TX */
106 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, 148 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
107 SUNXI_FUNCTION(0x0, "gpio_in"), 149 SUNXI_FUNCTION(0x0, "gpio_in"),
108 SUNXI_FUNCTION(0x1, "gpio_out")), 150 SUNXI_FUNCTION(0x1, "gpio_out"),
151 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
109 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5, 152 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB5,
110 SUNXI_FUNCTION(0x0, "gpio_in"), 153 SUNXI_FUNCTION(0x0, "gpio_in"),
111 SUNXI_FUNCTION(0x1, "gpio_out")), 154 SUNXI_FUNCTION(0x1, "gpio_out"),
155 SUNXI_FUNCTION(0x2, "i2s"), /* MCLK */
156 SUNXI_FUNCTION(0x3, "ac97")), /* MCLK */
112 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6, 157 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB6,
113 SUNXI_FUNCTION(0x0, "gpio_in"), 158 SUNXI_FUNCTION(0x0, "gpio_in"),
114 SUNXI_FUNCTION(0x1, "gpio_out")), 159 SUNXI_FUNCTION(0x1, "gpio_out"),
160 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
161 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
115 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7, 162 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB7,
116 SUNXI_FUNCTION(0x0, "gpio_in"), 163 SUNXI_FUNCTION(0x0, "gpio_in"),
117 SUNXI_FUNCTION(0x1, "gpio_out")), 164 SUNXI_FUNCTION(0x1, "gpio_out"),
165 SUNXI_FUNCTION(0x2, "i2s"), /* LRCK */
166 SUNXI_FUNCTION(0x3, "ac97")), /* SYNC */
118 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8, 167 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB8,
119 SUNXI_FUNCTION(0x0, "gpio_in"), 168 SUNXI_FUNCTION(0x0, "gpio_in"),
120 SUNXI_FUNCTION(0x1, "gpio_out")), 169 SUNXI_FUNCTION(0x1, "gpio_out"),
170 SUNXI_FUNCTION(0x2, "i2s"), /* DO0 */
171 SUNXI_FUNCTION(0x3, "ac97")), /* DO */
121 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9, 172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB9,
122 SUNXI_FUNCTION(0x0, "gpio_in"), 173 SUNXI_FUNCTION(0x0, "gpio_in"),
123 SUNXI_FUNCTION(0x1, "gpio_out")), 174 SUNXI_FUNCTION(0x1, "gpio_out"),
175 SUNXI_FUNCTION(0x2, "i2s")), /* DO1 */
124 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, 176 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
125 SUNXI_FUNCTION(0x0, "gpio_in"), 177 SUNXI_FUNCTION(0x0, "gpio_in"),
126 SUNXI_FUNCTION(0x1, "gpio_out")), 178 SUNXI_FUNCTION(0x1, "gpio_out"),
179 SUNXI_FUNCTION(0x2, "i2s")), /* DO2 */
127 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11, 180 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB11,
128 SUNXI_FUNCTION(0x0, "gpio_in"), 181 SUNXI_FUNCTION(0x0, "gpio_in"),
129 SUNXI_FUNCTION(0x1, "gpio_out")), 182 SUNXI_FUNCTION(0x1, "gpio_out"),
183 SUNXI_FUNCTION(0x2, "i2s")), /* DO3 */
130 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12, 184 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB12,
131 SUNXI_FUNCTION(0x0, "gpio_in"), 185 SUNXI_FUNCTION(0x0, "gpio_in"),
132 SUNXI_FUNCTION(0x1, "gpio_out")), 186 SUNXI_FUNCTION(0x1, "gpio_out"),
187 SUNXI_FUNCTION(0x2, "i2s"), /* DI */
188 SUNXI_FUNCTION(0x3, "ac97")), /* DI */
133 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13, 189 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB13,
134 SUNXI_FUNCTION(0x0, "gpio_in"), 190 SUNXI_FUNCTION(0x0, "gpio_in"),
135 SUNXI_FUNCTION(0x1, "gpio_out")), 191 SUNXI_FUNCTION(0x1, "gpio_out"),
192 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
136 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14, 193 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB14,
137 SUNXI_FUNCTION(0x0, "gpio_in"), 194 SUNXI_FUNCTION(0x0, "gpio_in"),
138 SUNXI_FUNCTION(0x1, "gpio_out")), 195 SUNXI_FUNCTION(0x1, "gpio_out"),
196 SUNXI_FUNCTION(0x2, "spi2"), /* CS0 */
197 SUNXI_FUNCTION(0x3, "jtag")), /* MS0 */
139 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, 198 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
140 SUNXI_FUNCTION(0x0, "gpio_in"), 199 SUNXI_FUNCTION(0x0, "gpio_in"),
141 SUNXI_FUNCTION(0x1, "gpio_out")), 200 SUNXI_FUNCTION(0x1, "gpio_out"),
201 SUNXI_FUNCTION(0x2, "spi2"), /* CLK */
202 SUNXI_FUNCTION(0x3, "jtag")), /* CK0 */
142 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, 203 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
143 SUNXI_FUNCTION(0x0, "gpio_in"), 204 SUNXI_FUNCTION(0x0, "gpio_in"),
144 SUNXI_FUNCTION(0x1, "gpio_out")), 205 SUNXI_FUNCTION(0x1, "gpio_out"),
206 SUNXI_FUNCTION(0x2, "spi2"), /* MOSI */
207 SUNXI_FUNCTION(0x3, "jtag")), /* DO0 */
145 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, 208 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
146 SUNXI_FUNCTION(0x0, "gpio_in"), 209 SUNXI_FUNCTION(0x0, "gpio_in"),
147 SUNXI_FUNCTION(0x1, "gpio_out")), 210 SUNXI_FUNCTION(0x1, "gpio_out"),
211 SUNXI_FUNCTION(0x2, "spi2"), /* MISO */
212 SUNXI_FUNCTION(0x3, "jtag")), /* DI0 */
148 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, 213 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
149 SUNXI_FUNCTION(0x0, "gpio_in"), 214 SUNXI_FUNCTION(0x0, "gpio_in"),
150 SUNXI_FUNCTION(0x1, "gpio_out")), 215 SUNXI_FUNCTION(0x1, "gpio_out"),
216 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
151 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19, 217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB19,
152 SUNXI_FUNCTION(0x0, "gpio_in"), 218 SUNXI_FUNCTION(0x0, "gpio_in"),
153 SUNXI_FUNCTION(0x1, "gpio_out")), 219 SUNXI_FUNCTION(0x1, "gpio_out"),
220 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
154 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20, 221 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB20,
155 SUNXI_FUNCTION(0x0, "gpio_in"), 222 SUNXI_FUNCTION(0x0, "gpio_in"),
156 SUNXI_FUNCTION(0x1, "gpio_out")), 223 SUNXI_FUNCTION(0x1, "gpio_out"),
224 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
157 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21, 225 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB21,
158 SUNXI_FUNCTION(0x0, "gpio_in"), 226 SUNXI_FUNCTION(0x0, "gpio_in"),
159 SUNXI_FUNCTION(0x1, "gpio_out")), 227 SUNXI_FUNCTION(0x1, "gpio_out"),
228 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
160 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22, 229 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB22,
161 SUNXI_FUNCTION(0x0, "gpio_in"), 230 SUNXI_FUNCTION(0x0, "gpio_in"),
162 SUNXI_FUNCTION(0x1, "gpio_out"), 231 SUNXI_FUNCTION(0x1, "gpio_out"),
163 SUNXI_FUNCTION(0x2, "uart0")), /* TX */ 232 SUNXI_FUNCTION(0x2, "uart0"), /* TX */
233 SUNXI_FUNCTION(0x3, "ir1")), /* TX */
164 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23, 234 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB23,
165 SUNXI_FUNCTION(0x0, "gpio_in"), 235 SUNXI_FUNCTION(0x0, "gpio_in"),
166 SUNXI_FUNCTION(0x1, "gpio_out"), 236 SUNXI_FUNCTION(0x1, "gpio_out"),
167 SUNXI_FUNCTION(0x2, "uart0")), /* RX */ 237 SUNXI_FUNCTION(0x2, "uart0"), /* RX */
238 SUNXI_FUNCTION(0x3, "ir1")), /* RX */
168 /* Hole */ 239 /* Hole */
169 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, 240 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
170 SUNXI_FUNCTION(0x0, "gpio_in"), 241 SUNXI_FUNCTION(0x0, "gpio_in"),
171 SUNXI_FUNCTION(0x1, "gpio_out")), 242 SUNXI_FUNCTION(0x1, "gpio_out"),
243 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
244 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
172 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, 245 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
173 SUNXI_FUNCTION(0x0, "gpio_in"), 246 SUNXI_FUNCTION(0x0, "gpio_in"),
174 SUNXI_FUNCTION(0x1, "gpio_out")), 247 SUNXI_FUNCTION(0x1, "gpio_out"),
248 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
249 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
175 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, 250 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
176 SUNXI_FUNCTION(0x0, "gpio_in"), 251 SUNXI_FUNCTION(0x0, "gpio_in"),
177 SUNXI_FUNCTION(0x1, "gpio_out")), 252 SUNXI_FUNCTION(0x1, "gpio_out"),
253 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
254 SUNXI_FUNCTION(0x3, "spi0")), /* SCK */
178 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, 255 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
179 SUNXI_FUNCTION(0x0, "gpio_in"), 256 SUNXI_FUNCTION(0x0, "gpio_in"),
180 SUNXI_FUNCTION(0x1, "gpio_out")), 257 SUNXI_FUNCTION(0x1, "gpio_out"),
258 SUNXI_FUNCTION(0x2, "nand0")), /* NCE1 */
181 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, 259 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
182 SUNXI_FUNCTION(0x0, "gpio_in"), 260 SUNXI_FUNCTION(0x0, "gpio_in"),
183 SUNXI_FUNCTION(0x1, "gpio_out")), 261 SUNXI_FUNCTION(0x1, "gpio_out"),
262 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
184 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, 263 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
185 SUNXI_FUNCTION(0x0, "gpio_in"), 264 SUNXI_FUNCTION(0x0, "gpio_in"),
186 SUNXI_FUNCTION(0x1, "gpio_out")), 265 SUNXI_FUNCTION(0x1, "gpio_out"),
266 SUNXI_FUNCTION(0x2, "nand0")), /* NRE# */
187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, 267 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
188 SUNXI_FUNCTION(0x0, "gpio_in"), 268 SUNXI_FUNCTION(0x0, "gpio_in"),
189 SUNXI_FUNCTION(0x1, "gpio_out")), 269 SUNXI_FUNCTION(0x1, "gpio_out"),
270 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
271 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
190 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, 272 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
191 SUNXI_FUNCTION(0x0, "gpio_in"), 273 SUNXI_FUNCTION(0x0, "gpio_in"),
192 SUNXI_FUNCTION(0x1, "gpio_out")), 274 SUNXI_FUNCTION(0x1, "gpio_out"),
275 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
276 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
193 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, 277 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
194 SUNXI_FUNCTION(0x0, "gpio_in"), 278 SUNXI_FUNCTION(0x0, "gpio_in"),
195 SUNXI_FUNCTION(0x1, "gpio_out")), 279 SUNXI_FUNCTION(0x1, "gpio_out"),
280 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
281 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
196 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, 282 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
197 SUNXI_FUNCTION(0x0, "gpio_in"), 283 SUNXI_FUNCTION(0x0, "gpio_in"),
198 SUNXI_FUNCTION(0x1, "gpio_out")), 284 SUNXI_FUNCTION(0x1, "gpio_out"),
285 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
286 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
199 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, 287 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
200 SUNXI_FUNCTION(0x0, "gpio_in"), 288 SUNXI_FUNCTION(0x0, "gpio_in"),
201 SUNXI_FUNCTION(0x1, "gpio_out")), 289 SUNXI_FUNCTION(0x1, "gpio_out"),
290 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
291 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
202 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, 292 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
203 SUNXI_FUNCTION(0x0, "gpio_in"), 293 SUNXI_FUNCTION(0x0, "gpio_in"),
204 SUNXI_FUNCTION(0x1, "gpio_out")), 294 SUNXI_FUNCTION(0x1, "gpio_out"),
295 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
296 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
205 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, 297 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
206 SUNXI_FUNCTION(0x0, "gpio_in"), 298 SUNXI_FUNCTION(0x0, "gpio_in"),
207 SUNXI_FUNCTION(0x1, "gpio_out")), 299 SUNXI_FUNCTION(0x1, "gpio_out"),
300 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */
208 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, 301 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
209 SUNXI_FUNCTION(0x0, "gpio_in"), 302 SUNXI_FUNCTION(0x0, "gpio_in"),
210 SUNXI_FUNCTION(0x1, "gpio_out")), 303 SUNXI_FUNCTION(0x1, "gpio_out"),
304 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */
211 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, 305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
212 SUNXI_FUNCTION(0x0, "gpio_in"), 306 SUNXI_FUNCTION(0x0, "gpio_in"),
213 SUNXI_FUNCTION(0x1, "gpio_out")), 307 SUNXI_FUNCTION(0x1, "gpio_out"),
308 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */
214 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, 309 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
215 SUNXI_FUNCTION(0x0, "gpio_in"), 310 SUNXI_FUNCTION(0x0, "gpio_in"),
216 SUNXI_FUNCTION(0x1, "gpio_out")), 311 SUNXI_FUNCTION(0x1, "gpio_out"),
312 SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */
217 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16, 313 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC16,
218 SUNXI_FUNCTION(0x0, "gpio_in"), 314 SUNXI_FUNCTION(0x0, "gpio_in"),
219 SUNXI_FUNCTION(0x1, "gpio_out")), 315 SUNXI_FUNCTION(0x1, "gpio_out"),
316 SUNXI_FUNCTION(0x2, "nand0")), /* NWP */
220 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17, 317 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC17,
221 SUNXI_FUNCTION(0x0, "gpio_in"), 318 SUNXI_FUNCTION(0x0, "gpio_in"),
222 SUNXI_FUNCTION(0x1, "gpio_out")), 319 SUNXI_FUNCTION(0x1, "gpio_out"),
320 SUNXI_FUNCTION(0x2, "nand0")), /* NCE2 */
223 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18, 321 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC18,
224 SUNXI_FUNCTION(0x0, "gpio_in"), 322 SUNXI_FUNCTION(0x0, "gpio_in"),
225 SUNXI_FUNCTION(0x1, "gpio_out")), 323 SUNXI_FUNCTION(0x1, "gpio_out"),
324 SUNXI_FUNCTION(0x2, "nand0")), /* NCE3 */
226 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, 325 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
227 SUNXI_FUNCTION(0x0, "gpio_in"), 326 SUNXI_FUNCTION(0x0, "gpio_in"),
228 SUNXI_FUNCTION(0x1, "gpio_out")), 327 SUNXI_FUNCTION(0x1, "gpio_out"),
328 SUNXI_FUNCTION(0x2, "nand0"), /* NCE4 */
329 SUNXI_FUNCTION(0x3, "spi2")), /* CS0 */
229 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20, 330 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC20,
230 SUNXI_FUNCTION(0x0, "gpio_in"), 331 SUNXI_FUNCTION(0x0, "gpio_in"),
231 SUNXI_FUNCTION(0x1, "gpio_out")), 332 SUNXI_FUNCTION(0x1, "gpio_out"),
333 SUNXI_FUNCTION(0x2, "nand0"), /* NCE5 */
334 SUNXI_FUNCTION(0x3, "spi2")), /* CLK */
232 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21, 335 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC21,
233 SUNXI_FUNCTION(0x0, "gpio_in"), 336 SUNXI_FUNCTION(0x0, "gpio_in"),
234 SUNXI_FUNCTION(0x1, "gpio_out")), 337 SUNXI_FUNCTION(0x1, "gpio_out"),
338 SUNXI_FUNCTION(0x2, "nand0"), /* NCE6 */
339 SUNXI_FUNCTION(0x3, "spi2")), /* MOSI */
235 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22, 340 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC22,
236 SUNXI_FUNCTION(0x0, "gpio_in"), 341 SUNXI_FUNCTION(0x0, "gpio_in"),
237 SUNXI_FUNCTION(0x1, "gpio_out")), 342 SUNXI_FUNCTION(0x1, "gpio_out"),
343 SUNXI_FUNCTION(0x2, "nand0"), /* NCE7 */
344 SUNXI_FUNCTION(0x3, "spi2")), /* MISO */
238 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23, 345 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC23,
239 SUNXI_FUNCTION(0x0, "gpio_in"), 346 SUNXI_FUNCTION(0x0, "gpio_in"),
240 SUNXI_FUNCTION(0x1, "gpio_out")), 347 SUNXI_FUNCTION(0x1, "gpio_out"),
348 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
241 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24, 349 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC24,
242 SUNXI_FUNCTION(0x0, "gpio_in"), 350 SUNXI_FUNCTION(0x0, "gpio_in"),
243 SUNXI_FUNCTION(0x1, "gpio_out")), 351 SUNXI_FUNCTION(0x1, "gpio_out"),
352 SUNXI_FUNCTION(0x2, "nand0")), /* NDQS */
244 /* Hole */ 353 /* Hole */
245 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0, 354 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD0,
246 SUNXI_FUNCTION(0x0, "gpio_in"), 355 SUNXI_FUNCTION(0x0, "gpio_in"),
247 SUNXI_FUNCTION(0x1, "gpio_out")), 356 SUNXI_FUNCTION(0x1, "gpio_out"),
357 SUNXI_FUNCTION(0x2, "lcd0"), /* D0 */
358 SUNXI_FUNCTION(0x3, "lvds0")), /* VP0 */
248 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1, 359 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD1,
249 SUNXI_FUNCTION(0x0, "gpio_in"), 360 SUNXI_FUNCTION(0x0, "gpio_in"),
250 SUNXI_FUNCTION(0x1, "gpio_out")), 361 SUNXI_FUNCTION(0x1, "gpio_out"),
362 SUNXI_FUNCTION(0x2, "lcd0"), /* D1 */
363 SUNXI_FUNCTION(0x3, "lvds0")), /* VN0 */
251 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, 364 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
252 SUNXI_FUNCTION(0x0, "gpio_in"), 365 SUNXI_FUNCTION(0x0, "gpio_in"),
253 SUNXI_FUNCTION(0x1, "gpio_out")), 366 SUNXI_FUNCTION(0x1, "gpio_out"),
367 SUNXI_FUNCTION(0x2, "lcd0"), /* D2 */
368 SUNXI_FUNCTION(0x3, "lvds0")), /* VP1 */
254 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, 369 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
255 SUNXI_FUNCTION(0x0, "gpio_in"), 370 SUNXI_FUNCTION(0x0, "gpio_in"),
256 SUNXI_FUNCTION(0x1, "gpio_out")), 371 SUNXI_FUNCTION(0x1, "gpio_out"),
372 SUNXI_FUNCTION(0x2, "lcd0"), /* D3 */
373 SUNXI_FUNCTION(0x3, "lvds0")), /* VN1 */
257 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, 374 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
258 SUNXI_FUNCTION(0x0, "gpio_in"), 375 SUNXI_FUNCTION(0x0, "gpio_in"),
259 SUNXI_FUNCTION(0x1, "gpio_out")), 376 SUNXI_FUNCTION(0x1, "gpio_out"),
377 SUNXI_FUNCTION(0x2, "lcd0"), /* D4 */
378 SUNXI_FUNCTION(0x3, "lvds0")), /* VP2 */
260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, 379 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
261 SUNXI_FUNCTION(0x0, "gpio_in"), 380 SUNXI_FUNCTION(0x0, "gpio_in"),
262 SUNXI_FUNCTION(0x1, "gpio_out")), 381 SUNXI_FUNCTION(0x1, "gpio_out"),
382 SUNXI_FUNCTION(0x2, "lcd0"), /* D5 */
383 SUNXI_FUNCTION(0x3, "lvds0")), /* VN2 */
263 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, 384 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
264 SUNXI_FUNCTION(0x0, "gpio_in"), 385 SUNXI_FUNCTION(0x0, "gpio_in"),
265 SUNXI_FUNCTION(0x1, "gpio_out")), 386 SUNXI_FUNCTION(0x1, "gpio_out"),
387 SUNXI_FUNCTION(0x2, "lcd0"), /* D6 */
388 SUNXI_FUNCTION(0x3, "lvds0")), /* VPC */
266 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, 389 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
267 SUNXI_FUNCTION(0x0, "gpio_in"), 390 SUNXI_FUNCTION(0x0, "gpio_in"),
268 SUNXI_FUNCTION(0x1, "gpio_out")), 391 SUNXI_FUNCTION(0x1, "gpio_out"),
392 SUNXI_FUNCTION(0x2, "lcd0"), /* D7 */
393 SUNXI_FUNCTION(0x3, "lvds0")), /* VNC */
269 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8, 394 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD8,
270 SUNXI_FUNCTION(0x0, "gpio_in"), 395 SUNXI_FUNCTION(0x0, "gpio_in"),
271 SUNXI_FUNCTION(0x1, "gpio_out")), 396 SUNXI_FUNCTION(0x1, "gpio_out"),
397 SUNXI_FUNCTION(0x2, "lcd0"), /* D8 */
398 SUNXI_FUNCTION(0x3, "lvds0")), /* VP3 */
272 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9, 399 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD9,
273 SUNXI_FUNCTION(0x0, "gpio_in"), 400 SUNXI_FUNCTION(0x0, "gpio_in"),
274 SUNXI_FUNCTION(0x1, "gpio_out")), 401 SUNXI_FUNCTION(0x1, "gpio_out"),
402 SUNXI_FUNCTION(0x2, "lcd0"), /* D9 */
403 SUNXI_FUNCTION(0x3, "lvds0")), /* VM3 */
275 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, 404 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
276 SUNXI_FUNCTION(0x0, "gpio_in"), 405 SUNXI_FUNCTION(0x0, "gpio_in"),
277 SUNXI_FUNCTION(0x1, "gpio_out")), 406 SUNXI_FUNCTION(0x1, "gpio_out"),
407 SUNXI_FUNCTION(0x2, "lcd0"), /* D10 */
408 SUNXI_FUNCTION(0x3, "lvds1")), /* VP0 */
278 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, 409 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
279 SUNXI_FUNCTION(0x0, "gpio_in"), 410 SUNXI_FUNCTION(0x0, "gpio_in"),
280 SUNXI_FUNCTION(0x1, "gpio_out")), 411 SUNXI_FUNCTION(0x1, "gpio_out"),
412 SUNXI_FUNCTION(0x2, "lcd0"), /* D11 */
413 SUNXI_FUNCTION(0x3, "lvds1")), /* VN0 */
281 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, 414 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
282 SUNXI_FUNCTION(0x0, "gpio_in"), 415 SUNXI_FUNCTION(0x0, "gpio_in"),
283 SUNXI_FUNCTION(0x1, "gpio_out")), 416 SUNXI_FUNCTION(0x1, "gpio_out"),
417 SUNXI_FUNCTION(0x2, "lcd0"), /* D12 */
418 SUNXI_FUNCTION(0x3, "lvds1")), /* VP1 */
284 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, 419 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
285 SUNXI_FUNCTION(0x0, "gpio_in"), 420 SUNXI_FUNCTION(0x0, "gpio_in"),
286 SUNXI_FUNCTION(0x1, "gpio_out")), 421 SUNXI_FUNCTION(0x1, "gpio_out"),
422 SUNXI_FUNCTION(0x2, "lcd0"), /* D13 */
423 SUNXI_FUNCTION(0x3, "lvds1")), /* VN1 */
287 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, 424 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
288 SUNXI_FUNCTION(0x0, "gpio_in"), 425 SUNXI_FUNCTION(0x0, "gpio_in"),
289 SUNXI_FUNCTION(0x1, "gpio_out")), 426 SUNXI_FUNCTION(0x1, "gpio_out"),
427 SUNXI_FUNCTION(0x2, "lcd0"), /* D14 */
428 SUNXI_FUNCTION(0x3, "lvds1")), /* VP2 */
290 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, 429 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
291 SUNXI_FUNCTION(0x0, "gpio_in"), 430 SUNXI_FUNCTION(0x0, "gpio_in"),
292 SUNXI_FUNCTION(0x1, "gpio_out")), 431 SUNXI_FUNCTION(0x1, "gpio_out"),
432 SUNXI_FUNCTION(0x2, "lcd0"), /* D15 */
433 SUNXI_FUNCTION(0x3, "lvds1")), /* VN2 */
293 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16, 434 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD16,
294 SUNXI_FUNCTION(0x0, "gpio_in"), 435 SUNXI_FUNCTION(0x0, "gpio_in"),
295 SUNXI_FUNCTION(0x1, "gpio_out")), 436 SUNXI_FUNCTION(0x1, "gpio_out"),
437 SUNXI_FUNCTION(0x2, "lcd0"), /* D16 */
438 SUNXI_FUNCTION(0x3, "lvds1")), /* VPC */
296 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17, 439 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD17,
297 SUNXI_FUNCTION(0x0, "gpio_in"), 440 SUNXI_FUNCTION(0x0, "gpio_in"),
298 SUNXI_FUNCTION(0x1, "gpio_out")), 441 SUNXI_FUNCTION(0x1, "gpio_out"),
442 SUNXI_FUNCTION(0x2, "lcd0"), /* D17 */
443 SUNXI_FUNCTION(0x3, "lvds1")), /* VNC */
299 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, 444 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
300 SUNXI_FUNCTION(0x0, "gpio_in"), 445 SUNXI_FUNCTION(0x0, "gpio_in"),
301 SUNXI_FUNCTION(0x1, "gpio_out")), 446 SUNXI_FUNCTION(0x1, "gpio_out"),
447 SUNXI_FUNCTION(0x2, "lcd0"), /* D18 */
448 SUNXI_FUNCTION(0x3, "lvds1")), /* VP3 */
302 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, 449 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
303 SUNXI_FUNCTION(0x0, "gpio_in"), 450 SUNXI_FUNCTION(0x0, "gpio_in"),
304 SUNXI_FUNCTION(0x1, "gpio_out")), 451 SUNXI_FUNCTION(0x1, "gpio_out"),
452 SUNXI_FUNCTION(0x2, "lcd0"), /* D19 */
453 SUNXI_FUNCTION(0x3, "lvds1")), /* VN3 */
305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, 454 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
306 SUNXI_FUNCTION(0x0, "gpio_in"), 455 SUNXI_FUNCTION(0x0, "gpio_in"),
307 SUNXI_FUNCTION(0x1, "gpio_out")), 456 SUNXI_FUNCTION(0x1, "gpio_out"),
457 SUNXI_FUNCTION(0x2, "lcd0"), /* D20 */
458 SUNXI_FUNCTION(0x3, "csi1")), /* MCLK */
308 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, 459 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
309 SUNXI_FUNCTION(0x0, "gpio_in"), 460 SUNXI_FUNCTION(0x0, "gpio_in"),
310 SUNXI_FUNCTION(0x1, "gpio_out")), 461 SUNXI_FUNCTION(0x1, "gpio_out"),
462 SUNXI_FUNCTION(0x2, "lcd0"), /* D21 */
463 SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
311 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, 464 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
312 SUNXI_FUNCTION(0x0, "gpio_in"), 465 SUNXI_FUNCTION(0x0, "gpio_in"),
313 SUNXI_FUNCTION(0x1, "gpio_out")), 466 SUNXI_FUNCTION(0x1, "gpio_out"),
467 SUNXI_FUNCTION(0x2, "lcd0"), /* D22 */
468 SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
314 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, 469 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
315 SUNXI_FUNCTION(0x0, "gpio_in"), 470 SUNXI_FUNCTION(0x0, "gpio_in"),
316 SUNXI_FUNCTION(0x1, "gpio_out")), 471 SUNXI_FUNCTION(0x1, "gpio_out"),
472 SUNXI_FUNCTION(0x2, "lcd0"), /* D23 */
473 SUNXI_FUNCTION(0x3, "sim")), /* DET */
317 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, 474 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
318 SUNXI_FUNCTION(0x0, "gpio_in"), 475 SUNXI_FUNCTION(0x0, "gpio_in"),
319 SUNXI_FUNCTION(0x1, "gpio_out")), 476 SUNXI_FUNCTION(0x1, "gpio_out"),
477 SUNXI_FUNCTION(0x2, "lcd0"), /* CLK */
478 SUNXI_FUNCTION(0x3, "sim")), /* VCCEN */
320 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, 479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
321 SUNXI_FUNCTION(0x0, "gpio_in"), 480 SUNXI_FUNCTION(0x0, "gpio_in"),
322 SUNXI_FUNCTION(0x1, "gpio_out")), 481 SUNXI_FUNCTION(0x1, "gpio_out"),
482 SUNXI_FUNCTION(0x2, "lcd0"), /* DE */
483 SUNXI_FUNCTION(0x3, "sim")), /* RST */
323 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, 484 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
324 SUNXI_FUNCTION(0x0, "gpio_in"), 485 SUNXI_FUNCTION(0x0, "gpio_in"),
325 SUNXI_FUNCTION(0x1, "gpio_out")), 486 SUNXI_FUNCTION(0x1, "gpio_out"),
487 SUNXI_FUNCTION(0x2, "lcd0"), /* HSYNC */
488 SUNXI_FUNCTION(0x3, "sim")), /* SCK */
326 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, 489 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
327 SUNXI_FUNCTION(0x0, "gpio_in"), 490 SUNXI_FUNCTION(0x0, "gpio_in"),
328 SUNXI_FUNCTION(0x1, "gpio_out")), 491 SUNXI_FUNCTION(0x1, "gpio_out"),
492 SUNXI_FUNCTION(0x2, "lcd0"), /* VSYNC */
493 SUNXI_FUNCTION(0x3, "sim")), /* SDA */
329 /* Hole */ 494 /* Hole */
330 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, 495 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
331 SUNXI_FUNCTION(0x0, "gpio_in"), 496 SUNXI_FUNCTION(0x0, "gpio_in"),
332 SUNXI_FUNCTION(0x1, "gpio_out")), 497 SUNXI_FUNCTION(0x1, "gpio_out"),
498 SUNXI_FUNCTION(0x2, "ts0"), /* CLK */
499 SUNXI_FUNCTION(0x3, "csi0")), /* PCK */
333 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, 500 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
334 SUNXI_FUNCTION(0x0, "gpio_in"), 501 SUNXI_FUNCTION(0x0, "gpio_in"),
335 SUNXI_FUNCTION(0x1, "gpio_out")), 502 SUNXI_FUNCTION(0x1, "gpio_out"),
503 SUNXI_FUNCTION(0x2, "ts0"), /* ERR */
504 SUNXI_FUNCTION(0x3, "csi0")), /* CK */
336 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, 505 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
337 SUNXI_FUNCTION(0x0, "gpio_in"), 506 SUNXI_FUNCTION(0x0, "gpio_in"),
338 SUNXI_FUNCTION(0x1, "gpio_out")), 507 SUNXI_FUNCTION(0x1, "gpio_out"),
508 SUNXI_FUNCTION(0x2, "ts0"), /* SYNC */
509 SUNXI_FUNCTION(0x3, "csi0")), /* HSYNC */
339 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, 510 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
340 SUNXI_FUNCTION(0x0, "gpio_in"), 511 SUNXI_FUNCTION(0x0, "gpio_in"),
341 SUNXI_FUNCTION(0x1, "gpio_out")), 512 SUNXI_FUNCTION(0x1, "gpio_out"),
513 SUNXI_FUNCTION(0x2, "ts0"), /* DVLD */
514 SUNXI_FUNCTION(0x3, "csi0")), /* VSYNC */
342 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, 515 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
343 SUNXI_FUNCTION(0x0, "gpio_in"), 516 SUNXI_FUNCTION(0x0, "gpio_in"),
344 SUNXI_FUNCTION(0x1, "gpio_out")), 517 SUNXI_FUNCTION(0x1, "gpio_out"),
518 SUNXI_FUNCTION(0x2, "ts0"), /* D0 */
519 SUNXI_FUNCTION(0x3, "csi0")), /* D0 */
345 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, 520 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
346 SUNXI_FUNCTION(0x0, "gpio_in"), 521 SUNXI_FUNCTION(0x0, "gpio_in"),
347 SUNXI_FUNCTION(0x1, "gpio_out")), 522 SUNXI_FUNCTION(0x1, "gpio_out"),
523 SUNXI_FUNCTION(0x2, "ts0"), /* D1 */
524 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
525 SUNXI_FUNCTION(0x4, "sim")), /* VPPEN */
348 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, 526 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
349 SUNXI_FUNCTION(0x0, "gpio_in"), 527 SUNXI_FUNCTION(0x0, "gpio_in"),
350 SUNXI_FUNCTION(0x1, "gpio_out")), 528 SUNXI_FUNCTION(0x1, "gpio_out"),
529 SUNXI_FUNCTION(0x2, "ts0"), /* D2 */
530 SUNXI_FUNCTION(0x3, "csi0")), /* D2 */
351 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, 531 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
352 SUNXI_FUNCTION(0x0, "gpio_in"), 532 SUNXI_FUNCTION(0x0, "gpio_in"),
353 SUNXI_FUNCTION(0x1, "gpio_out")), 533 SUNXI_FUNCTION(0x1, "gpio_out"),
534 SUNXI_FUNCTION(0x2, "ts0"), /* D3 */
535 SUNXI_FUNCTION(0x3, "csi0")), /* D3 */
354 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, 536 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
355 SUNXI_FUNCTION(0x0, "gpio_in"), 537 SUNXI_FUNCTION(0x0, "gpio_in"),
356 SUNXI_FUNCTION(0x1, "gpio_out")), 538 SUNXI_FUNCTION(0x1, "gpio_out"),
539 SUNXI_FUNCTION(0x2, "ts0"), /* D4 */
540 SUNXI_FUNCTION(0x3, "csi0")), /* D4 */
357 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, 541 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
358 SUNXI_FUNCTION(0x0, "gpio_in"), 542 SUNXI_FUNCTION(0x0, "gpio_in"),
359 SUNXI_FUNCTION(0x1, "gpio_out")), 543 SUNXI_FUNCTION(0x1, "gpio_out"),
544 SUNXI_FUNCTION(0x2, "ts0"), /* D5 */
545 SUNXI_FUNCTION(0x3, "csi0")), /* D5 */
360 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, 546 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
361 SUNXI_FUNCTION(0x0, "gpio_in"), 547 SUNXI_FUNCTION(0x0, "gpio_in"),
362 SUNXI_FUNCTION(0x1, "gpio_out")), 548 SUNXI_FUNCTION(0x1, "gpio_out"),
549 SUNXI_FUNCTION(0x2, "ts0"), /* D6 */
550 SUNXI_FUNCTION(0x3, "csi0")), /* D6 */
363 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, 551 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
364 SUNXI_FUNCTION(0x0, "gpio_in"), 552 SUNXI_FUNCTION(0x0, "gpio_in"),
365 SUNXI_FUNCTION(0x1, "gpio_out")), 553 SUNXI_FUNCTION(0x1, "gpio_out"),
554 SUNXI_FUNCTION(0x2, "ts0"), /* D7 */
555 SUNXI_FUNCTION(0x3, "csi0")), /* D7 */
366 /* Hole */ 556 /* Hole */
367 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, 557 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
368 SUNXI_FUNCTION(0x0, "gpio_in"), 558 SUNXI_FUNCTION(0x0, "gpio_in"),
369 SUNXI_FUNCTION(0x1, "gpio_out")), 559 SUNXI_FUNCTION(0x1, "gpio_out"),
560 SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
561 SUNXI_FUNCTION(0x4, "jtag")), /* MSI */
370 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, 562 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
371 SUNXI_FUNCTION(0x0, "gpio_in"), 563 SUNXI_FUNCTION(0x0, "gpio_in"),
372 SUNXI_FUNCTION(0x1, "gpio_out")), 564 SUNXI_FUNCTION(0x1, "gpio_out"),
565 SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
566 SUNXI_FUNCTION(0x4, "jtag")), /* DI1 */
373 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, 567 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
374 SUNXI_FUNCTION(0x0, "gpio_in"), 568 SUNXI_FUNCTION(0x0, "gpio_in"),
375 SUNXI_FUNCTION(0x1, "gpio_out"), 569 SUNXI_FUNCTION(0x1, "gpio_out"),
570 SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
376 SUNXI_FUNCTION(0x4, "uart0")), /* TX */ 571 SUNXI_FUNCTION(0x4, "uart0")), /* TX */
377 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, 572 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
378 SUNXI_FUNCTION(0x0, "gpio_in"), 573 SUNXI_FUNCTION(0x0, "gpio_in"),
379 SUNXI_FUNCTION(0x1, "gpio_out")), 574 SUNXI_FUNCTION(0x1, "gpio_out"),
575 SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
576 SUNXI_FUNCTION(0x4, "jtag")), /* DO1 */
380 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, 577 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
381 SUNXI_FUNCTION(0x0, "gpio_in"), 578 SUNXI_FUNCTION(0x0, "gpio_in"),
382 SUNXI_FUNCTION(0x1, "gpio_out"), 579 SUNXI_FUNCTION(0x1, "gpio_out"),
580 SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
383 SUNXI_FUNCTION(0x4, "uart0")), /* RX */ 581 SUNXI_FUNCTION(0x4, "uart0")), /* RX */
384 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, 582 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
385 SUNXI_FUNCTION(0x0, "gpio_in"), 583 SUNXI_FUNCTION(0x0, "gpio_in"),
386 SUNXI_FUNCTION(0x1, "gpio_out")), 584 SUNXI_FUNCTION(0x1, "gpio_out"),
585 SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
586 SUNXI_FUNCTION(0x4, "jtag")), /* CK1 */
387 /* Hole */ 587 /* Hole */
388 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, 588 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
389 SUNXI_FUNCTION(0x0, "gpio_in"), 589 SUNXI_FUNCTION(0x0, "gpio_in"),
390 SUNXI_FUNCTION(0x1, "gpio_out")), 590 SUNXI_FUNCTION(0x1, "gpio_out"),
591 SUNXI_FUNCTION(0x2, "ts1"), /* CLK */
592 SUNXI_FUNCTION(0x3, "csi1"), /* PCK */
593 SUNXI_FUNCTION(0x4, "mmc1")), /* CMD */
391 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1, 594 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG1,
392 SUNXI_FUNCTION(0x0, "gpio_in"), 595 SUNXI_FUNCTION(0x0, "gpio_in"),
393 SUNXI_FUNCTION(0x1, "gpio_out")), 596 SUNXI_FUNCTION(0x1, "gpio_out"),
597 SUNXI_FUNCTION(0x2, "ts1"), /* ERR */
598 SUNXI_FUNCTION(0x3, "csi1"), /* CK */
599 SUNXI_FUNCTION(0x4, "mmc1")), /* CLK */
394 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2, 600 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG2,
395 SUNXI_FUNCTION(0x0, "gpio_in"), 601 SUNXI_FUNCTION(0x0, "gpio_in"),
396 SUNXI_FUNCTION(0x1, "gpio_out")), 602 SUNXI_FUNCTION(0x1, "gpio_out"),
603 SUNXI_FUNCTION(0x2, "ts1"), /* SYNC */
604 SUNXI_FUNCTION(0x3, "csi1"), /* HSYNC */
605 SUNXI_FUNCTION(0x4, "mmc1")), /* D0 */
397 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, 606 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
398 SUNXI_FUNCTION(0x0, "gpio_in"), 607 SUNXI_FUNCTION(0x0, "gpio_in"),
399 SUNXI_FUNCTION(0x1, "gpio_out")), 608 SUNXI_FUNCTION(0x1, "gpio_out"),
609 SUNXI_FUNCTION(0x2, "ts1"), /* DVLD */
610 SUNXI_FUNCTION(0x3, "csi1"), /* VSYNC */
611 SUNXI_FUNCTION(0x4, "mmc1")), /* D1 */
400 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, 612 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
401 SUNXI_FUNCTION(0x0, "gpio_in"), 613 SUNXI_FUNCTION(0x0, "gpio_in"),
402 SUNXI_FUNCTION(0x1, "gpio_out")), 614 SUNXI_FUNCTION(0x1, "gpio_out"),
615 SUNXI_FUNCTION(0x2, "ts1"), /* D0 */
616 SUNXI_FUNCTION(0x3, "csi1"), /* D0 */
617 SUNXI_FUNCTION(0x4, "mmc1"), /* D2 */
618 SUNXI_FUNCTION(0x5, "csi0")), /* D8 */
403 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5, 619 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG5,
404 SUNXI_FUNCTION(0x0, "gpio_in"), 620 SUNXI_FUNCTION(0x0, "gpio_in"),
405 SUNXI_FUNCTION(0x1, "gpio_out")), 621 SUNXI_FUNCTION(0x1, "gpio_out"),
622 SUNXI_FUNCTION(0x2, "ts1"), /* D1 */
623 SUNXI_FUNCTION(0x3, "csi1"), /* D1 */
624 SUNXI_FUNCTION(0x4, "mmc1"), /* D3 */
625 SUNXI_FUNCTION(0x5, "csi0")), /* D9 */
406 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6, 626 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG6,
407 SUNXI_FUNCTION(0x0, "gpio_in"), 627 SUNXI_FUNCTION(0x0, "gpio_in"),
408 SUNXI_FUNCTION(0x1, "gpio_out")), 628 SUNXI_FUNCTION(0x1, "gpio_out"),
629 SUNXI_FUNCTION(0x2, "ts1"), /* D2 */
630 SUNXI_FUNCTION(0x3, "csi1"), /* D2 */
631 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
632 SUNXI_FUNCTION(0x5, "csi0")), /* D10 */
409 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7, 633 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG7,
410 SUNXI_FUNCTION(0x0, "gpio_in"), 634 SUNXI_FUNCTION(0x0, "gpio_in"),
411 SUNXI_FUNCTION(0x1, "gpio_out")), 635 SUNXI_FUNCTION(0x1, "gpio_out"),
636 SUNXI_FUNCTION(0x2, "ts1"), /* D3 */
637 SUNXI_FUNCTION(0x3, "csi1"), /* D3 */
638 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
639 SUNXI_FUNCTION(0x5, "csi0")), /* D11 */
412 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8, 640 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG8,
413 SUNXI_FUNCTION(0x0, "gpio_in"), 641 SUNXI_FUNCTION(0x0, "gpio_in"),
414 SUNXI_FUNCTION(0x1, "gpio_out")), 642 SUNXI_FUNCTION(0x1, "gpio_out"),
643 SUNXI_FUNCTION(0x2, "ts1"), /* D4 */
644 SUNXI_FUNCTION(0x3, "csi1"), /* D4 */
645 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
646 SUNXI_FUNCTION(0x5, "csi0")), /* D12 */
415 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, 647 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
416 SUNXI_FUNCTION(0x0, "gpio_in"), 648 SUNXI_FUNCTION(0x0, "gpio_in"),
417 SUNXI_FUNCTION(0x1, "gpio_out")), 649 SUNXI_FUNCTION(0x1, "gpio_out"),
650 SUNXI_FUNCTION(0x2, "ts1"), /* D5 */
651 SUNXI_FUNCTION(0x3, "csi1"), /* D5 */
652 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
653 SUNXI_FUNCTION(0x5, "csi0")), /* D13 */
418 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, 654 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
419 SUNXI_FUNCTION(0x0, "gpio_in"), 655 SUNXI_FUNCTION(0x0, "gpio_in"),
420 SUNXI_FUNCTION(0x1, "gpio_out")), 656 SUNXI_FUNCTION(0x1, "gpio_out"),
657 SUNXI_FUNCTION(0x2, "ts1"), /* D6 */
658 SUNXI_FUNCTION(0x3, "csi1"), /* D6 */
659 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
660 SUNXI_FUNCTION(0x5, "csi0")), /* D14 */
421 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, 661 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
422 SUNXI_FUNCTION(0x0, "gpio_in"), 662 SUNXI_FUNCTION(0x0, "gpio_in"),
423 SUNXI_FUNCTION(0x1, "gpio_out")), 663 SUNXI_FUNCTION(0x1, "gpio_out"),
664 SUNXI_FUNCTION(0x2, "ts1"), /* D7 */
665 SUNXI_FUNCTION(0x3, "csi1"), /* D7 */
666 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
667 SUNXI_FUNCTION(0x5, "csi0")), /* D15 */
424 /* Hole */ 668 /* Hole */
425 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0, 669 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH0,
426 SUNXI_FUNCTION(0x0, "gpio_in"), 670 SUNXI_FUNCTION(0x0, "gpio_in"),
427 SUNXI_FUNCTION(0x1, "gpio_out")), 671 SUNXI_FUNCTION(0x1, "gpio_out"),
672 SUNXI_FUNCTION(0x2, "lcd1"), /* D0 */
673 SUNXI_FUNCTION(0x3, "pata"), /* ATAA0 */
674 SUNXI_FUNCTION(0x4, "uart3"), /* TX */
675 SUNXI_FUNCTION(0x7, "csi1")), /* D0 */
428 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1, 676 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH1,
429 SUNXI_FUNCTION(0x0, "gpio_in"), 677 SUNXI_FUNCTION(0x0, "gpio_in"),
430 SUNXI_FUNCTION(0x1, "gpio_out")), 678 SUNXI_FUNCTION(0x1, "gpio_out"),
679 SUNXI_FUNCTION(0x2, "lcd1"), /* D1 */
680 SUNXI_FUNCTION(0x3, "pata"), /* ATAA1 */
681 SUNXI_FUNCTION(0x4, "uart3"), /* RX */
682 SUNXI_FUNCTION(0x7, "csi1")), /* D1 */
431 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2, 683 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH2,
432 SUNXI_FUNCTION(0x0, "gpio_in"), 684 SUNXI_FUNCTION(0x0, "gpio_in"),
433 SUNXI_FUNCTION(0x1, "gpio_out")), 685 SUNXI_FUNCTION(0x1, "gpio_out"),
686 SUNXI_FUNCTION(0x2, "lcd1"), /* D2 */
687 SUNXI_FUNCTION(0x3, "pata"), /* ATAA2 */
688 SUNXI_FUNCTION(0x4, "uart3"), /* RTS */
689 SUNXI_FUNCTION(0x7, "csi1")), /* D2 */
434 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3, 690 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH3,
435 SUNXI_FUNCTION(0x0, "gpio_in"), 691 SUNXI_FUNCTION(0x0, "gpio_in"),
436 SUNXI_FUNCTION(0x1, "gpio_out")), 692 SUNXI_FUNCTION(0x1, "gpio_out"),
693 SUNXI_FUNCTION(0x2, "lcd1"), /* D3 */
694 SUNXI_FUNCTION(0x3, "pata"), /* ATAIRQ */
695 SUNXI_FUNCTION(0x4, "uart3"), /* CTS */
696 SUNXI_FUNCTION(0x7, "csi1")), /* D3 */
437 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4, 697 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH4,
438 SUNXI_FUNCTION(0x0, "gpio_in"), 698 SUNXI_FUNCTION(0x0, "gpio_in"),
439 SUNXI_FUNCTION(0x1, "gpio_out")), 699 SUNXI_FUNCTION(0x1, "gpio_out"),
700 SUNXI_FUNCTION(0x2, "lcd1"), /* D4 */
701 SUNXI_FUNCTION(0x3, "pata"), /* ATAD0 */
702 SUNXI_FUNCTION(0x4, "uart4"), /* TX */
703 SUNXI_FUNCTION(0x7, "csi1")), /* D4 */
440 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5, 704 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH5,
441 SUNXI_FUNCTION(0x0, "gpio_in"), 705 SUNXI_FUNCTION(0x0, "gpio_in"),
442 SUNXI_FUNCTION(0x1, "gpio_out")), 706 SUNXI_FUNCTION(0x1, "gpio_out"),
707 SUNXI_FUNCTION(0x2, "lcd1"), /* D5 */
708 SUNXI_FUNCTION(0x3, "pata"), /* ATAD1 */
709 SUNXI_FUNCTION(0x4, "uart4"), /* RX */
710 SUNXI_FUNCTION(0x7, "csi1")), /* D5 */
443 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6, 711 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH6,
444 SUNXI_FUNCTION(0x0, "gpio_in"), 712 SUNXI_FUNCTION(0x0, "gpio_in"),
445 SUNXI_FUNCTION(0x1, "gpio_out")), 713 SUNXI_FUNCTION(0x1, "gpio_out"),
714 SUNXI_FUNCTION(0x2, "lcd1"), /* D6 */
715 SUNXI_FUNCTION(0x3, "pata"), /* ATAD2 */
716 SUNXI_FUNCTION(0x4, "uart5"), /* TX */
717 SUNXI_FUNCTION(0x5, "ms"), /* BS */
718 SUNXI_FUNCTION(0x7, "csi1")), /* D6 */
446 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7, 719 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH7,
447 SUNXI_FUNCTION(0x0, "gpio_in"), 720 SUNXI_FUNCTION(0x0, "gpio_in"),
448 SUNXI_FUNCTION(0x1, "gpio_out")), 721 SUNXI_FUNCTION(0x1, "gpio_out"),
722 SUNXI_FUNCTION(0x2, "lcd1"), /* D7 */
723 SUNXI_FUNCTION(0x3, "pata"), /* ATAD3 */
724 SUNXI_FUNCTION(0x4, "uart5"), /* RX */
725 SUNXI_FUNCTION(0x5, "ms"), /* CLK */
726 SUNXI_FUNCTION(0x7, "csi1")), /* D7 */
449 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8, 727 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH8,
450 SUNXI_FUNCTION(0x0, "gpio_in"), 728 SUNXI_FUNCTION(0x0, "gpio_in"),
451 SUNXI_FUNCTION(0x1, "gpio_out")), 729 SUNXI_FUNCTION(0x1, "gpio_out"),
730 SUNXI_FUNCTION(0x2, "lcd1"), /* D8 */
731 SUNXI_FUNCTION(0x3, "pata"), /* ATAD4 */
732 SUNXI_FUNCTION(0x4, "keypad"), /* IN0 */
733 SUNXI_FUNCTION(0x5, "ms"), /* D0 */
734 SUNXI_FUNCTION(0x7, "csi1")), /* D8 */
452 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9, 735 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH9,
453 SUNXI_FUNCTION(0x0, "gpio_in"), 736 SUNXI_FUNCTION(0x0, "gpio_in"),
454 SUNXI_FUNCTION(0x1, "gpio_out")), 737 SUNXI_FUNCTION(0x1, "gpio_out"),
738 SUNXI_FUNCTION(0x2, "lcd1"), /* D9 */
739 SUNXI_FUNCTION(0x3, "pata"), /* ATAD5 */
740 SUNXI_FUNCTION(0x4, "keypad"), /* IN1 */
741 SUNXI_FUNCTION(0x5, "ms"), /* D1 */
742 SUNXI_FUNCTION(0x7, "csi1")), /* D9 */
455 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10, 743 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH10,
456 SUNXI_FUNCTION(0x0, "gpio_in"), 744 SUNXI_FUNCTION(0x0, "gpio_in"),
457 SUNXI_FUNCTION(0x1, "gpio_out")), 745 SUNXI_FUNCTION(0x1, "gpio_out"),
746 SUNXI_FUNCTION(0x2, "lcd1"), /* D10 */
747 SUNXI_FUNCTION(0x3, "pata"), /* ATAD6 */
748 SUNXI_FUNCTION(0x4, "keypad"), /* IN2 */
749 SUNXI_FUNCTION(0x5, "ms"), /* D2 */
750 SUNXI_FUNCTION(0x7, "csi1")), /* D10 */
458 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11, 751 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH11,
459 SUNXI_FUNCTION(0x0, "gpio_in"), 752 SUNXI_FUNCTION(0x0, "gpio_in"),
460 SUNXI_FUNCTION(0x1, "gpio_out")), 753 SUNXI_FUNCTION(0x1, "gpio_out"),
754 SUNXI_FUNCTION(0x2, "lcd1"), /* D11 */
755 SUNXI_FUNCTION(0x3, "pata"), /* ATAD7 */
756 SUNXI_FUNCTION(0x4, "keypad"), /* IN3 */
757 SUNXI_FUNCTION(0x5, "ms"), /* D3 */
758 SUNXI_FUNCTION(0x7, "csi1")), /* D11 */
461 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12, 759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH12,
462 SUNXI_FUNCTION(0x0, "gpio_in"), 760 SUNXI_FUNCTION(0x0, "gpio_in"),
463 SUNXI_FUNCTION(0x1, "gpio_out")), 761 SUNXI_FUNCTION(0x1, "gpio_out"),
762 SUNXI_FUNCTION(0x2, "lcd1"), /* D12 */
763 SUNXI_FUNCTION(0x3, "pata"), /* ATAD8 */
764 SUNXI_FUNCTION(0x4, "ps2"), /* SCK1 */
765 SUNXI_FUNCTION(0x7, "csi1")), /* D12 */
464 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13, 766 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH13,
465 SUNXI_FUNCTION(0x0, "gpio_in"), 767 SUNXI_FUNCTION(0x0, "gpio_in"),
466 SUNXI_FUNCTION(0x1, "gpio_out")), 768 SUNXI_FUNCTION(0x1, "gpio_out"),
769 SUNXI_FUNCTION(0x2, "lcd1"), /* D13 */
770 SUNXI_FUNCTION(0x3, "pata"), /* ATAD9 */
771 SUNXI_FUNCTION(0x4, "ps2"), /* SDA1 */
772 SUNXI_FUNCTION(0x5, "sim"), /* RST */
773 SUNXI_FUNCTION(0x7, "csi1")), /* D13 */
467 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14, 774 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH14,
468 SUNXI_FUNCTION(0x0, "gpio_in"), 775 SUNXI_FUNCTION(0x0, "gpio_in"),
469 SUNXI_FUNCTION(0x1, "gpio_out")), 776 SUNXI_FUNCTION(0x1, "gpio_out"),
777 SUNXI_FUNCTION(0x2, "lcd1"), /* D14 */
778 SUNXI_FUNCTION(0x3, "pata"), /* ATAD10 */
779 SUNXI_FUNCTION(0x4, "keypad"), /* IN4 */
780 SUNXI_FUNCTION(0x5, "sim"), /* VPPEN */
781 SUNXI_FUNCTION(0x7, "csi1")), /* D14 */
470 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15, 782 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH15,
471 SUNXI_FUNCTION(0x0, "gpio_in"), 783 SUNXI_FUNCTION(0x0, "gpio_in"),
472 SUNXI_FUNCTION(0x1, "gpio_out")), 784 SUNXI_FUNCTION(0x1, "gpio_out"),
785 SUNXI_FUNCTION(0x2, "lcd1"), /* D15 */
786 SUNXI_FUNCTION(0x3, "pata"), /* ATAD11 */
787 SUNXI_FUNCTION(0x4, "keypad"), /* IN5 */
788 SUNXI_FUNCTION(0x5, "sim"), /* VPPPP */
789 SUNXI_FUNCTION(0x7, "csi1")), /* D15 */
473 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16, 790 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH16,
474 SUNXI_FUNCTION(0x0, "gpio_in"), 791 SUNXI_FUNCTION(0x0, "gpio_in"),
475 SUNXI_FUNCTION(0x1, "gpio_out")), 792 SUNXI_FUNCTION(0x1, "gpio_out"),
793 SUNXI_FUNCTION(0x2, "lcd1"), /* D16 */
794 SUNXI_FUNCTION(0x3, "pata"), /* ATAD12 */
795 SUNXI_FUNCTION(0x4, "keypad"), /* IN6 */
796 SUNXI_FUNCTION(0x7, "csi1")), /* D16 */
476 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17, 797 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH17,
477 SUNXI_FUNCTION(0x0, "gpio_in"), 798 SUNXI_FUNCTION(0x0, "gpio_in"),
478 SUNXI_FUNCTION(0x1, "gpio_out")), 799 SUNXI_FUNCTION(0x1, "gpio_out"),
800 SUNXI_FUNCTION(0x2, "lcd1"), /* D17 */
801 SUNXI_FUNCTION(0x3, "pata"), /* ATAD13 */
802 SUNXI_FUNCTION(0x4, "keypad"), /* IN7 */
803 SUNXI_FUNCTION(0x5, "sim"), /* VCCEN */
804 SUNXI_FUNCTION(0x7, "csi1")), /* D17 */
479 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18, 805 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH18,
480 SUNXI_FUNCTION(0x0, "gpio_in"), 806 SUNXI_FUNCTION(0x0, "gpio_in"),
481 SUNXI_FUNCTION(0x1, "gpio_out")), 807 SUNXI_FUNCTION(0x1, "gpio_out"),
808 SUNXI_FUNCTION(0x2, "lcd1"), /* D18 */
809 SUNXI_FUNCTION(0x3, "pata"), /* ATAD14 */
810 SUNXI_FUNCTION(0x4, "keypad"), /* OUT0 */
811 SUNXI_FUNCTION(0x5, "sim"), /* SCK */
812 SUNXI_FUNCTION(0x7, "csi1")), /* D18 */
482 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19, 813 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH19,
483 SUNXI_FUNCTION(0x0, "gpio_in"), 814 SUNXI_FUNCTION(0x0, "gpio_in"),
484 SUNXI_FUNCTION(0x1, "gpio_out")), 815 SUNXI_FUNCTION(0x1, "gpio_out"),
816 SUNXI_FUNCTION(0x2, "lcd1"), /* D19 */
817 SUNXI_FUNCTION(0x3, "pata"), /* ATAD15 */
818 SUNXI_FUNCTION(0x4, "keypad"), /* OUT1 */
819 SUNXI_FUNCTION(0x5, "sim"), /* SDA */
820 SUNXI_FUNCTION(0x7, "csi1")), /* D19 */
485 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20, 821 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH20,
486 SUNXI_FUNCTION(0x0, "gpio_in"), 822 SUNXI_FUNCTION(0x0, "gpio_in"),
487 SUNXI_FUNCTION(0x1, "gpio_out")), 823 SUNXI_FUNCTION(0x1, "gpio_out"),
824 SUNXI_FUNCTION(0x2, "lcd1"), /* D20 */
825 SUNXI_FUNCTION(0x3, "pata"), /* ATAOE */
826 SUNXI_FUNCTION(0x4, "can"), /* TX */
827 SUNXI_FUNCTION(0x7, "csi1")), /* D20 */
488 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21, 828 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH21,
489 SUNXI_FUNCTION(0x0, "gpio_in"), 829 SUNXI_FUNCTION(0x0, "gpio_in"),
490 SUNXI_FUNCTION(0x1, "gpio_out")), 830 SUNXI_FUNCTION(0x1, "gpio_out"),
831 SUNXI_FUNCTION(0x2, "lcd1"), /* D21 */
832 SUNXI_FUNCTION(0x3, "pata"), /* ATADREQ */
833 SUNXI_FUNCTION(0x4, "can"), /* RX */
834 SUNXI_FUNCTION(0x7, "csi1")), /* D21 */
491 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22, 835 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH22,
492 SUNXI_FUNCTION(0x0, "gpio_in"), 836 SUNXI_FUNCTION(0x0, "gpio_in"),
493 SUNXI_FUNCTION(0x1, "gpio_out")), 837 SUNXI_FUNCTION(0x1, "gpio_out"),
838 SUNXI_FUNCTION(0x2, "lcd1"), /* D22 */
839 SUNXI_FUNCTION(0x3, "pata"), /* ATADACK */
840 SUNXI_FUNCTION(0x4, "keypad"), /* OUT2 */
841 SUNXI_FUNCTION(0x5, "mmc1"), /* CMD */
842 SUNXI_FUNCTION(0x7, "csi1")), /* D22 */
494 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23, 843 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH23,
495 SUNXI_FUNCTION(0x0, "gpio_in"), 844 SUNXI_FUNCTION(0x0, "gpio_in"),
496 SUNXI_FUNCTION(0x1, "gpio_out")), 845 SUNXI_FUNCTION(0x1, "gpio_out"),
846 SUNXI_FUNCTION(0x2, "lcd1"), /* D23 */
847 SUNXI_FUNCTION(0x3, "pata"), /* ATACS0 */
848 SUNXI_FUNCTION(0x4, "keypad"), /* OUT3 */
849 SUNXI_FUNCTION(0x5, "mmc1"), /* CLK */
850 SUNXI_FUNCTION(0x7, "csi1")), /* D23 */
497 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24, 851 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH24,
498 SUNXI_FUNCTION(0x0, "gpio_in"), 852 SUNXI_FUNCTION(0x0, "gpio_in"),
499 SUNXI_FUNCTION(0x1, "gpio_out")), 853 SUNXI_FUNCTION(0x1, "gpio_out"),
854 SUNXI_FUNCTION(0x2, "lcd1"), /* CLK */
855 SUNXI_FUNCTION(0x3, "pata"), /* ATACS1 */
856 SUNXI_FUNCTION(0x4, "keypad"), /* OUT4 */
857 SUNXI_FUNCTION(0x5, "mmc1"), /* D0 */
858 SUNXI_FUNCTION(0x7, "csi1")), /* PCLK */
500 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25, 859 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH25,
501 SUNXI_FUNCTION(0x0, "gpio_in"), 860 SUNXI_FUNCTION(0x0, "gpio_in"),
502 SUNXI_FUNCTION(0x1, "gpio_out")), 861 SUNXI_FUNCTION(0x1, "gpio_out"),
862 SUNXI_FUNCTION(0x2, "lcd1"), /* DE */
863 SUNXI_FUNCTION(0x3, "pata"), /* ATAIORDY */
864 SUNXI_FUNCTION(0x4, "keypad"), /* OUT5 */
865 SUNXI_FUNCTION(0x5, "mmc1"), /* D1 */
866 SUNXI_FUNCTION(0x7, "csi1")), /* FIELD */
503 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26, 867 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH26,
504 SUNXI_FUNCTION(0x0, "gpio_in"), 868 SUNXI_FUNCTION(0x0, "gpio_in"),
505 SUNXI_FUNCTION(0x1, "gpio_out")), 869 SUNXI_FUNCTION(0x1, "gpio_out"),
870 SUNXI_FUNCTION(0x2, "lcd1"), /* HSYNC */
871 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOR */
872 SUNXI_FUNCTION(0x4, "keypad"), /* OUT6 */
873 SUNXI_FUNCTION(0x5, "mmc1"), /* D2 */
874 SUNXI_FUNCTION(0x7, "csi1")), /* HSYNC */
506 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27, 875 SUNXI_PIN(SUNXI_PINCTRL_PIN_PH27,
507 SUNXI_FUNCTION(0x0, "gpio_in"), 876 SUNXI_FUNCTION(0x0, "gpio_in"),
508 SUNXI_FUNCTION(0x1, "gpio_out")), 877 SUNXI_FUNCTION(0x1, "gpio_out"),
878 SUNXI_FUNCTION(0x2, "lcd1"), /* VSYNC */
879 SUNXI_FUNCTION(0x3, "pata"), /* ATAIOW */
880 SUNXI_FUNCTION(0x4, "keypad"), /* OUT7 */
881 SUNXI_FUNCTION(0x5, "mmc1"), /* D3 */
882 SUNXI_FUNCTION(0x7, "csi1")), /* VSYNC */
509 /* Hole */ 883 /* Hole */
510 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0, 884 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI0,
511 SUNXI_FUNCTION(0x0, "gpio_in"), 885 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -518,277 +892,401 @@ static const struct sunxi_desc_pin sun4i_a10_pins[] = {
518 SUNXI_FUNCTION(0x1, "gpio_out")), 892 SUNXI_FUNCTION(0x1, "gpio_out")),
519 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3, 893 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI3,
520 SUNXI_FUNCTION(0x0, "gpio_in"), 894 SUNXI_FUNCTION(0x0, "gpio_in"),
521 SUNXI_FUNCTION(0x1, "gpio_out")), 895 SUNXI_FUNCTION(0x1, "gpio_out"),
896 SUNXI_FUNCTION(0x2, "pwm")), /* PWM1 */
522 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4, 897 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI4,
523 SUNXI_FUNCTION(0x0, "gpio_in"), 898 SUNXI_FUNCTION(0x0, "gpio_in"),
524 SUNXI_FUNCTION(0x1, "gpio_out")), 899 SUNXI_FUNCTION(0x1, "gpio_out"),
900 SUNXI_FUNCTION(0x2, "mmc3")), /* CMD */
525 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5, 901 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI5,
526 SUNXI_FUNCTION(0x0, "gpio_in"), 902 SUNXI_FUNCTION(0x0, "gpio_in"),
527 SUNXI_FUNCTION(0x1, "gpio_out")), 903 SUNXI_FUNCTION(0x1, "gpio_out"),
904 SUNXI_FUNCTION(0x2, "mmc3")), /* CLK */
528 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6, 905 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI6,
529 SUNXI_FUNCTION(0x0, "gpio_in"), 906 SUNXI_FUNCTION(0x0, "gpio_in"),
530 SUNXI_FUNCTION(0x1, "gpio_out")), 907 SUNXI_FUNCTION(0x1, "gpio_out"),
908 SUNXI_FUNCTION(0x2, "mmc3")), /* D0 */
531 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7, 909 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI7,
532 SUNXI_FUNCTION(0x0, "gpio_in"), 910 SUNXI_FUNCTION(0x0, "gpio_in"),
533 SUNXI_FUNCTION(0x1, "gpio_out")), 911 SUNXI_FUNCTION(0x1, "gpio_out"),
912 SUNXI_FUNCTION(0x2, "mmc3")), /* D1 */
534 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8, 913 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI8,
535 SUNXI_FUNCTION(0x0, "gpio_in"), 914 SUNXI_FUNCTION(0x0, "gpio_in"),
536 SUNXI_FUNCTION(0x1, "gpio_out")), 915 SUNXI_FUNCTION(0x1, "gpio_out"),
916 SUNXI_FUNCTION(0x2, "mmc3")), /* D2 */
537 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9, 917 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI9,
538 SUNXI_FUNCTION(0x0, "gpio_in"), 918 SUNXI_FUNCTION(0x0, "gpio_in"),
539 SUNXI_FUNCTION(0x1, "gpio_out")), 919 SUNXI_FUNCTION(0x1, "gpio_out"),
920 SUNXI_FUNCTION(0x2, "mmc3")), /* D3 */
540 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10, 921 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI10,
541 SUNXI_FUNCTION(0x0, "gpio_in"), 922 SUNXI_FUNCTION(0x0, "gpio_in"),
542 SUNXI_FUNCTION(0x1, "gpio_out")), 923 SUNXI_FUNCTION(0x1, "gpio_out"),
924 SUNXI_FUNCTION(0x2, "spi0"), /* CS0 */
925 SUNXI_FUNCTION(0x3, "uart5")), /* TX */
543 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11, 926 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI11,
544 SUNXI_FUNCTION(0x0, "gpio_in"), 927 SUNXI_FUNCTION(0x0, "gpio_in"),
545 SUNXI_FUNCTION(0x1, "gpio_out")), 928 SUNXI_FUNCTION(0x1, "gpio_out"),
929 SUNXI_FUNCTION(0x2, "spi0"), /* CLK */
930 SUNXI_FUNCTION(0x3, "uart5")), /* RX */
546 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12, 931 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI12,
547 SUNXI_FUNCTION(0x0, "gpio_in"), 932 SUNXI_FUNCTION(0x0, "gpio_in"),
548 SUNXI_FUNCTION(0x1, "gpio_out")), 933 SUNXI_FUNCTION(0x1, "gpio_out"),
934 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
935 SUNXI_FUNCTION(0x3, "uart6")), /* TX */
549 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13, 936 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
550 SUNXI_FUNCTION(0x0, "gpio_in"), 937 SUNXI_FUNCTION(0x0, "gpio_in"),
551 SUNXI_FUNCTION(0x1, "gpio_out")), 938 SUNXI_FUNCTION(0x1, "gpio_out"),
939 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
940 SUNXI_FUNCTION(0x3, "uart6")), /* RX */
552 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14, 941 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
553 SUNXI_FUNCTION(0x0, "gpio_in"), 942 SUNXI_FUNCTION(0x0, "gpio_in"),
554 SUNXI_FUNCTION(0x1, "gpio_out")), 943 SUNXI_FUNCTION(0x1, "gpio_out"),
944 SUNXI_FUNCTION(0x2, "spi0"), /* CS1 */
945 SUNXI_FUNCTION(0x3, "ps2"), /* SCK1 */
946 SUNXI_FUNCTION(0x4, "timer4")), /* TCLKIN0 */
555 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15, 947 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI15,
556 SUNXI_FUNCTION(0x0, "gpio_in"), 948 SUNXI_FUNCTION(0x0, "gpio_in"),
557 SUNXI_FUNCTION(0x1, "gpio_out")), 949 SUNXI_FUNCTION(0x1, "gpio_out"),
950 SUNXI_FUNCTION(0x2, "spi1"), /* CS1 */
951 SUNXI_FUNCTION(0x3, "ps2"), /* SDA1 */
952 SUNXI_FUNCTION(0x4, "timer5")), /* TCLKIN1 */
558 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16, 953 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI16,
559 SUNXI_FUNCTION(0x0, "gpio_in"), 954 SUNXI_FUNCTION(0x0, "gpio_in"),
560 SUNXI_FUNCTION(0x1, "gpio_out")), 955 SUNXI_FUNCTION(0x1, "gpio_out"),
956 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
957 SUNXI_FUNCTION(0x3, "uart2")), /* RTS */
561 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17, 958 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI17,
562 SUNXI_FUNCTION(0x0, "gpio_in"), 959 SUNXI_FUNCTION(0x0, "gpio_in"),
563 SUNXI_FUNCTION(0x1, "gpio_out")), 960 SUNXI_FUNCTION(0x1, "gpio_out"),
961 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
962 SUNXI_FUNCTION(0x3, "uart2")), /* CTS */
564 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18, 963 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI18,
565 SUNXI_FUNCTION(0x0, "gpio_in"), 964 SUNXI_FUNCTION(0x0, "gpio_in"),
566 SUNXI_FUNCTION(0x1, "gpio_out")), 965 SUNXI_FUNCTION(0x1, "gpio_out"),
966 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
967 SUNXI_FUNCTION(0x3, "uart2")), /* TX */
567 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19, 968 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI19,
568 SUNXI_FUNCTION(0x0, "gpio_in"), 969 SUNXI_FUNCTION(0x0, "gpio_in"),
569 SUNXI_FUNCTION(0x1, "gpio_out")), 970 SUNXI_FUNCTION(0x1, "gpio_out"),
971 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
972 SUNXI_FUNCTION(0x3, "uart2")), /* RX */
570 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20, 973 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI20,
571 SUNXI_FUNCTION(0x0, "gpio_in"), 974 SUNXI_FUNCTION(0x0, "gpio_in"),
572 SUNXI_FUNCTION(0x1, "gpio_out")), 975 SUNXI_FUNCTION(0x1, "gpio_out"),
976 SUNXI_FUNCTION(0x2, "ps2"), /* SCK0 */
977 SUNXI_FUNCTION(0x3, "uart7"), /* TX */
978 SUNXI_FUNCTION(0x4, "hdmi")), /* HSCL */
573 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21, 979 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI21,
574 SUNXI_FUNCTION(0x0, "gpio_in"), 980 SUNXI_FUNCTION(0x0, "gpio_in"),
575 SUNXI_FUNCTION(0x1, "gpio_out")), 981 SUNXI_FUNCTION(0x1, "gpio_out"),
982 SUNXI_FUNCTION(0x2, "ps2"), /* SDA0 */
983 SUNXI_FUNCTION(0x3, "uart7"), /* RX */
984 SUNXI_FUNCTION(0x4, "hdmi")), /* HSDA */
576}; 985};
577 986
578static const struct sunxi_desc_pin sun5i_a13_pins[] = { 987static const struct sunxi_desc_pin sun5i_a13_pins[] = {
579 /* Hole */ 988 /* Hole */
580 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0, 989 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB0,
581 SUNXI_FUNCTION(0x0, "gpio_in"), 990 SUNXI_FUNCTION(0x0, "gpio_in"),
582 SUNXI_FUNCTION(0x1, "gpio_out")), 991 SUNXI_FUNCTION(0x1, "gpio_out"),
992 SUNXI_FUNCTION(0x2, "i2c0")), /* SCK */
583 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1, 993 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB1,
584 SUNXI_FUNCTION(0x0, "gpio_in"), 994 SUNXI_FUNCTION(0x0, "gpio_in"),
585 SUNXI_FUNCTION(0x1, "gpio_out")), 995 SUNXI_FUNCTION(0x1, "gpio_out"),
996 SUNXI_FUNCTION(0x2, "i2c0")), /* SDA */
586 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2, 997 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB2,
587 SUNXI_FUNCTION(0x0, "gpio_in"), 998 SUNXI_FUNCTION(0x0, "gpio_in"),
588 SUNXI_FUNCTION(0x1, "gpio_out")), 999 SUNXI_FUNCTION(0x1, "gpio_out"),
1000 SUNXI_FUNCTION(0x2, "pwm")),
589 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3, 1001 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB3,
590 SUNXI_FUNCTION(0x0, "gpio_in"), 1002 SUNXI_FUNCTION(0x0, "gpio_in"),
591 SUNXI_FUNCTION(0x1, "gpio_out")), 1003 SUNXI_FUNCTION(0x1, "gpio_out"),
1004 SUNXI_FUNCTION(0x2, "ir0")), /* TX */
592 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4, 1005 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB4,
593 SUNXI_FUNCTION(0x0, "gpio_in"), 1006 SUNXI_FUNCTION(0x0, "gpio_in"),
594 SUNXI_FUNCTION(0x1, "gpio_out")), 1007 SUNXI_FUNCTION(0x1, "gpio_out"),
1008 SUNXI_FUNCTION(0x2, "ir0")), /* RX */
595 /* Hole */ 1009 /* Hole */
596 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10, 1010 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB10,
597 SUNXI_FUNCTION(0x0, "gpio_in"), 1011 SUNXI_FUNCTION(0x0, "gpio_in"),
598 SUNXI_FUNCTION(0x1, "gpio_out")), 1012 SUNXI_FUNCTION(0x1, "gpio_out"),
1013 SUNXI_FUNCTION(0x2, "spi2")), /* CS1 */
599 /* Hole */ 1014 /* Hole */
600 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15, 1015 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB15,
601 SUNXI_FUNCTION(0x0, "gpio_in"), 1016 SUNXI_FUNCTION(0x0, "gpio_in"),
602 SUNXI_FUNCTION(0x1, "gpio_out")), 1017 SUNXI_FUNCTION(0x1, "gpio_out"),
1018 SUNXI_FUNCTION(0x2, "i2c1")), /* SCK */
603 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16, 1019 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB16,
604 SUNXI_FUNCTION(0x0, "gpio_in"), 1020 SUNXI_FUNCTION(0x0, "gpio_in"),
605 SUNXI_FUNCTION(0x1, "gpio_out")), 1021 SUNXI_FUNCTION(0x1, "gpio_out"),
1022 SUNXI_FUNCTION(0x2, "i2c1")), /* SDA */
606 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17, 1023 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB17,
607 SUNXI_FUNCTION(0x0, "gpio_in"), 1024 SUNXI_FUNCTION(0x0, "gpio_in"),
608 SUNXI_FUNCTION(0x1, "gpio_out")), 1025 SUNXI_FUNCTION(0x1, "gpio_out"),
1026 SUNXI_FUNCTION(0x2, "i2c2")), /* SCK */
609 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18, 1027 SUNXI_PIN(SUNXI_PINCTRL_PIN_PB18,
610 SUNXI_FUNCTION(0x0, "gpio_in"), 1028 SUNXI_FUNCTION(0x0, "gpio_in"),
611 SUNXI_FUNCTION(0x1, "gpio_out")), 1029 SUNXI_FUNCTION(0x1, "gpio_out"),
1030 SUNXI_FUNCTION(0x2, "i2c2")), /* SDA */
612 /* Hole */ 1031 /* Hole */
613 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0, 1032 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC0,
614 SUNXI_FUNCTION(0x0, "gpio_in"), 1033 SUNXI_FUNCTION(0x0, "gpio_in"),
615 SUNXI_FUNCTION(0x1, "gpio_out")), 1034 SUNXI_FUNCTION(0x1, "gpio_out"),
1035 SUNXI_FUNCTION(0x2, "nand0"), /* NWE */
1036 SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
616 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1, 1037 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC1,
617 SUNXI_FUNCTION(0x0, "gpio_in"), 1038 SUNXI_FUNCTION(0x0, "gpio_in"),
618 SUNXI_FUNCTION(0x1, "gpio_out")), 1039 SUNXI_FUNCTION(0x1, "gpio_out"),
1040 SUNXI_FUNCTION(0x2, "nand0"), /* NALE */
1041 SUNXI_FUNCTION(0x3, "spi0")), /* MISO */
619 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2, 1042 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC2,
620 SUNXI_FUNCTION(0x0, "gpio_in"), 1043 SUNXI_FUNCTION(0x0, "gpio_in"),
621 SUNXI_FUNCTION(0x1, "gpio_out")), 1044 SUNXI_FUNCTION(0x1, "gpio_out"),
1045 SUNXI_FUNCTION(0x2, "nand0"), /* NCLE */
1046 SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
622 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3, 1047 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC3,
623 SUNXI_FUNCTION(0x0, "gpio_in"), 1048 SUNXI_FUNCTION(0x0, "gpio_in"),
624 SUNXI_FUNCTION(0x1, "gpio_out")), 1049 SUNXI_FUNCTION(0x1, "gpio_out"),
1050 SUNXI_FUNCTION(0x2, "nand0"), /* NCE1 */
1051 SUNXI_FUNCTION(0x3, "spi0")), /* CS0 */
625 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4, 1052 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC4,
626 SUNXI_FUNCTION(0x0, "gpio_in"), 1053 SUNXI_FUNCTION(0x0, "gpio_in"),
627 SUNXI_FUNCTION(0x1, "gpio_out")), 1054 SUNXI_FUNCTION(0x1, "gpio_out"),
1055 SUNXI_FUNCTION(0x2, "nand0")), /* NCE0 */
628 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5, 1056 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC5,
629 SUNXI_FUNCTION(0x0, "gpio_in"), 1057 SUNXI_FUNCTION(0x0, "gpio_in"),
630 SUNXI_FUNCTION(0x1, "gpio_out")), 1058 SUNXI_FUNCTION(0x1, "gpio_out"),
1059 SUNXI_FUNCTION(0x2, "nand0")), /* NRE */
631 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6, 1060 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC6,
632 SUNXI_FUNCTION(0x0, "gpio_in"), 1061 SUNXI_FUNCTION(0x0, "gpio_in"),
633 SUNXI_FUNCTION(0x1, "gpio_out")), 1062 SUNXI_FUNCTION(0x1, "gpio_out"),
1063 SUNXI_FUNCTION(0x2, "nand0"), /* NRB0 */
1064 SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
634 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7, 1065 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC7,
635 SUNXI_FUNCTION(0x0, "gpio_in"), 1066 SUNXI_FUNCTION(0x0, "gpio_in"),
636 SUNXI_FUNCTION(0x1, "gpio_out")), 1067 SUNXI_FUNCTION(0x1, "gpio_out"),
1068 SUNXI_FUNCTION(0x2, "nand0"), /* NRB1 */
1069 SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
637 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8, 1070 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC8,
638 SUNXI_FUNCTION(0x0, "gpio_in"), 1071 SUNXI_FUNCTION(0x0, "gpio_in"),
639 SUNXI_FUNCTION(0x1, "gpio_out")), 1072 SUNXI_FUNCTION(0x1, "gpio_out"),
1073 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ0 */
1074 SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
640 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9, 1075 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC9,
641 SUNXI_FUNCTION(0x0, "gpio_in"), 1076 SUNXI_FUNCTION(0x0, "gpio_in"),
642 SUNXI_FUNCTION(0x1, "gpio_out")), 1077 SUNXI_FUNCTION(0x1, "gpio_out"),
1078 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ1 */
1079 SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
643 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10, 1080 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC10,
644 SUNXI_FUNCTION(0x0, "gpio_in"), 1081 SUNXI_FUNCTION(0x0, "gpio_in"),
645 SUNXI_FUNCTION(0x1, "gpio_out")), 1082 SUNXI_FUNCTION(0x1, "gpio_out"),
1083 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ2 */
1084 SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
646 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11, 1085 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC11,
647 SUNXI_FUNCTION(0x0, "gpio_in"), 1086 SUNXI_FUNCTION(0x0, "gpio_in"),
648 SUNXI_FUNCTION(0x1, "gpio_out")), 1087 SUNXI_FUNCTION(0x1, "gpio_out"),
1088 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ3 */
1089 SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
649 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12, 1090 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC12,
650 SUNXI_FUNCTION(0x0, "gpio_in"), 1091 SUNXI_FUNCTION(0x0, "gpio_in"),
651 SUNXI_FUNCTION(0x1, "gpio_out")), 1092 SUNXI_FUNCTION(0x1, "gpio_out"),
1093 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */
1094 SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
652 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13, 1095 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC13,
653 SUNXI_FUNCTION(0x0, "gpio_in"), 1096 SUNXI_FUNCTION(0x0, "gpio_in"),
654 SUNXI_FUNCTION(0x1, "gpio_out")), 1097 SUNXI_FUNCTION(0x1, "gpio_out"),
1098 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */
1099 SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
655 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14, 1100 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC14,
656 SUNXI_FUNCTION(0x0, "gpio_in"), 1101 SUNXI_FUNCTION(0x0, "gpio_in"),
657 SUNXI_FUNCTION(0x1, "gpio_out")), 1102 SUNXI_FUNCTION(0x1, "gpio_out"),
1103 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */
1104 SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
658 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15, 1105 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC15,
659 SUNXI_FUNCTION(0x0, "gpio_in"), 1106 SUNXI_FUNCTION(0x0, "gpio_in"),
660 SUNXI_FUNCTION(0x1, "gpio_out")), 1107 SUNXI_FUNCTION(0x1, "gpio_out"),
1108 SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */
1109 SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
661 /* Hole */ 1110 /* Hole */
662 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19, 1111 SUNXI_PIN(SUNXI_PINCTRL_PIN_PC19,
663 SUNXI_FUNCTION(0x0, "gpio_in"), 1112 SUNXI_FUNCTION(0x0, "gpio_in"),
664 SUNXI_FUNCTION(0x1, "gpio_out")), 1113 SUNXI_FUNCTION(0x1, "gpio_out"),
1114 SUNXI_FUNCTION(0x2, "nand0"), /* NDQS */
1115 SUNXI_FUNCTION(0x4, "uart3")), /* RTS */
665 /* Hole */ 1116 /* Hole */
666 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2, 1117 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD2,
667 SUNXI_FUNCTION(0x0, "gpio_in"), 1118 SUNXI_FUNCTION(0x0, "gpio_in"),
668 SUNXI_FUNCTION(0x1, "gpio_out")), 1119 SUNXI_FUNCTION(0x1, "gpio_out"),
1120 SUNXI_FUNCTION(0x2, "lcd0")), /* D2 */
669 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3, 1121 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD3,
670 SUNXI_FUNCTION(0x0, "gpio_in"), 1122 SUNXI_FUNCTION(0x0, "gpio_in"),
671 SUNXI_FUNCTION(0x1, "gpio_out")), 1123 SUNXI_FUNCTION(0x1, "gpio_out"),
1124 SUNXI_FUNCTION(0x2, "lcd0")), /* D3 */
672 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4, 1125 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD4,
673 SUNXI_FUNCTION(0x0, "gpio_in"), 1126 SUNXI_FUNCTION(0x0, "gpio_in"),
674 SUNXI_FUNCTION(0x1, "gpio_out")), 1127 SUNXI_FUNCTION(0x1, "gpio_out"),
1128 SUNXI_FUNCTION(0x2, "lcd0")), /* D4 */
675 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5, 1129 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD5,
676 SUNXI_FUNCTION(0x0, "gpio_in"), 1130 SUNXI_FUNCTION(0x0, "gpio_in"),
677 SUNXI_FUNCTION(0x1, "gpio_out")), 1131 SUNXI_FUNCTION(0x1, "gpio_out"),
1132 SUNXI_FUNCTION(0x2, "lcd0")), /* D5 */
678 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6, 1133 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD6,
679 SUNXI_FUNCTION(0x0, "gpio_in"), 1134 SUNXI_FUNCTION(0x0, "gpio_in"),
680 SUNXI_FUNCTION(0x1, "gpio_out")), 1135 SUNXI_FUNCTION(0x1, "gpio_out"),
1136 SUNXI_FUNCTION(0x2, "lcd0")), /* D6 */
681 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7, 1137 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD7,
682 SUNXI_FUNCTION(0x0, "gpio_in"), 1138 SUNXI_FUNCTION(0x0, "gpio_in"),
683 SUNXI_FUNCTION(0x1, "gpio_out")), 1139 SUNXI_FUNCTION(0x1, "gpio_out"),
1140 SUNXI_FUNCTION(0x2, "lcd0")), /* D7 */
684 /* Hole */ 1141 /* Hole */
685 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10, 1142 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD10,
686 SUNXI_FUNCTION(0x0, "gpio_in"), 1143 SUNXI_FUNCTION(0x0, "gpio_in"),
687 SUNXI_FUNCTION(0x1, "gpio_out")), 1144 SUNXI_FUNCTION(0x1, "gpio_out"),
1145 SUNXI_FUNCTION(0x2, "lcd0")), /* D10 */
688 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11, 1146 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD11,
689 SUNXI_FUNCTION(0x0, "gpio_in"), 1147 SUNXI_FUNCTION(0x0, "gpio_in"),
690 SUNXI_FUNCTION(0x1, "gpio_out")), 1148 SUNXI_FUNCTION(0x1, "gpio_out"),
1149 SUNXI_FUNCTION(0x2, "lcd0")), /* D11 */
691 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12, 1150 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD12,
692 SUNXI_FUNCTION(0x0, "gpio_in"), 1151 SUNXI_FUNCTION(0x0, "gpio_in"),
693 SUNXI_FUNCTION(0x1, "gpio_out")), 1152 SUNXI_FUNCTION(0x1, "gpio_out"),
1153 SUNXI_FUNCTION(0x2, "lcd0")), /* D12 */
694 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13, 1154 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD13,
695 SUNXI_FUNCTION(0x0, "gpio_in"), 1155 SUNXI_FUNCTION(0x0, "gpio_in"),
696 SUNXI_FUNCTION(0x1, "gpio_out")), 1156 SUNXI_FUNCTION(0x1, "gpio_out"),
1157 SUNXI_FUNCTION(0x2, "lcd0")), /* D13 */
697 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14, 1158 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD14,
698 SUNXI_FUNCTION(0x0, "gpio_in"), 1159 SUNXI_FUNCTION(0x0, "gpio_in"),
699 SUNXI_FUNCTION(0x1, "gpio_out")), 1160 SUNXI_FUNCTION(0x1, "gpio_out"),
1161 SUNXI_FUNCTION(0x2, "lcd0")), /* D14 */
700 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15, 1162 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD15,
701 SUNXI_FUNCTION(0x0, "gpio_in"), 1163 SUNXI_FUNCTION(0x0, "gpio_in"),
702 SUNXI_FUNCTION(0x1, "gpio_out")), 1164 SUNXI_FUNCTION(0x1, "gpio_out"),
1165 SUNXI_FUNCTION(0x2, "lcd0")), /* D15 */
703 /* Hole */ 1166 /* Hole */
704 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18, 1167 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD18,
705 SUNXI_FUNCTION(0x0, "gpio_in"), 1168 SUNXI_FUNCTION(0x0, "gpio_in"),
706 SUNXI_FUNCTION(0x1, "gpio_out")), 1169 SUNXI_FUNCTION(0x1, "gpio_out"),
1170 SUNXI_FUNCTION(0x2, "lcd0")), /* D18 */
707 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19, 1171 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD19,
708 SUNXI_FUNCTION(0x0, "gpio_in"), 1172 SUNXI_FUNCTION(0x0, "gpio_in"),
709 SUNXI_FUNCTION(0x1, "gpio_out")), 1173 SUNXI_FUNCTION(0x1, "gpio_out"),
1174 SUNXI_FUNCTION(0x2, "lcd0")), /* D19 */
710 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20, 1175 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD20,
711 SUNXI_FUNCTION(0x0, "gpio_in"), 1176 SUNXI_FUNCTION(0x0, "gpio_in"),
712 SUNXI_FUNCTION(0x1, "gpio_out")), 1177 SUNXI_FUNCTION(0x1, "gpio_out"),
1178 SUNXI_FUNCTION(0x2, "lcd0")), /* D20 */
713 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21, 1179 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD21,
714 SUNXI_FUNCTION(0x0, "gpio_in"), 1180 SUNXI_FUNCTION(0x0, "gpio_in"),
715 SUNXI_FUNCTION(0x1, "gpio_out")), 1181 SUNXI_FUNCTION(0x1, "gpio_out"),
1182 SUNXI_FUNCTION(0x2, "lcd0")), /* D21 */
716 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22, 1183 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD22,
717 SUNXI_FUNCTION(0x0, "gpio_in"), 1184 SUNXI_FUNCTION(0x0, "gpio_in"),
718 SUNXI_FUNCTION(0x1, "gpio_out")), 1185 SUNXI_FUNCTION(0x1, "gpio_out"),
1186 SUNXI_FUNCTION(0x2, "lcd0")), /* D22 */
719 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23, 1187 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD23,
720 SUNXI_FUNCTION(0x0, "gpio_in"), 1188 SUNXI_FUNCTION(0x0, "gpio_in"),
721 SUNXI_FUNCTION(0x1, "gpio_out")), 1189 SUNXI_FUNCTION(0x1, "gpio_out"),
1190 SUNXI_FUNCTION(0x2, "lcd0")), /* D23 */
722 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24, 1191 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD24,
723 SUNXI_FUNCTION(0x0, "gpio_in"), 1192 SUNXI_FUNCTION(0x0, "gpio_in"),
724 SUNXI_FUNCTION(0x1, "gpio_out")), 1193 SUNXI_FUNCTION(0x1, "gpio_out"),
1194 SUNXI_FUNCTION(0x2, "lcd0")), /* CLK */
725 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25, 1195 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD25,
726 SUNXI_FUNCTION(0x0, "gpio_in"), 1196 SUNXI_FUNCTION(0x0, "gpio_in"),
727 SUNXI_FUNCTION(0x1, "gpio_out")), 1197 SUNXI_FUNCTION(0x1, "gpio_out"),
1198 SUNXI_FUNCTION(0x2, "lcd0")), /* DE */
728 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26, 1199 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD26,
729 SUNXI_FUNCTION(0x0, "gpio_in"), 1200 SUNXI_FUNCTION(0x0, "gpio_in"),
730 SUNXI_FUNCTION(0x1, "gpio_out")), 1201 SUNXI_FUNCTION(0x1, "gpio_out"),
1202 SUNXI_FUNCTION(0x2, "lcd0")), /* HSYNC */
731 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27, 1203 SUNXI_PIN(SUNXI_PINCTRL_PIN_PD27,
732 SUNXI_FUNCTION(0x0, "gpio_in"), 1204 SUNXI_FUNCTION(0x0, "gpio_in"),
733 SUNXI_FUNCTION(0x1, "gpio_out")), 1205 SUNXI_FUNCTION(0x1, "gpio_out"),
1206 SUNXI_FUNCTION(0x2, "lcd0")), /* VSYNC */
734 /* Hole */ 1207 /* Hole */
735 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0, 1208 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE0,
736 SUNXI_FUNCTION(0x0, "gpio_in"), 1209 SUNXI_FUNCTION(0x0, "gpio_in"),
737 SUNXI_FUNCTION(0x1, "gpio_out")), 1210 SUNXI_FUNCTION(0x3, "csi0"), /* PCLK */
1211 SUNXI_FUNCTION(0x4, "spi2")), /* CS0 */
738 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1, 1212 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE1,
739 SUNXI_FUNCTION(0x0, "gpio_in"), 1213 SUNXI_FUNCTION(0x0, "gpio_in"),
740 SUNXI_FUNCTION(0x1, "gpio_out")), 1214 SUNXI_FUNCTION(0x3, "csi0"), /* MCLK */
1215 SUNXI_FUNCTION(0x4, "spi2")), /* CLK */
741 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2, 1216 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE2,
742 SUNXI_FUNCTION(0x0, "gpio_in"), 1217 SUNXI_FUNCTION(0x0, "gpio_in"),
743 SUNXI_FUNCTION(0x1, "gpio_out")), 1218 SUNXI_FUNCTION(0x3, "csi0"), /* HSYNC */
1219 SUNXI_FUNCTION(0x4, "spi2")), /* MOSI */
744 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3, 1220 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE3,
745 SUNXI_FUNCTION(0x0, "gpio_in"), 1221 SUNXI_FUNCTION(0x0, "gpio_in"),
746 SUNXI_FUNCTION(0x1, "gpio_out")), 1222 SUNXI_FUNCTION(0x1, "gpio_out"),
1223 SUNXI_FUNCTION(0x3, "csi0"), /* VSYNC */
1224 SUNXI_FUNCTION(0x4, "spi2")), /* MISO */
747 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4, 1225 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE4,
748 SUNXI_FUNCTION(0x0, "gpio_in"), 1226 SUNXI_FUNCTION(0x0, "gpio_in"),
749 SUNXI_FUNCTION(0x1, "gpio_out")), 1227 SUNXI_FUNCTION(0x1, "gpio_out"),
1228 SUNXI_FUNCTION(0x3, "csi0"), /* D0 */
1229 SUNXI_FUNCTION(0x4, "mmc2")), /* D0 */
750 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5, 1230 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE5,
751 SUNXI_FUNCTION(0x0, "gpio_in"), 1231 SUNXI_FUNCTION(0x0, "gpio_in"),
752 SUNXI_FUNCTION(0x1, "gpio_out")), 1232 SUNXI_FUNCTION(0x1, "gpio_out"),
1233 SUNXI_FUNCTION(0x3, "csi0"), /* D1 */
1234 SUNXI_FUNCTION(0x4, "mmc2")), /* D1 */
753 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6, 1235 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE6,
754 SUNXI_FUNCTION(0x0, "gpio_in"), 1236 SUNXI_FUNCTION(0x0, "gpio_in"),
755 SUNXI_FUNCTION(0x1, "gpio_out")), 1237 SUNXI_FUNCTION(0x1, "gpio_out"),
1238 SUNXI_FUNCTION(0x3, "csi0"), /* D2 */
1239 SUNXI_FUNCTION(0x4, "mmc2")), /* D2 */
756 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7, 1240 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE7,
757 SUNXI_FUNCTION(0x0, "gpio_in"), 1241 SUNXI_FUNCTION(0x0, "gpio_in"),
758 SUNXI_FUNCTION(0x1, "gpio_out")), 1242 SUNXI_FUNCTION(0x1, "gpio_out"),
1243 SUNXI_FUNCTION(0x3, "csi0"), /* D3 */
1244 SUNXI_FUNCTION(0x4, "mmc2")), /* D3 */
759 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8, 1245 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE8,
760 SUNXI_FUNCTION(0x0, "gpio_in"), 1246 SUNXI_FUNCTION(0x0, "gpio_in"),
761 SUNXI_FUNCTION(0x1, "gpio_out")), 1247 SUNXI_FUNCTION(0x1, "gpio_out"),
1248 SUNXI_FUNCTION(0x3, "csi0"), /* D4 */
1249 SUNXI_FUNCTION(0x4, "mmc2")), /* CMD */
762 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9, 1250 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE9,
763 SUNXI_FUNCTION(0x0, "gpio_in"), 1251 SUNXI_FUNCTION(0x0, "gpio_in"),
764 SUNXI_FUNCTION(0x1, "gpio_out")), 1252 SUNXI_FUNCTION(0x1, "gpio_out"),
1253 SUNXI_FUNCTION(0x3, "csi0"), /* D5 */
1254 SUNXI_FUNCTION(0x4, "mmc2")), /* CLK */
765 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10, 1255 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE10,
766 SUNXI_FUNCTION(0x0, "gpio_in"), 1256 SUNXI_FUNCTION(0x0, "gpio_in"),
767 SUNXI_FUNCTION(0x1, "gpio_out"), 1257 SUNXI_FUNCTION(0x1, "gpio_out"),
1258 SUNXI_FUNCTION(0x3, "csi0"), /* D6 */
768 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 1259 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
769 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11, 1260 SUNXI_PIN(SUNXI_PINCTRL_PIN_PE11,
770 SUNXI_FUNCTION(0x0, "gpio_in"), 1261 SUNXI_FUNCTION(0x0, "gpio_in"),
771 SUNXI_FUNCTION(0x1, "gpio_out"), 1262 SUNXI_FUNCTION(0x1, "gpio_out"),
1263 SUNXI_FUNCTION(0x3, "csi0"), /* D7 */
772 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 1264 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
773 /* Hole */ 1265 /* Hole */
774 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0, 1266 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF0,
775 SUNXI_FUNCTION(0x0, "gpio_in"), 1267 SUNXI_FUNCTION(0x0, "gpio_in"),
776 SUNXI_FUNCTION(0x1, "gpio_out")), 1268 SUNXI_FUNCTION(0x1, "gpio_out"),
1269 SUNXI_FUNCTION(0x4, "mmc0")), /* D1 */
777 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1, 1270 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF1,
778 SUNXI_FUNCTION(0x0, "gpio_in"), 1271 SUNXI_FUNCTION(0x0, "gpio_in"),
779 SUNXI_FUNCTION(0x1, "gpio_out")), 1272 SUNXI_FUNCTION(0x1, "gpio_out"),
1273 SUNXI_FUNCTION(0x4, "mmc0")), /* D0 */
780 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2, 1274 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF2,
781 SUNXI_FUNCTION(0x0, "gpio_in"), 1275 SUNXI_FUNCTION(0x0, "gpio_in"),
782 SUNXI_FUNCTION(0x1, "gpio_out")), 1276 SUNXI_FUNCTION(0x1, "gpio_out"),
1277 SUNXI_FUNCTION(0x4, "mmc0")), /* CLK */
783 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3, 1278 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF3,
784 SUNXI_FUNCTION(0x0, "gpio_in"), 1279 SUNXI_FUNCTION(0x0, "gpio_in"),
785 SUNXI_FUNCTION(0x1, "gpio_out")), 1280 SUNXI_FUNCTION(0x1, "gpio_out"),
1281 SUNXI_FUNCTION(0x4, "mmc0")), /* CMD */
786 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4, 1282 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF4,
787 SUNXI_FUNCTION(0x0, "gpio_in"), 1283 SUNXI_FUNCTION(0x0, "gpio_in"),
788 SUNXI_FUNCTION(0x1, "gpio_out")), 1284 SUNXI_FUNCTION(0x1, "gpio_out"),
1285 SUNXI_FUNCTION(0x4, "mmc0")), /* D3 */
789 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5, 1286 SUNXI_PIN(SUNXI_PINCTRL_PIN_PF5,
790 SUNXI_FUNCTION(0x0, "gpio_in"), 1287 SUNXI_FUNCTION(0x0, "gpio_in"),
791 SUNXI_FUNCTION(0x1, "gpio_out")), 1288 SUNXI_FUNCTION(0x1, "gpio_out"),
1289 SUNXI_FUNCTION(0x4, "mmc0")), /* D2 */
792 /* Hole */ 1290 /* Hole */
793 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0, 1291 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG0,
794 SUNXI_FUNCTION(0x0, "gpio_in"), 1292 SUNXI_FUNCTION(0x0, "gpio_in"),
@@ -802,24 +1300,34 @@ static const struct sunxi_desc_pin sun5i_a13_pins[] = {
802 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3, 1300 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG3,
803 SUNXI_FUNCTION(0x0, "gpio_in"), 1301 SUNXI_FUNCTION(0x0, "gpio_in"),
804 SUNXI_FUNCTION(0x1, "gpio_out"), 1302 SUNXI_FUNCTION(0x1, "gpio_out"),
1303 SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
805 SUNXI_FUNCTION(0x4, "uart1")), /* TX */ 1304 SUNXI_FUNCTION(0x4, "uart1")), /* TX */
806 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4, 1305 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG4,
807 SUNXI_FUNCTION(0x0, "gpio_in"), 1306 SUNXI_FUNCTION(0x0, "gpio_in"),
808 SUNXI_FUNCTION(0x1, "gpio_out"), 1307 SUNXI_FUNCTION(0x1, "gpio_out"),
1308 SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
809 SUNXI_FUNCTION(0x4, "uart1")), /* RX */ 1309 SUNXI_FUNCTION(0x4, "uart1")), /* RX */
810 /* Hole */ 1310/* Hole */
811 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9, 1311 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG9,
812 SUNXI_FUNCTION(0x0, "gpio_in"), 1312 SUNXI_FUNCTION(0x0, "gpio_in"),
813 SUNXI_FUNCTION(0x1, "gpio_out")), 1313 SUNXI_FUNCTION(0x1, "gpio_out"),
1314 SUNXI_FUNCTION(0x2, "spi1"), /* CS0 */
1315 SUNXI_FUNCTION(0x3, "uart3")), /* TX */
814 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10, 1316 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG10,
815 SUNXI_FUNCTION(0x0, "gpio_in"), 1317 SUNXI_FUNCTION(0x0, "gpio_in"),
816 SUNXI_FUNCTION(0x1, "gpio_out")), 1318 SUNXI_FUNCTION(0x1, "gpio_out"),
1319 SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
1320 SUNXI_FUNCTION(0x3, "uart3")), /* RX */
817 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11, 1321 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG11,
818 SUNXI_FUNCTION(0x0, "gpio_in"), 1322 SUNXI_FUNCTION(0x0, "gpio_in"),
819 SUNXI_FUNCTION(0x1, "gpio_out")), 1323 SUNXI_FUNCTION(0x1, "gpio_out"),
1324 SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
1325 SUNXI_FUNCTION(0x3, "uart3")), /* CTS */
820 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12, 1326 SUNXI_PIN(SUNXI_PINCTRL_PIN_PG12,
821 SUNXI_FUNCTION(0x0, "gpio_in"), 1327 SUNXI_FUNCTION(0x0, "gpio_in"),
822 SUNXI_FUNCTION(0x1, "gpio_out")), 1328 SUNXI_FUNCTION(0x1, "gpio_out"),
1329 SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
1330 SUNXI_FUNCTION(0x3, "uart3")), /* RTS */
823}; 1331};
824 1332
825static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = { 1333static const struct sunxi_pinctrl_desc sun4i_a10_pinctrl_data = {
@@ -1029,7 +1537,7 @@ static void sunxi_pctrl_dt_free_map(struct pinctrl_dev *pctldev,
1029 kfree(map); 1537 kfree(map);
1030} 1538}
1031 1539
1032static struct pinctrl_ops sunxi_pctrl_ops = { 1540static const struct pinctrl_ops sunxi_pctrl_ops = {
1033 .dt_node_to_map = sunxi_pctrl_dt_node_to_map, 1541 .dt_node_to_map = sunxi_pctrl_dt_node_to_map,
1034 .dt_free_map = sunxi_pctrl_dt_free_map, 1542 .dt_free_map = sunxi_pctrl_dt_free_map,
1035 .get_groups_count = sunxi_pctrl_get_groups_count, 1543 .get_groups_count = sunxi_pctrl_get_groups_count,
@@ -1098,7 +1606,7 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
1098 return 0; 1606 return 0;
1099} 1607}
1100 1608
1101static struct pinconf_ops sunxi_pconf_ops = { 1609static const struct pinconf_ops sunxi_pconf_ops = {
1102 .pin_config_group_get = sunxi_pconf_group_get, 1610 .pin_config_group_get = sunxi_pconf_group_get,
1103 .pin_config_group_set = sunxi_pconf_group_set, 1611 .pin_config_group_set = sunxi_pconf_group_set,
1104}; 1612};
@@ -1204,7 +1712,7 @@ error:
1204 return ret; 1712 return ret;
1205} 1713}
1206 1714
1207static struct pinmux_ops sunxi_pmx_ops = { 1715static const struct pinmux_ops sunxi_pmx_ops = {
1208 .get_functions_count = sunxi_pmx_get_funcs_cnt, 1716 .get_functions_count = sunxi_pmx_get_funcs_cnt,
1209 .get_function_name = sunxi_pmx_get_func_name, 1717 .get_function_name = sunxi_pmx_get_func_name,
1210 .get_function_groups = sunxi_pmx_get_func_groups, 1718 .get_function_groups = sunxi_pmx_get_func_groups,
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c
index f195d77a3572..2fa9bc6cd7ab 100644
--- a/drivers/pinctrl/pinctrl-tegra.c
+++ b/drivers/pinctrl/pinctrl-tegra.c
@@ -316,7 +316,7 @@ static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
316 return 0; 316 return 0;
317} 317}
318 318
319static struct pinctrl_ops tegra_pinctrl_ops = { 319static const struct pinctrl_ops tegra_pinctrl_ops = {
320 .get_groups_count = tegra_pinctrl_get_groups_count, 320 .get_groups_count = tegra_pinctrl_get_groups_count,
321 .get_group_name = tegra_pinctrl_get_group_name, 321 .get_group_name = tegra_pinctrl_get_group_name,
322 .get_group_pins = tegra_pinctrl_get_group_pins, 322 .get_group_pins = tegra_pinctrl_get_group_pins,
@@ -401,7 +401,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev,
401 pmx_writel(pmx, val, g->mux_bank, g->mux_reg); 401 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
402} 402}
403 403
404static struct pinmux_ops tegra_pinmux_ops = { 404static const struct pinmux_ops tegra_pinmux_ops = {
405 .get_functions_count = tegra_pinctrl_get_funcs_count, 405 .get_functions_count = tegra_pinctrl_get_funcs_count,
406 .get_function_name = tegra_pinctrl_get_func_name, 406 .get_function_name = tegra_pinctrl_get_func_name,
407 .get_function_groups = tegra_pinctrl_get_func_groups, 407 .get_function_groups = tegra_pinctrl_get_func_groups,
@@ -676,7 +676,7 @@ static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
676} 676}
677#endif 677#endif
678 678
679static struct pinconf_ops tegra_pinconf_ops = { 679static const struct pinconf_ops tegra_pinconf_ops = {
680 .pin_config_get = tegra_pinconf_get, 680 .pin_config_get = tegra_pinconf_get,
681 .pin_config_set = tegra_pinconf_set, 681 .pin_config_set = tegra_pinconf_set,
682 .pin_config_group_get = tegra_pinconf_group_get, 682 .pin_config_group_get = tegra_pinconf_group_get,
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 2b5772550836..6a3a7503e6a0 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -860,7 +860,7 @@ static void u300_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
860 seq_printf(s, " " DRIVER_NAME); 860 seq_printf(s, " " DRIVER_NAME);
861} 861}
862 862
863static struct pinctrl_ops u300_pctrl_ops = { 863static const struct pinctrl_ops u300_pctrl_ops = {
864 .get_groups_count = u300_get_groups_count, 864 .get_groups_count = u300_get_groups_count,
865 .get_group_name = u300_get_group_name, 865 .get_group_name = u300_get_group_name,
866 .get_group_pins = u300_get_group_pins, 866 .get_group_pins = u300_get_group_pins,
@@ -1003,7 +1003,7 @@ static int u300_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
1003 return 0; 1003 return 0;
1004} 1004}
1005 1005
1006static struct pinmux_ops u300_pmx_ops = { 1006static const struct pinmux_ops u300_pmx_ops = {
1007 .get_functions_count = u300_pmx_get_funcs_count, 1007 .get_functions_count = u300_pmx_get_funcs_count,
1008 .get_function_name = u300_pmx_get_func_name, 1008 .get_function_name = u300_pmx_get_func_name,
1009 .get_function_groups = u300_pmx_get_groups, 1009 .get_function_groups = u300_pmx_get_groups,
@@ -1046,7 +1046,7 @@ static int u300_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
1046 return 0; 1046 return 0;
1047} 1047}
1048 1048
1049static struct pinconf_ops u300_pconf_ops = { 1049static const struct pinconf_ops u300_pconf_ops = {
1050 .is_generic = true, 1050 .is_generic = true,
1051 .pin_config_get = u300_pin_config_get, 1051 .pin_config_get = u300_pin_config_get,
1052 .pin_config_set = u300_pin_config_set, 1052 .pin_config_set = u300_pin_config_set,
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
index 068224efa6fa..f2977cff8366 100644
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -553,7 +553,7 @@ int xway_pinconf_group_set(struct pinctrl_dev *pctldev,
553 return ret; 553 return ret;
554} 554}
555 555
556static struct pinconf_ops xway_pinconf_ops = { 556static const struct pinconf_ops xway_pinconf_ops = {
557 .pin_config_get = xway_pinconf_get, 557 .pin_config_get = xway_pinconf_get,
558 .pin_config_set = xway_pinconf_set, 558 .pin_config_set = xway_pinconf_set,
559 .pin_config_group_set = xway_pinconf_group_set, 559 .pin_config_group_set = xway_pinconf_group_set,
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index c3340f54d2ad..0e1f99c33d47 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -10,6 +10,7 @@ config PINCTRL_SH_PFC
10 select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB 10 select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
11 select PINMUX 11 select PINMUX
12 select PINCONF 12 select PINCONF
13 select GENERIC_PINCONF
13 def_bool y 14 def_bool y
14 help 15 help
15 This enables pin control drivers for SH and SH Mobile platforms 16 This enables pin control drivers for SH and SH Mobile platforms
@@ -21,6 +22,11 @@ config GPIO_SH_PFC
21 This enables support for GPIOs within the SoC's pin function 22 This enables support for GPIOs within the SoC's pin function
22 controller. 23 controller.
23 24
25config PINCTRL_PFC_R8A73A4
26 def_bool y
27 depends on ARCH_R8A73A4
28 select PINCTRL_SH_PFC
29
24config PINCTRL_PFC_R8A7740 30config PINCTRL_PFC_R8A7740
25 def_bool y 31 def_bool y
26 depends on ARCH_R8A7740 32 depends on ARCH_R8A7740
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index e8b9562c47e1..211cd8e98a8a 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -3,6 +3,7 @@ ifeq ($(CONFIG_GPIO_SH_PFC),y)
3sh-pfc-objs += gpio.o 3sh-pfc-objs += gpio.o
4endif 4endif
5obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o 5obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc.o
6obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o
6obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o 7obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
7obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o 8obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
8obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o 9obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 970ddff2b0b6..b551336924a5 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -10,7 +10,6 @@
10 */ 10 */
11 11
12#define DRV_NAME "sh-pfc" 12#define DRV_NAME "sh-pfc"
13#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
14 13
15#include <linux/bitops.h> 14#include <linux/bitops.h>
16#include <linux/err.h> 15#include <linux/err.h>
@@ -30,10 +29,8 @@ static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev)
30 struct resource *res; 29 struct resource *res;
31 int k; 30 int k;
32 31
33 if (pdev->num_resources == 0) { 32 if (pdev->num_resources == 0)
34 pfc->num_windows = 0; 33 return -EINVAL;
35 return 0;
36 }
37 34
38 pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources * 35 pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources *
39 sizeof(*pfc->window), GFP_NOWAIT); 36 sizeof(*pfc->window), GFP_NOWAIT);
@@ -59,11 +56,11 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
59 unsigned long address) 56 unsigned long address)
60{ 57{
61 struct sh_pfc_window *window; 58 struct sh_pfc_window *window;
62 int k; 59 unsigned int i;
63 60
64 /* scan through physical windows and convert address */ 61 /* scan through physical windows and convert address */
65 for (k = 0; k < pfc->num_windows; k++) { 62 for (i = 0; i < pfc->num_windows; i++) {
66 window = pfc->window + k; 63 window = pfc->window + i;
67 64
68 if (address < window->phys) 65 if (address < window->phys)
69 continue; 66 continue;
@@ -74,11 +71,33 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
74 return window->virt + (address - window->phys); 71 return window->virt + (address - window->phys);
75 } 72 }
76 73
77 /* no windows defined, register must be 1:1 mapped virt:phys */ 74 BUG();
78 return (void __iomem *)address; 75 return NULL;
76}
77
78int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
79{
80 unsigned int offset;
81 unsigned int i;
82
83 if (pfc->info->ranges == NULL)
84 return pin;
85
86 for (i = 0, offset = 0; i < pfc->info->nr_ranges; ++i) {
87 const struct pinmux_range *range = &pfc->info->ranges[i];
88
89 if (pin <= range->end)
90 return pin >= range->begin
91 ? offset + pin - range->begin : -1;
92
93 offset += range->end - range->begin + 1;
94 }
95
96 return -EINVAL;
79} 97}
80 98
81static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r) 99static int sh_pfc_enum_in_range(pinmux_enum_t enum_id,
100 const struct pinmux_range *r)
82{ 101{
83 if (enum_id < r->begin) 102 if (enum_id < r->begin)
84 return 0; 103 return 0;
@@ -89,8 +108,8 @@ static int sh_pfc_enum_in_range(pinmux_enum_t enum_id, struct pinmux_range *r)
89 return 1; 108 return 1;
90} 109}
91 110
92static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg, 111unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
93 unsigned long reg_width) 112 unsigned long reg_width)
94{ 113{
95 switch (reg_width) { 114 switch (reg_width) {
96 case 8: 115 case 8:
@@ -105,8 +124,8 @@ static unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
105 return 0; 124 return 0;
106} 125}
107 126
108static void sh_pfc_write_raw_reg(void __iomem *mapped_reg, 127void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
109 unsigned long reg_width, unsigned long data) 128 unsigned long data)
110{ 129{
111 switch (reg_width) { 130 switch (reg_width) {
112 case 8: 131 case 8:
@@ -123,39 +142,8 @@ static void sh_pfc_write_raw_reg(void __iomem *mapped_reg,
123 BUG(); 142 BUG();
124} 143}
125 144
126int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos)
127{
128 unsigned long pos;
129
130 pos = dr->reg_width - (in_pos + 1);
131
132 pr_debug("read_bit: addr = %lx, pos = %ld, "
133 "r_width = %ld\n", dr->reg, pos, dr->reg_width);
134
135 return (sh_pfc_read_raw_reg(dr->mapped_reg, dr->reg_width) >> pos) & 1;
136}
137
138void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos,
139 unsigned long value)
140{
141 unsigned long pos;
142
143 pos = dr->reg_width - (in_pos + 1);
144
145 pr_debug("write_bit addr = %lx, value = %d, pos = %ld, "
146 "r_width = %ld\n",
147 dr->reg, !!value, pos, dr->reg_width);
148
149 if (value)
150 set_bit(pos, &dr->reg_shadow);
151 else
152 clear_bit(pos, &dr->reg_shadow);
153
154 sh_pfc_write_raw_reg(dr->mapped_reg, dr->reg_width, dr->reg_shadow);
155}
156
157static void sh_pfc_config_reg_helper(struct sh_pfc *pfc, 145static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
158 struct pinmux_cfg_reg *crp, 146 const struct pinmux_cfg_reg *crp,
159 unsigned long in_pos, 147 unsigned long in_pos,
160 void __iomem **mapped_regp, 148 void __iomem **mapped_regp,
161 unsigned long *maskp, 149 unsigned long *maskp,
@@ -176,24 +164,8 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
176 } 164 }
177} 165}
178 166
179static int sh_pfc_read_config_reg(struct sh_pfc *pfc,
180 struct pinmux_cfg_reg *crp,
181 unsigned long field)
182{
183 void __iomem *mapped_reg;
184 unsigned long mask, pos;
185
186 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
187
188 pr_debug("read_reg: addr = %lx, field = %ld, "
189 "r_width = %ld, f_width = %ld\n",
190 crp->reg, field, crp->reg_width, crp->field_width);
191
192 return (sh_pfc_read_raw_reg(mapped_reg, crp->reg_width) >> pos) & mask;
193}
194
195static void sh_pfc_write_config_reg(struct sh_pfc *pfc, 167static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
196 struct pinmux_cfg_reg *crp, 168 const struct pinmux_cfg_reg *crp,
197 unsigned long field, unsigned long value) 169 unsigned long field, unsigned long value)
198{ 170{
199 void __iomem *mapped_reg; 171 void __iomem *mapped_reg;
@@ -201,9 +173,9 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
201 173
202 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos); 174 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
203 175
204 pr_debug("write_reg addr = %lx, value = %ld, field = %ld, " 176 dev_dbg(pfc->dev, "write_reg addr = %lx, value = %ld, field = %ld, "
205 "r_width = %ld, f_width = %ld\n", 177 "r_width = %ld, f_width = %ld\n",
206 crp->reg, value, field, crp->reg_width, crp->field_width); 178 crp->reg, value, field, crp->reg_width, crp->field_width);
207 179
208 mask = ~(mask << pos); 180 mask = ~(mask << pos);
209 value = value << pos; 181 value = value << pos;
@@ -220,83 +192,11 @@ static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
220 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data); 192 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
221} 193}
222 194
223static int sh_pfc_setup_data_reg(struct sh_pfc *pfc, unsigned gpio)
224{
225 struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
226 struct pinmux_data_reg *data_reg;
227 int k, n;
228
229 if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data))
230 return -1;
231
232 k = 0;
233 while (1) {
234 data_reg = pfc->info->data_regs + k;
235
236 if (!data_reg->reg_width)
237 break;
238
239 data_reg->mapped_reg = sh_pfc_phys_to_virt(pfc, data_reg->reg);
240
241 for (n = 0; n < data_reg->reg_width; n++) {
242 if (data_reg->enum_ids[n] == gpiop->enum_id) {
243 gpiop->flags &= ~PINMUX_FLAG_DREG;
244 gpiop->flags |= (k << PINMUX_FLAG_DREG_SHIFT);
245 gpiop->flags &= ~PINMUX_FLAG_DBIT;
246 gpiop->flags |= (n << PINMUX_FLAG_DBIT_SHIFT);
247 return 0;
248 }
249 }
250 k++;
251 }
252
253 BUG();
254
255 return -1;
256}
257
258static void sh_pfc_setup_data_regs(struct sh_pfc *pfc)
259{
260 struct pinmux_data_reg *drp;
261 int k;
262
263 for (k = pfc->info->first_gpio; k <= pfc->info->last_gpio; k++)
264 sh_pfc_setup_data_reg(pfc, k);
265
266 k = 0;
267 while (1) {
268 drp = pfc->info->data_regs + k;
269
270 if (!drp->reg_width)
271 break;
272
273 drp->reg_shadow = sh_pfc_read_raw_reg(drp->mapped_reg,
274 drp->reg_width);
275 k++;
276 }
277}
278
279int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio,
280 struct pinmux_data_reg **drp, int *bitp)
281{
282 struct pinmux_gpio *gpiop = &pfc->info->gpios[gpio];
283 int k, n;
284
285 if (!sh_pfc_enum_in_range(gpiop->enum_id, &pfc->info->data))
286 return -1;
287
288 k = (gpiop->flags & PINMUX_FLAG_DREG) >> PINMUX_FLAG_DREG_SHIFT;
289 n = (gpiop->flags & PINMUX_FLAG_DBIT) >> PINMUX_FLAG_DBIT_SHIFT;
290 *drp = pfc->info->data_regs + k;
291 *bitp = n;
292 return 0;
293}
294
295static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id, 195static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
296 struct pinmux_cfg_reg **crp, int *fieldp, 196 const struct pinmux_cfg_reg **crp, int *fieldp,
297 int *valuep, unsigned long **cntp) 197 int *valuep)
298{ 198{
299 struct pinmux_cfg_reg *config_reg; 199 const struct pinmux_cfg_reg *config_reg;
300 unsigned long r_width, f_width, curr_width, ncomb; 200 unsigned long r_width, f_width, curr_width, ncomb;
301 int k, m, n, pos, bit_pos; 201 int k, m, n, pos, bit_pos;
302 202
@@ -324,7 +224,6 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
324 *crp = config_reg; 224 *crp = config_reg;
325 *fieldp = m; 225 *fieldp = m;
326 *valuep = n; 226 *valuep = n;
327 *cntp = &config_reg->cnt[m];
328 return 0; 227 return 0;
329 } 228 }
330 } 229 }
@@ -334,50 +233,42 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, pinmux_enum_t enum_id,
334 k++; 233 k++;
335 } 234 }
336 235
337 return -1; 236 return -EINVAL;
338} 237}
339 238
340int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, 239static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, pinmux_enum_t mark, int pos,
341 pinmux_enum_t *enum_idp) 240 pinmux_enum_t *enum_idp)
342{ 241{
343 pinmux_enum_t enum_id = pfc->info->gpios[gpio].enum_id; 242 const pinmux_enum_t *data = pfc->info->gpio_data;
344 pinmux_enum_t *data = pfc->info->gpio_data;
345 int k; 243 int k;
346 244
347 if (!sh_pfc_enum_in_range(enum_id, &pfc->info->data)) {
348 if (!sh_pfc_enum_in_range(enum_id, &pfc->info->mark)) {
349 pr_err("non data/mark enum_id for gpio %d\n", gpio);
350 return -1;
351 }
352 }
353
354 if (pos) { 245 if (pos) {
355 *enum_idp = data[pos + 1]; 246 *enum_idp = data[pos + 1];
356 return pos + 1; 247 return pos + 1;
357 } 248 }
358 249
359 for (k = 0; k < pfc->info->gpio_data_size; k++) { 250 for (k = 0; k < pfc->info->gpio_data_size; k++) {
360 if (data[k] == enum_id) { 251 if (data[k] == mark) {
361 *enum_idp = data[k + 1]; 252 *enum_idp = data[k + 1];
362 return k + 1; 253 return k + 1;
363 } 254 }
364 } 255 }
365 256
366 pr_err("cannot locate data/mark enum_id for gpio %d\n", gpio); 257 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
367 return -1; 258 mark);
259 return -EINVAL;
368} 260}
369 261
370int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type, 262int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
371 int cfg_mode)
372{ 263{
373 struct pinmux_cfg_reg *cr = NULL; 264 const struct pinmux_cfg_reg *cr = NULL;
374 pinmux_enum_t enum_id; 265 pinmux_enum_t enum_id;
375 struct pinmux_range *range; 266 const struct pinmux_range *range;
376 int in_range, pos, field, value; 267 int in_range, pos, field, value;
377 unsigned long *cntp; 268 int ret;
378 269
379 switch (pinmux_type) { 270 switch (pinmux_type) {
380 271 case PINMUX_TYPE_GPIO:
381 case PINMUX_TYPE_FUNCTION: 272 case PINMUX_TYPE_FUNCTION:
382 range = NULL; 273 range = NULL;
383 break; 274 break;
@@ -399,33 +290,37 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
399 break; 290 break;
400 291
401 default: 292 default:
402 goto out_err; 293 return -EINVAL;
403 } 294 }
404 295
405 pos = 0; 296 pos = 0;
406 enum_id = 0; 297 enum_id = 0;
407 field = 0; 298 field = 0;
408 value = 0; 299 value = 0;
300
301 /* Iterate over all the configuration fields we need to update. */
409 while (1) { 302 while (1) {
410 pos = sh_pfc_gpio_to_enum(pfc, gpio, pos, &enum_id); 303 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
411 if (pos <= 0) 304 if (pos < 0)
412 goto out_err; 305 return pos;
413 306
414 if (!enum_id) 307 if (!enum_id)
415 break; 308 break;
416 309
417 /* first check if this is a function enum */ 310 /* Check if the configuration field selects a function. If it
311 * doesn't, skip the field if it's not applicable to the
312 * requested pinmux type.
313 */
418 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function); 314 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
419 if (!in_range) { 315 if (!in_range) {
420 /* not a function enum */ 316 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
421 if (range) { 317 /* Functions are allowed to modify all
422 /* 318 * fields.
423 * other range exists, so this pin is 319 */
424 * a regular GPIO pin that now is being 320 in_range = 1;
425 * bound to a specific direction. 321 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
426 * 322 /* Input/output types can only modify fields
427 * for this case we only allow function enums 323 * that correspond to their respective ranges.
428 * and the enums that match the other range.
429 */ 324 */
430 in_range = sh_pfc_enum_in_range(enum_id, range); 325 in_range = sh_pfc_enum_in_range(enum_id, range);
431 326
@@ -436,60 +331,29 @@ int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
436 */ 331 */
437 if (in_range && enum_id == range->force) 332 if (in_range && enum_id == range->force)
438 continue; 333 continue;
439 } else {
440 /*
441 * no other range exists, so this pin
442 * must then be of the function type.
443 *
444 * allow function type pins to select
445 * any combination of function/in/out
446 * in their MARK lists.
447 */
448 in_range = 1;
449 } 334 }
335 /* GPIOs are only allowed to modify function fields. */
450 } 336 }
451 337
452 if (!in_range) 338 if (!in_range)
453 continue; 339 continue;
454 340
455 if (sh_pfc_get_config_reg(pfc, enum_id, &cr, 341 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
456 &field, &value, &cntp) != 0) 342 if (ret < 0)
457 goto out_err; 343 return ret;
458
459 switch (cfg_mode) {
460 case GPIO_CFG_DRYRUN:
461 if (!*cntp ||
462 (sh_pfc_read_config_reg(pfc, cr, field) != value))
463 continue;
464 break;
465
466 case GPIO_CFG_REQ:
467 sh_pfc_write_config_reg(pfc, cr, field, value);
468 *cntp = *cntp + 1;
469 break;
470 344
471 case GPIO_CFG_FREE: 345 sh_pfc_write_config_reg(pfc, cr, field, value);
472 *cntp = *cntp - 1;
473 break;
474 }
475 } 346 }
476 347
477 return 0; 348 return 0;
478 out_err:
479 return -1;
480} 349}
481 350
482static int sh_pfc_probe(struct platform_device *pdev) 351static int sh_pfc_probe(struct platform_device *pdev)
483{ 352{
484 struct sh_pfc_soc_info *info; 353 const struct sh_pfc_soc_info *info;
485 struct sh_pfc *pfc; 354 struct sh_pfc *pfc;
486 int ret; 355 int ret;
487 356
488 /*
489 * Ensure that the type encoding fits
490 */
491 BUILD_BUG_ON(PINMUX_FLAG_TYPE > ((1 << PINMUX_FLAG_DBIT_SHIFT) - 1));
492
493 info = pdev->id_entry->driver_data 357 info = pdev->id_entry->driver_data
494 ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data; 358 ? (void *)pdev->id_entry->driver_data : pdev->dev.platform_data;
495 if (info == NULL) 359 if (info == NULL)
@@ -509,7 +373,6 @@ static int sh_pfc_probe(struct platform_device *pdev)
509 spin_lock_init(&pfc->lock); 373 spin_lock_init(&pfc->lock);
510 374
511 pinctrl_provide_dummies(); 375 pinctrl_provide_dummies();
512 sh_pfc_setup_data_regs(pfc);
513 376
514 /* 377 /*
515 * Initialize pinctrl bindings first 378 * Initialize pinctrl bindings first
@@ -529,13 +392,13 @@ static int sh_pfc_probe(struct platform_device *pdev)
529 * PFC state as it is, given that there are already 392 * PFC state as it is, given that there are already
530 * extant users of it that have succeeded by this point. 393 * extant users of it that have succeeded by this point.
531 */ 394 */
532 pr_notice("failed to init GPIO chip, ignoring...\n"); 395 dev_notice(pfc->dev, "failed to init GPIO chip, ignoring...\n");
533 } 396 }
534#endif 397#endif
535 398
536 platform_set_drvdata(pdev, pfc); 399 platform_set_drvdata(pdev, pfc);
537 400
538 pr_info("%s support registered\n", info->name); 401 dev_info(pfc->dev, "%s support registered\n", info->name);
539 402
540 return 0; 403 return 0;
541} 404}
@@ -555,6 +418,9 @@ static int sh_pfc_remove(struct platform_device *pdev)
555} 418}
556 419
557static const struct platform_device_id sh_pfc_id_table[] = { 420static const struct platform_device_id sh_pfc_id_table[] = {
421#ifdef CONFIG_PINCTRL_PFC_R8A73A4
422 { "pfc-r8a73a4", (kernel_ulong_t)&r8a73a4_pinmux_info },
423#endif
558#ifdef CONFIG_PINCTRL_PFC_R8A7740 424#ifdef CONFIG_PINCTRL_PFC_R8A7740
559 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info }, 425 { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
560#endif 426#endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index ba7c33c33599..89cb4289d761 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -26,13 +26,17 @@ struct sh_pfc_pinctrl;
26 26
27struct sh_pfc { 27struct sh_pfc {
28 struct device *dev; 28 struct device *dev;
29 struct sh_pfc_soc_info *info; 29 const struct sh_pfc_soc_info *info;
30 spinlock_t lock; 30 spinlock_t lock;
31 31
32 unsigned int num_windows; 32 unsigned int num_windows;
33 struct sh_pfc_window *window; 33 struct sh_pfc_window *window;
34 34
35 unsigned int nr_pins;
36
35 struct sh_pfc_chip *gpio; 37 struct sh_pfc_chip *gpio;
38 struct sh_pfc_chip *func;
39
36 struct sh_pfc_pinctrl *pinctrl; 40 struct sh_pfc_pinctrl *pinctrl;
37}; 41};
38 42
@@ -42,31 +46,30 @@ int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc);
42int sh_pfc_register_pinctrl(struct sh_pfc *pfc); 46int sh_pfc_register_pinctrl(struct sh_pfc *pfc);
43int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc); 47int sh_pfc_unregister_pinctrl(struct sh_pfc *pfc);
44 48
45int sh_pfc_read_bit(struct pinmux_data_reg *dr, unsigned long in_pos); 49unsigned long sh_pfc_read_raw_reg(void __iomem *mapped_reg,
46void sh_pfc_write_bit(struct pinmux_data_reg *dr, unsigned long in_pos, 50 unsigned long reg_width);
47 unsigned long value); 51void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned long reg_width,
48int sh_pfc_get_data_reg(struct sh_pfc *pfc, unsigned gpio, 52 unsigned long data);
49 struct pinmux_data_reg **drp, int *bitp); 53
50int sh_pfc_gpio_to_enum(struct sh_pfc *pfc, unsigned gpio, int pos, 54int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin);
51 pinmux_enum_t *enum_idp); 55int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
52int sh_pfc_config_gpio(struct sh_pfc *pfc, unsigned gpio, int pinmux_type,
53 int cfg_mode);
54 56
55extern struct sh_pfc_soc_info r8a7740_pinmux_info; 57extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
56extern struct sh_pfc_soc_info r8a7779_pinmux_info; 58extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
57extern struct sh_pfc_soc_info sh7203_pinmux_info; 59extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
58extern struct sh_pfc_soc_info sh7264_pinmux_info; 60extern const struct sh_pfc_soc_info sh7203_pinmux_info;
59extern struct sh_pfc_soc_info sh7269_pinmux_info; 61extern const struct sh_pfc_soc_info sh7264_pinmux_info;
60extern struct sh_pfc_soc_info sh7372_pinmux_info; 62extern const struct sh_pfc_soc_info sh7269_pinmux_info;
61extern struct sh_pfc_soc_info sh73a0_pinmux_info; 63extern const struct sh_pfc_soc_info sh7372_pinmux_info;
62extern struct sh_pfc_soc_info sh7720_pinmux_info; 64extern const struct sh_pfc_soc_info sh73a0_pinmux_info;
63extern struct sh_pfc_soc_info sh7722_pinmux_info; 65extern const struct sh_pfc_soc_info sh7720_pinmux_info;
64extern struct sh_pfc_soc_info sh7723_pinmux_info; 66extern const struct sh_pfc_soc_info sh7722_pinmux_info;
65extern struct sh_pfc_soc_info sh7724_pinmux_info; 67extern const struct sh_pfc_soc_info sh7723_pinmux_info;
66extern struct sh_pfc_soc_info sh7734_pinmux_info; 68extern const struct sh_pfc_soc_info sh7724_pinmux_info;
67extern struct sh_pfc_soc_info sh7757_pinmux_info; 69extern const struct sh_pfc_soc_info sh7734_pinmux_info;
68extern struct sh_pfc_soc_info sh7785_pinmux_info; 70extern const struct sh_pfc_soc_info sh7757_pinmux_info;
69extern struct sh_pfc_soc_info sh7786_pinmux_info; 71extern const struct sh_pfc_soc_info sh7785_pinmux_info;
70extern struct sh_pfc_soc_info shx3_pinmux_info; 72extern const struct sh_pfc_soc_info sh7786_pinmux_info;
73extern const struct sh_pfc_soc_info shx3_pinmux_info;
71 74
72#endif /* __SH_PFC_CORE_H__ */ 75#endif /* __SH_PFC_CORE_H__ */
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index a535075c8b69..d37efa7dcf90 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -9,8 +9,6 @@
9 * for more details. 9 * for more details.
10 */ 10 */
11 11
12#define pr_fmt(fmt) KBUILD_MODNAME " gpio: " fmt
13
14#include <linux/device.h> 12#include <linux/device.h>
15#include <linux/gpio.h> 13#include <linux/gpio.h>
16#include <linux/init.h> 14#include <linux/init.h>
@@ -21,9 +19,23 @@
21 19
22#include "core.h" 20#include "core.h"
23 21
22struct sh_pfc_gpio_data_reg {
23 const struct pinmux_data_reg *info;
24 unsigned long shadow;
25};
26
27struct sh_pfc_gpio_pin {
28 u8 dbit;
29 u8 dreg;
30};
31
24struct sh_pfc_chip { 32struct sh_pfc_chip {
25 struct sh_pfc *pfc; 33 struct sh_pfc *pfc;
26 struct gpio_chip gpio_chip; 34 struct gpio_chip gpio_chip;
35
36 struct sh_pfc_window *mem;
37 struct sh_pfc_gpio_data_reg *regs;
38 struct sh_pfc_gpio_pin *pins;
27}; 39};
28 40
29static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc) 41static struct sh_pfc_chip *gpio_to_pfc_chip(struct gpio_chip *gc)
@@ -36,143 +48,367 @@ static struct sh_pfc *gpio_to_pfc(struct gpio_chip *gc)
36 return gpio_to_pfc_chip(gc)->pfc; 48 return gpio_to_pfc_chip(gc)->pfc;
37} 49}
38 50
39static int sh_gpio_request(struct gpio_chip *gc, unsigned offset) 51static void gpio_get_data_reg(struct sh_pfc_chip *chip, unsigned int gpio,
52 struct sh_pfc_gpio_data_reg **reg,
53 unsigned int *bit)
40{ 54{
41 return pinctrl_request_gpio(offset); 55 int idx = sh_pfc_get_pin_index(chip->pfc, gpio);
56 struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[idx];
57
58 *reg = &chip->regs[gpio_pin->dreg];
59 *bit = gpio_pin->dbit;
42} 60}
43 61
44static void sh_gpio_free(struct gpio_chip *gc, unsigned offset) 62static unsigned long gpio_read_data_reg(struct sh_pfc_chip *chip,
63 const struct pinmux_data_reg *dreg)
45{ 64{
46 pinctrl_free_gpio(offset); 65 void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt;
66
67 return sh_pfc_read_raw_reg(mem, dreg->reg_width);
47} 68}
48 69
49static void sh_gpio_set_value(struct sh_pfc *pfc, unsigned gpio, int value) 70static void gpio_write_data_reg(struct sh_pfc_chip *chip,
71 const struct pinmux_data_reg *dreg,
72 unsigned long value)
50{ 73{
51 struct pinmux_data_reg *dr = NULL; 74 void __iomem *mem = dreg->reg - chip->mem->phys + chip->mem->virt;
52 int bit = 0;
53 75
54 if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0) 76 sh_pfc_write_raw_reg(mem, dreg->reg_width, value);
55 BUG();
56 else
57 sh_pfc_write_bit(dr, bit, value);
58} 77}
59 78
60static int sh_gpio_get_value(struct sh_pfc *pfc, unsigned gpio) 79static void gpio_setup_data_reg(struct sh_pfc_chip *chip, unsigned gpio)
61{ 80{
62 struct pinmux_data_reg *dr = NULL; 81 struct sh_pfc *pfc = chip->pfc;
63 int bit = 0; 82 struct sh_pfc_gpio_pin *gpio_pin = &chip->pins[gpio];
83 const struct sh_pfc_pin *pin = &pfc->info->pins[gpio];
84 const struct pinmux_data_reg *dreg;
85 unsigned int bit;
86 unsigned int i;
87
88 for (i = 0, dreg = pfc->info->data_regs; dreg->reg; ++i, ++dreg) {
89 for (bit = 0; bit < dreg->reg_width; bit++) {
90 if (dreg->enum_ids[bit] == pin->enum_id) {
91 gpio_pin->dreg = i;
92 gpio_pin->dbit = bit;
93 return;
94 }
95 }
96 }
64 97
65 if (sh_pfc_get_data_reg(pfc, gpio, &dr, &bit) != 0) 98 BUG();
99}
100
101static int gpio_setup_data_regs(struct sh_pfc_chip *chip)
102{
103 struct sh_pfc *pfc = chip->pfc;
104 const struct pinmux_data_reg *dreg;
105 unsigned int i;
106
107 /* Count the number of data registers, allocate memory and initialize
108 * them.
109 */
110 for (i = 0; pfc->info->data_regs[i].reg_width; ++i)
111 ;
112
113 chip->regs = devm_kzalloc(pfc->dev, i * sizeof(*chip->regs),
114 GFP_KERNEL);
115 if (chip->regs == NULL)
116 return -ENOMEM;
117
118 for (i = 0, dreg = pfc->info->data_regs; dreg->reg_width; ++i, ++dreg) {
119 chip->regs[i].info = dreg;
120 chip->regs[i].shadow = gpio_read_data_reg(chip, dreg);
121 }
122
123 for (i = 0; i < pfc->info->nr_pins; i++) {
124 if (pfc->info->pins[i].enum_id == 0)
125 continue;
126
127 gpio_setup_data_reg(chip, i);
128 }
129
130 return 0;
131}
132
133/* -----------------------------------------------------------------------------
134 * Pin GPIOs
135 */
136
137static int gpio_pin_request(struct gpio_chip *gc, unsigned offset)
138{
139 struct sh_pfc *pfc = gpio_to_pfc(gc);
140 int idx = sh_pfc_get_pin_index(pfc, offset);
141
142 if (idx < 0 || pfc->info->pins[idx].enum_id == 0)
66 return -EINVAL; 143 return -EINVAL;
67 144
68 return sh_pfc_read_bit(dr, bit); 145 return pinctrl_request_gpio(offset);
146}
147
148static void gpio_pin_free(struct gpio_chip *gc, unsigned offset)
149{
150 return pinctrl_free_gpio(offset);
151}
152
153static void gpio_pin_set_value(struct sh_pfc_chip *chip, unsigned offset,
154 int value)
155{
156 struct sh_pfc_gpio_data_reg *reg;
157 unsigned long pos;
158 unsigned int bit;
159
160 gpio_get_data_reg(chip, offset, &reg, &bit);
161
162 pos = reg->info->reg_width - (bit + 1);
163
164 if (value)
165 set_bit(pos, &reg->shadow);
166 else
167 clear_bit(pos, &reg->shadow);
168
169 gpio_write_data_reg(chip, reg->info, reg->shadow);
69} 170}
70 171
71static int sh_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 172static int gpio_pin_direction_input(struct gpio_chip *gc, unsigned offset)
72{ 173{
73 return pinctrl_gpio_direction_input(offset); 174 return pinctrl_gpio_direction_input(offset);
74} 175}
75 176
76static int sh_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 177static int gpio_pin_direction_output(struct gpio_chip *gc, unsigned offset,
77 int value) 178 int value)
78{ 179{
79 sh_gpio_set_value(gpio_to_pfc(gc), offset, value); 180 gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
80 181
81 return pinctrl_gpio_direction_output(offset); 182 return pinctrl_gpio_direction_output(offset);
82} 183}
83 184
84static int sh_gpio_get(struct gpio_chip *gc, unsigned offset) 185static int gpio_pin_get(struct gpio_chip *gc, unsigned offset)
85{ 186{
86 return sh_gpio_get_value(gpio_to_pfc(gc), offset); 187 struct sh_pfc_chip *chip = gpio_to_pfc_chip(gc);
188 struct sh_pfc_gpio_data_reg *reg;
189 unsigned long pos;
190 unsigned int bit;
191
192 gpio_get_data_reg(chip, offset, &reg, &bit);
193
194 pos = reg->info->reg_width - (bit + 1);
195
196 return (gpio_read_data_reg(chip, reg->info) >> pos) & 1;
87} 197}
88 198
89static void sh_gpio_set(struct gpio_chip *gc, unsigned offset, int value) 199static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
90{ 200{
91 sh_gpio_set_value(gpio_to_pfc(gc), offset, value); 201 gpio_pin_set_value(gpio_to_pfc_chip(gc), offset, value);
92} 202}
93 203
94static int sh_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 204static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
95{ 205{
96 struct sh_pfc *pfc = gpio_to_pfc(gc); 206 struct sh_pfc *pfc = gpio_to_pfc(gc);
97 pinmux_enum_t enum_id; 207 int i, k;
98 pinmux_enum_t *enum_ids;
99 int i, k, pos;
100
101 pos = 0;
102 enum_id = 0;
103 while (1) {
104 pos = sh_pfc_gpio_to_enum(pfc, offset, pos, &enum_id);
105 if (pos <= 0 || !enum_id)
106 break;
107 208
108 for (i = 0; i < pfc->info->gpio_irq_size; i++) { 209 for (i = 0; i < pfc->info->gpio_irq_size; i++) {
109 enum_ids = pfc->info->gpio_irq[i].enum_ids; 210 unsigned short *gpios = pfc->info->gpio_irq[i].gpios;
110 for (k = 0; enum_ids[k]; k++) { 211
111 if (enum_ids[k] == enum_id) 212 for (k = 0; gpios[k]; k++) {
112 return pfc->info->gpio_irq[i].irq; 213 if (gpios[k] == offset)
113 } 214 return pfc->info->gpio_irq[i].irq;
114 } 215 }
115 } 216 }
116 217
117 return -ENOSYS; 218 return -ENOSYS;
118} 219}
119 220
120static void sh_pfc_gpio_setup(struct sh_pfc_chip *chip) 221static int gpio_pin_setup(struct sh_pfc_chip *chip)
121{ 222{
122 struct sh_pfc *pfc = chip->pfc; 223 struct sh_pfc *pfc = chip->pfc;
123 struct gpio_chip *gc = &chip->gpio_chip; 224 struct gpio_chip *gc = &chip->gpio_chip;
225 int ret;
226
227 chip->pins = devm_kzalloc(pfc->dev, pfc->nr_pins * sizeof(*chip->pins),
228 GFP_KERNEL);
229 if (chip->pins == NULL)
230 return -ENOMEM;
231
232 ret = gpio_setup_data_regs(chip);
233 if (ret < 0)
234 return ret;
235
236 gc->request = gpio_pin_request;
237 gc->free = gpio_pin_free;
238 gc->direction_input = gpio_pin_direction_input;
239 gc->get = gpio_pin_get;
240 gc->direction_output = gpio_pin_direction_output;
241 gc->set = gpio_pin_set;
242 gc->to_irq = gpio_pin_to_irq;
124 243
125 gc->request = sh_gpio_request; 244 gc->label = pfc->info->name;
126 gc->free = sh_gpio_free; 245 gc->dev = pfc->dev;
127 gc->direction_input = sh_gpio_direction_input; 246 gc->owner = THIS_MODULE;
128 gc->get = sh_gpio_get; 247 gc->base = 0;
129 gc->direction_output = sh_gpio_direction_output; 248 gc->ngpio = pfc->nr_pins;
130 gc->set = sh_gpio_set; 249
131 gc->to_irq = sh_gpio_to_irq; 250 return 0;
251}
252
253/* -----------------------------------------------------------------------------
254 * Function GPIOs
255 */
256
257static int gpio_function_request(struct gpio_chip *gc, unsigned offset)
258{
259 static bool __print_once;
260 struct sh_pfc *pfc = gpio_to_pfc(gc);
261 unsigned int mark = pfc->info->func_gpios[offset].enum_id;
262 unsigned long flags;
263 int ret;
264
265 if (!__print_once) {
266 dev_notice(pfc->dev,
267 "Use of GPIO API for function requests is deprecated."
268 " Convert to pinctrl\n");
269 __print_once = true;
270 }
271
272 if (mark == 0)
273 return -EINVAL;
132 274
133 WARN_ON(pfc->info->first_gpio != 0); /* needs testing */ 275 spin_lock_irqsave(&pfc->lock, flags);
276 ret = sh_pfc_config_mux(pfc, mark, PINMUX_TYPE_FUNCTION);
277 spin_unlock_irqrestore(&pfc->lock, flags);
278
279 return ret;
280}
281
282static void gpio_function_free(struct gpio_chip *gc, unsigned offset)
283{
284}
285
286static int gpio_function_setup(struct sh_pfc_chip *chip)
287{
288 struct sh_pfc *pfc = chip->pfc;
289 struct gpio_chip *gc = &chip->gpio_chip;
290
291 gc->request = gpio_function_request;
292 gc->free = gpio_function_free;
134 293
135 gc->label = pfc->info->name; 294 gc->label = pfc->info->name;
136 gc->owner = THIS_MODULE; 295 gc->owner = THIS_MODULE;
137 gc->base = pfc->info->first_gpio; 296 gc->base = pfc->nr_pins;
138 gc->ngpio = (pfc->info->last_gpio - pfc->info->first_gpio) + 1; 297 gc->ngpio = pfc->info->nr_func_gpios;
298
299 return 0;
139} 300}
140 301
141int sh_pfc_register_gpiochip(struct sh_pfc *pfc) 302/* -----------------------------------------------------------------------------
303 * Register/unregister
304 */
305
306static struct sh_pfc_chip *
307sh_pfc_add_gpiochip(struct sh_pfc *pfc, int(*setup)(struct sh_pfc_chip *),
308 struct sh_pfc_window *mem)
142{ 309{
143 struct sh_pfc_chip *chip; 310 struct sh_pfc_chip *chip;
144 int ret; 311 int ret;
145 312
146 chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL); 313 chip = devm_kzalloc(pfc->dev, sizeof(*chip), GFP_KERNEL);
147 if (unlikely(!chip)) 314 if (unlikely(!chip))
148 return -ENOMEM; 315 return ERR_PTR(-ENOMEM);
149 316
317 chip->mem = mem;
150 chip->pfc = pfc; 318 chip->pfc = pfc;
151 319
152 sh_pfc_gpio_setup(chip); 320 ret = setup(chip);
321 if (ret < 0)
322 return ERR_PTR(ret);
153 323
154 ret = gpiochip_add(&chip->gpio_chip); 324 ret = gpiochip_add(&chip->gpio_chip);
155 if (unlikely(ret < 0)) 325 if (unlikely(ret < 0))
156 return ret; 326 return ERR_PTR(ret);
327
328 dev_info(pfc->dev, "%s handling gpio %u -> %u\n",
329 chip->gpio_chip.label, chip->gpio_chip.base,
330 chip->gpio_chip.base + chip->gpio_chip.ngpio - 1);
331
332 return chip;
333}
334
335int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
336{
337 const struct pinmux_range *ranges;
338 struct pinmux_range def_range;
339 struct sh_pfc_chip *chip;
340 unsigned int nr_ranges;
341 unsigned int i;
342 int ret;
343
344 if (pfc->info->data_regs == NULL)
345 return 0;
346
347 /* Find the memory window that contain the GPIO registers. Boards that
348 * register a separate GPIO device will not supply a memory resource
349 * that covers the data registers. In that case don't try to handle
350 * GPIOs.
351 */
352 for (i = 0; i < pfc->num_windows; ++i) {
353 struct sh_pfc_window *window = &pfc->window[i];
354
355 if (pfc->info->data_regs[0].reg >= window->phys &&
356 pfc->info->data_regs[0].reg < window->phys + window->size)
357 break;
358 }
359
360 if (i == pfc->num_windows)
361 return 0;
362
363 /* Register the real GPIOs chip. */
364 chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->window[i]);
365 if (IS_ERR(chip))
366 return PTR_ERR(chip);
157 367
158 pfc->gpio = chip; 368 pfc->gpio = chip;
159 369
160 pr_info("%s handling gpio %d -> %d\n", 370 /* Register the GPIO to pin mappings. */
161 pfc->info->name, pfc->info->first_gpio, 371 if (pfc->info->ranges == NULL) {
162 pfc->info->last_gpio); 372 def_range.begin = 0;
373 def_range.end = pfc->info->nr_pins - 1;
374 ranges = &def_range;
375 nr_ranges = 1;
376 } else {
377 ranges = pfc->info->ranges;
378 nr_ranges = pfc->info->nr_ranges;
379 }
380
381 for (i = 0; i < nr_ranges; ++i) {
382 const struct pinmux_range *range = &ranges[i];
383
384 ret = gpiochip_add_pin_range(&chip->gpio_chip,
385 dev_name(pfc->dev),
386 range->begin, range->begin,
387 range->end - range->begin + 1);
388 if (ret < 0)
389 return ret;
390 }
391
392 /* Register the function GPIOs chip. */
393 if (pfc->info->nr_func_gpios == 0)
394 return 0;
395
396 chip = sh_pfc_add_gpiochip(pfc, gpio_function_setup, NULL);
397 if (IS_ERR(chip))
398 return PTR_ERR(chip);
399
400 pfc->func = chip;
163 401
164 return 0; 402 return 0;
165} 403}
166 404
167int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc) 405int sh_pfc_unregister_gpiochip(struct sh_pfc *pfc)
168{ 406{
169 struct sh_pfc_chip *chip = pfc->gpio; 407 int err;
170 int ret; 408 int ret;
171 409
172 ret = gpiochip_remove(&chip->gpio_chip); 410 ret = gpiochip_remove(&pfc->gpio->gpio_chip);
173 if (unlikely(ret < 0)) 411 err = gpiochip_remove(&pfc->func->gpio_chip);
174 return ret;
175 412
176 pfc->gpio = NULL; 413 return ret < 0 ? ret : err;
177 return 0;
178} 414}
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
new file mode 100644
index 000000000000..bbff5596e922
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -0,0 +1,2587 @@
1/*
2 * Copyright (C) 2012-2013 Renesas Solutions Corp.
3 * Copyright (C) 2013 Magnus Damm
4 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; version 2 of the
9 * License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20#include <linux/io.h>
21#include <linux/kernel.h>
22#include <linux/pinctrl/pinconf-generic.h>
23#include <mach/irqs.h>
24#include <mach/r8a73a4.h>
25
26#include "core.h"
27#include "sh_pfc.h"
28
29#define CPU_ALL_PORT(fn, pfx, sfx) \
30 /* Port0 - Port30 */ \
31 PORT_10(fn, pfx, sfx), \
32 PORT_10(fn, pfx##1, sfx), \
33 PORT_10(fn, pfx##2, sfx), \
34 PORT_1(fn, pfx##30, sfx), \
35 /* Port32 - Port40 */ \
36 PORT_1(fn, pfx##32, sfx), PORT_1(fn, pfx##33, sfx), \
37 PORT_1(fn, pfx##34, sfx), PORT_1(fn, pfx##35, sfx), \
38 PORT_1(fn, pfx##36, sfx), PORT_1(fn, pfx##37, sfx), \
39 PORT_1(fn, pfx##38, sfx), PORT_1(fn, pfx##39, sfx), \
40 PORT_1(fn, pfx##40, sfx), \
41 /* Port64 - Port85 */ \
42 PORT_1(fn, pfx##64, sfx), PORT_1(fn, pfx##65, sfx), \
43 PORT_1(fn, pfx##66, sfx), PORT_1(fn, pfx##67, sfx), \
44 PORT_1(fn, pfx##68, sfx), PORT_1(fn, pfx##69, sfx), \
45 PORT_10(fn, pfx##7, sfx), \
46 PORT_1(fn, pfx##80, sfx), PORT_1(fn, pfx##81, sfx), \
47 PORT_1(fn, pfx##82, sfx), PORT_1(fn, pfx##83, sfx), \
48 PORT_1(fn, pfx##84, sfx), PORT_1(fn, pfx##85, sfx), \
49 /* Port96 - Port126 */ \
50 PORT_1(fn, pfx##96, sfx), PORT_1(fn, pfx##97, sfx), \
51 PORT_1(fn, pfx##98, sfx), PORT_1(fn, pfx##99, sfx), \
52 PORT_10(fn, pfx##10, sfx), \
53 PORT_10(fn, pfx##11, sfx), \
54 PORT_1(fn, pfx##120, sfx), PORT_1(fn, pfx##121, sfx), \
55 PORT_1(fn, pfx##122, sfx), PORT_1(fn, pfx##123, sfx), \
56 PORT_1(fn, pfx##124, sfx), PORT_1(fn, pfx##125, sfx), \
57 PORT_1(fn, pfx##126, sfx), \
58 /* Port128 - Port134 */ \
59 PORT_1(fn, pfx##128, sfx), PORT_1(fn, pfx##129, sfx), \
60 PORT_1(fn, pfx##130, sfx), PORT_1(fn, pfx##131, sfx), \
61 PORT_1(fn, pfx##132, sfx), PORT_1(fn, pfx##133, sfx), \
62 PORT_1(fn, pfx##134, sfx), \
63 /* Port160 - Port178 */ \
64 PORT_10(fn, pfx##16, sfx), \
65 PORT_1(fn, pfx##170, sfx), PORT_1(fn, pfx##171, sfx), \
66 PORT_1(fn, pfx##172, sfx), PORT_1(fn, pfx##173, sfx), \
67 PORT_1(fn, pfx##174, sfx), PORT_1(fn, pfx##175, sfx), \
68 PORT_1(fn, pfx##176, sfx), PORT_1(fn, pfx##177, sfx), \
69 PORT_1(fn, pfx##178, sfx), \
70 /* Port192 - Port222 */ \
71 PORT_1(fn, pfx##192, sfx), PORT_1(fn, pfx##193, sfx), \
72 PORT_1(fn, pfx##194, sfx), PORT_1(fn, pfx##195, sfx), \
73 PORT_1(fn, pfx##196, sfx), PORT_1(fn, pfx##197, sfx), \
74 PORT_1(fn, pfx##198, sfx), PORT_1(fn, pfx##199, sfx), \
75 PORT_10(fn, pfx##20, sfx), \
76 PORT_10(fn, pfx##21, sfx), \
77 PORT_1(fn, pfx##220, sfx), PORT_1(fn, pfx##221, sfx), \
78 PORT_1(fn, pfx##222, sfx), \
79 /* Port224 - Port250 */ \
80 PORT_1(fn, pfx##224, sfx), PORT_1(fn, pfx##225, sfx), \
81 PORT_1(fn, pfx##226, sfx), PORT_1(fn, pfx##227, sfx), \
82 PORT_1(fn, pfx##228, sfx), PORT_1(fn, pfx##229, sfx), \
83 PORT_10(fn, pfx##23, sfx), \
84 PORT_10(fn, pfx##24, sfx), \
85 PORT_1(fn, pfx##250, sfx), \
86 /* Port256 - Port283 */ \
87 PORT_1(fn, pfx##256, sfx), PORT_1(fn, pfx##257, sfx), \
88 PORT_1(fn, pfx##258, sfx), PORT_1(fn, pfx##259, sfx), \
89 PORT_10(fn, pfx##26, sfx), \
90 PORT_10(fn, pfx##27, sfx), \
91 PORT_1(fn, pfx##280, sfx), PORT_1(fn, pfx##281, sfx), \
92 PORT_1(fn, pfx##282, sfx), PORT_1(fn, pfx##283, sfx), \
93 /* Port288 - Port308 */ \
94 PORT_1(fn, pfx##288, sfx), PORT_1(fn, pfx##289, sfx), \
95 PORT_10(fn, pfx##29, sfx), \
96 PORT_1(fn, pfx##300, sfx), PORT_1(fn, pfx##301, sfx), \
97 PORT_1(fn, pfx##302, sfx), PORT_1(fn, pfx##303, sfx), \
98 PORT_1(fn, pfx##304, sfx), PORT_1(fn, pfx##305, sfx), \
99 PORT_1(fn, pfx##306, sfx), PORT_1(fn, pfx##307, sfx), \
100 PORT_1(fn, pfx##308, sfx), \
101 /* Port320 - Port329 */ \
102 PORT_10(fn, pfx##32, sfx)
103
104
105enum {
106 PINMUX_RESERVED = 0,
107
108 /* PORT0_DATA -> PORT329_DATA */
109 PINMUX_DATA_BEGIN,
110 PORT_ALL(DATA),
111 PINMUX_DATA_END,
112
113 /* PORT0_IN -> PORT329_IN */
114 PINMUX_INPUT_BEGIN,
115 PORT_ALL(IN),
116 PINMUX_INPUT_END,
117
118 /* PORT0_OUT -> PORT329_OUT */
119 PINMUX_OUTPUT_BEGIN,
120 PORT_ALL(OUT),
121 PINMUX_OUTPUT_END,
122
123 PINMUX_FUNCTION_BEGIN,
124 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
125 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
126 PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
127 PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
128 PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
129 PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
130 PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
131 PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
132 PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
133 PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
134
135 MSEL1CR_31_0, MSEL1CR_31_1,
136 MSEL1CR_27_0, MSEL1CR_27_1,
137 MSEL1CR_25_0, MSEL1CR_25_1,
138 MSEL1CR_24_0, MSEL1CR_24_1,
139 MSEL1CR_22_0, MSEL1CR_22_1,
140 MSEL1CR_21_0, MSEL1CR_21_1,
141 MSEL1CR_20_0, MSEL1CR_20_1,
142 MSEL1CR_19_0, MSEL1CR_19_1,
143 MSEL1CR_18_0, MSEL1CR_18_1,
144 MSEL1CR_17_0, MSEL1CR_17_1,
145 MSEL1CR_16_0, MSEL1CR_16_1,
146 MSEL1CR_15_0, MSEL1CR_15_1,
147 MSEL1CR_14_0, MSEL1CR_14_1,
148 MSEL1CR_13_0, MSEL1CR_13_1,
149 MSEL1CR_12_0, MSEL1CR_12_1,
150 MSEL1CR_11_0, MSEL1CR_11_1,
151 MSEL1CR_10_0, MSEL1CR_10_1,
152 MSEL1CR_09_0, MSEL1CR_09_1,
153 MSEL1CR_08_0, MSEL1CR_08_1,
154 MSEL1CR_07_0, MSEL1CR_07_1,
155 MSEL1CR_06_0, MSEL1CR_06_1,
156 MSEL1CR_05_0, MSEL1CR_05_1,
157 MSEL1CR_04_0, MSEL1CR_04_1,
158 MSEL1CR_03_0, MSEL1CR_03_1,
159 MSEL1CR_02_0, MSEL1CR_02_1,
160 MSEL1CR_01_0, MSEL1CR_01_1,
161 MSEL1CR_00_0, MSEL1CR_00_1,
162
163 MSEL3CR_31_0, MSEL3CR_31_1,
164 MSEL3CR_28_0, MSEL3CR_28_1,
165 MSEL3CR_27_0, MSEL3CR_27_1,
166 MSEL3CR_26_0, MSEL3CR_26_1,
167 MSEL3CR_23_0, MSEL3CR_23_1,
168 MSEL3CR_22_0, MSEL3CR_22_1,
169 MSEL3CR_21_0, MSEL3CR_21_1,
170 MSEL3CR_20_0, MSEL3CR_20_1,
171 MSEL3CR_19_0, MSEL3CR_19_1,
172 MSEL3CR_18_0, MSEL3CR_18_1,
173 MSEL3CR_17_0, MSEL3CR_17_1,
174 MSEL3CR_16_0, MSEL3CR_16_1,
175 MSEL3CR_15_0, MSEL3CR_15_1,
176 MSEL3CR_12_0, MSEL3CR_12_1,
177 MSEL3CR_11_0, MSEL3CR_11_1,
178 MSEL3CR_10_0, MSEL3CR_10_1,
179 MSEL3CR_09_0, MSEL3CR_09_1,
180 MSEL3CR_06_0, MSEL3CR_06_1,
181 MSEL3CR_03_0, MSEL3CR_03_1,
182 MSEL3CR_01_0, MSEL3CR_01_1,
183 MSEL3CR_00_0, MSEL3CR_00_1,
184
185 MSEL4CR_30_0, MSEL4CR_30_1,
186 MSEL4CR_29_0, MSEL4CR_29_1,
187 MSEL4CR_28_0, MSEL4CR_28_1,
188 MSEL4CR_27_0, MSEL4CR_27_1,
189 MSEL4CR_26_0, MSEL4CR_26_1,
190 MSEL4CR_25_0, MSEL4CR_25_1,
191 MSEL4CR_24_0, MSEL4CR_24_1,
192 MSEL4CR_23_0, MSEL4CR_23_1,
193 MSEL4CR_22_0, MSEL4CR_22_1,
194 MSEL4CR_21_0, MSEL4CR_21_1,
195 MSEL4CR_20_0, MSEL4CR_20_1,
196 MSEL4CR_19_0, MSEL4CR_19_1,
197 MSEL4CR_18_0, MSEL4CR_18_1,
198 MSEL4CR_17_0, MSEL4CR_17_1,
199 MSEL4CR_16_0, MSEL4CR_16_1,
200 MSEL4CR_15_0, MSEL4CR_15_1,
201 MSEL4CR_14_0, MSEL4CR_14_1,
202 MSEL4CR_13_0, MSEL4CR_13_1,
203 MSEL4CR_12_0, MSEL4CR_12_1,
204 MSEL4CR_11_0, MSEL4CR_11_1,
205 MSEL4CR_10_0, MSEL4CR_10_1,
206 MSEL4CR_09_0, MSEL4CR_09_1,
207 MSEL4CR_07_0, MSEL4CR_07_1,
208 MSEL4CR_04_0, MSEL4CR_04_1,
209 MSEL4CR_01_0, MSEL4CR_01_1,
210
211 MSEL5CR_31_0, MSEL5CR_31_1,
212 MSEL5CR_30_0, MSEL5CR_30_1,
213 MSEL5CR_29_0, MSEL5CR_29_1,
214 MSEL5CR_28_0, MSEL5CR_28_1,
215 MSEL5CR_27_0, MSEL5CR_27_1,
216 MSEL5CR_26_0, MSEL5CR_26_1,
217 MSEL5CR_25_0, MSEL5CR_25_1,
218 MSEL5CR_24_0, MSEL5CR_24_1,
219 MSEL5CR_23_0, MSEL5CR_23_1,
220 MSEL5CR_22_0, MSEL5CR_22_1,
221 MSEL5CR_21_0, MSEL5CR_21_1,
222 MSEL5CR_20_0, MSEL5CR_20_1,
223 MSEL5CR_19_0, MSEL5CR_19_1,
224 MSEL5CR_18_0, MSEL5CR_18_1,
225 MSEL5CR_17_0, MSEL5CR_17_1,
226 MSEL5CR_16_0, MSEL5CR_16_1,
227 MSEL5CR_15_0, MSEL5CR_15_1,
228 MSEL5CR_14_0, MSEL5CR_14_1,
229 MSEL5CR_13_0, MSEL5CR_13_1,
230 MSEL5CR_12_0, MSEL5CR_12_1,
231 MSEL5CR_11_0, MSEL5CR_11_1,
232 MSEL5CR_10_0, MSEL5CR_10_1,
233 MSEL5CR_09_0, MSEL5CR_09_1,
234 MSEL5CR_08_0, MSEL5CR_08_1,
235 MSEL5CR_07_0, MSEL5CR_07_1,
236 MSEL5CR_06_0, MSEL5CR_06_1,
237
238 MSEL8CR_16_0, MSEL8CR_16_1,
239 MSEL8CR_01_0, MSEL8CR_01_1,
240 MSEL8CR_00_0, MSEL8CR_00_1,
241
242 PINMUX_FUNCTION_END,
243
244 PINMUX_MARK_BEGIN,
245
246
247#define F1(a) a##_MARK
248#define F2(a) a##_MARK
249#define F3(a) a##_MARK
250#define F4(a) a##_MARK
251#define F5(a) a##_MARK
252#define F6(a) a##_MARK
253#define F7(a) a##_MARK
254#define IRQ(a) IRQ##a##_MARK
255
256 F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
257 F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
258 F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
259 F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
260 F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
261 F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
262 F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
263 F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
264 F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
265 F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
266 F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
267 F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
268 F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
269 F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
270 F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
271 F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
272 F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
273 F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
274 F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
275 F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
276 F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
277 F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
278 F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
279 F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
280 F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
281 F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
282 F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
283 F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
284 F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
285 F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
286 F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
287 F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
288
289 F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
290 F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
291 F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
292 F1(SCIFA1_RTS), F7(CSCIF1_RTS),
293 F1(SCIFA1_CTS), F7(CSCIF1_CTS),
294 F1(SCIFA1_SCK), F7(CSCIF1_SCK),
295 F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
296 F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
297 F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
298 F7(CHSCIF0_HSCK), /* Port40 */
299
300 F1(PDM0_DATA), /* Port64 */
301 F1(PDM1_DATA),
302 F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
303 IRQ(40),
304 F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
305 F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
306 F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
307 F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
308 F7(CHSCIF1_HRTS), /* Port70 */
309 F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
310 F7(CHSCIF1_HCTS),
311 F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
312 F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
313 F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
314 F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
315 F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
316
317 F1(KEYIN0), /* Port96 */
318 F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
319 F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
320 F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
321 F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
322 F2(KEYOUT7), F5(RFANAEN), IRQ(45),
323 F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
324 F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
325 F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
326 F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
327 F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
328 F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
329 F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
330 F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
331 F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
332 F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
333 F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
334 F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
335 F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
336 F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
337 F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
338 F5(SIM0_VOLTSEL1), /* Port130 */
339 F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
340 F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
341 F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
342 IRQ(20), /* Port160 */
343 IRQ(21), IRQ(22), IRQ(23),
344 F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
345 F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
346 F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
347 IRQ(24), IRQ(25), IRQ(26), IRQ(27),
348 F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
349 F1(A9), F2(MMCD1_6), IRQ(32),
350 F1(A8), F2(MMCD1_5), IRQ(33),
351 F1(A7), F2(MMCD1_4), IRQ(34),
352 F1(A6), F2(MMCD1_3), IRQ(35),
353 F1(A5), F2(MMCD1_2), IRQ(36),
354 F1(A4), F2(MMCD1_1), IRQ(37),
355 F1(A3), F2(MMCD1_0), IRQ(38),
356 F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
357 F1(A1),
358 F1(A0), F2(BS),
359 F1(CKO), F2(MMCCLK1),
360 F1(CS0_N), F5(SIM0_GPO1),
361 F1(CS2_N), F5(SIM0_GPO2),
362 F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
363 F1(D15), F5(GIO_OUT15),
364 F1(D14), F5(GIO_OUT14),
365 F1(D13), F5(GIO_OUT13),
366 F1(D12), F5(GIO_OUT12), /* Port210 */
367 F1(D11), F5(WGM_TXP2),
368 F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
369 F1(D9), F2(VIO_D9), F5(GIO_OUT9),
370 F1(D8), F2(VIO_D8), F5(GIO_OUT8),
371 F1(D7), F2(VIO_D7), F5(GIO_OUT7),
372 F1(D6), F2(VIO_D6), F5(GIO_OUT6),
373 F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
374 F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
375 F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
376 F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
377 F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
378 F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
379 F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
380 F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
381 F1(WE0_N), F2(RDWR_227),
382 F1(WE1_N), F5(SIM0_GPO0),
383 F1(PWMO), F2(VIO_CKO1_229),
384 F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
385 F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
386 F2(VIO_CKO3_233), F4(SF_PORT_1_233),
387 F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
388 F1(FSIAISLD), F2(PDM3_DATA_235),
389 F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
390 F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
391 F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
392 F1(FSIBISLD), /* Port240 */
393 F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
394 F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
395 F1(FSIBCK), F3(ISP_SHUTTER0_245),
396 F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
397 F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
398 F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
399 F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
400 F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
401 F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
402 F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
403 F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
404 F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
405 F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
406 F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
407 F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
408 F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
409 F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
410 F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
411 F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
412 F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
413 F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
414 F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
415 F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
416 F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
417 F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
418 F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
419 F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
420 F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
421 F4(MSIOF6_SS1), /* Port300 */
422 F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
423 F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
424 F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
425 F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
426 IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
427 IRQ(55), IRQ(56), IRQ(57),
428 PINMUX_MARK_END,
429};
430
431#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
432#define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
433
434static const pinmux_enum_t pinmux_data[] = {
435 /* specify valid pin states for each pin in GPIO mode */
436 PINMUX_DATA_ALL(),
437
438 /* Port0 */
439 PINMUX_DATA(LCDD0_MARK, PORT0_FN1),
440 PINMUX_DATA(PDM2_CLK_0_MARK, PORT0_FN3),
441 PINMUX_DATA(DU0_DR0_MARK, PORT0_FN7),
442 PINMUX_DATA(IRQ0_MARK, PORT0_FN0),
443
444 /* Port1 */
445 PINMUX_DATA(LCDD1_MARK, PORT1_FN1),
446 PINMUX_DATA(PDM2_DATA_1_MARK, PORT1_FN3, MSEL3CR_12_0),
447 PINMUX_DATA(DU0_DR19_MARK, PORT1_FN7),
448 PINMUX_DATA(IRQ1_MARK, PORT1_FN0),
449
450 /* Port2 */
451 PINMUX_DATA(LCDD2_MARK, PORT2_FN1),
452 PINMUX_DATA(PDM3_CLK_2_MARK, PORT2_FN3),
453 PINMUX_DATA(DU0_DR2_MARK, PORT2_FN7),
454 PINMUX_DATA(IRQ2_MARK, PORT2_FN0),
455
456 /* Port3 */
457 PINMUX_DATA(LCDD3_MARK, PORT3_FN1),
458 PINMUX_DATA(PDM3_DATA_3_MARK, PORT3_FN3, MSEL3CR_12_0),
459 PINMUX_DATA(DU0_DR3_MARK, PORT3_FN7),
460 PINMUX_DATA(IRQ3_MARK, PORT3_FN0),
461
462 /* Port4 */
463 PINMUX_DATA(LCDD4_MARK, PORT4_FN1),
464 PINMUX_DATA(PDM4_CLK_4_MARK, PORT4_FN3),
465 PINMUX_DATA(DU0_DR4_MARK, PORT4_FN7),
466 PINMUX_DATA(IRQ4_MARK, PORT4_FN0),
467
468 /* Port5 */
469 PINMUX_DATA(LCDD5_MARK, PORT5_FN1),
470 PINMUX_DATA(PDM4_DATA_5_MARK, PORT5_FN3, MSEL3CR_12_0),
471 PINMUX_DATA(DU0_DR5_MARK, PORT5_FN7),
472 PINMUX_DATA(IRQ5_MARK, PORT5_FN0),
473
474 /* Port6 */
475 PINMUX_DATA(LCDD6_MARK, PORT6_FN1),
476 PINMUX_DATA(PDM0_OUTCLK_6_MARK, PORT6_FN3),
477 PINMUX_DATA(DU0_DR6_MARK, PORT6_FN7),
478 PINMUX_DATA(IRQ6_MARK, PORT6_FN0),
479
480 /* Port7 */
481 PINMUX_DATA(LCDD7_MARK, PORT7_FN1),
482 PINMUX_DATA(PDM0_OUTDATA_7_MARK, PORT7_FN3),
483 PINMUX_DATA(DU0_DR7_MARK, PORT7_FN7),
484 PINMUX_DATA(IRQ7_MARK, PORT7_FN0),
485
486 /* Port8 */
487 PINMUX_DATA(LCDD8_MARK, PORT8_FN1),
488 PINMUX_DATA(PDM1_OUTCLK_8_MARK, PORT8_FN3),
489 PINMUX_DATA(DU0_DG0_MARK, PORT8_FN7),
490 PINMUX_DATA(IRQ8_MARK, PORT8_FN0),
491
492 /* Port9 */
493 PINMUX_DATA(LCDD9_MARK, PORT9_FN1),
494 PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
495 PINMUX_DATA(DU0_DG1_MARK, PORT9_FN7),
496 PINMUX_DATA(IRQ9_MARK, PORT9_FN0),
497
498 /* Port10 */
499 PINMUX_DATA(LCDD10_MARK, PORT10_FN1),
500 PINMUX_DATA(FSICCK_MARK, PORT10_FN3),
501 PINMUX_DATA(DU0_DG2_MARK, PORT10_FN7),
502 PINMUX_DATA(IRQ10_MARK, PORT10_FN0),
503
504 /* Port11 */
505 PINMUX_DATA(LCDD11_MARK, PORT11_FN1),
506 PINMUX_DATA(FSICISLD_MARK, PORT11_FN3),
507 PINMUX_DATA(DU0_DG3_MARK, PORT11_FN7),
508 PINMUX_DATA(IRQ11_MARK, PORT11_FN0),
509
510 /* Port12 */
511 PINMUX_DATA(LCDD12_MARK, PORT12_FN1),
512 PINMUX_DATA(FSICOMC_MARK, PORT12_FN3),
513 PINMUX_DATA(DU0_DG4_MARK, PORT12_FN7),
514 PINMUX_DATA(IRQ12_MARK, PORT12_FN0),
515
516 /* Port13 */
517 PINMUX_DATA(LCDD13_MARK, PORT13_FN1),
518 PINMUX_DATA(FSICOLR_MARK, PORT13_FN3),
519 PINMUX_DATA(FSICILR_MARK, PORT13_FN4),
520 PINMUX_DATA(DU0_DG5_MARK, PORT13_FN7),
521 PINMUX_DATA(IRQ13_MARK, PORT13_FN0),
522
523 /* Port14 */
524 PINMUX_DATA(LCDD14_MARK, PORT14_FN1),
525 PINMUX_DATA(FSICOBT_MARK, PORT14_FN3),
526 PINMUX_DATA(FSICIBT_MARK, PORT14_FN4),
527 PINMUX_DATA(DU0_DG6_MARK, PORT14_FN7),
528 PINMUX_DATA(IRQ14_MARK, PORT14_FN0),
529
530 /* Port15 */
531 PINMUX_DATA(LCDD15_MARK, PORT15_FN1),
532 PINMUX_DATA(FSICOSLD_MARK, PORT15_FN3),
533 PINMUX_DATA(DU0_DG7_MARK, PORT15_FN7),
534 PINMUX_DATA(IRQ15_MARK, PORT15_FN0),
535
536 /* Port16 */
537 PINMUX_DATA(LCDD16_MARK, PORT16_FN1),
538 PINMUX_DATA(TPU1TO1_MARK, PORT16_FN4),
539 PINMUX_DATA(DU0_DB0_MARK, PORT16_FN7),
540
541 /* Port17 */
542 PINMUX_DATA(LCDD17_MARK, PORT17_FN1),
543 PINMUX_DATA(SF_IRQ_00_MARK, PORT17_FN4),
544 PINMUX_DATA(DU0_DB1_MARK, PORT17_FN7),
545
546 /* Port18 */
547 PINMUX_DATA(LCDD18_MARK, PORT18_FN1),
548 PINMUX_DATA(SF_IRQ_01_MARK, PORT18_FN4),
549 PINMUX_DATA(DU0_DB2_MARK, PORT18_FN7),
550
551 /* Port19 */
552 PINMUX_DATA(LCDD19_MARK, PORT19_FN1),
553 PINMUX_DATA(SCIFB3_RTS_19_MARK, PORT19_FN3),
554 PINMUX_DATA(DU0_DB3_MARK, PORT19_FN7),
555
556 /* Port20 */
557 PINMUX_DATA(LCDD20_MARK, PORT20_FN1),
558 PINMUX_DATA(SCIFB3_CTS_20_MARK, PORT20_FN3, MSEL3CR_09_0),
559 PINMUX_DATA(DU0_DB4_MARK, PORT20_FN7),
560
561 /* Port21 */
562 PINMUX_DATA(LCDD21_MARK, PORT21_FN1),
563 PINMUX_DATA(SCIFB3_TXD_21_MARK, PORT21_FN3, MSEL3CR_09_0),
564 PINMUX_DATA(DU0_DB5_MARK, PORT21_FN7),
565
566 /* Port22 */
567 PINMUX_DATA(LCDD22_MARK, PORT22_FN1),
568 PINMUX_DATA(SCIFB3_RXD_22_MARK, PORT22_FN3, MSEL3CR_09_0),
569 PINMUX_DATA(DU0_DB6_MARK, PORT22_FN7),
570
571 /* Port23 */
572 PINMUX_DATA(LCDD23_MARK, PORT23_FN1),
573 PINMUX_DATA(SCIFB3_SCK_23_MARK, PORT23_FN3),
574 PINMUX_DATA(DU0_DB7_MARK, PORT23_FN7),
575
576 /* Port24 */
577 PINMUX_DATA(LCDHSYN_MARK, PORT24_FN1),
578 PINMUX_DATA(LCDCS_MARK, PORT24_FN2),
579 PINMUX_DATA(SCIFB1_RTS_24_MARK, PORT24_FN3),
580 PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK, PORT24_FN7),
581
582 /* Port25 */
583 PINMUX_DATA(LCDVSYN_MARK, PORT25_FN1),
584 PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
585 PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK, PORT25_FN7),
586
587 /* Port26 */
588 PINMUX_DATA(LCDDCK_MARK, PORT26_FN1),
589 PINMUX_DATA(LCDWR_MARK, PORT26_FN2),
590 PINMUX_DATA(SCIFB1_TXD_26_MARK, PORT26_FN3, MSEL3CR_11_0),
591 PINMUX_DATA(DU0_DOTCLKIN_MARK, PORT26_FN7),
592
593 /* Port27 */
594 PINMUX_DATA(LCDDISP_MARK, PORT27_FN1),
595 PINMUX_DATA(LCDRS_MARK, PORT27_FN2),
596 PINMUX_DATA(SCIFB1_RXD_27_MARK, PORT27_FN3, MSEL3CR_11_0),
597 PINMUX_DATA(DU0_DOTCLKOUT_MARK, PORT27_FN7),
598
599 /* Port28 */
600 PINMUX_DATA(LCDRD_N_MARK, PORT28_FN1),
601 PINMUX_DATA(SCIFB1_SCK_28_MARK, PORT28_FN3),
602 PINMUX_DATA(DU0_DOTCLKOUTB_MARK, PORT28_FN7),
603
604 /* Port29 */
605 PINMUX_DATA(LCDLCLK_MARK, PORT29_FN1),
606 PINMUX_DATA(SF_IRQ_02_MARK, PORT29_FN4),
607 PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK, PORT29_FN7),
608
609 /* Port30 */
610 PINMUX_DATA(LCDDON_MARK, PORT30_FN1),
611 PINMUX_DATA(SF_IRQ_03_MARK, PORT30_FN4),
612 PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK, PORT30_FN7),
613
614 /* Port32 */
615 PINMUX_DATA(SCIFA0_RTS_MARK, PORT32_FN1),
616 PINMUX_DATA(SIM0_DET_MARK, PORT32_FN5),
617 PINMUX_DATA(CSCIF0_RTS_MARK, PORT32_FN7),
618
619 /* Port33 */
620 PINMUX_DATA(SCIFA0_CTS_MARK, PORT33_FN1),
621 PINMUX_DATA(SIM1_DET_MARK, PORT33_FN5),
622 PINMUX_DATA(CSCIF0_CTS_MARK, PORT33_FN7),
623
624 /* Port34 */
625 PINMUX_DATA(SCIFA0_SCK_MARK, PORT34_FN1),
626 PINMUX_DATA(SIM0_PWRON_MARK, PORT34_FN5),
627 PINMUX_DATA(CSCIF0_SCK_MARK, PORT34_FN7),
628
629 /* Port35 */
630 PINMUX_DATA(SCIFA1_RTS_MARK, PORT35_FN1),
631 PINMUX_DATA(CSCIF1_RTS_MARK, PORT35_FN7),
632
633 /* Port36 */
634 PINMUX_DATA(SCIFA1_CTS_MARK, PORT36_FN1),
635 PINMUX_DATA(CSCIF1_CTS_MARK, PORT36_FN7),
636
637 /* Port37 */
638 PINMUX_DATA(SCIFA1_SCK_MARK, PORT37_FN1),
639 PINMUX_DATA(CSCIF1_SCK_MARK, PORT37_FN7),
640
641 /* Port38 */
642 PINMUX_DATA(SCIFB0_RTS_MARK, PORT38_FN1),
643 PINMUX_DATA(TPU0TO1_MARK, PORT38_FN3),
644 PINMUX_DATA(SCIFB3_RTS_38_MARK, PORT38_FN4),
645 PINMUX_DATA(CHSCIF0_HRTS_MARK, PORT38_FN7),
646
647 /* Port39 */
648 PINMUX_DATA(SCIFB0_CTS_MARK, PORT39_FN1),
649 PINMUX_DATA(TPU0TO2_MARK, PORT39_FN3),
650 PINMUX_DATA(SCIFB3_CTS_39_MARK, PORT39_FN4, MSEL3CR_09_1),
651 PINMUX_DATA(CHSCIF0_HCTS_MARK, PORT39_FN7),
652
653 /* Port40 */
654 PINMUX_DATA(SCIFB0_SCK_MARK, PORT40_FN1),
655 PINMUX_DATA(TPU0TO3_MARK, PORT40_FN3),
656 PINMUX_DATA(SCIFB3_SCK_40_MARK, PORT40_FN4),
657 PINMUX_DATA(CHSCIF0_HSCK_MARK, PORT40_FN7),
658
659 /* Port64 */
660 PINMUX_DATA(PDM0_DATA_MARK, PORT64_FN1),
661
662 /* Port65 */
663 PINMUX_DATA(PDM1_DATA_MARK, PORT65_FN1),
664
665 /* Port66 */
666 PINMUX_DATA(HSI_RX_WAKE_MARK, PORT66_FN1),
667 PINMUX_DATA(SCIFB2_CTS_66_MARK, PORT66_FN2, MSEL3CR_10_0),
668 PINMUX_DATA(MSIOF3_SYNC_MARK, PORT66_FN3),
669 PINMUX_DATA(GenIO4_MARK, PORT66_FN5),
670 PINMUX_DATA(IRQ40_MARK, PORT66_FN0),
671
672 /* Port67 */
673 PINMUX_DATA(HSI_RX_READY_MARK, PORT67_FN1),
674 PINMUX_DATA(SCIFB1_TXD_67_MARK, PORT67_FN2, MSEL3CR_11_1),
675 PINMUX_DATA(GIO_OUT3_67_MARK, PORT67_FN5),
676 PINMUX_DATA(CHSCIF1_HTX_MARK, PORT67_FN7),
677
678 /* Port68 */
679 PINMUX_DATA(HSI_RX_FLAG_MARK, PORT68_FN1),
680 PINMUX_DATA(SCIFB2_TXD_68_MARK, PORT68_FN2, MSEL3CR_10_0),
681 PINMUX_DATA(MSIOF3_TXD_MARK, PORT68_FN3),
682 PINMUX_DATA(GIO_OUT4_68_MARK, PORT68_FN5),
683
684 /* Port69 */
685 PINMUX_DATA(HSI_RX_DATA_MARK, PORT69_FN1),
686 PINMUX_DATA(SCIFB2_RXD_69_MARK, PORT69_FN2, MSEL3CR_10_0),
687 PINMUX_DATA(MSIOF3_RXD_MARK, PORT69_FN3),
688 PINMUX_DATA(GIO_OUT5_69_MARK, PORT69_FN5),
689
690 /* Port70 */
691 PINMUX_DATA(HSI_TX_FLAG_MARK, PORT70_FN1),
692 PINMUX_DATA(SCIFB1_RTS_70_MARK, PORT70_FN2),
693 PINMUX_DATA(GIO_OUT1_70_MARK, PORT70_FN5),
694 PINMUX_DATA(HSIC_TSTCLK0_MARK, PORT70_FN6),
695 PINMUX_DATA(CHSCIF1_HRTS_MARK, PORT70_FN7),
696
697 /* Port71 */
698 PINMUX_DATA(HSI_TX_DATA_MARK, PORT71_FN1),
699 PINMUX_DATA(SCIFB1_CTS_71_MARK, PORT71_FN2, MSEL3CR_11_1),
700 PINMUX_DATA(GIO_OUT2_71_MARK, PORT71_FN5),
701 PINMUX_DATA(HSIC_TSTCLK1_MARK, PORT71_FN6),
702 PINMUX_DATA(CHSCIF1_HCTS_MARK, PORT71_FN7),
703
704 /* Port72 */
705 PINMUX_DATA(HSI_TX_WAKE_MARK, PORT72_FN1),
706 PINMUX_DATA(SCIFB1_RXD_72_MARK, PORT72_FN2, MSEL3CR_11_1),
707 PINMUX_DATA(GenIO8_MARK, PORT72_FN5),
708 PINMUX_DATA(CHSCIF1_HRX_MARK, PORT72_FN7),
709
710 /* Port73 */
711 PINMUX_DATA(HSI_TX_READY_MARK, PORT73_FN1),
712 PINMUX_DATA(SCIFB2_RTS_73_MARK, PORT73_FN2),
713 PINMUX_DATA(MSIOF3_SCK_MARK, PORT73_FN3),
714 PINMUX_DATA(GIO_OUT0_73_MARK, PORT73_FN5),
715
716 /* Port74 - Port85 */
717 PINMUX_DATA(IRDA_OUT_MARK, PORT74_FN1),
718 PINMUX_DATA(IRDA_IN_MARK, PORT75_FN1),
719 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT76_FN1),
720 PINMUX_DATA(TPU0TO0_MARK, PORT77_FN1),
721 PINMUX_DATA(DIGRFEN_MARK, PORT78_FN1),
722 PINMUX_DATA(GPS_TIMESTAMP_MARK, PORT79_FN1),
723 PINMUX_DATA(TXP_MARK, PORT80_FN1),
724 PINMUX_DATA(TXP2_MARK, PORT81_FN1),
725 PINMUX_DATA(COEX_0_MARK, PORT82_FN1),
726 PINMUX_DATA(COEX_1_MARK, PORT83_FN1),
727 PINMUX_DATA(IRQ19_MARK, PORT84_FN0),
728 PINMUX_DATA(IRQ18_MARK, PORT85_FN0),
729
730 /* Port96 - Port101 */
731 PINMUX_DATA(KEYIN0_MARK, PORT96_FN1),
732 PINMUX_DATA(KEYIN1_MARK, PORT97_FN1),
733 PINMUX_DATA(KEYIN2_MARK, PORT98_FN1),
734 PINMUX_DATA(KEYIN3_MARK, PORT99_FN1),
735 PINMUX_DATA(KEYIN4_MARK, PORT100_FN1),
736 PINMUX_DATA(KEYIN5_MARK, PORT101_FN1),
737
738 /* Port102 */
739 PINMUX_DATA(KEYIN6_MARK, PORT102_FN1),
740 PINMUX_DATA(IRQ41_MARK, PORT102_FN0),
741
742 /* Port103 */
743 PINMUX_DATA(KEYIN7_MARK, PORT103_FN1),
744 PINMUX_DATA(IRQ42_MARK, PORT103_FN0),
745
746 /* Port104 - Port108 */
747 PINMUX_DATA(KEYOUT0_MARK, PORT104_FN2),
748 PINMUX_DATA(KEYOUT1_MARK, PORT105_FN2),
749 PINMUX_DATA(KEYOUT2_MARK, PORT106_FN2),
750 PINMUX_DATA(KEYOUT3_MARK, PORT107_FN2),
751 PINMUX_DATA(KEYOUT4_MARK, PORT108_FN2),
752
753 /* Port109 */
754 PINMUX_DATA(KEYOUT5_MARK, PORT109_FN2),
755 PINMUX_DATA(IRQ43_MARK, PORT109_FN0),
756
757 /* Port110 */
758 PINMUX_DATA(KEYOUT6_MARK, PORT110_FN2),
759 PINMUX_DATA(IRQ44_MARK, PORT110_FN0),
760
761 /* Port111 */
762 PINMUX_DATA(KEYOUT7_MARK, PORT111_FN2),
763 PINMUX_DATA(RFANAEN_MARK, PORT111_FN5),
764 PINMUX_DATA(IRQ45_MARK, PORT111_FN0),
765
766 /* Port112 */
767 PINMUX_DATA(KEYIN8_MARK, PORT112_FN1),
768 PINMUX_DATA(KEYOUT8_MARK, PORT112_FN2),
769 PINMUX_DATA(SF_IRQ_04_MARK, PORT112_FN4),
770 PINMUX_DATA(IRQ46_MARK, PORT112_FN0),
771
772 /* Port113 */
773 PINMUX_DATA(KEYIN9_MARK, PORT113_FN1),
774 PINMUX_DATA(KEYOUT9_MARK, PORT113_FN2),
775 PINMUX_DATA(SF_IRQ_05_MARK, PORT113_FN4),
776 PINMUX_DATA(IRQ47_MARK, PORT113_FN0),
777
778 /* Port114 */
779 PINMUX_DATA(KEYIN10_MARK, PORT114_FN1),
780 PINMUX_DATA(KEYOUT10_MARK, PORT114_FN2),
781 PINMUX_DATA(SF_IRQ_06_MARK, PORT114_FN4),
782 PINMUX_DATA(IRQ48_MARK, PORT114_FN0),
783
784 /* Port115 */
785 PINMUX_DATA(KEYIN11_MARK, PORT115_FN1),
786 PINMUX_DATA(KEYOUT11_MARK, PORT115_FN2),
787 PINMUX_DATA(SF_IRQ_07_MARK, PORT115_FN4),
788 PINMUX_DATA(IRQ49_MARK, PORT115_FN0),
789
790 /* Port116 */
791 PINMUX_DATA(SCIFA0_TXD_MARK, PORT116_FN1),
792 PINMUX_DATA(CSCIF0_TX_MARK, PORT116_FN7),
793
794 /* Port117 */
795 PINMUX_DATA(SCIFA0_RXD_MARK, PORT117_FN1),
796 PINMUX_DATA(CSCIF0_RX_MARK, PORT117_FN7),
797
798 /* Port118 */
799 PINMUX_DATA(SCIFA1_TXD_MARK, PORT118_FN1),
800 PINMUX_DATA(CSCIF1_TX_MARK, PORT118_FN7),
801
802 /* Port119 */
803 PINMUX_DATA(SCIFA1_RXD_MARK, PORT119_FN1),
804 PINMUX_DATA(CSCIF1_RX_MARK, PORT119_FN7),
805
806 /* Port120 */
807 PINMUX_DATA(SF_PORT_1_120_MARK, PORT120_FN3),
808 PINMUX_DATA(SCIFB3_RXD_120_MARK, PORT120_FN4, MSEL3CR_09_1),
809 PINMUX_DATA(DU0_CDE_MARK, PORT120_FN7),
810
811 /* Port121 */
812 PINMUX_DATA(SF_PORT_0_121_MARK, PORT121_FN3),
813 PINMUX_DATA(SCIFB3_TXD_121_MARK, PORT121_FN4, MSEL3CR_09_1),
814
815 /* Port122 */
816 PINMUX_DATA(SCIFB0_TXD_MARK, PORT122_FN1),
817 PINMUX_DATA(CHSCIF0_HTX_MARK, PORT122_FN7),
818
819 /* Port123 */
820 PINMUX_DATA(SCIFB0_RXD_MARK, PORT123_FN1),
821 PINMUX_DATA(CHSCIF0_HRX_MARK, PORT123_FN7),
822
823 /* Port124 */
824 PINMUX_DATA(ISP_STROBE_124_MARK, PORT124_FN3),
825
826 /* Port125 */
827 PINMUX_DATA(STP_ISD_0_MARK, PORT125_FN1),
828 PINMUX_DATA(PDM4_CLK_125_MARK, PORT125_FN2),
829 PINMUX_DATA(MSIOF2_TXD_MARK, PORT125_FN3),
830 PINMUX_DATA(SIM0_VOLTSEL0_MARK, PORT125_FN5),
831
832 /* Port126 */
833 PINMUX_DATA(TS_SDEN_MARK, PORT126_FN1),
834 PINMUX_DATA(MSIOF7_SYNC_MARK, PORT126_FN2),
835 PINMUX_DATA(STP_ISEN_1_MARK, PORT126_FN3),
836
837 /* Port128 */
838 PINMUX_DATA(STP_ISEN_0_MARK, PORT128_FN1),
839 PINMUX_DATA(PDM1_OUTDATA_128_MARK, PORT128_FN2),
840 PINMUX_DATA(MSIOF2_SYNC_MARK, PORT128_FN3),
841 PINMUX_DATA(SIM1_VOLTSEL1_MARK, PORT128_FN5),
842
843 /* Port129 */
844 PINMUX_DATA(TS_SPSYNC_MARK, PORT129_FN1),
845 PINMUX_DATA(MSIOF7_RXD_MARK, PORT129_FN2),
846 PINMUX_DATA(STP_ISSYNC_1_MARK, PORT129_FN3),
847
848 /* Port130 */
849 PINMUX_DATA(STP_ISSYNC_0_MARK, PORT130_FN1),
850 PINMUX_DATA(PDM4_DATA_130_MARK, PORT130_FN2, MSEL3CR_12_1),
851 PINMUX_DATA(MSIOF2_RXD_MARK, PORT130_FN3),
852 PINMUX_DATA(SIM0_VOLTSEL1_MARK, PORT130_FN5),
853
854 /* Port131 */
855 PINMUX_DATA(STP_OPWM_0_MARK, PORT131_FN1),
856 PINMUX_DATA(SIM1_PWRON_MARK, PORT131_FN5),
857
858 /* Port132 */
859 PINMUX_DATA(TS_SCK_MARK, PORT132_FN1),
860 PINMUX_DATA(MSIOF7_SCK_MARK, PORT132_FN2),
861 PINMUX_DATA(STP_ISCLK_1_MARK, PORT132_FN3),
862
863 /* Port133 */
864 PINMUX_DATA(STP_ISCLK_0_MARK, PORT133_FN1),
865 PINMUX_DATA(PDM1_OUTCLK_133_MARK, PORT133_FN2),
866 PINMUX_DATA(MSIOF2_SCK_MARK, PORT133_FN3),
867 PINMUX_DATA(SIM1_VOLTSEL0_MARK, PORT133_FN5),
868
869 /* Port134 */
870 PINMUX_DATA(TS_SDAT_MARK, PORT134_FN1),
871 PINMUX_DATA(MSIOF7_TXD_MARK, PORT134_FN2),
872 PINMUX_DATA(STP_ISD_1_MARK, PORT134_FN3),
873
874 /* Port160 - Port178 */
875 PINMUX_DATA(IRQ20_MARK, PORT160_FN0),
876 PINMUX_DATA(IRQ21_MARK, PORT161_FN0),
877 PINMUX_DATA(IRQ22_MARK, PORT162_FN0),
878 PINMUX_DATA(IRQ23_MARK, PORT163_FN0),
879 PINMUX_DATA(MMCD0_0_MARK, PORT164_FN1),
880 PINMUX_DATA(MMCD0_1_MARK, PORT165_FN1),
881 PINMUX_DATA(MMCD0_2_MARK, PORT166_FN1),
882 PINMUX_DATA(MMCD0_3_MARK, PORT167_FN1),
883 PINMUX_DATA(MMCD0_4_MARK, PORT168_FN1),
884 PINMUX_DATA(MMCD0_5_MARK, PORT169_FN1),
885 PINMUX_DATA(MMCD0_6_MARK, PORT170_FN1),
886 PINMUX_DATA(MMCD0_7_MARK, PORT171_FN1),
887 PINMUX_DATA(MMCCMD0_MARK, PORT172_FN1),
888 PINMUX_DATA(MMCCLK0_MARK, PORT173_FN1),
889 PINMUX_DATA(MMCRST_MARK, PORT174_FN1),
890 PINMUX_DATA(IRQ24_MARK, PORT175_FN0),
891 PINMUX_DATA(IRQ25_MARK, PORT176_FN0),
892 PINMUX_DATA(IRQ26_MARK, PORT177_FN0),
893 PINMUX_DATA(IRQ27_MARK, PORT178_FN0),
894
895 /* Port192 - Port200 FN1 */
896 PINMUX_DATA(A10_MARK, PORT192_FN1),
897 PINMUX_DATA(A9_MARK, PORT193_FN1),
898 PINMUX_DATA(A8_MARK, PORT194_FN1),
899 PINMUX_DATA(A7_MARK, PORT195_FN1),
900 PINMUX_DATA(A6_MARK, PORT196_FN1),
901 PINMUX_DATA(A5_MARK, PORT197_FN1),
902 PINMUX_DATA(A4_MARK, PORT198_FN1),
903 PINMUX_DATA(A3_MARK, PORT199_FN1),
904 PINMUX_DATA(A2_MARK, PORT200_FN1),
905
906 /* Port192 - Port200 FN2 */
907 PINMUX_DATA(MMCD1_7_MARK, PORT192_FN2),
908 PINMUX_DATA(MMCD1_6_MARK, PORT193_FN2),
909 PINMUX_DATA(MMCD1_5_MARK, PORT194_FN2),
910 PINMUX_DATA(MMCD1_4_MARK, PORT195_FN2),
911 PINMUX_DATA(MMCD1_3_MARK, PORT196_FN2),
912 PINMUX_DATA(MMCD1_2_MARK, PORT197_FN2),
913 PINMUX_DATA(MMCD1_1_MARK, PORT198_FN2),
914 PINMUX_DATA(MMCD1_0_MARK, PORT199_FN2),
915 PINMUX_DATA(MMCCMD1_MARK, PORT200_FN2),
916
917 /* Port192 - Port200 IRQ */
918 PINMUX_DATA(IRQ31_MARK, PORT192_FN0),
919 PINMUX_DATA(IRQ32_MARK, PORT193_FN0),
920 PINMUX_DATA(IRQ33_MARK, PORT194_FN0),
921 PINMUX_DATA(IRQ34_MARK, PORT195_FN0),
922 PINMUX_DATA(IRQ35_MARK, PORT196_FN0),
923 PINMUX_DATA(IRQ36_MARK, PORT197_FN0),
924 PINMUX_DATA(IRQ37_MARK, PORT198_FN0),
925 PINMUX_DATA(IRQ38_MARK, PORT199_FN0),
926 PINMUX_DATA(IRQ39_MARK, PORT200_FN0),
927
928 /* Port201 */
929 PINMUX_DATA(A1_MARK, PORT201_FN1),
930
931 /* Port202 */
932 PINMUX_DATA(A0_MARK, PORT202_FN1),
933 PINMUX_DATA(BS_MARK, PORT202_FN2),
934
935 /* Port203 */
936 PINMUX_DATA(CKO_MARK, PORT203_FN1),
937 PINMUX_DATA(MMCCLK1_MARK, PORT203_FN2),
938
939 /* Port204 */
940 PINMUX_DATA(CS0_N_MARK, PORT204_FN1),
941 PINMUX_DATA(SIM0_GPO1_MARK, PORT204_FN5),
942
943 /* Port205 */
944 PINMUX_DATA(CS2_N_MARK, PORT205_FN1),
945 PINMUX_DATA(SIM0_GPO2_MARK, PORT205_FN5),
946
947 /* Port206 */
948 PINMUX_DATA(CS4_N_MARK, PORT206_FN1),
949 PINMUX_DATA(VIO_VD_MARK, PORT206_FN2),
950 PINMUX_DATA(SIM1_GPO0_MARK, PORT206_FN5),
951
952 /* Port207 - Port212 FN1 */
953 PINMUX_DATA(D15_MARK, PORT207_FN1),
954 PINMUX_DATA(D14_MARK, PORT208_FN1),
955 PINMUX_DATA(D13_MARK, PORT209_FN1),
956 PINMUX_DATA(D12_MARK, PORT210_FN1),
957 PINMUX_DATA(D11_MARK, PORT211_FN1),
958 PINMUX_DATA(D10_MARK, PORT212_FN1),
959
960 /* Port207 - Port212 FN5 */
961 PINMUX_DATA(GIO_OUT15_MARK, PORT207_FN5),
962 PINMUX_DATA(GIO_OUT14_MARK, PORT208_FN5),
963 PINMUX_DATA(GIO_OUT13_MARK, PORT209_FN5),
964 PINMUX_DATA(GIO_OUT12_MARK, PORT210_FN5),
965 PINMUX_DATA(WGM_TXP2_MARK, PORT211_FN5),
966 PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK, PORT212_FN5),
967
968 /* Port213 - Port222 FN1 */
969 PINMUX_DATA(D9_MARK, PORT213_FN1),
970 PINMUX_DATA(D8_MARK, PORT214_FN1),
971 PINMUX_DATA(D7_MARK, PORT215_FN1),
972 PINMUX_DATA(D6_MARK, PORT216_FN1),
973 PINMUX_DATA(D5_MARK, PORT217_FN1),
974 PINMUX_DATA(D4_MARK, PORT218_FN1),
975 PINMUX_DATA(D3_MARK, PORT219_FN1),
976 PINMUX_DATA(D2_MARK, PORT220_FN1),
977 PINMUX_DATA(D1_MARK, PORT221_FN1),
978 PINMUX_DATA(D0_MARK, PORT222_FN1),
979
980 /* Port213 - Port222 FN2 */
981 PINMUX_DATA(VIO_D9_MARK, PORT213_FN2),
982 PINMUX_DATA(VIO_D8_MARK, PORT214_FN2),
983 PINMUX_DATA(VIO_D7_MARK, PORT215_FN2),
984 PINMUX_DATA(VIO_D6_MARK, PORT216_FN2),
985 PINMUX_DATA(VIO_D5_MARK, PORT217_FN2),
986 PINMUX_DATA(VIO_D4_MARK, PORT218_FN2),
987 PINMUX_DATA(VIO_D3_MARK, PORT219_FN2),
988 PINMUX_DATA(VIO_D2_MARK, PORT220_FN2),
989 PINMUX_DATA(VIO_D1_MARK, PORT221_FN2),
990 PINMUX_DATA(VIO_D0_MARK, PORT222_FN2),
991
992 /* Port213 - Port222 FN5 */
993 PINMUX_DATA(GIO_OUT9_MARK, PORT213_FN5),
994 PINMUX_DATA(GIO_OUT8_MARK, PORT214_FN5),
995 PINMUX_DATA(GIO_OUT7_MARK, PORT215_FN5),
996 PINMUX_DATA(GIO_OUT6_MARK, PORT216_FN5),
997 PINMUX_DATA(GIO_OUT5_217_MARK, PORT217_FN5),
998 PINMUX_DATA(GIO_OUT4_218_MARK, PORT218_FN5),
999 PINMUX_DATA(GIO_OUT3_219_MARK, PORT219_FN5),
1000 PINMUX_DATA(GIO_OUT2_220_MARK, PORT220_FN5),
1001 PINMUX_DATA(GIO_OUT1_221_MARK, PORT221_FN5),
1002 PINMUX_DATA(GIO_OUT0_222_MARK, PORT222_FN5),
1003
1004 /* Port224 */
1005 PINMUX_DATA(RDWR_224_MARK, PORT224_FN1),
1006 PINMUX_DATA(VIO_HD_MARK, PORT224_FN2),
1007 PINMUX_DATA(SIM1_GPO2_MARK, PORT224_FN5),
1008
1009 /* Port225 */
1010 PINMUX_DATA(RD_N_MARK, PORT225_FN1),
1011
1012 /* Port226 */
1013 PINMUX_DATA(WAIT_N_MARK, PORT226_FN1),
1014 PINMUX_DATA(VIO_CLK_MARK, PORT226_FN2),
1015 PINMUX_DATA(SIM1_GPO1_MARK, PORT226_FN5),
1016
1017 /* Port227 */
1018 PINMUX_DATA(WE0_N_MARK, PORT227_FN1),
1019 PINMUX_DATA(RDWR_227_MARK, PORT227_FN2),
1020
1021 /* Port228 */
1022 PINMUX_DATA(WE1_N_MARK, PORT228_FN1),
1023 PINMUX_DATA(SIM0_GPO0_MARK, PORT228_FN5),
1024
1025 /* Port229 */
1026 PINMUX_DATA(PWMO_MARK, PORT229_FN1),
1027 PINMUX_DATA(VIO_CKO1_229_MARK, PORT229_FN2),
1028
1029 /* Port230 */
1030 PINMUX_DATA(SLIM_CLK_MARK, PORT230_FN1),
1031 PINMUX_DATA(VIO_CKO4_230_MARK, PORT230_FN2),
1032
1033 /* Port231 */
1034 PINMUX_DATA(SLIM_DATA_MARK, PORT231_FN1),
1035 PINMUX_DATA(VIO_CKO5_231_MARK, PORT231_FN2),
1036
1037 /* Port232 */
1038 PINMUX_DATA(VIO_CKO2_232_MARK, PORT232_FN2),
1039 PINMUX_DATA(SF_PORT_0_232_MARK, PORT232_FN4),
1040
1041 /* Port233 */
1042 PINMUX_DATA(VIO_CKO3_233_MARK, PORT233_FN2),
1043 PINMUX_DATA(SF_PORT_1_233_MARK, PORT233_FN4),
1044
1045 /* Port234 */
1046 PINMUX_DATA(FSIACK_MARK, PORT234_FN1),
1047 PINMUX_DATA(PDM3_CLK_234_MARK, PORT234_FN2),
1048 PINMUX_DATA(ISP_IRIS1_234_MARK, PORT234_FN3),
1049
1050 /* Port235 */
1051 PINMUX_DATA(FSIAISLD_MARK, PORT235_FN1),
1052 PINMUX_DATA(PDM3_DATA_235_MARK, PORT235_FN2, MSEL3CR_12_1),
1053
1054 /* Port236 */
1055 PINMUX_DATA(FSIAOMC_MARK, PORT236_FN1),
1056 PINMUX_DATA(PDM0_OUTCLK_236_MARK, PORT236_FN2),
1057 PINMUX_DATA(ISP_IRIS0_236_MARK, PORT236_FN3),
1058
1059 /* Port237 */
1060 PINMUX_DATA(FSIAOLR_MARK, PORT237_FN1),
1061 PINMUX_DATA(FSIAILR_MARK, PORT237_FN2),
1062
1063 /* Port238 */
1064 PINMUX_DATA(FSIAOBT_MARK, PORT238_FN1),
1065 PINMUX_DATA(FSIAIBT_MARK, PORT238_FN2),
1066
1067 /* Port239 */
1068 PINMUX_DATA(FSIAOSLD_MARK, PORT239_FN1),
1069 PINMUX_DATA(PDM0_OUTDATA_239_MARK, PORT239_FN2),
1070
1071 /* Port240 */
1072 PINMUX_DATA(FSIBISLD_MARK, PORT240_FN1),
1073
1074 /* Port241 */
1075 PINMUX_DATA(FSIBOLR_MARK, PORT241_FN1),
1076 PINMUX_DATA(FSIBILR_MARK, PORT241_FN2),
1077
1078 /* Port242 */
1079 PINMUX_DATA(FSIBOMC_MARK, PORT242_FN1),
1080 PINMUX_DATA(ISP_SHUTTER1_242_MARK, PORT242_FN3),
1081
1082 /* Port243 */
1083 PINMUX_DATA(FSIBOBT_MARK, PORT243_FN1),
1084 PINMUX_DATA(FSIBIBT_MARK, PORT243_FN2),
1085
1086 /* Port244 */
1087 PINMUX_DATA(FSIBOSLD_MARK, PORT244_FN1),
1088 PINMUX_DATA(FSIASPDIF_MARK, PORT244_FN2),
1089
1090 /* Port245 */
1091 PINMUX_DATA(FSIBCK_MARK, PORT245_FN1),
1092 PINMUX_DATA(ISP_SHUTTER0_245_MARK, PORT245_FN3),
1093
1094 /* Port246 - Port250 FN1 */
1095 PINMUX_DATA(ISP_IRIS1_246_MARK, PORT246_FN1),
1096 PINMUX_DATA(ISP_IRIS0_247_MARK, PORT247_FN1),
1097 PINMUX_DATA(ISP_SHUTTER1_248_MARK, PORT248_FN1),
1098 PINMUX_DATA(ISP_SHUTTER0_249_MARK, PORT249_FN1),
1099 PINMUX_DATA(ISP_STROBE_250_MARK, PORT250_FN1),
1100
1101 /* Port256 - Port258 */
1102 PINMUX_DATA(MSIOF0_SYNC_MARK, PORT256_FN1),
1103 PINMUX_DATA(MSIOF0_RXD_MARK, PORT257_FN1),
1104 PINMUX_DATA(MSIOF0_SCK_MARK, PORT258_FN1),
1105
1106 /* Port259 */
1107 PINMUX_DATA(MSIOF0_SS2_MARK, PORT259_FN1),
1108 PINMUX_DATA(VIO_CKO3_259_MARK, PORT259_FN3),
1109
1110 /* Port260 */
1111 PINMUX_DATA(MSIOF0_TXD_MARK, PORT260_FN1),
1112
1113 /* Port261 */
1114 PINMUX_DATA(SCIFB1_SCK_261_MARK, PORT261_FN2),
1115 PINMUX_DATA(CHSCIF1_HSCK_MARK, PORT261_FN7),
1116
1117 /* Port262 */
1118 PINMUX_DATA(SCIFB2_SCK_262_MARK, PORT262_FN2),
1119
1120 /* Port263 - Port266 FN1 */
1121 PINMUX_DATA(MSIOF1_SS2_MARK, PORT263_FN1),
1122 PINMUX_DATA(MSIOF1_TXD_MARK, PORT264_FN1),
1123 PINMUX_DATA(MSIOF1_RXD_MARK, PORT265_FN1),
1124 PINMUX_DATA(MSIOF1_SS1_MARK, PORT266_FN1),
1125
1126 /* Port263 - Port266 FN4 */
1127 PINMUX_DATA(MSIOF5_SS2_MARK, PORT263_FN4),
1128 PINMUX_DATA(MSIOF5_TXD_MARK, PORT264_FN4),
1129 PINMUX_DATA(MSIOF5_RXD_MARK, PORT265_FN4),
1130 PINMUX_DATA(MSIOF5_SS1_MARK, PORT266_FN4),
1131
1132 /* Port267 */
1133 PINMUX_DATA(MSIOF0_SS1_MARK, PORT267_FN1),
1134
1135 /* Port268 */
1136 PINMUX_DATA(MSIOF1_SCK_MARK, PORT268_FN1),
1137 PINMUX_DATA(MSIOF5_SCK_MARK, PORT268_FN4),
1138
1139 /* Port269 */
1140 PINMUX_DATA(MSIOF1_SYNC_MARK, PORT269_FN1),
1141 PINMUX_DATA(MSIOF5_SYNC_MARK, PORT269_FN4),
1142
1143 /* Port270 - Port273 FN1 */
1144 PINMUX_DATA(MSIOF2_SS1_MARK, PORT270_FN1),
1145 PINMUX_DATA(MSIOF2_SS2_MARK, PORT271_FN1),
1146 PINMUX_DATA(MSIOF3_SS2_MARK, PORT272_FN1),
1147 PINMUX_DATA(MSIOF3_SS1_MARK, PORT273_FN1),
1148
1149 /* Port270 - Port273 FN3 */
1150 PINMUX_DATA(VIO_CKO5_270_MARK, PORT270_FN3),
1151 PINMUX_DATA(VIO_CKO2_271_MARK, PORT271_FN3),
1152 PINMUX_DATA(VIO_CKO1_272_MARK, PORT272_FN3),
1153 PINMUX_DATA(VIO_CKO4_273_MARK, PORT273_FN3),
1154
1155 /* Port274 */
1156 PINMUX_DATA(MSIOF4_SS2_MARK, PORT274_FN1),
1157 PINMUX_DATA(TPU1TO0_MARK, PORT274_FN4),
1158
1159 /* Port275 - Port280 */
1160 PINMUX_DATA(IC_DP_MARK, PORT275_FN1),
1161 PINMUX_DATA(SIM0_RST_MARK, PORT276_FN1),
1162 PINMUX_DATA(IC_DM_MARK, PORT277_FN1),
1163 PINMUX_DATA(SIM0_BSICOMP_MARK, PORT278_FN1),
1164 PINMUX_DATA(SIM0_CLK_MARK, PORT279_FN1),
1165 PINMUX_DATA(SIM0_IO_MARK, PORT280_FN1),
1166
1167 /* Port281 */
1168 PINMUX_DATA(SIM1_IO_MARK, PORT281_FN1),
1169 PINMUX_DATA(PDM2_DATA_281_MARK, PORT281_FN2, MSEL3CR_12_1),
1170
1171 /* Port282 */
1172 PINMUX_DATA(SIM1_CLK_MARK, PORT282_FN1),
1173 PINMUX_DATA(PDM2_CLK_282_MARK, PORT282_FN2),
1174
1175 /* Port283 */
1176 PINMUX_DATA(SIM1_RST_MARK, PORT283_FN1),
1177
1178 /* Port289 */
1179 PINMUX_DATA(SDHID1_0_MARK, PORT289_FN1),
1180 PINMUX_DATA(STMDATA0_2_MARK, PORT289_FN3),
1181
1182 /* Port290 */
1183 PINMUX_DATA(SDHID1_1_MARK, PORT290_FN1),
1184 PINMUX_DATA(STMDATA1_2_MARK, PORT290_FN3),
1185 PINMUX_DATA(IRQ51_MARK, PORT290_FN0),
1186
1187 /* Port291 - Port294 FN1 */
1188 PINMUX_DATA(SDHID1_2_MARK, PORT291_FN1),
1189 PINMUX_DATA(SDHID1_3_MARK, PORT292_FN1),
1190 PINMUX_DATA(SDHICLK1_MARK, PORT293_FN1),
1191 PINMUX_DATA(SDHICMD1_MARK, PORT294_FN1),
1192
1193 /* Port291 - Port294 FN3 */
1194 PINMUX_DATA(STMDATA2_2_MARK, PORT291_FN3),
1195 PINMUX_DATA(STMDATA3_2_MARK, PORT292_FN3),
1196 PINMUX_DATA(STMCLK_2_MARK, PORT293_FN3),
1197 PINMUX_DATA(STMSIDI_2_MARK, PORT294_FN3),
1198
1199 /* Port295 */
1200 PINMUX_DATA(SDHID2_0_MARK, PORT295_FN1),
1201 PINMUX_DATA(MSIOF4_TXD_MARK, PORT295_FN2),
1202 PINMUX_DATA(SCIFB2_TXD_295_MARK, PORT295_FN3, MSEL3CR_10_1),
1203 PINMUX_DATA(MSIOF6_TXD_MARK, PORT295_FN4),
1204
1205 /* Port296 */
1206 PINMUX_DATA(SDHID2_1_MARK, PORT296_FN1),
1207 PINMUX_DATA(MSIOF6_SS2_MARK, PORT296_FN4),
1208 PINMUX_DATA(IRQ52_MARK, PORT296_FN0),
1209
1210 /* Port297 - Port300 FN1 */
1211 PINMUX_DATA(SDHID2_2_MARK, PORT297_FN1),
1212 PINMUX_DATA(SDHID2_3_MARK, PORT298_FN1),
1213 PINMUX_DATA(SDHICLK2_MARK, PORT299_FN1),
1214 PINMUX_DATA(SDHICMD2_MARK, PORT300_FN1),
1215
1216 /* Port297 - Port300 FN2 */
1217 PINMUX_DATA(MSIOF4_RXD_MARK, PORT297_FN2),
1218 PINMUX_DATA(MSIOF4_SYNC_MARK, PORT298_FN2),
1219 PINMUX_DATA(MSIOF4_SCK_MARK, PORT299_FN2),
1220 PINMUX_DATA(MSIOF4_SS1_MARK, PORT300_FN2),
1221
1222 /* Port297 - Port300 FN3 */
1223 PINMUX_DATA(SCIFB2_RXD_297_MARK, PORT297_FN3, MSEL3CR_10_1),
1224 PINMUX_DATA(SCIFB2_CTS_298_MARK, PORT298_FN3, MSEL3CR_10_1),
1225 PINMUX_DATA(SCIFB2_SCK_299_MARK, PORT299_FN3),
1226 PINMUX_DATA(SCIFB2_RTS_300_MARK, PORT300_FN3),
1227
1228 /* Port297 - Port300 FN4 */
1229 PINMUX_DATA(MSIOF6_RXD_MARK, PORT297_FN4),
1230 PINMUX_DATA(MSIOF6_SYNC_MARK, PORT298_FN4),
1231 PINMUX_DATA(MSIOF6_SCK_MARK, PORT299_FN4),
1232 PINMUX_DATA(MSIOF6_SS1_MARK, PORT300_FN4),
1233
1234 /* Port301 */
1235 PINMUX_DATA(SDHICD0_MARK, PORT301_FN1),
1236 PINMUX_DATA(IRQ50_MARK, PORT301_FN0),
1237
1238 /* Port302 - Port306 FN1 */
1239 PINMUX_DATA(SDHID0_0_MARK, PORT302_FN1),
1240 PINMUX_DATA(SDHID0_1_MARK, PORT303_FN1),
1241 PINMUX_DATA(SDHID0_2_MARK, PORT304_FN1),
1242 PINMUX_DATA(SDHID0_3_MARK, PORT305_FN1),
1243 PINMUX_DATA(SDHICMD0_MARK, PORT306_FN1),
1244
1245 /* Port302 - Port306 FN3 */
1246 PINMUX_DATA(STMDATA0_1_MARK, PORT302_FN3),
1247 PINMUX_DATA(STMDATA1_1_MARK, PORT303_FN3),
1248 PINMUX_DATA(STMDATA2_1_MARK, PORT304_FN3),
1249 PINMUX_DATA(STMDATA3_1_MARK, PORT305_FN3),
1250 PINMUX_DATA(STMSIDI_1_MARK, PORT306_FN3),
1251
1252 /* Port307 */
1253 PINMUX_DATA(SDHIWP0_MARK, PORT307_FN1),
1254
1255 /* Port308 */
1256 PINMUX_DATA(SDHICLK0_MARK, PORT308_FN1),
1257 PINMUX_DATA(STMCLK_1_MARK, PORT308_FN3),
1258
1259 /* Port320 - Port329 */
1260 PINMUX_DATA(IRQ16_MARK, PORT320_FN0),
1261 PINMUX_DATA(IRQ17_MARK, PORT321_FN0),
1262 PINMUX_DATA(IRQ28_MARK, PORT322_FN0),
1263 PINMUX_DATA(IRQ29_MARK, PORT323_FN0),
1264 PINMUX_DATA(IRQ30_MARK, PORT324_FN0),
1265 PINMUX_DATA(IRQ53_MARK, PORT325_FN0),
1266 PINMUX_DATA(IRQ54_MARK, PORT326_FN0),
1267 PINMUX_DATA(IRQ55_MARK, PORT327_FN0),
1268 PINMUX_DATA(IRQ56_MARK, PORT328_FN0),
1269 PINMUX_DATA(IRQ57_MARK, PORT329_FN0),
1270};
1271
1272#define R8A73A4_PIN(pin, cfgs) \
1273 { \
1274 .name = __stringify(PORT##pin), \
1275 .enum_id = PORT##pin##_DATA, \
1276 .configs = cfgs, \
1277 }
1278
1279#define __O (SH_PFC_PIN_CFG_OUTPUT)
1280#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1281#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1282
1283#define R8A73A4_PIN_IO_PU_PD(pin) R8A73A4_PIN(pin, __IO | __PUD)
1284#define R8A73A4_PIN_O(pin) R8A73A4_PIN(pin, __O)
1285
1286static struct sh_pfc_pin pinmux_pins[] = {
1287 R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
1288 R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
1289 R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
1290 R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
1291 R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
1292 R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
1293 R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
1294 R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
1295 R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
1296 R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
1297 R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
1298 R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
1299 R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
1300 R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
1301 R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
1302 R8A73A4_PIN_IO_PU_PD(30),
1303 R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
1304 R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
1305 R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
1306 R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
1307 R8A73A4_PIN_IO_PU_PD(40),
1308 R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
1309 R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
1310 R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
1311 R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
1312 R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
1313 R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
1314 R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
1315 R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
1316 R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
1317 R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
1318 R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
1319 R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
1320 R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
1321 R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
1322 R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
1323 R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
1324 R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
1325 R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
1326 R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
1327 R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
1328 R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
1329 R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
1330 R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
1331 R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
1332 R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
1333 R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
1334 R8A73A4_PIN_IO_PU_PD(126),
1335 R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
1336 R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
1337 R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
1338 R8A73A4_PIN_IO_PU_PD(134),
1339 R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
1340 R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
1341 R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
1342 R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
1343 R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
1344 R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
1345 R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
1346 R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
1347 R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
1348 R8A73A4_PIN_IO_PU_PD(178),
1349 R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
1350 R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
1351 R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
1352 R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
1353 R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
1354 R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
1355 R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
1356 R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
1357 R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
1358 R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
1359 R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
1360 R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
1361 R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
1362 R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
1363 R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
1364 R8A73A4_PIN_IO_PU_PD(222),
1365 R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
1366 R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
1367 R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
1368 R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
1369 R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
1370 R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
1371 R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
1372 R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
1373 R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
1374 R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
1375 R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
1376 R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
1377 R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
1378 R8A73A4_PIN_IO_PU_PD(250),
1379 R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
1380 R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
1381 R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
1382 R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
1383 R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
1384 R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
1385 R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
1386 R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
1387 R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
1388 R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
1389 R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
1390 R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
1391 R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
1392 R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
1393 R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
1394 R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
1395 R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
1396 R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
1397 R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
1398 R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
1399 R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
1400 R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
1401 R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
1402 R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
1403 R8A73A4_PIN_IO_PU_PD(308),
1404 R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
1405 R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
1406 R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
1407 R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
1408 R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
1409};
1410
1411static const struct pinmux_range pinmux_ranges[] = {
1412 {.begin = 0, .end = 30,},
1413 {.begin = 32, .end = 40,},
1414 {.begin = 64, .end = 85,},
1415 {.begin = 96, .end = 126,},
1416 {.begin = 128, .end = 134,},
1417 {.begin = 160, .end = 178,},
1418 {.begin = 192, .end = 222,},
1419 {.begin = 224, .end = 250,},
1420 {.begin = 256, .end = 283,},
1421 {.begin = 288, .end = 308,},
1422 {.begin = 320, .end = 329,},
1423};
1424
1425/* - IRQC ------------------------------------------------------------------- */
1426#define IRQC_PINS_MUX(pin, irq_mark) \
1427static const unsigned int irqc_irq##irq_mark##_pins[] = { \
1428 pin, \
1429}; \
1430static const unsigned int irqc_irq##irq_mark##_mux[] = { \
1431 IRQ##irq_mark##_MARK, \
1432}
1433IRQC_PINS_MUX(0, 0);
1434IRQC_PINS_MUX(1, 1);
1435IRQC_PINS_MUX(2, 2);
1436IRQC_PINS_MUX(3, 3);
1437IRQC_PINS_MUX(4, 4);
1438IRQC_PINS_MUX(5, 5);
1439IRQC_PINS_MUX(6, 6);
1440IRQC_PINS_MUX(7, 7);
1441IRQC_PINS_MUX(8, 8);
1442IRQC_PINS_MUX(9, 9);
1443IRQC_PINS_MUX(10, 10);
1444IRQC_PINS_MUX(11, 11);
1445IRQC_PINS_MUX(12, 12);
1446IRQC_PINS_MUX(13, 13);
1447IRQC_PINS_MUX(14, 14);
1448IRQC_PINS_MUX(15, 15);
1449IRQC_PINS_MUX(66, 40);
1450IRQC_PINS_MUX(84, 19);
1451IRQC_PINS_MUX(85, 18);
1452IRQC_PINS_MUX(102, 41);
1453IRQC_PINS_MUX(103, 42);
1454IRQC_PINS_MUX(109, 43);
1455IRQC_PINS_MUX(110, 44);
1456IRQC_PINS_MUX(111, 45);
1457IRQC_PINS_MUX(112, 46);
1458IRQC_PINS_MUX(113, 47);
1459IRQC_PINS_MUX(114, 48);
1460IRQC_PINS_MUX(115, 49);
1461IRQC_PINS_MUX(160, 20);
1462IRQC_PINS_MUX(161, 21);
1463IRQC_PINS_MUX(162, 22);
1464IRQC_PINS_MUX(163, 23);
1465IRQC_PINS_MUX(175, 24);
1466IRQC_PINS_MUX(176, 25);
1467IRQC_PINS_MUX(177, 26);
1468IRQC_PINS_MUX(178, 27);
1469IRQC_PINS_MUX(192, 31);
1470IRQC_PINS_MUX(193, 32);
1471IRQC_PINS_MUX(194, 33);
1472IRQC_PINS_MUX(195, 34);
1473IRQC_PINS_MUX(196, 35);
1474IRQC_PINS_MUX(197, 36);
1475IRQC_PINS_MUX(198, 37);
1476IRQC_PINS_MUX(199, 38);
1477IRQC_PINS_MUX(200, 39);
1478IRQC_PINS_MUX(290, 51);
1479IRQC_PINS_MUX(296, 52);
1480IRQC_PINS_MUX(301, 50);
1481IRQC_PINS_MUX(320, 16);
1482IRQC_PINS_MUX(321, 17);
1483IRQC_PINS_MUX(322, 28);
1484IRQC_PINS_MUX(323, 29);
1485IRQC_PINS_MUX(324, 30);
1486IRQC_PINS_MUX(325, 53);
1487IRQC_PINS_MUX(326, 54);
1488IRQC_PINS_MUX(327, 55);
1489IRQC_PINS_MUX(328, 56);
1490IRQC_PINS_MUX(329, 57);
1491/* - SCIFA0 ----------------------------------------------------------------- */
1492static const unsigned int scifa0_data_pins[] = {
1493 /* SCIFA0_RXD, SCIFA0_TXD */
1494 117, 116,
1495};
1496static const unsigned int scifa0_data_mux[] = {
1497 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1498};
1499static const unsigned int scifa0_clk_pins[] = {
1500 /* SCIFA0_SCK */
1501 34,
1502};
1503static const unsigned int scifa0_clk_mux[] = {
1504 SCIFA0_SCK_MARK,
1505};
1506static const unsigned int scifa0_ctrl_pins[] = {
1507 /* SCIFA0_RTS, SCIFA0_CTS */
1508 32, 33,
1509};
1510static const unsigned int scifa0_ctrl_mux[] = {
1511 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1512};
1513/* - SCIFA1 ----------------------------------------------------------------- */
1514static const unsigned int scifa1_data_pins[] = {
1515 /* SCIFA1_RXD, SCIFA1_TXD */
1516 119, 118,
1517};
1518static const unsigned int scifa1_data_mux[] = {
1519 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1520};
1521static const unsigned int scifa1_clk_pins[] = {
1522 /* SCIFA1_SCK */
1523 37,
1524};
1525static const unsigned int scifa1_clk_mux[] = {
1526 SCIFA1_SCK_MARK,
1527};
1528static const unsigned int scifa1_ctrl_pins[] = {
1529 /* SCIFA1_RTS, SCIFA1_CTS */
1530 35, 36,
1531};
1532static const unsigned int scifa1_ctrl_mux[] = {
1533 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1534};
1535/* - SCIFB0 ----------------------------------------------------------------- */
1536static const unsigned int scifb0_data_pins[] = {
1537 /* SCIFB0_RXD, SCIFB0_TXD */
1538 123, 122,
1539};
1540static const unsigned int scifb0_data_mux[] = {
1541 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
1542};
1543static const unsigned int scifb0_clk_pins[] = {
1544 /* SCIFB0_SCK */
1545 40,
1546};
1547static const unsigned int scifb0_clk_mux[] = {
1548 SCIFB0_SCK_MARK,
1549};
1550static const unsigned int scifb0_ctrl_pins[] = {
1551 /* SCIFB0_RTS, SCIFB0_CTS */
1552 38, 39,
1553};
1554static const unsigned int scifb0_ctrl_mux[] = {
1555 SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
1556};
1557/* - SCIFB1 ----------------------------------------------------------------- */
1558static const unsigned int scifb1_data_pins[] = {
1559 /* SCIFB1_RXD, SCIFB1_TXD */
1560 27, 26,
1561};
1562static const unsigned int scifb1_data_mux[] = {
1563 SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
1564};
1565static const unsigned int scifb1_clk_pins[] = {
1566 /* SCIFB1_SCK */
1567 28,
1568};
1569static const unsigned int scifb1_clk_mux[] = {
1570 SCIFB1_SCK_28_MARK,
1571};
1572static const unsigned int scifb1_ctrl_pins[] = {
1573 /* SCIFB1_RTS, SCIFB1_CTS */
1574 24, 25,
1575};
1576static const unsigned int scifb1_ctrl_mux[] = {
1577 SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
1578};
1579static const unsigned int scifb1_data_b_pins[] = {
1580 /* SCIFB1_RXD, SCIFB1_TXD */
1581 72, 67,
1582};
1583static const unsigned int scifb1_data_b_mux[] = {
1584 SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
1585};
1586static const unsigned int scifb1_clk_b_pins[] = {
1587 /* SCIFB1_SCK */
1588 261,
1589};
1590static const unsigned int scifb1_clk_b_mux[] = {
1591 SCIFB1_SCK_261_MARK,
1592};
1593static const unsigned int scifb1_ctrl_b_pins[] = {
1594 /* SCIFB1_RTS, SCIFB1_CTS */
1595 70, 71,
1596};
1597static const unsigned int scifb1_ctrl_b_mux[] = {
1598 SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
1599};
1600/* - SCIFB2 ----------------------------------------------------------------- */
1601static const unsigned int scifb2_data_pins[] = {
1602 /* SCIFB2_RXD, SCIFB2_TXD */
1603 69, 68,
1604};
1605static const unsigned int scifb2_data_mux[] = {
1606 SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
1607};
1608static const unsigned int scifb2_clk_pins[] = {
1609 /* SCIFB2_SCK */
1610 262,
1611};
1612static const unsigned int scifb2_clk_mux[] = {
1613 SCIFB2_SCK_262_MARK,
1614};
1615static const unsigned int scifb2_ctrl_pins[] = {
1616 /* SCIFB2_RTS, SCIFB2_CTS */
1617 73, 66,
1618};
1619static const unsigned int scifb2_ctrl_mux[] = {
1620 SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
1621};
1622static const unsigned int scifb2_data_b_pins[] = {
1623 /* SCIFB2_RXD, SCIFB2_TXD */
1624 297, 295,
1625};
1626static const unsigned int scifb2_data_b_mux[] = {
1627 SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
1628};
1629static const unsigned int scifb2_clk_b_pins[] = {
1630 /* SCIFB2_SCK */
1631 299,
1632};
1633static const unsigned int scifb2_clk_b_mux[] = {
1634 SCIFB2_SCK_299_MARK,
1635};
1636static const unsigned int scifb2_ctrl_b_pins[] = {
1637 /* SCIFB2_RTS, SCIFB2_CTS */
1638 300, 298,
1639};
1640static const unsigned int scifb2_ctrl_b_mux[] = {
1641 SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
1642};
1643/* - SCIFB3 ----------------------------------------------------------------- */
1644static const unsigned int scifb3_data_pins[] = {
1645 /* SCIFB3_RXD, SCIFB3_TXD */
1646 22, 21,
1647};
1648static const unsigned int scifb3_data_mux[] = {
1649 SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
1650};
1651static const unsigned int scifb3_clk_pins[] = {
1652 /* SCIFB3_SCK */
1653 23,
1654};
1655static const unsigned int scifb3_clk_mux[] = {
1656 SCIFB3_SCK_23_MARK,
1657};
1658static const unsigned int scifb3_ctrl_pins[] = {
1659 /* SCIFB3_RTS, SCIFB3_CTS */
1660 19, 20,
1661};
1662static const unsigned int scifb3_ctrl_mux[] = {
1663 SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
1664};
1665static const unsigned int scifb3_data_b_pins[] = {
1666 /* SCIFB3_RXD, SCIFB3_TXD */
1667 120, 121,
1668};
1669static const unsigned int scifb3_data_b_mux[] = {
1670 SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
1671};
1672static const unsigned int scifb3_clk_b_pins[] = {
1673 /* SCIFB3_SCK */
1674 40,
1675};
1676static const unsigned int scifb3_clk_b_mux[] = {
1677 SCIFB3_SCK_40_MARK,
1678};
1679static const unsigned int scifb3_ctrl_b_pins[] = {
1680 /* SCIFB3_RTS, SCIFB3_CTS */
1681 38, 39,
1682};
1683static const unsigned int scifb3_ctrl_b_mux[] = {
1684 SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
1685};
1686
1687static const struct sh_pfc_pin_group pinmux_groups[] = {
1688 SH_PFC_PIN_GROUP(irqc_irq0),
1689 SH_PFC_PIN_GROUP(irqc_irq1),
1690 SH_PFC_PIN_GROUP(irqc_irq2),
1691 SH_PFC_PIN_GROUP(irqc_irq3),
1692 SH_PFC_PIN_GROUP(irqc_irq4),
1693 SH_PFC_PIN_GROUP(irqc_irq5),
1694 SH_PFC_PIN_GROUP(irqc_irq6),
1695 SH_PFC_PIN_GROUP(irqc_irq7),
1696 SH_PFC_PIN_GROUP(irqc_irq8),
1697 SH_PFC_PIN_GROUP(irqc_irq9),
1698 SH_PFC_PIN_GROUP(irqc_irq10),
1699 SH_PFC_PIN_GROUP(irqc_irq11),
1700 SH_PFC_PIN_GROUP(irqc_irq12),
1701 SH_PFC_PIN_GROUP(irqc_irq13),
1702 SH_PFC_PIN_GROUP(irqc_irq14),
1703 SH_PFC_PIN_GROUP(irqc_irq15),
1704 SH_PFC_PIN_GROUP(irqc_irq16),
1705 SH_PFC_PIN_GROUP(irqc_irq17),
1706 SH_PFC_PIN_GROUP(irqc_irq18),
1707 SH_PFC_PIN_GROUP(irqc_irq19),
1708 SH_PFC_PIN_GROUP(irqc_irq20),
1709 SH_PFC_PIN_GROUP(irqc_irq21),
1710 SH_PFC_PIN_GROUP(irqc_irq22),
1711 SH_PFC_PIN_GROUP(irqc_irq23),
1712 SH_PFC_PIN_GROUP(irqc_irq24),
1713 SH_PFC_PIN_GROUP(irqc_irq25),
1714 SH_PFC_PIN_GROUP(irqc_irq26),
1715 SH_PFC_PIN_GROUP(irqc_irq27),
1716 SH_PFC_PIN_GROUP(irqc_irq28),
1717 SH_PFC_PIN_GROUP(irqc_irq29),
1718 SH_PFC_PIN_GROUP(irqc_irq30),
1719 SH_PFC_PIN_GROUP(irqc_irq31),
1720 SH_PFC_PIN_GROUP(irqc_irq32),
1721 SH_PFC_PIN_GROUP(irqc_irq33),
1722 SH_PFC_PIN_GROUP(irqc_irq34),
1723 SH_PFC_PIN_GROUP(irqc_irq35),
1724 SH_PFC_PIN_GROUP(irqc_irq36),
1725 SH_PFC_PIN_GROUP(irqc_irq37),
1726 SH_PFC_PIN_GROUP(irqc_irq38),
1727 SH_PFC_PIN_GROUP(irqc_irq39),
1728 SH_PFC_PIN_GROUP(irqc_irq40),
1729 SH_PFC_PIN_GROUP(irqc_irq41),
1730 SH_PFC_PIN_GROUP(irqc_irq42),
1731 SH_PFC_PIN_GROUP(irqc_irq43),
1732 SH_PFC_PIN_GROUP(irqc_irq44),
1733 SH_PFC_PIN_GROUP(irqc_irq45),
1734 SH_PFC_PIN_GROUP(irqc_irq46),
1735 SH_PFC_PIN_GROUP(irqc_irq47),
1736 SH_PFC_PIN_GROUP(irqc_irq48),
1737 SH_PFC_PIN_GROUP(irqc_irq49),
1738 SH_PFC_PIN_GROUP(irqc_irq50),
1739 SH_PFC_PIN_GROUP(irqc_irq51),
1740 SH_PFC_PIN_GROUP(irqc_irq52),
1741 SH_PFC_PIN_GROUP(irqc_irq53),
1742 SH_PFC_PIN_GROUP(irqc_irq54),
1743 SH_PFC_PIN_GROUP(irqc_irq55),
1744 SH_PFC_PIN_GROUP(irqc_irq56),
1745 SH_PFC_PIN_GROUP(irqc_irq57),
1746 SH_PFC_PIN_GROUP(scifa0_data),
1747 SH_PFC_PIN_GROUP(scifa0_clk),
1748 SH_PFC_PIN_GROUP(scifa0_ctrl),
1749 SH_PFC_PIN_GROUP(scifa1_data),
1750 SH_PFC_PIN_GROUP(scifa1_clk),
1751 SH_PFC_PIN_GROUP(scifa1_ctrl),
1752 SH_PFC_PIN_GROUP(scifb0_data),
1753 SH_PFC_PIN_GROUP(scifb0_clk),
1754 SH_PFC_PIN_GROUP(scifb0_ctrl),
1755 SH_PFC_PIN_GROUP(scifb1_data),
1756 SH_PFC_PIN_GROUP(scifb1_clk),
1757 SH_PFC_PIN_GROUP(scifb1_ctrl),
1758 SH_PFC_PIN_GROUP(scifb1_data_b),
1759 SH_PFC_PIN_GROUP(scifb1_clk_b),
1760 SH_PFC_PIN_GROUP(scifb1_ctrl_b),
1761 SH_PFC_PIN_GROUP(scifb2_data),
1762 SH_PFC_PIN_GROUP(scifb2_clk),
1763 SH_PFC_PIN_GROUP(scifb2_ctrl),
1764 SH_PFC_PIN_GROUP(scifb2_data_b),
1765 SH_PFC_PIN_GROUP(scifb2_clk_b),
1766 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
1767 SH_PFC_PIN_GROUP(scifb3_data),
1768 SH_PFC_PIN_GROUP(scifb3_clk),
1769 SH_PFC_PIN_GROUP(scifb3_ctrl),
1770 SH_PFC_PIN_GROUP(scifb3_data_b),
1771 SH_PFC_PIN_GROUP(scifb3_clk_b),
1772 SH_PFC_PIN_GROUP(scifb3_ctrl_b),
1773};
1774
1775static const char * const irqc_groups[] = {
1776 "irqc_irq0",
1777 "irqc_irq1",
1778 "irqc_irq2",
1779 "irqc_irq3",
1780 "irqc_irq4",
1781 "irqc_irq5",
1782 "irqc_irq6",
1783 "irqc_irq7",
1784 "irqc_irq8",
1785 "irqc_irq9",
1786 "irqc_irq10",
1787 "irqc_irq11",
1788 "irqc_irq12",
1789 "irqc_irq13",
1790 "irqc_irq14",
1791 "irqc_irq15",
1792 "irqc_irq16",
1793 "irqc_irq17",
1794 "irqc_irq18",
1795 "irqc_irq19",
1796 "irqc_irq20",
1797 "irqc_irq21",
1798 "irqc_irq22",
1799 "irqc_irq23",
1800 "irqc_irq24",
1801 "irqc_irq25",
1802 "irqc_irq26",
1803 "irqc_irq27",
1804 "irqc_irq28",
1805 "irqc_irq29",
1806 "irqc_irq30",
1807 "irqc_irq31",
1808 "irqc_irq32",
1809 "irqc_irq33",
1810 "irqc_irq34",
1811 "irqc_irq35",
1812 "irqc_irq36",
1813 "irqc_irq37",
1814 "irqc_irq38",
1815 "irqc_irq39",
1816 "irqc_irq40",
1817 "irqc_irq41",
1818 "irqc_irq42",
1819 "irqc_irq43",
1820 "irqc_irq44",
1821 "irqc_irq45",
1822 "irqc_irq46",
1823 "irqc_irq47",
1824 "irqc_irq48",
1825 "irqc_irq49",
1826 "irqc_irq50",
1827 "irqc_irq51",
1828 "irqc_irq52",
1829 "irqc_irq53",
1830 "irqc_irq54",
1831 "irqc_irq55",
1832 "irqc_irq56",
1833 "irqc_irq57",
1834};
1835
1836static const char * const scifa0_groups[] = {
1837 "scifa0_data",
1838 "scifa0_clk",
1839 "scifa0_ctrl",
1840};
1841
1842static const char * const scifa1_groups[] = {
1843 "scifa1_data",
1844 "scifa1_clk",
1845 "scifa1_ctrl",
1846};
1847
1848static const char * const scifb0_groups[] = {
1849 "scifb0_data",
1850 "scifb0_clk",
1851 "scifb0_ctrl",
1852};
1853
1854static const char * const scifb1_groups[] = {
1855 "scifb1_data",
1856 "scifb1_clk",
1857 "scifb1_ctrl",
1858 "scifb1_data_b",
1859 "scifb1_clk_b",
1860 "scifb1_ctrl_b",
1861};
1862
1863static const char * const scifb2_groups[] = {
1864 "scifb2_data",
1865 "scifb2_clk",
1866 "scifb2_ctrl",
1867 "scifb2_data_b",
1868 "scifb2_clk_b",
1869 "scifb2_ctrl_b",
1870};
1871
1872static const char * const scifb3_groups[] = {
1873 "scifb3_data",
1874 "scifb3_clk",
1875 "scifb3_ctrl",
1876 "scifb3_data_b",
1877 "scifb3_clk_b",
1878 "scifb3_ctrl_b",
1879};
1880
1881static const struct sh_pfc_function pinmux_functions[] = {
1882 SH_PFC_FUNCTION(irqc),
1883 SH_PFC_FUNCTION(scifa0),
1884 SH_PFC_FUNCTION(scifa1),
1885 SH_PFC_FUNCTION(scifb0),
1886 SH_PFC_FUNCTION(scifb1),
1887 SH_PFC_FUNCTION(scifb2),
1888 SH_PFC_FUNCTION(scifb3),
1889};
1890
1891#undef PORTCR
1892#define PORTCR(nr, reg) \
1893 { \
1894 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
1895 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
1896 PORT##nr##_FN0, PORT##nr##_FN1, \
1897 PORT##nr##_FN2, PORT##nr##_FN3, \
1898 PORT##nr##_FN4, PORT##nr##_FN5, \
1899 PORT##nr##_FN6, PORT##nr##_FN7 } \
1900 }
1901
1902static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1903 PORTCR(0, 0xe6050000),
1904 PORTCR(1, 0xe6050001),
1905 PORTCR(2, 0xe6050002),
1906 PORTCR(3, 0xe6050003),
1907 PORTCR(4, 0xe6050004),
1908 PORTCR(5, 0xe6050005),
1909 PORTCR(6, 0xe6050006),
1910 PORTCR(7, 0xe6050007),
1911 PORTCR(8, 0xe6050008),
1912 PORTCR(9, 0xe6050009),
1913 PORTCR(10, 0xe605000A),
1914 PORTCR(11, 0xe605000B),
1915 PORTCR(12, 0xe605000C),
1916 PORTCR(13, 0xe605000D),
1917 PORTCR(14, 0xe605000E),
1918 PORTCR(15, 0xe605000F),
1919 PORTCR(16, 0xe6050010),
1920 PORTCR(17, 0xe6050011),
1921 PORTCR(18, 0xe6050012),
1922 PORTCR(19, 0xe6050013),
1923 PORTCR(20, 0xe6050014),
1924 PORTCR(21, 0xe6050015),
1925 PORTCR(22, 0xe6050016),
1926 PORTCR(23, 0xe6050017),
1927 PORTCR(24, 0xe6050018),
1928 PORTCR(25, 0xe6050019),
1929 PORTCR(26, 0xe605001A),
1930 PORTCR(27, 0xe605001B),
1931 PORTCR(28, 0xe605001C),
1932 PORTCR(29, 0xe605001D),
1933 PORTCR(30, 0xe605001E),
1934 PORTCR(32, 0xe6051020),
1935 PORTCR(33, 0xe6051021),
1936 PORTCR(34, 0xe6051022),
1937 PORTCR(35, 0xe6051023),
1938 PORTCR(36, 0xe6051024),
1939 PORTCR(37, 0xe6051025),
1940 PORTCR(38, 0xe6051026),
1941 PORTCR(39, 0xe6051027),
1942 PORTCR(40, 0xe6051028),
1943 PORTCR(64, 0xe6050040),
1944 PORTCR(65, 0xe6050041),
1945 PORTCR(66, 0xe6050042),
1946 PORTCR(67, 0xe6050043),
1947 PORTCR(68, 0xe6050044),
1948 PORTCR(69, 0xe6050045),
1949 PORTCR(70, 0xe6050046),
1950 PORTCR(71, 0xe6050047),
1951 PORTCR(72, 0xe6050048),
1952 PORTCR(73, 0xe6050049),
1953 PORTCR(74, 0xe605004A),
1954 PORTCR(75, 0xe605004B),
1955 PORTCR(76, 0xe605004C),
1956 PORTCR(77, 0xe605004D),
1957 PORTCR(78, 0xe605004E),
1958 PORTCR(79, 0xe605004F),
1959 PORTCR(80, 0xe6050050),
1960 PORTCR(81, 0xe6050051),
1961 PORTCR(82, 0xe6050052),
1962 PORTCR(83, 0xe6050053),
1963 PORTCR(84, 0xe6050054),
1964 PORTCR(85, 0xe6050055),
1965 PORTCR(96, 0xe6051060),
1966 PORTCR(97, 0xe6051061),
1967 PORTCR(98, 0xe6051062),
1968 PORTCR(99, 0xe6051063),
1969 PORTCR(100, 0xe6051064),
1970 PORTCR(101, 0xe6051065),
1971 PORTCR(102, 0xe6051066),
1972 PORTCR(103, 0xe6051067),
1973 PORTCR(104, 0xe6051068),
1974 PORTCR(105, 0xe6051069),
1975 PORTCR(106, 0xe605106A),
1976 PORTCR(107, 0xe605106B),
1977 PORTCR(108, 0xe605106C),
1978 PORTCR(109, 0xe605106D),
1979 PORTCR(110, 0xe605106E),
1980 PORTCR(111, 0xe605106F),
1981 PORTCR(112, 0xe6051070),
1982 PORTCR(113, 0xe6051071),
1983 PORTCR(114, 0xe6051072),
1984 PORTCR(115, 0xe6051073),
1985 PORTCR(116, 0xe6051074),
1986 PORTCR(117, 0xe6051075),
1987 PORTCR(118, 0xe6051076),
1988 PORTCR(119, 0xe6051077),
1989 PORTCR(120, 0xe6051078),
1990 PORTCR(121, 0xe6051079),
1991 PORTCR(122, 0xe605107A),
1992 PORTCR(123, 0xe605107B),
1993 PORTCR(124, 0xe605107C),
1994 PORTCR(125, 0xe605107D),
1995 PORTCR(126, 0xe605107E),
1996 PORTCR(128, 0xe6051080),
1997 PORTCR(129, 0xe6051081),
1998 PORTCR(130, 0xe6051082),
1999 PORTCR(131, 0xe6051083),
2000 PORTCR(132, 0xe6051084),
2001 PORTCR(133, 0xe6051085),
2002 PORTCR(134, 0xe6051086),
2003 PORTCR(160, 0xe60520A0),
2004 PORTCR(161, 0xe60520A1),
2005 PORTCR(162, 0xe60520A2),
2006 PORTCR(163, 0xe60520A3),
2007 PORTCR(164, 0xe60520A4),
2008 PORTCR(165, 0xe60520A5),
2009 PORTCR(166, 0xe60520A6),
2010 PORTCR(167, 0xe60520A7),
2011 PORTCR(168, 0xe60520A8),
2012 PORTCR(169, 0xe60520A9),
2013 PORTCR(170, 0xe60520AA),
2014 PORTCR(171, 0xe60520AB),
2015 PORTCR(172, 0xe60520AC),
2016 PORTCR(173, 0xe60520AD),
2017 PORTCR(174, 0xe60520AE),
2018 PORTCR(175, 0xe60520AF),
2019 PORTCR(176, 0xe60520B0),
2020 PORTCR(177, 0xe60520B1),
2021 PORTCR(178, 0xe60520B2),
2022 PORTCR(192, 0xe60520C0),
2023 PORTCR(193, 0xe60520C1),
2024 PORTCR(194, 0xe60520C2),
2025 PORTCR(195, 0xe60520C3),
2026 PORTCR(196, 0xe60520C4),
2027 PORTCR(197, 0xe60520C5),
2028 PORTCR(198, 0xe60520C6),
2029 PORTCR(199, 0xe60520C7),
2030 PORTCR(200, 0xe60520C8),
2031 PORTCR(201, 0xe60520C9),
2032 PORTCR(202, 0xe60520CA),
2033 PORTCR(203, 0xe60520CB),
2034 PORTCR(204, 0xe60520CC),
2035 PORTCR(205, 0xe60520CD),
2036 PORTCR(206, 0xe60520CE),
2037 PORTCR(207, 0xe60520CF),
2038 PORTCR(208, 0xe60520D0),
2039 PORTCR(209, 0xe60520D1),
2040 PORTCR(210, 0xe60520D2),
2041 PORTCR(211, 0xe60520D3),
2042 PORTCR(212, 0xe60520D4),
2043 PORTCR(213, 0xe60520D5),
2044 PORTCR(214, 0xe60520D6),
2045 PORTCR(215, 0xe60520D7),
2046 PORTCR(216, 0xe60520D8),
2047 PORTCR(217, 0xe60520D9),
2048 PORTCR(218, 0xe60520DA),
2049 PORTCR(219, 0xe60520DB),
2050 PORTCR(220, 0xe60520DC),
2051 PORTCR(221, 0xe60520DD),
2052 PORTCR(222, 0xe60520DE),
2053 PORTCR(224, 0xe60520E0),
2054 PORTCR(225, 0xe60520E1),
2055 PORTCR(226, 0xe60520E2),
2056 PORTCR(227, 0xe60520E3),
2057 PORTCR(228, 0xe60520E4),
2058 PORTCR(229, 0xe60520E5),
2059 PORTCR(230, 0xe60520e6),
2060 PORTCR(231, 0xe60520E7),
2061 PORTCR(232, 0xe60520E8),
2062 PORTCR(233, 0xe60520E9),
2063 PORTCR(234, 0xe60520EA),
2064 PORTCR(235, 0xe60520EB),
2065 PORTCR(236, 0xe60520EC),
2066 PORTCR(237, 0xe60520ED),
2067 PORTCR(238, 0xe60520EE),
2068 PORTCR(239, 0xe60520EF),
2069 PORTCR(240, 0xe60520F0),
2070 PORTCR(241, 0xe60520F1),
2071 PORTCR(242, 0xe60520F2),
2072 PORTCR(243, 0xe60520F3),
2073 PORTCR(244, 0xe60520F4),
2074 PORTCR(245, 0xe60520F5),
2075 PORTCR(246, 0xe60520F6),
2076 PORTCR(247, 0xe60520F7),
2077 PORTCR(248, 0xe60520F8),
2078 PORTCR(249, 0xe60520F9),
2079 PORTCR(250, 0xe60520FA),
2080 PORTCR(256, 0xe6052100),
2081 PORTCR(257, 0xe6052101),
2082 PORTCR(258, 0xe6052102),
2083 PORTCR(259, 0xe6052103),
2084 PORTCR(260, 0xe6052104),
2085 PORTCR(261, 0xe6052105),
2086 PORTCR(262, 0xe6052106),
2087 PORTCR(263, 0xe6052107),
2088 PORTCR(264, 0xe6052108),
2089 PORTCR(265, 0xe6052109),
2090 PORTCR(266, 0xe605210A),
2091 PORTCR(267, 0xe605210B),
2092 PORTCR(268, 0xe605210C),
2093 PORTCR(269, 0xe605210D),
2094 PORTCR(270, 0xe605210E),
2095 PORTCR(271, 0xe605210F),
2096 PORTCR(272, 0xe6052110),
2097 PORTCR(273, 0xe6052111),
2098 PORTCR(274, 0xe6052112),
2099 PORTCR(275, 0xe6052113),
2100 PORTCR(276, 0xe6052114),
2101 PORTCR(277, 0xe6052115),
2102 PORTCR(278, 0xe6052116),
2103 PORTCR(279, 0xe6052117),
2104 PORTCR(280, 0xe6052118),
2105 PORTCR(281, 0xe6052119),
2106 PORTCR(282, 0xe605211A),
2107 PORTCR(283, 0xe605211B),
2108 PORTCR(288, 0xe6053120),
2109 PORTCR(289, 0xe6053121),
2110 PORTCR(290, 0xe6053122),
2111 PORTCR(291, 0xe6053123),
2112 PORTCR(292, 0xe6053124),
2113 PORTCR(293, 0xe6053125),
2114 PORTCR(294, 0xe6053126),
2115 PORTCR(295, 0xe6053127),
2116 PORTCR(296, 0xe6053128),
2117 PORTCR(297, 0xe6053129),
2118 PORTCR(298, 0xe605312A),
2119 PORTCR(299, 0xe605312B),
2120 PORTCR(300, 0xe605312C),
2121 PORTCR(301, 0xe605312D),
2122 PORTCR(302, 0xe605312E),
2123 PORTCR(303, 0xe605312F),
2124 PORTCR(304, 0xe6053130),
2125 PORTCR(305, 0xe6053131),
2126 PORTCR(306, 0xe6053132),
2127 PORTCR(307, 0xe6053133),
2128 PORTCR(308, 0xe6053134),
2129 PORTCR(320, 0xe6053140),
2130 PORTCR(321, 0xe6053141),
2131 PORTCR(322, 0xe6053142),
2132 PORTCR(323, 0xe6053143),
2133 PORTCR(324, 0xe6053144),
2134 PORTCR(325, 0xe6053145),
2135 PORTCR(326, 0xe6053146),
2136 PORTCR(327, 0xe6053147),
2137 PORTCR(328, 0xe6053148),
2138 PORTCR(329, 0xe6053149),
2139
2140 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2141 MSEL1CR_31_0, MSEL1CR_31_1,
2142 0, 0,
2143 0, 0,
2144 0, 0,
2145 MSEL1CR_27_0, MSEL1CR_27_1,
2146 0, 0,
2147 MSEL1CR_25_0, MSEL1CR_25_1,
2148 MSEL1CR_24_0, MSEL1CR_24_1,
2149 0, 0,
2150 MSEL1CR_22_0, MSEL1CR_22_1,
2151 MSEL1CR_21_0, MSEL1CR_21_1,
2152 MSEL1CR_20_0, MSEL1CR_20_1,
2153 MSEL1CR_19_0, MSEL1CR_19_1,
2154 MSEL1CR_18_0, MSEL1CR_18_1,
2155 MSEL1CR_17_0, MSEL1CR_17_1,
2156 MSEL1CR_16_0, MSEL1CR_16_1,
2157 MSEL1CR_15_0, MSEL1CR_15_1,
2158 MSEL1CR_14_0, MSEL1CR_14_1,
2159 MSEL1CR_13_0, MSEL1CR_13_1,
2160 MSEL1CR_12_0, MSEL1CR_12_1,
2161 MSEL1CR_11_0, MSEL1CR_11_1,
2162 MSEL1CR_10_0, MSEL1CR_10_1,
2163 MSEL1CR_09_0, MSEL1CR_09_1,
2164 MSEL1CR_08_0, MSEL1CR_08_1,
2165 MSEL1CR_07_0, MSEL1CR_07_1,
2166 MSEL1CR_06_0, MSEL1CR_06_1,
2167 MSEL1CR_05_0, MSEL1CR_05_1,
2168 MSEL1CR_04_0, MSEL1CR_04_1,
2169 MSEL1CR_03_0, MSEL1CR_03_1,
2170 MSEL1CR_02_0, MSEL1CR_02_1,
2171 MSEL1CR_01_0, MSEL1CR_01_1,
2172 MSEL1CR_00_0, MSEL1CR_00_1,
2173 }
2174 },
2175 { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
2176 MSEL3CR_31_0, MSEL3CR_31_1,
2177 0, 0,
2178 0, 0,
2179 MSEL3CR_28_0, MSEL3CR_28_1,
2180 MSEL3CR_27_0, MSEL3CR_27_1,
2181 MSEL3CR_26_0, MSEL3CR_26_1,
2182 0, 0,
2183 0, 0,
2184 MSEL3CR_23_0, MSEL3CR_23_1,
2185 MSEL3CR_22_0, MSEL3CR_22_1,
2186 MSEL3CR_21_0, MSEL3CR_21_1,
2187 MSEL3CR_20_0, MSEL3CR_20_1,
2188 MSEL3CR_19_0, MSEL3CR_19_1,
2189 MSEL3CR_18_0, MSEL3CR_18_1,
2190 MSEL3CR_17_0, MSEL3CR_17_1,
2191 MSEL3CR_16_0, MSEL3CR_16_1,
2192 MSEL3CR_15_0, MSEL3CR_15_1,
2193 0, 0,
2194 0, 0,
2195 MSEL3CR_12_0, MSEL3CR_12_1,
2196 MSEL3CR_11_0, MSEL3CR_11_1,
2197 MSEL3CR_10_0, MSEL3CR_10_1,
2198 MSEL3CR_09_0, MSEL3CR_09_1,
2199 0, 0,
2200 0, 0,
2201 MSEL3CR_06_0, MSEL3CR_06_1,
2202 0, 0,
2203 0, 0,
2204 MSEL3CR_03_0, MSEL3CR_03_1,
2205 0, 0,
2206 MSEL3CR_01_0, MSEL3CR_01_1,
2207 MSEL3CR_00_0, MSEL3CR_00_1,
2208 }
2209 },
2210 { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
2211 0, 0,
2212 MSEL4CR_30_0, MSEL4CR_30_1,
2213 MSEL4CR_29_0, MSEL4CR_29_1,
2214 MSEL4CR_28_0, MSEL4CR_28_1,
2215 MSEL4CR_27_0, MSEL4CR_27_1,
2216 MSEL4CR_26_0, MSEL4CR_26_1,
2217 MSEL4CR_25_0, MSEL4CR_25_1,
2218 MSEL4CR_24_0, MSEL4CR_24_1,
2219 MSEL4CR_23_0, MSEL4CR_23_1,
2220 MSEL4CR_22_0, MSEL4CR_22_1,
2221 MSEL4CR_21_0, MSEL4CR_21_1,
2222 MSEL4CR_20_0, MSEL4CR_20_1,
2223 MSEL4CR_19_0, MSEL4CR_19_1,
2224 MSEL4CR_18_0, MSEL4CR_18_1,
2225 MSEL4CR_17_0, MSEL4CR_17_1,
2226 MSEL4CR_16_0, MSEL4CR_16_1,
2227 MSEL4CR_15_0, MSEL4CR_15_1,
2228 MSEL4CR_14_0, MSEL4CR_14_1,
2229 MSEL4CR_13_0, MSEL4CR_13_1,
2230 MSEL4CR_12_0, MSEL4CR_12_1,
2231 MSEL4CR_11_0, MSEL4CR_11_1,
2232 MSEL4CR_10_0, MSEL4CR_10_1,
2233 MSEL4CR_09_0, MSEL4CR_09_1,
2234 0, 0,
2235 MSEL4CR_07_0, MSEL4CR_07_1,
2236 0, 0,
2237 0, 0,
2238 MSEL4CR_04_0, MSEL4CR_04_1,
2239 0, 0,
2240 0, 0,
2241 MSEL4CR_01_0, MSEL4CR_01_1,
2242 0, 0,
2243 }
2244 },
2245 { PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {
2246 MSEL5CR_31_0, MSEL5CR_31_1,
2247 MSEL5CR_30_0, MSEL5CR_30_1,
2248 MSEL5CR_29_0, MSEL5CR_29_1,
2249 MSEL5CR_28_0, MSEL5CR_28_1,
2250 MSEL5CR_27_0, MSEL5CR_27_1,
2251 MSEL5CR_26_0, MSEL5CR_26_1,
2252 MSEL5CR_25_0, MSEL5CR_25_1,
2253 MSEL5CR_24_0, MSEL5CR_24_1,
2254 MSEL5CR_23_0, MSEL5CR_23_1,
2255 MSEL5CR_22_0, MSEL5CR_22_1,
2256 MSEL5CR_21_0, MSEL5CR_21_1,
2257 MSEL5CR_20_0, MSEL5CR_20_1,
2258 MSEL5CR_19_0, MSEL5CR_19_1,
2259 MSEL5CR_18_0, MSEL5CR_18_1,
2260 MSEL5CR_17_0, MSEL5CR_17_1,
2261 MSEL5CR_16_0, MSEL5CR_16_1,
2262 MSEL5CR_15_0, MSEL5CR_15_1,
2263 MSEL5CR_14_0, MSEL5CR_14_1,
2264 MSEL5CR_13_0, MSEL5CR_13_1,
2265 MSEL5CR_12_0, MSEL5CR_12_1,
2266 MSEL5CR_11_0, MSEL5CR_11_1,
2267 MSEL5CR_10_0, MSEL5CR_10_1,
2268 MSEL5CR_09_0, MSEL5CR_09_1,
2269 MSEL5CR_08_0, MSEL5CR_08_1,
2270 MSEL5CR_07_0, MSEL5CR_07_1,
2271 MSEL5CR_06_0, MSEL5CR_06_1,
2272 0, 0,
2273 0, 0,
2274 0, 0,
2275 0, 0,
2276 0, 0,
2277 0, 0,
2278 }
2279 },
2280 { PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {
2281 0, 0,
2282 0, 0,
2283 0, 0,
2284 0, 0,
2285 0, 0,
2286 0, 0,
2287 0, 0,
2288 0, 0,
2289 0, 0,
2290 0, 0,
2291 0, 0,
2292 0, 0,
2293 0, 0,
2294 0, 0,
2295 0, 0,
2296 MSEL8CR_16_0, MSEL8CR_16_1,
2297 0, 0,
2298 0, 0,
2299 0, 0,
2300 0, 0,
2301 0, 0,
2302 0, 0,
2303 0, 0,
2304 0, 0,
2305 0, 0,
2306 0, 0,
2307 0, 0,
2308 0, 0,
2309 0, 0,
2310 0, 0,
2311 MSEL8CR_01_0, MSEL8CR_01_1,
2312 MSEL8CR_00_0, MSEL8CR_00_1,
2313 }
2314 },
2315 { },
2316};
2317
2318static const struct pinmux_data_reg pinmux_data_regs[] = {
2319
2320 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
2321 0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2322 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2323 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2324 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2325 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2326 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2327 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2328 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
2329 }
2330 },
2331 { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
2332 0, 0, 0, 0,
2333 0, 0, 0, 0,
2334 0, 0, 0, 0,
2335 0, 0, 0, 0,
2336 0, 0, 0, 0,
2337 0, 0, 0, PORT40_DATA,
2338 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2339 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
2340 }
2341 },
2342 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) {
2343 0, 0, 0, 0,
2344 0, 0, 0, 0,
2345 0, 0, PORT85_DATA, PORT84_DATA,
2346 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2347 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2348 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2349 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2350 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
2351 }
2352 },
2353 { PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
2354 0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2355 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2356 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2357 PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2358 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2359 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2360 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2361 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
2362 }
2363 },
2364 { PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
2365 0, 0, 0, 0,
2366 0, 0, 0, 0,
2367 0, 0, 0, 0,
2368 0, 0, 0, 0,
2369 0, 0, 0, 0,
2370 0, 0, 0, 0,
2371 0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2372 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
2373 }
2374 },
2375 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
2376 0, 0, 0, 0,
2377 0, 0, 0, 0,
2378 0, 0, 0, 0,
2379 0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2380 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2381 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2382 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2383 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
2384 }
2385 },
2386 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
2387 0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
2388 PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
2389 PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
2390 PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
2391 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2392 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2393 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2394 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
2395 }
2396 },
2397 { PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) {
2398 0, 0, 0, 0,
2399 0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
2400 PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
2401 PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
2402 PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
2403 PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
2404 PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
2405 PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
2406 }
2407 },
2408 { PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) {
2409 0, 0, 0, 0,
2410 PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
2411 PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
2412 PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
2413 PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
2414 PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
2415 PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
2416 PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
2417 }
2418 },
2419 { PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) {
2420 0, 0, 0, 0,
2421 0, 0, 0, 0,
2422 0, 0, 0, PORT308_DATA,
2423 PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
2424 PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
2425 PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
2426 PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
2427 PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
2428 }
2429 },
2430 { PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) {
2431 0, 0, 0, 0,
2432 0, 0, 0, 0,
2433 0, 0, 0, 0,
2434 0, 0, 0, 0,
2435 0, 0, 0, 0,
2436 0, 0, PORT329_DATA, PORT328_DATA,
2437 PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
2438 PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
2439 }
2440 },
2441 { },
2442};
2443
2444static const struct pinmux_irq pinmux_irqs[] = {
2445 PINMUX_IRQ(irq_pin(0), 0),
2446 PINMUX_IRQ(irq_pin(1), 1),
2447 PINMUX_IRQ(irq_pin(2), 2),
2448 PINMUX_IRQ(irq_pin(3), 3),
2449 PINMUX_IRQ(irq_pin(4), 4),
2450 PINMUX_IRQ(irq_pin(5), 5),
2451 PINMUX_IRQ(irq_pin(6), 6),
2452 PINMUX_IRQ(irq_pin(7), 7),
2453 PINMUX_IRQ(irq_pin(8), 8),
2454 PINMUX_IRQ(irq_pin(9), 9),
2455 PINMUX_IRQ(irq_pin(10), 10),
2456 PINMUX_IRQ(irq_pin(11), 11),
2457 PINMUX_IRQ(irq_pin(12), 12),
2458 PINMUX_IRQ(irq_pin(13), 13),
2459 PINMUX_IRQ(irq_pin(14), 14),
2460 PINMUX_IRQ(irq_pin(15), 15),
2461 PINMUX_IRQ(irq_pin(16), 320),
2462 PINMUX_IRQ(irq_pin(17), 321),
2463 PINMUX_IRQ(irq_pin(18), 85),
2464 PINMUX_IRQ(irq_pin(19), 84),
2465 PINMUX_IRQ(irq_pin(20), 160),
2466 PINMUX_IRQ(irq_pin(21), 161),
2467 PINMUX_IRQ(irq_pin(22), 162),
2468 PINMUX_IRQ(irq_pin(23), 163),
2469 PINMUX_IRQ(irq_pin(24), 175),
2470 PINMUX_IRQ(irq_pin(25), 176),
2471 PINMUX_IRQ(irq_pin(26), 177),
2472 PINMUX_IRQ(irq_pin(27), 178),
2473 PINMUX_IRQ(irq_pin(28), 322),
2474 PINMUX_IRQ(irq_pin(29), 323),
2475 PINMUX_IRQ(irq_pin(30), 324),
2476 PINMUX_IRQ(irq_pin(31), 192),
2477 PINMUX_IRQ(irq_pin(32), 193),
2478 PINMUX_IRQ(irq_pin(33), 194),
2479 PINMUX_IRQ(irq_pin(34), 195),
2480 PINMUX_IRQ(irq_pin(35), 196),
2481 PINMUX_IRQ(irq_pin(36), 197),
2482 PINMUX_IRQ(irq_pin(37), 198),
2483 PINMUX_IRQ(irq_pin(38), 199),
2484 PINMUX_IRQ(irq_pin(39), 200),
2485 PINMUX_IRQ(irq_pin(40), 66),
2486 PINMUX_IRQ(irq_pin(41), 102),
2487 PINMUX_IRQ(irq_pin(42), 103),
2488 PINMUX_IRQ(irq_pin(43), 109),
2489 PINMUX_IRQ(irq_pin(44), 110),
2490 PINMUX_IRQ(irq_pin(45), 111),
2491 PINMUX_IRQ(irq_pin(46), 112),
2492 PINMUX_IRQ(irq_pin(47), 113),
2493 PINMUX_IRQ(irq_pin(48), 114),
2494 PINMUX_IRQ(irq_pin(49), 115),
2495 PINMUX_IRQ(irq_pin(50), 301),
2496 PINMUX_IRQ(irq_pin(51), 290),
2497 PINMUX_IRQ(irq_pin(52), 296),
2498 PINMUX_IRQ(irq_pin(53), 325),
2499 PINMUX_IRQ(irq_pin(54), 326),
2500 PINMUX_IRQ(irq_pin(55), 327),
2501 PINMUX_IRQ(irq_pin(56), 328),
2502 PINMUX_IRQ(irq_pin(57), 329),
2503};
2504
2505#define PORTCR_PULMD_OFF (0 << 6)
2506#define PORTCR_PULMD_DOWN (2 << 6)
2507#define PORTCR_PULMD_UP (3 << 6)
2508#define PORTCR_PULMD_MASK (3 << 6)
2509
2510static const unsigned int r8a73a4_portcr_offsets[] = {
2511 0x00000000, 0x00001000, 0x00000000, 0x00001000,
2512 0x00001000, 0x00002000, 0x00002000, 0x00002000,
2513 0x00002000, 0x00003000, 0x00003000,
2514};
2515
2516static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
2517 unsigned int pin)
2518{
2519 void __iomem *addr;
2520
2521 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2522
2523 switch (ioread8(addr) & PORTCR_PULMD_MASK) {
2524 case PORTCR_PULMD_UP:
2525 return PIN_CONFIG_BIAS_PULL_UP;
2526 case PORTCR_PULMD_DOWN:
2527 return PIN_CONFIG_BIAS_PULL_DOWN;
2528 case PORTCR_PULMD_OFF:
2529 default:
2530 return PIN_CONFIG_BIAS_DISABLE;
2531 }
2532}
2533
2534static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2535 unsigned int bias)
2536{
2537 void __iomem *addr;
2538 u32 value;
2539
2540 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2541 value = ioread8(addr) & ~PORTCR_PULMD_MASK;
2542
2543 switch (bias) {
2544 case PIN_CONFIG_BIAS_PULL_UP:
2545 value |= PORTCR_PULMD_UP;
2546 break;
2547 case PIN_CONFIG_BIAS_PULL_DOWN:
2548 value |= PORTCR_PULMD_DOWN;
2549 break;
2550 }
2551
2552 iowrite8(value, addr);
2553}
2554
2555static const struct sh_pfc_soc_operations r8a73a4_pinmux_ops = {
2556 .get_bias = r8a73a4_pinmux_get_bias,
2557 .set_bias = r8a73a4_pinmux_set_bias,
2558};
2559
2560const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
2561 .name = "r8a73a4_pfc",
2562 .ops = &r8a73a4_pinmux_ops,
2563
2564 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2565 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2566 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2567
2568 .pins = pinmux_pins,
2569 .nr_pins = ARRAY_SIZE(pinmux_pins),
2570
2571 .ranges = pinmux_ranges,
2572 .nr_ranges = ARRAY_SIZE(pinmux_ranges),
2573
2574 .groups = pinmux_groups,
2575 .nr_groups = ARRAY_SIZE(pinmux_groups),
2576 .functions = pinmux_functions,
2577 .nr_functions = ARRAY_SIZE(pinmux_functions),
2578
2579 .cfg_regs = pinmux_config_regs,
2580 .data_regs = pinmux_data_regs,
2581
2582 .gpio_data = pinmux_data,
2583 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2584
2585 .gpio_irq = pinmux_irqs,
2586 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
2587};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index 2b528280e3c1..bbd87d29bfd0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -577,7 +577,7 @@ enum {
577 PINMUX_MARK_END, 577 PINMUX_MARK_END,
578}; 578};
579 579
580static pinmux_enum_t pinmux_data[] = { 580static const pinmux_enum_t pinmux_data[] = {
581 /* specify valid pin states for each pin in GPIO mode */ 581 /* specify valid pin states for each pin in GPIO mode */
582 582
583 /* I/O and Pull U/D */ 583 /* I/O and Pull U/D */
@@ -1654,11 +1654,532 @@ static pinmux_enum_t pinmux_data[] = {
1654 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0), 1654 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1655}; 1655};
1656 1656
1657static struct pinmux_gpio pinmux_gpios[] = { 1657static struct sh_pfc_pin pinmux_pins[] = {
1658
1659 /* PORT */
1660 GPIO_PORT_ALL(), 1658 GPIO_PORT_ALL(),
1659};
1660
1661/* - LCD0 ------------------------------------------------------------------- */
1662static const unsigned int lcd0_data8_pins[] = {
1663 /* D[0:7] */
1664 58, 57, 56, 55, 54, 53, 52, 51,
1665};
1666static const unsigned int lcd0_data8_mux[] = {
1667 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1668 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1669};
1670static const unsigned int lcd0_data9_pins[] = {
1671 /* D[0:8] */
1672 58, 57, 56, 55, 54, 53, 52, 51,
1673 50,
1674};
1675static const unsigned int lcd0_data9_mux[] = {
1676 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1677 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1678 LCD0_D8_MARK,
1679};
1680static const unsigned int lcd0_data12_pins[] = {
1681 /* D[0:11] */
1682 58, 57, 56, 55, 54, 53, 52, 51,
1683 50, 49, 48, 47,
1684};
1685static const unsigned int lcd0_data12_mux[] = {
1686 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1687 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1688 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1689};
1690static const unsigned int lcd0_data16_pins[] = {
1691 /* D[0:15] */
1692 58, 57, 56, 55, 54, 53, 52, 51,
1693 50, 49, 48, 47, 46, 45, 44, 43,
1694};
1695static const unsigned int lcd0_data16_mux[] = {
1696 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1697 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1698 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1699 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
1700};
1701static const unsigned int lcd0_data18_pins[] = {
1702 /* D[0:17] */
1703 58, 57, 56, 55, 54, 53, 52, 51,
1704 50, 49, 48, 47, 46, 45, 44, 43,
1705 42, 41,
1706};
1707static const unsigned int lcd0_data18_mux[] = {
1708 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1709 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1710 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1711 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
1712 LCD0_D16_MARK, LCD0_D17_MARK,
1713};
1714static const unsigned int lcd0_data24_0_pins[] = {
1715 /* D[0:23] */
1716 58, 57, 56, 55, 54, 53, 52, 51,
1717 50, 49, 48, 47, 46, 45, 44, 43,
1718 42, 41, 40, 4, 3, 2, 0, 1,
1719};
1720static const unsigned int lcd0_data24_0_mux[] = {
1721 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1722 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1723 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1724 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
1725 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
1726 LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
1727 LCD0_D23_PORT1_MARK,
1728};
1729static const unsigned int lcd0_data24_1_pins[] = {
1730 /* D[0:23] */
1731 58, 57, 56, 55, 54, 53, 52, 51,
1732 50, 49, 48, 47, 46, 45, 44, 43,
1733 42, 41, 163, 162, 161, 158, 160, 159,
1734};
1735static const unsigned int lcd0_data24_1_mux[] = {
1736 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
1737 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
1738 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
1739 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
1740 LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
1741 LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
1742};
1743static const unsigned int lcd0_display_pins[] = {
1744 /* DON, VCPWC, VEPWC */
1745 61, 59, 60,
1746};
1747static const unsigned int lcd0_display_mux[] = {
1748 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
1749};
1750static const unsigned int lcd0_lclk_0_pins[] = {
1751 /* LCLK */
1752 102,
1753};
1754static const unsigned int lcd0_lclk_0_mux[] = {
1755 LCD0_LCLK_PORT102_MARK,
1756};
1757static const unsigned int lcd0_lclk_1_pins[] = {
1758 /* LCLK */
1759 165,
1760};
1761static const unsigned int lcd0_lclk_1_mux[] = {
1762 LCD0_LCLK_PORT165_MARK,
1763};
1764static const unsigned int lcd0_sync_pins[] = {
1765 /* VSYN, HSYN, DCK, DISP */
1766 63, 64, 62, 65,
1767};
1768static const unsigned int lcd0_sync_mux[] = {
1769 LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
1770};
1771static const unsigned int lcd0_sys_pins[] = {
1772 /* CS, WR, RD, RS */
1773 64, 62, 164, 65,
1774};
1775static const unsigned int lcd0_sys_mux[] = {
1776 LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
1777};
1778/* - LCD1 ------------------------------------------------------------------- */
1779static const unsigned int lcd1_data8_pins[] = {
1780 /* D[0:7] */
1781 4, 3, 2, 1, 0, 91, 92, 23,
1782};
1783static const unsigned int lcd1_data8_mux[] = {
1784 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1785 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1786};
1787static const unsigned int lcd1_data9_pins[] = {
1788 /* D[0:8] */
1789 4, 3, 2, 1, 0, 91, 92, 23,
1790 93,
1791};
1792static const unsigned int lcd1_data9_mux[] = {
1793 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1794 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1795 LCD1_D8_MARK,
1796};
1797static const unsigned int lcd1_data12_pins[] = {
1798 /* D[0:12] */
1799 4, 3, 2, 1, 0, 91, 92, 23,
1800 93, 94, 21, 201,
1801};
1802static const unsigned int lcd1_data12_mux[] = {
1803 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1804 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1805 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
1806};
1807static const unsigned int lcd1_data16_pins[] = {
1808 /* D[0:15] */
1809 4, 3, 2, 1, 0, 91, 92, 23,
1810 93, 94, 21, 201, 200, 199, 196, 195,
1811};
1812static const unsigned int lcd1_data16_mux[] = {
1813 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1814 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1815 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
1816 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
1817};
1818static const unsigned int lcd1_data18_pins[] = {
1819 /* D[0:17] */
1820 4, 3, 2, 1, 0, 91, 92, 23,
1821 93, 94, 21, 201, 200, 199, 196, 195,
1822 194, 193,
1823};
1824static const unsigned int lcd1_data18_mux[] = {
1825 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1826 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1827 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
1828 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
1829 LCD1_D16_MARK, LCD1_D17_MARK,
1830};
1831static const unsigned int lcd1_data24_pins[] = {
1832 /* D[0:23] */
1833 4, 3, 2, 1, 0, 91, 92, 23,
1834 93, 94, 21, 201, 200, 199, 196, 195,
1835 194, 193, 198, 197, 75, 74, 15, 14,
1836};
1837static const unsigned int lcd1_data24_mux[] = {
1838 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
1839 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
1840 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
1841 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
1842 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
1843 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
1844};
1845static const unsigned int lcd1_display_pins[] = {
1846 /* DON, VCPWC, VEPWC */
1847 100, 5, 6,
1848};
1849static const unsigned int lcd1_display_mux[] = {
1850 LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
1851};
1852static const unsigned int lcd1_lclk_pins[] = {
1853 /* LCLK */
1854 40,
1855};
1856static const unsigned int lcd1_lclk_mux[] = {
1857 LCD1_LCLK_MARK,
1858};
1859static const unsigned int lcd1_sync_pins[] = {
1860 /* VSYN, HSYN, DCK, DISP */
1861 98, 97, 99, 12,
1862};
1863static const unsigned int lcd1_sync_mux[] = {
1864 LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
1865};
1866static const unsigned int lcd1_sys_pins[] = {
1867 /* CS, WR, RD, RS */
1868 97, 99, 13, 12,
1869};
1870static const unsigned int lcd1_sys_mux[] = {
1871 LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
1872};
1873/* - MMCIF ------------------------------------------------------------------ */
1874static const unsigned int mmc0_data1_0_pins[] = {
1875 /* D[0] */
1876 68,
1877};
1878static const unsigned int mmc0_data1_0_mux[] = {
1879 MMC0_D0_PORT68_MARK,
1880};
1881static const unsigned int mmc0_data4_0_pins[] = {
1882 /* D[0:3] */
1883 68, 69, 70, 71,
1884};
1885static const unsigned int mmc0_data4_0_mux[] = {
1886 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
1887};
1888static const unsigned int mmc0_data8_0_pins[] = {
1889 /* D[0:7] */
1890 68, 69, 70, 71, 72, 73, 74, 75,
1891};
1892static const unsigned int mmc0_data8_0_mux[] = {
1893 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
1894 MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
1895};
1896static const unsigned int mmc0_ctrl_0_pins[] = {
1897 /* CMD, CLK */
1898 67, 66,
1899};
1900static const unsigned int mmc0_ctrl_0_mux[] = {
1901 MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
1902};
1903
1904static const unsigned int mmc0_data1_1_pins[] = {
1905 /* D[0] */
1906 149,
1907};
1908static const unsigned int mmc0_data1_1_mux[] = {
1909 MMC1_D0_PORT149_MARK,
1910};
1911static const unsigned int mmc0_data4_1_pins[] = {
1912 /* D[0:3] */
1913 149, 148, 147, 146,
1914};
1915static const unsigned int mmc0_data4_1_mux[] = {
1916 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
1917};
1918static const unsigned int mmc0_data8_1_pins[] = {
1919 /* D[0:7] */
1920 149, 148, 147, 146, 145, 144, 143, 142,
1921};
1922static const unsigned int mmc0_data8_1_mux[] = {
1923 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
1924 MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
1925};
1926static const unsigned int mmc0_ctrl_1_pins[] = {
1927 /* CMD, CLK */
1928 104, 103,
1929};
1930static const unsigned int mmc0_ctrl_1_mux[] = {
1931 MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
1932};
1933/* - SDHI0 ------------------------------------------------------------------ */
1934static const unsigned int sdhi0_data1_pins[] = {
1935 /* D0 */
1936 77,
1937};
1938static const unsigned int sdhi0_data1_mux[] = {
1939 SDHI0_D0_MARK,
1940};
1941static const unsigned int sdhi0_data4_pins[] = {
1942 /* D[0:3] */
1943 77, 78, 79, 80,
1944};
1945static const unsigned int sdhi0_data4_mux[] = {
1946 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
1947};
1948static const unsigned int sdhi0_ctrl_pins[] = {
1949 /* CMD, CLK */
1950 76, 82,
1951};
1952static const unsigned int sdhi0_ctrl_mux[] = {
1953 SDHI0_CMD_MARK, SDHI0_CLK_MARK,
1954};
1955static const unsigned int sdhi0_cd_pins[] = {
1956 /* CD */
1957 81,
1958};
1959static const unsigned int sdhi0_cd_mux[] = {
1960 SDHI0_CD_MARK,
1961};
1962static const unsigned int sdhi0_wp_pins[] = {
1963 /* WP */
1964 83,
1965};
1966static const unsigned int sdhi0_wp_mux[] = {
1967 SDHI0_WP_MARK,
1968};
1969/* - SDHI1 ------------------------------------------------------------------ */
1970static const unsigned int sdhi1_data1_pins[] = {
1971 /* D0 */
1972 68,
1973};
1974static const unsigned int sdhi1_data1_mux[] = {
1975 SDHI1_D0_MARK,
1976};
1977static const unsigned int sdhi1_data4_pins[] = {
1978 /* D[0:3] */
1979 68, 69, 70, 71,
1980};
1981static const unsigned int sdhi1_data4_mux[] = {
1982 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
1983};
1984static const unsigned int sdhi1_ctrl_pins[] = {
1985 /* CMD, CLK */
1986 67, 66,
1987};
1988static const unsigned int sdhi1_ctrl_mux[] = {
1989 SDHI1_CMD_MARK, SDHI1_CLK_MARK,
1990};
1991static const unsigned int sdhi1_cd_pins[] = {
1992 /* CD */
1993 72,
1994};
1995static const unsigned int sdhi1_cd_mux[] = {
1996 SDHI1_CD_MARK,
1997};
1998static const unsigned int sdhi1_wp_pins[] = {
1999 /* WP */
2000 73,
2001};
2002static const unsigned int sdhi1_wp_mux[] = {
2003 SDHI1_WP_MARK,
2004};
2005/* - SDHI2 ------------------------------------------------------------------ */
2006static const unsigned int sdhi2_data1_pins[] = {
2007 /* D0 */
2008 205,
2009};
2010static const unsigned int sdhi2_data1_mux[] = {
2011 SDHI2_D0_MARK,
2012};
2013static const unsigned int sdhi2_data4_pins[] = {
2014 /* D[0:3] */
2015 205, 206, 207, 208,
2016};
2017static const unsigned int sdhi2_data4_mux[] = {
2018 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
2019};
2020static const unsigned int sdhi2_ctrl_pins[] = {
2021 /* CMD, CLK */
2022 204, 203,
2023};
2024static const unsigned int sdhi2_ctrl_mux[] = {
2025 SDHI2_CMD_MARK, SDHI2_CLK_MARK,
2026};
2027static const unsigned int sdhi2_cd_0_pins[] = {
2028 /* CD */
2029 202,
2030};
2031static const unsigned int sdhi2_cd_0_mux[] = {
2032 SDHI2_CD_PORT202_MARK,
2033};
2034static const unsigned int sdhi2_wp_0_pins[] = {
2035 /* WP */
2036 177,
2037};
2038static const unsigned int sdhi2_wp_0_mux[] = {
2039 SDHI2_WP_PORT177_MARK,
2040};
2041static const unsigned int sdhi2_cd_1_pins[] = {
2042 /* CD */
2043 24,
2044};
2045static const unsigned int sdhi2_cd_1_mux[] = {
2046 SDHI2_CD_PORT24_MARK,
2047};
2048static const unsigned int sdhi2_wp_1_pins[] = {
2049 /* WP */
2050 25,
2051};
2052static const unsigned int sdhi2_wp_1_mux[] = {
2053 SDHI2_WP_PORT25_MARK,
2054};
2055
2056static const struct sh_pfc_pin_group pinmux_groups[] = {
2057 SH_PFC_PIN_GROUP(lcd0_data8),
2058 SH_PFC_PIN_GROUP(lcd0_data9),
2059 SH_PFC_PIN_GROUP(lcd0_data12),
2060 SH_PFC_PIN_GROUP(lcd0_data16),
2061 SH_PFC_PIN_GROUP(lcd0_data18),
2062 SH_PFC_PIN_GROUP(lcd0_data24_0),
2063 SH_PFC_PIN_GROUP(lcd0_data24_1),
2064 SH_PFC_PIN_GROUP(lcd0_display),
2065 SH_PFC_PIN_GROUP(lcd0_lclk_0),
2066 SH_PFC_PIN_GROUP(lcd0_lclk_1),
2067 SH_PFC_PIN_GROUP(lcd0_sync),
2068 SH_PFC_PIN_GROUP(lcd0_sys),
2069 SH_PFC_PIN_GROUP(lcd1_data8),
2070 SH_PFC_PIN_GROUP(lcd1_data9),
2071 SH_PFC_PIN_GROUP(lcd1_data12),
2072 SH_PFC_PIN_GROUP(lcd1_data16),
2073 SH_PFC_PIN_GROUP(lcd1_data18),
2074 SH_PFC_PIN_GROUP(lcd1_data24),
2075 SH_PFC_PIN_GROUP(lcd1_display),
2076 SH_PFC_PIN_GROUP(lcd1_lclk),
2077 SH_PFC_PIN_GROUP(lcd1_sync),
2078 SH_PFC_PIN_GROUP(lcd1_sys),
2079 SH_PFC_PIN_GROUP(mmc0_data1_0),
2080 SH_PFC_PIN_GROUP(mmc0_data4_0),
2081 SH_PFC_PIN_GROUP(mmc0_data8_0),
2082 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2083 SH_PFC_PIN_GROUP(mmc0_data1_1),
2084 SH_PFC_PIN_GROUP(mmc0_data4_1),
2085 SH_PFC_PIN_GROUP(mmc0_data8_1),
2086 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
2087 SH_PFC_PIN_GROUP(sdhi0_data1),
2088 SH_PFC_PIN_GROUP(sdhi0_data4),
2089 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2090 SH_PFC_PIN_GROUP(sdhi0_cd),
2091 SH_PFC_PIN_GROUP(sdhi0_wp),
2092 SH_PFC_PIN_GROUP(sdhi1_data1),
2093 SH_PFC_PIN_GROUP(sdhi1_data4),
2094 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2095 SH_PFC_PIN_GROUP(sdhi1_cd),
2096 SH_PFC_PIN_GROUP(sdhi1_wp),
2097 SH_PFC_PIN_GROUP(sdhi2_data1),
2098 SH_PFC_PIN_GROUP(sdhi2_data4),
2099 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2100 SH_PFC_PIN_GROUP(sdhi2_cd_0),
2101 SH_PFC_PIN_GROUP(sdhi2_wp_0),
2102 SH_PFC_PIN_GROUP(sdhi2_cd_1),
2103 SH_PFC_PIN_GROUP(sdhi2_wp_1),
2104};
2105
2106static const char * const lcd0_groups[] = {
2107 "lcd0_data8",
2108 "lcd0_data9",
2109 "lcd0_data12",
2110 "lcd0_data16",
2111 "lcd0_data18",
2112 "lcd0_data24_0",
2113 "lcd0_data24_1",
2114 "lcd0_display",
2115 "lcd0_lclk_0",
2116 "lcd0_lclk_1",
2117 "lcd0_sync",
2118 "lcd0_sys",
2119};
2120
2121static const char * const lcd1_groups[] = {
2122 "lcd1_data8",
2123 "lcd1_data9",
2124 "lcd1_data12",
2125 "lcd1_data16",
2126 "lcd1_data18",
2127 "lcd1_data24",
2128 "lcd1_display",
2129 "lcd1_lclk",
2130 "lcd1_sync",
2131 "lcd1_sys",
2132};
2133
2134static const char * const mmc0_groups[] = {
2135 "mmc0_data1_0",
2136 "mmc0_data4_0",
2137 "mmc0_data8_0",
2138 "mmc0_ctrl_0",
2139 "mmc0_data1_1",
2140 "mmc0_data4_1",
2141 "mmc0_data8_1",
2142 "mmc0_ctrl_1",
2143};
2144
2145static const char * const sdhi0_groups[] = {
2146 "sdhi0_data1",
2147 "sdhi0_data4",
2148 "sdhi0_ctrl",
2149 "sdhi0_cd",
2150 "sdhi0_wp",
2151};
2152
2153static const char * const sdhi1_groups[] = {
2154 "sdhi1_data1",
2155 "sdhi1_data4",
2156 "sdhi1_ctrl",
2157 "sdhi1_cd",
2158 "sdhi1_wp",
2159};
2160
2161static const char * const sdhi2_groups[] = {
2162 "sdhi2_data1",
2163 "sdhi2_data4",
2164 "sdhi2_ctrl",
2165 "sdhi2_cd_0",
2166 "sdhi2_wp_0",
2167 "sdhi2_cd_1",
2168 "sdhi2_wp_1",
2169};
2170
2171static const struct sh_pfc_function pinmux_functions[] = {
2172 SH_PFC_FUNCTION(lcd0),
2173 SH_PFC_FUNCTION(lcd1),
2174 SH_PFC_FUNCTION(mmc0),
2175 SH_PFC_FUNCTION(sdhi0),
2176 SH_PFC_FUNCTION(sdhi1),
2177 SH_PFC_FUNCTION(sdhi2),
2178};
1661 2179
2180#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
2181
2182static const struct pinmux_func pinmux_func_gpios[] = {
1662 /* IRQ */ 2183 /* IRQ */
1663 GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13), 2184 GPIO_FN(IRQ0_PORT2), GPIO_FN(IRQ0_PORT13),
1664 GPIO_FN(IRQ1), 2185 GPIO_FN(IRQ1),
@@ -1792,43 +2313,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1792 GPIO_FN(SCIFB_RTS_PORT172), 2313 GPIO_FN(SCIFB_RTS_PORT172),
1793 GPIO_FN(SCIFB_CTS_PORT173), 2314 GPIO_FN(SCIFB_CTS_PORT173),
1794 2315
1795 /* LCD0 */
1796 GPIO_FN(LCD0_D0), GPIO_FN(LCD0_D1), GPIO_FN(LCD0_D2),
1797 GPIO_FN(LCD0_D3), GPIO_FN(LCD0_D4), GPIO_FN(LCD0_D5),
1798 GPIO_FN(LCD0_D6), GPIO_FN(LCD0_D7), GPIO_FN(LCD0_D8),
1799 GPIO_FN(LCD0_D9), GPIO_FN(LCD0_D10), GPIO_FN(LCD0_D11),
1800 GPIO_FN(LCD0_D12), GPIO_FN(LCD0_D13), GPIO_FN(LCD0_D14),
1801 GPIO_FN(LCD0_D15), GPIO_FN(LCD0_D16), GPIO_FN(LCD0_D17),
1802 GPIO_FN(LCD0_DON), GPIO_FN(LCD0_VCPWC), GPIO_FN(LCD0_VEPWC),
1803 GPIO_FN(LCD0_DCK), GPIO_FN(LCD0_VSYN),
1804 GPIO_FN(LCD0_HSYN), GPIO_FN(LCD0_DISP),
1805 GPIO_FN(LCD0_WR), GPIO_FN(LCD0_RD),
1806 GPIO_FN(LCD0_CS), GPIO_FN(LCD0_RS),
1807
1808 GPIO_FN(LCD0_D18_PORT163), GPIO_FN(LCD0_D19_PORT162),
1809 GPIO_FN(LCD0_D20_PORT161), GPIO_FN(LCD0_D21_PORT158),
1810 GPIO_FN(LCD0_D22_PORT160), GPIO_FN(LCD0_D23_PORT159),
1811 GPIO_FN(LCD0_LCLK_PORT165), /* MSEL5CR_6_1 */
1812
1813 GPIO_FN(LCD0_D18_PORT40), GPIO_FN(LCD0_D19_PORT4),
1814 GPIO_FN(LCD0_D20_PORT3), GPIO_FN(LCD0_D21_PORT2),
1815 GPIO_FN(LCD0_D22_PORT0), GPIO_FN(LCD0_D23_PORT1),
1816 GPIO_FN(LCD0_LCLK_PORT102), /* MSEL5CR_6_0 */
1817
1818 /* LCD1 */
1819 GPIO_FN(LCD1_D0), GPIO_FN(LCD1_D1), GPIO_FN(LCD1_D2),
1820 GPIO_FN(LCD1_D3), GPIO_FN(LCD1_D4), GPIO_FN(LCD1_D5),
1821 GPIO_FN(LCD1_D6), GPIO_FN(LCD1_D7), GPIO_FN(LCD1_D8),
1822 GPIO_FN(LCD1_D9), GPIO_FN(LCD1_D10), GPIO_FN(LCD1_D11),
1823 GPIO_FN(LCD1_D12), GPIO_FN(LCD1_D13), GPIO_FN(LCD1_D14),
1824 GPIO_FN(LCD1_D15), GPIO_FN(LCD1_D16), GPIO_FN(LCD1_D17),
1825 GPIO_FN(LCD1_D18), GPIO_FN(LCD1_D19), GPIO_FN(LCD1_D20),
1826 GPIO_FN(LCD1_D21), GPIO_FN(LCD1_D22), GPIO_FN(LCD1_D23),
1827 GPIO_FN(LCD1_RS), GPIO_FN(LCD1_RD), GPIO_FN(LCD1_CS),
1828 GPIO_FN(LCD1_WR), GPIO_FN(LCD1_DCK), GPIO_FN(LCD1_DON),
1829 GPIO_FN(LCD1_VCPWC), GPIO_FN(LCD1_LCLK), GPIO_FN(LCD1_HSYN),
1830 GPIO_FN(LCD1_VSYN), GPIO_FN(LCD1_VEPWC), GPIO_FN(LCD1_DISP),
1831
1832 /* RSPI */ 2316 /* RSPI */
1833 GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A), 2317 GPIO_FN(RSPI_SSL0_A), GPIO_FN(RSPI_SSL1_A), GPIO_FN(RSPI_SSL2_A),
1834 GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A), 2318 GPIO_FN(RSPI_SSL3_A), GPIO_FN(RSPI_CK_A), GPIO_FN(RSPI_MOSI_A),
@@ -1889,26 +2373,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1889 GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */ 2373 GPIO_FN(SIM_D_PORT22), /* SIM_D Port 22/199 */
1890 GPIO_FN(SIM_D_PORT199), 2374 GPIO_FN(SIM_D_PORT199),
1891 2375
1892 /* SDHI0 */
1893 GPIO_FN(SDHI0_D0), GPIO_FN(SDHI0_D1), GPIO_FN(SDHI0_D2),
1894 GPIO_FN(SDHI0_D3), GPIO_FN(SDHI0_CD), GPIO_FN(SDHI0_WP),
1895 GPIO_FN(SDHI0_CMD), GPIO_FN(SDHI0_CLK),
1896
1897 /* SDHI1 */
1898 GPIO_FN(SDHI1_D0), GPIO_FN(SDHI1_D1), GPIO_FN(SDHI1_D2),
1899 GPIO_FN(SDHI1_D3), GPIO_FN(SDHI1_CD), GPIO_FN(SDHI1_WP),
1900 GPIO_FN(SDHI1_CMD), GPIO_FN(SDHI1_CLK),
1901
1902 /* SDHI2 */
1903 GPIO_FN(SDHI2_D0), GPIO_FN(SDHI2_D1), GPIO_FN(SDHI2_D2),
1904 GPIO_FN(SDHI2_D3), GPIO_FN(SDHI2_CLK), GPIO_FN(SDHI2_CMD),
1905
1906 GPIO_FN(SDHI2_CD_PORT24), /* MSEL5CR_19_0 */
1907 GPIO_FN(SDHI2_WP_PORT25),
1908
1909 GPIO_FN(SDHI2_WP_PORT177), /* MSEL5CR_19_1 */
1910 GPIO_FN(SDHI2_CD_PORT202),
1911
1912 /* MSIOF2 */ 2376 /* MSIOF2 */
1913 GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK), 2377 GPIO_FN(MSIOF2_TXD), GPIO_FN(MSIOF2_RXD), GPIO_FN(MSIOF2_TSCK),
1914 GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1), 2378 GPIO_FN(MSIOF2_SS2), GPIO_FN(MSIOF2_TSYNC), GPIO_FN(MSIOF2_SS1),
@@ -1953,21 +2417,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1953 GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK), 2417 GPIO_FN(MEMC_WAIT), GPIO_FN(MEMC_DREQ1), GPIO_FN(MEMC_BUSCLK),
1954 GPIO_FN(MEMC_A0), 2418 GPIO_FN(MEMC_A0),
1955 2419
1956 /* MMC */
1957 GPIO_FN(MMC0_D0_PORT68), GPIO_FN(MMC0_D1_PORT69),
1958 GPIO_FN(MMC0_D2_PORT70), GPIO_FN(MMC0_D3_PORT71),
1959 GPIO_FN(MMC0_D4_PORT72), GPIO_FN(MMC0_D5_PORT73),
1960 GPIO_FN(MMC0_D6_PORT74), GPIO_FN(MMC0_D7_PORT75),
1961 GPIO_FN(MMC0_CLK_PORT66),
1962 GPIO_FN(MMC0_CMD_PORT67), /* MSEL4CR_15_0 */
1963
1964 GPIO_FN(MMC1_D0_PORT149), GPIO_FN(MMC1_D1_PORT148),
1965 GPIO_FN(MMC1_D2_PORT147), GPIO_FN(MMC1_D3_PORT146),
1966 GPIO_FN(MMC1_D4_PORT145), GPIO_FN(MMC1_D5_PORT144),
1967 GPIO_FN(MMC1_D6_PORT143), GPIO_FN(MMC1_D7_PORT142),
1968 GPIO_FN(MMC1_CLK_PORT103),
1969 GPIO_FN(MMC1_CMD_PORT104), /* MSEL4CR_15_1 */
1970
1971 /* MSIOF0 */ 2420 /* MSIOF0 */
1972 GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD), 2421 GPIO_FN(MSIOF0_SS1), GPIO_FN(MSIOF0_SS2), GPIO_FN(MSIOF0_RXD),
1973 GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1), 2422 GPIO_FN(MSIOF0_TXD), GPIO_FN(MSIOF0_MCK0), GPIO_FN(MSIOF0_MCK1),
@@ -2126,7 +2575,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
2126 GPIO_FN(TRACEAUD_FROM_MEMC), 2575 GPIO_FN(TRACEAUD_FROM_MEMC),
2127}; 2576};
2128 2577
2129static struct pinmux_cfg_reg pinmux_config_regs[] = { 2578static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2130 PORTCR(0, 0xe6050000), /* PORT0CR */ 2579 PORTCR(0, 0xe6050000), /* PORT0CR */
2131 PORTCR(1, 0xe6050001), /* PORT1CR */ 2580 PORTCR(1, 0xe6050001), /* PORT1CR */
2132 PORTCR(2, 0xe6050002), /* PORT2CR */ 2581 PORTCR(2, 0xe6050002), /* PORT2CR */
@@ -2440,7 +2889,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2440 { }, 2889 { },
2441}; 2890};
2442 2891
2443static struct pinmux_data_reg pinmux_data_regs[] = { 2892static const struct pinmux_data_reg pinmux_data_regs[] = {
2444 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) { 2893 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
2445 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, 2894 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2446 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, 2895 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
@@ -2544,7 +2993,7 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2544 { }, 2993 { },
2545}; 2994};
2546 2995
2547static struct pinmux_irq pinmux_irqs[] = { 2996static const struct pinmux_irq pinmux_irqs[] = {
2548 PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */ 2997 PINMUX_IRQ(irq_pin(0), GPIO_PORT2, GPIO_PORT13), /* IRQ0A */
2549 PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */ 2998 PINMUX_IRQ(irq_pin(1), GPIO_PORT20), /* IRQ1A */
2550 PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */ 2999 PINMUX_IRQ(irq_pin(2), GPIO_PORT11, GPIO_PORT12), /* IRQ2A */
@@ -2579,11 +3028,8 @@ static struct pinmux_irq pinmux_irqs[] = {
2579 PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */ 3028 PINMUX_IRQ(irq_pin(31), GPIO_PORT41, GPIO_PORT167),/* IRQ31A */
2580}; 3029};
2581 3030
2582struct sh_pfc_soc_info r8a7740_pinmux_info = { 3031const struct sh_pfc_soc_info r8a7740_pinmux_info = {
2583 .name = "r8a7740_pfc", 3032 .name = "r8a7740_pfc",
2584 .reserved_id = PINMUX_RESERVED,
2585 .data = { PINMUX_DATA_BEGIN,
2586 PINMUX_DATA_END },
2587 .input = { PINMUX_INPUT_BEGIN, 3033 .input = { PINMUX_INPUT_BEGIN,
2588 PINMUX_INPUT_END }, 3034 PINMUX_INPUT_END },
2589 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, 3035 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
@@ -2592,15 +3038,19 @@ struct sh_pfc_soc_info r8a7740_pinmux_info = {
2592 PINMUX_INPUT_PULLDOWN_END }, 3038 PINMUX_INPUT_PULLDOWN_END },
2593 .output = { PINMUX_OUTPUT_BEGIN, 3039 .output = { PINMUX_OUTPUT_BEGIN,
2594 PINMUX_OUTPUT_END }, 3040 PINMUX_OUTPUT_END },
2595 .mark = { PINMUX_MARK_BEGIN,
2596 PINMUX_MARK_END },
2597 .function = { PINMUX_FUNCTION_BEGIN, 3041 .function = { PINMUX_FUNCTION_BEGIN,
2598 PINMUX_FUNCTION_END }, 3042 PINMUX_FUNCTION_END },
2599 3043
2600 .first_gpio = GPIO_PORT0, 3044 .pins = pinmux_pins,
2601 .last_gpio = GPIO_FN_TRACEAUD_FROM_MEMC, 3045 .nr_pins = ARRAY_SIZE(pinmux_pins),
3046 .groups = pinmux_groups,
3047 .nr_groups = ARRAY_SIZE(pinmux_groups),
3048 .functions = pinmux_functions,
3049 .nr_functions = ARRAY_SIZE(pinmux_functions),
3050
3051 .func_gpios = pinmux_func_gpios,
3052 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2602 3053
2603 .gpios = pinmux_gpios,
2604 .cfg_regs = pinmux_config_regs, 3054 .cfg_regs = pinmux_config_regs,
2605 .data_regs = pinmux_data_regs, 3055 .data_regs = pinmux_data_regs,
2606 3056
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 13feaa0c0eb7..62dcdcdec940 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -19,57 +19,77 @@
19 */ 19 */
20 20
21#include <linux/kernel.h> 21#include <linux/kernel.h>
22#include <mach/r8a7779.h>
23 22
24#include "sh_pfc.h" 23#include "sh_pfc.h"
25 24
26#define CPU_32_PORT(fn, pfx, sfx) \ 25#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
27 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ 26
28 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ 27#define PORT_GP_32(bank, fn, sfx) \
29 PORT_1(fn, pfx##31, sfx) 28 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
30 29 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
31#define CPU_32_PORT6(fn, pfx, sfx) \ 30 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
32 PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ 31 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
33 PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ 32 PORT_GP_1(bank, 8, fn, sfx), PORT_GP_1(bank, 9, fn, sfx), \
34 PORT_1(fn, pfx##4, sfx), PORT_1(fn, pfx##5, sfx), \ 33 PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx), \
35 PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ 34 PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx), \
36 PORT_1(fn, pfx##8, sfx) 35 PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx), \
37 36 PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx), \
38#define CPU_ALL_PORT(fn, pfx, sfx) \ 37 PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx), \
39 CPU_32_PORT(fn, pfx##_0_, sfx), \ 38 PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx), \
40 CPU_32_PORT(fn, pfx##_1_, sfx), \ 39 PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx), \
41 CPU_32_PORT(fn, pfx##_2_, sfx), \ 40 PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx), \
42 CPU_32_PORT(fn, pfx##_3_, sfx), \ 41 PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx), \
43 CPU_32_PORT(fn, pfx##_4_, sfx), \ 42 PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx), \
44 CPU_32_PORT(fn, pfx##_5_, sfx), \ 43 PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
45 CPU_32_PORT6(fn, pfx##_6_, sfx) 44
46 45#define PORT_GP_32_9(bank, fn, sfx) \
47#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) 46 PORT_GP_1(bank, 0, fn, sfx), PORT_GP_1(bank, 1, fn, sfx), \
48#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ 47 PORT_GP_1(bank, 2, fn, sfx), PORT_GP_1(bank, 3, fn, sfx), \
49 GP##pfx##_IN, GP##pfx##_OUT) 48 PORT_GP_1(bank, 4, fn, sfx), PORT_GP_1(bank, 5, fn, sfx), \
50 49 PORT_GP_1(bank, 6, fn, sfx), PORT_GP_1(bank, 7, fn, sfx), \
51#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT 50 PORT_GP_1(bank, 8, fn, sfx)
52#define _GP_INDT(pfx, sfx) GP##pfx##_DATA 51
53 52#define PORT_GP_32_REV(bank, fn, sfx) \
54#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) 53 PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
55#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) 54 PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
56#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) 55 PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
57 56 PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
58 57 PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
59#define PORT_10_REV(fn, pfx, sfx) \ 58 PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
60 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ 59 PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
61 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ 60 PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
62 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ 61 PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
63 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ 62 PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
64 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) 63 PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
65 64 PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
66#define CPU_32_PORT_REV(fn, pfx, sfx) \ 65 PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
67 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ 66 PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
68 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ 67 PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
69 PORT_10_REV(fn, pfx, sfx) 68 PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
70 69
71#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) 70#define CPU_ALL_PORT(fn, sfx) \
72#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) 71 PORT_GP_32(0, fn, sfx), \
72 PORT_GP_32(1, fn, sfx), \
73 PORT_GP_32(2, fn, sfx), \
74 PORT_GP_32(3, fn, sfx), \
75 PORT_GP_32(4, fn, sfx), \
76 PORT_GP_32(5, fn, sfx), \
77 PORT_GP_32_9(6, fn, sfx)
78
79#define _GP_PORT_ALL(bank, pin, name, sfx) name##_##sfx
80
81#define _GP_GPIO(bank, pin, _name, sfx) \
82 [(bank * 32) + pin] = { \
83 .name = __stringify(_name), \
84 .enum_id = _name##_DATA, \
85 }
86
87#define _GP_DATA(bank, pin, name, sfx) \
88 PINMUX_DATA(name##_DATA, name##_FN)
89
90#define GP_ALL(str) CPU_ALL_PORT(_GP_PORT_ALL, str)
91#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
92#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
73 93
74#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) 94#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
75#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ 95#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
@@ -82,14 +102,6 @@ enum {
82 GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */ 102 GP_ALL(DATA), /* GP_0_0_DATA -> GP_6_8_DATA */
83 PINMUX_DATA_END, 103 PINMUX_DATA_END,
84 104
85 PINMUX_INPUT_BEGIN,
86 GP_ALL(IN), /* GP_0_0_IN -> GP_6_8_IN */
87 PINMUX_INPUT_END,
88
89 PINMUX_OUTPUT_BEGIN,
90 GP_ALL(OUT), /* GP_0_0_OUT -> GP_6_8_OUT */
91 PINMUX_OUTPUT_END,
92
93 PINMUX_FUNCTION_BEGIN, 105 PINMUX_FUNCTION_BEGIN,
94 GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */ 106 GP_ALL(FN), /* GP_0_0_FN -> GP_6_8_FN */
95 107
@@ -371,7 +383,7 @@ enum {
371 FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS, 383 FN_VI1_DATA6_VI1_B6, FN_SD2_CD, FN_MT0_VCXO, FN_SPA_TMS,
372 FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, 384 FN_HSPI_TX1_D, FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM,
373 FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0, 385 FN_SPA_TDI, FN_HSPI_RX1_D, FN_VI1_G0, FN_VI3_DATA0,
374 FN_DU1_DOTCLKOUT1, FN_TS_SCK1, FN_DREQ2_B, FN_TX2, 386 FN_TS_SCK1, FN_DREQ2_B, FN_TX2,
375 FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1, 387 FN_SPA_TDO, FN_HCTS0_B, FN_VI1_G1, FN_VI3_DATA1,
376 FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B, 388 FN_SSI_SCK1, FN_TS_SDEN1, FN_DACK2_B, FN_RX2, FN_HRTS0_B,
377 389
@@ -447,7 +459,8 @@ enum {
447 A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK, 459 A0_MARK, SD1_DAT3_MARK, MMC0_D3_MARK, FD3_MARK,
448 BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK, 460 BS_MARK, SD1_DAT2_MARK, MMC0_D2_MARK, FD2_MARK,
449 ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK, 461 ATADIR0_MARK, SDSELF_MARK, HCTS1_MARK, TX4_C_MARK,
450 USB_PENC2_MARK, SCK0_MARK, PWM1_MARK, PWMFSW0_MARK, 462 USB_PENC0_MARK, USB_PENC1_MARK, USB_PENC2_MARK,
463 SCK0_MARK, PWM1_MARK, PWMFSW0_MARK,
451 SCIF_CLK_MARK, TCLK0_C_MARK, 464 SCIF_CLK_MARK, TCLK0_C_MARK,
452 465
453 EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK, 466 EX_CS0_MARK, RX3_C_IRDA_RX_C_MARK, MMC0_D6_MARK,
@@ -632,7 +645,7 @@ enum {
632 HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK, 645 HSPI_CS1_D_MARK, ADICHS2_B_MARK, VI1_DATA6_VI1_B6_MARK, SD2_CD_MARK,
633 MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK, 646 MT0_VCXO_MARK, SPA_TMS_MARK, HSPI_TX1_D_MARK, VI1_DATA7_VI1_B7_MARK,
634 SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK, 647 SD2_WP_MARK, MT0_PWM_MARK, SPA_TDI_MARK, HSPI_RX1_D_MARK,
635 VI1_G0_MARK, VI3_DATA0_MARK, DU1_DOTCLKOUT1_MARK, TS_SCK1_MARK, 648 VI1_G0_MARK, VI3_DATA0_MARK, TS_SCK1_MARK,
636 DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK, 649 DREQ2_B_MARK, TX2_MARK, SPA_TDO_MARK, HCTS0_B_MARK,
637 VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK, 650 VI1_G1_MARK, VI3_DATA1_MARK, SSI_SCK1_MARK, TS_SDEN1_MARK,
638 DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK, 651 DACK2_B_MARK, RX2_MARK, HRTS0_B_MARK,
@@ -649,7 +662,7 @@ enum {
649 PINMUX_MARK_END, 662 PINMUX_MARK_END,
650}; 663};
651 664
652static pinmux_enum_t pinmux_data[] = { 665static const pinmux_enum_t pinmux_data[] = {
653 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 666 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
654 667
655 PINMUX_DATA(AVS1_MARK, FN_AVS1), 668 PINMUX_DATA(AVS1_MARK, FN_AVS1),
@@ -658,6 +671,9 @@ static pinmux_enum_t pinmux_data[] = {
658 PINMUX_DATA(A18_MARK, FN_A18), 671 PINMUX_DATA(A18_MARK, FN_A18),
659 PINMUX_DATA(A19_MARK, FN_A19), 672 PINMUX_DATA(A19_MARK, FN_A19),
660 673
674 PINMUX_DATA(USB_PENC0_MARK, FN_USB_PENC0),
675 PINMUX_DATA(USB_PENC1_MARK, FN_USB_PENC1),
676
661 PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2), 677 PINMUX_IPSR_DATA(IP0_2_0, USB_PENC2),
662 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0), 678 PINMUX_IPSR_MODSEL_DATA(IP0_2_0, SCK0, SEL_SCIF0_0),
663 PINMUX_IPSR_DATA(IP0_2_0, PWM1), 679 PINMUX_IPSR_DATA(IP0_2_0, PWM1),
@@ -1399,7 +1415,6 @@ static pinmux_enum_t pinmux_data[] = {
1399 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3), 1415 PINMUX_IPSR_MODSEL_DATA(IP11_23_21, HSPI_RX1_D, SEL_HSPI1_3),
1400 PINMUX_IPSR_DATA(IP11_26_24, VI1_G0), 1416 PINMUX_IPSR_DATA(IP11_26_24, VI1_G0),
1401 PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0), 1417 PINMUX_IPSR_DATA(IP11_26_24, VI3_DATA0),
1402 PINMUX_IPSR_DATA(IP11_26_24, DU1_DOTCLKOUT1),
1403 PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1), 1418 PINMUX_IPSR_DATA(IP11_26_24, TS_SCK1),
1404 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1), 1419 PINMUX_IPSR_MODSEL_DATA(IP11_26_24, DREQ2_B, SEL_EXBUS2_1),
1405 PINMUX_IPSR_DATA(IP11_26_24, TX2), 1420 PINMUX_IPSR_DATA(IP11_26_24, TX2),
@@ -1450,280 +1465,1260 @@ static pinmux_enum_t pinmux_data[] = {
1450 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1), 1465 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
1451}; 1466};
1452 1467
1453static struct pinmux_gpio pinmux_gpios[] = { 1468static struct sh_pfc_pin pinmux_pins[] = {
1454 PINMUX_GPIO_GP_ALL(), 1469 PINMUX_GPIO_GP_ALL(),
1455 GPIO_FN(AVS1), GPIO_FN(AVS2), GPIO_FN(A17), GPIO_FN(A18), 1470};
1456 GPIO_FN(A19),
1457 1471
1458 /* IPSR0 */ 1472/* - DU0 -------------------------------------------------------------------- */
1459 GPIO_FN(USB_PENC2), GPIO_FN(SCK0), GPIO_FN(PWM1), GPIO_FN(PWMFSW0), 1473static const unsigned int du0_rgb666_pins[] = {
1460 GPIO_FN(SCIF_CLK), GPIO_FN(TCLK0_C), GPIO_FN(BS), GPIO_FN(SD1_DAT2), 1474 /* R[7:2], G[7:2], B[7:2] */
1461 GPIO_FN(MMC0_D2), GPIO_FN(FD2), GPIO_FN(ATADIR0), GPIO_FN(SDSELF), 1475 188, 187, 186, 185, 184, 183,
1462 GPIO_FN(HCTS1), GPIO_FN(TX4_C), GPIO_FN(A0), GPIO_FN(SD1_DAT3), 1476 194, 193, 192, 191, 190, 189,
1463 GPIO_FN(MMC0_D3), GPIO_FN(FD3), GPIO_FN(A20), GPIO_FN(TX5_D), 1477 200, 199, 198, 197, 196, 195,
1464 GPIO_FN(HSPI_TX2_B), GPIO_FN(A21), GPIO_FN(SCK5_D), 1478};
1465 GPIO_FN(HSPI_CLK2_B), GPIO_FN(A22), GPIO_FN(RX5_D), 1479static const unsigned int du0_rgb666_mux[] = {
1466 GPIO_FN(HSPI_RX2_B), GPIO_FN(VI1_R0), GPIO_FN(A23), GPIO_FN(FCLE), 1480 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1467 GPIO_FN(HSPI_CLK2), GPIO_FN(VI1_R1), GPIO_FN(A24), GPIO_FN(SD1_CD), 1481 DU0_DR3_MARK, DU0_DR2_MARK,
1468 GPIO_FN(MMC0_D4), GPIO_FN(FD4), GPIO_FN(HSPI_CS2), GPIO_FN(VI1_R2), 1482 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1469 GPIO_FN(SSI_WS78_B), GPIO_FN(A25), GPIO_FN(SD1_WP), GPIO_FN(MMC0_D5), 1483 DU0_DG3_MARK, DU0_DG2_MARK,
1470 GPIO_FN(FD5), GPIO_FN(HSPI_RX2), GPIO_FN(VI1_R3), GPIO_FN(TX5_B), 1484 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1471 GPIO_FN(SSI_SDATA7_B), GPIO_FN(CTS0_B), GPIO_FN(CLKOUT), 1485 DU0_DB3_MARK, DU0_DB2_MARK,
1472 GPIO_FN(TX3C_IRDA_TX_C), GPIO_FN(PWM0_B), GPIO_FN(CS0), 1486};
1473 GPIO_FN(HSPI_CS2_B), GPIO_FN(CS1_A26), GPIO_FN(HSPI_TX2), 1487static const unsigned int du0_rgb888_pins[] = {
1474 GPIO_FN(SDSELF_B), GPIO_FN(RD_WR), GPIO_FN(FWE), GPIO_FN(ATAG0), 1488 /* R[7:0], G[7:0], B[7:0] */
1475 GPIO_FN(VI1_R7), GPIO_FN(HRTS1), GPIO_FN(RX4_C), 1489 188, 187, 186, 185, 184, 183, 24, 23,
1490 194, 193, 192, 191, 190, 189, 26, 25,
1491 200, 199, 198, 197, 196, 195, 28, 27,
1492};
1493static const unsigned int du0_rgb888_mux[] = {
1494 DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
1495 DU0_DR3_MARK, DU0_DR2_MARK, DU0_DR1_MARK, DU0_DR0_MARK,
1496 DU0_DG7_MARK, DU0_DG6_MARK, DU0_DG5_MARK, DU0_DG4_MARK,
1497 DU0_DG3_MARK, DU0_DG2_MARK, DU0_DG1_MARK, DU0_DG0_MARK,
1498 DU0_DB7_MARK, DU0_DB6_MARK, DU0_DB5_MARK, DU0_DB4_MARK,
1499 DU0_DB3_MARK, DU0_DB2_MARK, DU0_DB1_MARK, DU0_DB0_MARK,
1500};
1501static const unsigned int du0_clk_in_pins[] = {
1502 /* CLKIN */
1503 29,
1504};
1505static const unsigned int du0_clk_in_mux[] = {
1506 DU0_DOTCLKIN_MARK,
1507};
1508static const unsigned int du0_clk_out_0_pins[] = {
1509 /* CLKOUT */
1510 180,
1511};
1512static const unsigned int du0_clk_out_0_mux[] = {
1513 DU0_DOTCLKOUT0_MARK,
1514};
1515static const unsigned int du0_clk_out_1_pins[] = {
1516 /* CLKOUT */
1517 30,
1518};
1519static const unsigned int du0_clk_out_1_mux[] = {
1520 DU0_DOTCLKOUT1_MARK,
1521};
1522static const unsigned int du0_sync_0_pins[] = {
1523 /* VSYNC, HSYNC, DISP */
1524 182, 181, 31,
1525};
1526static const unsigned int du0_sync_0_mux[] = {
1527 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1528 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1529};
1530static const unsigned int du0_sync_1_pins[] = {
1531 /* VSYNC, HSYNC, DISP */
1532 182, 181, 32,
1533};
1534static const unsigned int du0_sync_1_mux[] = {
1535 DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
1536 DU0_DISP_MARK
1537};
1538static const unsigned int du0_oddf_pins[] = {
1539 /* ODDF */
1540 31,
1541};
1542static const unsigned int du0_oddf_mux[] = {
1543 DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
1544};
1545static const unsigned int du0_cde_pins[] = {
1546 /* CDE */
1547 33,
1548};
1549static const unsigned int du0_cde_mux[] = {
1550 DU0_CDE_MARK
1551};
1552/* - DU1 -------------------------------------------------------------------- */
1553static const unsigned int du1_rgb666_pins[] = {
1554 /* R[7:2], G[7:2], B[7:2] */
1555 41, 40, 39, 38, 37, 36,
1556 49, 48, 47, 46, 45, 44,
1557 57, 56, 55, 54, 53, 52,
1558};
1559static const unsigned int du1_rgb666_mux[] = {
1560 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1561 DU1_DR3_MARK, DU1_DR2_MARK,
1562 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1563 DU1_DG3_MARK, DU1_DG2_MARK,
1564 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1565 DU1_DB3_MARK, DU1_DB2_MARK,
1566};
1567static const unsigned int du1_rgb888_pins[] = {
1568 /* R[7:0], G[7:0], B[7:0] */
1569 41, 40, 39, 38, 37, 36, 35, 34,
1570 49, 48, 47, 46, 45, 44, 43, 32,
1571 57, 56, 55, 54, 53, 52, 51, 50,
1572};
1573static const unsigned int du1_rgb888_mux[] = {
1574 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1575 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1576 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1577 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1578 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1579 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1580};
1581static const unsigned int du1_clk_in_pins[] = {
1582 /* CLKIN */
1583 58,
1584};
1585static const unsigned int du1_clk_in_mux[] = {
1586 DU1_DOTCLKIN_MARK,
1587};
1588static const unsigned int du1_clk_out_pins[] = {
1589 /* CLKOUT */
1590 59,
1591};
1592static const unsigned int du1_clk_out_mux[] = {
1593 DU1_DOTCLKOUT_MARK,
1594};
1595static const unsigned int du1_sync_0_pins[] = {
1596 /* VSYNC, HSYNC, DISP */
1597 61, 60, 62,
1598};
1599static const unsigned int du1_sync_0_mux[] = {
1600 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1601 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1602};
1603static const unsigned int du1_sync_1_pins[] = {
1604 /* VSYNC, HSYNC, DISP */
1605 61, 60, 63,
1606};
1607static const unsigned int du1_sync_1_mux[] = {
1608 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
1609 DU1_DISP_MARK
1610};
1611static const unsigned int du1_oddf_pins[] = {
1612 /* ODDF */
1613 62,
1614};
1615static const unsigned int du1_oddf_mux[] = {
1616 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
1617};
1618static const unsigned int du1_cde_pins[] = {
1619 /* CDE */
1620 64,
1621};
1622static const unsigned int du1_cde_mux[] = {
1623 DU1_CDE_MARK
1624};
1625/* - HSPI0 ------------------------------------------------------------------ */
1626static const unsigned int hspi0_pins[] = {
1627 /* CLK, CS, RX, TX */
1628 150, 151, 153, 152,
1629};
1630static const unsigned int hspi0_mux[] = {
1631 HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
1632};
1633/* - HSPI1 ------------------------------------------------------------------ */
1634static const unsigned int hspi1_pins[] = {
1635 /* CLK, CS, RX, TX */
1636 63, 58, 64, 62,
1637};
1638static const unsigned int hspi1_mux[] = {
1639 HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
1640};
1641static const unsigned int hspi1_b_pins[] = {
1642 /* CLK, CS, RX, TX */
1643 90, 91, 93, 92,
1644};
1645static const unsigned int hspi1_b_mux[] = {
1646 HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
1647};
1648static const unsigned int hspi1_c_pins[] = {
1649 /* CLK, CS, RX, TX */
1650 141, 142, 144, 143,
1651};
1652static const unsigned int hspi1_c_mux[] = {
1653 HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
1654};
1655static const unsigned int hspi1_d_pins[] = {
1656 /* CLK, CS, RX, TX */
1657 101, 102, 104, 103,
1658};
1659static const unsigned int hspi1_d_mux[] = {
1660 HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
1661};
1662/* - HSPI2 ------------------------------------------------------------------ */
1663static const unsigned int hspi2_pins[] = {
1664 /* CLK, CS, RX, TX */
1665 9, 10, 11, 14,
1666};
1667static const unsigned int hspi2_mux[] = {
1668 HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
1669};
1670static const unsigned int hspi2_b_pins[] = {
1671 /* CLK, CS, RX, TX */
1672 7, 13, 8, 6,
1673};
1674static const unsigned int hspi2_b_mux[] = {
1675 HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
1676};
1677/* - INTC ------------------------------------------------------------------- */
1678static const unsigned int intc_irq0_pins[] = {
1679 /* IRQ */
1680 78,
1681};
1682static const unsigned int intc_irq0_mux[] = {
1683 IRQ0_MARK,
1684};
1685static const unsigned int intc_irq0_b_pins[] = {
1686 /* IRQ */
1687 141,
1688};
1689static const unsigned int intc_irq0_b_mux[] = {
1690 IRQ0_B_MARK,
1691};
1692static const unsigned int intc_irq1_pins[] = {
1693 /* IRQ */
1694 79,
1695};
1696static const unsigned int intc_irq1_mux[] = {
1697 IRQ1_MARK,
1698};
1699static const unsigned int intc_irq1_b_pins[] = {
1700 /* IRQ */
1701 142,
1702};
1703static const unsigned int intc_irq1_b_mux[] = {
1704 IRQ1_B_MARK,
1705};
1706static const unsigned int intc_irq2_pins[] = {
1707 /* IRQ */
1708 88,
1709};
1710static const unsigned int intc_irq2_mux[] = {
1711 IRQ2_MARK,
1712};
1713static const unsigned int intc_irq2_b_pins[] = {
1714 /* IRQ */
1715 143,
1716};
1717static const unsigned int intc_irq2_b_mux[] = {
1718 IRQ2_B_MARK,
1719};
1720static const unsigned int intc_irq3_pins[] = {
1721 /* IRQ */
1722 89,
1723};
1724static const unsigned int intc_irq3_mux[] = {
1725 IRQ3_MARK,
1726};
1727static const unsigned int intc_irq3_b_pins[] = {
1728 /* IRQ */
1729 144,
1730};
1731static const unsigned int intc_irq3_b_mux[] = {
1732 IRQ3_B_MARK,
1733};
1734/* - LSBC ------------------------------------------------------------------- */
1735static const unsigned int lbsc_cs0_pins[] = {
1736 /* CS */
1737 13,
1738};
1739static const unsigned int lbsc_cs0_mux[] = {
1740 CS0_MARK,
1741};
1742static const unsigned int lbsc_cs1_pins[] = {
1743 /* CS */
1744 14,
1745};
1746static const unsigned int lbsc_cs1_mux[] = {
1747 CS1_A26_MARK,
1748};
1749static const unsigned int lbsc_ex_cs0_pins[] = {
1750 /* CS */
1751 15,
1752};
1753static const unsigned int lbsc_ex_cs0_mux[] = {
1754 EX_CS0_MARK,
1755};
1756static const unsigned int lbsc_ex_cs1_pins[] = {
1757 /* CS */
1758 16,
1759};
1760static const unsigned int lbsc_ex_cs1_mux[] = {
1761 EX_CS1_MARK,
1762};
1763static const unsigned int lbsc_ex_cs2_pins[] = {
1764 /* CS */
1765 17,
1766};
1767static const unsigned int lbsc_ex_cs2_mux[] = {
1768 EX_CS2_MARK,
1769};
1770static const unsigned int lbsc_ex_cs3_pins[] = {
1771 /* CS */
1772 18,
1773};
1774static const unsigned int lbsc_ex_cs3_mux[] = {
1775 EX_CS3_MARK,
1776};
1777static const unsigned int lbsc_ex_cs4_pins[] = {
1778 /* CS */
1779 19,
1780};
1781static const unsigned int lbsc_ex_cs4_mux[] = {
1782 EX_CS4_MARK,
1783};
1784static const unsigned int lbsc_ex_cs5_pins[] = {
1785 /* CS */
1786 20,
1787};
1788static const unsigned int lbsc_ex_cs5_mux[] = {
1789 EX_CS5_MARK,
1790};
1791/* - MMCIF ------------------------------------------------------------------ */
1792static const unsigned int mmc0_data1_pins[] = {
1793 /* D[0] */
1794 19,
1795};
1796static const unsigned int mmc0_data1_mux[] = {
1797 MMC0_D0_MARK,
1798};
1799static const unsigned int mmc0_data4_pins[] = {
1800 /* D[0:3] */
1801 19, 20, 21, 2,
1802};
1803static const unsigned int mmc0_data4_mux[] = {
1804 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1805};
1806static const unsigned int mmc0_data8_pins[] = {
1807 /* D[0:7] */
1808 19, 20, 21, 2, 10, 11, 15, 16,
1809};
1810static const unsigned int mmc0_data8_mux[] = {
1811 MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
1812 MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
1813};
1814static const unsigned int mmc0_ctrl_pins[] = {
1815 /* CMD, CLK */
1816 18, 17,
1817};
1818static const unsigned int mmc0_ctrl_mux[] = {
1819 MMC0_CMD_MARK, MMC0_CLK_MARK,
1820};
1821static const unsigned int mmc1_data1_pins[] = {
1822 /* D[0] */
1823 72,
1824};
1825static const unsigned int mmc1_data1_mux[] = {
1826 MMC1_D0_MARK,
1827};
1828static const unsigned int mmc1_data4_pins[] = {
1829 /* D[0:3] */
1830 72, 73, 74, 75,
1831};
1832static const unsigned int mmc1_data4_mux[] = {
1833 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1834};
1835static const unsigned int mmc1_data8_pins[] = {
1836 /* D[0:7] */
1837 72, 73, 74, 75, 76, 77, 80, 81,
1838};
1839static const unsigned int mmc1_data8_mux[] = {
1840 MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
1841 MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
1842};
1843static const unsigned int mmc1_ctrl_pins[] = {
1844 /* CMD, CLK */
1845 68, 65,
1846};
1847static const unsigned int mmc1_ctrl_mux[] = {
1848 MMC1_CMD_MARK, MMC1_CLK_MARK,
1849};
1850/* - SCIF0 ------------------------------------------------------------------ */
1851static const unsigned int scif0_data_pins[] = {
1852 /* RXD, TXD */
1853 153, 152,
1854};
1855static const unsigned int scif0_data_mux[] = {
1856 RX0_MARK, TX0_MARK,
1857};
1858static const unsigned int scif0_clk_pins[] = {
1859 /* SCK */
1860 156,
1861};
1862static const unsigned int scif0_clk_mux[] = {
1863 SCK0_MARK,
1864};
1865static const unsigned int scif0_ctrl_pins[] = {
1866 /* RTS, CTS */
1867 151, 150,
1868};
1869static const unsigned int scif0_ctrl_mux[] = {
1870 RTS0_TANS_MARK, CTS0_MARK,
1871};
1872static const unsigned int scif0_data_b_pins[] = {
1873 /* RXD, TXD */
1874 20, 19,
1875};
1876static const unsigned int scif0_data_b_mux[] = {
1877 RX0_B_MARK, TX0_B_MARK,
1878};
1879static const unsigned int scif0_clk_b_pins[] = {
1880 /* SCK */
1881 33,
1882};
1883static const unsigned int scif0_clk_b_mux[] = {
1884 SCK0_B_MARK,
1885};
1886static const unsigned int scif0_ctrl_b_pins[] = {
1887 /* RTS, CTS */
1888 18, 11,
1889};
1890static const unsigned int scif0_ctrl_b_mux[] = {
1891 RTS0_B_TANS_B_MARK, CTS0_B_MARK,
1892};
1893static const unsigned int scif0_data_c_pins[] = {
1894 /* RXD, TXD */
1895 146, 147,
1896};
1897static const unsigned int scif0_data_c_mux[] = {
1898 RX0_C_MARK, TX0_C_MARK,
1899};
1900static const unsigned int scif0_clk_c_pins[] = {
1901 /* SCK */
1902 145,
1903};
1904static const unsigned int scif0_clk_c_mux[] = {
1905 SCK0_C_MARK,
1906};
1907static const unsigned int scif0_ctrl_c_pins[] = {
1908 /* RTS, CTS */
1909 149, 148,
1910};
1911static const unsigned int scif0_ctrl_c_mux[] = {
1912 RTS0_C_TANS_C_MARK, CTS0_C_MARK,
1913};
1914static const unsigned int scif0_data_d_pins[] = {
1915 /* RXD, TXD */
1916 43, 42,
1917};
1918static const unsigned int scif0_data_d_mux[] = {
1919 RX0_D_MARK, TX0_D_MARK,
1920};
1921static const unsigned int scif0_clk_d_pins[] = {
1922 /* SCK */
1923 50,
1924};
1925static const unsigned int scif0_clk_d_mux[] = {
1926 SCK0_D_MARK,
1927};
1928static const unsigned int scif0_ctrl_d_pins[] = {
1929 /* RTS, CTS */
1930 51, 35,
1931};
1932static const unsigned int scif0_ctrl_d_mux[] = {
1933 RTS0_D_TANS_D_MARK, CTS0_D_MARK,
1934};
1935/* - SCIF1 ------------------------------------------------------------------ */
1936static const unsigned int scif1_data_pins[] = {
1937 /* RXD, TXD */
1938 149, 148,
1939};
1940static const unsigned int scif1_data_mux[] = {
1941 RX1_MARK, TX1_MARK,
1942};
1943static const unsigned int scif1_clk_pins[] = {
1944 /* SCK */
1945 145,
1946};
1947static const unsigned int scif1_clk_mux[] = {
1948 SCK1_MARK,
1949};
1950static const unsigned int scif1_ctrl_pins[] = {
1951 /* RTS, CTS */
1952 147, 146,
1953};
1954static const unsigned int scif1_ctrl_mux[] = {
1955 RTS1_TANS_MARK, CTS1_MARK,
1956};
1957static const unsigned int scif1_data_b_pins[] = {
1958 /* RXD, TXD */
1959 117, 114,
1960};
1961static const unsigned int scif1_data_b_mux[] = {
1962 RX1_B_MARK, TX1_B_MARK,
1963};
1964static const unsigned int scif1_clk_b_pins[] = {
1965 /* SCK */
1966 113,
1967};
1968static const unsigned int scif1_clk_b_mux[] = {
1969 SCK1_B_MARK,
1970};
1971static const unsigned int scif1_ctrl_b_pins[] = {
1972 /* RTS, CTS */
1973 115, 116,
1974};
1975static const unsigned int scif1_ctrl_b_mux[] = {
1976 RTS1_B_TANS_B_MARK, CTS1_B_MARK,
1977};
1978static const unsigned int scif1_data_c_pins[] = {
1979 /* RXD, TXD */
1980 67, 66,
1981};
1982static const unsigned int scif1_data_c_mux[] = {
1983 RX1_C_MARK, TX1_C_MARK,
1984};
1985static const unsigned int scif1_clk_c_pins[] = {
1986 /* SCK */
1987 86,
1988};
1989static const unsigned int scif1_clk_c_mux[] = {
1990 SCK1_C_MARK,
1991};
1992static const unsigned int scif1_ctrl_c_pins[] = {
1993 /* RTS, CTS */
1994 69, 68,
1995};
1996static const unsigned int scif1_ctrl_c_mux[] = {
1997 RTS1_C_TANS_C_MARK, CTS1_C_MARK,
1998};
1999/* - SCIF2 ------------------------------------------------------------------ */
2000static const unsigned int scif2_data_pins[] = {
2001 /* RXD, TXD */
2002 106, 105,
2003};
2004static const unsigned int scif2_data_mux[] = {
2005 RX2_MARK, TX2_MARK,
2006};
2007static const unsigned int scif2_clk_pins[] = {
2008 /* SCK */
2009 107,
2010};
2011static const unsigned int scif2_clk_mux[] = {
2012 SCK2_MARK,
2013};
2014static const unsigned int scif2_data_b_pins[] = {
2015 /* RXD, TXD */
2016 120, 119,
2017};
2018static const unsigned int scif2_data_b_mux[] = {
2019 RX2_B_MARK, TX2_B_MARK,
2020};
2021static const unsigned int scif2_clk_b_pins[] = {
2022 /* SCK */
2023 118,
2024};
2025static const unsigned int scif2_clk_b_mux[] = {
2026 SCK2_B_MARK,
2027};
2028static const unsigned int scif2_data_c_pins[] = {
2029 /* RXD, TXD */
2030 33, 31,
2031};
2032static const unsigned int scif2_data_c_mux[] = {
2033 RX2_C_MARK, TX2_C_MARK,
2034};
2035static const unsigned int scif2_clk_c_pins[] = {
2036 /* SCK */
2037 32,
2038};
2039static const unsigned int scif2_clk_c_mux[] = {
2040 SCK2_C_MARK,
2041};
2042static const unsigned int scif2_data_d_pins[] = {
2043 /* RXD, TXD */
2044 64, 62,
2045};
2046static const unsigned int scif2_data_d_mux[] = {
2047 RX2_D_MARK, TX2_D_MARK,
2048};
2049static const unsigned int scif2_clk_d_pins[] = {
2050 /* SCK */
2051 63,
2052};
2053static const unsigned int scif2_clk_d_mux[] = {
2054 SCK2_D_MARK,
2055};
2056static const unsigned int scif2_data_e_pins[] = {
2057 /* RXD, TXD */
2058 20, 19,
2059};
2060static const unsigned int scif2_data_e_mux[] = {
2061 RX2_E_MARK, TX2_E_MARK,
2062};
2063/* - SCIF3 ------------------------------------------------------------------ */
2064static const unsigned int scif3_data_pins[] = {
2065 /* RXD, TXD */
2066 137, 136,
2067};
2068static const unsigned int scif3_data_mux[] = {
2069 RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
2070};
2071static const unsigned int scif3_clk_pins[] = {
2072 /* SCK */
2073 135,
2074};
2075static const unsigned int scif3_clk_mux[] = {
2076 SCK3_MARK,
2077};
1476 2078
1477 /* IPSR1 */ 2079static const unsigned int scif3_data_b_pins[] = {
1478 GPIO_FN(EX_CS0), GPIO_FN(RX3_C_IRDA_RX_C), GPIO_FN(MMC0_D6), 2080 /* RXD, TXD */
1479 GPIO_FN(FD6), GPIO_FN(EX_CS1), GPIO_FN(MMC0_D7), GPIO_FN(FD7), 2081 64, 62,
1480 GPIO_FN(EX_CS2), GPIO_FN(SD1_CLK), GPIO_FN(MMC0_CLK), GPIO_FN(FALE), 2082};
1481 GPIO_FN(ATACS00), GPIO_FN(EX_CS3), GPIO_FN(SD1_CMD), GPIO_FN(MMC0_CMD), 2083static const unsigned int scif3_data_b_mux[] = {
1482 GPIO_FN(FRE), GPIO_FN(ATACS10), GPIO_FN(VI1_R4), GPIO_FN(RX5_B), 2084 RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
1483 GPIO_FN(HSCK1), GPIO_FN(SSI_SDATA8_B), GPIO_FN(RTS0_B_TANS_B), 2085};
1484 GPIO_FN(SSI_SDATA9), GPIO_FN(EX_CS4), GPIO_FN(SD1_DAT0), 2086static const unsigned int scif3_data_c_pins[] = {
1485 GPIO_FN(MMC0_D0), GPIO_FN(FD0), GPIO_FN(ATARD0), GPIO_FN(VI1_R5), 2087 /* RXD, TXD */
1486 GPIO_FN(SCK5_B), GPIO_FN(HTX1), GPIO_FN(TX2_E), GPIO_FN(TX0_B), 2088 15, 12,
1487 GPIO_FN(SSI_SCK9), GPIO_FN(EX_CS5), GPIO_FN(SD1_DAT1), 2089};
1488 GPIO_FN(MMC0_D1), GPIO_FN(FD1), GPIO_FN(ATAWR0), GPIO_FN(VI1_R6), 2090static const unsigned int scif3_data_c_mux[] = {
1489 GPIO_FN(HRX1), GPIO_FN(RX2_E), GPIO_FN(RX0_B), GPIO_FN(SSI_WS9), 2091 RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
1490 GPIO_FN(MLB_CLK), GPIO_FN(PWM2), GPIO_FN(SCK4), GPIO_FN(MLB_SIG), 2092};
1491 GPIO_FN(PWM3), GPIO_FN(TX4), GPIO_FN(MLB_DAT), GPIO_FN(PWM4), 2093static const unsigned int scif3_data_d_pins[] = {
1492 GPIO_FN(RX4), GPIO_FN(HTX0), GPIO_FN(TX1), GPIO_FN(SDATA), 2094 /* RXD, TXD */
1493 GPIO_FN(CTS0_C), GPIO_FN(SUB_TCK), GPIO_FN(CC5_STATE2), 2095 30, 29,
1494 GPIO_FN(CC5_STATE10), GPIO_FN(CC5_STATE18), GPIO_FN(CC5_STATE26), 2096};
1495 GPIO_FN(CC5_STATE34), 2097static const unsigned int scif3_data_d_mux[] = {
2098 RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
2099};
2100static const unsigned int scif3_data_e_pins[] = {
2101 /* RXD, TXD */
2102 35, 34,
2103};
2104static const unsigned int scif3_data_e_mux[] = {
2105 RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
2106};
2107static const unsigned int scif3_clk_e_pins[] = {
2108 /* SCK */
2109 42,
2110};
2111static const unsigned int scif3_clk_e_mux[] = {
2112 SCK3_E_MARK,
2113};
2114/* - SCIF4 ------------------------------------------------------------------ */
2115static const unsigned int scif4_data_pins[] = {
2116 /* RXD, TXD */
2117 123, 122,
2118};
2119static const unsigned int scif4_data_mux[] = {
2120 RX4_MARK, TX4_MARK,
2121};
2122static const unsigned int scif4_clk_pins[] = {
2123 /* SCK */
2124 121,
2125};
2126static const unsigned int scif4_clk_mux[] = {
2127 SCK4_MARK,
2128};
2129static const unsigned int scif4_data_b_pins[] = {
2130 /* RXD, TXD */
2131 111, 110,
2132};
2133static const unsigned int scif4_data_b_mux[] = {
2134 RX4_B_MARK, TX4_B_MARK,
2135};
2136static const unsigned int scif4_clk_b_pins[] = {
2137 /* SCK */
2138 112,
2139};
2140static const unsigned int scif4_clk_b_mux[] = {
2141 SCK4_B_MARK,
2142};
2143static const unsigned int scif4_data_c_pins[] = {
2144 /* RXD, TXD */
2145 22, 21,
2146};
2147static const unsigned int scif4_data_c_mux[] = {
2148 RX4_C_MARK, TX4_C_MARK,
2149};
2150static const unsigned int scif4_data_d_pins[] = {
2151 /* RXD, TXD */
2152 69, 68,
2153};
2154static const unsigned int scif4_data_d_mux[] = {
2155 RX4_D_MARK, TX4_D_MARK,
2156};
2157/* - SCIF5 ------------------------------------------------------------------ */
2158static const unsigned int scif5_data_pins[] = {
2159 /* RXD, TXD */
2160 51, 50,
2161};
2162static const unsigned int scif5_data_mux[] = {
2163 RX5_MARK, TX5_MARK,
2164};
2165static const unsigned int scif5_clk_pins[] = {
2166 /* SCK */
2167 43,
2168};
2169static const unsigned int scif5_clk_mux[] = {
2170 SCK5_MARK,
2171};
2172static const unsigned int scif5_data_b_pins[] = {
2173 /* RXD, TXD */
2174 18, 11,
2175};
2176static const unsigned int scif5_data_b_mux[] = {
2177 RX5_B_MARK, TX5_B_MARK,
2178};
2179static const unsigned int scif5_clk_b_pins[] = {
2180 /* SCK */
2181 19,
2182};
2183static const unsigned int scif5_clk_b_mux[] = {
2184 SCK5_B_MARK,
2185};
2186static const unsigned int scif5_data_c_pins[] = {
2187 /* RXD, TXD */
2188 24, 23,
2189};
2190static const unsigned int scif5_data_c_mux[] = {
2191 RX5_C_MARK, TX5_C_MARK,
2192};
2193static const unsigned int scif5_clk_c_pins[] = {
2194 /* SCK */
2195 28,
2196};
2197static const unsigned int scif5_clk_c_mux[] = {
2198 SCK5_C_MARK,
2199};
2200static const unsigned int scif5_data_d_pins[] = {
2201 /* RXD, TXD */
2202 8, 6,
2203};
2204static const unsigned int scif5_data_d_mux[] = {
2205 RX5_D_MARK, TX5_D_MARK,
2206};
2207static const unsigned int scif5_clk_d_pins[] = {
2208 /* SCK */
2209 7,
2210};
2211static const unsigned int scif5_clk_d_mux[] = {
2212 SCK5_D_MARK,
2213};
2214/* - SDHI0 ------------------------------------------------------------------ */
2215static const unsigned int sdhi0_data1_pins[] = {
2216 /* D0 */
2217 117,
2218};
2219static const unsigned int sdhi0_data1_mux[] = {
2220 SD0_DAT0_MARK,
2221};
2222static const unsigned int sdhi0_data4_pins[] = {
2223 /* D[0:3] */
2224 117, 118, 119, 120,
2225};
2226static const unsigned int sdhi0_data4_mux[] = {
2227 SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
2228};
2229static const unsigned int sdhi0_ctrl_pins[] = {
2230 /* CMD, CLK */
2231 114, 113,
2232};
2233static const unsigned int sdhi0_ctrl_mux[] = {
2234 SD0_CMD_MARK, SD0_CLK_MARK,
2235};
2236static const unsigned int sdhi0_cd_pins[] = {
2237 /* CD */
2238 115,
2239};
2240static const unsigned int sdhi0_cd_mux[] = {
2241 SD0_CD_MARK,
2242};
2243static const unsigned int sdhi0_wp_pins[] = {
2244 /* WP */
2245 116,
2246};
2247static const unsigned int sdhi0_wp_mux[] = {
2248 SD0_WP_MARK,
2249};
2250/* - SDHI1 ------------------------------------------------------------------ */
2251static const unsigned int sdhi1_data1_pins[] = {
2252 /* D0 */
2253 19,
2254};
2255static const unsigned int sdhi1_data1_mux[] = {
2256 SD1_DAT0_MARK,
2257};
2258static const unsigned int sdhi1_data4_pins[] = {
2259 /* D[0:3] */
2260 19, 20, 21, 2,
2261};
2262static const unsigned int sdhi1_data4_mux[] = {
2263 SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
2264};
2265static const unsigned int sdhi1_ctrl_pins[] = {
2266 /* CMD, CLK */
2267 18, 17,
2268};
2269static const unsigned int sdhi1_ctrl_mux[] = {
2270 SD1_CMD_MARK, SD1_CLK_MARK,
2271};
2272static const unsigned int sdhi1_cd_pins[] = {
2273 /* CD */
2274 10,
2275};
2276static const unsigned int sdhi1_cd_mux[] = {
2277 SD1_CD_MARK,
2278};
2279static const unsigned int sdhi1_wp_pins[] = {
2280 /* WP */
2281 11,
2282};
2283static const unsigned int sdhi1_wp_mux[] = {
2284 SD1_WP_MARK,
2285};
2286/* - SDHI2 ------------------------------------------------------------------ */
2287static const unsigned int sdhi2_data1_pins[] = {
2288 /* D0 */
2289 97,
2290};
2291static const unsigned int sdhi2_data1_mux[] = {
2292 SD2_DAT0_MARK,
2293};
2294static const unsigned int sdhi2_data4_pins[] = {
2295 /* D[0:3] */
2296 97, 98, 99, 100,
2297};
2298static const unsigned int sdhi2_data4_mux[] = {
2299 SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
2300};
2301static const unsigned int sdhi2_ctrl_pins[] = {
2302 /* CMD, CLK */
2303 102, 101,
2304};
2305static const unsigned int sdhi2_ctrl_mux[] = {
2306 SD2_CMD_MARK, SD2_CLK_MARK,
2307};
2308static const unsigned int sdhi2_cd_pins[] = {
2309 /* CD */
2310 103,
2311};
2312static const unsigned int sdhi2_cd_mux[] = {
2313 SD2_CD_MARK,
2314};
2315static const unsigned int sdhi2_wp_pins[] = {
2316 /* WP */
2317 104,
2318};
2319static const unsigned int sdhi2_wp_mux[] = {
2320 SD2_WP_MARK,
2321};
2322/* - SDHI3 ------------------------------------------------------------------ */
2323static const unsigned int sdhi3_data1_pins[] = {
2324 /* D0 */
2325 50,
2326};
2327static const unsigned int sdhi3_data1_mux[] = {
2328 SD3_DAT0_MARK,
2329};
2330static const unsigned int sdhi3_data4_pins[] = {
2331 /* D[0:3] */
2332 50, 51, 52, 53,
2333};
2334static const unsigned int sdhi3_data4_mux[] = {
2335 SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
2336};
2337static const unsigned int sdhi3_ctrl_pins[] = {
2338 /* CMD, CLK */
2339 35, 34,
2340};
2341static const unsigned int sdhi3_ctrl_mux[] = {
2342 SD3_CMD_MARK, SD3_CLK_MARK,
2343};
2344static const unsigned int sdhi3_cd_pins[] = {
2345 /* CD */
2346 62,
2347};
2348static const unsigned int sdhi3_cd_mux[] = {
2349 SD3_CD_MARK,
2350};
2351static const unsigned int sdhi3_wp_pins[] = {
2352 /* WP */
2353 64,
2354};
2355static const unsigned int sdhi3_wp_mux[] = {
2356 SD3_WP_MARK,
2357};
2358/* - USB0 ------------------------------------------------------------------- */
2359static const unsigned int usb0_pins[] = {
2360 /* OVC */
2361 150, 154,
2362};
2363static const unsigned int usb0_mux[] = {
2364 USB_OVC0_MARK, USB_PENC0_MARK,
2365};
2366/* - USB1 ------------------------------------------------------------------- */
2367static const unsigned int usb1_pins[] = {
2368 /* OVC */
2369 152, 155,
2370};
2371static const unsigned int usb1_mux[] = {
2372 USB_OVC1_MARK, USB_PENC1_MARK,
2373};
2374/* - USB2 ------------------------------------------------------------------- */
2375static const unsigned int usb2_pins[] = {
2376 /* OVC, PENC */
2377 125, 156,
2378};
2379static const unsigned int usb2_mux[] = {
2380 USB_OVC2_MARK, USB_PENC2_MARK,
2381};
1496 2382
1497 /* IPSR2 */ 2383static const struct sh_pfc_pin_group pinmux_groups[] = {
1498 GPIO_FN(HRX0), GPIO_FN(RX1), GPIO_FN(SCKZ), GPIO_FN(RTS0_C_TANS_C), 2384 SH_PFC_PIN_GROUP(du0_rgb666),
1499 GPIO_FN(SUB_TDI), GPIO_FN(CC5_STATE3), GPIO_FN(CC5_STATE11), 2385 SH_PFC_PIN_GROUP(du0_rgb888),
1500 GPIO_FN(CC5_STATE19), GPIO_FN(CC5_STATE27), GPIO_FN(CC5_STATE35), 2386 SH_PFC_PIN_GROUP(du0_clk_in),
1501 GPIO_FN(HSCK0), GPIO_FN(SCK1), GPIO_FN(MTS), GPIO_FN(PWM5), 2387 SH_PFC_PIN_GROUP(du0_clk_out_0),
1502 GPIO_FN(SCK0_C), GPIO_FN(SSI_SDATA9_B), GPIO_FN(SUB_TDO), 2388 SH_PFC_PIN_GROUP(du0_clk_out_1),
1503 GPIO_FN(CC5_STATE0), GPIO_FN(CC5_STATE8), GPIO_FN(CC5_STATE16), 2389 SH_PFC_PIN_GROUP(du0_sync_0),
1504 GPIO_FN(CC5_STATE24), GPIO_FN(CC5_STATE32), GPIO_FN(HCTS0), 2390 SH_PFC_PIN_GROUP(du0_sync_1),
1505 GPIO_FN(CTS1), GPIO_FN(STM), GPIO_FN(PWM0_D), GPIO_FN(RX0_C), 2391 SH_PFC_PIN_GROUP(du0_oddf),
1506 GPIO_FN(SCIF_CLK_C), GPIO_FN(SUB_TRST), GPIO_FN(TCLK1_B), 2392 SH_PFC_PIN_GROUP(du0_cde),
1507 GPIO_FN(CC5_OSCOUT), GPIO_FN(HRTS0), GPIO_FN(RTS1_TANS), 2393 SH_PFC_PIN_GROUP(du1_rgb666),
1508 GPIO_FN(MDATA), GPIO_FN(TX0_C), GPIO_FN(SUB_TMS), GPIO_FN(CC5_STATE1), 2394 SH_PFC_PIN_GROUP(du1_rgb888),
1509 GPIO_FN(CC5_STATE9), GPIO_FN(CC5_STATE17), GPIO_FN(CC5_STATE25), 2395 SH_PFC_PIN_GROUP(du1_clk_in),
1510 GPIO_FN(CC5_STATE33), GPIO_FN(DU0_DR0), GPIO_FN(LCDOUT0), 2396 SH_PFC_PIN_GROUP(du1_clk_out),
1511 GPIO_FN(DREQ0), GPIO_FN(GPS_CLK_B), GPIO_FN(AUDATA0), 2397 SH_PFC_PIN_GROUP(du1_sync_0),
1512 GPIO_FN(TX5_C), GPIO_FN(DU0_DR1), GPIO_FN(LCDOUT1), GPIO_FN(DACK0), 2398 SH_PFC_PIN_GROUP(du1_sync_1),
1513 GPIO_FN(DRACK0), GPIO_FN(GPS_SIGN_B), GPIO_FN(AUDATA1), GPIO_FN(RX5_C), 2399 SH_PFC_PIN_GROUP(du1_oddf),
1514 GPIO_FN(DU0_DR2), GPIO_FN(LCDOUT2), GPIO_FN(DU0_DR3), GPIO_FN(LCDOUT3), 2400 SH_PFC_PIN_GROUP(du1_cde),
1515 GPIO_FN(DU0_DR4), GPIO_FN(LCDOUT4), GPIO_FN(DU0_DR5), GPIO_FN(LCDOUT5), 2401 SH_PFC_PIN_GROUP(hspi0),
1516 GPIO_FN(DU0_DR6), GPIO_FN(LCDOUT6), GPIO_FN(DU0_DR7), GPIO_FN(LCDOUT7), 2402 SH_PFC_PIN_GROUP(hspi1),
1517 GPIO_FN(DU0_DG0), GPIO_FN(LCDOUT8), GPIO_FN(DREQ1), GPIO_FN(SCL2), 2403 SH_PFC_PIN_GROUP(hspi1_b),
1518 GPIO_FN(AUDATA2), 2404 SH_PFC_PIN_GROUP(hspi1_c),
2405 SH_PFC_PIN_GROUP(hspi1_d),
2406 SH_PFC_PIN_GROUP(hspi2),
2407 SH_PFC_PIN_GROUP(hspi2_b),
2408 SH_PFC_PIN_GROUP(intc_irq0),
2409 SH_PFC_PIN_GROUP(intc_irq0_b),
2410 SH_PFC_PIN_GROUP(intc_irq1),
2411 SH_PFC_PIN_GROUP(intc_irq1_b),
2412 SH_PFC_PIN_GROUP(intc_irq2),
2413 SH_PFC_PIN_GROUP(intc_irq2_b),
2414 SH_PFC_PIN_GROUP(intc_irq3),
2415 SH_PFC_PIN_GROUP(intc_irq3_b),
2416 SH_PFC_PIN_GROUP(lbsc_cs0),
2417 SH_PFC_PIN_GROUP(lbsc_cs1),
2418 SH_PFC_PIN_GROUP(lbsc_ex_cs0),
2419 SH_PFC_PIN_GROUP(lbsc_ex_cs1),
2420 SH_PFC_PIN_GROUP(lbsc_ex_cs2),
2421 SH_PFC_PIN_GROUP(lbsc_ex_cs3),
2422 SH_PFC_PIN_GROUP(lbsc_ex_cs4),
2423 SH_PFC_PIN_GROUP(lbsc_ex_cs5),
2424 SH_PFC_PIN_GROUP(mmc0_data1),
2425 SH_PFC_PIN_GROUP(mmc0_data4),
2426 SH_PFC_PIN_GROUP(mmc0_data8),
2427 SH_PFC_PIN_GROUP(mmc0_ctrl),
2428 SH_PFC_PIN_GROUP(mmc1_data1),
2429 SH_PFC_PIN_GROUP(mmc1_data4),
2430 SH_PFC_PIN_GROUP(mmc1_data8),
2431 SH_PFC_PIN_GROUP(mmc1_ctrl),
2432 SH_PFC_PIN_GROUP(scif0_data),
2433 SH_PFC_PIN_GROUP(scif0_clk),
2434 SH_PFC_PIN_GROUP(scif0_ctrl),
2435 SH_PFC_PIN_GROUP(scif0_data_b),
2436 SH_PFC_PIN_GROUP(scif0_clk_b),
2437 SH_PFC_PIN_GROUP(scif0_ctrl_b),
2438 SH_PFC_PIN_GROUP(scif0_data_c),
2439 SH_PFC_PIN_GROUP(scif0_clk_c),
2440 SH_PFC_PIN_GROUP(scif0_ctrl_c),
2441 SH_PFC_PIN_GROUP(scif0_data_d),
2442 SH_PFC_PIN_GROUP(scif0_clk_d),
2443 SH_PFC_PIN_GROUP(scif0_ctrl_d),
2444 SH_PFC_PIN_GROUP(scif1_data),
2445 SH_PFC_PIN_GROUP(scif1_clk),
2446 SH_PFC_PIN_GROUP(scif1_ctrl),
2447 SH_PFC_PIN_GROUP(scif1_data_b),
2448 SH_PFC_PIN_GROUP(scif1_clk_b),
2449 SH_PFC_PIN_GROUP(scif1_ctrl_b),
2450 SH_PFC_PIN_GROUP(scif1_data_c),
2451 SH_PFC_PIN_GROUP(scif1_clk_c),
2452 SH_PFC_PIN_GROUP(scif1_ctrl_c),
2453 SH_PFC_PIN_GROUP(scif2_data),
2454 SH_PFC_PIN_GROUP(scif2_clk),
2455 SH_PFC_PIN_GROUP(scif2_data_b),
2456 SH_PFC_PIN_GROUP(scif2_clk_b),
2457 SH_PFC_PIN_GROUP(scif2_data_c),
2458 SH_PFC_PIN_GROUP(scif2_clk_c),
2459 SH_PFC_PIN_GROUP(scif2_data_d),
2460 SH_PFC_PIN_GROUP(scif2_clk_d),
2461 SH_PFC_PIN_GROUP(scif2_data_e),
2462 SH_PFC_PIN_GROUP(scif3_data),
2463 SH_PFC_PIN_GROUP(scif3_clk),
2464 SH_PFC_PIN_GROUP(scif3_data_b),
2465 SH_PFC_PIN_GROUP(scif3_data_c),
2466 SH_PFC_PIN_GROUP(scif3_data_d),
2467 SH_PFC_PIN_GROUP(scif3_data_e),
2468 SH_PFC_PIN_GROUP(scif3_clk_e),
2469 SH_PFC_PIN_GROUP(scif4_data),
2470 SH_PFC_PIN_GROUP(scif4_clk),
2471 SH_PFC_PIN_GROUP(scif4_data_b),
2472 SH_PFC_PIN_GROUP(scif4_clk_b),
2473 SH_PFC_PIN_GROUP(scif4_data_c),
2474 SH_PFC_PIN_GROUP(scif4_data_d),
2475 SH_PFC_PIN_GROUP(scif5_data),
2476 SH_PFC_PIN_GROUP(scif5_clk),
2477 SH_PFC_PIN_GROUP(scif5_data_b),
2478 SH_PFC_PIN_GROUP(scif5_clk_b),
2479 SH_PFC_PIN_GROUP(scif5_data_c),
2480 SH_PFC_PIN_GROUP(scif5_clk_c),
2481 SH_PFC_PIN_GROUP(scif5_data_d),
2482 SH_PFC_PIN_GROUP(scif5_clk_d),
2483 SH_PFC_PIN_GROUP(sdhi0_data1),
2484 SH_PFC_PIN_GROUP(sdhi0_data4),
2485 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2486 SH_PFC_PIN_GROUP(sdhi0_cd),
2487 SH_PFC_PIN_GROUP(sdhi0_wp),
2488 SH_PFC_PIN_GROUP(sdhi1_data1),
2489 SH_PFC_PIN_GROUP(sdhi1_data4),
2490 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2491 SH_PFC_PIN_GROUP(sdhi1_cd),
2492 SH_PFC_PIN_GROUP(sdhi1_wp),
2493 SH_PFC_PIN_GROUP(sdhi2_data1),
2494 SH_PFC_PIN_GROUP(sdhi2_data4),
2495 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2496 SH_PFC_PIN_GROUP(sdhi2_cd),
2497 SH_PFC_PIN_GROUP(sdhi2_wp),
2498 SH_PFC_PIN_GROUP(sdhi3_data1),
2499 SH_PFC_PIN_GROUP(sdhi3_data4),
2500 SH_PFC_PIN_GROUP(sdhi3_ctrl),
2501 SH_PFC_PIN_GROUP(sdhi3_cd),
2502 SH_PFC_PIN_GROUP(sdhi3_wp),
2503 SH_PFC_PIN_GROUP(usb0),
2504 SH_PFC_PIN_GROUP(usb1),
2505 SH_PFC_PIN_GROUP(usb2),
2506};
1519 2507
1520 /* IPSR3 */ 2508static const char * const du0_groups[] = {
1521 GPIO_FN(DU0_DG1), GPIO_FN(LCDOUT9), GPIO_FN(DACK1), GPIO_FN(SDA2), 2509 "du0_rgb666",
1522 GPIO_FN(AUDATA3), GPIO_FN(DU0_DG2), GPIO_FN(LCDOUT10), 2510 "du0_rgb888",
1523 GPIO_FN(DU0_DG3), GPIO_FN(LCDOUT11), GPIO_FN(DU0_DG4), 2511 "du0_clk_in",
1524 GPIO_FN(LCDOUT12), GPIO_FN(DU0_DG5), GPIO_FN(LCDOUT13), 2512 "du0_clk_out_0",
1525 GPIO_FN(DU0_DG6), GPIO_FN(LCDOUT14), GPIO_FN(DU0_DG7), 2513 "du0_clk_out_1",
1526 GPIO_FN(LCDOUT15), GPIO_FN(DU0_DB0), GPIO_FN(LCDOUT16), 2514 "du0_sync_0",
1527 GPIO_FN(EX_WAIT1), GPIO_FN(SCL1), GPIO_FN(TCLK1), GPIO_FN(AUDATA4), 2515 "du0_sync_1",
1528 GPIO_FN(DU0_DB1), GPIO_FN(LCDOUT17), GPIO_FN(EX_WAIT2), GPIO_FN(SDA1), 2516 "du0_oddf",
1529 GPIO_FN(GPS_MAG_B), GPIO_FN(AUDATA5), GPIO_FN(SCK5_C), 2517 "du0_cde",
1530 GPIO_FN(DU0_DB2), GPIO_FN(LCDOUT18), GPIO_FN(DU0_DB3), 2518};
1531 GPIO_FN(LCDOUT19), GPIO_FN(DU0_DB4), GPIO_FN(LCDOUT20),
1532 GPIO_FN(DU0_DB5), GPIO_FN(LCDOUT21), GPIO_FN(DU0_DB6),
1533 GPIO_FN(LCDOUT22), GPIO_FN(DU0_DB7), GPIO_FN(LCDOUT23),
1534 GPIO_FN(DU0_DOTCLKIN), GPIO_FN(QSTVA_QVS), GPIO_FN(TX3_D_IRDA_TX_D),
1535 GPIO_FN(SCL3_B), GPIO_FN(DU0_DOTCLKOUT0), GPIO_FN(QCLK),
1536 GPIO_FN(DU0_DOTCLKOUT1), GPIO_FN(QSTVB_QVE), GPIO_FN(RX3_D_IRDA_RX_D),
1537 GPIO_FN(SDA3_B), GPIO_FN(SDA2_C), GPIO_FN(DACK0_B), GPIO_FN(DRACK0_B),
1538 GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(QSTH_QHS),
1539 GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE),
1540 GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), GPIO_FN(QCPV_QDE),
1541 GPIO_FN(CAN1_TX), GPIO_FN(TX2_C), GPIO_FN(SCL2_C), GPIO_FN(REMOCON),
1542 2519
1543 /* IPSR4 */ 2520static const char * const du1_groups[] = {
1544 GPIO_FN(DU0_DISP), GPIO_FN(QPOLA), GPIO_FN(CAN_CLK_C), GPIO_FN(SCK2_C), 2521 "du1_rgb666",
1545 GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), GPIO_FN(CAN1_RX), GPIO_FN(RX2_C), 2522 "du1_rgb888",
1546 GPIO_FN(DREQ0_B), GPIO_FN(SSI_SCK78_B), GPIO_FN(SCK0_B), 2523 "du1_clk_in",
1547 GPIO_FN(DU1_DR0), GPIO_FN(VI2_DATA0_VI2_B0), GPIO_FN(PWM6), 2524 "du1_clk_out",
1548 GPIO_FN(SD3_CLK), GPIO_FN(TX3_E_IRDA_TX_E), GPIO_FN(AUDCK), 2525 "du1_sync_0",
1549 GPIO_FN(PWMFSW0_B), GPIO_FN(DU1_DR1), GPIO_FN(VI2_DATA1_VI2_B1), 2526 "du1_sync_1",
1550 GPIO_FN(PWM0), GPIO_FN(SD3_CMD), GPIO_FN(RX3_E_IRDA_RX_E), 2527 "du1_oddf",
1551 GPIO_FN(AUDSYNC), GPIO_FN(CTS0_D), GPIO_FN(DU1_DR2), GPIO_FN(VI2_G0), 2528 "du1_cde",
1552 GPIO_FN(DU1_DR3), GPIO_FN(VI2_G1), GPIO_FN(DU1_DR4), GPIO_FN(VI2_G2), 2529};
1553 GPIO_FN(DU1_DR5), GPIO_FN(VI2_G3), GPIO_FN(DU1_DR6), GPIO_FN(VI2_G4),
1554 GPIO_FN(DU1_DR7), GPIO_FN(VI2_G5), GPIO_FN(DU1_DG0),
1555 GPIO_FN(VI2_DATA2_VI2_B2), GPIO_FN(SCL1_B), GPIO_FN(SD3_DAT2),
1556 GPIO_FN(SCK3_E), GPIO_FN(AUDATA6), GPIO_FN(TX0_D), GPIO_FN(DU1_DG1),
1557 GPIO_FN(VI2_DATA3_VI2_B3), GPIO_FN(SDA1_B), GPIO_FN(SD3_DAT3),
1558 GPIO_FN(SCK5), GPIO_FN(AUDATA7), GPIO_FN(RX0_D), GPIO_FN(DU1_DG2),
1559 GPIO_FN(VI2_G6), GPIO_FN(DU1_DG3), GPIO_FN(VI2_G7), GPIO_FN(DU1_DG4),
1560 GPIO_FN(VI2_R0), GPIO_FN(DU1_DG5), GPIO_FN(VI2_R1), GPIO_FN(DU1_DG6),
1561 GPIO_FN(VI2_R2), GPIO_FN(DU1_DG7), GPIO_FN(VI2_R3), GPIO_FN(DU1_DB0),
1562 GPIO_FN(VI2_DATA4_VI2_B4), GPIO_FN(SCL2_B), GPIO_FN(SD3_DAT0),
1563 GPIO_FN(TX5), GPIO_FN(SCK0_D),
1564 2530
1565 /* IPSR5 */ 2531static const char * const hspi0_groups[] = {
1566 GPIO_FN(DU1_DB1), GPIO_FN(VI2_DATA5_VI2_B5), GPIO_FN(SDA2_B), 2532 "hspi0",
1567 GPIO_FN(SD3_DAT1), GPIO_FN(RX5), GPIO_FN(RTS0_D_TANS_D), 2533};
1568 GPIO_FN(DU1_DB2), GPIO_FN(VI2_R4), GPIO_FN(DU1_DB3), GPIO_FN(VI2_R5),
1569 GPIO_FN(DU1_DB4), GPIO_FN(VI2_R6), GPIO_FN(DU1_DB5), GPIO_FN(VI2_R7),
1570 GPIO_FN(DU1_DB6), GPIO_FN(SCL2_D), GPIO_FN(DU1_DB7), GPIO_FN(SDA2_D),
1571 GPIO_FN(DU1_DOTCLKIN), GPIO_FN(VI2_CLKENB), GPIO_FN(HSPI_CS1),
1572 GPIO_FN(SCL1_D), GPIO_FN(DU1_DOTCLKOUT), GPIO_FN(VI2_FIELD),
1573 GPIO_FN(SDA1_D), GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(VI2_HSYNC),
1574 GPIO_FN(VI3_HSYNC), GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(VI2_VSYNC),
1575 GPIO_FN(VI3_VSYNC), GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE),
1576 GPIO_FN(VI2_CLK), GPIO_FN(TX3_B_IRDA_TX_B), GPIO_FN(SD3_CD),
1577 GPIO_FN(HSPI_TX1), GPIO_FN(VI1_CLKENB), GPIO_FN(VI3_CLKENB),
1578 GPIO_FN(AUDIO_CLKC), GPIO_FN(TX2_D), GPIO_FN(SPEEDIN),
1579 GPIO_FN(GPS_SIGN_D), GPIO_FN(DU1_DISP), GPIO_FN(VI2_DATA6_VI2_B6),
1580 GPIO_FN(TCLK0), GPIO_FN(QSTVA_B_QVS_B), GPIO_FN(HSPI_CLK1),
1581 GPIO_FN(SCK2_D), GPIO_FN(AUDIO_CLKOUT_B), GPIO_FN(GPS_MAG_D),
1582 GPIO_FN(DU1_CDE), GPIO_FN(VI2_DATA7_VI2_B7), GPIO_FN(RX3_B_IRDA_RX_B),
1583 GPIO_FN(SD3_WP), GPIO_FN(HSPI_RX1), GPIO_FN(VI1_FIELD),
1584 GPIO_FN(VI3_FIELD), GPIO_FN(AUDIO_CLKOUT), GPIO_FN(RX2_D),
1585 GPIO_FN(GPS_CLK_C), GPIO_FN(GPS_CLK_D), GPIO_FN(AUDIO_CLKA),
1586 GPIO_FN(CAN_TXCLK), GPIO_FN(AUDIO_CLKB), GPIO_FN(USB_OVC2),
1587 GPIO_FN(CAN_DEBUGOUT0), GPIO_FN(MOUT0),
1588 2534
1589 /* IPSR6 */ 2535static const char * const hspi1_groups[] = {
1590 GPIO_FN(SSI_SCK0129), GPIO_FN(CAN_DEBUGOUT1), GPIO_FN(MOUT1), 2536 "hspi1",
1591 GPIO_FN(SSI_WS0129), GPIO_FN(CAN_DEBUGOUT2), GPIO_FN(MOUT2), 2537 "hspi1_b",
1592 GPIO_FN(SSI_SDATA0), GPIO_FN(CAN_DEBUGOUT3), GPIO_FN(MOUT5), 2538 "hspi1_c",
1593 GPIO_FN(SSI_SDATA1), GPIO_FN(CAN_DEBUGOUT4), GPIO_FN(MOUT6), 2539 "hspi1_d",
1594 GPIO_FN(SSI_SDATA2), GPIO_FN(CAN_DEBUGOUT5), GPIO_FN(SSI_SCK34), 2540};
1595 GPIO_FN(CAN_DEBUGOUT6), GPIO_FN(CAN0_TX_B), GPIO_FN(IERX),
1596 GPIO_FN(SSI_SCK9_C), GPIO_FN(SSI_WS34), GPIO_FN(CAN_DEBUGOUT7),
1597 GPIO_FN(CAN0_RX_B), GPIO_FN(IETX), GPIO_FN(SSI_WS9_C),
1598 GPIO_FN(SSI_SDATA3), GPIO_FN(PWM0_C), GPIO_FN(CAN_DEBUGOUT8),
1599 GPIO_FN(CAN_CLK_B), GPIO_FN(IECLK), GPIO_FN(SCIF_CLK_B),
1600 GPIO_FN(TCLK0_B), GPIO_FN(SSI_SDATA4), GPIO_FN(CAN_DEBUGOUT9),
1601 GPIO_FN(SSI_SDATA9_C), GPIO_FN(SSI_SCK5), GPIO_FN(ADICLK),
1602 GPIO_FN(CAN_DEBUGOUT10), GPIO_FN(SCK3), GPIO_FN(TCLK0_D),
1603 GPIO_FN(SSI_WS5), GPIO_FN(ADICS_SAMP), GPIO_FN(CAN_DEBUGOUT11),
1604 GPIO_FN(TX3_IRDA_TX), GPIO_FN(SSI_SDATA5), GPIO_FN(ADIDATA),
1605 GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(RX3_IRDA_RX), GPIO_FN(SSI_SCK6),
1606 GPIO_FN(ADICHS0), GPIO_FN(CAN0_TX), GPIO_FN(IERX_B),
1607 2541
1608 /* IPSR7 */ 2542static const char * const hspi2_groups[] = {
1609 GPIO_FN(SSI_WS6), GPIO_FN(ADICHS1), GPIO_FN(CAN0_RX), GPIO_FN(IETX_B), 2543 "hspi2",
1610 GPIO_FN(SSI_SDATA6), GPIO_FN(ADICHS2), GPIO_FN(CAN_CLK), 2544 "hspi2_b",
1611 GPIO_FN(IECLK_B), GPIO_FN(SSI_SCK78), GPIO_FN(CAN_DEBUGOUT13), 2545};
1612 GPIO_FN(IRQ0_B), GPIO_FN(SSI_SCK9_B), GPIO_FN(HSPI_CLK1_C),
1613 GPIO_FN(SSI_WS78), GPIO_FN(CAN_DEBUGOUT14), GPIO_FN(IRQ1_B),
1614 GPIO_FN(SSI_WS9_B), GPIO_FN(HSPI_CS1_C), GPIO_FN(SSI_SDATA7),
1615 GPIO_FN(CAN_DEBUGOUT15), GPIO_FN(IRQ2_B), GPIO_FN(TCLK1_C),
1616 GPIO_FN(HSPI_TX1_C), GPIO_FN(SSI_SDATA8), GPIO_FN(VSP),
1617 GPIO_FN(IRQ3_B), GPIO_FN(HSPI_RX1_C), GPIO_FN(SD0_CLK),
1618 GPIO_FN(ATACS01), GPIO_FN(SCK1_B), GPIO_FN(SD0_CMD), GPIO_FN(ATACS11),
1619 GPIO_FN(TX1_B), GPIO_FN(CC5_TDO), GPIO_FN(SD0_DAT0), GPIO_FN(ATADIR1),
1620 GPIO_FN(RX1_B), GPIO_FN(CC5_TRST), GPIO_FN(SD0_DAT1), GPIO_FN(ATAG1),
1621 GPIO_FN(SCK2_B), GPIO_FN(CC5_TMS), GPIO_FN(SD0_DAT2), GPIO_FN(ATARD1),
1622 GPIO_FN(TX2_B), GPIO_FN(CC5_TCK), GPIO_FN(SD0_DAT3), GPIO_FN(ATAWR1),
1623 GPIO_FN(RX2_B), GPIO_FN(CC5_TDI), GPIO_FN(SD0_CD), GPIO_FN(DREQ2),
1624 GPIO_FN(RTS1_B_TANS_B), GPIO_FN(SD0_WP), GPIO_FN(DACK2),
1625 GPIO_FN(CTS1_B),
1626 2546
1627 /* IPSR8 */ 2547static const char * const intc_groups[] = {
1628 GPIO_FN(HSPI_CLK0), GPIO_FN(CTS0), GPIO_FN(USB_OVC0), GPIO_FN(AD_CLK), 2548 "intc_irq0",
1629 GPIO_FN(CC5_STATE4), GPIO_FN(CC5_STATE12), GPIO_FN(CC5_STATE20), 2549 "intc_irq0_b",
1630 GPIO_FN(CC5_STATE28), GPIO_FN(CC5_STATE36), GPIO_FN(HSPI_CS0), 2550 "intc_irq1",
1631 GPIO_FN(RTS0_TANS), GPIO_FN(USB_OVC1), GPIO_FN(AD_DI), 2551 "intc_irq1_b",
1632 GPIO_FN(CC5_STATE5), GPIO_FN(CC5_STATE13), GPIO_FN(CC5_STATE21), 2552 "intc_irq2",
1633 GPIO_FN(CC5_STATE29), GPIO_FN(CC5_STATE37), GPIO_FN(HSPI_TX0), 2553 "intc_irq2_b",
1634 GPIO_FN(TX0), GPIO_FN(CAN_DEBUG_HW_TRIGGER), GPIO_FN(AD_DO), 2554 "intc_irq3",
1635 GPIO_FN(CC5_STATE6), GPIO_FN(CC5_STATE14), GPIO_FN(CC5_STATE22), 2555 "intc_irq4_b",
1636 GPIO_FN(CC5_STATE30), GPIO_FN(CC5_STATE38), GPIO_FN(HSPI_RX0), 2556};
1637 GPIO_FN(RX0), GPIO_FN(CAN_STEP0), GPIO_FN(AD_NCS), GPIO_FN(CC5_STATE7),
1638 GPIO_FN(CC5_STATE15), GPIO_FN(CC5_STATE23), GPIO_FN(CC5_STATE31),
1639 GPIO_FN(CC5_STATE39), GPIO_FN(FMCLK), GPIO_FN(RDS_CLK), GPIO_FN(PCMOE),
1640 GPIO_FN(BPFCLK), GPIO_FN(PCMWE), GPIO_FN(FMIN), GPIO_FN(RDS_DATA),
1641 GPIO_FN(VI0_CLK), GPIO_FN(MMC1_CLK), GPIO_FN(VI0_CLKENB),
1642 GPIO_FN(TX1_C), GPIO_FN(HTX1_B), GPIO_FN(MT1_SYNC),
1643 GPIO_FN(VI0_FIELD), GPIO_FN(RX1_C), GPIO_FN(HRX1_B),
1644 GPIO_FN(VI0_HSYNC), GPIO_FN(VI0_DATA0_B_VI0_B0_B), GPIO_FN(CTS1_C),
1645 GPIO_FN(TX4_D), GPIO_FN(MMC1_CMD), GPIO_FN(HSCK1_B),
1646 GPIO_FN(VI0_VSYNC), GPIO_FN(VI0_DATA1_B_VI0_B1_B),
1647 GPIO_FN(RTS1_C_TANS_C), GPIO_FN(RX4_D), GPIO_FN(PWMFSW0_C),
1648 2557
1649 /* IPSR9 */ 2558static const char * const lbsc_groups[] = {
1650 GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(HRTS1_B), GPIO_FN(MT1_VCXO), 2559 "lbsc_cs0",
1651 GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(HCTS1_B), GPIO_FN(MT1_PWM), 2560 "lbsc_cs1",
1652 GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(MMC1_D0), GPIO_FN(VI0_DATA3_VI0_B3), 2561 "lbsc_ex_cs0",
1653 GPIO_FN(MMC1_D1), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(MMC1_D2), 2562 "lbsc_ex_cs1",
1654 GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(MMC1_D3), GPIO_FN(VI0_DATA6_VI0_B6), 2563 "lbsc_ex_cs2",
1655 GPIO_FN(MMC1_D4), GPIO_FN(ARM_TRACEDATA_0), GPIO_FN(VI0_DATA7_VI0_B7), 2564 "lbsc_ex_cs3",
1656 GPIO_FN(MMC1_D5), GPIO_FN(ARM_TRACEDATA_1), GPIO_FN(VI0_G0), 2565 "lbsc_ex_cs4",
1657 GPIO_FN(SSI_SCK78_C), GPIO_FN(IRQ0), GPIO_FN(ARM_TRACEDATA_2), 2566 "lbsc_ex_cs5",
1658 GPIO_FN(VI0_G1), GPIO_FN(SSI_WS78_C), GPIO_FN(IRQ1), 2567};
1659 GPIO_FN(ARM_TRACEDATA_3), GPIO_FN(VI0_G2), GPIO_FN(ETH_TXD1),
1660 GPIO_FN(MMC1_D6), GPIO_FN(ARM_TRACEDATA_4), GPIO_FN(TS_SPSYNC0),
1661 GPIO_FN(VI0_G3), GPIO_FN(ETH_CRS_DV), GPIO_FN(MMC1_D7),
1662 GPIO_FN(ARM_TRACEDATA_5), GPIO_FN(TS_SDAT0), GPIO_FN(VI0_G4),
1663 GPIO_FN(ETH_TX_EN), GPIO_FN(SD2_DAT0_B), GPIO_FN(ARM_TRACEDATA_6),
1664 GPIO_FN(VI0_G5), GPIO_FN(ETH_RX_ER), GPIO_FN(SD2_DAT1_B),
1665 GPIO_FN(ARM_TRACEDATA_7), GPIO_FN(VI0_G6), GPIO_FN(ETH_RXD0),
1666 GPIO_FN(SD2_DAT2_B), GPIO_FN(ARM_TRACEDATA_8), GPIO_FN(VI0_G7),
1667 GPIO_FN(ETH_RXD1), GPIO_FN(SD2_DAT3_B), GPIO_FN(ARM_TRACEDATA_9),
1668 2568
1669 /* IPSR10 */ 2569static const char * const mmc0_groups[] = {
1670 GPIO_FN(VI0_R0), GPIO_FN(SSI_SDATA7_C), GPIO_FN(SCK1_C), 2570 "mmc0_data1",
1671 GPIO_FN(DREQ1_B), GPIO_FN(ARM_TRACEDATA_10), GPIO_FN(DREQ0_C), 2571 "mmc0_data4",
1672 GPIO_FN(VI0_R1), GPIO_FN(SSI_SDATA8_C), GPIO_FN(DACK1_B), 2572 "mmc0_data8",
1673 GPIO_FN(ARM_TRACEDATA_11), GPIO_FN(DACK0_C), GPIO_FN(DRACK0_C), 2573 "mmc0_ctrl",
1674 GPIO_FN(VI0_R2), GPIO_FN(ETH_LINK), GPIO_FN(SD2_CLK_B), GPIO_FN(IRQ2), 2574};
1675 GPIO_FN(ARM_TRACEDATA_12), GPIO_FN(VI0_R3), GPIO_FN(ETH_MAGIC),
1676 GPIO_FN(SD2_CMD_B), GPIO_FN(IRQ3), GPIO_FN(ARM_TRACEDATA_13),
1677 GPIO_FN(VI0_R4), GPIO_FN(ETH_REFCLK), GPIO_FN(SD2_CD_B),
1678 GPIO_FN(HSPI_CLK1_B), GPIO_FN(ARM_TRACEDATA_14), GPIO_FN(MT1_CLK),
1679 GPIO_FN(TS_SCK0), GPIO_FN(VI0_R5), GPIO_FN(ETH_TXD0),
1680 GPIO_FN(SD2_WP_B), GPIO_FN(HSPI_CS1_B), GPIO_FN(ARM_TRACEDATA_15),
1681 GPIO_FN(MT1_D), GPIO_FN(TS_SDEN0), GPIO_FN(VI0_R6), GPIO_FN(ETH_MDC),
1682 GPIO_FN(DREQ2_C), GPIO_FN(HSPI_TX1_B), GPIO_FN(TRACECLK),
1683 GPIO_FN(MT1_BEN), GPIO_FN(PWMFSW0_D), GPIO_FN(VI0_R7),
1684 GPIO_FN(ETH_MDIO), GPIO_FN(DACK2_C), GPIO_FN(HSPI_RX1_B),
1685 GPIO_FN(SCIF_CLK_D), GPIO_FN(TRACECTL), GPIO_FN(MT1_PEN),
1686 GPIO_FN(VI1_CLK), GPIO_FN(SIM_D), GPIO_FN(SDA3), GPIO_FN(VI1_HSYNC),
1687 GPIO_FN(VI3_CLK), GPIO_FN(SSI_SCK4), GPIO_FN(GPS_SIGN_C),
1688 GPIO_FN(PWMFSW0_E), GPIO_FN(VI1_VSYNC), GPIO_FN(AUDIO_CLKOUT_C),
1689 GPIO_FN(SSI_WS4), GPIO_FN(SIM_CLK), GPIO_FN(GPS_MAG_C),
1690 GPIO_FN(SPV_TRST), GPIO_FN(SCL3),
1691 2575
1692 /* IPSR11 */ 2576static const char * const mmc1_groups[] = {
1693 GPIO_FN(VI1_DATA0_VI1_B0), GPIO_FN(SD2_DAT0), GPIO_FN(SIM_RST), 2577 "mmc1_data1",
1694 GPIO_FN(SPV_TCK), GPIO_FN(ADICLK_B), GPIO_FN(VI1_DATA1_VI1_B1), 2578 "mmc1_data4",
1695 GPIO_FN(SD2_DAT1), GPIO_FN(MT0_CLK), GPIO_FN(SPV_TMS), 2579 "mmc1_data8",
1696 GPIO_FN(ADICS_B_SAMP_B), GPIO_FN(VI1_DATA2_VI1_B2), GPIO_FN(SD2_DAT2), 2580 "mmc1_ctrl",
1697 GPIO_FN(MT0_D), GPIO_FN(SPVTDI), GPIO_FN(ADIDATA_B), 2581};
1698 GPIO_FN(VI1_DATA3_VI1_B3), GPIO_FN(SD2_DAT3), GPIO_FN(MT0_BEN),
1699 GPIO_FN(SPV_TDO), GPIO_FN(ADICHS0_B), GPIO_FN(VI1_DATA4_VI1_B4),
1700 GPIO_FN(SD2_CLK), GPIO_FN(MT0_PEN), GPIO_FN(SPA_TRST),
1701 GPIO_FN(HSPI_CLK1_D), GPIO_FN(ADICHS1_B), GPIO_FN(VI1_DATA5_VI1_B5),
1702 GPIO_FN(SD2_CMD), GPIO_FN(MT0_SYNC), GPIO_FN(SPA_TCK),
1703 GPIO_FN(HSPI_CS1_D), GPIO_FN(ADICHS2_B), GPIO_FN(VI1_DATA6_VI1_B6),
1704 GPIO_FN(SD2_CD), GPIO_FN(MT0_VCXO), GPIO_FN(SPA_TMS),
1705 GPIO_FN(HSPI_TX1_D), GPIO_FN(VI1_DATA7_VI1_B7), GPIO_FN(SD2_WP),
1706 GPIO_FN(MT0_PWM), GPIO_FN(SPA_TDI), GPIO_FN(HSPI_RX1_D),
1707 GPIO_FN(VI1_G0), GPIO_FN(VI3_DATA0), GPIO_FN(DU1_DOTCLKOUT1),
1708 GPIO_FN(TS_SCK1), GPIO_FN(DREQ2_B), GPIO_FN(TX2), GPIO_FN(SPA_TDO),
1709 GPIO_FN(HCTS0_B), GPIO_FN(VI1_G1), GPIO_FN(VI3_DATA1),
1710 GPIO_FN(SSI_SCK1), GPIO_FN(TS_SDEN1), GPIO_FN(DACK2_B), GPIO_FN(RX2),
1711 GPIO_FN(HRTS0_B),
1712 2582
1713 /* IPSR12 */ 2583static const char * const scif0_groups[] = {
1714 GPIO_FN(VI1_G2), GPIO_FN(VI3_DATA2), GPIO_FN(SSI_WS1), 2584 "scif0_data",
1715 GPIO_FN(TS_SPSYNC1), GPIO_FN(SCK2), GPIO_FN(HSCK0_B), GPIO_FN(VI1_G3), 2585 "scif0_clk",
1716 GPIO_FN(VI3_DATA3), GPIO_FN(SSI_SCK2), GPIO_FN(TS_SDAT1), 2586 "scif0_ctrl",
1717 GPIO_FN(SCL1_C), GPIO_FN(HTX0_B), GPIO_FN(VI1_G4), GPIO_FN(VI3_DATA4), 2587 "scif0_data_b",
1718 GPIO_FN(SSI_WS2), GPIO_FN(SDA1_C), GPIO_FN(SIM_RST_B), 2588 "scif0_clk_b",
1719 GPIO_FN(HRX0_B), GPIO_FN(VI1_G5), GPIO_FN(VI3_DATA5), 2589 "scif0_ctrl_b",
1720 GPIO_FN(GPS_CLK), GPIO_FN(FSE), GPIO_FN(TX4_B), GPIO_FN(SIM_D_B), 2590 "scif0_data_c",
1721 GPIO_FN(VI1_G6), GPIO_FN(VI3_DATA6), GPIO_FN(GPS_SIGN), GPIO_FN(FRB), 2591 "scif0_clk_c",
1722 GPIO_FN(RX4_B), GPIO_FN(SIM_CLK_B), GPIO_FN(VI1_G7), 2592 "scif0_ctrl_c",
1723 GPIO_FN(VI3_DATA7), GPIO_FN(GPS_MAG), GPIO_FN(FCE), GPIO_FN(SCK4_B), 2593 "scif0_data_d",
1724}; 2594 "scif0_clk_d",
1725 2595 "scif0_ctrl_d",
1726static struct pinmux_cfg_reg pinmux_config_regs[] = { 2596};
2597
2598static const char * const scif1_groups[] = {
2599 "scif1_data",
2600 "scif1_clk",
2601 "scif1_ctrl",
2602 "scif1_data_b",
2603 "scif1_clk_b",
2604 "scif1_ctrl_b",
2605 "scif1_data_c",
2606 "scif1_clk_c",
2607 "scif1_ctrl_c",
2608};
2609
2610static const char * const scif2_groups[] = {
2611 "scif2_data",
2612 "scif2_clk",
2613 "scif2_data_b",
2614 "scif2_clk_b",
2615 "scif2_data_c",
2616 "scif2_clk_c",
2617 "scif2_data_d",
2618 "scif2_clk_d",
2619 "scif2_data_e",
2620};
2621
2622static const char * const scif3_groups[] = {
2623 "scif3_data",
2624 "scif3_clk",
2625 "scif3_data_b",
2626 "scif3_data_c",
2627 "scif3_data_d",
2628 "scif3_data_e",
2629 "scif3_clk_e",
2630};
2631
2632static const char * const scif4_groups[] = {
2633 "scif4_data",
2634 "scif4_clk",
2635 "scif4_data_b",
2636 "scif4_clk_b",
2637 "scif4_data_c",
2638 "scif4_data_d",
2639};
2640
2641static const char * const scif5_groups[] = {
2642 "scif5_data",
2643 "scif5_clk",
2644 "scif5_data_b",
2645 "scif5_clk_b",
2646 "scif5_data_c",
2647 "scif5_clk_c",
2648 "scif5_data_d",
2649 "scif5_clk_d",
2650};
2651
2652static const char * const sdhi0_groups[] = {
2653 "sdhi0_data1",
2654 "sdhi0_data4",
2655 "sdhi0_ctrl",
2656 "sdhi0_cd",
2657 "sdhi0_wp",
2658};
2659
2660static const char * const sdhi1_groups[] = {
2661 "sdhi1_data1",
2662 "sdhi1_data4",
2663 "sdhi1_ctrl",
2664 "sdhi1_cd",
2665 "sdhi1_wp",
2666};
2667
2668static const char * const sdhi2_groups[] = {
2669 "sdhi2_data1",
2670 "sdhi2_data4",
2671 "sdhi2_ctrl",
2672 "sdhi2_cd",
2673 "sdhi2_wp",
2674};
2675
2676static const char * const sdhi3_groups[] = {
2677 "sdhi3_data1",
2678 "sdhi3_data4",
2679 "sdhi3_ctrl",
2680 "sdhi3_cd",
2681 "sdhi3_wp",
2682};
2683
2684static const char * const usb0_groups[] = {
2685 "usb0",
2686};
2687
2688static const char * const usb1_groups[] = {
2689 "usb1",
2690};
2691
2692static const char * const usb2_groups[] = {
2693 "usb2",
2694};
2695
2696static const struct sh_pfc_function pinmux_functions[] = {
2697 SH_PFC_FUNCTION(du0),
2698 SH_PFC_FUNCTION(du1),
2699 SH_PFC_FUNCTION(hspi0),
2700 SH_PFC_FUNCTION(hspi1),
2701 SH_PFC_FUNCTION(hspi2),
2702 SH_PFC_FUNCTION(intc),
2703 SH_PFC_FUNCTION(lbsc),
2704 SH_PFC_FUNCTION(mmc0),
2705 SH_PFC_FUNCTION(mmc1),
2706 SH_PFC_FUNCTION(sdhi0),
2707 SH_PFC_FUNCTION(sdhi1),
2708 SH_PFC_FUNCTION(sdhi2),
2709 SH_PFC_FUNCTION(sdhi3),
2710 SH_PFC_FUNCTION(scif0),
2711 SH_PFC_FUNCTION(scif1),
2712 SH_PFC_FUNCTION(scif2),
2713 SH_PFC_FUNCTION(scif3),
2714 SH_PFC_FUNCTION(scif4),
2715 SH_PFC_FUNCTION(scif5),
2716 SH_PFC_FUNCTION(usb0),
2717 SH_PFC_FUNCTION(usb1),
2718 SH_PFC_FUNCTION(usb2),
2719};
2720
2721static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1727 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { 2722 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
1728 GP_0_31_FN, FN_IP3_31_29, 2723 GP_0_31_FN, FN_IP3_31_29,
1729 GP_0_30_FN, FN_IP3_26_24, 2724 GP_0_30_FN, FN_IP3_26_24,
@@ -2412,7 +3407,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2412 FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1, 3407 FN_VI1_G1, FN_VI3_DATA1, FN_SSI_SCK1, FN_TS_SDEN1,
2413 FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0, 3408 FN_DACK2_B, FN_RX2, FN_HRTS0_B, 0,
2414 /* IP11_26_24 [3] */ 3409 /* IP11_26_24 [3] */
2415 FN_VI1_G0, FN_VI3_DATA0, FN_DU1_DOTCLKOUT1, FN_TS_SCK1, 3410 FN_VI1_G0, FN_VI3_DATA0, 0, FN_TS_SCK1,
2416 FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B, 3411 FN_DREQ2_B, FN_TX2, FN_SPA_TDO, FN_HCTS0_B,
2417 /* IP11_23_21 [3] */ 3412 /* IP11_23_21 [3] */
2418 FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI, 3413 FN_VI1_DATA7_VI1_B7, FN_SD2_WP, FN_MT0_PWM, FN_SPA_TDI,
@@ -2558,66 +3553,24 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2558 /* SEL_I2C1 [2] */ 3553 /* SEL_I2C1 [2] */
2559 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 } 3554 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, FN_SEL_I2C1_3 }
2560 }, 3555 },
2561 { PINMUX_CFG_REG("INOUTSEL0", 0xffc40004, 32, 1) { GP_INOUTSEL(0) } },
2562 { PINMUX_CFG_REG("INOUTSEL1", 0xffc41004, 32, 1) { GP_INOUTSEL(1) } },
2563 { PINMUX_CFG_REG("INOUTSEL2", 0xffc42004, 32, 1) { GP_INOUTSEL(2) } },
2564 { PINMUX_CFG_REG("INOUTSEL3", 0xffc43004, 32, 1) { GP_INOUTSEL(3) } },
2565 { PINMUX_CFG_REG("INOUTSEL4", 0xffc44004, 32, 1) { GP_INOUTSEL(4) } },
2566 { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { GP_INOUTSEL(5) } },
2567 { PINMUX_CFG_REG("INOUTSEL6", 0xffc46004, 32, 1) {
2568 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2569 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2570 0, 0, 0, 0, 0, 0, 0, 0,
2571 0, 0,
2572 0, 0,
2573 0, 0,
2574 GP_6_8_IN, GP_6_8_OUT,
2575 GP_6_7_IN, GP_6_7_OUT,
2576 GP_6_6_IN, GP_6_6_OUT,
2577 GP_6_5_IN, GP_6_5_OUT,
2578 GP_6_4_IN, GP_6_4_OUT,
2579 GP_6_3_IN, GP_6_3_OUT,
2580 GP_6_2_IN, GP_6_2_OUT,
2581 GP_6_1_IN, GP_6_1_OUT,
2582 GP_6_0_IN, GP_6_0_OUT, }
2583 },
2584 { },
2585};
2586
2587static struct pinmux_data_reg pinmux_data_regs[] = {
2588 { PINMUX_DATA_REG("INDT0", 0xffc40008, 32) { GP_INDT(0) } },
2589 { PINMUX_DATA_REG("INDT1", 0xffc41008, 32) { GP_INDT(1) } },
2590 { PINMUX_DATA_REG("INDT2", 0xffc42008, 32) { GP_INDT(2) } },
2591 { PINMUX_DATA_REG("INDT3", 0xffc43008, 32) { GP_INDT(3) } },
2592 { PINMUX_DATA_REG("INDT4", 0xffc44008, 32) { GP_INDT(4) } },
2593 { PINMUX_DATA_REG("INDT5", 0xffc45008, 32) { GP_INDT(5) } },
2594 { PINMUX_DATA_REG("INDT6", 0xffc46008, 32) {
2595 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2596 0, 0, 0, 0, 0, 0, 0, GP_6_8_DATA,
2597 GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA,
2598 GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA }
2599 },
2600 { }, 3556 { },
2601}; 3557};
2602 3558
2603struct sh_pfc_soc_info r8a7779_pinmux_info = { 3559const struct sh_pfc_soc_info r8a7779_pinmux_info = {
2604 .name = "r8a7779_pfc", 3560 .name = "r8a7779_pfc",
2605 3561
2606 .unlock_reg = 0xfffc0000, /* PMMR */ 3562 .unlock_reg = 0xfffc0000, /* PMMR */
2607 3563
2608 .reserved_id = PINMUX_RESERVED,
2609 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2610 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2611 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2612 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2613 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 3564 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2614 3565
2615 .first_gpio = GPIO_GP_0_0, 3566 .pins = pinmux_pins,
2616 .last_gpio = GPIO_FN_SCK4_B, 3567 .nr_pins = ARRAY_SIZE(pinmux_pins),
3568 .groups = pinmux_groups,
3569 .nr_groups = ARRAY_SIZE(pinmux_groups),
3570 .functions = pinmux_functions,
3571 .nr_functions = ARRAY_SIZE(pinmux_functions),
2617 3572
2618 .gpios = pinmux_gpios,
2619 .cfg_regs = pinmux_config_regs, 3573 .cfg_regs = pinmux_config_regs,
2620 .data_regs = pinmux_data_regs,
2621 3574
2622 .gpio_data = pinmux_data, 3575 .gpio_data = pinmux_data,
2623 .gpio_data_size = ARRAY_SIZE(pinmux_data), 3576 .gpio_data_size = ARRAY_SIZE(pinmux_data),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
index 01b425dfd162..f63d51dc3f4c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
@@ -272,7 +272,7 @@ enum {
272 PINMUX_MARK_END, 272 PINMUX_MARK_END,
273}; 273};
274 274
275static pinmux_enum_t pinmux_data[] = { 275static const pinmux_enum_t pinmux_data[] = {
276 276
277 /* PA */ 277 /* PA */
278 PINMUX_DATA(PA7_DATA, PA7_IN), 278 PINMUX_DATA(PA7_DATA, PA7_IN),
@@ -703,7 +703,7 @@ static pinmux_enum_t pinmux_data[] = {
703 PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11), 703 PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11),
704}; 704};
705 705
706static struct pinmux_gpio pinmux_gpios[] = { 706static struct sh_pfc_pin pinmux_pins[] = {
707 707
708 /* PA */ 708 /* PA */
709 PINMUX_GPIO(GPIO_PA7, PA7_DATA), 709 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
@@ -815,265 +815,269 @@ static struct pinmux_gpio pinmux_gpios[] = {
815 PINMUX_GPIO(GPIO_PF2, PF2_DATA), 815 PINMUX_GPIO(GPIO_PF2, PF2_DATA),
816 PINMUX_GPIO(GPIO_PF1, PF1_DATA), 816 PINMUX_GPIO(GPIO_PF1, PF1_DATA),
817 PINMUX_GPIO(GPIO_PF0, PF0_DATA), 817 PINMUX_GPIO(GPIO_PF0, PF0_DATA),
818};
819
820#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
818 821
822static const struct pinmux_func pinmux_func_gpios[] = {
819 /* INTC */ 823 /* INTC */
820 PINMUX_GPIO(GPIO_FN_PINT7_PB, PINT7_PB_MARK), 824 GPIO_FN(PINT7_PB),
821 PINMUX_GPIO(GPIO_FN_PINT6_PB, PINT6_PB_MARK), 825 GPIO_FN(PINT6_PB),
822 PINMUX_GPIO(GPIO_FN_PINT5_PB, PINT5_PB_MARK), 826 GPIO_FN(PINT5_PB),
823 PINMUX_GPIO(GPIO_FN_PINT4_PB, PINT4_PB_MARK), 827 GPIO_FN(PINT4_PB),
824 PINMUX_GPIO(GPIO_FN_PINT3_PB, PINT3_PB_MARK), 828 GPIO_FN(PINT3_PB),
825 PINMUX_GPIO(GPIO_FN_PINT2_PB, PINT2_PB_MARK), 829 GPIO_FN(PINT2_PB),
826 PINMUX_GPIO(GPIO_FN_PINT1_PB, PINT1_PB_MARK), 830 GPIO_FN(PINT1_PB),
827 PINMUX_GPIO(GPIO_FN_PINT0_PB, PINT0_PB_MARK), 831 GPIO_FN(PINT0_PB),
828 PINMUX_GPIO(GPIO_FN_PINT7_PD, PINT7_PD_MARK), 832 GPIO_FN(PINT7_PD),
829 PINMUX_GPIO(GPIO_FN_PINT6_PD, PINT6_PD_MARK), 833 GPIO_FN(PINT6_PD),
830 PINMUX_GPIO(GPIO_FN_PINT5_PD, PINT5_PD_MARK), 834 GPIO_FN(PINT5_PD),
831 PINMUX_GPIO(GPIO_FN_PINT4_PD, PINT4_PD_MARK), 835 GPIO_FN(PINT4_PD),
832 PINMUX_GPIO(GPIO_FN_PINT3_PD, PINT3_PD_MARK), 836 GPIO_FN(PINT3_PD),
833 PINMUX_GPIO(GPIO_FN_PINT2_PD, PINT2_PD_MARK), 837 GPIO_FN(PINT2_PD),
834 PINMUX_GPIO(GPIO_FN_PINT1_PD, PINT1_PD_MARK), 838 GPIO_FN(PINT1_PD),
835 PINMUX_GPIO(GPIO_FN_PINT0_PD, PINT0_PD_MARK), 839 GPIO_FN(PINT0_PD),
836 PINMUX_GPIO(GPIO_FN_IRQ7_PB, IRQ7_PB_MARK), 840 GPIO_FN(IRQ7_PB),
837 PINMUX_GPIO(GPIO_FN_IRQ6_PB, IRQ6_PB_MARK), 841 GPIO_FN(IRQ6_PB),
838 PINMUX_GPIO(GPIO_FN_IRQ5_PB, IRQ5_PB_MARK), 842 GPIO_FN(IRQ5_PB),
839 PINMUX_GPIO(GPIO_FN_IRQ4_PB, IRQ4_PB_MARK), 843 GPIO_FN(IRQ4_PB),
840 PINMUX_GPIO(GPIO_FN_IRQ3_PB, IRQ3_PB_MARK), 844 GPIO_FN(IRQ3_PB),
841 PINMUX_GPIO(GPIO_FN_IRQ2_PB, IRQ2_PB_MARK), 845 GPIO_FN(IRQ2_PB),
842 PINMUX_GPIO(GPIO_FN_IRQ1_PB, IRQ1_PB_MARK), 846 GPIO_FN(IRQ1_PB),
843 PINMUX_GPIO(GPIO_FN_IRQ0_PB, IRQ0_PB_MARK), 847 GPIO_FN(IRQ0_PB),
844 PINMUX_GPIO(GPIO_FN_IRQ7_PD, IRQ7_PD_MARK), 848 GPIO_FN(IRQ7_PD),
845 PINMUX_GPIO(GPIO_FN_IRQ6_PD, IRQ6_PD_MARK), 849 GPIO_FN(IRQ6_PD),
846 PINMUX_GPIO(GPIO_FN_IRQ5_PD, IRQ5_PD_MARK), 850 GPIO_FN(IRQ5_PD),
847 PINMUX_GPIO(GPIO_FN_IRQ4_PD, IRQ4_PD_MARK), 851 GPIO_FN(IRQ4_PD),
848 PINMUX_GPIO(GPIO_FN_IRQ3_PD, IRQ3_PD_MARK), 852 GPIO_FN(IRQ3_PD),
849 PINMUX_GPIO(GPIO_FN_IRQ2_PD, IRQ2_PD_MARK), 853 GPIO_FN(IRQ2_PD),
850 PINMUX_GPIO(GPIO_FN_IRQ1_PD, IRQ1_PD_MARK), 854 GPIO_FN(IRQ1_PD),
851 PINMUX_GPIO(GPIO_FN_IRQ0_PD, IRQ0_PD_MARK), 855 GPIO_FN(IRQ0_PD),
852 PINMUX_GPIO(GPIO_FN_IRQ7_PE, IRQ7_PE_MARK), 856 GPIO_FN(IRQ7_PE),
853 PINMUX_GPIO(GPIO_FN_IRQ6_PE, IRQ6_PE_MARK), 857 GPIO_FN(IRQ6_PE),
854 PINMUX_GPIO(GPIO_FN_IRQ5_PE, IRQ5_PE_MARK), 858 GPIO_FN(IRQ5_PE),
855 PINMUX_GPIO(GPIO_FN_IRQ4_PE, IRQ4_PE_MARK), 859 GPIO_FN(IRQ4_PE),
856 PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK), 860 GPIO_FN(IRQ3_PE),
857 PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK), 861 GPIO_FN(IRQ2_PE),
858 PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK), 862 GPIO_FN(IRQ1_PE),
859 PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK), 863 GPIO_FN(IRQ0_PE),
860 864
861 PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), 865 GPIO_FN(WDTOVF),
862 PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), 866 GPIO_FN(IRQOUT),
863 PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK), 867 GPIO_FN(REFOUT),
864 PINMUX_GPIO(GPIO_FN_IRQOUT_REFOUT, IRQOUT_REFOUT_MARK), 868 GPIO_FN(IRQOUT_REFOUT),
865 PINMUX_GPIO(GPIO_FN_UBCTRG, UBCTRG_MARK), 869 GPIO_FN(UBCTRG),
866 870
867 /* CAN */ 871 /* CAN */
868 PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), 872 GPIO_FN(CTX1),
869 PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), 873 GPIO_FN(CRX1),
870 PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), 874 GPIO_FN(CTX0),
871 PINMUX_GPIO(GPIO_FN_CTX0_CTX1, CTX0_CTX1_MARK), 875 GPIO_FN(CTX0_CTX1),
872 PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), 876 GPIO_FN(CRX0),
873 PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), 877 GPIO_FN(CRX0_CRX1),
874 878
875 /* IIC3 */ 879 /* IIC3 */
876 PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), 880 GPIO_FN(SDA3),
877 PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), 881 GPIO_FN(SCL3),
878 PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), 882 GPIO_FN(SDA2),
879 PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), 883 GPIO_FN(SCL2),
880 PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), 884 GPIO_FN(SDA1),
881 PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), 885 GPIO_FN(SCL1),
882 PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), 886 GPIO_FN(SDA0),
883 PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), 887 GPIO_FN(SCL0),
884 888
885 /* DMAC */ 889 /* DMAC */
886 PINMUX_GPIO(GPIO_FN_TEND0_PD, TEND0_PD_MARK), 890 GPIO_FN(TEND0_PD),
887 PINMUX_GPIO(GPIO_FN_TEND0_PE, TEND0_PE_MARK), 891 GPIO_FN(TEND0_PE),
888 PINMUX_GPIO(GPIO_FN_DACK0_PD, DACK0_PD_MARK), 892 GPIO_FN(DACK0_PD),
889 PINMUX_GPIO(GPIO_FN_DACK0_PE, DACK0_PE_MARK), 893 GPIO_FN(DACK0_PE),
890 PINMUX_GPIO(GPIO_FN_DREQ0_PD, DREQ0_PD_MARK), 894 GPIO_FN(DREQ0_PD),
891 PINMUX_GPIO(GPIO_FN_DREQ0_PE, DREQ0_PE_MARK), 895 GPIO_FN(DREQ0_PE),
892 PINMUX_GPIO(GPIO_FN_TEND1_PD, TEND1_PD_MARK), 896 GPIO_FN(TEND1_PD),
893 PINMUX_GPIO(GPIO_FN_TEND1_PE, TEND1_PE_MARK), 897 GPIO_FN(TEND1_PE),
894 PINMUX_GPIO(GPIO_FN_DACK1_PD, DACK1_PD_MARK), 898 GPIO_FN(DACK1_PD),
895 PINMUX_GPIO(GPIO_FN_DACK1_PE, DACK1_PE_MARK), 899 GPIO_FN(DACK1_PE),
896 PINMUX_GPIO(GPIO_FN_DREQ1_PD, DREQ1_PD_MARK), 900 GPIO_FN(DREQ1_PD),
897 PINMUX_GPIO(GPIO_FN_DREQ1_PE, DREQ1_PE_MARK), 901 GPIO_FN(DREQ1_PE),
898 PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), 902 GPIO_FN(DACK2),
899 PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), 903 GPIO_FN(DREQ2),
900 PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), 904 GPIO_FN(DACK3),
901 PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), 905 GPIO_FN(DREQ3),
902 906
903 /* ADC */ 907 /* ADC */
904 PINMUX_GPIO(GPIO_FN_ADTRG_PD, ADTRG_PD_MARK), 908 GPIO_FN(ADTRG_PD),
905 PINMUX_GPIO(GPIO_FN_ADTRG_PE, ADTRG_PE_MARK), 909 GPIO_FN(ADTRG_PE),
906 910
907 /* BSC */ 911 /* BSC */
908 PINMUX_GPIO(GPIO_FN_D31, D31_MARK), 912 GPIO_FN(D31),
909 PINMUX_GPIO(GPIO_FN_D30, D30_MARK), 913 GPIO_FN(D30),
910 PINMUX_GPIO(GPIO_FN_D29, D29_MARK), 914 GPIO_FN(D29),
911 PINMUX_GPIO(GPIO_FN_D28, D28_MARK), 915 GPIO_FN(D28),
912 PINMUX_GPIO(GPIO_FN_D27, D27_MARK), 916 GPIO_FN(D27),
913 PINMUX_GPIO(GPIO_FN_D26, D26_MARK), 917 GPIO_FN(D26),
914 PINMUX_GPIO(GPIO_FN_D25, D25_MARK), 918 GPIO_FN(D25),
915 PINMUX_GPIO(GPIO_FN_D24, D24_MARK), 919 GPIO_FN(D24),
916 PINMUX_GPIO(GPIO_FN_D23, D23_MARK), 920 GPIO_FN(D23),
917 PINMUX_GPIO(GPIO_FN_D22, D22_MARK), 921 GPIO_FN(D22),
918 PINMUX_GPIO(GPIO_FN_D21, D21_MARK), 922 GPIO_FN(D21),
919 PINMUX_GPIO(GPIO_FN_D20, D20_MARK), 923 GPIO_FN(D20),
920 PINMUX_GPIO(GPIO_FN_D19, D19_MARK), 924 GPIO_FN(D19),
921 PINMUX_GPIO(GPIO_FN_D18, D18_MARK), 925 GPIO_FN(D18),
922 PINMUX_GPIO(GPIO_FN_D17, D17_MARK), 926 GPIO_FN(D17),
923 PINMUX_GPIO(GPIO_FN_D16, D16_MARK), 927 GPIO_FN(D16),
924 PINMUX_GPIO(GPIO_FN_A25, A25_MARK), 928 GPIO_FN(A25),
925 PINMUX_GPIO(GPIO_FN_A24, A24_MARK), 929 GPIO_FN(A24),
926 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 930 GPIO_FN(A23),
927 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 931 GPIO_FN(A22),
928 PINMUX_GPIO(GPIO_FN_A21, A21_MARK), 932 GPIO_FN(A21),
929 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), 933 GPIO_FN(CS4),
930 PINMUX_GPIO(GPIO_FN_MRES, MRES_MARK), 934 GPIO_FN(MRES),
931 PINMUX_GPIO(GPIO_FN_BS, BS_MARK), 935 GPIO_FN(BS),
932 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 936 GPIO_FN(IOIS16),
933 PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), 937 GPIO_FN(CS1),
934 PINMUX_GPIO(GPIO_FN_CS6_CE1B, CS6_CE1B_MARK), 938 GPIO_FN(CS6_CE1B),
935 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), 939 GPIO_FN(CE2B),
936 PINMUX_GPIO(GPIO_FN_CS5_CE1A, CS5_CE1A_MARK), 940 GPIO_FN(CS5_CE1A),
937 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), 941 GPIO_FN(CE2A),
938 PINMUX_GPIO(GPIO_FN_FRAME, FRAME_MARK), 942 GPIO_FN(FRAME),
939 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), 943 GPIO_FN(WAIT),
940 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), 944 GPIO_FN(RDWR),
941 PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), 945 GPIO_FN(CKE),
942 PINMUX_GPIO(GPIO_FN_CASU, CASU_MARK), 946 GPIO_FN(CASU),
943 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), 947 GPIO_FN(BREQ),
944 PINMUX_GPIO(GPIO_FN_RASU, RASU_MARK), 948 GPIO_FN(RASU),
945 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), 949 GPIO_FN(BACK),
946 PINMUX_GPIO(GPIO_FN_CASL, CASL_MARK), 950 GPIO_FN(CASL),
947 PINMUX_GPIO(GPIO_FN_RASL, RASL_MARK), 951 GPIO_FN(RASL),
948 PINMUX_GPIO(GPIO_FN_WE3_DQMUU_AH_ICIO_WR, WE3_DQMUU_AH_ICIO_WR_MARK), 952 GPIO_FN(WE3_DQMUU_AH_ICIO_WR),
949 PINMUX_GPIO(GPIO_FN_WE2_DQMUL_ICIORD, WE2_DQMUL_ICIORD_MARK), 953 GPIO_FN(WE2_DQMUL_ICIORD),
950 PINMUX_GPIO(GPIO_FN_WE1_DQMLU_WE, WE1_DQMLU_WE_MARK), 954 GPIO_FN(WE1_DQMLU_WE),
951 PINMUX_GPIO(GPIO_FN_WE0_DQMLL, WE0_DQMLL_MARK), 955 GPIO_FN(WE0_DQMLL),
952 PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), 956 GPIO_FN(CS3),
953 PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), 957 GPIO_FN(CS2),
954 PINMUX_GPIO(GPIO_FN_A1, A1_MARK), 958 GPIO_FN(A1),
955 PINMUX_GPIO(GPIO_FN_A0, A0_MARK), 959 GPIO_FN(A0),
956 PINMUX_GPIO(GPIO_FN_CS7, CS7_MARK), 960 GPIO_FN(CS7),
957 961
958 /* TMU */ 962 /* TMU */
959 PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), 963 GPIO_FN(TIOC4D),
960 PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), 964 GPIO_FN(TIOC4C),
961 PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), 965 GPIO_FN(TIOC4B),
962 PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), 966 GPIO_FN(TIOC4A),
963 PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), 967 GPIO_FN(TIOC3D),
964 PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), 968 GPIO_FN(TIOC3C),
965 PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), 969 GPIO_FN(TIOC3B),
966 PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), 970 GPIO_FN(TIOC3A),
967 PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), 971 GPIO_FN(TIOC2B),
968 PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), 972 GPIO_FN(TIOC1B),
969 PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), 973 GPIO_FN(TIOC2A),
970 PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), 974 GPIO_FN(TIOC1A),
971 PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), 975 GPIO_FN(TIOC0D),
972 PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), 976 GPIO_FN(TIOC0C),
973 PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), 977 GPIO_FN(TIOC0B),
974 PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), 978 GPIO_FN(TIOC0A),
975 PINMUX_GPIO(GPIO_FN_TCLKD_PD, TCLKD_PD_MARK), 979 GPIO_FN(TCLKD_PD),
976 PINMUX_GPIO(GPIO_FN_TCLKC_PD, TCLKC_PD_MARK), 980 GPIO_FN(TCLKC_PD),
977 PINMUX_GPIO(GPIO_FN_TCLKB_PD, TCLKB_PD_MARK), 981 GPIO_FN(TCLKB_PD),
978 PINMUX_GPIO(GPIO_FN_TCLKA_PD, TCLKA_PD_MARK), 982 GPIO_FN(TCLKA_PD),
979 PINMUX_GPIO(GPIO_FN_TCLKD_PF, TCLKD_PF_MARK), 983 GPIO_FN(TCLKD_PF),
980 PINMUX_GPIO(GPIO_FN_TCLKC_PF, TCLKC_PF_MARK), 984 GPIO_FN(TCLKC_PF),
981 PINMUX_GPIO(GPIO_FN_TCLKB_PF, TCLKB_PF_MARK), 985 GPIO_FN(TCLKB_PF),
982 PINMUX_GPIO(GPIO_FN_TCLKA_PF, TCLKA_PF_MARK), 986 GPIO_FN(TCLKA_PF),
983 987
984 /* SSU */ 988 /* SSU */
985 PINMUX_GPIO(GPIO_FN_SCS0_PD, SCS0_PD_MARK), 989 GPIO_FN(SCS0_PD),
986 PINMUX_GPIO(GPIO_FN_SSO0_PD, SSO0_PD_MARK), 990 GPIO_FN(SSO0_PD),
987 PINMUX_GPIO(GPIO_FN_SSI0_PD, SSI0_PD_MARK), 991 GPIO_FN(SSI0_PD),
988 PINMUX_GPIO(GPIO_FN_SSCK0_PD, SSCK0_PD_MARK), 992 GPIO_FN(SSCK0_PD),
989 PINMUX_GPIO(GPIO_FN_SCS0_PF, SCS0_PF_MARK), 993 GPIO_FN(SCS0_PF),
990 PINMUX_GPIO(GPIO_FN_SSO0_PF, SSO0_PF_MARK), 994 GPIO_FN(SSO0_PF),
991 PINMUX_GPIO(GPIO_FN_SSI0_PF, SSI0_PF_MARK), 995 GPIO_FN(SSI0_PF),
992 PINMUX_GPIO(GPIO_FN_SSCK0_PF, SSCK0_PF_MARK), 996 GPIO_FN(SSCK0_PF),
993 PINMUX_GPIO(GPIO_FN_SCS1_PD, SCS1_PD_MARK), 997 GPIO_FN(SCS1_PD),
994 PINMUX_GPIO(GPIO_FN_SSO1_PD, SSO1_PD_MARK), 998 GPIO_FN(SSO1_PD),
995 PINMUX_GPIO(GPIO_FN_SSI1_PD, SSI1_PD_MARK), 999 GPIO_FN(SSI1_PD),
996 PINMUX_GPIO(GPIO_FN_SSCK1_PD, SSCK1_PD_MARK), 1000 GPIO_FN(SSCK1_PD),
997 PINMUX_GPIO(GPIO_FN_SCS1_PF, SCS1_PF_MARK), 1001 GPIO_FN(SCS1_PF),
998 PINMUX_GPIO(GPIO_FN_SSO1_PF, SSO1_PF_MARK), 1002 GPIO_FN(SSO1_PF),
999 PINMUX_GPIO(GPIO_FN_SSI1_PF, SSI1_PF_MARK), 1003 GPIO_FN(SSI1_PF),
1000 PINMUX_GPIO(GPIO_FN_SSCK1_PF, SSCK1_PF_MARK), 1004 GPIO_FN(SSCK1_PF),
1001 1005
1002 /* SCIF */ 1006 /* SCIF */
1003 PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), 1007 GPIO_FN(TXD0),
1004 PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), 1008 GPIO_FN(RXD0),
1005 PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), 1009 GPIO_FN(SCK0),
1006 PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), 1010 GPIO_FN(TXD1),
1007 PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), 1011 GPIO_FN(RXD1),
1008 PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), 1012 GPIO_FN(SCK1),
1009 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), 1013 GPIO_FN(TXD2),
1010 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), 1014 GPIO_FN(RXD2),
1011 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), 1015 GPIO_FN(SCK2),
1012 PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), 1016 GPIO_FN(RTS3),
1013 PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), 1017 GPIO_FN(CTS3),
1014 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), 1018 GPIO_FN(TXD3),
1015 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), 1019 GPIO_FN(RXD3),
1016 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), 1020 GPIO_FN(SCK3),
1017 1021
1018 /* SSI */ 1022 /* SSI */
1019 PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), 1023 GPIO_FN(AUDIO_CLK),
1020 PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), 1024 GPIO_FN(SSIDATA3),
1021 PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), 1025 GPIO_FN(SSIWS3),
1022 PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), 1026 GPIO_FN(SSISCK3),
1023 PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), 1027 GPIO_FN(SSIDATA2),
1024 PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), 1028 GPIO_FN(SSIWS2),
1025 PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), 1029 GPIO_FN(SSISCK2),
1026 PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), 1030 GPIO_FN(SSIDATA1),
1027 PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), 1031 GPIO_FN(SSIWS1),
1028 PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), 1032 GPIO_FN(SSISCK1),
1029 PINMUX_GPIO(GPIO_FN_SSIDATA0, SSIDATA0_MARK), 1033 GPIO_FN(SSIDATA0),
1030 PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), 1034 GPIO_FN(SSIWS0),
1031 PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), 1035 GPIO_FN(SSISCK0),
1032 1036
1033 /* FLCTL */ 1037 /* FLCTL */
1034 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), 1038 GPIO_FN(FCE),
1035 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), 1039 GPIO_FN(FRB),
1036 PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), 1040 GPIO_FN(NAF7),
1037 PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), 1041 GPIO_FN(NAF6),
1038 PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), 1042 GPIO_FN(NAF5),
1039 PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), 1043 GPIO_FN(NAF4),
1040 PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), 1044 GPIO_FN(NAF3),
1041 PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), 1045 GPIO_FN(NAF2),
1042 PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), 1046 GPIO_FN(NAF1),
1043 PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), 1047 GPIO_FN(NAF0),
1044 PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), 1048 GPIO_FN(FSC),
1045 PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), 1049 GPIO_FN(FOE),
1046 PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), 1050 GPIO_FN(FCDE),
1047 PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), 1051 GPIO_FN(FWE),
1048 1052
1049 /* LCDC */ 1053 /* LCDC */
1050 PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK), 1054 GPIO_FN(LCD_VEPWC),
1051 PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK), 1055 GPIO_FN(LCD_VCPWC),
1052 PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), 1056 GPIO_FN(LCD_CLK),
1053 PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK), 1057 GPIO_FN(LCD_FLM),
1054 PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), 1058 GPIO_FN(LCD_M_DISP),
1055 PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK), 1059 GPIO_FN(LCD_CL2),
1056 PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK), 1060 GPIO_FN(LCD_CL1),
1057 PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK), 1061 GPIO_FN(LCD_DON),
1058 PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), 1062 GPIO_FN(LCD_DATA15),
1059 PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), 1063 GPIO_FN(LCD_DATA14),
1060 PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), 1064 GPIO_FN(LCD_DATA13),
1061 PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), 1065 GPIO_FN(LCD_DATA12),
1062 PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), 1066 GPIO_FN(LCD_DATA11),
1063 PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), 1067 GPIO_FN(LCD_DATA10),
1064 PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), 1068 GPIO_FN(LCD_DATA9),
1065 PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), 1069 GPIO_FN(LCD_DATA8),
1066 PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), 1070 GPIO_FN(LCD_DATA7),
1067 PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), 1071 GPIO_FN(LCD_DATA6),
1068 PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), 1072 GPIO_FN(LCD_DATA5),
1069 PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), 1073 GPIO_FN(LCD_DATA4),
1070 PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), 1074 GPIO_FN(LCD_DATA3),
1071 PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), 1075 GPIO_FN(LCD_DATA2),
1072 PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), 1076 GPIO_FN(LCD_DATA1),
1073 PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), 1077 GPIO_FN(LCD_DATA0),
1074}; 1078};
1075 1079
1076static struct pinmux_cfg_reg pinmux_config_regs[] = { 1080static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1077 { PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) { 1081 { PINMUX_CFG_REG("PBIORL", 0xfffe3886, 16, 1) {
1078 0, 0, 1082 0, 0,
1079 0, 0, 1083 0, 0,
@@ -1525,7 +1529,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1525 {} 1529 {}
1526}; 1530};
1527 1531
1528static struct pinmux_data_reg pinmux_data_regs[] = { 1532static const struct pinmux_data_reg pinmux_data_regs[] = {
1529 { PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) { 1533 { PINMUX_DATA_REG("PADRL", 0xfffe3802, 16) {
1530 0, 0, 0, 0, 1534 0, 0, 0, 0,
1531 0, 0, 0, 0, 1535 0, 0, 0, 0,
@@ -1571,19 +1575,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1571 { }, 1575 { },
1572}; 1576};
1573 1577
1574struct sh_pfc_soc_info sh7203_pinmux_info = { 1578const struct sh_pfc_soc_info sh7203_pinmux_info = {
1575 .name = "sh7203_pfc", 1579 .name = "sh7203_pfc",
1576 .reserved_id = PINMUX_RESERVED,
1577 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1578 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, 1580 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
1579 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, 1581 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
1580 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1581 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 1582 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1582 1583
1583 .first_gpio = GPIO_PA7, 1584 .pins = pinmux_pins,
1584 .last_gpio = GPIO_FN_LCD_DATA0, 1585 .nr_pins = ARRAY_SIZE(pinmux_pins),
1586 .func_gpios = pinmux_func_gpios,
1587 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
1585 1588
1586 .gpios = pinmux_gpios,
1587 .cfg_regs = pinmux_config_regs, 1589 .cfg_regs = pinmux_config_regs,
1588 .data_regs = pinmux_data_regs, 1590 .data_regs = pinmux_data_regs,
1589 1591
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
index 2ba5639dcf34..284675249ed9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
@@ -604,7 +604,7 @@ enum {
604 PINMUX_MARK_END, 604 PINMUX_MARK_END,
605}; 605};
606 606
607static pinmux_enum_t pinmux_data[] = { 607static const pinmux_enum_t pinmux_data[] = {
608 608
609 /* Port A */ 609 /* Port A */
610 PINMUX_DATA(PA3_DATA, PA3_IN), 610 PINMUX_DATA(PA3_DATA, PA3_IN),
@@ -1072,7 +1072,7 @@ static pinmux_enum_t pinmux_data[] = {
1072 PINMUX_DATA(SD_D2_MARK, PK0MD_10), 1072 PINMUX_DATA(SD_D2_MARK, PK0MD_10),
1073}; 1073};
1074 1074
1075static struct pinmux_gpio pinmux_gpios[] = { 1075static struct sh_pfc_pin pinmux_pins[] = {
1076 1076
1077 /* Port A */ 1077 /* Port A */
1078 PINMUX_GPIO(GPIO_PA3, PA3_DATA), 1078 PINMUX_GPIO(GPIO_PA3, PA3_DATA),
@@ -1216,257 +1216,261 @@ static struct pinmux_gpio pinmux_gpios[] = {
1216 PINMUX_GPIO(GPIO_PK2, PK2_DATA), 1216 PINMUX_GPIO(GPIO_PK2, PK2_DATA),
1217 PINMUX_GPIO(GPIO_PK1, PK1_DATA), 1217 PINMUX_GPIO(GPIO_PK1, PK1_DATA),
1218 PINMUX_GPIO(GPIO_PK0, PK0_DATA), 1218 PINMUX_GPIO(GPIO_PK0, PK0_DATA),
1219};
1220
1221#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
1219 1222
1223static const struct pinmux_func pinmux_func_gpios[] = {
1220 /* INTC */ 1224 /* INTC */
1221 PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK), 1225 GPIO_FN(PINT7_PG),
1222 PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK), 1226 GPIO_FN(PINT6_PG),
1223 PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK), 1227 GPIO_FN(PINT5_PG),
1224 PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK), 1228 GPIO_FN(PINT4_PG),
1225 PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK), 1229 GPIO_FN(PINT3_PG),
1226 PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK), 1230 GPIO_FN(PINT2_PG),
1227 PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK), 1231 GPIO_FN(PINT1_PG),
1228 1232
1229 PINMUX_GPIO(GPIO_FN_IRQ7_PC, IRQ7_PC_MARK), 1233 GPIO_FN(IRQ7_PC),
1230 PINMUX_GPIO(GPIO_FN_IRQ6_PC, IRQ6_PC_MARK), 1234 GPIO_FN(IRQ6_PC),
1231 PINMUX_GPIO(GPIO_FN_IRQ5_PC, IRQ5_PC_MARK), 1235 GPIO_FN(IRQ5_PC),
1232 PINMUX_GPIO(GPIO_FN_IRQ4_PC, IRQ4_PC_MARK), 1236 GPIO_FN(IRQ4_PC),
1233 PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK), 1237 GPIO_FN(IRQ3_PG),
1234 PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK), 1238 GPIO_FN(IRQ2_PG),
1235 PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK), 1239 GPIO_FN(IRQ1_PJ),
1236 PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK), 1240 GPIO_FN(IRQ0_PJ),
1237 PINMUX_GPIO(GPIO_FN_IRQ3_PE, IRQ3_PE_MARK), 1241 GPIO_FN(IRQ3_PE),
1238 PINMUX_GPIO(GPIO_FN_IRQ2_PE, IRQ2_PE_MARK), 1242 GPIO_FN(IRQ2_PE),
1239 PINMUX_GPIO(GPIO_FN_IRQ1_PE, IRQ1_PE_MARK), 1243 GPIO_FN(IRQ1_PE),
1240 PINMUX_GPIO(GPIO_FN_IRQ0_PE, IRQ0_PE_MARK), 1244 GPIO_FN(IRQ0_PE),
1241 1245
1242 /* WDT */ 1246 /* WDT */
1243 PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), 1247 GPIO_FN(WDTOVF),
1244 1248
1245 /* CAN */ 1249 /* CAN */
1246 PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), 1250 GPIO_FN(CTX1),
1247 PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), 1251 GPIO_FN(CRX1),
1248 PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), 1252 GPIO_FN(CTX0),
1249 PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), 1253 GPIO_FN(CRX0),
1250 PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), 1254 GPIO_FN(CRX0_CRX1),
1251 1255
1252 /* DMAC */ 1256 /* DMAC */
1253 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), 1257 GPIO_FN(TEND0),
1254 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), 1258 GPIO_FN(DACK0),
1255 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 1259 GPIO_FN(DREQ0),
1256 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), 1260 GPIO_FN(TEND1),
1257 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), 1261 GPIO_FN(DACK1),
1258 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 1262 GPIO_FN(DREQ1),
1259 1263
1260 /* ADC */ 1264 /* ADC */
1261 PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), 1265 GPIO_FN(ADTRG),
1262 1266
1263 /* BSCh */ 1267 /* BSCh */
1264 PINMUX_GPIO(GPIO_FN_A25, A25_MARK), 1268 GPIO_FN(A25),
1265 PINMUX_GPIO(GPIO_FN_A24, A24_MARK), 1269 GPIO_FN(A24),
1266 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 1270 GPIO_FN(A23),
1267 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 1271 GPIO_FN(A22),
1268 PINMUX_GPIO(GPIO_FN_A21, A21_MARK), 1272 GPIO_FN(A21),
1269 PINMUX_GPIO(GPIO_FN_A20, A20_MARK), 1273 GPIO_FN(A20),
1270 PINMUX_GPIO(GPIO_FN_A19, A19_MARK), 1274 GPIO_FN(A19),
1271 PINMUX_GPIO(GPIO_FN_A18, A18_MARK), 1275 GPIO_FN(A18),
1272 PINMUX_GPIO(GPIO_FN_A17, A17_MARK), 1276 GPIO_FN(A17),
1273 PINMUX_GPIO(GPIO_FN_A16, A16_MARK), 1277 GPIO_FN(A16),
1274 PINMUX_GPIO(GPIO_FN_A15, A15_MARK), 1278 GPIO_FN(A15),
1275 PINMUX_GPIO(GPIO_FN_A14, A14_MARK), 1279 GPIO_FN(A14),
1276 PINMUX_GPIO(GPIO_FN_A13, A13_MARK), 1280 GPIO_FN(A13),
1277 PINMUX_GPIO(GPIO_FN_A12, A12_MARK), 1281 GPIO_FN(A12),
1278 PINMUX_GPIO(GPIO_FN_A11, A11_MARK), 1282 GPIO_FN(A11),
1279 PINMUX_GPIO(GPIO_FN_A10, A10_MARK), 1283 GPIO_FN(A10),
1280 PINMUX_GPIO(GPIO_FN_A9, A9_MARK), 1284 GPIO_FN(A9),
1281 PINMUX_GPIO(GPIO_FN_A8, A8_MARK), 1285 GPIO_FN(A8),
1282 PINMUX_GPIO(GPIO_FN_A7, A7_MARK), 1286 GPIO_FN(A7),
1283 PINMUX_GPIO(GPIO_FN_A6, A6_MARK), 1287 GPIO_FN(A6),
1284 PINMUX_GPIO(GPIO_FN_A5, A5_MARK), 1288 GPIO_FN(A5),
1285 PINMUX_GPIO(GPIO_FN_A4, A4_MARK), 1289 GPIO_FN(A4),
1286 PINMUX_GPIO(GPIO_FN_A3, A3_MARK), 1290 GPIO_FN(A3),
1287 PINMUX_GPIO(GPIO_FN_A2, A2_MARK), 1291 GPIO_FN(A2),
1288 PINMUX_GPIO(GPIO_FN_A1, A1_MARK), 1292 GPIO_FN(A1),
1289 PINMUX_GPIO(GPIO_FN_A0, A0_MARK), 1293 GPIO_FN(A0),
1290 1294
1291 PINMUX_GPIO(GPIO_FN_D15, D15_MARK), 1295 GPIO_FN(D15),
1292 PINMUX_GPIO(GPIO_FN_D14, D14_MARK), 1296 GPIO_FN(D14),
1293 PINMUX_GPIO(GPIO_FN_D13, D13_MARK), 1297 GPIO_FN(D13),
1294 PINMUX_GPIO(GPIO_FN_D12, D12_MARK), 1298 GPIO_FN(D12),
1295 PINMUX_GPIO(GPIO_FN_D11, D11_MARK), 1299 GPIO_FN(D11),
1296 PINMUX_GPIO(GPIO_FN_D10, D10_MARK), 1300 GPIO_FN(D10),
1297 PINMUX_GPIO(GPIO_FN_D9, D9_MARK), 1301 GPIO_FN(D9),
1298 PINMUX_GPIO(GPIO_FN_D8, D8_MARK), 1302 GPIO_FN(D8),
1299 PINMUX_GPIO(GPIO_FN_D7, D7_MARK), 1303 GPIO_FN(D7),
1300 PINMUX_GPIO(GPIO_FN_D6, D6_MARK), 1304 GPIO_FN(D6),
1301 PINMUX_GPIO(GPIO_FN_D5, D5_MARK), 1305 GPIO_FN(D5),
1302 PINMUX_GPIO(GPIO_FN_D4, D4_MARK), 1306 GPIO_FN(D4),
1303 PINMUX_GPIO(GPIO_FN_D3, D3_MARK), 1307 GPIO_FN(D3),
1304 PINMUX_GPIO(GPIO_FN_D2, D2_MARK), 1308 GPIO_FN(D2),
1305 PINMUX_GPIO(GPIO_FN_D1, D1_MARK), 1309 GPIO_FN(D1),
1306 PINMUX_GPIO(GPIO_FN_D0, D0_MARK), 1310 GPIO_FN(D0),
1307 1311
1308 PINMUX_GPIO(GPIO_FN_BS, BS_MARK), 1312 GPIO_FN(BS),
1309 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), 1313 GPIO_FN(CS4),
1310 PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), 1314 GPIO_FN(CS3),
1311 PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), 1315 GPIO_FN(CS2),
1312 PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), 1316 GPIO_FN(CS1),
1313 PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), 1317 GPIO_FN(CS0),
1314 PINMUX_GPIO(GPIO_FN_CS6CE1B, CS6CE1B_MARK), 1318 GPIO_FN(CS6CE1B),
1315 PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK), 1319 GPIO_FN(CS5CE1A),
1316 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), 1320 GPIO_FN(CE2A),
1317 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), 1321 GPIO_FN(CE2B),
1318 PINMUX_GPIO(GPIO_FN_RD, RD_MARK), 1322 GPIO_FN(RD),
1319 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), 1323 GPIO_FN(RDWR),
1320 PINMUX_GPIO(GPIO_FN_ICIOWRAH, ICIOWRAH_MARK), 1324 GPIO_FN(ICIOWRAH),
1321 PINMUX_GPIO(GPIO_FN_ICIORD, ICIORD_MARK), 1325 GPIO_FN(ICIORD),
1322 PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK), 1326 GPIO_FN(WE1DQMUWE),
1323 PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK), 1327 GPIO_FN(WE0DQML),
1324 PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), 1328 GPIO_FN(RAS),
1325 PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), 1329 GPIO_FN(CAS),
1326 PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), 1330 GPIO_FN(CKE),
1327 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), 1331 GPIO_FN(WAIT),
1328 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), 1332 GPIO_FN(BREQ),
1329 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), 1333 GPIO_FN(BACK),
1330 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 1334 GPIO_FN(IOIS16),
1331 1335
1332 /* TMU */ 1336 /* TMU */
1333 PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), 1337 GPIO_FN(TIOC4D),
1334 PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), 1338 GPIO_FN(TIOC4C),
1335 PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), 1339 GPIO_FN(TIOC4B),
1336 PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), 1340 GPIO_FN(TIOC4A),
1337 PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), 1341 GPIO_FN(TIOC3D),
1338 PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), 1342 GPIO_FN(TIOC3C),
1339 PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), 1343 GPIO_FN(TIOC3B),
1340 PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), 1344 GPIO_FN(TIOC3A),
1341 PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), 1345 GPIO_FN(TIOC2B),
1342 PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), 1346 GPIO_FN(TIOC1B),
1343 PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), 1347 GPIO_FN(TIOC2A),
1344 PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), 1348 GPIO_FN(TIOC1A),
1345 PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), 1349 GPIO_FN(TIOC0D),
1346 PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), 1350 GPIO_FN(TIOC0C),
1347 PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), 1351 GPIO_FN(TIOC0B),
1348 PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), 1352 GPIO_FN(TIOC0A),
1349 PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK), 1353 GPIO_FN(TCLKD),
1350 PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK), 1354 GPIO_FN(TCLKC),
1351 PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK), 1355 GPIO_FN(TCLKB),
1352 PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK), 1356 GPIO_FN(TCLKA),
1353 1357
1354 /* SCIF */ 1358 /* SCIF */
1355 PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), 1359 GPIO_FN(TXD0),
1356 PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), 1360 GPIO_FN(RXD0),
1357 PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), 1361 GPIO_FN(SCK0),
1358 PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), 1362 GPIO_FN(TXD1),
1359 PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), 1363 GPIO_FN(RXD1),
1360 PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), 1364 GPIO_FN(SCK1),
1361 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), 1365 GPIO_FN(TXD2),
1362 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), 1366 GPIO_FN(RXD2),
1363 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), 1367 GPIO_FN(SCK2),
1364 PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), 1368 GPIO_FN(RTS3),
1365 PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), 1369 GPIO_FN(CTS3),
1366 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), 1370 GPIO_FN(TXD3),
1367 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), 1371 GPIO_FN(RXD3),
1368 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), 1372 GPIO_FN(SCK3),
1369 PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), 1373 GPIO_FN(TXD4),
1370 PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), 1374 GPIO_FN(RXD4),
1371 PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK), 1375 GPIO_FN(TXD5),
1372 PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK), 1376 GPIO_FN(RXD5),
1373 PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK), 1377 GPIO_FN(TXD6),
1374 PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK), 1378 GPIO_FN(RXD6),
1375 PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK), 1379 GPIO_FN(TXD7),
1376 PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK), 1380 GPIO_FN(RXD7),
1377 PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK), 1381 GPIO_FN(RTS1),
1378 PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK), 1382 GPIO_FN(CTS1),
1379 1383
1380 /* RSPI */ 1384 /* RSPI */
1381 PINMUX_GPIO(GPIO_FN_RSPCK0, RSPCK0_MARK), 1385 GPIO_FN(RSPCK0),
1382 PINMUX_GPIO(GPIO_FN_MOSI0, MOSI0_MARK), 1386 GPIO_FN(MOSI0),
1383 PINMUX_GPIO(GPIO_FN_MISO0_PF12, MISO0_PF12_MARK), 1387 GPIO_FN(MISO0_PF12),
1384 PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK), 1388 GPIO_FN(MISO1),
1385 PINMUX_GPIO(GPIO_FN_SSL00, SSL00_MARK), 1389 GPIO_FN(SSL00),
1386 PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK), 1390 GPIO_FN(RSPCK1),
1387 PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK), 1391 GPIO_FN(MOSI1),
1388 PINMUX_GPIO(GPIO_FN_MISO1_PG19, MISO1_PG19_MARK), 1392 GPIO_FN(MISO1_PG19),
1389 PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK), 1393 GPIO_FN(SSL10),
1390 1394
1391 /* IIC3 */ 1395 /* IIC3 */
1392 PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), 1396 GPIO_FN(SCL0),
1393 PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), 1397 GPIO_FN(SCL1),
1394 PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), 1398 GPIO_FN(SCL2),
1395 PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), 1399 GPIO_FN(SDA0),
1396 PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), 1400 GPIO_FN(SDA1),
1397 PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), 1401 GPIO_FN(SDA2),
1398 1402
1399 /* SSI */ 1403 /* SSI */
1400 PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), 1404 GPIO_FN(SSISCK0),
1401 PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), 1405 GPIO_FN(SSIWS0),
1402 PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK), 1406 GPIO_FN(SSITXD0),
1403 PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK), 1407 GPIO_FN(SSIRXD0),
1404 PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), 1408 GPIO_FN(SSIWS1),
1405 PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), 1409 GPIO_FN(SSIWS2),
1406 PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), 1410 GPIO_FN(SSIWS3),
1407 PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), 1411 GPIO_FN(SSISCK1),
1408 PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), 1412 GPIO_FN(SSISCK2),
1409 PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), 1413 GPIO_FN(SSISCK3),
1410 PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), 1414 GPIO_FN(SSIDATA1),
1411 PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), 1415 GPIO_FN(SSIDATA2),
1412 PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), 1416 GPIO_FN(SSIDATA3),
1413 PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), 1417 GPIO_FN(AUDIO_CLK),
1414 1418
1415 /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */ 1419 /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
1416 PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK), 1420 GPIO_FN(SIOFTXD),
1417 PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK), 1421 GPIO_FN(SIOFRXD),
1418 PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK), 1422 GPIO_FN(SIOFSYNC),
1419 PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK), 1423 GPIO_FN(SIOFSCK),
1420 1424
1421 /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */ 1425 /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
1422 PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK), 1426 GPIO_FN(SPDIF_IN),
1423 PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK), 1427 GPIO_FN(SPDIF_OUT),
1424 1428
1425 /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ 1429 /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
1426 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), 1430 GPIO_FN(FCE),
1427 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), 1431 GPIO_FN(FRB),
1428 1432
1429 /* VDC3 */ 1433 /* VDC3 */
1430 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), 1434 GPIO_FN(DV_CLK),
1431 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), 1435 GPIO_FN(DV_VSYNC),
1432 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), 1436 GPIO_FN(DV_HSYNC),
1433 1437
1434 PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK), 1438 GPIO_FN(DV_DATA7),
1435 PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK), 1439 GPIO_FN(DV_DATA6),
1436 PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK), 1440 GPIO_FN(DV_DATA5),
1437 PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK), 1441 GPIO_FN(DV_DATA4),
1438 PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK), 1442 GPIO_FN(DV_DATA3),
1439 PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK), 1443 GPIO_FN(DV_DATA2),
1440 PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK), 1444 GPIO_FN(DV_DATA1),
1441 PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK), 1445 GPIO_FN(DV_DATA0),
1442 1446
1443 PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), 1447 GPIO_FN(LCD_CLK),
1444 PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK), 1448 GPIO_FN(LCD_EXTCLK),
1445 PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK), 1449 GPIO_FN(LCD_VSYNC),
1446 PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK), 1450 GPIO_FN(LCD_HSYNC),
1447 PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK), 1451 GPIO_FN(LCD_DE),
1448 1452
1449 PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), 1453 GPIO_FN(LCD_DATA15),
1450 PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), 1454 GPIO_FN(LCD_DATA14),
1451 PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), 1455 GPIO_FN(LCD_DATA13),
1452 PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), 1456 GPIO_FN(LCD_DATA12),
1453 PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), 1457 GPIO_FN(LCD_DATA11),
1454 PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), 1458 GPIO_FN(LCD_DATA10),
1455 PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), 1459 GPIO_FN(LCD_DATA9),
1456 PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), 1460 GPIO_FN(LCD_DATA8),
1457 PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), 1461 GPIO_FN(LCD_DATA7),
1458 PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), 1462 GPIO_FN(LCD_DATA6),
1459 PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), 1463 GPIO_FN(LCD_DATA5),
1460 PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), 1464 GPIO_FN(LCD_DATA4),
1461 PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), 1465 GPIO_FN(LCD_DATA3),
1462 PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), 1466 GPIO_FN(LCD_DATA2),
1463 PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), 1467 GPIO_FN(LCD_DATA1),
1464 PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), 1468 GPIO_FN(LCD_DATA0),
1465 1469
1466 PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), 1470 GPIO_FN(LCD_M_DISP),
1467}; 1471};
1468 1472
1469static struct pinmux_cfg_reg pinmux_config_regs[] = { 1473static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1470 { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) { 1474 { PINMUX_CFG_REG("PAIOR0", 0xfffe3812, 16, 1) {
1471 0, 0, 0, 0, 0, 0, 0, 0, 1475 0, 0, 0, 0, 0, 0, 0, 0,
1472 0, 0, 0, 0, 0, 0, 0, 0, 1476 0, 0, 0, 0, 0, 0, 0, 0,
@@ -2032,7 +2036,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2032 {} 2036 {}
2033}; 2037};
2034 2038
2035static struct pinmux_data_reg pinmux_data_regs[] = { 2039static const struct pinmux_data_reg pinmux_data_regs[] = {
2036 { PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) { 2040 { PINMUX_DATA_REG("PADR1", 0xfffe3814, 16) {
2037 0, 0, 0, 0, 0, 0, 0, PA3_DATA, 2041 0, 0, 0, 0, 0, 0, 0, PA3_DATA,
2038 0, 0, 0, 0, 0, 0, 0, PA2_DATA } 2042 0, 0, 0, 0, 0, 0, 0, PA2_DATA }
@@ -2110,19 +2114,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2110 { } 2114 { }
2111}; 2115};
2112 2116
2113struct sh_pfc_soc_info sh7264_pinmux_info = { 2117const struct sh_pfc_soc_info sh7264_pinmux_info = {
2114 .name = "sh7264_pfc", 2118 .name = "sh7264_pfc",
2115 .reserved_id = PINMUX_RESERVED,
2116 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2117 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, 2119 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
2118 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, 2120 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
2119 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2120 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2121 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2121 2122
2122 .first_gpio = GPIO_PA3, 2123 .pins = pinmux_pins,
2123 .last_gpio = GPIO_FN_LCD_M_DISP, 2124 .nr_pins = ARRAY_SIZE(pinmux_pins),
2125 .func_gpios = pinmux_func_gpios,
2126 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2124 2127
2125 .gpios = pinmux_gpios,
2126 .cfg_regs = pinmux_config_regs, 2128 .cfg_regs = pinmux_config_regs,
2127 .data_regs = pinmux_data_regs, 2129 .data_regs = pinmux_data_regs,
2128 2130
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
index b1b5d6d4ad76..4c401a74acd5 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
@@ -781,7 +781,7 @@ enum {
781 PINMUX_MARK_END, 781 PINMUX_MARK_END,
782}; 782};
783 783
784static pinmux_enum_t pinmux_data[] = { 784static const pinmux_enum_t pinmux_data[] = {
785 785
786 /* Port A */ 786 /* Port A */
787 PINMUX_DATA(PA1_DATA, PA1_IN), 787 PINMUX_DATA(PA1_DATA, PA1_IN),
@@ -1452,7 +1452,7 @@ static pinmux_enum_t pinmux_data[] = {
1452 PINMUX_DATA(PWM1A_MARK, PJ0MD_100), 1452 PINMUX_DATA(PWM1A_MARK, PJ0MD_100),
1453}; 1453};
1454 1454
1455static struct pinmux_gpio pinmux_gpios[] = { 1455static struct sh_pfc_pin pinmux_pins[] = {
1456 /* Port A */ 1456 /* Port A */
1457 PINMUX_GPIO(GPIO_PA1, PA1_DATA), 1457 PINMUX_GPIO(GPIO_PA1, PA1_DATA),
1458 PINMUX_GPIO(GPIO_PA0, PA0_DATA), 1458 PINMUX_GPIO(GPIO_PA0, PA0_DATA),
@@ -1613,339 +1613,343 @@ static struct pinmux_gpio pinmux_gpios[] = {
1613 PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), 1613 PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
1614 PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), 1614 PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
1615 PINMUX_GPIO(GPIO_PJ0, PJ0_DATA), 1615 PINMUX_GPIO(GPIO_PJ0, PJ0_DATA),
1616};
1617
1618#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
1616 1619
1620static const struct pinmux_func pinmux_func_gpios[] = {
1617 /* INTC */ 1621 /* INTC */
1618 PINMUX_GPIO(GPIO_FN_IRQ7_PG, IRQ7_PG_MARK), 1622 GPIO_FN(IRQ7_PG),
1619 PINMUX_GPIO(GPIO_FN_IRQ6_PG, IRQ6_PG_MARK), 1623 GPIO_FN(IRQ6_PG),
1620 PINMUX_GPIO(GPIO_FN_IRQ5_PG, IRQ5_PG_MARK), 1624 GPIO_FN(IRQ5_PG),
1621 PINMUX_GPIO(GPIO_FN_IRQ4_PG, IRQ4_PG_MARK), 1625 GPIO_FN(IRQ4_PG),
1622 PINMUX_GPIO(GPIO_FN_IRQ3_PG, IRQ3_PG_MARK), 1626 GPIO_FN(IRQ3_PG),
1623 PINMUX_GPIO(GPIO_FN_IRQ2_PG, IRQ2_PG_MARK), 1627 GPIO_FN(IRQ2_PG),
1624 PINMUX_GPIO(GPIO_FN_IRQ1_PG, IRQ1_PG_MARK), 1628 GPIO_FN(IRQ1_PG),
1625 PINMUX_GPIO(GPIO_FN_IRQ0_PG, IRQ0_PG_MARK), 1629 GPIO_FN(IRQ0_PG),
1626 PINMUX_GPIO(GPIO_FN_IRQ7_PF, IRQ7_PF_MARK), 1630 GPIO_FN(IRQ7_PF),
1627 PINMUX_GPIO(GPIO_FN_IRQ6_PF, IRQ6_PF_MARK), 1631 GPIO_FN(IRQ6_PF),
1628 PINMUX_GPIO(GPIO_FN_IRQ5_PF, IRQ5_PF_MARK), 1632 GPIO_FN(IRQ5_PF),
1629 PINMUX_GPIO(GPIO_FN_IRQ4_PF, IRQ4_PF_MARK), 1633 GPIO_FN(IRQ4_PF),
1630 PINMUX_GPIO(GPIO_FN_IRQ3_PJ, IRQ3_PJ_MARK), 1634 GPIO_FN(IRQ3_PJ),
1631 PINMUX_GPIO(GPIO_FN_IRQ2_PJ, IRQ2_PJ_MARK), 1635 GPIO_FN(IRQ2_PJ),
1632 PINMUX_GPIO(GPIO_FN_IRQ1_PJ, IRQ1_PJ_MARK), 1636 GPIO_FN(IRQ1_PJ),
1633 PINMUX_GPIO(GPIO_FN_IRQ0_PJ, IRQ0_PJ_MARK), 1637 GPIO_FN(IRQ0_PJ),
1634 PINMUX_GPIO(GPIO_FN_IRQ1_PC, IRQ1_PC_MARK), 1638 GPIO_FN(IRQ1_PC),
1635 PINMUX_GPIO(GPIO_FN_IRQ0_PC, IRQ0_PC_MARK), 1639 GPIO_FN(IRQ0_PC),
1636 1640
1637 PINMUX_GPIO(GPIO_FN_PINT7_PG, PINT7_PG_MARK), 1641 GPIO_FN(PINT7_PG),
1638 PINMUX_GPIO(GPIO_FN_PINT6_PG, PINT6_PG_MARK), 1642 GPIO_FN(PINT6_PG),
1639 PINMUX_GPIO(GPIO_FN_PINT5_PG, PINT5_PG_MARK), 1643 GPIO_FN(PINT5_PG),
1640 PINMUX_GPIO(GPIO_FN_PINT4_PG, PINT4_PG_MARK), 1644 GPIO_FN(PINT4_PG),
1641 PINMUX_GPIO(GPIO_FN_PINT3_PG, PINT3_PG_MARK), 1645 GPIO_FN(PINT3_PG),
1642 PINMUX_GPIO(GPIO_FN_PINT2_PG, PINT2_PG_MARK), 1646 GPIO_FN(PINT2_PG),
1643 PINMUX_GPIO(GPIO_FN_PINT1_PG, PINT1_PG_MARK), 1647 GPIO_FN(PINT1_PG),
1644 PINMUX_GPIO(GPIO_FN_PINT0_PG, PINT0_PG_MARK), 1648 GPIO_FN(PINT0_PG),
1645 PINMUX_GPIO(GPIO_FN_PINT7_PH, PINT7_PH_MARK), 1649 GPIO_FN(PINT7_PH),
1646 PINMUX_GPIO(GPIO_FN_PINT6_PH, PINT6_PH_MARK), 1650 GPIO_FN(PINT6_PH),
1647 PINMUX_GPIO(GPIO_FN_PINT5_PH, PINT5_PH_MARK), 1651 GPIO_FN(PINT5_PH),
1648 PINMUX_GPIO(GPIO_FN_PINT4_PH, PINT4_PH_MARK), 1652 GPIO_FN(PINT4_PH),
1649 PINMUX_GPIO(GPIO_FN_PINT3_PH, PINT3_PH_MARK), 1653 GPIO_FN(PINT3_PH),
1650 PINMUX_GPIO(GPIO_FN_PINT2_PH, PINT2_PH_MARK), 1654 GPIO_FN(PINT2_PH),
1651 PINMUX_GPIO(GPIO_FN_PINT1_PH, PINT1_PH_MARK), 1655 GPIO_FN(PINT1_PH),
1652 PINMUX_GPIO(GPIO_FN_PINT0_PH, PINT0_PH_MARK), 1656 GPIO_FN(PINT0_PH),
1653 PINMUX_GPIO(GPIO_FN_PINT7_PJ, PINT7_PJ_MARK), 1657 GPIO_FN(PINT7_PJ),
1654 PINMUX_GPIO(GPIO_FN_PINT6_PJ, PINT6_PJ_MARK), 1658 GPIO_FN(PINT6_PJ),
1655 PINMUX_GPIO(GPIO_FN_PINT5_PJ, PINT5_PJ_MARK), 1659 GPIO_FN(PINT5_PJ),
1656 PINMUX_GPIO(GPIO_FN_PINT4_PJ, PINT4_PJ_MARK), 1660 GPIO_FN(PINT4_PJ),
1657 PINMUX_GPIO(GPIO_FN_PINT3_PJ, PINT3_PJ_MARK), 1661 GPIO_FN(PINT3_PJ),
1658 PINMUX_GPIO(GPIO_FN_PINT2_PJ, PINT2_PJ_MARK), 1662 GPIO_FN(PINT2_PJ),
1659 PINMUX_GPIO(GPIO_FN_PINT1_PJ, PINT1_PJ_MARK), 1663 GPIO_FN(PINT1_PJ),
1660 PINMUX_GPIO(GPIO_FN_PINT0_PJ, PINT0_PJ_MARK), 1664 GPIO_FN(PINT0_PJ),
1661 1665
1662 /* WDT */ 1666 /* WDT */
1663 PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), 1667 GPIO_FN(WDTOVF),
1664 1668
1665 /* CAN */ 1669 /* CAN */
1666 PINMUX_GPIO(GPIO_FN_CTX1, CTX1_MARK), 1670 GPIO_FN(CTX1),
1667 PINMUX_GPIO(GPIO_FN_CRX1, CRX1_MARK), 1671 GPIO_FN(CRX1),
1668 PINMUX_GPIO(GPIO_FN_CTX0, CTX0_MARK), 1672 GPIO_FN(CTX0),
1669 PINMUX_GPIO(GPIO_FN_CRX0, CRX0_MARK), 1673 GPIO_FN(CRX0),
1670 PINMUX_GPIO(GPIO_FN_CRX0_CRX1, CRX0_CRX1_MARK), 1674 GPIO_FN(CRX0_CRX1),
1671 PINMUX_GPIO(GPIO_FN_CRX0_CRX1_CRX2, CRX0_CRX1_CRX2_MARK), 1675 GPIO_FN(CRX0_CRX1_CRX2),
1672 1676
1673 /* DMAC */ 1677 /* DMAC */
1674 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), 1678 GPIO_FN(TEND0),
1675 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), 1679 GPIO_FN(DACK0),
1676 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 1680 GPIO_FN(DREQ0),
1677 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), 1681 GPIO_FN(TEND1),
1678 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), 1682 GPIO_FN(DACK1),
1679 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 1683 GPIO_FN(DREQ1),
1680 1684
1681 /* ADC */ 1685 /* ADC */
1682 PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), 1686 GPIO_FN(ADTRG),
1683 1687
1684 /* BSCh */ 1688 /* BSCh */
1685 PINMUX_GPIO(GPIO_FN_A25, A25_MARK), 1689 GPIO_FN(A25),
1686 PINMUX_GPIO(GPIO_FN_A24, A24_MARK), 1690 GPIO_FN(A24),
1687 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 1691 GPIO_FN(A23),
1688 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 1692 GPIO_FN(A22),
1689 PINMUX_GPIO(GPIO_FN_A21, A21_MARK), 1693 GPIO_FN(A21),
1690 PINMUX_GPIO(GPIO_FN_A20, A20_MARK), 1694 GPIO_FN(A20),
1691 PINMUX_GPIO(GPIO_FN_A19, A19_MARK), 1695 GPIO_FN(A19),
1692 PINMUX_GPIO(GPIO_FN_A18, A18_MARK), 1696 GPIO_FN(A18),
1693 PINMUX_GPIO(GPIO_FN_A17, A17_MARK), 1697 GPIO_FN(A17),
1694 PINMUX_GPIO(GPIO_FN_A16, A16_MARK), 1698 GPIO_FN(A16),
1695 PINMUX_GPIO(GPIO_FN_A15, A15_MARK), 1699 GPIO_FN(A15),
1696 PINMUX_GPIO(GPIO_FN_A14, A14_MARK), 1700 GPIO_FN(A14),
1697 PINMUX_GPIO(GPIO_FN_A13, A13_MARK), 1701 GPIO_FN(A13),
1698 PINMUX_GPIO(GPIO_FN_A12, A12_MARK), 1702 GPIO_FN(A12),
1699 PINMUX_GPIO(GPIO_FN_A11, A11_MARK), 1703 GPIO_FN(A11),
1700 PINMUX_GPIO(GPIO_FN_A10, A10_MARK), 1704 GPIO_FN(A10),
1701 PINMUX_GPIO(GPIO_FN_A9, A9_MARK), 1705 GPIO_FN(A9),
1702 PINMUX_GPIO(GPIO_FN_A8, A8_MARK), 1706 GPIO_FN(A8),
1703 PINMUX_GPIO(GPIO_FN_A7, A7_MARK), 1707 GPIO_FN(A7),
1704 PINMUX_GPIO(GPIO_FN_A6, A6_MARK), 1708 GPIO_FN(A6),
1705 PINMUX_GPIO(GPIO_FN_A5, A5_MARK), 1709 GPIO_FN(A5),
1706 PINMUX_GPIO(GPIO_FN_A4, A4_MARK), 1710 GPIO_FN(A4),
1707 PINMUX_GPIO(GPIO_FN_A3, A3_MARK), 1711 GPIO_FN(A3),
1708 PINMUX_GPIO(GPIO_FN_A2, A2_MARK), 1712 GPIO_FN(A2),
1709 PINMUX_GPIO(GPIO_FN_A1, A1_MARK), 1713 GPIO_FN(A1),
1710 PINMUX_GPIO(GPIO_FN_A0, A0_MARK), 1714 GPIO_FN(A0),
1711 1715
1712 PINMUX_GPIO(GPIO_FN_D15, D15_MARK), 1716 GPIO_FN(D15),
1713 PINMUX_GPIO(GPIO_FN_D14, D14_MARK), 1717 GPIO_FN(D14),
1714 PINMUX_GPIO(GPIO_FN_D13, D13_MARK), 1718 GPIO_FN(D13),
1715 PINMUX_GPIO(GPIO_FN_D12, D12_MARK), 1719 GPIO_FN(D12),
1716 PINMUX_GPIO(GPIO_FN_D11, D11_MARK), 1720 GPIO_FN(D11),
1717 PINMUX_GPIO(GPIO_FN_D10, D10_MARK), 1721 GPIO_FN(D10),
1718 PINMUX_GPIO(GPIO_FN_D9, D9_MARK), 1722 GPIO_FN(D9),
1719 PINMUX_GPIO(GPIO_FN_D8, D8_MARK), 1723 GPIO_FN(D8),
1720 PINMUX_GPIO(GPIO_FN_D7, D7_MARK), 1724 GPIO_FN(D7),
1721 PINMUX_GPIO(GPIO_FN_D6, D6_MARK), 1725 GPIO_FN(D6),
1722 PINMUX_GPIO(GPIO_FN_D5, D5_MARK), 1726 GPIO_FN(D5),
1723 PINMUX_GPIO(GPIO_FN_D4, D4_MARK), 1727 GPIO_FN(D4),
1724 PINMUX_GPIO(GPIO_FN_D3, D3_MARK), 1728 GPIO_FN(D3),
1725 PINMUX_GPIO(GPIO_FN_D2, D2_MARK), 1729 GPIO_FN(D2),
1726 PINMUX_GPIO(GPIO_FN_D1, D1_MARK), 1730 GPIO_FN(D1),
1727 PINMUX_GPIO(GPIO_FN_D0, D0_MARK), 1731 GPIO_FN(D0),
1728 1732
1729 PINMUX_GPIO(GPIO_FN_BS, BS_MARK), 1733 GPIO_FN(BS),
1730 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), 1734 GPIO_FN(CS4),
1731 PINMUX_GPIO(GPIO_FN_CS3, CS3_MARK), 1735 GPIO_FN(CS3),
1732 PINMUX_GPIO(GPIO_FN_CS2, CS2_MARK), 1736 GPIO_FN(CS2),
1733 PINMUX_GPIO(GPIO_FN_CS1, CS1_MARK), 1737 GPIO_FN(CS1),
1734 PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), 1738 GPIO_FN(CS0),
1735 PINMUX_GPIO(GPIO_FN_CS5CE1A, CS5CE1A_MARK), 1739 GPIO_FN(CS5CE1A),
1736 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), 1740 GPIO_FN(CE2A),
1737 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), 1741 GPIO_FN(CE2B),
1738 PINMUX_GPIO(GPIO_FN_RD, RD_MARK), 1742 GPIO_FN(RD),
1739 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), 1743 GPIO_FN(RDWR),
1740 PINMUX_GPIO(GPIO_FN_WE3ICIOWRAHDQMUU, WE3ICIOWRAHDQMUU_MARK), 1744 GPIO_FN(WE3ICIOWRAHDQMUU),
1741 PINMUX_GPIO(GPIO_FN_WE2ICIORDDQMUL, WE2ICIORDDQMUL_MARK), 1745 GPIO_FN(WE2ICIORDDQMUL),
1742 PINMUX_GPIO(GPIO_FN_WE1DQMUWE, WE1DQMUWE_MARK), 1746 GPIO_FN(WE1DQMUWE),
1743 PINMUX_GPIO(GPIO_FN_WE0DQML, WE0DQML_MARK), 1747 GPIO_FN(WE0DQML),
1744 PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), 1748 GPIO_FN(RAS),
1745 PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), 1749 GPIO_FN(CAS),
1746 PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), 1750 GPIO_FN(CKE),
1747 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), 1751 GPIO_FN(WAIT),
1748 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), 1752 GPIO_FN(BREQ),
1749 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), 1753 GPIO_FN(BACK),
1750 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 1754 GPIO_FN(IOIS16),
1751 1755
1752 /* TMU */ 1756 /* TMU */
1753 PINMUX_GPIO(GPIO_FN_TIOC4D, TIOC4D_MARK), 1757 GPIO_FN(TIOC4D),
1754 PINMUX_GPIO(GPIO_FN_TIOC4C, TIOC4C_MARK), 1758 GPIO_FN(TIOC4C),
1755 PINMUX_GPIO(GPIO_FN_TIOC4B, TIOC4B_MARK), 1759 GPIO_FN(TIOC4B),
1756 PINMUX_GPIO(GPIO_FN_TIOC4A, TIOC4A_MARK), 1760 GPIO_FN(TIOC4A),
1757 PINMUX_GPIO(GPIO_FN_TIOC3D, TIOC3D_MARK), 1761 GPIO_FN(TIOC3D),
1758 PINMUX_GPIO(GPIO_FN_TIOC3C, TIOC3C_MARK), 1762 GPIO_FN(TIOC3C),
1759 PINMUX_GPIO(GPIO_FN_TIOC3B, TIOC3B_MARK), 1763 GPIO_FN(TIOC3B),
1760 PINMUX_GPIO(GPIO_FN_TIOC3A, TIOC3A_MARK), 1764 GPIO_FN(TIOC3A),
1761 PINMUX_GPIO(GPIO_FN_TIOC2B, TIOC2B_MARK), 1765 GPIO_FN(TIOC2B),
1762 PINMUX_GPIO(GPIO_FN_TIOC1B, TIOC1B_MARK), 1766 GPIO_FN(TIOC1B),
1763 PINMUX_GPIO(GPIO_FN_TIOC2A, TIOC2A_MARK), 1767 GPIO_FN(TIOC2A),
1764 PINMUX_GPIO(GPIO_FN_TIOC1A, TIOC1A_MARK), 1768 GPIO_FN(TIOC1A),
1765 PINMUX_GPIO(GPIO_FN_TIOC0D, TIOC0D_MARK), 1769 GPIO_FN(TIOC0D),
1766 PINMUX_GPIO(GPIO_FN_TIOC0C, TIOC0C_MARK), 1770 GPIO_FN(TIOC0C),
1767 PINMUX_GPIO(GPIO_FN_TIOC0B, TIOC0B_MARK), 1771 GPIO_FN(TIOC0B),
1768 PINMUX_GPIO(GPIO_FN_TIOC0A, TIOC0A_MARK), 1772 GPIO_FN(TIOC0A),
1769 PINMUX_GPIO(GPIO_FN_TCLKD, TCLKD_MARK), 1773 GPIO_FN(TCLKD),
1770 PINMUX_GPIO(GPIO_FN_TCLKC, TCLKC_MARK), 1774 GPIO_FN(TCLKC),
1771 PINMUX_GPIO(GPIO_FN_TCLKB, TCLKB_MARK), 1775 GPIO_FN(TCLKB),
1772 PINMUX_GPIO(GPIO_FN_TCLKA, TCLKA_MARK), 1776 GPIO_FN(TCLKA),
1773 1777
1774 /* SCIF */ 1778 /* SCIF */
1775 PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), 1779 GPIO_FN(SCK0),
1776 PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), 1780 GPIO_FN(TXD0),
1777 PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), 1781 GPIO_FN(RXD0),
1778 PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), 1782 GPIO_FN(SCK1),
1779 PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), 1783 GPIO_FN(TXD1),
1780 PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), 1784 GPIO_FN(RXD1),
1781 PINMUX_GPIO(GPIO_FN_RTS1, RTS1_MARK), 1785 GPIO_FN(RTS1),
1782 PINMUX_GPIO(GPIO_FN_CTS1, CTS1_MARK), 1786 GPIO_FN(CTS1),
1783 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), 1787 GPIO_FN(SCK2),
1784 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), 1788 GPIO_FN(TXD2),
1785 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), 1789 GPIO_FN(RXD2),
1786 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), 1790 GPIO_FN(SCK3),
1787 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), 1791 GPIO_FN(TXD3),
1788 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), 1792 GPIO_FN(RXD3),
1789 PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK), 1793 GPIO_FN(SCK4),
1790 PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), 1794 GPIO_FN(TXD4),
1791 PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), 1795 GPIO_FN(RXD4),
1792 PINMUX_GPIO(GPIO_FN_SCK5, SCK5_MARK), 1796 GPIO_FN(SCK5),
1793 PINMUX_GPIO(GPIO_FN_TXD5, TXD5_MARK), 1797 GPIO_FN(TXD5),
1794 PINMUX_GPIO(GPIO_FN_RXD5, RXD5_MARK), 1798 GPIO_FN(RXD5),
1795 PINMUX_GPIO(GPIO_FN_RTS5, RTS5_MARK), 1799 GPIO_FN(RTS5),
1796 PINMUX_GPIO(GPIO_FN_CTS5, CTS5_MARK), 1800 GPIO_FN(CTS5),
1797 PINMUX_GPIO(GPIO_FN_SCK6, SCK6_MARK), 1801 GPIO_FN(SCK6),
1798 PINMUX_GPIO(GPIO_FN_TXD6, TXD6_MARK), 1802 GPIO_FN(TXD6),
1799 PINMUX_GPIO(GPIO_FN_RXD6, RXD6_MARK), 1803 GPIO_FN(RXD6),
1800 PINMUX_GPIO(GPIO_FN_SCK7, SCK7_MARK), 1804 GPIO_FN(SCK7),
1801 PINMUX_GPIO(GPIO_FN_TXD7, TXD7_MARK), 1805 GPIO_FN(TXD7),
1802 PINMUX_GPIO(GPIO_FN_RXD7, RXD7_MARK), 1806 GPIO_FN(RXD7),
1803 PINMUX_GPIO(GPIO_FN_RTS7, RTS7_MARK), 1807 GPIO_FN(RTS7),
1804 PINMUX_GPIO(GPIO_FN_CTS7, CTS7_MARK), 1808 GPIO_FN(CTS7),
1805 1809
1806 /* RSPI */ 1810 /* RSPI */
1807 PINMUX_GPIO(GPIO_FN_RSPCK0_PJ16, RSPCK0_PJ16_MARK), 1811 GPIO_FN(RSPCK0_PJ16),
1808 PINMUX_GPIO(GPIO_FN_SSL00_PJ17, SSL00_PJ17_MARK), 1812 GPIO_FN(SSL00_PJ17),
1809 PINMUX_GPIO(GPIO_FN_MOSI0_PJ18, MOSI0_PJ18_MARK), 1813 GPIO_FN(MOSI0_PJ18),
1810 PINMUX_GPIO(GPIO_FN_MISO0_PJ19, MISO0_PJ19_MARK), 1814 GPIO_FN(MISO0_PJ19),
1811 PINMUX_GPIO(GPIO_FN_RSPCK0_PB17, RSPCK0_PB17_MARK), 1815 GPIO_FN(RSPCK0_PB17),
1812 PINMUX_GPIO(GPIO_FN_SSL00_PB18, SSL00_PB18_MARK), 1816 GPIO_FN(SSL00_PB18),
1813 PINMUX_GPIO(GPIO_FN_MOSI0_PB19, MOSI0_PB19_MARK), 1817 GPIO_FN(MOSI0_PB19),
1814 PINMUX_GPIO(GPIO_FN_MISO0_PB20, MISO0_PB20_MARK), 1818 GPIO_FN(MISO0_PB20),
1815 PINMUX_GPIO(GPIO_FN_RSPCK1, RSPCK1_MARK), 1819 GPIO_FN(RSPCK1),
1816 PINMUX_GPIO(GPIO_FN_MOSI1, MOSI1_MARK), 1820 GPIO_FN(MOSI1),
1817 PINMUX_GPIO(GPIO_FN_MISO1, MISO1_MARK), 1821 GPIO_FN(MISO1),
1818 PINMUX_GPIO(GPIO_FN_SSL10, SSL10_MARK), 1822 GPIO_FN(SSL10),
1819 1823
1820 /* IIC3 */ 1824 /* IIC3 */
1821 PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), 1825 GPIO_FN(SCL0),
1822 PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), 1826 GPIO_FN(SCL1),
1823 PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), 1827 GPIO_FN(SCL2),
1824 PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), 1828 GPIO_FN(SDA0),
1825 PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), 1829 GPIO_FN(SDA1),
1826 PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), 1830 GPIO_FN(SDA2),
1827 1831
1828 /* SSI */ 1832 /* SSI */
1829 PINMUX_GPIO(GPIO_FN_SSISCK0, SSISCK0_MARK), 1833 GPIO_FN(SSISCK0),
1830 PINMUX_GPIO(GPIO_FN_SSIWS0, SSIWS0_MARK), 1834 GPIO_FN(SSIWS0),
1831 PINMUX_GPIO(GPIO_FN_SSITXD0, SSITXD0_MARK), 1835 GPIO_FN(SSITXD0),
1832 PINMUX_GPIO(GPIO_FN_SSIRXD0, SSIRXD0_MARK), 1836 GPIO_FN(SSIRXD0),
1833 PINMUX_GPIO(GPIO_FN_SSIWS1, SSIWS1_MARK), 1837 GPIO_FN(SSIWS1),
1834 PINMUX_GPIO(GPIO_FN_SSIWS2, SSIWS2_MARK), 1838 GPIO_FN(SSIWS2),
1835 PINMUX_GPIO(GPIO_FN_SSIWS3, SSIWS3_MARK), 1839 GPIO_FN(SSIWS3),
1836 PINMUX_GPIO(GPIO_FN_SSISCK1, SSISCK1_MARK), 1840 GPIO_FN(SSISCK1),
1837 PINMUX_GPIO(GPIO_FN_SSISCK2, SSISCK2_MARK), 1841 GPIO_FN(SSISCK2),
1838 PINMUX_GPIO(GPIO_FN_SSISCK3, SSISCK3_MARK), 1842 GPIO_FN(SSISCK3),
1839 PINMUX_GPIO(GPIO_FN_SSIDATA1, SSIDATA1_MARK), 1843 GPIO_FN(SSIDATA1),
1840 PINMUX_GPIO(GPIO_FN_SSIDATA2, SSIDATA2_MARK), 1844 GPIO_FN(SSIDATA2),
1841 PINMUX_GPIO(GPIO_FN_SSIDATA3, SSIDATA3_MARK), 1845 GPIO_FN(SSIDATA3),
1842 PINMUX_GPIO(GPIO_FN_AUDIO_CLK, AUDIO_CLK_MARK), 1846 GPIO_FN(AUDIO_CLK),
1843 PINMUX_GPIO(GPIO_FN_AUDIO_XOUT, AUDIO_XOUT_MARK), 1847 GPIO_FN(AUDIO_XOUT),
1844 1848
1845 /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */ 1849 /* SIOF */ /* NOTE Shares AUDIO_CLK with SSI */
1846 PINMUX_GPIO(GPIO_FN_SIOFTXD, SIOFTXD_MARK), 1850 GPIO_FN(SIOFTXD),
1847 PINMUX_GPIO(GPIO_FN_SIOFRXD, SIOFRXD_MARK), 1851 GPIO_FN(SIOFRXD),
1848 PINMUX_GPIO(GPIO_FN_SIOFSYNC, SIOFSYNC_MARK), 1852 GPIO_FN(SIOFSYNC),
1849 PINMUX_GPIO(GPIO_FN_SIOFSCK, SIOFSCK_MARK), 1853 GPIO_FN(SIOFSCK),
1850 1854
1851 /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */ 1855 /* SPDIF */ /* NOTE Shares AUDIO_CLK with SSI */
1852 PINMUX_GPIO(GPIO_FN_SPDIF_IN, SPDIF_IN_MARK), 1856 GPIO_FN(SPDIF_IN),
1853 PINMUX_GPIO(GPIO_FN_SPDIF_OUT, SPDIF_OUT_MARK), 1857 GPIO_FN(SPDIF_OUT),
1854 1858
1855 /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */ 1859 /* NANDFMC */ /* NOTE Controller is not available in boot mode 0 */
1856 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), 1860 GPIO_FN(FCE),
1857 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), 1861 GPIO_FN(FRB),
1858 1862
1859 /* VDC3 */ 1863 /* VDC3 */
1860 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), 1864 GPIO_FN(DV_CLK),
1861 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), 1865 GPIO_FN(DV_VSYNC),
1862 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), 1866 GPIO_FN(DV_HSYNC),
1863 1867
1864 PINMUX_GPIO(GPIO_FN_DV_DATA23, DV_DATA23_MARK), 1868 GPIO_FN(DV_DATA23),
1865 PINMUX_GPIO(GPIO_FN_DV_DATA22, DV_DATA22_MARK), 1869 GPIO_FN(DV_DATA22),
1866 PINMUX_GPIO(GPIO_FN_DV_DATA21, DV_DATA21_MARK), 1870 GPIO_FN(DV_DATA21),
1867 PINMUX_GPIO(GPIO_FN_DV_DATA20, DV_DATA20_MARK), 1871 GPIO_FN(DV_DATA20),
1868 PINMUX_GPIO(GPIO_FN_DV_DATA19, DV_DATA19_MARK), 1872 GPIO_FN(DV_DATA19),
1869 PINMUX_GPIO(GPIO_FN_DV_DATA18, DV_DATA18_MARK), 1873 GPIO_FN(DV_DATA18),
1870 PINMUX_GPIO(GPIO_FN_DV_DATA17, DV_DATA17_MARK), 1874 GPIO_FN(DV_DATA17),
1871 PINMUX_GPIO(GPIO_FN_DV_DATA16, DV_DATA16_MARK), 1875 GPIO_FN(DV_DATA16),
1872 PINMUX_GPIO(GPIO_FN_DV_DATA15, DV_DATA15_MARK), 1876 GPIO_FN(DV_DATA15),
1873 PINMUX_GPIO(GPIO_FN_DV_DATA14, DV_DATA14_MARK), 1877 GPIO_FN(DV_DATA14),
1874 PINMUX_GPIO(GPIO_FN_DV_DATA13, DV_DATA13_MARK), 1878 GPIO_FN(DV_DATA13),
1875 PINMUX_GPIO(GPIO_FN_DV_DATA12, DV_DATA12_MARK), 1879 GPIO_FN(DV_DATA12),
1876 PINMUX_GPIO(GPIO_FN_DV_DATA11, DV_DATA11_MARK), 1880 GPIO_FN(DV_DATA11),
1877 PINMUX_GPIO(GPIO_FN_DV_DATA10, DV_DATA10_MARK), 1881 GPIO_FN(DV_DATA10),
1878 PINMUX_GPIO(GPIO_FN_DV_DATA9, DV_DATA9_MARK), 1882 GPIO_FN(DV_DATA9),
1879 PINMUX_GPIO(GPIO_FN_DV_DATA8, DV_DATA8_MARK), 1883 GPIO_FN(DV_DATA8),
1880 PINMUX_GPIO(GPIO_FN_DV_DATA7, DV_DATA7_MARK), 1884 GPIO_FN(DV_DATA7),
1881 PINMUX_GPIO(GPIO_FN_DV_DATA6, DV_DATA6_MARK), 1885 GPIO_FN(DV_DATA6),
1882 PINMUX_GPIO(GPIO_FN_DV_DATA5, DV_DATA5_MARK), 1886 GPIO_FN(DV_DATA5),
1883 PINMUX_GPIO(GPIO_FN_DV_DATA4, DV_DATA4_MARK), 1887 GPIO_FN(DV_DATA4),
1884 PINMUX_GPIO(GPIO_FN_DV_DATA3, DV_DATA3_MARK), 1888 GPIO_FN(DV_DATA3),
1885 PINMUX_GPIO(GPIO_FN_DV_DATA2, DV_DATA2_MARK), 1889 GPIO_FN(DV_DATA2),
1886 PINMUX_GPIO(GPIO_FN_DV_DATA1, DV_DATA1_MARK), 1890 GPIO_FN(DV_DATA1),
1887 PINMUX_GPIO(GPIO_FN_DV_DATA0, DV_DATA0_MARK), 1891 GPIO_FN(DV_DATA0),
1888 1892
1889 PINMUX_GPIO(GPIO_FN_LCD_CLK, LCD_CLK_MARK), 1893 GPIO_FN(LCD_CLK),
1890 PINMUX_GPIO(GPIO_FN_LCD_EXTCLK, LCD_EXTCLK_MARK), 1894 GPIO_FN(LCD_EXTCLK),
1891 PINMUX_GPIO(GPIO_FN_LCD_VSYNC, LCD_VSYNC_MARK), 1895 GPIO_FN(LCD_VSYNC),
1892 PINMUX_GPIO(GPIO_FN_LCD_HSYNC, LCD_HSYNC_MARK), 1896 GPIO_FN(LCD_HSYNC),
1893 PINMUX_GPIO(GPIO_FN_LCD_DE, LCD_DE_MARK), 1897 GPIO_FN(LCD_DE),
1894 1898
1895 PINMUX_GPIO(GPIO_FN_LCD_DATA23_PG23, LCD_DATA23_PG23_MARK), 1899 GPIO_FN(LCD_DATA23_PG23),
1896 PINMUX_GPIO(GPIO_FN_LCD_DATA22_PG22, LCD_DATA22_PG22_MARK), 1900 GPIO_FN(LCD_DATA22_PG22),
1897 PINMUX_GPIO(GPIO_FN_LCD_DATA21_PG21, LCD_DATA21_PG21_MARK), 1901 GPIO_FN(LCD_DATA21_PG21),
1898 PINMUX_GPIO(GPIO_FN_LCD_DATA20_PG20, LCD_DATA20_PG20_MARK), 1902 GPIO_FN(LCD_DATA20_PG20),
1899 PINMUX_GPIO(GPIO_FN_LCD_DATA19_PG19, LCD_DATA19_PG19_MARK), 1903 GPIO_FN(LCD_DATA19_PG19),
1900 PINMUX_GPIO(GPIO_FN_LCD_DATA18_PG18, LCD_DATA18_PG18_MARK), 1904 GPIO_FN(LCD_DATA18_PG18),
1901 PINMUX_GPIO(GPIO_FN_LCD_DATA17_PG17, LCD_DATA17_PG17_MARK), 1905 GPIO_FN(LCD_DATA17_PG17),
1902 PINMUX_GPIO(GPIO_FN_LCD_DATA16_PG16, LCD_DATA16_PG16_MARK), 1906 GPIO_FN(LCD_DATA16_PG16),
1903 PINMUX_GPIO(GPIO_FN_LCD_DATA15_PG15, LCD_DATA15_PG15_MARK), 1907 GPIO_FN(LCD_DATA15_PG15),
1904 PINMUX_GPIO(GPIO_FN_LCD_DATA14_PG14, LCD_DATA14_PG14_MARK), 1908 GPIO_FN(LCD_DATA14_PG14),
1905 PINMUX_GPIO(GPIO_FN_LCD_DATA13_PG13, LCD_DATA13_PG13_MARK), 1909 GPIO_FN(LCD_DATA13_PG13),
1906 PINMUX_GPIO(GPIO_FN_LCD_DATA12_PG12, LCD_DATA12_PG12_MARK), 1910 GPIO_FN(LCD_DATA12_PG12),
1907 PINMUX_GPIO(GPIO_FN_LCD_DATA11_PG11, LCD_DATA11_PG11_MARK), 1911 GPIO_FN(LCD_DATA11_PG11),
1908 PINMUX_GPIO(GPIO_FN_LCD_DATA10_PG10, LCD_DATA10_PG10_MARK), 1912 GPIO_FN(LCD_DATA10_PG10),
1909 PINMUX_GPIO(GPIO_FN_LCD_DATA9_PG9, LCD_DATA9_PG9_MARK), 1913 GPIO_FN(LCD_DATA9_PG9),
1910 PINMUX_GPIO(GPIO_FN_LCD_DATA8_PG8, LCD_DATA8_PG8_MARK), 1914 GPIO_FN(LCD_DATA8_PG8),
1911 PINMUX_GPIO(GPIO_FN_LCD_DATA7_PG7, LCD_DATA7_PG7_MARK), 1915 GPIO_FN(LCD_DATA7_PG7),
1912 PINMUX_GPIO(GPIO_FN_LCD_DATA6_PG6, LCD_DATA6_PG6_MARK), 1916 GPIO_FN(LCD_DATA6_PG6),
1913 PINMUX_GPIO(GPIO_FN_LCD_DATA5_PG5, LCD_DATA5_PG5_MARK), 1917 GPIO_FN(LCD_DATA5_PG5),
1914 PINMUX_GPIO(GPIO_FN_LCD_DATA4_PG4, LCD_DATA4_PG4_MARK), 1918 GPIO_FN(LCD_DATA4_PG4),
1915 PINMUX_GPIO(GPIO_FN_LCD_DATA3_PG3, LCD_DATA3_PG3_MARK), 1919 GPIO_FN(LCD_DATA3_PG3),
1916 PINMUX_GPIO(GPIO_FN_LCD_DATA2_PG2, LCD_DATA2_PG2_MARK), 1920 GPIO_FN(LCD_DATA2_PG2),
1917 PINMUX_GPIO(GPIO_FN_LCD_DATA1_PG1, LCD_DATA1_PG1_MARK), 1921 GPIO_FN(LCD_DATA1_PG1),
1918 PINMUX_GPIO(GPIO_FN_LCD_DATA0_PG0, LCD_DATA0_PG0_MARK), 1922 GPIO_FN(LCD_DATA0_PG0),
1919 1923
1920 PINMUX_GPIO(GPIO_FN_LCD_DATA23_PJ23, LCD_DATA23_PJ23_MARK), 1924 GPIO_FN(LCD_DATA23_PJ23),
1921 PINMUX_GPIO(GPIO_FN_LCD_DATA22_PJ22, LCD_DATA22_PJ22_MARK), 1925 GPIO_FN(LCD_DATA22_PJ22),
1922 PINMUX_GPIO(GPIO_FN_LCD_DATA21_PJ21, LCD_DATA21_PJ21_MARK), 1926 GPIO_FN(LCD_DATA21_PJ21),
1923 PINMUX_GPIO(GPIO_FN_LCD_DATA20_PJ20, LCD_DATA20_PJ20_MARK), 1927 GPIO_FN(LCD_DATA20_PJ20),
1924 PINMUX_GPIO(GPIO_FN_LCD_DATA19_PJ19, LCD_DATA19_PJ19_MARK), 1928 GPIO_FN(LCD_DATA19_PJ19),
1925 PINMUX_GPIO(GPIO_FN_LCD_DATA18_PJ18, LCD_DATA18_PJ18_MARK), 1929 GPIO_FN(LCD_DATA18_PJ18),
1926 PINMUX_GPIO(GPIO_FN_LCD_DATA17_PJ17, LCD_DATA17_PJ17_MARK), 1930 GPIO_FN(LCD_DATA17_PJ17),
1927 PINMUX_GPIO(GPIO_FN_LCD_DATA16_PJ16, LCD_DATA16_PJ16_MARK), 1931 GPIO_FN(LCD_DATA16_PJ16),
1928 PINMUX_GPIO(GPIO_FN_LCD_DATA15_PJ15, LCD_DATA15_PJ15_MARK), 1932 GPIO_FN(LCD_DATA15_PJ15),
1929 PINMUX_GPIO(GPIO_FN_LCD_DATA14_PJ14, LCD_DATA14_PJ14_MARK), 1933 GPIO_FN(LCD_DATA14_PJ14),
1930 PINMUX_GPIO(GPIO_FN_LCD_DATA13_PJ13, LCD_DATA13_PJ13_MARK), 1934 GPIO_FN(LCD_DATA13_PJ13),
1931 PINMUX_GPIO(GPIO_FN_LCD_DATA12_PJ12, LCD_DATA12_PJ12_MARK), 1935 GPIO_FN(LCD_DATA12_PJ12),
1932 PINMUX_GPIO(GPIO_FN_LCD_DATA11_PJ11, LCD_DATA11_PJ11_MARK), 1936 GPIO_FN(LCD_DATA11_PJ11),
1933 PINMUX_GPIO(GPIO_FN_LCD_DATA10_PJ10, LCD_DATA10_PJ10_MARK), 1937 GPIO_FN(LCD_DATA10_PJ10),
1934 PINMUX_GPIO(GPIO_FN_LCD_DATA9_PJ9, LCD_DATA9_PJ9_MARK), 1938 GPIO_FN(LCD_DATA9_PJ9),
1935 PINMUX_GPIO(GPIO_FN_LCD_DATA8_PJ8, LCD_DATA8_PJ8_MARK), 1939 GPIO_FN(LCD_DATA8_PJ8),
1936 PINMUX_GPIO(GPIO_FN_LCD_DATA7_PJ7, LCD_DATA7_PJ7_MARK), 1940 GPIO_FN(LCD_DATA7_PJ7),
1937 PINMUX_GPIO(GPIO_FN_LCD_DATA6_PJ6, LCD_DATA6_PJ6_MARK), 1941 GPIO_FN(LCD_DATA6_PJ6),
1938 PINMUX_GPIO(GPIO_FN_LCD_DATA5_PJ5, LCD_DATA5_PJ5_MARK), 1942 GPIO_FN(LCD_DATA5_PJ5),
1939 PINMUX_GPIO(GPIO_FN_LCD_DATA4_PJ4, LCD_DATA4_PJ4_MARK), 1943 GPIO_FN(LCD_DATA4_PJ4),
1940 PINMUX_GPIO(GPIO_FN_LCD_DATA3_PJ3, LCD_DATA3_PJ3_MARK), 1944 GPIO_FN(LCD_DATA3_PJ3),
1941 PINMUX_GPIO(GPIO_FN_LCD_DATA2_PJ2, LCD_DATA2_PJ2_MARK), 1945 GPIO_FN(LCD_DATA2_PJ2),
1942 PINMUX_GPIO(GPIO_FN_LCD_DATA1_PJ1, LCD_DATA1_PJ1_MARK), 1946 GPIO_FN(LCD_DATA1_PJ1),
1943 PINMUX_GPIO(GPIO_FN_LCD_DATA0_PJ0, LCD_DATA0_PJ0_MARK), 1947 GPIO_FN(LCD_DATA0_PJ0),
1944 1948
1945 PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), 1949 GPIO_FN(LCD_M_DISP),
1946}; 1950};
1947 1951
1948static struct pinmux_cfg_reg pinmux_config_regs[] = { 1952static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1949 /* "name" addr register_size Field_Width */ 1953 /* "name" addr register_size Field_Width */
1950 1954
1951 /* where Field_Width is 1 for single mode registers or 4 for upto 16 1955 /* where Field_Width is 1 for single mode registers or 4 for upto 16
@@ -2734,7 +2738,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2734 {} 2738 {}
2735}; 2739};
2736 2740
2737static struct pinmux_data_reg pinmux_data_regs[] = { 2741static const struct pinmux_data_reg pinmux_data_regs[] = {
2738 { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) { 2742 { PINMUX_DATA_REG("PADR0", 0xfffe3816, 16) {
2739 0, 0, 0, 0, 0, 0, 0, PA1_DATA, 2743 0, 0, 0, 0, 0, 0, 0, PA1_DATA,
2740 0, 0, 0, 0, 0, 0, 0, PA0_DATA } 2744 0, 0, 0, 0, 0, 0, 0, PA0_DATA }
@@ -2813,19 +2817,17 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2813 { } 2817 { }
2814}; 2818};
2815 2819
2816struct sh_pfc_soc_info sh7269_pinmux_info = { 2820const struct sh_pfc_soc_info sh7269_pinmux_info = {
2817 .name = "sh7269_pfc", 2821 .name = "sh7269_pfc",
2818 .reserved_id = PINMUX_RESERVED,
2819 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2820 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN }, 2822 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END, FORCE_IN },
2821 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT }, 2823 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END, FORCE_OUT },
2822 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2823 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2824 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2824 2825
2825 .first_gpio = GPIO_PA1, 2826 .pins = pinmux_pins,
2826 .last_gpio = GPIO_FN_LCD_M_DISP, 2827 .nr_pins = ARRAY_SIZE(pinmux_pins),
2828 .func_gpios = pinmux_func_gpios,
2829 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2827 2830
2828 .gpios = pinmux_gpios,
2829 .cfg_regs = pinmux_config_regs, 2831 .cfg_regs = pinmux_config_regs,
2830 .data_regs = pinmux_data_regs, 2832 .data_regs = pinmux_data_regs,
2831 2833
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index d44e7f02069b..df0ae21a5ac8 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -368,7 +368,7 @@ enum {
368 PINMUX_MARK_END, 368 PINMUX_MARK_END,
369}; 369};
370 370
371static pinmux_enum_t pinmux_data[] = { 371static const pinmux_enum_t pinmux_data[] = {
372 372
373 /* specify valid pin states for each pin in GPIO mode */ 373 /* specify valid pin states for each pin in GPIO mode */
374 PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1), 374 PORT_DATA_IO_PD(0), PORT_DATA_IO_PD(1),
@@ -929,11 +929,214 @@ static pinmux_enum_t pinmux_data[] = {
929 PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1), 929 PINMUX_DATA(MFIv4_MARK, MSEL4CR_6_1),
930}; 930};
931 931
932static struct pinmux_gpio pinmux_gpios[] = { 932static struct sh_pfc_pin pinmux_pins[] = {
933
934 /* PORT */
935 GPIO_PORT_ALL(), 933 GPIO_PORT_ALL(),
934};
936 935
936/* - MMCIF ------------------------------------------------------------------ */
937static const unsigned int mmc0_data1_0_pins[] = {
938 /* D[0] */
939 84,
940};
941static const unsigned int mmc0_data1_0_mux[] = {
942 MMCD0_0_MARK,
943};
944static const unsigned int mmc0_data4_0_pins[] = {
945 /* D[0:3] */
946 84, 85, 86, 87,
947};
948static const unsigned int mmc0_data4_0_mux[] = {
949 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
950};
951static const unsigned int mmc0_data8_0_pins[] = {
952 /* D[0:7] */
953 84, 85, 86, 87, 88, 89, 90, 91,
954};
955static const unsigned int mmc0_data8_0_mux[] = {
956 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
957 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
958};
959static const unsigned int mmc0_ctrl_0_pins[] = {
960 /* CMD, CLK */
961 92, 99,
962};
963static const unsigned int mmc0_ctrl_0_mux[] = {
964 MMCCMD0_MARK, MMCCLK0_MARK,
965};
966
967static const unsigned int mmc0_data1_1_pins[] = {
968 /* D[0] */
969 54,
970};
971static const unsigned int mmc0_data1_1_mux[] = {
972 MMCD1_0_MARK,
973};
974static const unsigned int mmc0_data4_1_pins[] = {
975 /* D[0:3] */
976 54, 55, 56, 57,
977};
978static const unsigned int mmc0_data4_1_mux[] = {
979 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
980};
981static const unsigned int mmc0_data8_1_pins[] = {
982 /* D[0:7] */
983 54, 55, 56, 57, 58, 59, 60, 61,
984};
985static const unsigned int mmc0_data8_1_mux[] = {
986 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
987 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
988};
989static const unsigned int mmc0_ctrl_1_pins[] = {
990 /* CMD, CLK */
991 67, 66,
992};
993static const unsigned int mmc0_ctrl_1_mux[] = {
994 MMCCMD1_MARK, MMCCLK1_MARK,
995};
996/* - SDHI0 ------------------------------------------------------------------ */
997static const unsigned int sdhi0_data1_pins[] = {
998 /* D0 */
999 173,
1000};
1001static const unsigned int sdhi0_data1_mux[] = {
1002 SDHID0_0_MARK,
1003};
1004static const unsigned int sdhi0_data4_pins[] = {
1005 /* D[0:3] */
1006 173, 174, 175, 176,
1007};
1008static const unsigned int sdhi0_data4_mux[] = {
1009 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
1010};
1011static const unsigned int sdhi0_ctrl_pins[] = {
1012 /* CMD, CLK */
1013 177, 171,
1014};
1015static const unsigned int sdhi0_ctrl_mux[] = {
1016 SDHICMD0_MARK, SDHICLK0_MARK,
1017};
1018static const unsigned int sdhi0_cd_pins[] = {
1019 /* CD */
1020 172,
1021};
1022static const unsigned int sdhi0_cd_mux[] = {
1023 SDHICD0_MARK,
1024};
1025static const unsigned int sdhi0_wp_pins[] = {
1026 /* WP */
1027 178,
1028};
1029static const unsigned int sdhi0_wp_mux[] = {
1030 SDHIWP0_MARK,
1031};
1032/* - SDHI1 ------------------------------------------------------------------ */
1033static const unsigned int sdhi1_data1_pins[] = {
1034 /* D0 */
1035 180,
1036};
1037static const unsigned int sdhi1_data1_mux[] = {
1038 SDHID1_0_MARK,
1039};
1040static const unsigned int sdhi1_data4_pins[] = {
1041 /* D[0:3] */
1042 180, 181, 182, 183,
1043};
1044static const unsigned int sdhi1_data4_mux[] = {
1045 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
1046};
1047static const unsigned int sdhi1_ctrl_pins[] = {
1048 /* CMD, CLK */
1049 184, 179,
1050};
1051static const unsigned int sdhi1_ctrl_mux[] = {
1052 SDHICMD1_MARK, SDHICLK1_MARK,
1053};
1054
1055static const unsigned int sdhi2_data1_pins[] = {
1056 /* D0 */
1057 186,
1058};
1059static const unsigned int sdhi2_data1_mux[] = {
1060 SDHID2_0_MARK,
1061};
1062static const unsigned int sdhi2_data4_pins[] = {
1063 /* D[0:3] */
1064 186, 187, 188, 189,
1065};
1066static const unsigned int sdhi2_data4_mux[] = {
1067 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
1068};
1069static const unsigned int sdhi2_ctrl_pins[] = {
1070 /* CMD, CLK */
1071 190, 185,
1072};
1073static const unsigned int sdhi2_ctrl_mux[] = {
1074 SDHICMD2_MARK, SDHICLK2_MARK,
1075};
1076
1077static const struct sh_pfc_pin_group pinmux_groups[] = {
1078 SH_PFC_PIN_GROUP(mmc0_data1_0),
1079 SH_PFC_PIN_GROUP(mmc0_data4_0),
1080 SH_PFC_PIN_GROUP(mmc0_data8_0),
1081 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
1082 SH_PFC_PIN_GROUP(mmc0_data1_1),
1083 SH_PFC_PIN_GROUP(mmc0_data4_1),
1084 SH_PFC_PIN_GROUP(mmc0_data8_1),
1085 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
1086 SH_PFC_PIN_GROUP(sdhi0_data1),
1087 SH_PFC_PIN_GROUP(sdhi0_data4),
1088 SH_PFC_PIN_GROUP(sdhi0_ctrl),
1089 SH_PFC_PIN_GROUP(sdhi0_cd),
1090 SH_PFC_PIN_GROUP(sdhi0_wp),
1091 SH_PFC_PIN_GROUP(sdhi1_data1),
1092 SH_PFC_PIN_GROUP(sdhi1_data4),
1093 SH_PFC_PIN_GROUP(sdhi1_ctrl),
1094 SH_PFC_PIN_GROUP(sdhi2_data1),
1095 SH_PFC_PIN_GROUP(sdhi2_data4),
1096 SH_PFC_PIN_GROUP(sdhi2_ctrl),
1097};
1098
1099static const char * const mmc0_groups[] = {
1100 "mmc0_data1_0",
1101 "mmc0_data4_0",
1102 "mmc0_data8_0",
1103 "mmc0_ctrl_0",
1104 "mmc0_data1_1",
1105 "mmc0_data4_1",
1106 "mmc0_data8_1",
1107 "mmc0_ctrl_1",
1108};
1109
1110static const char * const sdhi0_groups[] = {
1111 "sdhi0_data1",
1112 "sdhi0_data4",
1113 "sdhi0_ctrl",
1114 "sdhi0_cd",
1115 "sdhi0_wp",
1116};
1117
1118static const char * const sdhi1_groups[] = {
1119 "sdhi1_data1",
1120 "sdhi1_data4",
1121 "sdhi1_ctrl",
1122};
1123
1124static const char * const sdhi2_groups[] = {
1125 "sdhi2_data1",
1126 "sdhi2_data4",
1127 "sdhi2_ctrl",
1128};
1129
1130static const struct sh_pfc_function pinmux_functions[] = {
1131 SH_PFC_FUNCTION(mmc0),
1132 SH_PFC_FUNCTION(sdhi0),
1133 SH_PFC_FUNCTION(sdhi1),
1134 SH_PFC_FUNCTION(sdhi2),
1135};
1136
1137#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
1138
1139static const struct pinmux_func pinmux_func_gpios[] = {
937 /* IRQ */ 1140 /* IRQ */
938 GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1), 1141 GPIO_FN(IRQ0_6), GPIO_FN(IRQ0_162), GPIO_FN(IRQ1),
939 GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8), 1142 GPIO_FN(IRQ2_4), GPIO_FN(IRQ2_5), GPIO_FN(IRQ3_8),
@@ -1074,18 +1277,6 @@ static struct pinmux_gpio pinmux_gpios[] = {
1074 GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13), 1277 GPIO_FN(D11_NAF11), GPIO_FN(D12_NAF12), GPIO_FN(D13_NAF13),
1075 GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15), 1278 GPIO_FN(D14_NAF14), GPIO_FN(D15_NAF15),
1076 1279
1077 /* MMCIF(1) */
1078 GPIO_FN(MMCD0_0), GPIO_FN(MMCD0_1), GPIO_FN(MMCD0_2),
1079 GPIO_FN(MMCD0_3), GPIO_FN(MMCD0_4), GPIO_FN(MMCD0_5),
1080 GPIO_FN(MMCD0_6), GPIO_FN(MMCD0_7), GPIO_FN(MMCCMD0),
1081 GPIO_FN(MMCCLK0),
1082
1083 /* MMCIF(2) */
1084 GPIO_FN(MMCD1_0), GPIO_FN(MMCD1_1), GPIO_FN(MMCD1_2),
1085 GPIO_FN(MMCD1_3), GPIO_FN(MMCD1_4), GPIO_FN(MMCD1_5),
1086 GPIO_FN(MMCD1_6), GPIO_FN(MMCD1_7), GPIO_FN(MMCCLK1),
1087 GPIO_FN(MMCCMD1),
1088
1089 /* SPU2 */ 1280 /* SPU2 */
1090 GPIO_FN(VINT_I), 1281 GPIO_FN(VINT_I),
1091 1282
@@ -1182,25 +1373,12 @@ static struct pinmux_gpio pinmux_gpios[] = {
1182 /* HDMI */ 1373 /* HDMI */
1183 GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC), 1374 GPIO_FN(HDMI_HPD), GPIO_FN(HDMI_CEC),
1184 1375
1185 /* SDHI0 */
1186 GPIO_FN(SDHICLK0), GPIO_FN(SDHICD0), GPIO_FN(SDHICMD0),
1187 GPIO_FN(SDHIWP0), GPIO_FN(SDHID0_0), GPIO_FN(SDHID0_1),
1188 GPIO_FN(SDHID0_2), GPIO_FN(SDHID0_3),
1189
1190 /* SDHI1 */
1191 GPIO_FN(SDHICLK1), GPIO_FN(SDHICMD1), GPIO_FN(SDHID1_0),
1192 GPIO_FN(SDHID1_1), GPIO_FN(SDHID1_2), GPIO_FN(SDHID1_3),
1193
1194 /* SDHI2 */
1195 GPIO_FN(SDHICLK2), GPIO_FN(SDHICMD2), GPIO_FN(SDHID2_0),
1196 GPIO_FN(SDHID2_1), GPIO_FN(SDHID2_2), GPIO_FN(SDHID2_3),
1197
1198 /* SDENC */ 1376 /* SDENC */
1199 GPIO_FN(SDENC_CPG), 1377 GPIO_FN(SDENC_CPG),
1200 GPIO_FN(SDENC_DV_CLKI), 1378 GPIO_FN(SDENC_DV_CLKI),
1201}; 1379};
1202 1380
1203static struct pinmux_cfg_reg pinmux_config_regs[] = { 1381static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1204 PORTCR(0, 0xE6051000), /* PORT0CR */ 1382 PORTCR(0, 0xE6051000), /* PORT0CR */
1205 PORTCR(1, 0xE6051001), /* PORT1CR */ 1383 PORTCR(1, 0xE6051001), /* PORT1CR */
1206 PORTCR(2, 0xE6051002), /* PORT2CR */ 1384 PORTCR(2, 0xE6051002), /* PORT2CR */
@@ -1472,7 +1650,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1472 { }, 1650 { },
1473}; 1651};
1474 1652
1475static struct pinmux_data_reg pinmux_data_regs[] = { 1653static const struct pinmux_data_reg pinmux_data_regs[] = {
1476 { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) { 1654 { PINMUX_DATA_REG("PORTL095_064DR", 0xE6054008, 32) {
1477 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA, 1655 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
1478 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA, 1656 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
@@ -1597,56 +1775,59 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1597 1775
1598#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5)) 1776#define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
1599#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5)) 1777#define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
1600static struct pinmux_irq pinmux_irqs[] = { 1778static const struct pinmux_irq pinmux_irqs[] = {
1601 PINMUX_IRQ(EXT_IRQ16L(0), PORT6_FN0, PORT162_FN0), 1779 PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162),
1602 PINMUX_IRQ(EXT_IRQ16L(1), PORT12_FN0), 1780 PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12),
1603 PINMUX_IRQ(EXT_IRQ16L(2), PORT4_FN0, PORT5_FN0), 1781 PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5),
1604 PINMUX_IRQ(EXT_IRQ16L(3), PORT8_FN0, PORT16_FN0), 1782 PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16),
1605 PINMUX_IRQ(EXT_IRQ16L(4), PORT17_FN0, PORT163_FN0), 1783 PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163),
1606 PINMUX_IRQ(EXT_IRQ16L(5), PORT18_FN0), 1784 PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18),
1607 PINMUX_IRQ(EXT_IRQ16L(6), PORT39_FN0, PORT164_FN0), 1785 PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164),
1608 PINMUX_IRQ(EXT_IRQ16L(7), PORT40_FN0, PORT167_FN0), 1786 PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167),
1609 PINMUX_IRQ(EXT_IRQ16L(8), PORT41_FN0, PORT168_FN0), 1787 PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168),
1610 PINMUX_IRQ(EXT_IRQ16L(9), PORT42_FN0, PORT169_FN0), 1788 PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169),
1611 PINMUX_IRQ(EXT_IRQ16L(10), PORT65_FN0), 1789 PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65),
1612 PINMUX_IRQ(EXT_IRQ16L(11), PORT67_FN0), 1790 PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67),
1613 PINMUX_IRQ(EXT_IRQ16L(12), PORT80_FN0, PORT137_FN0), 1791 PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137),
1614 PINMUX_IRQ(EXT_IRQ16L(13), PORT81_FN0, PORT145_FN0), 1792 PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145),
1615 PINMUX_IRQ(EXT_IRQ16L(14), PORT82_FN0, PORT146_FN0), 1793 PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146),
1616 PINMUX_IRQ(EXT_IRQ16L(15), PORT83_FN0, PORT147_FN0), 1794 PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147),
1617 PINMUX_IRQ(EXT_IRQ16H(16), PORT84_FN0, PORT170_FN0), 1795 PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170),
1618 PINMUX_IRQ(EXT_IRQ16H(17), PORT85_FN0), 1796 PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85),
1619 PINMUX_IRQ(EXT_IRQ16H(18), PORT86_FN0), 1797 PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86),
1620 PINMUX_IRQ(EXT_IRQ16H(19), PORT87_FN0), 1798 PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87),
1621 PINMUX_IRQ(EXT_IRQ16H(20), PORT92_FN0), 1799 PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92),
1622 PINMUX_IRQ(EXT_IRQ16H(21), PORT93_FN0), 1800 PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93),
1623 PINMUX_IRQ(EXT_IRQ16H(22), PORT94_FN0), 1801 PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94),
1624 PINMUX_IRQ(EXT_IRQ16H(23), PORT95_FN0), 1802 PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95),
1625 PINMUX_IRQ(EXT_IRQ16H(24), PORT112_FN0), 1803 PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112),
1626 PINMUX_IRQ(EXT_IRQ16H(25), PORT119_FN0), 1804 PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119),
1627 PINMUX_IRQ(EXT_IRQ16H(26), PORT121_FN0, PORT172_FN0), 1805 PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172),
1628 PINMUX_IRQ(EXT_IRQ16H(27), PORT122_FN0, PORT180_FN0), 1806 PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180),
1629 PINMUX_IRQ(EXT_IRQ16H(28), PORT123_FN0, PORT181_FN0), 1807 PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181),
1630 PINMUX_IRQ(EXT_IRQ16H(29), PORT129_FN0, PORT182_FN0), 1808 PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182),
1631 PINMUX_IRQ(EXT_IRQ16H(30), PORT130_FN0, PORT183_FN0), 1809 PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183),
1632 PINMUX_IRQ(EXT_IRQ16H(31), PORT138_FN0, PORT184_FN0), 1810 PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184),
1633}; 1811};
1634 1812
1635struct sh_pfc_soc_info sh7372_pinmux_info = { 1813const struct sh_pfc_soc_info sh7372_pinmux_info = {
1636 .name = "sh7372_pfc", 1814 .name = "sh7372_pfc",
1637 .reserved_id = PINMUX_RESERVED,
1638 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1639 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 1815 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1640 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 1816 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1641 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, 1817 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
1642 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 1818 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1643 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1644 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 1819 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1645 1820
1646 .first_gpio = GPIO_PORT0, 1821 .pins = pinmux_pins,
1647 .last_gpio = GPIO_FN_SDENC_DV_CLKI, 1822 .nr_pins = ARRAY_SIZE(pinmux_pins),
1823 .groups = pinmux_groups,
1824 .nr_groups = ARRAY_SIZE(pinmux_groups),
1825 .functions = pinmux_functions,
1826 .nr_functions = ARRAY_SIZE(pinmux_functions),
1827
1828 .func_gpios = pinmux_func_gpios,
1829 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
1648 1830
1649 .gpios = pinmux_gpios,
1650 .cfg_regs = pinmux_config_regs, 1831 .cfg_regs = pinmux_config_regs,
1651 .data_regs = pinmux_data_regs, 1832 .data_regs = pinmux_data_regs,
1652 1833
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 6f15c03077a0..587f7772abf2 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -18,18 +18,18 @@
18 * along with this program; if not, write to the Free Software 18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */ 20 */
21#include <linux/io.h>
21#include <linux/kernel.h> 22#include <linux/kernel.h>
23#include <linux/pinctrl/pinconf-generic.h>
24
22#include <mach/sh73a0.h> 25#include <mach/sh73a0.h>
23#include <mach/irqs.h> 26#include <mach/irqs.h>
24 27
28#include "core.h"
25#include "sh_pfc.h" 29#include "sh_pfc.h"
26 30
27#define CPU_ALL_PORT(fn, pfx, sfx) \ 31#define CPU_ALL_PORT(fn, pfx, sfx) \
28 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ 32 PORT_10(fn, pfx, sfx), PORT_90(fn, pfx, sfx), \
29 PORT_10(fn, pfx##2, sfx), PORT_10(fn, pfx##3, sfx), \
30 PORT_10(fn, pfx##4, sfx), PORT_10(fn, pfx##5, sfx), \
31 PORT_10(fn, pfx##6, sfx), PORT_10(fn, pfx##7, sfx), \
32 PORT_10(fn, pfx##8, sfx), PORT_10(fn, pfx##9, sfx), \
33 PORT_10(fn, pfx##10, sfx), \ 33 PORT_10(fn, pfx##10, sfx), \
34 PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \ 34 PORT_1(fn, pfx##110, sfx), PORT_1(fn, pfx##111, sfx), \
35 PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \ 35 PORT_1(fn, pfx##112, sfx), PORT_1(fn, pfx##113, sfx), \
@@ -66,14 +66,6 @@ enum {
66 PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */ 66 PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
67 PINMUX_INPUT_END, 67 PINMUX_INPUT_END,
68 68
69 PINMUX_INPUT_PULLUP_BEGIN,
70 PORT_ALL(IN_PU), /* PORT0_IN_PU -> PORT309_IN_PU */
71 PINMUX_INPUT_PULLUP_END,
72
73 PINMUX_INPUT_PULLDOWN_BEGIN,
74 PORT_ALL(IN_PD), /* PORT0_IN_PD -> PORT309_IN_PD */
75 PINMUX_INPUT_PULLDOWN_END,
76
77 PINMUX_OUTPUT_BEGIN, 69 PINMUX_OUTPUT_BEGIN,
78 PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */ 70 PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
79 PINMUX_OUTPUT_END, 71 PINMUX_OUTPUT_END,
@@ -468,328 +460,15 @@ enum {
468 EDBGREQ_PD_MARK, 460 EDBGREQ_PD_MARK,
469 EDBGREQ_PU_MARK, 461 EDBGREQ_PU_MARK,
470 462
471 /* Functions with pull-ups */
472 KEYIN0_PU_MARK,
473 KEYIN1_PU_MARK,
474 KEYIN2_PU_MARK,
475 KEYIN3_PU_MARK,
476 KEYIN4_PU_MARK,
477 KEYIN5_PU_MARK,
478 KEYIN6_PU_MARK,
479 KEYIN7_PU_MARK,
480 SDHICD0_PU_MARK,
481 SDHID0_0_PU_MARK,
482 SDHID0_1_PU_MARK,
483 SDHID0_2_PU_MARK,
484 SDHID0_3_PU_MARK,
485 SDHICMD0_PU_MARK,
486 SDHIWP0_PU_MARK,
487 SDHID1_0_PU_MARK,
488 SDHID1_1_PU_MARK,
489 SDHID1_2_PU_MARK,
490 SDHID1_3_PU_MARK,
491 SDHICMD1_PU_MARK,
492 SDHID2_0_PU_MARK,
493 SDHID2_1_PU_MARK,
494 SDHID2_2_PU_MARK,
495 SDHID2_3_PU_MARK,
496 SDHICMD2_PU_MARK,
497 MMCCMD0_PU_MARK,
498 MMCCMD1_PU_MARK,
499 MMCD0_0_PU_MARK,
500 MMCD0_1_PU_MARK,
501 MMCD0_2_PU_MARK,
502 MMCD0_3_PU_MARK,
503 MMCD0_4_PU_MARK,
504 MMCD0_5_PU_MARK,
505 MMCD0_6_PU_MARK,
506 MMCD0_7_PU_MARK,
507 FSIBISLD_PU_MARK,
508 FSIACK_PU_MARK,
509 FSIAILR_PU_MARK,
510 FSIAIBT_PU_MARK,
511 FSIAISLD_PU_MARK,
512
513 PINMUX_MARK_END, 463 PINMUX_MARK_END,
514}; 464};
515 465
516static pinmux_enum_t pinmux_data[] = { 466#define _PORT_DATA(pfx, sfx) PORT_DATA_IO(pfx)
517 /* specify valid pin states for each pin in GPIO mode */ 467#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
518 468
519 /* Table 25-1 (I/O and Pull U/D) */ 469static const pinmux_enum_t pinmux_data[] = {
520 PORT_DATA_I_PD(0), 470 /* specify valid pin states for each pin in GPIO mode */
521 PORT_DATA_I_PU(1), 471 PINMUX_DATA_GP_ALL(),
522 PORT_DATA_I_PU(2),
523 PORT_DATA_I_PU(3),
524 PORT_DATA_I_PU(4),
525 PORT_DATA_I_PU(5),
526 PORT_DATA_I_PU(6),
527 PORT_DATA_I_PU(7),
528 PORT_DATA_I_PU(8),
529 PORT_DATA_I_PD(9),
530 PORT_DATA_I_PD(10),
531 PORT_DATA_I_PU_PD(11),
532 PORT_DATA_IO_PU_PD(12),
533 PORT_DATA_IO_PU_PD(13),
534 PORT_DATA_IO_PU_PD(14),
535 PORT_DATA_IO_PU_PD(15),
536 PORT_DATA_IO_PD(16),
537 PORT_DATA_IO_PD(17),
538 PORT_DATA_IO_PU(18),
539 PORT_DATA_IO_PU(19),
540 PORT_DATA_O(20),
541 PORT_DATA_O(21),
542 PORT_DATA_O(22),
543 PORT_DATA_O(23),
544 PORT_DATA_O(24),
545 PORT_DATA_I_PD(25),
546 PORT_DATA_I_PD(26),
547 PORT_DATA_IO_PU(27),
548 PORT_DATA_IO_PU(28),
549 PORT_DATA_IO_PD(29),
550 PORT_DATA_IO_PD(30),
551 PORT_DATA_IO_PU(31),
552 PORT_DATA_IO_PD(32),
553 PORT_DATA_I_PU_PD(33),
554 PORT_DATA_IO_PD(34),
555 PORT_DATA_I_PU_PD(35),
556 PORT_DATA_IO_PD(36),
557 PORT_DATA_IO(37),
558 PORT_DATA_O(38),
559 PORT_DATA_I_PU(39),
560 PORT_DATA_I_PU_PD(40),
561 PORT_DATA_O(41),
562 PORT_DATA_IO_PD(42),
563 PORT_DATA_IO_PU_PD(43),
564 PORT_DATA_IO_PU_PD(44),
565 PORT_DATA_IO_PD(45),
566 PORT_DATA_IO_PD(46),
567 PORT_DATA_IO_PD(47),
568 PORT_DATA_I_PD(48),
569 PORT_DATA_IO_PU_PD(49),
570 PORT_DATA_IO_PD(50),
571
572 PORT_DATA_IO_PD(51),
573 PORT_DATA_O(52),
574 PORT_DATA_IO_PU_PD(53),
575 PORT_DATA_IO_PU_PD(54),
576 PORT_DATA_IO_PD(55),
577 PORT_DATA_I_PU_PD(56),
578 PORT_DATA_IO(57),
579 PORT_DATA_IO(58),
580 PORT_DATA_IO(59),
581 PORT_DATA_IO(60),
582 PORT_DATA_IO(61),
583 PORT_DATA_IO_PD(62),
584 PORT_DATA_IO_PD(63),
585 PORT_DATA_IO_PU_PD(64),
586 PORT_DATA_IO_PD(65),
587 PORT_DATA_IO_PU_PD(66),
588 PORT_DATA_IO_PU_PD(67),
589 PORT_DATA_IO_PU_PD(68),
590 PORT_DATA_IO_PU_PD(69),
591 PORT_DATA_IO_PU_PD(70),
592 PORT_DATA_IO_PU_PD(71),
593 PORT_DATA_IO_PU_PD(72),
594 PORT_DATA_I_PU_PD(73),
595 PORT_DATA_IO_PU(74),
596 PORT_DATA_IO_PU(75),
597 PORT_DATA_IO_PU(76),
598 PORT_DATA_IO_PU(77),
599 PORT_DATA_IO_PU(78),
600 PORT_DATA_IO_PU(79),
601 PORT_DATA_IO_PU(80),
602 PORT_DATA_IO_PU(81),
603 PORT_DATA_IO_PU(82),
604 PORT_DATA_IO_PU(83),
605 PORT_DATA_IO_PU(84),
606 PORT_DATA_IO_PU(85),
607 PORT_DATA_IO_PU(86),
608 PORT_DATA_IO_PU(87),
609 PORT_DATA_IO_PU(88),
610 PORT_DATA_IO_PU(89),
611 PORT_DATA_O(90),
612 PORT_DATA_IO_PU(91),
613 PORT_DATA_O(92),
614 PORT_DATA_IO_PU(93),
615 PORT_DATA_O(94),
616 PORT_DATA_I_PU_PD(95),
617 PORT_DATA_IO(96),
618 PORT_DATA_IO(97),
619 PORT_DATA_IO(98),
620 PORT_DATA_I_PU(99),
621 PORT_DATA_O(100),
622 PORT_DATA_O(101),
623 PORT_DATA_I_PU(102),
624 PORT_DATA_IO_PD(103),
625 PORT_DATA_I_PU_PD(104),
626 PORT_DATA_I_PD(105),
627 PORT_DATA_I_PD(106),
628 PORT_DATA_I_PU_PD(107),
629 PORT_DATA_I_PU_PD(108),
630 PORT_DATA_IO_PD(109),
631 PORT_DATA_IO_PD(110),
632 PORT_DATA_IO_PU_PD(111),
633 PORT_DATA_IO_PU_PD(112),
634 PORT_DATA_IO_PU_PD(113),
635 PORT_DATA_IO_PD(114),
636 PORT_DATA_IO_PU(115),
637 PORT_DATA_IO_PU(116),
638 PORT_DATA_IO_PU_PD(117),
639 PORT_DATA_IO_PU_PD(118),
640 PORT_DATA_IO_PD(128),
641
642 PORT_DATA_IO_PD(129),
643 PORT_DATA_IO_PU_PD(130),
644 PORT_DATA_IO_PD(131),
645 PORT_DATA_IO_PD(132),
646 PORT_DATA_IO_PD(133),
647 PORT_DATA_IO_PU_PD(134),
648 PORT_DATA_IO_PU_PD(135),
649 PORT_DATA_IO_PU_PD(136),
650 PORT_DATA_IO_PU_PD(137),
651 PORT_DATA_IO_PD(138),
652 PORT_DATA_IO_PD(139),
653 PORT_DATA_IO_PD(140),
654 PORT_DATA_IO_PD(141),
655 PORT_DATA_IO_PD(142),
656 PORT_DATA_IO_PD(143),
657 PORT_DATA_IO_PU_PD(144),
658 PORT_DATA_IO_PD(145),
659 PORT_DATA_IO_PU_PD(146),
660 PORT_DATA_IO_PU_PD(147),
661 PORT_DATA_IO_PU_PD(148),
662 PORT_DATA_IO_PU_PD(149),
663 PORT_DATA_I_PU_PD(150),
664 PORT_DATA_IO_PU_PD(151),
665 PORT_DATA_IO_PU_PD(152),
666 PORT_DATA_IO_PD(153),
667 PORT_DATA_IO_PD(154),
668 PORT_DATA_I_PU_PD(155),
669 PORT_DATA_IO_PU_PD(156),
670 PORT_DATA_I_PD(157),
671 PORT_DATA_IO_PD(158),
672 PORT_DATA_IO_PU_PD(159),
673 PORT_DATA_IO_PU_PD(160),
674 PORT_DATA_I_PU_PD(161),
675 PORT_DATA_I_PU_PD(162),
676 PORT_DATA_IO_PU_PD(163),
677 PORT_DATA_I_PU_PD(164),
678 PORT_DATA_IO_PD(192),
679 PORT_DATA_IO_PU_PD(193),
680 PORT_DATA_IO_PD(194),
681 PORT_DATA_IO_PU_PD(195),
682 PORT_DATA_IO_PD(196),
683 PORT_DATA_IO_PD(197),
684 PORT_DATA_IO_PD(198),
685 PORT_DATA_IO_PD(199),
686 PORT_DATA_IO_PU_PD(200),
687 PORT_DATA_IO_PU_PD(201),
688 PORT_DATA_IO_PU_PD(202),
689 PORT_DATA_IO_PU_PD(203),
690 PORT_DATA_IO_PU_PD(204),
691 PORT_DATA_IO_PU_PD(205),
692 PORT_DATA_IO_PU_PD(206),
693 PORT_DATA_IO_PD(207),
694 PORT_DATA_IO_PD(208),
695 PORT_DATA_IO_PD(209),
696 PORT_DATA_IO_PD(210),
697 PORT_DATA_IO_PD(211),
698 PORT_DATA_IO_PD(212),
699 PORT_DATA_IO_PD(213),
700 PORT_DATA_IO_PU_PD(214),
701 PORT_DATA_IO_PU_PD(215),
702 PORT_DATA_IO_PD(216),
703 PORT_DATA_IO_PD(217),
704 PORT_DATA_O(218),
705 PORT_DATA_IO_PD(219),
706 PORT_DATA_IO_PD(220),
707 PORT_DATA_IO_PU_PD(221),
708 PORT_DATA_IO_PU_PD(222),
709 PORT_DATA_I_PU_PD(223),
710 PORT_DATA_I_PU_PD(224),
711
712 PORT_DATA_IO_PU_PD(225),
713 PORT_DATA_O(226),
714 PORT_DATA_IO_PU_PD(227),
715 PORT_DATA_I_PU_PD(228),
716 PORT_DATA_I_PD(229),
717 PORT_DATA_IO(230),
718 PORT_DATA_IO_PU_PD(231),
719 PORT_DATA_IO_PU_PD(232),
720 PORT_DATA_I_PU_PD(233),
721 PORT_DATA_IO_PU_PD(234),
722 PORT_DATA_IO_PU_PD(235),
723 PORT_DATA_IO_PU_PD(236),
724 PORT_DATA_IO_PD(237),
725 PORT_DATA_IO_PU_PD(238),
726 PORT_DATA_IO_PU_PD(239),
727 PORT_DATA_IO_PU_PD(240),
728 PORT_DATA_O(241),
729 PORT_DATA_I_PD(242),
730 PORT_DATA_IO_PU_PD(243),
731 PORT_DATA_IO_PU_PD(244),
732 PORT_DATA_IO_PU_PD(245),
733 PORT_DATA_IO_PU_PD(246),
734 PORT_DATA_IO_PU_PD(247),
735 PORT_DATA_IO_PU_PD(248),
736 PORT_DATA_IO_PU_PD(249),
737 PORT_DATA_IO_PU_PD(250),
738 PORT_DATA_IO_PU_PD(251),
739 PORT_DATA_IO_PU_PD(252),
740 PORT_DATA_IO_PU_PD(253),
741 PORT_DATA_IO_PU_PD(254),
742 PORT_DATA_IO_PU_PD(255),
743 PORT_DATA_IO_PU_PD(256),
744 PORT_DATA_IO_PU_PD(257),
745 PORT_DATA_IO_PU_PD(258),
746 PORT_DATA_IO_PU_PD(259),
747 PORT_DATA_IO_PU_PD(260),
748 PORT_DATA_IO_PU_PD(261),
749 PORT_DATA_IO_PU_PD(262),
750 PORT_DATA_IO_PU_PD(263),
751 PORT_DATA_IO_PU_PD(264),
752 PORT_DATA_IO_PU_PD(265),
753 PORT_DATA_IO_PU_PD(266),
754 PORT_DATA_IO_PU_PD(267),
755 PORT_DATA_IO_PU_PD(268),
756 PORT_DATA_IO_PU_PD(269),
757 PORT_DATA_IO_PU_PD(270),
758 PORT_DATA_IO_PU_PD(271),
759 PORT_DATA_IO_PU_PD(272),
760 PORT_DATA_IO_PU_PD(273),
761 PORT_DATA_IO_PU_PD(274),
762 PORT_DATA_IO_PU_PD(275),
763 PORT_DATA_IO_PU_PD(276),
764 PORT_DATA_IO_PU_PD(277),
765 PORT_DATA_IO_PU_PD(278),
766 PORT_DATA_IO_PU_PD(279),
767 PORT_DATA_IO_PU_PD(280),
768 PORT_DATA_O(281),
769 PORT_DATA_O(282),
770 PORT_DATA_I_PU(288),
771 PORT_DATA_IO_PU_PD(289),
772 PORT_DATA_IO_PU_PD(290),
773 PORT_DATA_IO_PU_PD(291),
774 PORT_DATA_IO_PU_PD(292),
775 PORT_DATA_IO_PU_PD(293),
776 PORT_DATA_IO_PU_PD(294),
777 PORT_DATA_IO_PU_PD(295),
778 PORT_DATA_IO_PU_PD(296),
779 PORT_DATA_IO_PU_PD(297),
780 PORT_DATA_IO_PU_PD(298),
781
782 PORT_DATA_IO_PU_PD(299),
783 PORT_DATA_IO_PU_PD(300),
784 PORT_DATA_IO_PU_PD(301),
785 PORT_DATA_IO_PU_PD(302),
786 PORT_DATA_IO_PU_PD(303),
787 PORT_DATA_IO_PU_PD(304),
788 PORT_DATA_IO_PU_PD(305),
789 PORT_DATA_O(306),
790 PORT_DATA_O(307),
791 PORT_DATA_I_PU(308),
792 PORT_DATA_O(309),
793 472
794 /* Table 25-1 (Function 0-7) */ 473 /* Table 25-1 (Function 0-7) */
795 PINMUX_DATA(VBUS_0_MARK, PORT0_FN1), 474 PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
@@ -1358,28 +1037,19 @@ static pinmux_enum_t pinmux_data[] = {
1358 PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3), 1037 PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
1359 PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1), 1038 PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
1360 PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0), 1039 PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
1361 PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU, 1040 PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
1362 MSEL4CR_MSEL15_0), 1041 PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
1363 PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU, 1042 PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
1364 MSEL4CR_MSEL15_0), 1043 PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
1365 PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU, 1044 PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
1366 MSEL4CR_MSEL15_0),
1367 PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU,
1368 MSEL4CR_MSEL15_0),
1369 PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU,
1370 MSEL4CR_MSEL15_0), \
1371 PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3), 1045 PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
1372 PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU, 1046 PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
1373 MSEL4CR_MSEL15_0), \
1374 PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3), 1047 PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
1375 PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU, 1048 PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
1376 MSEL4CR_MSEL15_0), \
1377 PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3), 1049 PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
1378 PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU, 1050 PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
1379 MSEL4CR_MSEL15_0), \
1380 PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3), 1051 PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
1381 PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU, 1052 PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
1382 MSEL4CR_MSEL15_0),
1383 PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \ 1053 PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
1384 PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2), 1054 PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
1385 PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1), 1055 PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
@@ -1485,69 +1155,1791 @@ static pinmux_enum_t pinmux_data[] = {
1485 PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1), 1155 PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
1486 PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0), 1156 PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
1487 PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1), 1157 PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
1158};
1159
1160#define SH73A0_PIN(pin, cfgs) \
1161 { \
1162 .name = __stringify(PORT##pin), \
1163 .enum_id = PORT##pin##_DATA, \
1164 .configs = cfgs, \
1165 }
1166
1167#define __I (SH_PFC_PIN_CFG_INPUT)
1168#define __O (SH_PFC_PIN_CFG_OUTPUT)
1169#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1170#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
1171#define __PU (SH_PFC_PIN_CFG_PULL_UP)
1172#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1173
1174#define SH73A0_PIN_I_PD(pin) SH73A0_PIN(pin, __I | __PD)
1175#define SH73A0_PIN_I_PU(pin) SH73A0_PIN(pin, __I | __PU)
1176#define SH73A0_PIN_I_PU_PD(pin) SH73A0_PIN(pin, __I | __PUD)
1177#define SH73A0_PIN_IO(pin) SH73A0_PIN(pin, __IO)
1178#define SH73A0_PIN_IO_PD(pin) SH73A0_PIN(pin, __IO | __PD)
1179#define SH73A0_PIN_IO_PU(pin) SH73A0_PIN(pin, __IO | __PU)
1180#define SH73A0_PIN_IO_PU_PD(pin) SH73A0_PIN(pin, __IO | __PUD)
1181#define SH73A0_PIN_O(pin) SH73A0_PIN(pin, __O)
1182
1183static struct sh_pfc_pin pinmux_pins[] = {
1184 /* Table 25-1 (I/O and Pull U/D) */
1185 SH73A0_PIN_I_PD(0),
1186 SH73A0_PIN_I_PU(1),
1187 SH73A0_PIN_I_PU(2),
1188 SH73A0_PIN_I_PU(3),
1189 SH73A0_PIN_I_PU(4),
1190 SH73A0_PIN_I_PU(5),
1191 SH73A0_PIN_I_PU(6),
1192 SH73A0_PIN_I_PU(7),
1193 SH73A0_PIN_I_PU(8),
1194 SH73A0_PIN_I_PD(9),
1195 SH73A0_PIN_I_PD(10),
1196 SH73A0_PIN_I_PU_PD(11),
1197 SH73A0_PIN_IO_PU_PD(12),
1198 SH73A0_PIN_IO_PU_PD(13),
1199 SH73A0_PIN_IO_PU_PD(14),
1200 SH73A0_PIN_IO_PU_PD(15),
1201 SH73A0_PIN_IO_PD(16),
1202 SH73A0_PIN_IO_PD(17),
1203 SH73A0_PIN_IO_PU(18),
1204 SH73A0_PIN_IO_PU(19),
1205 SH73A0_PIN_O(20),
1206 SH73A0_PIN_O(21),
1207 SH73A0_PIN_O(22),
1208 SH73A0_PIN_O(23),
1209 SH73A0_PIN_O(24),
1210 SH73A0_PIN_I_PD(25),
1211 SH73A0_PIN_I_PD(26),
1212 SH73A0_PIN_IO_PU(27),
1213 SH73A0_PIN_IO_PU(28),
1214 SH73A0_PIN_IO_PD(29),
1215 SH73A0_PIN_IO_PD(30),
1216 SH73A0_PIN_IO_PU(31),
1217 SH73A0_PIN_IO_PD(32),
1218 SH73A0_PIN_I_PU_PD(33),
1219 SH73A0_PIN_IO_PD(34),
1220 SH73A0_PIN_I_PU_PD(35),
1221 SH73A0_PIN_IO_PD(36),
1222 SH73A0_PIN_IO(37),
1223 SH73A0_PIN_O(38),
1224 SH73A0_PIN_I_PU(39),
1225 SH73A0_PIN_I_PU_PD(40),
1226 SH73A0_PIN_O(41),
1227 SH73A0_PIN_IO_PD(42),
1228 SH73A0_PIN_IO_PU_PD(43),
1229 SH73A0_PIN_IO_PU_PD(44),
1230 SH73A0_PIN_IO_PD(45),
1231 SH73A0_PIN_IO_PD(46),
1232 SH73A0_PIN_IO_PD(47),
1233 SH73A0_PIN_I_PD(48),
1234 SH73A0_PIN_IO_PU_PD(49),
1235 SH73A0_PIN_IO_PD(50),
1236 SH73A0_PIN_IO_PD(51),
1237 SH73A0_PIN_O(52),
1238 SH73A0_PIN_IO_PU_PD(53),
1239 SH73A0_PIN_IO_PU_PD(54),
1240 SH73A0_PIN_IO_PD(55),
1241 SH73A0_PIN_I_PU_PD(56),
1242 SH73A0_PIN_IO(57),
1243 SH73A0_PIN_IO(58),
1244 SH73A0_PIN_IO(59),
1245 SH73A0_PIN_IO(60),
1246 SH73A0_PIN_IO(61),
1247 SH73A0_PIN_IO_PD(62),
1248 SH73A0_PIN_IO_PD(63),
1249 SH73A0_PIN_IO_PU_PD(64),
1250 SH73A0_PIN_IO_PD(65),
1251 SH73A0_PIN_IO_PU_PD(66),
1252 SH73A0_PIN_IO_PU_PD(67),
1253 SH73A0_PIN_IO_PU_PD(68),
1254 SH73A0_PIN_IO_PU_PD(69),
1255 SH73A0_PIN_IO_PU_PD(70),
1256 SH73A0_PIN_IO_PU_PD(71),
1257 SH73A0_PIN_IO_PU_PD(72),
1258 SH73A0_PIN_I_PU_PD(73),
1259 SH73A0_PIN_IO_PU(74),
1260 SH73A0_PIN_IO_PU(75),
1261 SH73A0_PIN_IO_PU(76),
1262 SH73A0_PIN_IO_PU(77),
1263 SH73A0_PIN_IO_PU(78),
1264 SH73A0_PIN_IO_PU(79),
1265 SH73A0_PIN_IO_PU(80),
1266 SH73A0_PIN_IO_PU(81),
1267 SH73A0_PIN_IO_PU(82),
1268 SH73A0_PIN_IO_PU(83),
1269 SH73A0_PIN_IO_PU(84),
1270 SH73A0_PIN_IO_PU(85),
1271 SH73A0_PIN_IO_PU(86),
1272 SH73A0_PIN_IO_PU(87),
1273 SH73A0_PIN_IO_PU(88),
1274 SH73A0_PIN_IO_PU(89),
1275 SH73A0_PIN_O(90),
1276 SH73A0_PIN_IO_PU(91),
1277 SH73A0_PIN_O(92),
1278 SH73A0_PIN_IO_PU(93),
1279 SH73A0_PIN_O(94),
1280 SH73A0_PIN_I_PU_PD(95),
1281 SH73A0_PIN_IO(96),
1282 SH73A0_PIN_IO(97),
1283 SH73A0_PIN_IO(98),
1284 SH73A0_PIN_I_PU(99),
1285 SH73A0_PIN_O(100),
1286 SH73A0_PIN_O(101),
1287 SH73A0_PIN_I_PU(102),
1288 SH73A0_PIN_IO_PD(103),
1289 SH73A0_PIN_I_PU_PD(104),
1290 SH73A0_PIN_I_PD(105),
1291 SH73A0_PIN_I_PD(106),
1292 SH73A0_PIN_I_PU_PD(107),
1293 SH73A0_PIN_I_PU_PD(108),
1294 SH73A0_PIN_IO_PD(109),
1295 SH73A0_PIN_IO_PD(110),
1296 SH73A0_PIN_IO_PU_PD(111),
1297 SH73A0_PIN_IO_PU_PD(112),
1298 SH73A0_PIN_IO_PU_PD(113),
1299 SH73A0_PIN_IO_PD(114),
1300 SH73A0_PIN_IO_PU(115),
1301 SH73A0_PIN_IO_PU(116),
1302 SH73A0_PIN_IO_PU_PD(117),
1303 SH73A0_PIN_IO_PU_PD(118),
1304 SH73A0_PIN_IO_PD(128),
1305 SH73A0_PIN_IO_PD(129),
1306 SH73A0_PIN_IO_PU_PD(130),
1307 SH73A0_PIN_IO_PD(131),
1308 SH73A0_PIN_IO_PD(132),
1309 SH73A0_PIN_IO_PD(133),
1310 SH73A0_PIN_IO_PU_PD(134),
1311 SH73A0_PIN_IO_PU_PD(135),
1312 SH73A0_PIN_IO_PU_PD(136),
1313 SH73A0_PIN_IO_PU_PD(137),
1314 SH73A0_PIN_IO_PD(138),
1315 SH73A0_PIN_IO_PD(139),
1316 SH73A0_PIN_IO_PD(140),
1317 SH73A0_PIN_IO_PD(141),
1318 SH73A0_PIN_IO_PD(142),
1319 SH73A0_PIN_IO_PD(143),
1320 SH73A0_PIN_IO_PU_PD(144),
1321 SH73A0_PIN_IO_PD(145),
1322 SH73A0_PIN_IO_PU_PD(146),
1323 SH73A0_PIN_IO_PU_PD(147),
1324 SH73A0_PIN_IO_PU_PD(148),
1325 SH73A0_PIN_IO_PU_PD(149),
1326 SH73A0_PIN_I_PU_PD(150),
1327 SH73A0_PIN_IO_PU_PD(151),
1328 SH73A0_PIN_IO_PU_PD(152),
1329 SH73A0_PIN_IO_PD(153),
1330 SH73A0_PIN_IO_PD(154),
1331 SH73A0_PIN_I_PU_PD(155),
1332 SH73A0_PIN_IO_PU_PD(156),
1333 SH73A0_PIN_I_PD(157),
1334 SH73A0_PIN_IO_PD(158),
1335 SH73A0_PIN_IO_PU_PD(159),
1336 SH73A0_PIN_IO_PU_PD(160),
1337 SH73A0_PIN_I_PU_PD(161),
1338 SH73A0_PIN_I_PU_PD(162),
1339 SH73A0_PIN_IO_PU_PD(163),
1340 SH73A0_PIN_I_PU_PD(164),
1341 SH73A0_PIN_IO_PD(192),
1342 SH73A0_PIN_IO_PU_PD(193),
1343 SH73A0_PIN_IO_PD(194),
1344 SH73A0_PIN_IO_PU_PD(195),
1345 SH73A0_PIN_IO_PD(196),
1346 SH73A0_PIN_IO_PD(197),
1347 SH73A0_PIN_IO_PD(198),
1348 SH73A0_PIN_IO_PD(199),
1349 SH73A0_PIN_IO_PU_PD(200),
1350 SH73A0_PIN_IO_PU_PD(201),
1351 SH73A0_PIN_IO_PU_PD(202),
1352 SH73A0_PIN_IO_PU_PD(203),
1353 SH73A0_PIN_IO_PU_PD(204),
1354 SH73A0_PIN_IO_PU_PD(205),
1355 SH73A0_PIN_IO_PU_PD(206),
1356 SH73A0_PIN_IO_PD(207),
1357 SH73A0_PIN_IO_PD(208),
1358 SH73A0_PIN_IO_PD(209),
1359 SH73A0_PIN_IO_PD(210),
1360 SH73A0_PIN_IO_PD(211),
1361 SH73A0_PIN_IO_PD(212),
1362 SH73A0_PIN_IO_PD(213),
1363 SH73A0_PIN_IO_PU_PD(214),
1364 SH73A0_PIN_IO_PU_PD(215),
1365 SH73A0_PIN_IO_PD(216),
1366 SH73A0_PIN_IO_PD(217),
1367 SH73A0_PIN_O(218),
1368 SH73A0_PIN_IO_PD(219),
1369 SH73A0_PIN_IO_PD(220),
1370 SH73A0_PIN_IO_PU_PD(221),
1371 SH73A0_PIN_IO_PU_PD(222),
1372 SH73A0_PIN_I_PU_PD(223),
1373 SH73A0_PIN_I_PU_PD(224),
1374 SH73A0_PIN_IO_PU_PD(225),
1375 SH73A0_PIN_O(226),
1376 SH73A0_PIN_IO_PU_PD(227),
1377 SH73A0_PIN_I_PU_PD(228),
1378 SH73A0_PIN_I_PD(229),
1379 SH73A0_PIN_IO(230),
1380 SH73A0_PIN_IO_PU_PD(231),
1381 SH73A0_PIN_IO_PU_PD(232),
1382 SH73A0_PIN_I_PU_PD(233),
1383 SH73A0_PIN_IO_PU_PD(234),
1384 SH73A0_PIN_IO_PU_PD(235),
1385 SH73A0_PIN_IO_PU_PD(236),
1386 SH73A0_PIN_IO_PD(237),
1387 SH73A0_PIN_IO_PU_PD(238),
1388 SH73A0_PIN_IO_PU_PD(239),
1389 SH73A0_PIN_IO_PU_PD(240),
1390 SH73A0_PIN_O(241),
1391 SH73A0_PIN_I_PD(242),
1392 SH73A0_PIN_IO_PU_PD(243),
1393 SH73A0_PIN_IO_PU_PD(244),
1394 SH73A0_PIN_IO_PU_PD(245),
1395 SH73A0_PIN_IO_PU_PD(246),
1396 SH73A0_PIN_IO_PU_PD(247),
1397 SH73A0_PIN_IO_PU_PD(248),
1398 SH73A0_PIN_IO_PU_PD(249),
1399 SH73A0_PIN_IO_PU_PD(250),
1400 SH73A0_PIN_IO_PU_PD(251),
1401 SH73A0_PIN_IO_PU_PD(252),
1402 SH73A0_PIN_IO_PU_PD(253),
1403 SH73A0_PIN_IO_PU_PD(254),
1404 SH73A0_PIN_IO_PU_PD(255),
1405 SH73A0_PIN_IO_PU_PD(256),
1406 SH73A0_PIN_IO_PU_PD(257),
1407 SH73A0_PIN_IO_PU_PD(258),
1408 SH73A0_PIN_IO_PU_PD(259),
1409 SH73A0_PIN_IO_PU_PD(260),
1410 SH73A0_PIN_IO_PU_PD(261),
1411 SH73A0_PIN_IO_PU_PD(262),
1412 SH73A0_PIN_IO_PU_PD(263),
1413 SH73A0_PIN_IO_PU_PD(264),
1414 SH73A0_PIN_IO_PU_PD(265),
1415 SH73A0_PIN_IO_PU_PD(266),
1416 SH73A0_PIN_IO_PU_PD(267),
1417 SH73A0_PIN_IO_PU_PD(268),
1418 SH73A0_PIN_IO_PU_PD(269),
1419 SH73A0_PIN_IO_PU_PD(270),
1420 SH73A0_PIN_IO_PU_PD(271),
1421 SH73A0_PIN_IO_PU_PD(272),
1422 SH73A0_PIN_IO_PU_PD(273),
1423 SH73A0_PIN_IO_PU_PD(274),
1424 SH73A0_PIN_IO_PU_PD(275),
1425 SH73A0_PIN_IO_PU_PD(276),
1426 SH73A0_PIN_IO_PU_PD(277),
1427 SH73A0_PIN_IO_PU_PD(278),
1428 SH73A0_PIN_IO_PU_PD(279),
1429 SH73A0_PIN_IO_PU_PD(280),
1430 SH73A0_PIN_O(281),
1431 SH73A0_PIN_O(282),
1432 SH73A0_PIN_I_PU(288),
1433 SH73A0_PIN_IO_PU_PD(289),
1434 SH73A0_PIN_IO_PU_PD(290),
1435 SH73A0_PIN_IO_PU_PD(291),
1436 SH73A0_PIN_IO_PU_PD(292),
1437 SH73A0_PIN_IO_PU_PD(293),
1438 SH73A0_PIN_IO_PU_PD(294),
1439 SH73A0_PIN_IO_PU_PD(295),
1440 SH73A0_PIN_IO_PU_PD(296),
1441 SH73A0_PIN_IO_PU_PD(297),
1442 SH73A0_PIN_IO_PU_PD(298),
1443 SH73A0_PIN_IO_PU_PD(299),
1444 SH73A0_PIN_IO_PU_PD(300),
1445 SH73A0_PIN_IO_PU_PD(301),
1446 SH73A0_PIN_IO_PU_PD(302),
1447 SH73A0_PIN_IO_PU_PD(303),
1448 SH73A0_PIN_IO_PU_PD(304),
1449 SH73A0_PIN_IO_PU_PD(305),
1450 SH73A0_PIN_O(306),
1451 SH73A0_PIN_O(307),
1452 SH73A0_PIN_I_PU(308),
1453 SH73A0_PIN_O(309),
1454};
1455
1456static const struct pinmux_range pinmux_ranges[] = {
1457 {.begin = 0, .end = 118,},
1458 {.begin = 128, .end = 164,},
1459 {.begin = 192, .end = 282,},
1460 {.begin = 288, .end = 309,},
1461};
1462
1463/* Pin numbers for pins without a corresponding GPIO port number are computed
1464 * from the row and column numbers with a 1000 offset to avoid collisions with
1465 * GPIO port numbers.
1466 */
1467#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
1468
1469/* - BSC -------------------------------------------------------------------- */
1470static const unsigned int bsc_data_0_7_pins[] = {
1471 /* D[0:7] */
1472 74, 75, 76, 77, 78, 79, 80, 81,
1473};
1474static const unsigned int bsc_data_0_7_mux[] = {
1475 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1476 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1477};
1478static const unsigned int bsc_data_8_15_pins[] = {
1479 /* D[8:15] */
1480 82, 83, 84, 85, 86, 87, 88, 89,
1481};
1482static const unsigned int bsc_data_8_15_mux[] = {
1483 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1484 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1485};
1486static const unsigned int bsc_cs4_pins[] = {
1487 /* CS */
1488 90,
1489};
1490static const unsigned int bsc_cs4_mux[] = {
1491 CS4__MARK,
1492};
1493static const unsigned int bsc_cs5_a_pins[] = {
1494 /* CS */
1495 91,
1496};
1497static const unsigned int bsc_cs5_a_mux[] = {
1498 CS5A__MARK,
1499};
1500static const unsigned int bsc_cs5_b_pins[] = {
1501 /* CS */
1502 92,
1503};
1504static const unsigned int bsc_cs5_b_mux[] = {
1505 CS5B__MARK,
1506};
1507static const unsigned int bsc_cs6_a_pins[] = {
1508 /* CS */
1509 94,
1510};
1511static const unsigned int bsc_cs6_a_mux[] = {
1512 CS6A__MARK,
1513};
1514static const unsigned int bsc_cs6_b_pins[] = {
1515 /* CS */
1516 93,
1517};
1518static const unsigned int bsc_cs6_b_mux[] = {
1519 CS6B__MARK,
1520};
1521static const unsigned int bsc_rd_pins[] = {
1522 /* RD */
1523 96,
1524};
1525static const unsigned int bsc_rd_mux[] = {
1526 RD__FSC_MARK,
1527};
1528static const unsigned int bsc_rdwr_0_pins[] = {
1529 /* RDWR */
1530 91,
1531};
1532static const unsigned int bsc_rdwr_0_mux[] = {
1533 PORT91_RDWR_MARK,
1534};
1535static const unsigned int bsc_rdwr_1_pins[] = {
1536 /* RDWR */
1537 97,
1538};
1539static const unsigned int bsc_rdwr_1_mux[] = {
1540 RDWR_FWE_MARK,
1541};
1542static const unsigned int bsc_rdwr_2_pins[] = {
1543 /* RDWR */
1544 149,
1545};
1546static const unsigned int bsc_rdwr_2_mux[] = {
1547 PORT149_RDWR_MARK,
1548};
1549static const unsigned int bsc_we0_pins[] = {
1550 /* WE0 */
1551 97,
1552};
1553static const unsigned int bsc_we0_mux[] = {
1554 WE0__FWE_MARK,
1555};
1556static const unsigned int bsc_we1_pins[] = {
1557 /* WE1 */
1558 98,
1559};
1560static const unsigned int bsc_we1_mux[] = {
1561 WE1__MARK,
1562};
1563/* - FSIA ------------------------------------------------------------------- */
1564static const unsigned int fsia_mclk_in_pins[] = {
1565 /* CK */
1566 49,
1567};
1568static const unsigned int fsia_mclk_in_mux[] = {
1569 FSIACK_MARK,
1570};
1571static const unsigned int fsia_mclk_out_pins[] = {
1572 /* OMC */
1573 49,
1574};
1575static const unsigned int fsia_mclk_out_mux[] = {
1576 FSIAOMC_MARK,
1577};
1578static const unsigned int fsia_sclk_in_pins[] = {
1579 /* ILR, IBT */
1580 50, 51,
1581};
1582static const unsigned int fsia_sclk_in_mux[] = {
1583 FSIAILR_MARK, FSIAIBT_MARK,
1584};
1585static const unsigned int fsia_sclk_out_pins[] = {
1586 /* OLR, OBT */
1587 50, 51,
1588};
1589static const unsigned int fsia_sclk_out_mux[] = {
1590 FSIAOLR_MARK, FSIAOBT_MARK,
1591};
1592static const unsigned int fsia_data_in_pins[] = {
1593 /* ISLD */
1594 55,
1595};
1596static const unsigned int fsia_data_in_mux[] = {
1597 FSIAISLD_MARK,
1598};
1599static const unsigned int fsia_data_out_pins[] = {
1600 /* OSLD */
1601 52,
1602};
1603static const unsigned int fsia_data_out_mux[] = {
1604 FSIAOSLD_MARK,
1605};
1606static const unsigned int fsia_spdif_pins[] = {
1607 /* SPDIF */
1608 53,
1609};
1610static const unsigned int fsia_spdif_mux[] = {
1611 FSIASPDIF_MARK,
1612};
1613/* - FSIB ------------------------------------------------------------------- */
1614static const unsigned int fsib_mclk_in_pins[] = {
1615 /* CK */
1616 54,
1617};
1618static const unsigned int fsib_mclk_in_mux[] = {
1619 FSIBCK_MARK,
1620};
1621static const unsigned int fsib_mclk_out_pins[] = {
1622 /* OMC */
1623 54,
1624};
1625static const unsigned int fsib_mclk_out_mux[] = {
1626 FSIBOMC_MARK,
1627};
1628static const unsigned int fsib_sclk_in_pins[] = {
1629 /* ILR, IBT */
1630 37, 36,
1631};
1632static const unsigned int fsib_sclk_in_mux[] = {
1633 FSIBILR_MARK, FSIBIBT_MARK,
1634};
1635static const unsigned int fsib_sclk_out_pins[] = {
1636 /* OLR, OBT */
1637 37, 36,
1638};
1639static const unsigned int fsib_sclk_out_mux[] = {
1640 FSIBOLR_MARK, FSIBOBT_MARK,
1641};
1642static const unsigned int fsib_data_in_pins[] = {
1643 /* ISLD */
1644 39,
1645};
1646static const unsigned int fsib_data_in_mux[] = {
1647 FSIBISLD_MARK,
1648};
1649static const unsigned int fsib_data_out_pins[] = {
1650 /* OSLD */
1651 38,
1652};
1653static const unsigned int fsib_data_out_mux[] = {
1654 FSIBOSLD_MARK,
1655};
1656static const unsigned int fsib_spdif_pins[] = {
1657 /* SPDIF */
1658 53,
1659};
1660static const unsigned int fsib_spdif_mux[] = {
1661 FSIBSPDIF_MARK,
1662};
1663/* - FSIC ------------------------------------------------------------------- */
1664static const unsigned int fsic_mclk_in_pins[] = {
1665 /* CK */
1666 54,
1667};
1668static const unsigned int fsic_mclk_in_mux[] = {
1669 FSICCK_MARK,
1670};
1671static const unsigned int fsic_mclk_out_pins[] = {
1672 /* OMC */
1673 54,
1674};
1675static const unsigned int fsic_mclk_out_mux[] = {
1676 FSICOMC_MARK,
1677};
1678static const unsigned int fsic_sclk_in_pins[] = {
1679 /* ILR, IBT */
1680 46, 45,
1681};
1682static const unsigned int fsic_sclk_in_mux[] = {
1683 FSICILR_MARK, FSICIBT_MARK,
1684};
1685static const unsigned int fsic_sclk_out_pins[] = {
1686 /* OLR, OBT */
1687 46, 45,
1688};
1689static const unsigned int fsic_sclk_out_mux[] = {
1690 FSICOLR_MARK, FSICOBT_MARK,
1691};
1692static const unsigned int fsic_data_in_pins[] = {
1693 /* ISLD */
1694 48,
1695};
1696static const unsigned int fsic_data_in_mux[] = {
1697 FSICISLD_MARK,
1698};
1699static const unsigned int fsic_data_out_pins[] = {
1700 /* OSLD, OSLDT1, OSLDT2, OSLDT3 */
1701 47, 44, 42, 16,
1702};
1703static const unsigned int fsic_data_out_mux[] = {
1704 FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
1705};
1706static const unsigned int fsic_spdif_0_pins[] = {
1707 /* SPDIF */
1708 53,
1709};
1710static const unsigned int fsic_spdif_0_mux[] = {
1711 PORT53_FSICSPDIF_MARK,
1712};
1713static const unsigned int fsic_spdif_1_pins[] = {
1714 /* SPDIF */
1715 47,
1716};
1717static const unsigned int fsic_spdif_1_mux[] = {
1718 PORT47_FSICSPDIF_MARK,
1719};
1720/* - FSID ------------------------------------------------------------------- */
1721static const unsigned int fsid_sclk_in_pins[] = {
1722 /* ILR, IBT */
1723 46, 45,
1724};
1725static const unsigned int fsid_sclk_in_mux[] = {
1726 FSIDILR_MARK, FSIDIBT_MARK,
1727};
1728static const unsigned int fsid_sclk_out_pins[] = {
1729 /* OLR, OBT */
1730 46, 45,
1731};
1732static const unsigned int fsid_sclk_out_mux[] = {
1733 FSIDOLR_MARK, FSIDOBT_MARK,
1734};
1735static const unsigned int fsid_data_in_pins[] = {
1736 /* ISLD */
1737 48,
1738};
1739static const unsigned int fsid_data_in_mux[] = {
1740 FSIDISLD_MARK,
1741};
1742/* - I2C2 ------------------------------------------------------------------- */
1743static const unsigned int i2c2_0_pins[] = {
1744 /* SCL, SDA */
1745 237, 236,
1746};
1747static const unsigned int i2c2_0_mux[] = {
1748 PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
1749};
1750static const unsigned int i2c2_1_pins[] = {
1751 /* SCL, SDA */
1752 27, 28,
1753};
1754static const unsigned int i2c2_1_mux[] = {
1755 PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
1756};
1757static const unsigned int i2c2_2_pins[] = {
1758 /* SCL, SDA */
1759 115, 116,
1760};
1761static const unsigned int i2c2_2_mux[] = {
1762 PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
1763};
1764/* - I2C3 ------------------------------------------------------------------- */
1765static const unsigned int i2c3_0_pins[] = {
1766 /* SCL, SDA */
1767 248, 249,
1768};
1769static const unsigned int i2c3_0_mux[] = {
1770 PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
1771};
1772static const unsigned int i2c3_1_pins[] = {
1773 /* SCL, SDA */
1774 27, 28,
1775};
1776static const unsigned int i2c3_1_mux[] = {
1777 PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
1778};
1779static const unsigned int i2c3_2_pins[] = {
1780 /* SCL, SDA */
1781 115, 116,
1782};
1783static const unsigned int i2c3_2_mux[] = {
1784 PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
1785};
1786/* - IrDA ------------------------------------------------------------------- */
1787static const unsigned int irda_0_pins[] = {
1788 /* OUT, IN, FIRSEL */
1789 241, 242, 243,
1790};
1791static const unsigned int irda_0_mux[] = {
1792 PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
1793};
1794static const unsigned int irda_1_pins[] = {
1795 /* OUT, IN, FIRSEL */
1796 49, 53, 54,
1797};
1798static const unsigned int irda_1_mux[] = {
1799 PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
1800};
1801/* - KEYSC ------------------------------------------------------------------ */
1802static const unsigned int keysc_in5_pins[] = {
1803 /* KEYIN[0:4] */
1804 66, 67, 68, 69, 70,
1805};
1806static const unsigned int keysc_in5_mux[] = {
1807 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1808 KEYIN4_MARK,
1809};
1810static const unsigned int keysc_in6_pins[] = {
1811 /* KEYIN[0:5] */
1812 66, 67, 68, 69, 70, 71,
1813};
1814static const unsigned int keysc_in6_mux[] = {
1815 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1816 KEYIN4_MARK, KEYIN5_MARK,
1817};
1818static const unsigned int keysc_in7_pins[] = {
1819 /* KEYIN[0:6] */
1820 66, 67, 68, 69, 70, 71, 72,
1821};
1822static const unsigned int keysc_in7_mux[] = {
1823 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1824 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
1825};
1826static const unsigned int keysc_in8_pins[] = {
1827 /* KEYIN[0:7] */
1828 66, 67, 68, 69, 70, 71, 72, 73,
1829};
1830static const unsigned int keysc_in8_mux[] = {
1831 KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1832 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
1833};
1834static const unsigned int keysc_out04_pins[] = {
1835 /* KEYOUT[0:4] */
1836 65, 64, 63, 62, 61,
1837};
1838static const unsigned int keysc_out04_mux[] = {
1839 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
1840};
1841static const unsigned int keysc_out5_pins[] = {
1842 /* KEYOUT5 */
1843 60,
1844};
1845static const unsigned int keysc_out5_mux[] = {
1846 KEYOUT5_MARK,
1847};
1848static const unsigned int keysc_out6_0_pins[] = {
1849 /* KEYOUT6 */
1850 59,
1851};
1852static const unsigned int keysc_out6_0_mux[] = {
1853 PORT59_KEYOUT6_MARK,
1854};
1855static const unsigned int keysc_out6_1_pins[] = {
1856 /* KEYOUT6 */
1857 131,
1858};
1859static const unsigned int keysc_out6_1_mux[] = {
1860 PORT131_KEYOUT6_MARK,
1861};
1862static const unsigned int keysc_out6_2_pins[] = {
1863 /* KEYOUT6 */
1864 143,
1865};
1866static const unsigned int keysc_out6_2_mux[] = {
1867 PORT143_KEYOUT6_MARK,
1868};
1869static const unsigned int keysc_out7_0_pins[] = {
1870 /* KEYOUT7 */
1871 58,
1872};
1873static const unsigned int keysc_out7_0_mux[] = {
1874 PORT58_KEYOUT7_MARK,
1875};
1876static const unsigned int keysc_out7_1_pins[] = {
1877 /* KEYOUT7 */
1878 132,
1879};
1880static const unsigned int keysc_out7_1_mux[] = {
1881 PORT132_KEYOUT7_MARK,
1882};
1883static const unsigned int keysc_out7_2_pins[] = {
1884 /* KEYOUT7 */
1885 144,
1886};
1887static const unsigned int keysc_out7_2_mux[] = {
1888 PORT144_KEYOUT7_MARK,
1889};
1890static const unsigned int keysc_out8_0_pins[] = {
1891 /* KEYOUT8 */
1892 PIN_NUMBER(6, 26),
1893};
1894static const unsigned int keysc_out8_0_mux[] = {
1895 KEYOUT8_MARK,
1896};
1897static const unsigned int keysc_out8_1_pins[] = {
1898 /* KEYOUT8 */
1899 136,
1900};
1901static const unsigned int keysc_out8_1_mux[] = {
1902 PORT136_KEYOUT8_MARK,
1903};
1904static const unsigned int keysc_out8_2_pins[] = {
1905 /* KEYOUT8 */
1906 138,
1907};
1908static const unsigned int keysc_out8_2_mux[] = {
1909 PORT138_KEYOUT8_MARK,
1910};
1911static const unsigned int keysc_out9_0_pins[] = {
1912 /* KEYOUT9 */
1913 137,
1914};
1915static const unsigned int keysc_out9_0_mux[] = {
1916 PORT137_KEYOUT9_MARK,
1917};
1918static const unsigned int keysc_out9_1_pins[] = {
1919 /* KEYOUT9 */
1920 139,
1921};
1922static const unsigned int keysc_out9_1_mux[] = {
1923 PORT139_KEYOUT9_MARK,
1924};
1925static const unsigned int keysc_out9_2_pins[] = {
1926 /* KEYOUT9 */
1927 149,
1928};
1929static const unsigned int keysc_out9_2_mux[] = {
1930 PORT149_KEYOUT9_MARK,
1931};
1932static const unsigned int keysc_out10_0_pins[] = {
1933 /* KEYOUT10 */
1934 132,
1935};
1936static const unsigned int keysc_out10_0_mux[] = {
1937 PORT132_KEYOUT10_MARK,
1938};
1939static const unsigned int keysc_out10_1_pins[] = {
1940 /* KEYOUT10 */
1941 142,
1942};
1943static const unsigned int keysc_out10_1_mux[] = {
1944 PORT142_KEYOUT10_MARK,
1945};
1946static const unsigned int keysc_out11_0_pins[] = {
1947 /* KEYOUT11 */
1948 131,
1949};
1950static const unsigned int keysc_out11_0_mux[] = {
1951 PORT131_KEYOUT11_MARK,
1952};
1953static const unsigned int keysc_out11_1_pins[] = {
1954 /* KEYOUT11 */
1955 143,
1956};
1957static const unsigned int keysc_out11_1_mux[] = {
1958 PORT143_KEYOUT11_MARK,
1959};
1960/* - LCD -------------------------------------------------------------------- */
1961static const unsigned int lcd_data8_pins[] = {
1962 /* D[0:7] */
1963 192, 193, 194, 195, 196, 197, 198, 199,
1964};
1965static const unsigned int lcd_data8_mux[] = {
1966 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1967 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1968};
1969static const unsigned int lcd_data9_pins[] = {
1970 /* D[0:8] */
1971 192, 193, 194, 195, 196, 197, 198, 199,
1972 200,
1973};
1974static const unsigned int lcd_data9_mux[] = {
1975 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1976 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1977 LCDD8_MARK,
1978};
1979static const unsigned int lcd_data12_pins[] = {
1980 /* D[0:11] */
1981 192, 193, 194, 195, 196, 197, 198, 199,
1982 200, 201, 202, 203,
1983};
1984static const unsigned int lcd_data12_mux[] = {
1985 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1986 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1987 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1988};
1989static const unsigned int lcd_data16_pins[] = {
1990 /* D[0:15] */
1991 192, 193, 194, 195, 196, 197, 198, 199,
1992 200, 201, 202, 203, 204, 205, 206, 207,
1993};
1994static const unsigned int lcd_data16_mux[] = {
1995 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1996 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1997 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1998 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1999};
2000static const unsigned int lcd_data18_pins[] = {
2001 /* D[0:17] */
2002 192, 193, 194, 195, 196, 197, 198, 199,
2003 200, 201, 202, 203, 204, 205, 206, 207,
2004 208, 209,
2005};
2006static const unsigned int lcd_data18_mux[] = {
2007 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2008 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2009 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2010 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2011 LCDD16_MARK, LCDD17_MARK,
2012};
2013static const unsigned int lcd_data24_pins[] = {
2014 /* D[0:23] */
2015 192, 193, 194, 195, 196, 197, 198, 199,
2016 200, 201, 202, 203, 204, 205, 206, 207,
2017 208, 209, 210, 211, 212, 213, 214, 215
2018};
2019static const unsigned int lcd_data24_mux[] = {
2020 LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2021 LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2022 LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2023 LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2024 LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
2025 LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
2026};
2027static const unsigned int lcd_display_pins[] = {
2028 /* DON */
2029 222,
2030};
2031static const unsigned int lcd_display_mux[] = {
2032 LCDDON_MARK,
2033};
2034static const unsigned int lcd_lclk_pins[] = {
2035 /* LCLK */
2036 221,
2037};
2038static const unsigned int lcd_lclk_mux[] = {
2039 LCDLCLK_MARK,
2040};
2041static const unsigned int lcd_sync_pins[] = {
2042 /* VSYN, HSYN, DCK, DISP */
2043 220, 218, 216, 219,
2044};
2045static const unsigned int lcd_sync_mux[] = {
2046 LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
2047};
2048static const unsigned int lcd_sys_pins[] = {
2049 /* CS, WR, RD, RS */
2050 218, 216, 217, 219,
2051};
2052static const unsigned int lcd_sys_mux[] = {
2053 LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
2054};
2055/* - LCD2 ------------------------------------------------------------------- */
2056static const unsigned int lcd2_data8_pins[] = {
2057 /* D[0:7] */
2058 128, 129, 142, 143, 144, 145, 138, 139,
2059};
2060static const unsigned int lcd2_data8_mux[] = {
2061 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2062 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2063};
2064static const unsigned int lcd2_data9_pins[] = {
2065 /* D[0:8] */
2066 128, 129, 142, 143, 144, 145, 138, 139,
2067 140,
2068};
2069static const unsigned int lcd2_data9_mux[] = {
2070 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2071 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2072 LCD2D8_MARK,
2073};
2074static const unsigned int lcd2_data12_pins[] = {
2075 /* D[0:12] */
2076 128, 129, 142, 143, 144, 145, 138, 139,
2077 140, 141, 130, 131,
2078};
2079static const unsigned int lcd2_data12_mux[] = {
2080 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2081 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2082 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2083};
2084static const unsigned int lcd2_data16_pins[] = {
2085 /* D[0:15] */
2086 128, 129, 142, 143, 144, 145, 138, 139,
2087 140, 141, 130, 131, 132, 133, 134, 135,
2088};
2089static const unsigned int lcd2_data16_mux[] = {
2090 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2091 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2092 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2093 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2094};
2095static const unsigned int lcd2_data18_pins[] = {
2096 /* D[0:17] */
2097 128, 129, 142, 143, 144, 145, 138, 139,
2098 140, 141, 130, 131, 132, 133, 134, 135,
2099 136, 137,
2100};
2101static const unsigned int lcd2_data18_mux[] = {
2102 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2103 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2104 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2105 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2106 LCD2D16_MARK, LCD2D17_MARK,
2107};
2108static const unsigned int lcd2_data24_pins[] = {
2109 /* D[0:23] */
2110 128, 129, 142, 143, 144, 145, 138, 139,
2111 140, 141, 130, 131, 132, 133, 134, 135,
2112 136, 137, 146, 147, 234, 235, 238, 239
2113};
2114static const unsigned int lcd2_data24_mux[] = {
2115 LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2116 LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2117 LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2118 LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2119 LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
2120 LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
2121};
2122static const unsigned int lcd2_sync_0_pins[] = {
2123 /* VSYN, HSYN, DCK, DISP */
2124 128, 129, 146, 145,
2125};
2126static const unsigned int lcd2_sync_0_mux[] = {
2127 PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
2128 LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
2129};
2130static const unsigned int lcd2_sync_1_pins[] = {
2131 /* VSYN, HSYN, DCK, DISP */
2132 222, 221, 219, 217,
2133};
2134static const unsigned int lcd2_sync_1_mux[] = {
2135 PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
2136 LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
2137};
2138static const unsigned int lcd2_sys_0_pins[] = {
2139 /* CS, WR, RD, RS */
2140 129, 146, 147, 145,
2141};
2142static const unsigned int lcd2_sys_0_mux[] = {
2143 PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
2144 LCD2RD__MARK, PORT145_LCD2RS_MARK,
2145};
2146static const unsigned int lcd2_sys_1_pins[] = {
2147 /* CS, WR, RD, RS */
2148 221, 219, 147, 217,
2149};
2150static const unsigned int lcd2_sys_1_mux[] = {
2151 PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
2152 LCD2RD__MARK, PORT217_LCD2RS_MARK,
2153};
2154/* - MMCIF ------------------------------------------------------------------ */
2155static const unsigned int mmc0_data1_0_pins[] = {
2156 /* D[0] */
2157 271,
2158};
2159static const unsigned int mmc0_data1_0_mux[] = {
2160 MMCD0_0_MARK,
2161};
2162static const unsigned int mmc0_data4_0_pins[] = {
2163 /* D[0:3] */
2164 271, 272, 273, 274,
2165};
2166static const unsigned int mmc0_data4_0_mux[] = {
2167 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2168};
2169static const unsigned int mmc0_data8_0_pins[] = {
2170 /* D[0:7] */
2171 271, 272, 273, 274, 275, 276, 277, 278,
2172};
2173static const unsigned int mmc0_data8_0_mux[] = {
2174 MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2175 MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
2176};
2177static const unsigned int mmc0_ctrl_0_pins[] = {
2178 /* CMD, CLK */
2179 279, 270,
2180};
2181static const unsigned int mmc0_ctrl_0_mux[] = {
2182 MMCCMD0_MARK, MMCCLK0_MARK,
2183};
1488 2184
1489 /* Functions with pull-ups */ 2185static const unsigned int mmc0_data1_1_pins[] = {
1490 PINMUX_DATA(KEYIN0_PU_MARK, PORT66_FN2, PORT66_IN_PU), 2186 /* D[0] */
1491 PINMUX_DATA(KEYIN1_PU_MARK, PORT67_FN2, PORT67_IN_PU), 2187 305,
1492 PINMUX_DATA(KEYIN2_PU_MARK, PORT68_FN2, PORT68_IN_PU), 2188};
1493 PINMUX_DATA(KEYIN3_PU_MARK, PORT69_FN2, PORT69_IN_PU), 2189static const unsigned int mmc0_data1_1_mux[] = {
1494 PINMUX_DATA(KEYIN4_PU_MARK, PORT70_FN2, PORT70_IN_PU), 2190 MMCD1_0_MARK,
1495 PINMUX_DATA(KEYIN5_PU_MARK, PORT71_FN2, PORT71_IN_PU), 2191};
1496 PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU), 2192static const unsigned int mmc0_data4_1_pins[] = {
1497 PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU), 2193 /* D[0:3] */
1498 2194 305, 304, 303, 302,
1499 PINMUX_DATA(SDHICD0_PU_MARK, PORT251_FN1, PORT251_IN_PU), 2195};
1500 PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU), 2196static const unsigned int mmc0_data4_1_mux[] = {
1501 PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU), 2197 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1502 PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU), 2198};
1503 PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU), 2199static const unsigned int mmc0_data8_1_pins[] = {
1504 PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU), 2200 /* D[0:7] */
1505 PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT256_IN_PU), 2201 305, 304, 303, 302, 301, 300, 299, 298,
1506 PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU), 2202};
1507 PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU), 2203static const unsigned int mmc0_data8_1_mux[] = {
1508 PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU), 2204 MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1509 PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU), 2205 MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
1510 PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU), 2206};
1511 PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU), 2207static const unsigned int mmc0_ctrl_1_pins[] = {
1512 PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU), 2208 /* CMD, CLK */
1513 PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU), 2209 297, 289,
1514 PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU), 2210};
1515 PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU), 2211static const unsigned int mmc0_ctrl_1_mux[] = {
1516 2212 MMCCMD1_MARK, MMCCLK1_MARK,
1517 PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU, 2213};
1518 MSEL4CR_MSEL15_0), 2214/* - SCIFA0 ----------------------------------------------------------------- */
1519 PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU, 2215static const unsigned int scifa0_data_pins[] = {
1520 MSEL4CR_MSEL15_1), 2216 /* RXD, TXD */
1521 2217 43, 17,
1522 PINMUX_DATA(MMCD0_0_PU_MARK, 2218};
1523 PORT271_FN1, PORT271_IN_PU, MSEL4CR_MSEL15_0), 2219static const unsigned int scifa0_data_mux[] = {
1524 PINMUX_DATA(MMCD0_1_PU_MARK, 2220 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1525 PORT272_FN1, PORT272_IN_PU, MSEL4CR_MSEL15_0), 2221};
1526 PINMUX_DATA(MMCD0_2_PU_MARK, 2222static const unsigned int scifa0_clk_pins[] = {
1527 PORT273_FN1, PORT273_IN_PU, MSEL4CR_MSEL15_0), 2223 /* SCK */
1528 PINMUX_DATA(MMCD0_3_PU_MARK, 2224 16,
1529 PORT274_FN1, PORT274_IN_PU, MSEL4CR_MSEL15_0), 2225};
1530 PINMUX_DATA(MMCD0_4_PU_MARK, 2226static const unsigned int scifa0_clk_mux[] = {
1531 PORT275_FN1, PORT275_IN_PU, MSEL4CR_MSEL15_0), 2227 SCIFA0_SCK_MARK,
1532 PINMUX_DATA(MMCD0_5_PU_MARK, 2228};
1533 PORT276_FN1, PORT276_IN_PU, MSEL4CR_MSEL15_0), 2229static const unsigned int scifa0_ctrl_pins[] = {
1534 PINMUX_DATA(MMCD0_6_PU_MARK, 2230 /* RTS, CTS */
1535 PORT277_FN1, PORT277_IN_PU, MSEL4CR_MSEL15_0), 2231 42, 44,
1536 PINMUX_DATA(MMCD0_7_PU_MARK, 2232};
1537 PORT278_FN1, PORT278_IN_PU, MSEL4CR_MSEL15_0), 2233static const unsigned int scifa0_ctrl_mux[] = {
1538 2234 SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
1539 PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU), 2235};
1540 PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU), 2236/* - SCIFA1 ----------------------------------------------------------------- */
1541 PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU), 2237static const unsigned int scifa1_data_pins[] = {
1542 PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU), 2238 /* RXD, TXD */
1543 PINMUX_DATA(FSIAISLD_PU_MARK, PORT55_FN1, PORT55_IN_PU), 2239 228, 225,
1544}; 2240};
1545 2241static const unsigned int scifa1_data_mux[] = {
1546static struct pinmux_gpio pinmux_gpios[] = { 2242 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1547 GPIO_PORT_ALL(), 2243};
2244static const unsigned int scifa1_clk_pins[] = {
2245 /* SCK */
2246 226,
2247};
2248static const unsigned int scifa1_clk_mux[] = {
2249 SCIFA1_SCK_MARK,
2250};
2251static const unsigned int scifa1_ctrl_pins[] = {
2252 /* RTS, CTS */
2253 227, 229,
2254};
2255static const unsigned int scifa1_ctrl_mux[] = {
2256 SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
2257};
2258/* - SCIFA2 ----------------------------------------------------------------- */
2259static const unsigned int scifa2_data_0_pins[] = {
2260 /* RXD, TXD */
2261 155, 154,
2262};
2263static const unsigned int scifa2_data_0_mux[] = {
2264 SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
2265};
2266static const unsigned int scifa2_clk_0_pins[] = {
2267 /* SCK */
2268 158,
2269};
2270static const unsigned int scifa2_clk_0_mux[] = {
2271 SCIFA2_SCK1_MARK,
2272};
2273static const unsigned int scifa2_ctrl_0_pins[] = {
2274 /* RTS, CTS */
2275 156, 157,
2276};
2277static const unsigned int scifa2_ctrl_0_mux[] = {
2278 SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
2279};
2280static const unsigned int scifa2_data_1_pins[] = {
2281 /* RXD, TXD */
2282 233, 230,
2283};
2284static const unsigned int scifa2_data_1_mux[] = {
2285 SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
2286};
2287static const unsigned int scifa2_clk_1_pins[] = {
2288 /* SCK */
2289 232,
2290};
2291static const unsigned int scifa2_clk_1_mux[] = {
2292 SCIFA2_SCK2_MARK,
2293};
2294static const unsigned int scifa2_ctrl_1_pins[] = {
2295 /* RTS, CTS */
2296 234, 231,
2297};
2298static const unsigned int scifa2_ctrl_1_mux[] = {
2299 SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
2300};
2301/* - SCIFA3 ----------------------------------------------------------------- */
2302static const unsigned int scifa3_data_pins[] = {
2303 /* RXD, TXD */
2304 108, 110,
2305};
2306static const unsigned int scifa3_data_mux[] = {
2307 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2308};
2309static const unsigned int scifa3_ctrl_pins[] = {
2310 /* RTS, CTS */
2311 109, 107,
2312};
2313static const unsigned int scifa3_ctrl_mux[] = {
2314 SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
2315};
2316/* - SCIFA4 ----------------------------------------------------------------- */
2317static const unsigned int scifa4_data_pins[] = {
2318 /* RXD, TXD */
2319 33, 32,
2320};
2321static const unsigned int scifa4_data_mux[] = {
2322 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2323};
2324static const unsigned int scifa4_ctrl_pins[] = {
2325 /* RTS, CTS */
2326 34, 35,
2327};
2328static const unsigned int scifa4_ctrl_mux[] = {
2329 SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
2330};
2331/* - SCIFA5 ----------------------------------------------------------------- */
2332static const unsigned int scifa5_data_0_pins[] = {
2333 /* RXD, TXD */
2334 246, 247,
2335};
2336static const unsigned int scifa5_data_0_mux[] = {
2337 PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
2338};
2339static const unsigned int scifa5_clk_0_pins[] = {
2340 /* SCK */
2341 248,
2342};
2343static const unsigned int scifa5_clk_0_mux[] = {
2344 PORT248_SCIFA5_SCK_MARK,
2345};
2346static const unsigned int scifa5_ctrl_0_pins[] = {
2347 /* RTS, CTS */
2348 245, 244,
2349};
2350static const unsigned int scifa5_ctrl_0_mux[] = {
2351 PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
2352};
2353static const unsigned int scifa5_data_1_pins[] = {
2354 /* RXD, TXD */
2355 195, 196,
2356};
2357static const unsigned int scifa5_data_1_mux[] = {
2358 PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
2359};
2360static const unsigned int scifa5_clk_1_pins[] = {
2361 /* SCK */
2362 197,
2363};
2364static const unsigned int scifa5_clk_1_mux[] = {
2365 PORT197_SCIFA5_SCK_MARK,
2366};
2367static const unsigned int scifa5_ctrl_1_pins[] = {
2368 /* RTS, CTS */
2369 194, 193,
2370};
2371static const unsigned int scifa5_ctrl_1_mux[] = {
2372 PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
2373};
2374static const unsigned int scifa5_data_2_pins[] = {
2375 /* RXD, TXD */
2376 162, 160,
2377};
2378static const unsigned int scifa5_data_2_mux[] = {
2379 PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
2380};
2381static const unsigned int scifa5_clk_2_pins[] = {
2382 /* SCK */
2383 159,
2384};
2385static const unsigned int scifa5_clk_2_mux[] = {
2386 PORT159_SCIFA5_SCK_MARK,
2387};
2388static const unsigned int scifa5_ctrl_2_pins[] = {
2389 /* RTS, CTS */
2390 163, 161,
2391};
2392static const unsigned int scifa5_ctrl_2_mux[] = {
2393 PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
2394};
2395/* - SCIFA6 ----------------------------------------------------------------- */
2396static const unsigned int scifa6_pins[] = {
2397 /* TXD */
2398 240,
2399};
2400static const unsigned int scifa6_mux[] = {
2401 SCIFA6_TXD_MARK,
2402};
2403/* - SCIFA7 ----------------------------------------------------------------- */
2404static const unsigned int scifa7_data_pins[] = {
2405 /* RXD, TXD */
2406 12, 18,
2407};
2408static const unsigned int scifa7_data_mux[] = {
2409 SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2410};
2411static const unsigned int scifa7_ctrl_pins[] = {
2412 /* RTS, CTS */
2413 19, 13,
2414};
2415static const unsigned int scifa7_ctrl_mux[] = {
2416 SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
2417};
2418/* - SCIFB ------------------------------------------------------------------ */
2419static const unsigned int scifb_data_0_pins[] = {
2420 /* RXD, TXD */
2421 162, 160,
2422};
2423static const unsigned int scifb_data_0_mux[] = {
2424 PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
2425};
2426static const unsigned int scifb_clk_0_pins[] = {
2427 /* SCK */
2428 159,
2429};
2430static const unsigned int scifb_clk_0_mux[] = {
2431 PORT159_SCIFB_SCK_MARK,
2432};
2433static const unsigned int scifb_ctrl_0_pins[] = {
2434 /* RTS, CTS */
2435 163, 161,
2436};
2437static const unsigned int scifb_ctrl_0_mux[] = {
2438 PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
2439};
2440static const unsigned int scifb_data_1_pins[] = {
2441 /* RXD, TXD */
2442 246, 247,
2443};
2444static const unsigned int scifb_data_1_mux[] = {
2445 PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
2446};
2447static const unsigned int scifb_clk_1_pins[] = {
2448 /* SCK */
2449 248,
2450};
2451static const unsigned int scifb_clk_1_mux[] = {
2452 PORT248_SCIFB_SCK_MARK,
2453};
2454static const unsigned int scifb_ctrl_1_pins[] = {
2455 /* RTS, CTS */
2456 245, 244,
2457};
2458static const unsigned int scifb_ctrl_1_mux[] = {
2459 PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
2460};
2461/* - SDHI0 ------------------------------------------------------------------ */
2462static const unsigned int sdhi0_data1_pins[] = {
2463 /* D0 */
2464 252,
2465};
2466static const unsigned int sdhi0_data1_mux[] = {
2467 SDHID0_0_MARK,
2468};
2469static const unsigned int sdhi0_data4_pins[] = {
2470 /* D[0:3] */
2471 252, 253, 254, 255,
2472};
2473static const unsigned int sdhi0_data4_mux[] = {
2474 SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
2475};
2476static const unsigned int sdhi0_ctrl_pins[] = {
2477 /* CMD, CLK */
2478 256, 250,
2479};
2480static const unsigned int sdhi0_ctrl_mux[] = {
2481 SDHICMD0_MARK, SDHICLK0_MARK,
2482};
2483static const unsigned int sdhi0_cd_pins[] = {
2484 /* CD */
2485 251,
2486};
2487static const unsigned int sdhi0_cd_mux[] = {
2488 SDHICD0_MARK,
2489};
2490static const unsigned int sdhi0_wp_pins[] = {
2491 /* WP */
2492 257,
2493};
2494static const unsigned int sdhi0_wp_mux[] = {
2495 SDHIWP0_MARK,
2496};
2497/* - SDHI1 ------------------------------------------------------------------ */
2498static const unsigned int sdhi1_data1_pins[] = {
2499 /* D0 */
2500 259,
2501};
2502static const unsigned int sdhi1_data1_mux[] = {
2503 SDHID1_0_MARK,
2504};
2505static const unsigned int sdhi1_data4_pins[] = {
2506 /* D[0:3] */
2507 259, 260, 261, 262,
2508};
2509static const unsigned int sdhi1_data4_mux[] = {
2510 SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
2511};
2512static const unsigned int sdhi1_ctrl_pins[] = {
2513 /* CMD, CLK */
2514 263, 258,
2515};
2516static const unsigned int sdhi1_ctrl_mux[] = {
2517 SDHICMD1_MARK, SDHICLK1_MARK,
2518};
2519/* - SDHI2 ------------------------------------------------------------------ */
2520static const unsigned int sdhi2_data1_pins[] = {
2521 /* D0 */
2522 265,
2523};
2524static const unsigned int sdhi2_data1_mux[] = {
2525 SDHID2_0_MARK,
2526};
2527static const unsigned int sdhi2_data4_pins[] = {
2528 /* D[0:3] */
2529 265, 266, 267, 268,
2530};
2531static const unsigned int sdhi2_data4_mux[] = {
2532 SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
2533};
2534static const unsigned int sdhi2_ctrl_pins[] = {
2535 /* CMD, CLK */
2536 269, 264,
2537};
2538static const unsigned int sdhi2_ctrl_mux[] = {
2539 SDHICMD2_MARK, SDHICLK2_MARK,
2540};
2541/* - USB -------------------------------------------------------------------- */
2542static const unsigned int usb_vbus_pins[] = {
2543 /* VBUS */
2544 0,
2545};
2546static const unsigned int usb_vbus_mux[] = {
2547 VBUS_0_MARK,
2548};
2549
2550static const struct sh_pfc_pin_group pinmux_groups[] = {
2551 SH_PFC_PIN_GROUP(bsc_data_0_7),
2552 SH_PFC_PIN_GROUP(bsc_data_8_15),
2553 SH_PFC_PIN_GROUP(bsc_cs4),
2554 SH_PFC_PIN_GROUP(bsc_cs5_a),
2555 SH_PFC_PIN_GROUP(bsc_cs5_b),
2556 SH_PFC_PIN_GROUP(bsc_cs6_a),
2557 SH_PFC_PIN_GROUP(bsc_cs6_b),
2558 SH_PFC_PIN_GROUP(bsc_rd),
2559 SH_PFC_PIN_GROUP(bsc_rdwr_0),
2560 SH_PFC_PIN_GROUP(bsc_rdwr_1),
2561 SH_PFC_PIN_GROUP(bsc_rdwr_2),
2562 SH_PFC_PIN_GROUP(bsc_we0),
2563 SH_PFC_PIN_GROUP(bsc_we1),
2564 SH_PFC_PIN_GROUP(fsia_mclk_in),
2565 SH_PFC_PIN_GROUP(fsia_mclk_out),
2566 SH_PFC_PIN_GROUP(fsia_sclk_in),
2567 SH_PFC_PIN_GROUP(fsia_sclk_out),
2568 SH_PFC_PIN_GROUP(fsia_data_in),
2569 SH_PFC_PIN_GROUP(fsia_data_out),
2570 SH_PFC_PIN_GROUP(fsia_spdif),
2571 SH_PFC_PIN_GROUP(fsib_mclk_in),
2572 SH_PFC_PIN_GROUP(fsib_mclk_out),
2573 SH_PFC_PIN_GROUP(fsib_sclk_in),
2574 SH_PFC_PIN_GROUP(fsib_sclk_out),
2575 SH_PFC_PIN_GROUP(fsib_data_in),
2576 SH_PFC_PIN_GROUP(fsib_data_out),
2577 SH_PFC_PIN_GROUP(fsib_spdif),
2578 SH_PFC_PIN_GROUP(fsic_mclk_in),
2579 SH_PFC_PIN_GROUP(fsic_mclk_out),
2580 SH_PFC_PIN_GROUP(fsic_sclk_in),
2581 SH_PFC_PIN_GROUP(fsic_sclk_out),
2582 SH_PFC_PIN_GROUP(fsic_data_in),
2583 SH_PFC_PIN_GROUP(fsic_data_out),
2584 SH_PFC_PIN_GROUP(fsic_spdif_0),
2585 SH_PFC_PIN_GROUP(fsic_spdif_1),
2586 SH_PFC_PIN_GROUP(fsid_sclk_in),
2587 SH_PFC_PIN_GROUP(fsid_sclk_out),
2588 SH_PFC_PIN_GROUP(fsid_data_in),
2589 SH_PFC_PIN_GROUP(i2c2_0),
2590 SH_PFC_PIN_GROUP(i2c2_1),
2591 SH_PFC_PIN_GROUP(i2c2_2),
2592 SH_PFC_PIN_GROUP(i2c3_0),
2593 SH_PFC_PIN_GROUP(i2c3_1),
2594 SH_PFC_PIN_GROUP(i2c3_2),
2595 SH_PFC_PIN_GROUP(irda_0),
2596 SH_PFC_PIN_GROUP(irda_1),
2597 SH_PFC_PIN_GROUP(keysc_in5),
2598 SH_PFC_PIN_GROUP(keysc_in6),
2599 SH_PFC_PIN_GROUP(keysc_in7),
2600 SH_PFC_PIN_GROUP(keysc_in8),
2601 SH_PFC_PIN_GROUP(keysc_out04),
2602 SH_PFC_PIN_GROUP(keysc_out5),
2603 SH_PFC_PIN_GROUP(keysc_out6_0),
2604 SH_PFC_PIN_GROUP(keysc_out6_1),
2605 SH_PFC_PIN_GROUP(keysc_out6_2),
2606 SH_PFC_PIN_GROUP(keysc_out7_0),
2607 SH_PFC_PIN_GROUP(keysc_out7_1),
2608 SH_PFC_PIN_GROUP(keysc_out7_2),
2609 SH_PFC_PIN_GROUP(keysc_out8_0),
2610 SH_PFC_PIN_GROUP(keysc_out8_1),
2611 SH_PFC_PIN_GROUP(keysc_out8_2),
2612 SH_PFC_PIN_GROUP(keysc_out9_0),
2613 SH_PFC_PIN_GROUP(keysc_out9_1),
2614 SH_PFC_PIN_GROUP(keysc_out9_2),
2615 SH_PFC_PIN_GROUP(keysc_out10_0),
2616 SH_PFC_PIN_GROUP(keysc_out10_1),
2617 SH_PFC_PIN_GROUP(keysc_out11_0),
2618 SH_PFC_PIN_GROUP(keysc_out11_1),
2619 SH_PFC_PIN_GROUP(lcd_data8),
2620 SH_PFC_PIN_GROUP(lcd_data9),
2621 SH_PFC_PIN_GROUP(lcd_data12),
2622 SH_PFC_PIN_GROUP(lcd_data16),
2623 SH_PFC_PIN_GROUP(lcd_data18),
2624 SH_PFC_PIN_GROUP(lcd_data24),
2625 SH_PFC_PIN_GROUP(lcd_display),
2626 SH_PFC_PIN_GROUP(lcd_lclk),
2627 SH_PFC_PIN_GROUP(lcd_sync),
2628 SH_PFC_PIN_GROUP(lcd_sys),
2629 SH_PFC_PIN_GROUP(lcd2_data8),
2630 SH_PFC_PIN_GROUP(lcd2_data9),
2631 SH_PFC_PIN_GROUP(lcd2_data12),
2632 SH_PFC_PIN_GROUP(lcd2_data16),
2633 SH_PFC_PIN_GROUP(lcd2_data18),
2634 SH_PFC_PIN_GROUP(lcd2_data24),
2635 SH_PFC_PIN_GROUP(lcd2_sync_0),
2636 SH_PFC_PIN_GROUP(lcd2_sync_1),
2637 SH_PFC_PIN_GROUP(lcd2_sys_0),
2638 SH_PFC_PIN_GROUP(lcd2_sys_1),
2639 SH_PFC_PIN_GROUP(mmc0_data1_0),
2640 SH_PFC_PIN_GROUP(mmc0_data4_0),
2641 SH_PFC_PIN_GROUP(mmc0_data8_0),
2642 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2643 SH_PFC_PIN_GROUP(mmc0_data1_1),
2644 SH_PFC_PIN_GROUP(mmc0_data4_1),
2645 SH_PFC_PIN_GROUP(mmc0_data8_1),
2646 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
2647 SH_PFC_PIN_GROUP(scifa0_data),
2648 SH_PFC_PIN_GROUP(scifa0_clk),
2649 SH_PFC_PIN_GROUP(scifa0_ctrl),
2650 SH_PFC_PIN_GROUP(scifa1_data),
2651 SH_PFC_PIN_GROUP(scifa1_clk),
2652 SH_PFC_PIN_GROUP(scifa1_ctrl),
2653 SH_PFC_PIN_GROUP(scifa2_data_0),
2654 SH_PFC_PIN_GROUP(scifa2_clk_0),
2655 SH_PFC_PIN_GROUP(scifa2_ctrl_0),
2656 SH_PFC_PIN_GROUP(scifa2_data_1),
2657 SH_PFC_PIN_GROUP(scifa2_clk_1),
2658 SH_PFC_PIN_GROUP(scifa2_ctrl_1),
2659 SH_PFC_PIN_GROUP(scifa3_data),
2660 SH_PFC_PIN_GROUP(scifa3_ctrl),
2661 SH_PFC_PIN_GROUP(scifa4_data),
2662 SH_PFC_PIN_GROUP(scifa4_ctrl),
2663 SH_PFC_PIN_GROUP(scifa5_data_0),
2664 SH_PFC_PIN_GROUP(scifa5_clk_0),
2665 SH_PFC_PIN_GROUP(scifa5_ctrl_0),
2666 SH_PFC_PIN_GROUP(scifa5_data_1),
2667 SH_PFC_PIN_GROUP(scifa5_clk_1),
2668 SH_PFC_PIN_GROUP(scifa5_ctrl_1),
2669 SH_PFC_PIN_GROUP(scifa5_data_2),
2670 SH_PFC_PIN_GROUP(scifa5_clk_2),
2671 SH_PFC_PIN_GROUP(scifa5_ctrl_2),
2672 SH_PFC_PIN_GROUP(scifa6),
2673 SH_PFC_PIN_GROUP(scifa7_data),
2674 SH_PFC_PIN_GROUP(scifa7_ctrl),
2675 SH_PFC_PIN_GROUP(scifb_data_0),
2676 SH_PFC_PIN_GROUP(scifb_clk_0),
2677 SH_PFC_PIN_GROUP(scifb_ctrl_0),
2678 SH_PFC_PIN_GROUP(scifb_data_1),
2679 SH_PFC_PIN_GROUP(scifb_clk_1),
2680 SH_PFC_PIN_GROUP(scifb_ctrl_1),
2681 SH_PFC_PIN_GROUP(sdhi0_data1),
2682 SH_PFC_PIN_GROUP(sdhi0_data4),
2683 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2684 SH_PFC_PIN_GROUP(sdhi0_cd),
2685 SH_PFC_PIN_GROUP(sdhi0_wp),
2686 SH_PFC_PIN_GROUP(sdhi1_data1),
2687 SH_PFC_PIN_GROUP(sdhi1_data4),
2688 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2689 SH_PFC_PIN_GROUP(sdhi2_data1),
2690 SH_PFC_PIN_GROUP(sdhi2_data4),
2691 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2692 SH_PFC_PIN_GROUP(usb_vbus),
2693};
2694
2695static const char * const bsc_groups[] = {
2696 "bsc_data_0_7",
2697 "bsc_data_8_15",
2698 "bsc_cs4",
2699 "bsc_cs5_a",
2700 "bsc_cs5_b",
2701 "bsc_cs6_a",
2702 "bsc_cs6_b",
2703 "bsc_rd",
2704 "bsc_rdwr_0",
2705 "bsc_rdwr_1",
2706 "bsc_rdwr_2",
2707 "bsc_we0",
2708 "bsc_we1",
2709};
2710
2711static const char * const fsia_groups[] = {
2712 "fsia_mclk_in",
2713 "fsia_mclk_out",
2714 "fsia_sclk_in",
2715 "fsia_sclk_out",
2716 "fsia_data_in",
2717 "fsia_data_out",
2718 "fsia_spdif",
2719};
2720
2721static const char * const fsib_groups[] = {
2722 "fsib_mclk_in",
2723 "fsib_mclk_out",
2724 "fsib_sclk_in",
2725 "fsib_sclk_out",
2726 "fsib_data_in",
2727 "fsib_data_out",
2728 "fsib_spdif",
2729};
2730
2731static const char * const fsic_groups[] = {
2732 "fsic_mclk_in",
2733 "fsic_mclk_out",
2734 "fsic_sclk_in",
2735 "fsic_sclk_out",
2736 "fsic_data_in",
2737 "fsic_data_out",
2738 "fsic_spdif",
2739};
2740
2741static const char * const fsid_groups[] = {
2742 "fsid_sclk_in",
2743 "fsid_sclk_out",
2744 "fsid_data_in",
2745};
2746
2747static const char * const i2c2_groups[] = {
2748 "i2c2_0",
2749 "i2c2_1",
2750 "i2c2_2",
2751};
2752
2753static const char * const i2c3_groups[] = {
2754 "i2c3_0",
2755 "i2c3_1",
2756 "i2c3_2",
2757};
2758
2759static const char * const irda_groups[] = {
2760 "irda_0",
2761 "irda_1",
2762};
1548 2763
2764static const char * const keysc_groups[] = {
2765 "keysc_in5",
2766 "keysc_in6",
2767 "keysc_in7",
2768 "keysc_in8",
2769 "keysc_out04",
2770 "keysc_out5",
2771 "keysc_out6_0",
2772 "keysc_out6_1",
2773 "keysc_out6_2",
2774 "keysc_out7_0",
2775 "keysc_out7_1",
2776 "keysc_out7_2",
2777 "keysc_out8_0",
2778 "keysc_out8_1",
2779 "keysc_out8_2",
2780 "keysc_out9_0",
2781 "keysc_out9_1",
2782 "keysc_out9_2",
2783 "keysc_out10_0",
2784 "keysc_out10_1",
2785 "keysc_out11_0",
2786 "keysc_out11_1",
2787};
2788
2789static const char * const lcd_groups[] = {
2790 "lcd_data8",
2791 "lcd_data9",
2792 "lcd_data12",
2793 "lcd_data16",
2794 "lcd_data18",
2795 "lcd_data24",
2796 "lcd_display",
2797 "lcd_lclk",
2798 "lcd_sync",
2799 "lcd_sys",
2800};
2801
2802static const char * const lcd2_groups[] = {
2803 "lcd2_data8",
2804 "lcd2_data9",
2805 "lcd2_data12",
2806 "lcd2_data16",
2807 "lcd2_data18",
2808 "lcd2_data24",
2809 "lcd2_sync_0",
2810 "lcd2_sync_1",
2811 "lcd2_sys_0",
2812 "lcd2_sys_1",
2813};
2814
2815static const char * const mmc0_groups[] = {
2816 "mmc0_data1_0",
2817 "mmc0_data4_0",
2818 "mmc0_data8_0",
2819 "mmc0_ctrl_0",
2820 "mmc0_data1_1",
2821 "mmc0_data4_1",
2822 "mmc0_data8_1",
2823 "mmc0_ctrl_1",
2824};
2825
2826static const char * const scifa0_groups[] = {
2827 "scifa0_data",
2828 "scifa0_clk",
2829 "scifa0_ctrl",
2830};
2831
2832static const char * const scifa1_groups[] = {
2833 "scifa1_data",
2834 "scifa1_clk",
2835 "scifa1_ctrl",
2836};
2837
2838static const char * const scifa2_groups[] = {
2839 "scifa2_data_0",
2840 "scifa2_clk_0",
2841 "scifa2_ctrl_0",
2842 "scifa2_data_1",
2843 "scifa2_clk_1",
2844 "scifa2_ctrl_1",
2845};
2846
2847static const char * const scifa3_groups[] = {
2848 "scifa3_data",
2849 "scifa3_ctrl",
2850};
2851
2852static const char * const scifa4_groups[] = {
2853 "scifa4_data",
2854 "scifa4_ctrl",
2855};
2856
2857static const char * const scifa5_groups[] = {
2858 "scifa5_data_0",
2859 "scifa5_clk_0",
2860 "scifa5_ctrl_0",
2861 "scifa5_data_1",
2862 "scifa5_clk_1",
2863 "scifa5_ctrl_1",
2864 "scifa5_data_2",
2865 "scifa5_clk_2",
2866 "scifa5_ctrl_2",
2867};
2868
2869static const char * const scifa6_groups[] = {
2870 "scifa6",
2871};
2872
2873static const char * const scifa7_groups[] = {
2874 "scifa7_data",
2875 "scifa7_ctrl",
2876};
2877
2878static const char * const scifb_groups[] = {
2879 "scifb_data_0",
2880 "scifb_clk_0",
2881 "scifb_ctrl_0",
2882 "scifb_data_1",
2883 "scifb_clk_1",
2884 "scifb_ctrl_1",
2885};
2886
2887static const char * const sdhi0_groups[] = {
2888 "sdhi0_data1",
2889 "sdhi0_data4",
2890 "sdhi0_ctrl",
2891 "sdhi0_cd",
2892 "sdhi0_wp",
2893};
2894
2895static const char * const sdhi1_groups[] = {
2896 "sdhi1_data1",
2897 "sdhi1_data4",
2898 "sdhi1_ctrl",
2899};
2900
2901static const char * const sdhi2_groups[] = {
2902 "sdhi2_data1",
2903 "sdhi2_data4",
2904 "sdhi2_ctrl",
2905};
2906
2907static const char * const usb_groups[] = {
2908 "usb_vbus",
2909};
2910
2911static const struct sh_pfc_function pinmux_functions[] = {
2912 SH_PFC_FUNCTION(bsc),
2913 SH_PFC_FUNCTION(fsia),
2914 SH_PFC_FUNCTION(fsib),
2915 SH_PFC_FUNCTION(fsic),
2916 SH_PFC_FUNCTION(fsid),
2917 SH_PFC_FUNCTION(i2c2),
2918 SH_PFC_FUNCTION(i2c3),
2919 SH_PFC_FUNCTION(irda),
2920 SH_PFC_FUNCTION(keysc),
2921 SH_PFC_FUNCTION(lcd),
2922 SH_PFC_FUNCTION(lcd2),
2923 SH_PFC_FUNCTION(mmc0),
2924 SH_PFC_FUNCTION(scifa0),
2925 SH_PFC_FUNCTION(scifa1),
2926 SH_PFC_FUNCTION(scifa2),
2927 SH_PFC_FUNCTION(scifa3),
2928 SH_PFC_FUNCTION(scifa4),
2929 SH_PFC_FUNCTION(scifa5),
2930 SH_PFC_FUNCTION(scifa6),
2931 SH_PFC_FUNCTION(scifa7),
2932 SH_PFC_FUNCTION(scifb),
2933 SH_PFC_FUNCTION(sdhi0),
2934 SH_PFC_FUNCTION(sdhi1),
2935 SH_PFC_FUNCTION(sdhi2),
2936 SH_PFC_FUNCTION(usb),
2937};
2938
2939#define PINMUX_FN_BASE GPIO_FN_GPI0
2940
2941static const struct pinmux_func pinmux_func_gpios[] = {
1549 /* Table 25-1 (Functions 0-7) */ 2942 /* Table 25-1 (Functions 0-7) */
1550 GPIO_FN(VBUS_0),
1551 GPIO_FN(GPI0), 2943 GPIO_FN(GPI0),
1552 GPIO_FN(GPI1), 2944 GPIO_FN(GPI1),
1553 GPIO_FN(GPI2), 2945 GPIO_FN(GPI2),
@@ -1556,19 +2948,12 @@ static struct pinmux_gpio pinmux_gpios[] = {
1556 GPIO_FN(GPI5), 2948 GPIO_FN(GPI5),
1557 GPIO_FN(GPI6), 2949 GPIO_FN(GPI6),
1558 GPIO_FN(GPI7), 2950 GPIO_FN(GPI7),
1559 GPIO_FN(SCIFA7_RXD),
1560 GPIO_FN(SCIFA7_CTS_),
1561 GPIO_FN(GPO7), \ 2951 GPIO_FN(GPO7), \
1562 GPIO_FN(MFG0_OUT2), 2952 GPIO_FN(MFG0_OUT2),
1563 GPIO_FN(GPO6), \ 2953 GPIO_FN(GPO6), \
1564 GPIO_FN(MFG1_OUT2), 2954 GPIO_FN(MFG1_OUT2),
1565 GPIO_FN(GPO5), \ 2955 GPIO_FN(GPO5), \
1566 GPIO_FN(SCIFA0_SCK), \
1567 GPIO_FN(FSICOSLDT3), \
1568 GPIO_FN(PORT16_VIO_CKOR), 2956 GPIO_FN(PORT16_VIO_CKOR),
1569 GPIO_FN(SCIFA0_TXD),
1570 GPIO_FN(SCIFA7_TXD),
1571 GPIO_FN(SCIFA7_RTS_), \
1572 GPIO_FN(PORT19_VIO_CKO2), 2957 GPIO_FN(PORT19_VIO_CKO2),
1573 GPIO_FN(GPO0), 2958 GPIO_FN(GPO0),
1574 GPIO_FN(GPO1), 2959 GPIO_FN(GPO1),
@@ -1581,13 +2966,9 @@ static struct pinmux_gpio pinmux_gpios[] = {
1581 GPIO_FN(VINT), 2966 GPIO_FN(VINT),
1582 GPIO_FN(TCKON), 2967 GPIO_FN(TCKON),
1583 GPIO_FN(XDVFS1), \ 2968 GPIO_FN(XDVFS1), \
1584 GPIO_FN(PORT27_I2C_SCL2), \
1585 GPIO_FN(PORT27_I2C_SCL3), \
1586 GPIO_FN(MFG0_OUT1), \ 2969 GPIO_FN(MFG0_OUT1), \
1587 GPIO_FN(PORT27_IROUT), 2970 GPIO_FN(PORT27_IROUT),
1588 GPIO_FN(XDVFS2), \ 2971 GPIO_FN(XDVFS2), \
1589 GPIO_FN(PORT28_I2C_SDA2), \
1590 GPIO_FN(PORT28_I2C_SDA3), \
1591 GPIO_FN(PORT28_TPU1TO1), 2972 GPIO_FN(PORT28_TPU1TO1),
1592 GPIO_FN(SIM_RST), \ 2973 GPIO_FN(SIM_RST), \
1593 GPIO_FN(PORT29_TPU1TO1), 2974 GPIO_FN(PORT29_TPU1TO1),
@@ -1595,140 +2976,53 @@ static struct pinmux_gpio pinmux_gpios[] = {
1595 GPIO_FN(PORT30_VIO_CKOR), 2976 GPIO_FN(PORT30_VIO_CKOR),
1596 GPIO_FN(SIM_D), \ 2977 GPIO_FN(SIM_D), \
1597 GPIO_FN(PORT31_IROUT), 2978 GPIO_FN(PORT31_IROUT),
1598 GPIO_FN(SCIFA4_TXD),
1599 GPIO_FN(SCIFA4_RXD), \
1600 GPIO_FN(XWUP), 2979 GPIO_FN(XWUP),
1601 GPIO_FN(SCIFA4_RTS_),
1602 GPIO_FN(SCIFA4_CTS_),
1603 GPIO_FN(FSIBOBT), \
1604 GPIO_FN(FSIBIBT),
1605 GPIO_FN(FSIBOLR), \
1606 GPIO_FN(FSIBILR),
1607 GPIO_FN(FSIBOSLD),
1608 GPIO_FN(FSIBISLD),
1609 GPIO_FN(VACK), 2980 GPIO_FN(VACK),
1610 GPIO_FN(XTAL1L), 2981 GPIO_FN(XTAL1L),
1611 GPIO_FN(SCIFA0_RTS_), \
1612 GPIO_FN(FSICOSLDT2),
1613 GPIO_FN(SCIFA0_RXD),
1614 GPIO_FN(SCIFA0_CTS_), \
1615 GPIO_FN(FSICOSLDT1),
1616 GPIO_FN(FSICOBT), \
1617 GPIO_FN(FSICIBT), \
1618 GPIO_FN(FSIDOBT), \
1619 GPIO_FN(FSIDIBT),
1620 GPIO_FN(FSICOLR), \
1621 GPIO_FN(FSICILR), \
1622 GPIO_FN(FSIDOLR), \
1623 GPIO_FN(FSIDILR),
1624 GPIO_FN(FSICOSLD), \
1625 GPIO_FN(PORT47_FSICSPDIF),
1626 GPIO_FN(FSICISLD), \
1627 GPIO_FN(FSIDISLD),
1628 GPIO_FN(FSIACK), \
1629 GPIO_FN(PORT49_IRDA_OUT), \
1630 GPIO_FN(PORT49_IROUT), \ 2982 GPIO_FN(PORT49_IROUT), \
1631 GPIO_FN(FSIAOMC),
1632 GPIO_FN(FSIAOLR), \
1633 GPIO_FN(BBIF2_TSYNC2), \ 2983 GPIO_FN(BBIF2_TSYNC2), \
1634 GPIO_FN(TPU2TO2), \ 2984 GPIO_FN(TPU2TO2), \
1635 GPIO_FN(FSIAILR),
1636 2985
1637 GPIO_FN(FSIAOBT), \
1638 GPIO_FN(BBIF2_TSCK2), \ 2986 GPIO_FN(BBIF2_TSCK2), \
1639 GPIO_FN(TPU2TO3), \ 2987 GPIO_FN(TPU2TO3), \
1640 GPIO_FN(FSIAIBT),
1641 GPIO_FN(FSIAOSLD), \
1642 GPIO_FN(BBIF2_TXD2), 2988 GPIO_FN(BBIF2_TXD2),
1643 GPIO_FN(FSIASPDIF), \
1644 GPIO_FN(PORT53_IRDA_IN), \
1645 GPIO_FN(TPU3TO3), \ 2989 GPIO_FN(TPU3TO3), \
1646 GPIO_FN(FSIBSPDIF), \
1647 GPIO_FN(PORT53_FSICSPDIF),
1648 GPIO_FN(FSIBCK), \
1649 GPIO_FN(PORT54_IRDA_FIRSEL), \
1650 GPIO_FN(TPU3TO2), \ 2990 GPIO_FN(TPU3TO2), \
1651 GPIO_FN(FSIBOMC), \
1652 GPIO_FN(FSICCK), \
1653 GPIO_FN(FSICOMC),
1654 GPIO_FN(FSIAISLD), \
1655 GPIO_FN(TPU0TO0), 2991 GPIO_FN(TPU0TO0),
1656 GPIO_FN(A0), \ 2992 GPIO_FN(A0), \
1657 GPIO_FN(BS_), 2993 GPIO_FN(BS_),
1658 GPIO_FN(A12), \ 2994 GPIO_FN(A12), \
1659 GPIO_FN(PORT58_KEYOUT7), \
1660 GPIO_FN(TPU4TO2), 2995 GPIO_FN(TPU4TO2),
1661 GPIO_FN(A13), \ 2996 GPIO_FN(A13), \
1662 GPIO_FN(PORT59_KEYOUT6), \
1663 GPIO_FN(TPU0TO1), 2997 GPIO_FN(TPU0TO1),
1664 GPIO_FN(A14), \ 2998 GPIO_FN(A14), \
1665 GPIO_FN(KEYOUT5),
1666 GPIO_FN(A15), \ 2999 GPIO_FN(A15), \
1667 GPIO_FN(KEYOUT4),
1668 GPIO_FN(A16), \ 3000 GPIO_FN(A16), \
1669 GPIO_FN(KEYOUT3), \
1670 GPIO_FN(MSIOF0_SS1), 3001 GPIO_FN(MSIOF0_SS1),
1671 GPIO_FN(A17), \ 3002 GPIO_FN(A17), \
1672 GPIO_FN(KEYOUT2), \
1673 GPIO_FN(MSIOF0_TSYNC), 3003 GPIO_FN(MSIOF0_TSYNC),
1674 GPIO_FN(A18), \ 3004 GPIO_FN(A18), \
1675 GPIO_FN(KEYOUT1), \
1676 GPIO_FN(MSIOF0_TSCK), 3005 GPIO_FN(MSIOF0_TSCK),
1677 GPIO_FN(A19), \ 3006 GPIO_FN(A19), \
1678 GPIO_FN(KEYOUT0), \
1679 GPIO_FN(MSIOF0_TXD), 3007 GPIO_FN(MSIOF0_TXD),
1680 GPIO_FN(A20), \ 3008 GPIO_FN(A20), \
1681 GPIO_FN(KEYIN0), \
1682 GPIO_FN(MSIOF0_RSCK), 3009 GPIO_FN(MSIOF0_RSCK),
1683 GPIO_FN(A21), \ 3010 GPIO_FN(A21), \
1684 GPIO_FN(KEYIN1), \
1685 GPIO_FN(MSIOF0_RSYNC), 3011 GPIO_FN(MSIOF0_RSYNC),
1686 GPIO_FN(A22), \ 3012 GPIO_FN(A22), \
1687 GPIO_FN(KEYIN2), \
1688 GPIO_FN(MSIOF0_MCK0), 3013 GPIO_FN(MSIOF0_MCK0),
1689 GPIO_FN(A23), \ 3014 GPIO_FN(A23), \
1690 GPIO_FN(KEYIN3), \
1691 GPIO_FN(MSIOF0_MCK1), 3015 GPIO_FN(MSIOF0_MCK1),
1692 GPIO_FN(A24), \ 3016 GPIO_FN(A24), \
1693 GPIO_FN(KEYIN4), \
1694 GPIO_FN(MSIOF0_RXD), 3017 GPIO_FN(MSIOF0_RXD),
1695 GPIO_FN(A25), \ 3018 GPIO_FN(A25), \
1696 GPIO_FN(KEYIN5), \
1697 GPIO_FN(MSIOF0_SS2), 3019 GPIO_FN(MSIOF0_SS2),
1698 GPIO_FN(A26), \ 3020 GPIO_FN(A26), \
1699 GPIO_FN(KEYIN6),
1700 GPIO_FN(KEYIN7),
1701 GPIO_FN(D0_NAF0),
1702 GPIO_FN(D1_NAF1),
1703 GPIO_FN(D2_NAF2),
1704 GPIO_FN(D3_NAF3),
1705 GPIO_FN(D4_NAF4),
1706 GPIO_FN(D5_NAF5),
1707 GPIO_FN(D6_NAF6),
1708 GPIO_FN(D7_NAF7),
1709 GPIO_FN(D8_NAF8),
1710 GPIO_FN(D9_NAF9),
1711 GPIO_FN(D10_NAF10),
1712 GPIO_FN(D11_NAF11),
1713 GPIO_FN(D12_NAF12),
1714 GPIO_FN(D13_NAF13),
1715 GPIO_FN(D14_NAF14),
1716 GPIO_FN(D15_NAF15),
1717 GPIO_FN(CS4_),
1718 GPIO_FN(CS5A_), \
1719 GPIO_FN(PORT91_RDWR),
1720 GPIO_FN(CS5B_), \
1721 GPIO_FN(FCE1_), 3021 GPIO_FN(FCE1_),
1722 GPIO_FN(CS6B_), \
1723 GPIO_FN(DACK0), 3022 GPIO_FN(DACK0),
1724 GPIO_FN(FCE0_), \ 3023 GPIO_FN(FCE0_), \
1725 GPIO_FN(CS6A_),
1726 GPIO_FN(WAIT_), \ 3024 GPIO_FN(WAIT_), \
1727 GPIO_FN(DREQ0), 3025 GPIO_FN(DREQ0),
1728 GPIO_FN(RD__FSC),
1729 GPIO_FN(WE0__FWE), \
1730 GPIO_FN(RDWR_FWE),
1731 GPIO_FN(WE1_),
1732 GPIO_FN(FRB), 3026 GPIO_FN(FRB),
1733 GPIO_FN(CKO), 3027 GPIO_FN(CKO),
1734 GPIO_FN(NBRSTOUT_), 3028 GPIO_FN(NBRSTOUT_),
@@ -1737,14 +3031,10 @@ static struct pinmux_gpio pinmux_gpios[] = {
1737 GPIO_FN(BBIF2_RXD), 3031 GPIO_FN(BBIF2_RXD),
1738 GPIO_FN(BBIF2_SYNC), 3032 GPIO_FN(BBIF2_SYNC),
1739 GPIO_FN(BBIF2_SCK), 3033 GPIO_FN(BBIF2_SCK),
1740 GPIO_FN(SCIFA3_CTS_), \
1741 GPIO_FN(MFG3_IN2), 3034 GPIO_FN(MFG3_IN2),
1742 GPIO_FN(SCIFA3_RXD), \
1743 GPIO_FN(MFG3_IN1), 3035 GPIO_FN(MFG3_IN1),
1744 GPIO_FN(BBIF1_SS2), \ 3036 GPIO_FN(BBIF1_SS2), \
1745 GPIO_FN(SCIFA3_RTS_), \
1746 GPIO_FN(MFG3_OUT1), 3037 GPIO_FN(MFG3_OUT1),
1747 GPIO_FN(SCIFA3_TXD),
1748 GPIO_FN(HSI_RX_DATA), \ 3038 GPIO_FN(HSI_RX_DATA), \
1749 GPIO_FN(BBIF1_RXD), 3039 GPIO_FN(BBIF1_RXD),
1750 GPIO_FN(HSI_TX_WAKE), \ 3040 GPIO_FN(HSI_TX_WAKE), \
@@ -1755,103 +3045,57 @@ static struct pinmux_gpio pinmux_gpios[] = {
1755 GPIO_FN(BBIF1_TXD), 3045 GPIO_FN(BBIF1_TXD),
1756 GPIO_FN(HSI_RX_READY), \ 3046 GPIO_FN(HSI_RX_READY), \
1757 GPIO_FN(BBIF1_RSCK), \ 3047 GPIO_FN(BBIF1_RSCK), \
1758 GPIO_FN(PORT115_I2C_SCL2), \
1759 GPIO_FN(PORT115_I2C_SCL3),
1760 GPIO_FN(HSI_RX_WAKE), \ 3048 GPIO_FN(HSI_RX_WAKE), \
1761 GPIO_FN(BBIF1_RSYNC), \ 3049 GPIO_FN(BBIF1_RSYNC), \
1762 GPIO_FN(PORT116_I2C_SDA2), \
1763 GPIO_FN(PORT116_I2C_SDA3),
1764 GPIO_FN(HSI_RX_FLAG), \ 3050 GPIO_FN(HSI_RX_FLAG), \
1765 GPIO_FN(BBIF1_SS1), \ 3051 GPIO_FN(BBIF1_SS1), \
1766 GPIO_FN(BBIF1_FLOW), 3052 GPIO_FN(BBIF1_FLOW),
1767 GPIO_FN(HSI_TX_FLAG), 3053 GPIO_FN(HSI_TX_FLAG),
1768 GPIO_FN(VIO_VD), \ 3054 GPIO_FN(VIO_VD), \
1769 GPIO_FN(PORT128_LCD2VSYN), \
1770 GPIO_FN(VIO2_VD), \ 3055 GPIO_FN(VIO2_VD), \
1771 GPIO_FN(LCD2D0),
1772 3056
1773 GPIO_FN(VIO_HD), \ 3057 GPIO_FN(VIO_HD), \
1774 GPIO_FN(PORT129_LCD2HSYN), \
1775 GPIO_FN(PORT129_LCD2CS_), \
1776 GPIO_FN(VIO2_HD), \ 3058 GPIO_FN(VIO2_HD), \
1777 GPIO_FN(LCD2D1),
1778 GPIO_FN(VIO_D0), \ 3059 GPIO_FN(VIO_D0), \
1779 GPIO_FN(PORT130_MSIOF2_RXD), \ 3060 GPIO_FN(PORT130_MSIOF2_RXD), \
1780 GPIO_FN(LCD2D10),
1781 GPIO_FN(VIO_D1), \ 3061 GPIO_FN(VIO_D1), \
1782 GPIO_FN(PORT131_KEYOUT6), \
1783 GPIO_FN(PORT131_MSIOF2_SS1), \ 3062 GPIO_FN(PORT131_MSIOF2_SS1), \
1784 GPIO_FN(PORT131_KEYOUT11), \
1785 GPIO_FN(LCD2D11),
1786 GPIO_FN(VIO_D2), \ 3063 GPIO_FN(VIO_D2), \
1787 GPIO_FN(PORT132_KEYOUT7), \
1788 GPIO_FN(PORT132_MSIOF2_SS2), \ 3064 GPIO_FN(PORT132_MSIOF2_SS2), \
1789 GPIO_FN(PORT132_KEYOUT10), \
1790 GPIO_FN(LCD2D12),
1791 GPIO_FN(VIO_D3), \ 3065 GPIO_FN(VIO_D3), \
1792 GPIO_FN(MSIOF2_TSYNC), \ 3066 GPIO_FN(MSIOF2_TSYNC), \
1793 GPIO_FN(LCD2D13),
1794 GPIO_FN(VIO_D4), \ 3067 GPIO_FN(VIO_D4), \
1795 GPIO_FN(MSIOF2_TXD), \ 3068 GPIO_FN(MSIOF2_TXD), \
1796 GPIO_FN(LCD2D14),
1797 GPIO_FN(VIO_D5), \ 3069 GPIO_FN(VIO_D5), \
1798 GPIO_FN(MSIOF2_TSCK), \ 3070 GPIO_FN(MSIOF2_TSCK), \
1799 GPIO_FN(LCD2D15),
1800 GPIO_FN(VIO_D6), \ 3071 GPIO_FN(VIO_D6), \
1801 GPIO_FN(PORT136_KEYOUT8), \
1802 GPIO_FN(LCD2D16),
1803 GPIO_FN(VIO_D7), \ 3072 GPIO_FN(VIO_D7), \
1804 GPIO_FN(PORT137_KEYOUT9), \
1805 GPIO_FN(LCD2D17),
1806 GPIO_FN(VIO_D8), \ 3073 GPIO_FN(VIO_D8), \
1807 GPIO_FN(PORT138_KEYOUT8), \
1808 GPIO_FN(VIO2_D0), \ 3074 GPIO_FN(VIO2_D0), \
1809 GPIO_FN(LCD2D6),
1810 GPIO_FN(VIO_D9), \ 3075 GPIO_FN(VIO_D9), \
1811 GPIO_FN(PORT139_KEYOUT9), \
1812 GPIO_FN(VIO2_D1), \ 3076 GPIO_FN(VIO2_D1), \
1813 GPIO_FN(LCD2D7),
1814 GPIO_FN(VIO_D10), \ 3077 GPIO_FN(VIO_D10), \
1815 GPIO_FN(TPU0TO2), \ 3078 GPIO_FN(TPU0TO2), \
1816 GPIO_FN(VIO2_D2), \ 3079 GPIO_FN(VIO2_D2), \
1817 GPIO_FN(LCD2D8),
1818 GPIO_FN(VIO_D11), \ 3080 GPIO_FN(VIO_D11), \
1819 GPIO_FN(TPU0TO3), \ 3081 GPIO_FN(TPU0TO3), \
1820 GPIO_FN(VIO2_D3), \ 3082 GPIO_FN(VIO2_D3), \
1821 GPIO_FN(LCD2D9),
1822 GPIO_FN(VIO_D12), \ 3083 GPIO_FN(VIO_D12), \
1823 GPIO_FN(PORT142_KEYOUT10), \
1824 GPIO_FN(VIO2_D4), \ 3084 GPIO_FN(VIO2_D4), \
1825 GPIO_FN(LCD2D2),
1826 GPIO_FN(VIO_D13), \ 3085 GPIO_FN(VIO_D13), \
1827 GPIO_FN(PORT143_KEYOUT11), \
1828 GPIO_FN(PORT143_KEYOUT6), \
1829 GPIO_FN(VIO2_D5), \ 3086 GPIO_FN(VIO2_D5), \
1830 GPIO_FN(LCD2D3),
1831 GPIO_FN(VIO_D14), \ 3087 GPIO_FN(VIO_D14), \
1832 GPIO_FN(PORT144_KEYOUT7), \
1833 GPIO_FN(VIO2_D6), \ 3088 GPIO_FN(VIO2_D6), \
1834 GPIO_FN(LCD2D4),
1835 GPIO_FN(VIO_D15), \ 3089 GPIO_FN(VIO_D15), \
1836 GPIO_FN(TPU1TO3), \ 3090 GPIO_FN(TPU1TO3), \
1837 GPIO_FN(PORT145_LCD2DISP), \
1838 GPIO_FN(PORT145_LCD2RS), \
1839 GPIO_FN(VIO2_D7), \ 3091 GPIO_FN(VIO2_D7), \
1840 GPIO_FN(LCD2D5),
1841 GPIO_FN(VIO_CLK), \ 3092 GPIO_FN(VIO_CLK), \
1842 GPIO_FN(LCD2DCK), \
1843 GPIO_FN(PORT146_LCD2WR_), \
1844 GPIO_FN(VIO2_CLK), \ 3093 GPIO_FN(VIO2_CLK), \
1845 GPIO_FN(LCD2D18),
1846 GPIO_FN(VIO_FIELD), \ 3094 GPIO_FN(VIO_FIELD), \
1847 GPIO_FN(LCD2RD_), \
1848 GPIO_FN(VIO2_FIELD), \ 3095 GPIO_FN(VIO2_FIELD), \
1849 GPIO_FN(LCD2D19),
1850 GPIO_FN(VIO_CKO), 3096 GPIO_FN(VIO_CKO),
1851 GPIO_FN(A27), \ 3097 GPIO_FN(A27), \
1852 GPIO_FN(PORT149_RDWR), \
1853 GPIO_FN(MFG0_IN1), \ 3098 GPIO_FN(MFG0_IN1), \
1854 GPIO_FN(PORT149_KEYOUT9),
1855 GPIO_FN(MFG0_IN2), 3099 GPIO_FN(MFG0_IN2),
1856 GPIO_FN(TS_SPSYNC3), \ 3100 GPIO_FN(TS_SPSYNC3), \
1857 GPIO_FN(MSIOF2_RSCK), 3101 GPIO_FN(MSIOF2_RSCK),
@@ -1860,201 +3104,105 @@ static struct pinmux_gpio pinmux_gpios[] = {
1860 GPIO_FN(TPU1TO2), \ 3104 GPIO_FN(TPU1TO2), \
1861 GPIO_FN(TS_SDEN3), \ 3105 GPIO_FN(TS_SDEN3), \
1862 GPIO_FN(PORT153_MSIOF2_SS1), 3106 GPIO_FN(PORT153_MSIOF2_SS1),
1863 GPIO_FN(SCIFA2_TXD1), \
1864 GPIO_FN(MSIOF2_MCK0), 3107 GPIO_FN(MSIOF2_MCK0),
1865 GPIO_FN(SCIFA2_RXD1), \
1866 GPIO_FN(MSIOF2_MCK1), 3108 GPIO_FN(MSIOF2_MCK1),
1867 GPIO_FN(SCIFA2_RTS1_), \
1868 GPIO_FN(PORT156_MSIOF2_SS2), 3109 GPIO_FN(PORT156_MSIOF2_SS2),
1869 GPIO_FN(SCIFA2_CTS1_), \
1870 GPIO_FN(PORT157_MSIOF2_RXD), 3110 GPIO_FN(PORT157_MSIOF2_RXD),
1871 GPIO_FN(DINT_), \ 3111 GPIO_FN(DINT_), \
1872 GPIO_FN(SCIFA2_SCK1), \
1873 GPIO_FN(TS_SCK3), 3112 GPIO_FN(TS_SCK3),
1874 GPIO_FN(PORT159_SCIFB_SCK), \
1875 GPIO_FN(PORT159_SCIFA5_SCK), \
1876 GPIO_FN(NMI), 3113 GPIO_FN(NMI),
1877 GPIO_FN(PORT160_SCIFB_TXD), \
1878 GPIO_FN(PORT160_SCIFA5_TXD),
1879 GPIO_FN(PORT161_SCIFB_CTS_), \
1880 GPIO_FN(PORT161_SCIFA5_CTS_),
1881 GPIO_FN(PORT162_SCIFB_RXD), \
1882 GPIO_FN(PORT162_SCIFA5_RXD),
1883 GPIO_FN(PORT163_SCIFB_RTS_), \
1884 GPIO_FN(PORT163_SCIFA5_RTS_), \
1885 GPIO_FN(TPU3TO0), 3114 GPIO_FN(TPU3TO0),
1886 GPIO_FN(LCDD0),
1887 GPIO_FN(LCDD1), \
1888 GPIO_FN(PORT193_SCIFA5_CTS_), \
1889 GPIO_FN(BBIF2_TSYNC1), 3115 GPIO_FN(BBIF2_TSYNC1),
1890 GPIO_FN(LCDD2), \
1891 GPIO_FN(PORT194_SCIFA5_RTS_), \
1892 GPIO_FN(BBIF2_TSCK1), 3116 GPIO_FN(BBIF2_TSCK1),
1893 GPIO_FN(LCDD3), \
1894 GPIO_FN(PORT195_SCIFA5_RXD), \
1895 GPIO_FN(BBIF2_TXD1), 3117 GPIO_FN(BBIF2_TXD1),
1896 GPIO_FN(LCDD4), \
1897 GPIO_FN(PORT196_SCIFA5_TXD),
1898 GPIO_FN(LCDD5), \
1899 GPIO_FN(PORT197_SCIFA5_SCK), \
1900 GPIO_FN(MFG2_OUT2), \ 3118 GPIO_FN(MFG2_OUT2), \
1901 GPIO_FN(TPU2TO1), 3119 GPIO_FN(TPU2TO1),
1902 GPIO_FN(LCDD6),
1903 GPIO_FN(LCDD7), \
1904 GPIO_FN(TPU4TO1), \ 3120 GPIO_FN(TPU4TO1), \
1905 GPIO_FN(MFG4_OUT2), 3121 GPIO_FN(MFG4_OUT2),
1906 GPIO_FN(LCDD8), \
1907 GPIO_FN(D16), 3122 GPIO_FN(D16),
1908 GPIO_FN(LCDD9), \
1909 GPIO_FN(D17), 3123 GPIO_FN(D17),
1910 GPIO_FN(LCDD10), \
1911 GPIO_FN(D18), 3124 GPIO_FN(D18),
1912 GPIO_FN(LCDD11), \
1913 GPIO_FN(D19), 3125 GPIO_FN(D19),
1914 GPIO_FN(LCDD12), \
1915 GPIO_FN(D20), 3126 GPIO_FN(D20),
1916 GPIO_FN(LCDD13), \
1917 GPIO_FN(D21), 3127 GPIO_FN(D21),
1918 GPIO_FN(LCDD14), \
1919 GPIO_FN(D22), 3128 GPIO_FN(D22),
1920 GPIO_FN(LCDD15), \
1921 GPIO_FN(PORT207_MSIOF0L_SS1), \ 3129 GPIO_FN(PORT207_MSIOF0L_SS1), \
1922 GPIO_FN(D23), 3130 GPIO_FN(D23),
1923 GPIO_FN(LCDD16), \
1924 GPIO_FN(PORT208_MSIOF0L_SS2), \ 3131 GPIO_FN(PORT208_MSIOF0L_SS2), \
1925 GPIO_FN(D24), 3132 GPIO_FN(D24),
1926 GPIO_FN(LCDD17), \
1927 GPIO_FN(D25), 3133 GPIO_FN(D25),
1928 GPIO_FN(LCDD18), \
1929 GPIO_FN(DREQ2), \ 3134 GPIO_FN(DREQ2), \
1930 GPIO_FN(PORT210_MSIOF0L_SS1), \ 3135 GPIO_FN(PORT210_MSIOF0L_SS1), \
1931 GPIO_FN(D26), 3136 GPIO_FN(D26),
1932 GPIO_FN(LCDD19), \
1933 GPIO_FN(PORT211_MSIOF0L_SS2), \ 3137 GPIO_FN(PORT211_MSIOF0L_SS2), \
1934 GPIO_FN(D27), 3138 GPIO_FN(D27),
1935 GPIO_FN(LCDD20), \
1936 GPIO_FN(TS_SPSYNC1), \ 3139 GPIO_FN(TS_SPSYNC1), \
1937 GPIO_FN(MSIOF0L_MCK0), \ 3140 GPIO_FN(MSIOF0L_MCK0), \
1938 GPIO_FN(D28), 3141 GPIO_FN(D28),
1939 GPIO_FN(LCDD21), \
1940 GPIO_FN(TS_SDAT1), \ 3142 GPIO_FN(TS_SDAT1), \
1941 GPIO_FN(MSIOF0L_MCK1), \ 3143 GPIO_FN(MSIOF0L_MCK1), \
1942 GPIO_FN(D29), 3144 GPIO_FN(D29),
1943 GPIO_FN(LCDD22), \
1944 GPIO_FN(TS_SDEN1), \ 3145 GPIO_FN(TS_SDEN1), \
1945 GPIO_FN(MSIOF0L_RSCK), \ 3146 GPIO_FN(MSIOF0L_RSCK), \
1946 GPIO_FN(D30), 3147 GPIO_FN(D30),
1947 GPIO_FN(LCDD23), \
1948 GPIO_FN(TS_SCK1), \ 3148 GPIO_FN(TS_SCK1), \
1949 GPIO_FN(MSIOF0L_RSYNC), \ 3149 GPIO_FN(MSIOF0L_RSYNC), \
1950 GPIO_FN(D31), 3150 GPIO_FN(D31),
1951 GPIO_FN(LCDDCK), \
1952 GPIO_FN(LCDWR_),
1953 GPIO_FN(LCDRD_), \
1954 GPIO_FN(DACK2), \ 3151 GPIO_FN(DACK2), \
1955 GPIO_FN(PORT217_LCD2RS), \
1956 GPIO_FN(MSIOF0L_TSYNC), \ 3152 GPIO_FN(MSIOF0L_TSYNC), \
1957 GPIO_FN(VIO2_FIELD3), \ 3153 GPIO_FN(VIO2_FIELD3), \
1958 GPIO_FN(PORT217_LCD2DISP),
1959 GPIO_FN(LCDHSYN), \
1960 GPIO_FN(LCDCS_), \
1961 GPIO_FN(LCDCS2_), \
1962 GPIO_FN(DACK3), \ 3154 GPIO_FN(DACK3), \
1963 GPIO_FN(PORT218_VIO_CKOR), 3155 GPIO_FN(PORT218_VIO_CKOR),
1964 GPIO_FN(LCDDISP), \
1965 GPIO_FN(LCDRS), \
1966 GPIO_FN(PORT219_LCD2WR_), \
1967 GPIO_FN(DREQ3), \ 3156 GPIO_FN(DREQ3), \
1968 GPIO_FN(MSIOF0L_TSCK), \ 3157 GPIO_FN(MSIOF0L_TSCK), \
1969 GPIO_FN(VIO2_CLK3), \ 3158 GPIO_FN(VIO2_CLK3), \
1970 GPIO_FN(LCD2DCK_2),
1971 GPIO_FN(LCDVSYN), \
1972 GPIO_FN(LCDVSYN2),
1973 GPIO_FN(LCDLCLK), \
1974 GPIO_FN(DREQ1), \ 3159 GPIO_FN(DREQ1), \
1975 GPIO_FN(PORT221_LCD2CS_), \
1976 GPIO_FN(PWEN), \ 3160 GPIO_FN(PWEN), \
1977 GPIO_FN(MSIOF0L_RXD), \ 3161 GPIO_FN(MSIOF0L_RXD), \
1978 GPIO_FN(VIO2_HD3), \ 3162 GPIO_FN(VIO2_HD3), \
1979 GPIO_FN(PORT221_LCD2HSYN),
1980 GPIO_FN(LCDDON), \
1981 GPIO_FN(LCDDON2), \
1982 GPIO_FN(DACK1), \ 3163 GPIO_FN(DACK1), \
1983 GPIO_FN(OVCN), \ 3164 GPIO_FN(OVCN), \
1984 GPIO_FN(MSIOF0L_TXD), \ 3165 GPIO_FN(MSIOF0L_TXD), \
1985 GPIO_FN(VIO2_VD3), \ 3166 GPIO_FN(VIO2_VD3), \
1986 GPIO_FN(PORT222_LCD2VSYN),
1987 3167
1988 GPIO_FN(SCIFA1_TXD), \
1989 GPIO_FN(OVCN2), 3168 GPIO_FN(OVCN2),
1990 GPIO_FN(EXTLP), \ 3169 GPIO_FN(EXTLP), \
1991 GPIO_FN(SCIFA1_SCK), \
1992 GPIO_FN(PORT226_VIO_CKO2), 3170 GPIO_FN(PORT226_VIO_CKO2),
1993 GPIO_FN(SCIFA1_RTS_), \
1994 GPIO_FN(IDIN), 3171 GPIO_FN(IDIN),
1995 GPIO_FN(SCIFA1_RXD),
1996 GPIO_FN(SCIFA1_CTS_), \
1997 GPIO_FN(MFG1_IN1), 3172 GPIO_FN(MFG1_IN1),
1998 GPIO_FN(MSIOF1_TXD), \ 3173 GPIO_FN(MSIOF1_TXD), \
1999 GPIO_FN(SCIFA2_TXD2),
2000 GPIO_FN(MSIOF1_TSYNC), \ 3174 GPIO_FN(MSIOF1_TSYNC), \
2001 GPIO_FN(SCIFA2_CTS2_),
2002 GPIO_FN(MSIOF1_TSCK), \ 3175 GPIO_FN(MSIOF1_TSCK), \
2003 GPIO_FN(SCIFA2_SCK2),
2004 GPIO_FN(MSIOF1_RXD), \ 3176 GPIO_FN(MSIOF1_RXD), \
2005 GPIO_FN(SCIFA2_RXD2),
2006 GPIO_FN(MSIOF1_RSCK), \ 3177 GPIO_FN(MSIOF1_RSCK), \
2007 GPIO_FN(SCIFA2_RTS2_), \
2008 GPIO_FN(VIO2_CLK2), \ 3178 GPIO_FN(VIO2_CLK2), \
2009 GPIO_FN(LCD2D20),
2010 GPIO_FN(MSIOF1_RSYNC), \ 3179 GPIO_FN(MSIOF1_RSYNC), \
2011 GPIO_FN(MFG1_IN2), \ 3180 GPIO_FN(MFG1_IN2), \
2012 GPIO_FN(VIO2_VD2), \ 3181 GPIO_FN(VIO2_VD2), \
2013 GPIO_FN(LCD2D21),
2014 GPIO_FN(MSIOF1_MCK0), \ 3182 GPIO_FN(MSIOF1_MCK0), \
2015 GPIO_FN(PORT236_I2C_SDA2),
2016 GPIO_FN(MSIOF1_MCK1), \ 3183 GPIO_FN(MSIOF1_MCK1), \
2017 GPIO_FN(PORT237_I2C_SCL2),
2018 GPIO_FN(MSIOF1_SS1), \ 3184 GPIO_FN(MSIOF1_SS1), \
2019 GPIO_FN(VIO2_FIELD2), \ 3185 GPIO_FN(VIO2_FIELD2), \
2020 GPIO_FN(LCD2D22),
2021 GPIO_FN(MSIOF1_SS2), \ 3186 GPIO_FN(MSIOF1_SS2), \
2022 GPIO_FN(VIO2_HD2), \ 3187 GPIO_FN(VIO2_HD2), \
2023 GPIO_FN(LCD2D23),
2024 GPIO_FN(SCIFA6_TXD),
2025 GPIO_FN(PORT241_IRDA_OUT), \
2026 GPIO_FN(PORT241_IROUT), \ 3188 GPIO_FN(PORT241_IROUT), \
2027 GPIO_FN(MFG4_OUT1), \ 3189 GPIO_FN(MFG4_OUT1), \
2028 GPIO_FN(TPU4TO0), 3190 GPIO_FN(TPU4TO0),
2029 GPIO_FN(PORT242_IRDA_IN), \
2030 GPIO_FN(MFG4_IN2), 3191 GPIO_FN(MFG4_IN2),
2031 GPIO_FN(PORT243_IRDA_FIRSEL), \
2032 GPIO_FN(PORT243_VIO_CKO2), 3192 GPIO_FN(PORT243_VIO_CKO2),
2033 GPIO_FN(PORT244_SCIFA5_CTS_), \
2034 GPIO_FN(MFG2_IN1), \ 3193 GPIO_FN(MFG2_IN1), \
2035 GPIO_FN(PORT244_SCIFB_CTS_), \
2036 GPIO_FN(MSIOF2R_RXD), 3194 GPIO_FN(MSIOF2R_RXD),
2037 GPIO_FN(PORT245_SCIFA5_RTS_), \
2038 GPIO_FN(MFG2_IN2), \ 3195 GPIO_FN(MFG2_IN2), \
2039 GPIO_FN(PORT245_SCIFB_RTS_), \
2040 GPIO_FN(MSIOF2R_TXD), 3196 GPIO_FN(MSIOF2R_TXD),
2041 GPIO_FN(PORT246_SCIFA5_RXD), \
2042 GPIO_FN(MFG1_OUT1), \ 3197 GPIO_FN(MFG1_OUT1), \
2043 GPIO_FN(PORT246_SCIFB_RXD), \
2044 GPIO_FN(TPU1TO0), 3198 GPIO_FN(TPU1TO0),
2045 GPIO_FN(PORT247_SCIFA5_TXD), \
2046 GPIO_FN(MFG3_OUT2), \ 3199 GPIO_FN(MFG3_OUT2), \
2047 GPIO_FN(PORT247_SCIFB_TXD), \
2048 GPIO_FN(TPU3TO1), 3200 GPIO_FN(TPU3TO1),
2049 GPIO_FN(PORT248_SCIFA5_SCK), \
2050 GPIO_FN(MFG2_OUT1), \ 3201 GPIO_FN(MFG2_OUT1), \
2051 GPIO_FN(PORT248_SCIFB_SCK), \
2052 GPIO_FN(TPU2TO0), \ 3202 GPIO_FN(TPU2TO0), \
2053 GPIO_FN(PORT248_I2C_SCL3), \
2054 GPIO_FN(MSIOF2R_TSCK), 3203 GPIO_FN(MSIOF2R_TSCK),
2055 GPIO_FN(PORT249_IROUT), \ 3204 GPIO_FN(PORT249_IROUT), \
2056 GPIO_FN(MFG4_IN1), \ 3205 GPIO_FN(MFG4_IN1), \
2057 GPIO_FN(PORT249_I2C_SDA3), \
2058 GPIO_FN(MSIOF2R_TSYNC), 3206 GPIO_FN(MSIOF2R_TSYNC),
2059 GPIO_FN(SDHICLK0), 3207 GPIO_FN(SDHICLK0),
2060 GPIO_FN(SDHICD0), 3208 GPIO_FN(SDHICD0),
@@ -2172,56 +3320,24 @@ static struct pinmux_gpio pinmux_gpios[] = {
2172 GPIO_FN(IRQ9_MEM_INT), 3320 GPIO_FN(IRQ9_MEM_INT),
2173 GPIO_FN(IRQ9_MCP_INT), 3321 GPIO_FN(IRQ9_MCP_INT),
2174 GPIO_FN(A11), 3322 GPIO_FN(A11),
2175 GPIO_FN(KEYOUT8),
2176 GPIO_FN(TPU4TO3), 3323 GPIO_FN(TPU4TO3),
2177 GPIO_FN(RESETA_N_PU_ON), 3324 GPIO_FN(RESETA_N_PU_ON),
2178 GPIO_FN(RESETA_N_PU_OFF), 3325 GPIO_FN(RESETA_N_PU_OFF),
2179 GPIO_FN(EDBGREQ_PD), 3326 GPIO_FN(EDBGREQ_PD),
2180 GPIO_FN(EDBGREQ_PU), 3327 GPIO_FN(EDBGREQ_PU),
3328};
2181 3329
2182 /* Functions with pull-ups */ 3330#undef PORTCR
2183 GPIO_FN(KEYIN0_PU), 3331#define PORTCR(nr, reg) \
2184 GPIO_FN(KEYIN1_PU), 3332 { \
2185 GPIO_FN(KEYIN2_PU), 3333 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
2186 GPIO_FN(KEYIN3_PU), 3334 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
2187 GPIO_FN(KEYIN4_PU), 3335 PORT##nr##_FN0, PORT##nr##_FN1, \
2188 GPIO_FN(KEYIN5_PU), 3336 PORT##nr##_FN2, PORT##nr##_FN3, \
2189 GPIO_FN(KEYIN6_PU), 3337 PORT##nr##_FN4, PORT##nr##_FN5, \
2190 GPIO_FN(KEYIN7_PU), 3338 PORT##nr##_FN6, PORT##nr##_FN7 } \
2191 GPIO_FN(SDHICD0_PU), 3339 }
2192 GPIO_FN(SDHID0_0_PU), 3340static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2193 GPIO_FN(SDHID0_1_PU),
2194 GPIO_FN(SDHID0_2_PU),
2195 GPIO_FN(SDHID0_3_PU),
2196 GPIO_FN(SDHICMD0_PU),
2197 GPIO_FN(SDHIWP0_PU),
2198 GPIO_FN(SDHID1_0_PU),
2199 GPIO_FN(SDHID1_1_PU),
2200 GPIO_FN(SDHID1_2_PU),
2201 GPIO_FN(SDHID1_3_PU),
2202 GPIO_FN(SDHICMD1_PU),
2203 GPIO_FN(SDHID2_0_PU),
2204 GPIO_FN(SDHID2_1_PU),
2205 GPIO_FN(SDHID2_2_PU),
2206 GPIO_FN(SDHID2_3_PU),
2207 GPIO_FN(SDHICMD2_PU),
2208 GPIO_FN(MMCCMD0_PU),
2209 GPIO_FN(MMCCMD1_PU),
2210 GPIO_FN(MMCD0_0_PU),
2211 GPIO_FN(MMCD0_1_PU),
2212 GPIO_FN(MMCD0_2_PU),
2213 GPIO_FN(MMCD0_3_PU),
2214 GPIO_FN(MMCD0_4_PU),
2215 GPIO_FN(MMCD0_5_PU),
2216 GPIO_FN(MMCD0_6_PU),
2217 GPIO_FN(MMCD0_7_PU),
2218 GPIO_FN(FSIACK_PU),
2219 GPIO_FN(FSIAILR_PU),
2220 GPIO_FN(FSIAIBT_PU),
2221 GPIO_FN(FSIAISLD_PU),
2222};
2223
2224static struct pinmux_cfg_reg pinmux_config_regs[] = {
2225 PORTCR(0, 0xe6050000), /* PORT0CR */ 3341 PORTCR(0, 0xe6050000), /* PORT0CR */
2226 PORTCR(1, 0xe6050001), /* PORT1CR */ 3342 PORTCR(1, 0xe6050001), /* PORT1CR */
2227 PORTCR(2, 0xe6050002), /* PORT2CR */ 3343 PORTCR(2, 0xe6050002), /* PORT2CR */
@@ -2629,7 +3745,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2629 { }, 3745 { },
2630}; 3746};
2631 3747
2632static struct pinmux_data_reg pinmux_data_regs[] = { 3748static const struct pinmux_data_reg pinmux_data_regs[] = {
2633 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) { 3749 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
2634 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA, 3750 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2635 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA, 3751 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
@@ -2737,56 +3853,112 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2737#define EXT_IRQ16L(n) irq_pin(n) 3853#define EXT_IRQ16L(n) irq_pin(n)
2738#define EXT_IRQ16H(n) irq_pin(n) 3854#define EXT_IRQ16H(n) irq_pin(n)
2739 3855
2740static struct pinmux_irq pinmux_irqs[] = { 3856static const struct pinmux_irq pinmux_irqs[] = {
2741 PINMUX_IRQ(EXT_IRQ16H(19), PORT9_FN0), 3857 PINMUX_IRQ(EXT_IRQ16H(19), 9),
2742 PINMUX_IRQ(EXT_IRQ16L(1), PORT10_FN0), 3858 PINMUX_IRQ(EXT_IRQ16L(1), 10),
2743 PINMUX_IRQ(EXT_IRQ16L(0), PORT11_FN0), 3859 PINMUX_IRQ(EXT_IRQ16L(0), 11),
2744 PINMUX_IRQ(EXT_IRQ16H(18), PORT13_FN0), 3860 PINMUX_IRQ(EXT_IRQ16H(18), 13),
2745 PINMUX_IRQ(EXT_IRQ16H(20), PORT14_FN0), 3861 PINMUX_IRQ(EXT_IRQ16H(20), 14),
2746 PINMUX_IRQ(EXT_IRQ16H(21), PORT15_FN0), 3862 PINMUX_IRQ(EXT_IRQ16H(21), 15),
2747 PINMUX_IRQ(EXT_IRQ16H(31), PORT26_FN0), 3863 PINMUX_IRQ(EXT_IRQ16H(31), 26),
2748 PINMUX_IRQ(EXT_IRQ16H(30), PORT27_FN0), 3864 PINMUX_IRQ(EXT_IRQ16H(30), 27),
2749 PINMUX_IRQ(EXT_IRQ16H(29), PORT28_FN0), 3865 PINMUX_IRQ(EXT_IRQ16H(29), 28),
2750 PINMUX_IRQ(EXT_IRQ16H(22), PORT40_FN0), 3866 PINMUX_IRQ(EXT_IRQ16H(22), 40),
2751 PINMUX_IRQ(EXT_IRQ16H(23), PORT53_FN0), 3867 PINMUX_IRQ(EXT_IRQ16H(23), 53),
2752 PINMUX_IRQ(EXT_IRQ16L(10), PORT54_FN0), 3868 PINMUX_IRQ(EXT_IRQ16L(10), 54),
2753 PINMUX_IRQ(EXT_IRQ16L(9), PORT56_FN0), 3869 PINMUX_IRQ(EXT_IRQ16L(9), 56),
2754 PINMUX_IRQ(EXT_IRQ16H(26), PORT115_FN0), 3870 PINMUX_IRQ(EXT_IRQ16H(26), 115),
2755 PINMUX_IRQ(EXT_IRQ16H(27), PORT116_FN0), 3871 PINMUX_IRQ(EXT_IRQ16H(27), 116),
2756 PINMUX_IRQ(EXT_IRQ16H(28), PORT117_FN0), 3872 PINMUX_IRQ(EXT_IRQ16H(28), 117),
2757 PINMUX_IRQ(EXT_IRQ16H(24), PORT118_FN0), 3873 PINMUX_IRQ(EXT_IRQ16H(24), 118),
2758 PINMUX_IRQ(EXT_IRQ16L(6), PORT147_FN0), 3874 PINMUX_IRQ(EXT_IRQ16L(6), 147),
2759 PINMUX_IRQ(EXT_IRQ16L(2), PORT149_FN0), 3875 PINMUX_IRQ(EXT_IRQ16L(2), 149),
2760 PINMUX_IRQ(EXT_IRQ16L(7), PORT150_FN0), 3876 PINMUX_IRQ(EXT_IRQ16L(7), 150),
2761 PINMUX_IRQ(EXT_IRQ16L(12), PORT156_FN0), 3877 PINMUX_IRQ(EXT_IRQ16L(12), 156),
2762 PINMUX_IRQ(EXT_IRQ16L(4), PORT159_FN0), 3878 PINMUX_IRQ(EXT_IRQ16L(4), 159),
2763 PINMUX_IRQ(EXT_IRQ16H(25), PORT164_FN0), 3879 PINMUX_IRQ(EXT_IRQ16H(25), 164),
2764 PINMUX_IRQ(EXT_IRQ16L(8), PORT223_FN0), 3880 PINMUX_IRQ(EXT_IRQ16L(8), 223),
2765 PINMUX_IRQ(EXT_IRQ16L(3), PORT224_FN0), 3881 PINMUX_IRQ(EXT_IRQ16L(3), 224),
2766 PINMUX_IRQ(EXT_IRQ16L(5), PORT227_FN0), 3882 PINMUX_IRQ(EXT_IRQ16L(5), 227),
2767 PINMUX_IRQ(EXT_IRQ16H(17), PORT234_FN0), 3883 PINMUX_IRQ(EXT_IRQ16H(17), 234),
2768 PINMUX_IRQ(EXT_IRQ16L(11), PORT238_FN0), 3884 PINMUX_IRQ(EXT_IRQ16L(11), 238),
2769 PINMUX_IRQ(EXT_IRQ16L(13), PORT239_FN0), 3885 PINMUX_IRQ(EXT_IRQ16L(13), 239),
2770 PINMUX_IRQ(EXT_IRQ16H(16), PORT249_FN0), 3886 PINMUX_IRQ(EXT_IRQ16H(16), 249),
2771 PINMUX_IRQ(EXT_IRQ16L(14), PORT251_FN0), 3887 PINMUX_IRQ(EXT_IRQ16L(14), 251),
2772 PINMUX_IRQ(EXT_IRQ16L(9), PORT308_FN0), 3888 PINMUX_IRQ(EXT_IRQ16L(9), 308),
2773}; 3889};
2774 3890
2775struct sh_pfc_soc_info sh73a0_pinmux_info = { 3891#define PORTnCR_PULMD_OFF (0 << 6)
3892#define PORTnCR_PULMD_DOWN (2 << 6)
3893#define PORTnCR_PULMD_UP (3 << 6)
3894#define PORTnCR_PULMD_MASK (3 << 6)
3895
3896static const unsigned int sh73a0_portcr_offsets[] = {
3897 0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
3898 0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
3899};
3900
3901static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3902{
3903 void __iomem *addr = pfc->window->virt
3904 + sh73a0_portcr_offsets[pin >> 5] + pin;
3905 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
3906
3907 switch (value) {
3908 case PORTnCR_PULMD_UP:
3909 return PIN_CONFIG_BIAS_PULL_UP;
3910 case PORTnCR_PULMD_DOWN:
3911 return PIN_CONFIG_BIAS_PULL_DOWN;
3912 case PORTnCR_PULMD_OFF:
3913 default:
3914 return PIN_CONFIG_BIAS_DISABLE;
3915 }
3916}
3917
3918static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3919 unsigned int bias)
3920{
3921 void __iomem *addr = pfc->window->virt
3922 + sh73a0_portcr_offsets[pin >> 5] + pin;
3923 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
3924
3925 switch (bias) {
3926 case PIN_CONFIG_BIAS_PULL_UP:
3927 value |= PORTnCR_PULMD_UP;
3928 break;
3929 case PIN_CONFIG_BIAS_PULL_DOWN:
3930 value |= PORTnCR_PULMD_DOWN;
3931 break;
3932 }
3933
3934 iowrite8(value, addr);
3935}
3936
3937static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
3938 .get_bias = sh73a0_pinmux_get_bias,
3939 .set_bias = sh73a0_pinmux_set_bias,
3940};
3941
3942const struct sh_pfc_soc_info sh73a0_pinmux_info = {
2776 .name = "sh73a0_pfc", 3943 .name = "sh73a0_pfc",
2777 .reserved_id = PINMUX_RESERVED, 3944 .ops = &sh73a0_pinmux_ops,
2778 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, 3945
2779 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 3946 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2780 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
2781 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
2782 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 3947 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2783 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2784 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 3948 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2785 3949
2786 .first_gpio = GPIO_PORT0, 3950 .pins = pinmux_pins,
2787 .last_gpio = GPIO_FN_FSIAISLD_PU, 3951 .nr_pins = ARRAY_SIZE(pinmux_pins),
3952 .ranges = pinmux_ranges,
3953 .nr_ranges = ARRAY_SIZE(pinmux_ranges),
3954 .groups = pinmux_groups,
3955 .nr_groups = ARRAY_SIZE(pinmux_groups),
3956 .functions = pinmux_functions,
3957 .nr_functions = ARRAY_SIZE(pinmux_functions),
3958
3959 .func_gpios = pinmux_func_gpios,
3960 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2788 3961
2789 .gpios = pinmux_gpios,
2790 .cfg_regs = pinmux_config_regs, 3962 .cfg_regs = pinmux_config_regs,
2791 .data_regs = pinmux_data_regs, 3963 .data_regs = pinmux_data_regs,
2792 3964
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
index 10872ed688a6..52e9f6be665f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
@@ -262,7 +262,7 @@ enum {
262 PINMUX_MARK_END, 262 PINMUX_MARK_END,
263}; 263};
264 264
265static pinmux_enum_t pinmux_data[] = { 265static const pinmux_enum_t pinmux_data[] = {
266 /* PTA GPIO */ 266 /* PTA GPIO */
267 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU), 267 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
268 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU), 268 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
@@ -606,7 +606,7 @@ static pinmux_enum_t pinmux_data[] = {
606 PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN), 606 PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN),
607}; 607};
608 608
609static struct pinmux_gpio pinmux_gpios[] = { 609static struct sh_pfc_pin pinmux_pins[] = {
610 /* PTA */ 610 /* PTA */
611 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), 611 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
612 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), 612 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -759,202 +759,205 @@ static struct pinmux_gpio pinmux_gpios[] = {
759 PINMUX_GPIO(GPIO_PTV2, PTV2_DATA), 759 PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
760 PINMUX_GPIO(GPIO_PTV1, PTV1_DATA), 760 PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
761 PINMUX_GPIO(GPIO_PTV0, PTV0_DATA), 761 PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
762};
763
764#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
762 765
766static const struct pinmux_func pinmux_func_gpios[] = {
763 /* BSC */ 767 /* BSC */
764 PINMUX_GPIO(GPIO_FN_D31, D31_MARK), 768 GPIO_FN(D31),
765 PINMUX_GPIO(GPIO_FN_D30, D30_MARK), 769 GPIO_FN(D30),
766 PINMUX_GPIO(GPIO_FN_D29, D29_MARK), 770 GPIO_FN(D29),
767 PINMUX_GPIO(GPIO_FN_D28, D28_MARK), 771 GPIO_FN(D28),
768 PINMUX_GPIO(GPIO_FN_D27, D27_MARK), 772 GPIO_FN(D27),
769 PINMUX_GPIO(GPIO_FN_D26, D26_MARK), 773 GPIO_FN(D26),
770 PINMUX_GPIO(GPIO_FN_D25, D25_MARK), 774 GPIO_FN(D25),
771 PINMUX_GPIO(GPIO_FN_D24, D24_MARK), 775 GPIO_FN(D24),
772 PINMUX_GPIO(GPIO_FN_D23, D23_MARK), 776 GPIO_FN(D23),
773 PINMUX_GPIO(GPIO_FN_D22, D22_MARK), 777 GPIO_FN(D22),
774 PINMUX_GPIO(GPIO_FN_D21, D21_MARK), 778 GPIO_FN(D21),
775 PINMUX_GPIO(GPIO_FN_D20, D20_MARK), 779 GPIO_FN(D20),
776 PINMUX_GPIO(GPIO_FN_D19, D19_MARK), 780 GPIO_FN(D19),
777 PINMUX_GPIO(GPIO_FN_D18, D18_MARK), 781 GPIO_FN(D18),
778 PINMUX_GPIO(GPIO_FN_D17, D17_MARK), 782 GPIO_FN(D17),
779 PINMUX_GPIO(GPIO_FN_D16, D16_MARK), 783 GPIO_FN(D16),
780 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 784 GPIO_FN(IOIS16),
781 PINMUX_GPIO(GPIO_FN_RAS, RAS_MARK), 785 GPIO_FN(RAS),
782 PINMUX_GPIO(GPIO_FN_CAS, CAS_MARK), 786 GPIO_FN(CAS),
783 PINMUX_GPIO(GPIO_FN_CKE, CKE_MARK), 787 GPIO_FN(CKE),
784 PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), 788 GPIO_FN(CS5B_CE1A),
785 PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), 789 GPIO_FN(CS6B_CE1B),
786 PINMUX_GPIO(GPIO_FN_A25, A25_MARK), 790 GPIO_FN(A25),
787 PINMUX_GPIO(GPIO_FN_A24, A24_MARK), 791 GPIO_FN(A24),
788 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 792 GPIO_FN(A23),
789 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 793 GPIO_FN(A22),
790 PINMUX_GPIO(GPIO_FN_A21, A21_MARK), 794 GPIO_FN(A21),
791 PINMUX_GPIO(GPIO_FN_A20, A20_MARK), 795 GPIO_FN(A20),
792 PINMUX_GPIO(GPIO_FN_A19, A19_MARK), 796 GPIO_FN(A19),
793 PINMUX_GPIO(GPIO_FN_A0, A0_MARK), 797 GPIO_FN(A0),
794 PINMUX_GPIO(GPIO_FN_REFOUT, REFOUT_MARK), 798 GPIO_FN(REFOUT),
795 PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), 799 GPIO_FN(IRQOUT),
796 800
797 /* LCDC */ 801 /* LCDC */
798 PINMUX_GPIO(GPIO_FN_LCD_DATA15, LCD_DATA15_MARK), 802 GPIO_FN(LCD_DATA15),
799 PINMUX_GPIO(GPIO_FN_LCD_DATA14, LCD_DATA14_MARK), 803 GPIO_FN(LCD_DATA14),
800 PINMUX_GPIO(GPIO_FN_LCD_DATA13, LCD_DATA13_MARK), 804 GPIO_FN(LCD_DATA13),
801 PINMUX_GPIO(GPIO_FN_LCD_DATA12, LCD_DATA12_MARK), 805 GPIO_FN(LCD_DATA12),
802 PINMUX_GPIO(GPIO_FN_LCD_DATA11, LCD_DATA11_MARK), 806 GPIO_FN(LCD_DATA11),
803 PINMUX_GPIO(GPIO_FN_LCD_DATA10, LCD_DATA10_MARK), 807 GPIO_FN(LCD_DATA10),
804 PINMUX_GPIO(GPIO_FN_LCD_DATA9, LCD_DATA9_MARK), 808 GPIO_FN(LCD_DATA9),
805 PINMUX_GPIO(GPIO_FN_LCD_DATA8, LCD_DATA8_MARK), 809 GPIO_FN(LCD_DATA8),
806 PINMUX_GPIO(GPIO_FN_LCD_DATA7, LCD_DATA7_MARK), 810 GPIO_FN(LCD_DATA7),
807 PINMUX_GPIO(GPIO_FN_LCD_DATA6, LCD_DATA6_MARK), 811 GPIO_FN(LCD_DATA6),
808 PINMUX_GPIO(GPIO_FN_LCD_DATA5, LCD_DATA5_MARK), 812 GPIO_FN(LCD_DATA5),
809 PINMUX_GPIO(GPIO_FN_LCD_DATA4, LCD_DATA4_MARK), 813 GPIO_FN(LCD_DATA4),
810 PINMUX_GPIO(GPIO_FN_LCD_DATA3, LCD_DATA3_MARK), 814 GPIO_FN(LCD_DATA3),
811 PINMUX_GPIO(GPIO_FN_LCD_DATA2, LCD_DATA2_MARK), 815 GPIO_FN(LCD_DATA2),
812 PINMUX_GPIO(GPIO_FN_LCD_DATA1, LCD_DATA1_MARK), 816 GPIO_FN(LCD_DATA1),
813 PINMUX_GPIO(GPIO_FN_LCD_DATA0, LCD_DATA0_MARK), 817 GPIO_FN(LCD_DATA0),
814 PINMUX_GPIO(GPIO_FN_LCD_M_DISP, LCD_M_DISP_MARK), 818 GPIO_FN(LCD_M_DISP),
815 PINMUX_GPIO(GPIO_FN_LCD_CL1, LCD_CL1_MARK), 819 GPIO_FN(LCD_CL1),
816 PINMUX_GPIO(GPIO_FN_LCD_CL2, LCD_CL2_MARK), 820 GPIO_FN(LCD_CL2),
817 PINMUX_GPIO(GPIO_FN_LCD_DON, LCD_DON_MARK), 821 GPIO_FN(LCD_DON),
818 PINMUX_GPIO(GPIO_FN_LCD_FLM, LCD_FLM_MARK), 822 GPIO_FN(LCD_FLM),
819 PINMUX_GPIO(GPIO_FN_LCD_VEPWC, LCD_VEPWC_MARK), 823 GPIO_FN(LCD_VEPWC),
820 PINMUX_GPIO(GPIO_FN_LCD_VCPWC, LCD_VCPWC_MARK), 824 GPIO_FN(LCD_VCPWC),
821 825
822 /* AFEIF */ 826 /* AFEIF */
823 PINMUX_GPIO(GPIO_FN_AFE_RXIN, AFE_RXIN_MARK), 827 GPIO_FN(AFE_RXIN),
824 PINMUX_GPIO(GPIO_FN_AFE_RDET, AFE_RDET_MARK), 828 GPIO_FN(AFE_RDET),
825 PINMUX_GPIO(GPIO_FN_AFE_FS, AFE_FS_MARK), 829 GPIO_FN(AFE_FS),
826 PINMUX_GPIO(GPIO_FN_AFE_TXOUT, AFE_TXOUT_MARK), 830 GPIO_FN(AFE_TXOUT),
827 PINMUX_GPIO(GPIO_FN_AFE_SCLK, AFE_SCLK_MARK), 831 GPIO_FN(AFE_SCLK),
828 PINMUX_GPIO(GPIO_FN_AFE_RLYCNT, AFE_RLYCNT_MARK), 832 GPIO_FN(AFE_RLYCNT),
829 PINMUX_GPIO(GPIO_FN_AFE_HC1, AFE_HC1_MARK), 833 GPIO_FN(AFE_HC1),
830 834
831 /* IIC */ 835 /* IIC */
832 PINMUX_GPIO(GPIO_FN_IIC_SCL, IIC_SCL_MARK), 836 GPIO_FN(IIC_SCL),
833 PINMUX_GPIO(GPIO_FN_IIC_SDA, IIC_SDA_MARK), 837 GPIO_FN(IIC_SDA),
834 838
835 /* DAC */ 839 /* DAC */
836 PINMUX_GPIO(GPIO_FN_DA1, DA1_MARK), 840 GPIO_FN(DA1),
837 PINMUX_GPIO(GPIO_FN_DA0, DA0_MARK), 841 GPIO_FN(DA0),
838 842
839 /* ADC */ 843 /* ADC */
840 PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK), 844 GPIO_FN(AN3),
841 PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK), 845 GPIO_FN(AN2),
842 PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK), 846 GPIO_FN(AN1),
843 PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK), 847 GPIO_FN(AN0),
844 PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), 848 GPIO_FN(ADTRG),
845 849
846 /* USB */ 850 /* USB */
847 PINMUX_GPIO(GPIO_FN_USB1D_RCV, USB1D_RCV_MARK), 851 GPIO_FN(USB1D_RCV),
848 PINMUX_GPIO(GPIO_FN_USB1D_TXSE0, USB1D_TXSE0_MARK), 852 GPIO_FN(USB1D_TXSE0),
849 PINMUX_GPIO(GPIO_FN_USB1D_TXDPLS, USB1D_TXDPLS_MARK), 853 GPIO_FN(USB1D_TXDPLS),
850 PINMUX_GPIO(GPIO_FN_USB1D_DMNS, USB1D_DMNS_MARK), 854 GPIO_FN(USB1D_DMNS),
851 PINMUX_GPIO(GPIO_FN_USB1D_DPLS, USB1D_DPLS_MARK), 855 GPIO_FN(USB1D_DPLS),
852 PINMUX_GPIO(GPIO_FN_USB1D_SPEED, USB1D_SPEED_MARK), 856 GPIO_FN(USB1D_SPEED),
853 PINMUX_GPIO(GPIO_FN_USB1D_TXENL, USB1D_TXENL_MARK), 857 GPIO_FN(USB1D_TXENL),
854 858
855 PINMUX_GPIO(GPIO_FN_USB2_PWR_EN, USB2_PWR_EN_MARK), 859 GPIO_FN(USB2_PWR_EN),
856 PINMUX_GPIO(GPIO_FN_USB1_PWR_EN_USBF_UPLUP, 860 GPIO_FN(USB1_PWR_EN_USBF_UPLUP),
857 USB1_PWR_EN_USBF_UPLUP_MARK), 861 GPIO_FN(USB1D_SUSPEND),
858 PINMUX_GPIO(GPIO_FN_USB1D_SUSPEND, USB1D_SUSPEND_MARK),
859 862
860 /* INTC */ 863 /* INTC */
861 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), 864 GPIO_FN(IRQ5),
862 PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), 865 GPIO_FN(IRQ4),
863 PINMUX_GPIO(GPIO_FN_IRQ3_IRL3, IRQ3_IRL3_MARK), 866 GPIO_FN(IRQ3_IRL3),
864 PINMUX_GPIO(GPIO_FN_IRQ2_IRL2, IRQ2_IRL2_MARK), 867 GPIO_FN(IRQ2_IRL2),
865 PINMUX_GPIO(GPIO_FN_IRQ1_IRL1, IRQ1_IRL1_MARK), 868 GPIO_FN(IRQ1_IRL1),
866 PINMUX_GPIO(GPIO_FN_IRQ0_IRL0, IRQ0_IRL0_MARK), 869 GPIO_FN(IRQ0_IRL0),
867 870
868 /* PCC */ 871 /* PCC */
869 PINMUX_GPIO(GPIO_FN_PCC_REG, PCC_REG_MARK), 872 GPIO_FN(PCC_REG),
870 PINMUX_GPIO(GPIO_FN_PCC_DRV, PCC_DRV_MARK), 873 GPIO_FN(PCC_DRV),
871 PINMUX_GPIO(GPIO_FN_PCC_BVD2, PCC_BVD2_MARK), 874 GPIO_FN(PCC_BVD2),
872 PINMUX_GPIO(GPIO_FN_PCC_BVD1, PCC_BVD1_MARK), 875 GPIO_FN(PCC_BVD1),
873 PINMUX_GPIO(GPIO_FN_PCC_CD2, PCC_CD2_MARK), 876 GPIO_FN(PCC_CD2),
874 PINMUX_GPIO(GPIO_FN_PCC_CD1, PCC_CD1_MARK), 877 GPIO_FN(PCC_CD1),
875 PINMUX_GPIO(GPIO_FN_PCC_RESET, PCC_RESET_MARK), 878 GPIO_FN(PCC_RESET),
876 PINMUX_GPIO(GPIO_FN_PCC_RDY, PCC_RDY_MARK), 879 GPIO_FN(PCC_RDY),
877 PINMUX_GPIO(GPIO_FN_PCC_VS2, PCC_VS2_MARK), 880 GPIO_FN(PCC_VS2),
878 PINMUX_GPIO(GPIO_FN_PCC_VS1, PCC_VS1_MARK), 881 GPIO_FN(PCC_VS1),
879 882
880 /* HUDI */ 883 /* HUDI */
881 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), 884 GPIO_FN(AUDATA3),
882 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), 885 GPIO_FN(AUDATA2),
883 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), 886 GPIO_FN(AUDATA1),
884 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), 887 GPIO_FN(AUDATA0),
885 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), 888 GPIO_FN(AUDCK),
886 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), 889 GPIO_FN(AUDSYNC),
887 PINMUX_GPIO(GPIO_FN_ASEBRKAK, ASEBRKAK_MARK), 890 GPIO_FN(ASEBRKAK),
888 PINMUX_GPIO(GPIO_FN_TRST, TRST_MARK), 891 GPIO_FN(TRST),
889 PINMUX_GPIO(GPIO_FN_TMS, TMS_MARK), 892 GPIO_FN(TMS),
890 PINMUX_GPIO(GPIO_FN_TDO, TDO_MARK), 893 GPIO_FN(TDO),
891 PINMUX_GPIO(GPIO_FN_TDI, TDI_MARK), 894 GPIO_FN(TDI),
892 PINMUX_GPIO(GPIO_FN_TCK, TCK_MARK), 895 GPIO_FN(TCK),
893 896
894 /* DMAC */ 897 /* DMAC */
895 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), 898 GPIO_FN(DACK1),
896 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 899 GPIO_FN(DREQ1),
897 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), 900 GPIO_FN(DACK0),
898 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 901 GPIO_FN(DREQ0),
899 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), 902 GPIO_FN(TEND1),
900 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), 903 GPIO_FN(TEND0),
901 904
902 /* SIOF0 */ 905 /* SIOF0 */
903 PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK), 906 GPIO_FN(SIOF0_SYNC),
904 PINMUX_GPIO(GPIO_FN_SIOF0_MCLK, SIOF0_MCLK_MARK), 907 GPIO_FN(SIOF0_MCLK),
905 PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK), 908 GPIO_FN(SIOF0_TXD),
906 PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK), 909 GPIO_FN(SIOF0_RXD),
907 PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK), 910 GPIO_FN(SIOF0_SCK),
908 911
909 /* SIOF1 */ 912 /* SIOF1 */
910 PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK), 913 GPIO_FN(SIOF1_SYNC),
911 PINMUX_GPIO(GPIO_FN_SIOF1_MCLK, SIOF1_MCLK_MARK), 914 GPIO_FN(SIOF1_MCLK),
912 PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK), 915 GPIO_FN(SIOF1_TXD),
913 PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK), 916 GPIO_FN(SIOF1_RXD),
914 PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK), 917 GPIO_FN(SIOF1_SCK),
915 918
916 /* SCIF0 */ 919 /* SCIF0 */
917 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), 920 GPIO_FN(SCIF0_TXD),
918 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), 921 GPIO_FN(SCIF0_RXD),
919 PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), 922 GPIO_FN(SCIF0_RTS),
920 PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), 923 GPIO_FN(SCIF0_CTS),
921 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), 924 GPIO_FN(SCIF0_SCK),
922 925
923 /* SCIF1 */ 926 /* SCIF1 */
924 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), 927 GPIO_FN(SCIF1_TXD),
925 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), 928 GPIO_FN(SCIF1_RXD),
926 PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK), 929 GPIO_FN(SCIF1_RTS),
927 PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK), 930 GPIO_FN(SCIF1_CTS),
928 PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), 931 GPIO_FN(SCIF1_SCK),
929 932
930 /* TPU */ 933 /* TPU */
931 PINMUX_GPIO(GPIO_FN_TPU_TO1, TPU_TO1_MARK), 934 GPIO_FN(TPU_TO1),
932 PINMUX_GPIO(GPIO_FN_TPU_TO0, TPU_TO0_MARK), 935 GPIO_FN(TPU_TO0),
933 PINMUX_GPIO(GPIO_FN_TPU_TI3B, TPU_TI3B_MARK), 936 GPIO_FN(TPU_TI3B),
934 PINMUX_GPIO(GPIO_FN_TPU_TI3A, TPU_TI3A_MARK), 937 GPIO_FN(TPU_TI3A),
935 PINMUX_GPIO(GPIO_FN_TPU_TI2B, TPU_TI2B_MARK), 938 GPIO_FN(TPU_TI2B),
936 PINMUX_GPIO(GPIO_FN_TPU_TI2A, TPU_TI2A_MARK), 939 GPIO_FN(TPU_TI2A),
937 PINMUX_GPIO(GPIO_FN_TPU_TO3, TPU_TO3_MARK), 940 GPIO_FN(TPU_TO3),
938 PINMUX_GPIO(GPIO_FN_TPU_TO2, TPU_TO2_MARK), 941 GPIO_FN(TPU_TO2),
939 942
940 /* SIM */ 943 /* SIM */
941 PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), 944 GPIO_FN(SIM_D),
942 PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), 945 GPIO_FN(SIM_CLK),
943 PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), 946 GPIO_FN(SIM_RST),
944 947
945 /* MMC */ 948 /* MMC */
946 PINMUX_GPIO(GPIO_FN_MMC_DAT, MMC_DAT_MARK), 949 GPIO_FN(MMC_DAT),
947 PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK), 950 GPIO_FN(MMC_CMD),
948 PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK), 951 GPIO_FN(MMC_CLK),
949 PINMUX_GPIO(GPIO_FN_MMC_VDDON, MMC_VDDON_MARK), 952 GPIO_FN(MMC_VDDON),
950 PINMUX_GPIO(GPIO_FN_MMC_ODMOD, MMC_ODMOD_MARK), 953 GPIO_FN(MMC_ODMOD),
951 954
952 /* SYSC */ 955 /* SYSC */
953 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), 956 GPIO_FN(STATUS0),
954 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), 957 GPIO_FN(STATUS1),
955}; 958};
956 959
957static struct pinmux_cfg_reg pinmux_config_regs[] = { 960static const struct pinmux_cfg_reg pinmux_config_regs[] = {
958 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { 961 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
959 PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN, 962 PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
960 PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN, 963 PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
@@ -1138,7 +1141,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1138 {} 1141 {}
1139}; 1142};
1140 1143
1141static struct pinmux_data_reg pinmux_data_regs[] = { 1144static const struct pinmux_data_reg pinmux_data_regs[] = {
1142 { PINMUX_DATA_REG("PADR", 0xa4050140, 8) { 1145 { PINMUX_DATA_REG("PADR", 0xa4050140, 8) {
1143 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, 1146 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
1144 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } 1147 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -1214,20 +1217,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1214 { }, 1217 { },
1215}; 1218};
1216 1219
1217struct sh_pfc_soc_info sh7720_pinmux_info = { 1220const struct sh_pfc_soc_info sh7720_pinmux_info = {
1218 .name = "sh7720_pfc", 1221 .name = "sh7720_pfc",
1219 .reserved_id = PINMUX_RESERVED,
1220 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1221 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 1222 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1222 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 1223 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1223 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 1224 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1224 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1225 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 1225 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1226 1226
1227 .first_gpio = GPIO_PTA7, 1227 .pins = pinmux_pins,
1228 .last_gpio = GPIO_FN_STATUS1, 1228 .nr_pins = ARRAY_SIZE(pinmux_pins),
1229 .func_gpios = pinmux_func_gpios,
1230 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
1229 1231
1230 .gpios = pinmux_gpios,
1231 .cfg_regs = pinmux_config_regs, 1232 .cfg_regs = pinmux_config_regs,
1232 .data_regs = pinmux_data_regs, 1233 .data_regs = pinmux_data_regs,
1233 1234
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
index 2de0929315e6..32034387477b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
@@ -296,7 +296,7 @@ enum {
296 PINMUX_FUNCTION_END, 296 PINMUX_FUNCTION_END,
297}; 297};
298 298
299static pinmux_enum_t pinmux_data[] = { 299static const pinmux_enum_t pinmux_data[] = {
300 /* PTA */ 300 /* PTA */
301 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT), 301 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_IN_PD, PTA7_OUT),
302 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD), 302 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_IN_PD),
@@ -787,7 +787,7 @@ static pinmux_enum_t pinmux_data[] = {
787 PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5), 787 PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5),
788}; 788};
789 789
790static struct pinmux_gpio pinmux_gpios[] = { 790static struct sh_pfc_pin pinmux_pins[] = {
791 /* PTA */ 791 /* PTA */
792 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), 792 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
793 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), 793 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -982,289 +982,293 @@ static struct pinmux_gpio pinmux_gpios[] = {
982 PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA), 982 PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
983 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), 983 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
984 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), 984 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
985};
986
987#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
985 988
989static const struct pinmux_func pinmux_func_gpios[] = {
986 /* SCIF0 */ 990 /* SCIF0 */
987 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), 991 GPIO_FN(SCIF0_TXD),
988 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), 992 GPIO_FN(SCIF0_RXD),
989 PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), 993 GPIO_FN(SCIF0_RTS),
990 PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), 994 GPIO_FN(SCIF0_CTS),
991 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), 995 GPIO_FN(SCIF0_SCK),
992 996
993 /* SCIF1 */ 997 /* SCIF1 */
994 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), 998 GPIO_FN(SCIF1_TXD),
995 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), 999 GPIO_FN(SCIF1_RXD),
996 PINMUX_GPIO(GPIO_FN_SCIF1_RTS, SCIF1_RTS_MARK), 1000 GPIO_FN(SCIF1_RTS),
997 PINMUX_GPIO(GPIO_FN_SCIF1_CTS, SCIF1_CTS_MARK), 1001 GPIO_FN(SCIF1_CTS),
998 PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), 1002 GPIO_FN(SCIF1_SCK),
999 1003
1000 /* SCIF2 */ 1004 /* SCIF2 */
1001 PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK), 1005 GPIO_FN(SCIF2_TXD),
1002 PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK), 1006 GPIO_FN(SCIF2_RXD),
1003 PINMUX_GPIO(GPIO_FN_SCIF2_RTS, SCIF2_RTS_MARK), 1007 GPIO_FN(SCIF2_RTS),
1004 PINMUX_GPIO(GPIO_FN_SCIF2_CTS, SCIF2_CTS_MARK), 1008 GPIO_FN(SCIF2_CTS),
1005 PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK), 1009 GPIO_FN(SCIF2_SCK),
1006 1010
1007 /* SIO */ 1011 /* SIO */
1008 PINMUX_GPIO(GPIO_FN_SIOTXD, SIOTXD_MARK), 1012 GPIO_FN(SIOTXD),
1009 PINMUX_GPIO(GPIO_FN_SIORXD, SIORXD_MARK), 1013 GPIO_FN(SIORXD),
1010 PINMUX_GPIO(GPIO_FN_SIOD, SIOD_MARK), 1014 GPIO_FN(SIOD),
1011 PINMUX_GPIO(GPIO_FN_SIOSTRB0, SIOSTRB0_MARK), 1015 GPIO_FN(SIOSTRB0),
1012 PINMUX_GPIO(GPIO_FN_SIOSTRB1, SIOSTRB1_MARK), 1016 GPIO_FN(SIOSTRB1),
1013 PINMUX_GPIO(GPIO_FN_SIOSCK, SIOSCK_MARK), 1017 GPIO_FN(SIOSCK),
1014 PINMUX_GPIO(GPIO_FN_SIOMCK, SIOMCK_MARK), 1018 GPIO_FN(SIOMCK),
1015 1019
1016 /* CEU */ 1020 /* CEU */
1017 PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK), 1021 GPIO_FN(VIO_D15),
1018 PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK), 1022 GPIO_FN(VIO_D14),
1019 PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK), 1023 GPIO_FN(VIO_D13),
1020 PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK), 1024 GPIO_FN(VIO_D12),
1021 PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK), 1025 GPIO_FN(VIO_D11),
1022 PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK), 1026 GPIO_FN(VIO_D10),
1023 PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK), 1027 GPIO_FN(VIO_D9),
1024 PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK), 1028 GPIO_FN(VIO_D8),
1025 PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK), 1029 GPIO_FN(VIO_D7),
1026 PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK), 1030 GPIO_FN(VIO_D6),
1027 PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK), 1031 GPIO_FN(VIO_D5),
1028 PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK), 1032 GPIO_FN(VIO_D4),
1029 PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK), 1033 GPIO_FN(VIO_D3),
1030 PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK), 1034 GPIO_FN(VIO_D2),
1031 PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK), 1035 GPIO_FN(VIO_D1),
1032 PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK), 1036 GPIO_FN(VIO_D0),
1033 PINMUX_GPIO(GPIO_FN_VIO_CLK, VIO_CLK_MARK), 1037 GPIO_FN(VIO_CLK),
1034 PINMUX_GPIO(GPIO_FN_VIO_VD, VIO_VD_MARK), 1038 GPIO_FN(VIO_VD),
1035 PINMUX_GPIO(GPIO_FN_VIO_HD, VIO_HD_MARK), 1039 GPIO_FN(VIO_HD),
1036 PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK), 1040 GPIO_FN(VIO_FLD),
1037 PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), 1041 GPIO_FN(VIO_CKO),
1038 PINMUX_GPIO(GPIO_FN_VIO_STEX, VIO_STEX_MARK), 1042 GPIO_FN(VIO_STEX),
1039 PINMUX_GPIO(GPIO_FN_VIO_STEM, VIO_STEM_MARK), 1043 GPIO_FN(VIO_STEM),
1040 PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK), 1044 GPIO_FN(VIO_VD2),
1041 PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK), 1045 GPIO_FN(VIO_HD2),
1042 PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK), 1046 GPIO_FN(VIO_CLK2),
1043 1047
1044 /* LCDC */ 1048 /* LCDC */
1045 PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), 1049 GPIO_FN(LCDD23),
1046 PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), 1050 GPIO_FN(LCDD22),
1047 PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), 1051 GPIO_FN(LCDD21),
1048 PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), 1052 GPIO_FN(LCDD20),
1049 PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), 1053 GPIO_FN(LCDD19),
1050 PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), 1054 GPIO_FN(LCDD18),
1051 PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), 1055 GPIO_FN(LCDD17),
1052 PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), 1056 GPIO_FN(LCDD16),
1053 PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), 1057 GPIO_FN(LCDD15),
1054 PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), 1058 GPIO_FN(LCDD14),
1055 PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), 1059 GPIO_FN(LCDD13),
1056 PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), 1060 GPIO_FN(LCDD12),
1057 PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), 1061 GPIO_FN(LCDD11),
1058 PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), 1062 GPIO_FN(LCDD10),
1059 PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), 1063 GPIO_FN(LCDD9),
1060 PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), 1064 GPIO_FN(LCDD8),
1061 PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), 1065 GPIO_FN(LCDD7),
1062 PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), 1066 GPIO_FN(LCDD6),
1063 PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), 1067 GPIO_FN(LCDD5),
1064 PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), 1068 GPIO_FN(LCDD4),
1065 PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), 1069 GPIO_FN(LCDD3),
1066 PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), 1070 GPIO_FN(LCDD2),
1067 PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), 1071 GPIO_FN(LCDD1),
1068 PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), 1072 GPIO_FN(LCDD0),
1069 PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK), 1073 GPIO_FN(LCDLCLK),
1070 /* Main LCD */ 1074 /* Main LCD */
1071 PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), 1075 GPIO_FN(LCDDON),
1072 PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), 1076 GPIO_FN(LCDVCPWC),
1073 PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), 1077 GPIO_FN(LCDVEPWC),
1074 PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), 1078 GPIO_FN(LCDVSYN),
1075 /* Main LCD - RGB Mode */ 1079 /* Main LCD - RGB Mode */
1076 PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), 1080 GPIO_FN(LCDDCK),
1077 PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), 1081 GPIO_FN(LCDHSYN),
1078 PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), 1082 GPIO_FN(LCDDISP),
1079 /* Main LCD - SYS Mode */ 1083 /* Main LCD - SYS Mode */
1080 PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), 1084 GPIO_FN(LCDRS),
1081 PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), 1085 GPIO_FN(LCDCS),
1082 PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), 1086 GPIO_FN(LCDWR),
1083 PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), 1087 GPIO_FN(LCDRD),
1084 /* Sub LCD - SYS Mode */ 1088 /* Sub LCD - SYS Mode */
1085 PINMUX_GPIO(GPIO_FN_LCDDON2, LCDDON2_MARK), 1089 GPIO_FN(LCDDON2),
1086 PINMUX_GPIO(GPIO_FN_LCDVCPWC2, LCDVCPWC2_MARK), 1090 GPIO_FN(LCDVCPWC2),
1087 PINMUX_GPIO(GPIO_FN_LCDVEPWC2, LCDVEPWC2_MARK), 1091 GPIO_FN(LCDVEPWC2),
1088 PINMUX_GPIO(GPIO_FN_LCDVSYN2, LCDVSYN2_MARK), 1092 GPIO_FN(LCDVSYN2),
1089 PINMUX_GPIO(GPIO_FN_LCDCS2, LCDCS2_MARK), 1093 GPIO_FN(LCDCS2),
1090 1094
1091 /* BSC */ 1095 /* BSC */
1092 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 1096 GPIO_FN(IOIS16),
1093 PINMUX_GPIO(GPIO_FN_A25, A25_MARK), 1097 GPIO_FN(A25),
1094 PINMUX_GPIO(GPIO_FN_A24, A24_MARK), 1098 GPIO_FN(A24),
1095 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 1099 GPIO_FN(A23),
1096 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 1100 GPIO_FN(A22),
1097 PINMUX_GPIO(GPIO_FN_BS, BS_MARK), 1101 GPIO_FN(BS),
1098 PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), 1102 GPIO_FN(CS6B_CE1B),
1099 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), 1103 GPIO_FN(WAIT),
1100 PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), 1104 GPIO_FN(CS6A_CE2B),
1101 1105
1102 /* SBSC */ 1106 /* SBSC */
1103 PINMUX_GPIO(GPIO_FN_HPD63, HPD63_MARK), 1107 GPIO_FN(HPD63),
1104 PINMUX_GPIO(GPIO_FN_HPD62, HPD62_MARK), 1108 GPIO_FN(HPD62),
1105 PINMUX_GPIO(GPIO_FN_HPD61, HPD61_MARK), 1109 GPIO_FN(HPD61),
1106 PINMUX_GPIO(GPIO_FN_HPD60, HPD60_MARK), 1110 GPIO_FN(HPD60),
1107 PINMUX_GPIO(GPIO_FN_HPD59, HPD59_MARK), 1111 GPIO_FN(HPD59),
1108 PINMUX_GPIO(GPIO_FN_HPD58, HPD58_MARK), 1112 GPIO_FN(HPD58),
1109 PINMUX_GPIO(GPIO_FN_HPD57, HPD57_MARK), 1113 GPIO_FN(HPD57),
1110 PINMUX_GPIO(GPIO_FN_HPD56, HPD56_MARK), 1114 GPIO_FN(HPD56),
1111 PINMUX_GPIO(GPIO_FN_HPD55, HPD55_MARK), 1115 GPIO_FN(HPD55),
1112 PINMUX_GPIO(GPIO_FN_HPD54, HPD54_MARK), 1116 GPIO_FN(HPD54),
1113 PINMUX_GPIO(GPIO_FN_HPD53, HPD53_MARK), 1117 GPIO_FN(HPD53),
1114 PINMUX_GPIO(GPIO_FN_HPD52, HPD52_MARK), 1118 GPIO_FN(HPD52),
1115 PINMUX_GPIO(GPIO_FN_HPD51, HPD51_MARK), 1119 GPIO_FN(HPD51),
1116 PINMUX_GPIO(GPIO_FN_HPD50, HPD50_MARK), 1120 GPIO_FN(HPD50),
1117 PINMUX_GPIO(GPIO_FN_HPD49, HPD49_MARK), 1121 GPIO_FN(HPD49),
1118 PINMUX_GPIO(GPIO_FN_HPD48, HPD48_MARK), 1122 GPIO_FN(HPD48),
1119 PINMUX_GPIO(GPIO_FN_HPDQM7, HPDQM7_MARK), 1123 GPIO_FN(HPDQM7),
1120 PINMUX_GPIO(GPIO_FN_HPDQM6, HPDQM6_MARK), 1124 GPIO_FN(HPDQM6),
1121 PINMUX_GPIO(GPIO_FN_HPDQM5, HPDQM5_MARK), 1125 GPIO_FN(HPDQM5),
1122 PINMUX_GPIO(GPIO_FN_HPDQM4, HPDQM4_MARK), 1126 GPIO_FN(HPDQM4),
1123 1127
1124 /* IRQ */ 1128 /* IRQ */
1125 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), 1129 GPIO_FN(IRQ0),
1126 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), 1130 GPIO_FN(IRQ1),
1127 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), 1131 GPIO_FN(IRQ2),
1128 PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), 1132 GPIO_FN(IRQ3),
1129 PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), 1133 GPIO_FN(IRQ4),
1130 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), 1134 GPIO_FN(IRQ5),
1131 PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), 1135 GPIO_FN(IRQ6),
1132 PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), 1136 GPIO_FN(IRQ7),
1133 1137
1134 /* SDHI */ 1138 /* SDHI */
1135 PINMUX_GPIO(GPIO_FN_SDHICD, SDHICD_MARK), 1139 GPIO_FN(SDHICD),
1136 PINMUX_GPIO(GPIO_FN_SDHIWP, SDHIWP_MARK), 1140 GPIO_FN(SDHIWP),
1137 PINMUX_GPIO(GPIO_FN_SDHID3, SDHID3_MARK), 1141 GPIO_FN(SDHID3),
1138 PINMUX_GPIO(GPIO_FN_SDHID2, SDHID2_MARK), 1142 GPIO_FN(SDHID2),
1139 PINMUX_GPIO(GPIO_FN_SDHID1, SDHID1_MARK), 1143 GPIO_FN(SDHID1),
1140 PINMUX_GPIO(GPIO_FN_SDHID0, SDHID0_MARK), 1144 GPIO_FN(SDHID0),
1141 PINMUX_GPIO(GPIO_FN_SDHICMD, SDHICMD_MARK), 1145 GPIO_FN(SDHICMD),
1142 PINMUX_GPIO(GPIO_FN_SDHICLK, SDHICLK_MARK), 1146 GPIO_FN(SDHICLK),
1143 1147
1144 /* SIU - Port A */ 1148 /* SIU - Port A */
1145 PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK), 1149 GPIO_FN(SIUAOLR),
1146 PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK), 1150 GPIO_FN(SIUAOBT),
1147 PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK), 1151 GPIO_FN(SIUAISLD),
1148 PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK), 1152 GPIO_FN(SIUAILR),
1149 PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK), 1153 GPIO_FN(SIUAIBT),
1150 PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK), 1154 GPIO_FN(SIUAOSLD),
1151 PINMUX_GPIO(GPIO_FN_SIUMCKA, SIUMCKA_MARK), 1155 GPIO_FN(SIUMCKA),
1152 PINMUX_GPIO(GPIO_FN_SIUFCKA, SIUFCKA_MARK), 1156 GPIO_FN(SIUFCKA),
1153 1157
1154 /* SIU - Port B */ 1158 /* SIU - Port B */
1155 PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK), 1159 GPIO_FN(SIUBOLR),
1156 PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK), 1160 GPIO_FN(SIUBOBT),
1157 PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK), 1161 GPIO_FN(SIUBISLD),
1158 PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK), 1162 GPIO_FN(SIUBILR),
1159 PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK), 1163 GPIO_FN(SIUBIBT),
1160 PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK), 1164 GPIO_FN(SIUBOSLD),
1161 PINMUX_GPIO(GPIO_FN_SIUMCKB, SIUMCKB_MARK), 1165 GPIO_FN(SIUMCKB),
1162 PINMUX_GPIO(GPIO_FN_SIUFCKB, SIUFCKB_MARK), 1166 GPIO_FN(SIUFCKB),
1163 1167
1164 /* AUD */ 1168 /* AUD */
1165 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), 1169 GPIO_FN(AUDSYNC),
1166 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), 1170 GPIO_FN(AUDATA3),
1167 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), 1171 GPIO_FN(AUDATA2),
1168 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), 1172 GPIO_FN(AUDATA1),
1169 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), 1173 GPIO_FN(AUDATA0),
1170 1174
1171 /* DMAC */ 1175 /* DMAC */
1172 PINMUX_GPIO(GPIO_FN_DACK, DACK_MARK), 1176 GPIO_FN(DACK),
1173 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 1177 GPIO_FN(DREQ0),
1174 1178
1175 /* VOU */ 1179 /* VOU */
1176 PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), 1180 GPIO_FN(DV_CLKI),
1177 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), 1181 GPIO_FN(DV_CLK),
1178 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), 1182 GPIO_FN(DV_HSYNC),
1179 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), 1183 GPIO_FN(DV_VSYNC),
1180 PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), 1184 GPIO_FN(DV_D15),
1181 PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), 1185 GPIO_FN(DV_D14),
1182 PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), 1186 GPIO_FN(DV_D13),
1183 PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), 1187 GPIO_FN(DV_D12),
1184 PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), 1188 GPIO_FN(DV_D11),
1185 PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), 1189 GPIO_FN(DV_D10),
1186 PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), 1190 GPIO_FN(DV_D9),
1187 PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), 1191 GPIO_FN(DV_D8),
1188 PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), 1192 GPIO_FN(DV_D7),
1189 PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), 1193 GPIO_FN(DV_D6),
1190 PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), 1194 GPIO_FN(DV_D5),
1191 PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), 1195 GPIO_FN(DV_D4),
1192 PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), 1196 GPIO_FN(DV_D3),
1193 PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), 1197 GPIO_FN(DV_D2),
1194 PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), 1198 GPIO_FN(DV_D1),
1195 PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), 1199 GPIO_FN(DV_D0),
1196 1200
1197 /* CPG */ 1201 /* CPG */
1198 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), 1202 GPIO_FN(STATUS0),
1199 PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), 1203 GPIO_FN(PDSTATUS),
1200 1204
1201 /* SIOF0 */ 1205 /* SIOF0 */
1202 PINMUX_GPIO(GPIO_FN_SIOF0_MCK, SIOF0_MCK_MARK), 1206 GPIO_FN(SIOF0_MCK),
1203 PINMUX_GPIO(GPIO_FN_SIOF0_SCK, SIOF0_SCK_MARK), 1207 GPIO_FN(SIOF0_SCK),
1204 PINMUX_GPIO(GPIO_FN_SIOF0_SYNC, SIOF0_SYNC_MARK), 1208 GPIO_FN(SIOF0_SYNC),
1205 PINMUX_GPIO(GPIO_FN_SIOF0_SS1, SIOF0_SS1_MARK), 1209 GPIO_FN(SIOF0_SS1),
1206 PINMUX_GPIO(GPIO_FN_SIOF0_SS2, SIOF0_SS2_MARK), 1210 GPIO_FN(SIOF0_SS2),
1207 PINMUX_GPIO(GPIO_FN_SIOF0_TXD, SIOF0_TXD_MARK), 1211 GPIO_FN(SIOF0_TXD),
1208 PINMUX_GPIO(GPIO_FN_SIOF0_RXD, SIOF0_RXD_MARK), 1212 GPIO_FN(SIOF0_RXD),
1209 1213
1210 /* SIOF1 */ 1214 /* SIOF1 */
1211 PINMUX_GPIO(GPIO_FN_SIOF1_MCK, SIOF1_MCK_MARK), 1215 GPIO_FN(SIOF1_MCK),
1212 PINMUX_GPIO(GPIO_FN_SIOF1_SCK, SIOF1_SCK_MARK), 1216 GPIO_FN(SIOF1_SCK),
1213 PINMUX_GPIO(GPIO_FN_SIOF1_SYNC, SIOF1_SYNC_MARK), 1217 GPIO_FN(SIOF1_SYNC),
1214 PINMUX_GPIO(GPIO_FN_SIOF1_SS1, SIOF1_SS1_MARK), 1218 GPIO_FN(SIOF1_SS1),
1215 PINMUX_GPIO(GPIO_FN_SIOF1_SS2, SIOF1_SS2_MARK), 1219 GPIO_FN(SIOF1_SS2),
1216 PINMUX_GPIO(GPIO_FN_SIOF1_TXD, SIOF1_TXD_MARK), 1220 GPIO_FN(SIOF1_TXD),
1217 PINMUX_GPIO(GPIO_FN_SIOF1_RXD, SIOF1_RXD_MARK), 1221 GPIO_FN(SIOF1_RXD),
1218 1222
1219 /* SIM */ 1223 /* SIM */
1220 PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), 1224 GPIO_FN(SIM_D),
1221 PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), 1225 GPIO_FN(SIM_CLK),
1222 PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), 1226 GPIO_FN(SIM_RST),
1223 1227
1224 /* TSIF */ 1228 /* TSIF */
1225 PINMUX_GPIO(GPIO_FN_TS_SDAT, TS_SDAT_MARK), 1229 GPIO_FN(TS_SDAT),
1226 PINMUX_GPIO(GPIO_FN_TS_SCK, TS_SCK_MARK), 1230 GPIO_FN(TS_SCK),
1227 PINMUX_GPIO(GPIO_FN_TS_SDEN, TS_SDEN_MARK), 1231 GPIO_FN(TS_SDEN),
1228 PINMUX_GPIO(GPIO_FN_TS_SPSYNC, TS_SPSYNC_MARK), 1232 GPIO_FN(TS_SPSYNC),
1229 1233
1230 /* IRDA */ 1234 /* IRDA */
1231 PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), 1235 GPIO_FN(IRDA_IN),
1232 PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), 1236 GPIO_FN(IRDA_OUT),
1233 1237
1234 /* TPU */ 1238 /* TPU */
1235 PINMUX_GPIO(GPIO_FN_TPUTO, TPUTO_MARK), 1239 GPIO_FN(TPUTO),
1236 1240
1237 /* FLCTL */ 1241 /* FLCTL */
1238 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), 1242 GPIO_FN(FCE),
1239 PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), 1243 GPIO_FN(NAF7),
1240 PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), 1244 GPIO_FN(NAF6),
1241 PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), 1245 GPIO_FN(NAF5),
1242 PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), 1246 GPIO_FN(NAF4),
1243 PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), 1247 GPIO_FN(NAF3),
1244 PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), 1248 GPIO_FN(NAF2),
1245 PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), 1249 GPIO_FN(NAF1),
1246 PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), 1250 GPIO_FN(NAF0),
1247 PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), 1251 GPIO_FN(FCDE),
1248 PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), 1252 GPIO_FN(FOE),
1249 PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), 1253 GPIO_FN(FSC),
1250 PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), 1254 GPIO_FN(FWE),
1251 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), 1255 GPIO_FN(FRB),
1252 1256
1253 /* KEYSC */ 1257 /* KEYSC */
1254 PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), 1258 GPIO_FN(KEYIN0),
1255 PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), 1259 GPIO_FN(KEYIN1),
1256 PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), 1260 GPIO_FN(KEYIN2),
1257 PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), 1261 GPIO_FN(KEYIN3),
1258 PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), 1262 GPIO_FN(KEYIN4),
1259 PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), 1263 GPIO_FN(KEYOUT0),
1260 PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), 1264 GPIO_FN(KEYOUT1),
1261 PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), 1265 GPIO_FN(KEYOUT2),
1262 PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), 1266 GPIO_FN(KEYOUT3),
1263 PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), 1267 GPIO_FN(KEYOUT4_IN6),
1264 PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), 1268 GPIO_FN(KEYOUT5_IN5),
1265}; 1269};
1266 1270
1267static struct pinmux_cfg_reg pinmux_config_regs[] = { 1271static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1268 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { 1272 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
1269 VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN, 1273 VIO_D7_SCIF1_SCK, PTA7_OUT, PTA7_IN_PD, PTA7_IN,
1270 VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN, 1274 VIO_D6_SCIF1_RXD, 0, PTA6_IN_PD, PTA6_IN,
@@ -1660,7 +1664,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1660 {} 1664 {}
1661}; 1665};
1662 1666
1663static struct pinmux_data_reg pinmux_data_regs[] = { 1667static const struct pinmux_data_reg pinmux_data_regs[] = {
1664 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { 1668 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
1665 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, 1669 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
1666 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } 1670 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -1756,21 +1760,19 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1756 { }, 1760 { },
1757}; 1761};
1758 1762
1759struct sh_pfc_soc_info sh7722_pinmux_info = { 1763const struct sh_pfc_soc_info sh7722_pinmux_info = {
1760 .name = "sh7722_pfc", 1764 .name = "sh7722_pfc",
1761 .reserved_id = PINMUX_RESERVED,
1762 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1763 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 1765 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1764 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END }, 1766 .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
1765 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 1767 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1766 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 1768 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1767 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1768 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 1769 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1769 1770
1770 .first_gpio = GPIO_PTA7, 1771 .pins = pinmux_pins,
1771 .last_gpio = GPIO_FN_KEYOUT5_IN5, 1772 .nr_pins = ARRAY_SIZE(pinmux_pins),
1773 .func_gpios = pinmux_func_gpios,
1774 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
1772 1775
1773 .gpios = pinmux_gpios,
1774 .cfg_regs = pinmux_config_regs, 1776 .cfg_regs = pinmux_config_regs,
1775 .data_regs = pinmux_data_regs, 1777 .data_regs = pinmux_data_regs,
1776 1778
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
index 609673d3d70e..07ad1d8d6c8b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
@@ -350,7 +350,7 @@ enum {
350 PINMUX_MARK_END, 350 PINMUX_MARK_END,
351}; 351};
352 352
353static pinmux_enum_t pinmux_data[] = { 353static const pinmux_enum_t pinmux_data[] = {
354 /* PTA GPIO */ 354 /* PTA GPIO */
355 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), 355 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
356 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), 356 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
@@ -923,7 +923,7 @@ static pinmux_enum_t pinmux_data[] = {
923 PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN), 923 PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN),
924}; 924};
925 925
926static struct pinmux_gpio pinmux_gpios[] = { 926static struct sh_pfc_pin pinmux_pins[] = {
927 /* PTA */ 927 /* PTA */
928 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), 928 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
929 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), 929 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -1139,379 +1139,383 @@ static struct pinmux_gpio pinmux_gpios[] = {
1139 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), 1139 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
1140 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), 1140 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
1141 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), 1141 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
1142};
1143
1144#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
1142 1145
1146static const struct pinmux_func pinmux_func_gpios[] = {
1143 /* SCIF0 */ 1147 /* SCIF0 */
1144 PINMUX_GPIO(GPIO_FN_SCIF0_PTT_TXD, SCIF0_PTT_TXD_MARK), 1148 GPIO_FN(SCIF0_PTT_TXD),
1145 PINMUX_GPIO(GPIO_FN_SCIF0_PTT_RXD, SCIF0_PTT_RXD_MARK), 1149 GPIO_FN(SCIF0_PTT_RXD),
1146 PINMUX_GPIO(GPIO_FN_SCIF0_PTT_SCK, SCIF0_PTT_SCK_MARK), 1150 GPIO_FN(SCIF0_PTT_SCK),
1147 PINMUX_GPIO(GPIO_FN_SCIF0_PTU_TXD, SCIF0_PTU_TXD_MARK), 1151 GPIO_FN(SCIF0_PTU_TXD),
1148 PINMUX_GPIO(GPIO_FN_SCIF0_PTU_RXD, SCIF0_PTU_RXD_MARK), 1152 GPIO_FN(SCIF0_PTU_RXD),
1149 PINMUX_GPIO(GPIO_FN_SCIF0_PTU_SCK, SCIF0_PTU_SCK_MARK), 1153 GPIO_FN(SCIF0_PTU_SCK),
1150 1154
1151 /* SCIF1 */ 1155 /* SCIF1 */
1152 PINMUX_GPIO(GPIO_FN_SCIF1_PTS_TXD, SCIF1_PTS_TXD_MARK), 1156 GPIO_FN(SCIF1_PTS_TXD),
1153 PINMUX_GPIO(GPIO_FN_SCIF1_PTS_RXD, SCIF1_PTS_RXD_MARK), 1157 GPIO_FN(SCIF1_PTS_RXD),
1154 PINMUX_GPIO(GPIO_FN_SCIF1_PTS_SCK, SCIF1_PTS_SCK_MARK), 1158 GPIO_FN(SCIF1_PTS_SCK),
1155 PINMUX_GPIO(GPIO_FN_SCIF1_PTV_TXD, SCIF1_PTV_TXD_MARK), 1159 GPIO_FN(SCIF1_PTV_TXD),
1156 PINMUX_GPIO(GPIO_FN_SCIF1_PTV_RXD, SCIF1_PTV_RXD_MARK), 1160 GPIO_FN(SCIF1_PTV_RXD),
1157 PINMUX_GPIO(GPIO_FN_SCIF1_PTV_SCK, SCIF1_PTV_SCK_MARK), 1161 GPIO_FN(SCIF1_PTV_SCK),
1158 1162
1159 /* SCIF2 */ 1163 /* SCIF2 */
1160 PINMUX_GPIO(GPIO_FN_SCIF2_PTT_TXD, SCIF2_PTT_TXD_MARK), 1164 GPIO_FN(SCIF2_PTT_TXD),
1161 PINMUX_GPIO(GPIO_FN_SCIF2_PTT_RXD, SCIF2_PTT_RXD_MARK), 1165 GPIO_FN(SCIF2_PTT_RXD),
1162 PINMUX_GPIO(GPIO_FN_SCIF2_PTT_SCK, SCIF2_PTT_SCK_MARK), 1166 GPIO_FN(SCIF2_PTT_SCK),
1163 PINMUX_GPIO(GPIO_FN_SCIF2_PTU_TXD, SCIF2_PTU_TXD_MARK), 1167 GPIO_FN(SCIF2_PTU_TXD),
1164 PINMUX_GPIO(GPIO_FN_SCIF2_PTU_RXD, SCIF2_PTU_RXD_MARK), 1168 GPIO_FN(SCIF2_PTU_RXD),
1165 PINMUX_GPIO(GPIO_FN_SCIF2_PTU_SCK, SCIF2_PTU_SCK_MARK), 1169 GPIO_FN(SCIF2_PTU_SCK),
1166 1170
1167 /* SCIF3 */ 1171 /* SCIF3 */
1168 PINMUX_GPIO(GPIO_FN_SCIF3_PTS_TXD, SCIF3_PTS_TXD_MARK), 1172 GPIO_FN(SCIF3_PTS_TXD),
1169 PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RXD, SCIF3_PTS_RXD_MARK), 1173 GPIO_FN(SCIF3_PTS_RXD),
1170 PINMUX_GPIO(GPIO_FN_SCIF3_PTS_SCK, SCIF3_PTS_SCK_MARK), 1174 GPIO_FN(SCIF3_PTS_SCK),
1171 PINMUX_GPIO(GPIO_FN_SCIF3_PTS_RTS, SCIF3_PTS_RTS_MARK), 1175 GPIO_FN(SCIF3_PTS_RTS),
1172 PINMUX_GPIO(GPIO_FN_SCIF3_PTS_CTS, SCIF3_PTS_CTS_MARK), 1176 GPIO_FN(SCIF3_PTS_CTS),
1173 PINMUX_GPIO(GPIO_FN_SCIF3_PTV_TXD, SCIF3_PTV_TXD_MARK), 1177 GPIO_FN(SCIF3_PTV_TXD),
1174 PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RXD, SCIF3_PTV_RXD_MARK), 1178 GPIO_FN(SCIF3_PTV_RXD),
1175 PINMUX_GPIO(GPIO_FN_SCIF3_PTV_SCK, SCIF3_PTV_SCK_MARK), 1179 GPIO_FN(SCIF3_PTV_SCK),
1176 PINMUX_GPIO(GPIO_FN_SCIF3_PTV_RTS, SCIF3_PTV_RTS_MARK), 1180 GPIO_FN(SCIF3_PTV_RTS),
1177 PINMUX_GPIO(GPIO_FN_SCIF3_PTV_CTS, SCIF3_PTV_CTS_MARK), 1181 GPIO_FN(SCIF3_PTV_CTS),
1178 1182
1179 /* SCIF4 */ 1183 /* SCIF4 */
1180 PINMUX_GPIO(GPIO_FN_SCIF4_PTE_TXD, SCIF4_PTE_TXD_MARK), 1184 GPIO_FN(SCIF4_PTE_TXD),
1181 PINMUX_GPIO(GPIO_FN_SCIF4_PTE_RXD, SCIF4_PTE_RXD_MARK), 1185 GPIO_FN(SCIF4_PTE_RXD),
1182 PINMUX_GPIO(GPIO_FN_SCIF4_PTE_SCK, SCIF4_PTE_SCK_MARK), 1186 GPIO_FN(SCIF4_PTE_SCK),
1183 PINMUX_GPIO(GPIO_FN_SCIF4_PTN_TXD, SCIF4_PTN_TXD_MARK), 1187 GPIO_FN(SCIF4_PTN_TXD),
1184 PINMUX_GPIO(GPIO_FN_SCIF4_PTN_RXD, SCIF4_PTN_RXD_MARK), 1188 GPIO_FN(SCIF4_PTN_RXD),
1185 PINMUX_GPIO(GPIO_FN_SCIF4_PTN_SCK, SCIF4_PTN_SCK_MARK), 1189 GPIO_FN(SCIF4_PTN_SCK),
1186 1190
1187 /* SCIF5 */ 1191 /* SCIF5 */
1188 PINMUX_GPIO(GPIO_FN_SCIF5_PTE_TXD, SCIF5_PTE_TXD_MARK), 1192 GPIO_FN(SCIF5_PTE_TXD),
1189 PINMUX_GPIO(GPIO_FN_SCIF5_PTE_RXD, SCIF5_PTE_RXD_MARK), 1193 GPIO_FN(SCIF5_PTE_RXD),
1190 PINMUX_GPIO(GPIO_FN_SCIF5_PTE_SCK, SCIF5_PTE_SCK_MARK), 1194 GPIO_FN(SCIF5_PTE_SCK),
1191 PINMUX_GPIO(GPIO_FN_SCIF5_PTN_TXD, SCIF5_PTN_TXD_MARK), 1195 GPIO_FN(SCIF5_PTN_TXD),
1192 PINMUX_GPIO(GPIO_FN_SCIF5_PTN_RXD, SCIF5_PTN_RXD_MARK), 1196 GPIO_FN(SCIF5_PTN_RXD),
1193 PINMUX_GPIO(GPIO_FN_SCIF5_PTN_SCK, SCIF5_PTN_SCK_MARK), 1197 GPIO_FN(SCIF5_PTN_SCK),
1194 1198
1195 /* CEU */ 1199 /* CEU */
1196 PINMUX_GPIO(GPIO_FN_VIO_D15, VIO_D15_MARK), 1200 GPIO_FN(VIO_D15),
1197 PINMUX_GPIO(GPIO_FN_VIO_D14, VIO_D14_MARK), 1201 GPIO_FN(VIO_D14),
1198 PINMUX_GPIO(GPIO_FN_VIO_D13, VIO_D13_MARK), 1202 GPIO_FN(VIO_D13),
1199 PINMUX_GPIO(GPIO_FN_VIO_D12, VIO_D12_MARK), 1203 GPIO_FN(VIO_D12),
1200 PINMUX_GPIO(GPIO_FN_VIO_D11, VIO_D11_MARK), 1204 GPIO_FN(VIO_D11),
1201 PINMUX_GPIO(GPIO_FN_VIO_D10, VIO_D10_MARK), 1205 GPIO_FN(VIO_D10),
1202 PINMUX_GPIO(GPIO_FN_VIO_D9, VIO_D9_MARK), 1206 GPIO_FN(VIO_D9),
1203 PINMUX_GPIO(GPIO_FN_VIO_D8, VIO_D8_MARK), 1207 GPIO_FN(VIO_D8),
1204 PINMUX_GPIO(GPIO_FN_VIO_D7, VIO_D7_MARK), 1208 GPIO_FN(VIO_D7),
1205 PINMUX_GPIO(GPIO_FN_VIO_D6, VIO_D6_MARK), 1209 GPIO_FN(VIO_D6),
1206 PINMUX_GPIO(GPIO_FN_VIO_D5, VIO_D5_MARK), 1210 GPIO_FN(VIO_D5),
1207 PINMUX_GPIO(GPIO_FN_VIO_D4, VIO_D4_MARK), 1211 GPIO_FN(VIO_D4),
1208 PINMUX_GPIO(GPIO_FN_VIO_D3, VIO_D3_MARK), 1212 GPIO_FN(VIO_D3),
1209 PINMUX_GPIO(GPIO_FN_VIO_D2, VIO_D2_MARK), 1213 GPIO_FN(VIO_D2),
1210 PINMUX_GPIO(GPIO_FN_VIO_D1, VIO_D1_MARK), 1214 GPIO_FN(VIO_D1),
1211 PINMUX_GPIO(GPIO_FN_VIO_D0, VIO_D0_MARK), 1215 GPIO_FN(VIO_D0),
1212 PINMUX_GPIO(GPIO_FN_VIO_CLK1, VIO_CLK1_MARK), 1216 GPIO_FN(VIO_CLK1),
1213 PINMUX_GPIO(GPIO_FN_VIO_VD1, VIO_VD1_MARK), 1217 GPIO_FN(VIO_VD1),
1214 PINMUX_GPIO(GPIO_FN_VIO_HD1, VIO_HD1_MARK), 1218 GPIO_FN(VIO_HD1),
1215 PINMUX_GPIO(GPIO_FN_VIO_FLD, VIO_FLD_MARK), 1219 GPIO_FN(VIO_FLD),
1216 PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), 1220 GPIO_FN(VIO_CKO),
1217 PINMUX_GPIO(GPIO_FN_VIO_VD2, VIO_VD2_MARK), 1221 GPIO_FN(VIO_VD2),
1218 PINMUX_GPIO(GPIO_FN_VIO_HD2, VIO_HD2_MARK), 1222 GPIO_FN(VIO_HD2),
1219 PINMUX_GPIO(GPIO_FN_VIO_CLK2, VIO_CLK2_MARK), 1223 GPIO_FN(VIO_CLK2),
1220 1224
1221 /* LCDC */ 1225 /* LCDC */
1222 PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), 1226 GPIO_FN(LCDD23),
1223 PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), 1227 GPIO_FN(LCDD22),
1224 PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), 1228 GPIO_FN(LCDD21),
1225 PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), 1229 GPIO_FN(LCDD20),
1226 PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), 1230 GPIO_FN(LCDD19),
1227 PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), 1231 GPIO_FN(LCDD18),
1228 PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), 1232 GPIO_FN(LCDD17),
1229 PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), 1233 GPIO_FN(LCDD16),
1230 PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), 1234 GPIO_FN(LCDD15),
1231 PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), 1235 GPIO_FN(LCDD14),
1232 PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), 1236 GPIO_FN(LCDD13),
1233 PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), 1237 GPIO_FN(LCDD12),
1234 PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), 1238 GPIO_FN(LCDD11),
1235 PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), 1239 GPIO_FN(LCDD10),
1236 PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), 1240 GPIO_FN(LCDD9),
1237 PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), 1241 GPIO_FN(LCDD8),
1238 PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), 1242 GPIO_FN(LCDD7),
1239 PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), 1243 GPIO_FN(LCDD6),
1240 PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), 1244 GPIO_FN(LCDD5),
1241 PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), 1245 GPIO_FN(LCDD4),
1242 PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), 1246 GPIO_FN(LCDD3),
1243 PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), 1247 GPIO_FN(LCDD2),
1244 PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), 1248 GPIO_FN(LCDD1),
1245 PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), 1249 GPIO_FN(LCDD0),
1246 PINMUX_GPIO(GPIO_FN_LCDLCLK_PTR, LCDLCLK_PTR_MARK), 1250 GPIO_FN(LCDLCLK_PTR),
1247 PINMUX_GPIO(GPIO_FN_LCDLCLK_PTW, LCDLCLK_PTW_MARK), 1251 GPIO_FN(LCDLCLK_PTW),
1248 /* Main LCD */ 1252 /* Main LCD */
1249 PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), 1253 GPIO_FN(LCDDON),
1250 PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), 1254 GPIO_FN(LCDVCPWC),
1251 PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), 1255 GPIO_FN(LCDVEPWC),
1252 PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), 1256 GPIO_FN(LCDVSYN),
1253 /* Main LCD - RGB Mode */ 1257 /* Main LCD - RGB Mode */
1254 PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), 1258 GPIO_FN(LCDDCK),
1255 PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), 1259 GPIO_FN(LCDHSYN),
1256 PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), 1260 GPIO_FN(LCDDISP),
1257 /* Main LCD - SYS Mode */ 1261 /* Main LCD - SYS Mode */
1258 PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), 1262 GPIO_FN(LCDRS),
1259 PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), 1263 GPIO_FN(LCDCS),
1260 PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), 1264 GPIO_FN(LCDWR),
1261 PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), 1265 GPIO_FN(LCDRD),
1262 1266
1263 /* IRQ */ 1267 /* IRQ */
1264 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), 1268 GPIO_FN(IRQ0),
1265 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), 1269 GPIO_FN(IRQ1),
1266 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), 1270 GPIO_FN(IRQ2),
1267 PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), 1271 GPIO_FN(IRQ3),
1268 PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), 1272 GPIO_FN(IRQ4),
1269 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), 1273 GPIO_FN(IRQ5),
1270 PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), 1274 GPIO_FN(IRQ6),
1271 PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), 1275 GPIO_FN(IRQ7),
1272 1276
1273 /* AUD */ 1277 /* AUD */
1274 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), 1278 GPIO_FN(AUDCK),
1275 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), 1279 GPIO_FN(AUDSYNC),
1276 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), 1280 GPIO_FN(AUDATA3),
1277 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), 1281 GPIO_FN(AUDATA2),
1278 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), 1282 GPIO_FN(AUDATA1),
1279 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), 1283 GPIO_FN(AUDATA0),
1280 1284
1281 /* SDHI0 (PTD) */ 1285 /* SDHI0 (PTD) */
1282 PINMUX_GPIO(GPIO_FN_SDHI0CD_PTD, SDHI0CD_PTD_MARK), 1286 GPIO_FN(SDHI0CD_PTD),
1283 PINMUX_GPIO(GPIO_FN_SDHI0WP_PTD, SDHI0WP_PTD_MARK), 1287 GPIO_FN(SDHI0WP_PTD),
1284 PINMUX_GPIO(GPIO_FN_SDHI0D3_PTD, SDHI0D3_PTD_MARK), 1288 GPIO_FN(SDHI0D3_PTD),
1285 PINMUX_GPIO(GPIO_FN_SDHI0D2_PTD, SDHI0D2_PTD_MARK), 1289 GPIO_FN(SDHI0D2_PTD),
1286 PINMUX_GPIO(GPIO_FN_SDHI0D1_PTD, SDHI0D1_PTD_MARK), 1290 GPIO_FN(SDHI0D1_PTD),
1287 PINMUX_GPIO(GPIO_FN_SDHI0D0_PTD, SDHI0D0_PTD_MARK), 1291 GPIO_FN(SDHI0D0_PTD),
1288 PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTD, SDHI0CMD_PTD_MARK), 1292 GPIO_FN(SDHI0CMD_PTD),
1289 PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTD, SDHI0CLK_PTD_MARK), 1293 GPIO_FN(SDHI0CLK_PTD),
1290 1294
1291 /* SDHI0 (PTS) */ 1295 /* SDHI0 (PTS) */
1292 PINMUX_GPIO(GPIO_FN_SDHI0CD_PTS, SDHI0CD_PTS_MARK), 1296 GPIO_FN(SDHI0CD_PTS),
1293 PINMUX_GPIO(GPIO_FN_SDHI0WP_PTS, SDHI0WP_PTS_MARK), 1297 GPIO_FN(SDHI0WP_PTS),
1294 PINMUX_GPIO(GPIO_FN_SDHI0D3_PTS, SDHI0D3_PTS_MARK), 1298 GPIO_FN(SDHI0D3_PTS),
1295 PINMUX_GPIO(GPIO_FN_SDHI0D2_PTS, SDHI0D2_PTS_MARK), 1299 GPIO_FN(SDHI0D2_PTS),
1296 PINMUX_GPIO(GPIO_FN_SDHI0D1_PTS, SDHI0D1_PTS_MARK), 1300 GPIO_FN(SDHI0D1_PTS),
1297 PINMUX_GPIO(GPIO_FN_SDHI0D0_PTS, SDHI0D0_PTS_MARK), 1301 GPIO_FN(SDHI0D0_PTS),
1298 PINMUX_GPIO(GPIO_FN_SDHI0CMD_PTS, SDHI0CMD_PTS_MARK), 1302 GPIO_FN(SDHI0CMD_PTS),
1299 PINMUX_GPIO(GPIO_FN_SDHI0CLK_PTS, SDHI0CLK_PTS_MARK), 1303 GPIO_FN(SDHI0CLK_PTS),
1300 1304
1301 /* SDHI1 */ 1305 /* SDHI1 */
1302 PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK), 1306 GPIO_FN(SDHI1CD),
1303 PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK), 1307 GPIO_FN(SDHI1WP),
1304 PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK), 1308 GPIO_FN(SDHI1D3),
1305 PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK), 1309 GPIO_FN(SDHI1D2),
1306 PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK), 1310 GPIO_FN(SDHI1D1),
1307 PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK), 1311 GPIO_FN(SDHI1D0),
1308 PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK), 1312 GPIO_FN(SDHI1CMD),
1309 PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK), 1313 GPIO_FN(SDHI1CLK),
1310 1314
1311 /* SIUA */ 1315 /* SIUA */
1312 PINMUX_GPIO(GPIO_FN_SIUAFCK, SIUAFCK_MARK), 1316 GPIO_FN(SIUAFCK),
1313 PINMUX_GPIO(GPIO_FN_SIUAILR, SIUAILR_MARK), 1317 GPIO_FN(SIUAILR),
1314 PINMUX_GPIO(GPIO_FN_SIUAIBT, SIUAIBT_MARK), 1318 GPIO_FN(SIUAIBT),
1315 PINMUX_GPIO(GPIO_FN_SIUAISLD, SIUAISLD_MARK), 1319 GPIO_FN(SIUAISLD),
1316 PINMUX_GPIO(GPIO_FN_SIUAOLR, SIUAOLR_MARK), 1320 GPIO_FN(SIUAOLR),
1317 PINMUX_GPIO(GPIO_FN_SIUAOBT, SIUAOBT_MARK), 1321 GPIO_FN(SIUAOBT),
1318 PINMUX_GPIO(GPIO_FN_SIUAOSLD, SIUAOSLD_MARK), 1322 GPIO_FN(SIUAOSLD),
1319 PINMUX_GPIO(GPIO_FN_SIUAMCK, SIUAMCK_MARK), 1323 GPIO_FN(SIUAMCK),
1320 PINMUX_GPIO(GPIO_FN_SIUAISPD, SIUAISPD_MARK), 1324 GPIO_FN(SIUAISPD),
1321 PINMUX_GPIO(GPIO_FN_SIUAOSPD, SIUAOSPD_MARK), 1325 GPIO_FN(SIUAOSPD),
1322 1326
1323 /* SIUB */ 1327 /* SIUB */
1324 PINMUX_GPIO(GPIO_FN_SIUBFCK, SIUBFCK_MARK), 1328 GPIO_FN(SIUBFCK),
1325 PINMUX_GPIO(GPIO_FN_SIUBILR, SIUBILR_MARK), 1329 GPIO_FN(SIUBILR),
1326 PINMUX_GPIO(GPIO_FN_SIUBIBT, SIUBIBT_MARK), 1330 GPIO_FN(SIUBIBT),
1327 PINMUX_GPIO(GPIO_FN_SIUBISLD, SIUBISLD_MARK), 1331 GPIO_FN(SIUBISLD),
1328 PINMUX_GPIO(GPIO_FN_SIUBOLR, SIUBOLR_MARK), 1332 GPIO_FN(SIUBOLR),
1329 PINMUX_GPIO(GPIO_FN_SIUBOBT, SIUBOBT_MARK), 1333 GPIO_FN(SIUBOBT),
1330 PINMUX_GPIO(GPIO_FN_SIUBOSLD, SIUBOSLD_MARK), 1334 GPIO_FN(SIUBOSLD),
1331 PINMUX_GPIO(GPIO_FN_SIUBMCK, SIUBMCK_MARK), 1335 GPIO_FN(SIUBMCK),
1332 1336
1333 /* IRDA */ 1337 /* IRDA */
1334 PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), 1338 GPIO_FN(IRDA_IN),
1335 PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), 1339 GPIO_FN(IRDA_OUT),
1336 1340
1337 /* VOU */ 1341 /* VOU */
1338 PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), 1342 GPIO_FN(DV_CLKI),
1339 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), 1343 GPIO_FN(DV_CLK),
1340 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), 1344 GPIO_FN(DV_HSYNC),
1341 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), 1345 GPIO_FN(DV_VSYNC),
1342 PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), 1346 GPIO_FN(DV_D15),
1343 PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), 1347 GPIO_FN(DV_D14),
1344 PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), 1348 GPIO_FN(DV_D13),
1345 PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), 1349 GPIO_FN(DV_D12),
1346 PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), 1350 GPIO_FN(DV_D11),
1347 PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), 1351 GPIO_FN(DV_D10),
1348 PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), 1352 GPIO_FN(DV_D9),
1349 PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), 1353 GPIO_FN(DV_D8),
1350 PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), 1354 GPIO_FN(DV_D7),
1351 PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), 1355 GPIO_FN(DV_D6),
1352 PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), 1356 GPIO_FN(DV_D5),
1353 PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), 1357 GPIO_FN(DV_D4),
1354 PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), 1358 GPIO_FN(DV_D3),
1355 PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), 1359 GPIO_FN(DV_D2),
1356 PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), 1360 GPIO_FN(DV_D1),
1357 PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), 1361 GPIO_FN(DV_D0),
1358 1362
1359 /* KEYSC */ 1363 /* KEYSC */
1360 PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), 1364 GPIO_FN(KEYIN0),
1361 PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), 1365 GPIO_FN(KEYIN1),
1362 PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), 1366 GPIO_FN(KEYIN2),
1363 PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), 1367 GPIO_FN(KEYIN3),
1364 PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), 1368 GPIO_FN(KEYIN4),
1365 PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), 1369 GPIO_FN(KEYOUT0),
1366 PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), 1370 GPIO_FN(KEYOUT1),
1367 PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), 1371 GPIO_FN(KEYOUT2),
1368 PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), 1372 GPIO_FN(KEYOUT3),
1369 PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), 1373 GPIO_FN(KEYOUT4_IN6),
1370 PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), 1374 GPIO_FN(KEYOUT5_IN5),
1371 1375
1372 /* MSIOF0 (PTF) */ 1376 /* MSIOF0 (PTF) */
1373 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TXD, MSIOF0_PTF_TXD_MARK), 1377 GPIO_FN(MSIOF0_PTF_TXD),
1374 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RXD, MSIOF0_PTF_RXD_MARK), 1378 GPIO_FN(MSIOF0_PTF_RXD),
1375 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_MCK, MSIOF0_PTF_MCK_MARK), 1379 GPIO_FN(MSIOF0_PTF_MCK),
1376 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSYNC, MSIOF0_PTF_TSYNC_MARK), 1380 GPIO_FN(MSIOF0_PTF_TSYNC),
1377 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_TSCK, MSIOF0_PTF_TSCK_MARK), 1381 GPIO_FN(MSIOF0_PTF_TSCK),
1378 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSYNC, MSIOF0_PTF_RSYNC_MARK), 1382 GPIO_FN(MSIOF0_PTF_RSYNC),
1379 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_RSCK, MSIOF0_PTF_RSCK_MARK), 1383 GPIO_FN(MSIOF0_PTF_RSCK),
1380 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS1, MSIOF0_PTF_SS1_MARK), 1384 GPIO_FN(MSIOF0_PTF_SS1),
1381 PINMUX_GPIO(GPIO_FN_MSIOF0_PTF_SS2, MSIOF0_PTF_SS2_MARK), 1385 GPIO_FN(MSIOF0_PTF_SS2),
1382 1386
1383 /* MSIOF0 (PTT+PTX) */ 1387 /* MSIOF0 (PTT+PTX) */
1384 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TXD, MSIOF0_PTT_TXD_MARK), 1388 GPIO_FN(MSIOF0_PTT_TXD),
1385 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RXD, MSIOF0_PTT_RXD_MARK), 1389 GPIO_FN(MSIOF0_PTT_RXD),
1386 PINMUX_GPIO(GPIO_FN_MSIOF0_PTX_MCK, MSIOF0_PTX_MCK_MARK), 1390 GPIO_FN(MSIOF0_PTX_MCK),
1387 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSYNC, MSIOF0_PTT_TSYNC_MARK), 1391 GPIO_FN(MSIOF0_PTT_TSYNC),
1388 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_TSCK, MSIOF0_PTT_TSCK_MARK), 1392 GPIO_FN(MSIOF0_PTT_TSCK),
1389 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSYNC, MSIOF0_PTT_RSYNC_MARK), 1393 GPIO_FN(MSIOF0_PTT_RSYNC),
1390 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_RSCK, MSIOF0_PTT_RSCK_MARK), 1394 GPIO_FN(MSIOF0_PTT_RSCK),
1391 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS1, MSIOF0_PTT_SS1_MARK), 1395 GPIO_FN(MSIOF0_PTT_SS1),
1392 PINMUX_GPIO(GPIO_FN_MSIOF0_PTT_SS2, MSIOF0_PTT_SS2_MARK), 1396 GPIO_FN(MSIOF0_PTT_SS2),
1393 1397
1394 /* MSIOF1 */ 1398 /* MSIOF1 */
1395 PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK), 1399 GPIO_FN(MSIOF1_TXD),
1396 PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK), 1400 GPIO_FN(MSIOF1_RXD),
1397 PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK), 1401 GPIO_FN(MSIOF1_MCK),
1398 PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK), 1402 GPIO_FN(MSIOF1_TSYNC),
1399 PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK), 1403 GPIO_FN(MSIOF1_TSCK),
1400 PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK), 1404 GPIO_FN(MSIOF1_RSYNC),
1401 PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK), 1405 GPIO_FN(MSIOF1_RSCK),
1402 PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK), 1406 GPIO_FN(MSIOF1_SS1),
1403 PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK), 1407 GPIO_FN(MSIOF1_SS2),
1404 1408
1405 /* TSIF */ 1409 /* TSIF */
1406 PINMUX_GPIO(GPIO_FN_TS0_SDAT, TS0_SDAT_MARK), 1410 GPIO_FN(TS0_SDAT),
1407 PINMUX_GPIO(GPIO_FN_TS0_SCK, TS0_SCK_MARK), 1411 GPIO_FN(TS0_SCK),
1408 PINMUX_GPIO(GPIO_FN_TS0_SDEN, TS0_SDEN_MARK), 1412 GPIO_FN(TS0_SDEN),
1409 PINMUX_GPIO(GPIO_FN_TS0_SPSYNC, TS0_SPSYNC_MARK), 1413 GPIO_FN(TS0_SPSYNC),
1410 1414
1411 /* FLCTL */ 1415 /* FLCTL */
1412 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), 1416 GPIO_FN(FCE),
1413 PINMUX_GPIO(GPIO_FN_NAF7, NAF7_MARK), 1417 GPIO_FN(NAF7),
1414 PINMUX_GPIO(GPIO_FN_NAF6, NAF6_MARK), 1418 GPIO_FN(NAF6),
1415 PINMUX_GPIO(GPIO_FN_NAF5, NAF5_MARK), 1419 GPIO_FN(NAF5),
1416 PINMUX_GPIO(GPIO_FN_NAF4, NAF4_MARK), 1420 GPIO_FN(NAF4),
1417 PINMUX_GPIO(GPIO_FN_NAF3, NAF3_MARK), 1421 GPIO_FN(NAF3),
1418 PINMUX_GPIO(GPIO_FN_NAF2, NAF2_MARK), 1422 GPIO_FN(NAF2),
1419 PINMUX_GPIO(GPIO_FN_NAF1, NAF1_MARK), 1423 GPIO_FN(NAF1),
1420 PINMUX_GPIO(GPIO_FN_NAF0, NAF0_MARK), 1424 GPIO_FN(NAF0),
1421 PINMUX_GPIO(GPIO_FN_FCDE, FCDE_MARK), 1425 GPIO_FN(FCDE),
1422 PINMUX_GPIO(GPIO_FN_FOE, FOE_MARK), 1426 GPIO_FN(FOE),
1423 PINMUX_GPIO(GPIO_FN_FSC, FSC_MARK), 1427 GPIO_FN(FSC),
1424 PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), 1428 GPIO_FN(FWE),
1425 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), 1429 GPIO_FN(FRB),
1426 1430
1427 /* DMAC */ 1431 /* DMAC */
1428 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), 1432 GPIO_FN(DACK1),
1429 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 1433 GPIO_FN(DREQ1),
1430 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), 1434 GPIO_FN(DACK0),
1431 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 1435 GPIO_FN(DREQ0),
1432 1436
1433 /* ADC */ 1437 /* ADC */
1434 PINMUX_GPIO(GPIO_FN_AN3, AN3_MARK), 1438 GPIO_FN(AN3),
1435 PINMUX_GPIO(GPIO_FN_AN2, AN2_MARK), 1439 GPIO_FN(AN2),
1436 PINMUX_GPIO(GPIO_FN_AN1, AN1_MARK), 1440 GPIO_FN(AN1),
1437 PINMUX_GPIO(GPIO_FN_AN0, AN0_MARK), 1441 GPIO_FN(AN0),
1438 PINMUX_GPIO(GPIO_FN_ADTRG, ADTRG_MARK), 1442 GPIO_FN(ADTRG),
1439 1443
1440 /* CPG */ 1444 /* CPG */
1441 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), 1445 GPIO_FN(STATUS0),
1442 PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), 1446 GPIO_FN(PDSTATUS),
1443 1447
1444 /* TPU */ 1448 /* TPU */
1445 PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK), 1449 GPIO_FN(TPUTO0),
1446 PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK), 1450 GPIO_FN(TPUTO1),
1447 PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK), 1451 GPIO_FN(TPUTO2),
1448 PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK), 1452 GPIO_FN(TPUTO3),
1449 1453
1450 /* BSC */ 1454 /* BSC */
1451 PINMUX_GPIO(GPIO_FN_D31, D31_MARK), 1455 GPIO_FN(D31),
1452 PINMUX_GPIO(GPIO_FN_D30, D30_MARK), 1456 GPIO_FN(D30),
1453 PINMUX_GPIO(GPIO_FN_D29, D29_MARK), 1457 GPIO_FN(D29),
1454 PINMUX_GPIO(GPIO_FN_D28, D28_MARK), 1458 GPIO_FN(D28),
1455 PINMUX_GPIO(GPIO_FN_D27, D27_MARK), 1459 GPIO_FN(D27),
1456 PINMUX_GPIO(GPIO_FN_D26, D26_MARK), 1460 GPIO_FN(D26),
1457 PINMUX_GPIO(GPIO_FN_D25, D25_MARK), 1461 GPIO_FN(D25),
1458 PINMUX_GPIO(GPIO_FN_D24, D24_MARK), 1462 GPIO_FN(D24),
1459 PINMUX_GPIO(GPIO_FN_D23, D23_MARK), 1463 GPIO_FN(D23),
1460 PINMUX_GPIO(GPIO_FN_D22, D22_MARK), 1464 GPIO_FN(D22),
1461 PINMUX_GPIO(GPIO_FN_D21, D21_MARK), 1465 GPIO_FN(D21),
1462 PINMUX_GPIO(GPIO_FN_D20, D20_MARK), 1466 GPIO_FN(D20),
1463 PINMUX_GPIO(GPIO_FN_D19, D19_MARK), 1467 GPIO_FN(D19),
1464 PINMUX_GPIO(GPIO_FN_D18, D18_MARK), 1468 GPIO_FN(D18),
1465 PINMUX_GPIO(GPIO_FN_D17, D17_MARK), 1469 GPIO_FN(D17),
1466 PINMUX_GPIO(GPIO_FN_D16, D16_MARK), 1470 GPIO_FN(D16),
1467 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 1471 GPIO_FN(IOIS16),
1468 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), 1472 GPIO_FN(WAIT),
1469 PINMUX_GPIO(GPIO_FN_BS, BS_MARK), 1473 GPIO_FN(BS),
1470 PINMUX_GPIO(GPIO_FN_A25, A25_MARK), 1474 GPIO_FN(A25),
1471 PINMUX_GPIO(GPIO_FN_A24, A24_MARK), 1475 GPIO_FN(A24),
1472 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 1476 GPIO_FN(A23),
1473 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 1477 GPIO_FN(A22),
1474 PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), 1478 GPIO_FN(CS6B_CE1B),
1475 PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), 1479 GPIO_FN(CS6A_CE2B),
1476 PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), 1480 GPIO_FN(CS5B_CE1A),
1477 PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK), 1481 GPIO_FN(CS5A_CE2A),
1478 PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK), 1482 GPIO_FN(WE3_ICIOWR),
1479 PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK), 1483 GPIO_FN(WE2_ICIORD),
1480 1484
1481 /* ATAPI */ 1485 /* ATAPI */
1482 PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK), 1486 GPIO_FN(IDED15),
1483 PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK), 1487 GPIO_FN(IDED14),
1484 PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK), 1488 GPIO_FN(IDED13),
1485 PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK), 1489 GPIO_FN(IDED12),
1486 PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK), 1490 GPIO_FN(IDED11),
1487 PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK), 1491 GPIO_FN(IDED10),
1488 PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK), 1492 GPIO_FN(IDED9),
1489 PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK), 1493 GPIO_FN(IDED8),
1490 PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK), 1494 GPIO_FN(IDED7),
1491 PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK), 1495 GPIO_FN(IDED6),
1492 PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK), 1496 GPIO_FN(IDED5),
1493 PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK), 1497 GPIO_FN(IDED4),
1494 PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK), 1498 GPIO_FN(IDED3),
1495 PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK), 1499 GPIO_FN(IDED2),
1496 PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK), 1500 GPIO_FN(IDED1),
1497 PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK), 1501 GPIO_FN(IDED0),
1498 PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK), 1502 GPIO_FN(DIRECTION),
1499 PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK), 1503 GPIO_FN(EXBUF_ENB),
1500 PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK), 1504 GPIO_FN(IDERST),
1501 PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK), 1505 GPIO_FN(IODACK),
1502 PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK), 1506 GPIO_FN(IODREQ),
1503 PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK), 1507 GPIO_FN(IDEIORDY),
1504 PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK), 1508 GPIO_FN(IDEINT),
1505 PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK), 1509 GPIO_FN(IDEIOWR),
1506 PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK), 1510 GPIO_FN(IDEIORD),
1507 PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK), 1511 GPIO_FN(IDECS1),
1508 PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK), 1512 GPIO_FN(IDECS0),
1509 PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK), 1513 GPIO_FN(IDEA2),
1510 PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK), 1514 GPIO_FN(IDEA1),
1511 PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK), 1515 GPIO_FN(IDEA0),
1512}; 1516};
1513 1517
1514static struct pinmux_cfg_reg pinmux_config_regs[] = { 1518static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1515 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { 1519 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
1516 PTA7_FN, PTA7_OUT, 0, PTA7_IN, 1520 PTA7_FN, PTA7_OUT, 0, PTA7_IN,
1517 PTA6_FN, PTA6_OUT, 0, PTA6_IN, 1521 PTA6_FN, PTA6_OUT, 0, PTA6_IN,
@@ -1785,7 +1789,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1785 {} 1789 {}
1786}; 1790};
1787 1791
1788static struct pinmux_data_reg pinmux_data_regs[] = { 1792static const struct pinmux_data_reg pinmux_data_regs[] = {
1789 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { 1793 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
1790 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, 1794 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
1791 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } 1795 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -1881,20 +1885,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1881 { }, 1885 { },
1882}; 1886};
1883 1887
1884struct sh_pfc_soc_info sh7723_pinmux_info = { 1888const struct sh_pfc_soc_info sh7723_pinmux_info = {
1885 .name = "sh7723_pfc", 1889 .name = "sh7723_pfc",
1886 .reserved_id = PINMUX_RESERVED,
1887 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1888 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 1890 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1889 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 1891 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1890 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 1892 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1891 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1892 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 1893 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1893 1894
1894 .first_gpio = GPIO_PTA7, 1895 .pins = pinmux_pins,
1895 .last_gpio = GPIO_FN_IDEA0, 1896 .nr_pins = ARRAY_SIZE(pinmux_pins),
1897 .func_gpios = pinmux_func_gpios,
1898 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
1896 1899
1897 .gpios = pinmux_gpios,
1898 .cfg_regs = pinmux_config_regs, 1900 .cfg_regs = pinmux_config_regs,
1899 .data_regs = pinmux_data_regs, 1901 .data_regs = pinmux_data_regs,
1900 1902
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
index 233fbf750b39..35e551609805 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
@@ -572,7 +572,7 @@ enum {
572 PINMUX_MARK_END, 572 PINMUX_MARK_END,
573}; 573};
574 574
575static pinmux_enum_t pinmux_data[] = { 575static const pinmux_enum_t pinmux_data[] = {
576 /* PTA GPIO */ 576 /* PTA GPIO */
577 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU), 577 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT, PTA7_IN_PU),
578 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU), 578 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT, PTA6_IN_PU),
@@ -1192,7 +1192,7 @@ static pinmux_enum_t pinmux_data[] = {
1192 PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN), 1192 PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN),
1193}; 1193};
1194 1194
1195static struct pinmux_gpio pinmux_gpios[] = { 1195static struct sh_pfc_pin pinmux_pins[] = {
1196 /* PTA */ 1196 /* PTA */
1197 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), 1197 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
1198 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), 1198 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -1418,372 +1418,376 @@ static struct pinmux_gpio pinmux_gpios[] = {
1418 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), 1418 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
1419 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), 1419 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
1420 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), 1420 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
1421};
1422
1423#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
1421 1424
1425static const struct pinmux_func pinmux_func_gpios[] = {
1422 /* BSC */ 1426 /* BSC */
1423 PINMUX_GPIO(GPIO_FN_D31, D31_MARK), 1427 GPIO_FN(D31),
1424 PINMUX_GPIO(GPIO_FN_D30, D30_MARK), 1428 GPIO_FN(D30),
1425 PINMUX_GPIO(GPIO_FN_D29, D29_MARK), 1429 GPIO_FN(D29),
1426 PINMUX_GPIO(GPIO_FN_D28, D28_MARK), 1430 GPIO_FN(D28),
1427 PINMUX_GPIO(GPIO_FN_D27, D27_MARK), 1431 GPIO_FN(D27),
1428 PINMUX_GPIO(GPIO_FN_D26, D26_MARK), 1432 GPIO_FN(D26),
1429 PINMUX_GPIO(GPIO_FN_D25, D25_MARK), 1433 GPIO_FN(D25),
1430 PINMUX_GPIO(GPIO_FN_D24, D24_MARK), 1434 GPIO_FN(D24),
1431 PINMUX_GPIO(GPIO_FN_D23, D23_MARK), 1435 GPIO_FN(D23),
1432 PINMUX_GPIO(GPIO_FN_D22, D22_MARK), 1436 GPIO_FN(D22),
1433 PINMUX_GPIO(GPIO_FN_D21, D21_MARK), 1437 GPIO_FN(D21),
1434 PINMUX_GPIO(GPIO_FN_D20, D20_MARK), 1438 GPIO_FN(D20),
1435 PINMUX_GPIO(GPIO_FN_D19, D19_MARK), 1439 GPIO_FN(D19),
1436 PINMUX_GPIO(GPIO_FN_D18, D18_MARK), 1440 GPIO_FN(D18),
1437 PINMUX_GPIO(GPIO_FN_D17, D17_MARK), 1441 GPIO_FN(D17),
1438 PINMUX_GPIO(GPIO_FN_D16, D16_MARK), 1442 GPIO_FN(D16),
1439 PINMUX_GPIO(GPIO_FN_D15, D15_MARK), 1443 GPIO_FN(D15),
1440 PINMUX_GPIO(GPIO_FN_D14, D14_MARK), 1444 GPIO_FN(D14),
1441 PINMUX_GPIO(GPIO_FN_D13, D13_MARK), 1445 GPIO_FN(D13),
1442 PINMUX_GPIO(GPIO_FN_D12, D12_MARK), 1446 GPIO_FN(D12),
1443 PINMUX_GPIO(GPIO_FN_D11, D11_MARK), 1447 GPIO_FN(D11),
1444 PINMUX_GPIO(GPIO_FN_D10, D10_MARK), 1448 GPIO_FN(D10),
1445 PINMUX_GPIO(GPIO_FN_D9, D9_MARK), 1449 GPIO_FN(D9),
1446 PINMUX_GPIO(GPIO_FN_D8, D8_MARK), 1450 GPIO_FN(D8),
1447 PINMUX_GPIO(GPIO_FN_D7, D7_MARK), 1451 GPIO_FN(D7),
1448 PINMUX_GPIO(GPIO_FN_D6, D6_MARK), 1452 GPIO_FN(D6),
1449 PINMUX_GPIO(GPIO_FN_D5, D5_MARK), 1453 GPIO_FN(D5),
1450 PINMUX_GPIO(GPIO_FN_D4, D4_MARK), 1454 GPIO_FN(D4),
1451 PINMUX_GPIO(GPIO_FN_D3, D3_MARK), 1455 GPIO_FN(D3),
1452 PINMUX_GPIO(GPIO_FN_D2, D2_MARK), 1456 GPIO_FN(D2),
1453 PINMUX_GPIO(GPIO_FN_D1, D1_MARK), 1457 GPIO_FN(D1),
1454 PINMUX_GPIO(GPIO_FN_D0, D0_MARK), 1458 GPIO_FN(D0),
1455 PINMUX_GPIO(GPIO_FN_A25, A25_MARK), 1459 GPIO_FN(A25),
1456 PINMUX_GPIO(GPIO_FN_A24, A24_MARK), 1460 GPIO_FN(A24),
1457 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 1461 GPIO_FN(A23),
1458 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 1462 GPIO_FN(A22),
1459 PINMUX_GPIO(GPIO_FN_CS6B_CE1B, CS6B_CE1B_MARK), 1463 GPIO_FN(CS6B_CE1B),
1460 PINMUX_GPIO(GPIO_FN_CS6A_CE2B, CS6A_CE2B_MARK), 1464 GPIO_FN(CS6A_CE2B),
1461 PINMUX_GPIO(GPIO_FN_CS5B_CE1A, CS5B_CE1A_MARK), 1465 GPIO_FN(CS5B_CE1A),
1462 PINMUX_GPIO(GPIO_FN_CS5A_CE2A, CS5A_CE2A_MARK), 1466 GPIO_FN(CS5A_CE2A),
1463 PINMUX_GPIO(GPIO_FN_WE3_ICIOWR, WE3_ICIOWR_MARK), 1467 GPIO_FN(WE3_ICIOWR),
1464 PINMUX_GPIO(GPIO_FN_WE2_ICIORD, WE2_ICIORD_MARK), 1468 GPIO_FN(WE2_ICIORD),
1465 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 1469 GPIO_FN(IOIS16),
1466 PINMUX_GPIO(GPIO_FN_WAIT, WAIT_MARK), 1470 GPIO_FN(WAIT),
1467 PINMUX_GPIO(GPIO_FN_BS, BS_MARK), 1471 GPIO_FN(BS),
1468 1472
1469 /* KEYSC */ 1473 /* KEYSC */
1470 PINMUX_GPIO(GPIO_FN_KEYOUT5_IN5, KEYOUT5_IN5_MARK), 1474 GPIO_FN(KEYOUT5_IN5),
1471 PINMUX_GPIO(GPIO_FN_KEYOUT4_IN6, KEYOUT4_IN6_MARK), 1475 GPIO_FN(KEYOUT4_IN6),
1472 PINMUX_GPIO(GPIO_FN_KEYIN4, KEYIN4_MARK), 1476 GPIO_FN(KEYIN4),
1473 PINMUX_GPIO(GPIO_FN_KEYIN3, KEYIN3_MARK), 1477 GPIO_FN(KEYIN3),
1474 PINMUX_GPIO(GPIO_FN_KEYIN2, KEYIN2_MARK), 1478 GPIO_FN(KEYIN2),
1475 PINMUX_GPIO(GPIO_FN_KEYIN1, KEYIN1_MARK), 1479 GPIO_FN(KEYIN1),
1476 PINMUX_GPIO(GPIO_FN_KEYIN0, KEYIN0_MARK), 1480 GPIO_FN(KEYIN0),
1477 PINMUX_GPIO(GPIO_FN_KEYOUT3, KEYOUT3_MARK), 1481 GPIO_FN(KEYOUT3),
1478 PINMUX_GPIO(GPIO_FN_KEYOUT2, KEYOUT2_MARK), 1482 GPIO_FN(KEYOUT2),
1479 PINMUX_GPIO(GPIO_FN_KEYOUT1, KEYOUT1_MARK), 1483 GPIO_FN(KEYOUT1),
1480 PINMUX_GPIO(GPIO_FN_KEYOUT0, KEYOUT0_MARK), 1484 GPIO_FN(KEYOUT0),
1481 1485
1482 /* ATAPI */ 1486 /* ATAPI */
1483 PINMUX_GPIO(GPIO_FN_IDED15, IDED15_MARK), 1487 GPIO_FN(IDED15),
1484 PINMUX_GPIO(GPIO_FN_IDED14, IDED14_MARK), 1488 GPIO_FN(IDED14),
1485 PINMUX_GPIO(GPIO_FN_IDED13, IDED13_MARK), 1489 GPIO_FN(IDED13),
1486 PINMUX_GPIO(GPIO_FN_IDED12, IDED12_MARK), 1490 GPIO_FN(IDED12),
1487 PINMUX_GPIO(GPIO_FN_IDED11, IDED11_MARK), 1491 GPIO_FN(IDED11),
1488 PINMUX_GPIO(GPIO_FN_IDED10, IDED10_MARK), 1492 GPIO_FN(IDED10),
1489 PINMUX_GPIO(GPIO_FN_IDED9, IDED9_MARK), 1493 GPIO_FN(IDED9),
1490 PINMUX_GPIO(GPIO_FN_IDED8, IDED8_MARK), 1494 GPIO_FN(IDED8),
1491 PINMUX_GPIO(GPIO_FN_IDED7, IDED7_MARK), 1495 GPIO_FN(IDED7),
1492 PINMUX_GPIO(GPIO_FN_IDED6, IDED6_MARK), 1496 GPIO_FN(IDED6),
1493 PINMUX_GPIO(GPIO_FN_IDED5, IDED5_MARK), 1497 GPIO_FN(IDED5),
1494 PINMUX_GPIO(GPIO_FN_IDED4, IDED4_MARK), 1498 GPIO_FN(IDED4),
1495 PINMUX_GPIO(GPIO_FN_IDED3, IDED3_MARK), 1499 GPIO_FN(IDED3),
1496 PINMUX_GPIO(GPIO_FN_IDED2, IDED2_MARK), 1500 GPIO_FN(IDED2),
1497 PINMUX_GPIO(GPIO_FN_IDED1, IDED1_MARK), 1501 GPIO_FN(IDED1),
1498 PINMUX_GPIO(GPIO_FN_IDED0, IDED0_MARK), 1502 GPIO_FN(IDED0),
1499 PINMUX_GPIO(GPIO_FN_IDEA2, IDEA2_MARK), 1503 GPIO_FN(IDEA2),
1500 PINMUX_GPIO(GPIO_FN_IDEA1, IDEA1_MARK), 1504 GPIO_FN(IDEA1),
1501 PINMUX_GPIO(GPIO_FN_IDEA0, IDEA0_MARK), 1505 GPIO_FN(IDEA0),
1502 PINMUX_GPIO(GPIO_FN_IDEIOWR, IDEIOWR_MARK), 1506 GPIO_FN(IDEIOWR),
1503 PINMUX_GPIO(GPIO_FN_IODREQ, IODREQ_MARK), 1507 GPIO_FN(IODREQ),
1504 PINMUX_GPIO(GPIO_FN_IDECS0, IDECS0_MARK), 1508 GPIO_FN(IDECS0),
1505 PINMUX_GPIO(GPIO_FN_IDECS1, IDECS1_MARK), 1509 GPIO_FN(IDECS1),
1506 PINMUX_GPIO(GPIO_FN_IDEIORD, IDEIORD_MARK), 1510 GPIO_FN(IDEIORD),
1507 PINMUX_GPIO(GPIO_FN_DIRECTION, DIRECTION_MARK), 1511 GPIO_FN(DIRECTION),
1508 PINMUX_GPIO(GPIO_FN_EXBUF_ENB, EXBUF_ENB_MARK), 1512 GPIO_FN(EXBUF_ENB),
1509 PINMUX_GPIO(GPIO_FN_IDERST, IDERST_MARK), 1513 GPIO_FN(IDERST),
1510 PINMUX_GPIO(GPIO_FN_IODACK, IODACK_MARK), 1514 GPIO_FN(IODACK),
1511 PINMUX_GPIO(GPIO_FN_IDEINT, IDEINT_MARK), 1515 GPIO_FN(IDEINT),
1512 PINMUX_GPIO(GPIO_FN_IDEIORDY, IDEIORDY_MARK), 1516 GPIO_FN(IDEIORDY),
1513 1517
1514 /* TPU */ 1518 /* TPU */
1515 PINMUX_GPIO(GPIO_FN_TPUTO3, TPUTO3_MARK), 1519 GPIO_FN(TPUTO3),
1516 PINMUX_GPIO(GPIO_FN_TPUTO2, TPUTO2_MARK), 1520 GPIO_FN(TPUTO2),
1517 PINMUX_GPIO(GPIO_FN_TPUTO1, TPUTO1_MARK), 1521 GPIO_FN(TPUTO1),
1518 PINMUX_GPIO(GPIO_FN_TPUTO0, TPUTO0_MARK), 1522 GPIO_FN(TPUTO0),
1519 PINMUX_GPIO(GPIO_FN_TPUTI3, TPUTI3_MARK), 1523 GPIO_FN(TPUTI3),
1520 PINMUX_GPIO(GPIO_FN_TPUTI2, TPUTI2_MARK), 1524 GPIO_FN(TPUTI2),
1521 1525
1522 /* LCDC */ 1526 /* LCDC */
1523 PINMUX_GPIO(GPIO_FN_LCDD23, LCDD23_MARK), 1527 GPIO_FN(LCDD23),
1524 PINMUX_GPIO(GPIO_FN_LCDD22, LCDD22_MARK), 1528 GPIO_FN(LCDD22),
1525 PINMUX_GPIO(GPIO_FN_LCDD21, LCDD21_MARK), 1529 GPIO_FN(LCDD21),
1526 PINMUX_GPIO(GPIO_FN_LCDD20, LCDD20_MARK), 1530 GPIO_FN(LCDD20),
1527 PINMUX_GPIO(GPIO_FN_LCDD19, LCDD19_MARK), 1531 GPIO_FN(LCDD19),
1528 PINMUX_GPIO(GPIO_FN_LCDD18, LCDD18_MARK), 1532 GPIO_FN(LCDD18),
1529 PINMUX_GPIO(GPIO_FN_LCDD17, LCDD17_MARK), 1533 GPIO_FN(LCDD17),
1530 PINMUX_GPIO(GPIO_FN_LCDD16, LCDD16_MARK), 1534 GPIO_FN(LCDD16),
1531 PINMUX_GPIO(GPIO_FN_LCDD15, LCDD15_MARK), 1535 GPIO_FN(LCDD15),
1532 PINMUX_GPIO(GPIO_FN_LCDD14, LCDD14_MARK), 1536 GPIO_FN(LCDD14),
1533 PINMUX_GPIO(GPIO_FN_LCDD13, LCDD13_MARK), 1537 GPIO_FN(LCDD13),
1534 PINMUX_GPIO(GPIO_FN_LCDD12, LCDD12_MARK), 1538 GPIO_FN(LCDD12),
1535 PINMUX_GPIO(GPIO_FN_LCDD11, LCDD11_MARK), 1539 GPIO_FN(LCDD11),
1536 PINMUX_GPIO(GPIO_FN_LCDD10, LCDD10_MARK), 1540 GPIO_FN(LCDD10),
1537 PINMUX_GPIO(GPIO_FN_LCDD9, LCDD9_MARK), 1541 GPIO_FN(LCDD9),
1538 PINMUX_GPIO(GPIO_FN_LCDD8, LCDD8_MARK), 1542 GPIO_FN(LCDD8),
1539 PINMUX_GPIO(GPIO_FN_LCDD7, LCDD7_MARK), 1543 GPIO_FN(LCDD7),
1540 PINMUX_GPIO(GPIO_FN_LCDD6, LCDD6_MARK), 1544 GPIO_FN(LCDD6),
1541 PINMUX_GPIO(GPIO_FN_LCDD5, LCDD5_MARK), 1545 GPIO_FN(LCDD5),
1542 PINMUX_GPIO(GPIO_FN_LCDD4, LCDD4_MARK), 1546 GPIO_FN(LCDD4),
1543 PINMUX_GPIO(GPIO_FN_LCDD3, LCDD3_MARK), 1547 GPIO_FN(LCDD3),
1544 PINMUX_GPIO(GPIO_FN_LCDD2, LCDD2_MARK), 1548 GPIO_FN(LCDD2),
1545 PINMUX_GPIO(GPIO_FN_LCDD1, LCDD1_MARK), 1549 GPIO_FN(LCDD1),
1546 PINMUX_GPIO(GPIO_FN_LCDD0, LCDD0_MARK), 1550 GPIO_FN(LCDD0),
1547 PINMUX_GPIO(GPIO_FN_LCDVSYN, LCDVSYN_MARK), 1551 GPIO_FN(LCDVSYN),
1548 PINMUX_GPIO(GPIO_FN_LCDDISP, LCDDISP_MARK), 1552 GPIO_FN(LCDDISP),
1549 PINMUX_GPIO(GPIO_FN_LCDRS, LCDRS_MARK), 1553 GPIO_FN(LCDRS),
1550 PINMUX_GPIO(GPIO_FN_LCDHSYN, LCDHSYN_MARK), 1554 GPIO_FN(LCDHSYN),
1551 PINMUX_GPIO(GPIO_FN_LCDCS, LCDCS_MARK), 1555 GPIO_FN(LCDCS),
1552 PINMUX_GPIO(GPIO_FN_LCDDON, LCDDON_MARK), 1556 GPIO_FN(LCDDON),
1553 PINMUX_GPIO(GPIO_FN_LCDDCK, LCDDCK_MARK), 1557 GPIO_FN(LCDDCK),
1554 PINMUX_GPIO(GPIO_FN_LCDWR, LCDWR_MARK), 1558 GPIO_FN(LCDWR),
1555 PINMUX_GPIO(GPIO_FN_LCDVEPWC, LCDVEPWC_MARK), 1559 GPIO_FN(LCDVEPWC),
1556 PINMUX_GPIO(GPIO_FN_LCDVCPWC, LCDVCPWC_MARK), 1560 GPIO_FN(LCDVCPWC),
1557 PINMUX_GPIO(GPIO_FN_LCDRD, LCDRD_MARK), 1561 GPIO_FN(LCDRD),
1558 PINMUX_GPIO(GPIO_FN_LCDLCLK, LCDLCLK_MARK), 1562 GPIO_FN(LCDLCLK),
1559 1563
1560 /* SCIF0 */ 1564 /* SCIF0 */
1561 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), 1565 GPIO_FN(SCIF0_TXD),
1562 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), 1566 GPIO_FN(SCIF0_RXD),
1563 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), 1567 GPIO_FN(SCIF0_SCK),
1564 1568
1565 /* SCIF1 */ 1569 /* SCIF1 */
1566 PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), 1570 GPIO_FN(SCIF1_SCK),
1567 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), 1571 GPIO_FN(SCIF1_RXD),
1568 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), 1572 GPIO_FN(SCIF1_TXD),
1569 1573
1570 /* SCIF2 */ 1574 /* SCIF2 */
1571 PINMUX_GPIO(GPIO_FN_SCIF2_L_TXD, SCIF2_L_TXD_MARK), 1575 GPIO_FN(SCIF2_L_TXD),
1572 PINMUX_GPIO(GPIO_FN_SCIF2_L_SCK, SCIF2_L_SCK_MARK), 1576 GPIO_FN(SCIF2_L_SCK),
1573 PINMUX_GPIO(GPIO_FN_SCIF2_L_RXD, SCIF2_L_RXD_MARK), 1577 GPIO_FN(SCIF2_L_RXD),
1574 PINMUX_GPIO(GPIO_FN_SCIF2_V_TXD, SCIF2_V_TXD_MARK), 1578 GPIO_FN(SCIF2_V_TXD),
1575 PINMUX_GPIO(GPIO_FN_SCIF2_V_SCK, SCIF2_V_SCK_MARK), 1579 GPIO_FN(SCIF2_V_SCK),
1576 PINMUX_GPIO(GPIO_FN_SCIF2_V_RXD, SCIF2_V_RXD_MARK), 1580 GPIO_FN(SCIF2_V_RXD),
1577 1581
1578 /* SCIF3 */ 1582 /* SCIF3 */
1579 PINMUX_GPIO(GPIO_FN_SCIF3_V_SCK, SCIF3_V_SCK_MARK), 1583 GPIO_FN(SCIF3_V_SCK),
1580 PINMUX_GPIO(GPIO_FN_SCIF3_V_RXD, SCIF3_V_RXD_MARK), 1584 GPIO_FN(SCIF3_V_RXD),
1581 PINMUX_GPIO(GPIO_FN_SCIF3_V_TXD, SCIF3_V_TXD_MARK), 1585 GPIO_FN(SCIF3_V_TXD),
1582 PINMUX_GPIO(GPIO_FN_SCIF3_V_CTS, SCIF3_V_CTS_MARK), 1586 GPIO_FN(SCIF3_V_CTS),
1583 PINMUX_GPIO(GPIO_FN_SCIF3_V_RTS, SCIF3_V_RTS_MARK), 1587 GPIO_FN(SCIF3_V_RTS),
1584 PINMUX_GPIO(GPIO_FN_SCIF3_I_SCK, SCIF3_I_SCK_MARK), 1588 GPIO_FN(SCIF3_I_SCK),
1585 PINMUX_GPIO(GPIO_FN_SCIF3_I_RXD, SCIF3_I_RXD_MARK), 1589 GPIO_FN(SCIF3_I_RXD),
1586 PINMUX_GPIO(GPIO_FN_SCIF3_I_TXD, SCIF3_I_TXD_MARK), 1590 GPIO_FN(SCIF3_I_TXD),
1587 PINMUX_GPIO(GPIO_FN_SCIF3_I_CTS, SCIF3_I_CTS_MARK), 1591 GPIO_FN(SCIF3_I_CTS),
1588 PINMUX_GPIO(GPIO_FN_SCIF3_I_RTS, SCIF3_I_RTS_MARK), 1592 GPIO_FN(SCIF3_I_RTS),
1589 1593
1590 /* SCIF4 */ 1594 /* SCIF4 */
1591 PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), 1595 GPIO_FN(SCIF4_SCK),
1592 PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), 1596 GPIO_FN(SCIF4_RXD),
1593 PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), 1597 GPIO_FN(SCIF4_TXD),
1594 1598
1595 /* SCIF5 */ 1599 /* SCIF5 */
1596 PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), 1600 GPIO_FN(SCIF5_SCK),
1597 PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), 1601 GPIO_FN(SCIF5_RXD),
1598 PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), 1602 GPIO_FN(SCIF5_TXD),
1599 1603
1600 /* FSI */ 1604 /* FSI */
1601 PINMUX_GPIO(GPIO_FN_FSIMCKB, FSIMCKB_MARK), 1605 GPIO_FN(FSIMCKB),
1602 PINMUX_GPIO(GPIO_FN_FSIMCKA, FSIMCKA_MARK), 1606 GPIO_FN(FSIMCKA),
1603 PINMUX_GPIO(GPIO_FN_FSIOASD, FSIOASD_MARK), 1607 GPIO_FN(FSIOASD),
1604 PINMUX_GPIO(GPIO_FN_FSIIABCK, FSIIABCK_MARK), 1608 GPIO_FN(FSIIABCK),
1605 PINMUX_GPIO(GPIO_FN_FSIIALRCK, FSIIALRCK_MARK), 1609 GPIO_FN(FSIIALRCK),
1606 PINMUX_GPIO(GPIO_FN_FSIOABCK, FSIOABCK_MARK), 1610 GPIO_FN(FSIOABCK),
1607 PINMUX_GPIO(GPIO_FN_FSIOALRCK, FSIOALRCK_MARK), 1611 GPIO_FN(FSIOALRCK),
1608 PINMUX_GPIO(GPIO_FN_CLKAUDIOAO, CLKAUDIOAO_MARK), 1612 GPIO_FN(CLKAUDIOAO),
1609 PINMUX_GPIO(GPIO_FN_FSIIBSD, FSIIBSD_MARK), 1613 GPIO_FN(FSIIBSD),
1610 PINMUX_GPIO(GPIO_FN_FSIOBSD, FSIOBSD_MARK), 1614 GPIO_FN(FSIOBSD),
1611 PINMUX_GPIO(GPIO_FN_FSIIBBCK, FSIIBBCK_MARK), 1615 GPIO_FN(FSIIBBCK),
1612 PINMUX_GPIO(GPIO_FN_FSIIBLRCK, FSIIBLRCK_MARK), 1616 GPIO_FN(FSIIBLRCK),
1613 PINMUX_GPIO(GPIO_FN_FSIOBBCK, FSIOBBCK_MARK), 1617 GPIO_FN(FSIOBBCK),
1614 PINMUX_GPIO(GPIO_FN_FSIOBLRCK, FSIOBLRCK_MARK), 1618 GPIO_FN(FSIOBLRCK),
1615 PINMUX_GPIO(GPIO_FN_CLKAUDIOBO, CLKAUDIOBO_MARK), 1619 GPIO_FN(CLKAUDIOBO),
1616 PINMUX_GPIO(GPIO_FN_FSIIASD, FSIIASD_MARK), 1620 GPIO_FN(FSIIASD),
1617 1621
1618 /* AUD */ 1622 /* AUD */
1619 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), 1623 GPIO_FN(AUDCK),
1620 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), 1624 GPIO_FN(AUDSYNC),
1621 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), 1625 GPIO_FN(AUDATA3),
1622 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), 1626 GPIO_FN(AUDATA2),
1623 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), 1627 GPIO_FN(AUDATA1),
1624 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), 1628 GPIO_FN(AUDATA0),
1625 1629
1626 /* VIO */ 1630 /* VIO */
1627 PINMUX_GPIO(GPIO_FN_VIO_CKO, VIO_CKO_MARK), 1631 GPIO_FN(VIO_CKO),
1628 1632
1629 /* VIO0 */ 1633 /* VIO0 */
1630 PINMUX_GPIO(GPIO_FN_VIO0_D15, VIO0_D15_MARK), 1634 GPIO_FN(VIO0_D15),
1631 PINMUX_GPIO(GPIO_FN_VIO0_D14, VIO0_D14_MARK), 1635 GPIO_FN(VIO0_D14),
1632 PINMUX_GPIO(GPIO_FN_VIO0_D13, VIO0_D13_MARK), 1636 GPIO_FN(VIO0_D13),
1633 PINMUX_GPIO(GPIO_FN_VIO0_D12, VIO0_D12_MARK), 1637 GPIO_FN(VIO0_D12),
1634 PINMUX_GPIO(GPIO_FN_VIO0_D11, VIO0_D11_MARK), 1638 GPIO_FN(VIO0_D11),
1635 PINMUX_GPIO(GPIO_FN_VIO0_D10, VIO0_D10_MARK), 1639 GPIO_FN(VIO0_D10),
1636 PINMUX_GPIO(GPIO_FN_VIO0_D9, VIO0_D9_MARK), 1640 GPIO_FN(VIO0_D9),
1637 PINMUX_GPIO(GPIO_FN_VIO0_D8, VIO0_D8_MARK), 1641 GPIO_FN(VIO0_D8),
1638 PINMUX_GPIO(GPIO_FN_VIO0_D7, VIO0_D7_MARK), 1642 GPIO_FN(VIO0_D7),
1639 PINMUX_GPIO(GPIO_FN_VIO0_D6, VIO0_D6_MARK), 1643 GPIO_FN(VIO0_D6),
1640 PINMUX_GPIO(GPIO_FN_VIO0_D5, VIO0_D5_MARK), 1644 GPIO_FN(VIO0_D5),
1641 PINMUX_GPIO(GPIO_FN_VIO0_D4, VIO0_D4_MARK), 1645 GPIO_FN(VIO0_D4),
1642 PINMUX_GPIO(GPIO_FN_VIO0_D3, VIO0_D3_MARK), 1646 GPIO_FN(VIO0_D3),
1643 PINMUX_GPIO(GPIO_FN_VIO0_D2, VIO0_D2_MARK), 1647 GPIO_FN(VIO0_D2),
1644 PINMUX_GPIO(GPIO_FN_VIO0_D1, VIO0_D1_MARK), 1648 GPIO_FN(VIO0_D1),
1645 PINMUX_GPIO(GPIO_FN_VIO0_D0, VIO0_D0_MARK), 1649 GPIO_FN(VIO0_D0),
1646 PINMUX_GPIO(GPIO_FN_VIO0_VD, VIO0_VD_MARK), 1650 GPIO_FN(VIO0_VD),
1647 PINMUX_GPIO(GPIO_FN_VIO0_CLK, VIO0_CLK_MARK), 1651 GPIO_FN(VIO0_CLK),
1648 PINMUX_GPIO(GPIO_FN_VIO0_FLD, VIO0_FLD_MARK), 1652 GPIO_FN(VIO0_FLD),
1649 PINMUX_GPIO(GPIO_FN_VIO0_HD, VIO0_HD_MARK), 1653 GPIO_FN(VIO0_HD),
1650 1654
1651 /* VIO1 */ 1655 /* VIO1 */
1652 PINMUX_GPIO(GPIO_FN_VIO1_D7, VIO1_D7_MARK), 1656 GPIO_FN(VIO1_D7),
1653 PINMUX_GPIO(GPIO_FN_VIO1_D6, VIO1_D6_MARK), 1657 GPIO_FN(VIO1_D6),
1654 PINMUX_GPIO(GPIO_FN_VIO1_D5, VIO1_D5_MARK), 1658 GPIO_FN(VIO1_D5),
1655 PINMUX_GPIO(GPIO_FN_VIO1_D4, VIO1_D4_MARK), 1659 GPIO_FN(VIO1_D4),
1656 PINMUX_GPIO(GPIO_FN_VIO1_D3, VIO1_D3_MARK), 1660 GPIO_FN(VIO1_D3),
1657 PINMUX_GPIO(GPIO_FN_VIO1_D2, VIO1_D2_MARK), 1661 GPIO_FN(VIO1_D2),
1658 PINMUX_GPIO(GPIO_FN_VIO1_D1, VIO1_D1_MARK), 1662 GPIO_FN(VIO1_D1),
1659 PINMUX_GPIO(GPIO_FN_VIO1_D0, VIO1_D0_MARK), 1663 GPIO_FN(VIO1_D0),
1660 PINMUX_GPIO(GPIO_FN_VIO1_FLD, VIO1_FLD_MARK), 1664 GPIO_FN(VIO1_FLD),
1661 PINMUX_GPIO(GPIO_FN_VIO1_HD, VIO1_HD_MARK), 1665 GPIO_FN(VIO1_HD),
1662 PINMUX_GPIO(GPIO_FN_VIO1_VD, VIO1_VD_MARK), 1666 GPIO_FN(VIO1_VD),
1663 PINMUX_GPIO(GPIO_FN_VIO1_CLK, VIO1_CLK_MARK), 1667 GPIO_FN(VIO1_CLK),
1664 1668
1665 /* Eth */ 1669 /* Eth */
1666 PINMUX_GPIO(GPIO_FN_RMII_RXD0, RMII_RXD0_MARK), 1670 GPIO_FN(RMII_RXD0),
1667 PINMUX_GPIO(GPIO_FN_RMII_RXD1, RMII_RXD1_MARK), 1671 GPIO_FN(RMII_RXD1),
1668 PINMUX_GPIO(GPIO_FN_RMII_TXD0, RMII_TXD0_MARK), 1672 GPIO_FN(RMII_TXD0),
1669 PINMUX_GPIO(GPIO_FN_RMII_TXD1, RMII_TXD1_MARK), 1673 GPIO_FN(RMII_TXD1),
1670 PINMUX_GPIO(GPIO_FN_RMII_REF_CLK, RMII_REF_CLK_MARK), 1674 GPIO_FN(RMII_REF_CLK),
1671 PINMUX_GPIO(GPIO_FN_RMII_TX_EN, RMII_TX_EN_MARK), 1675 GPIO_FN(RMII_TX_EN),
1672 PINMUX_GPIO(GPIO_FN_RMII_RX_ER, RMII_RX_ER_MARK), 1676 GPIO_FN(RMII_RX_ER),
1673 PINMUX_GPIO(GPIO_FN_RMII_CRS_DV, RMII_CRS_DV_MARK), 1677 GPIO_FN(RMII_CRS_DV),
1674 PINMUX_GPIO(GPIO_FN_LNKSTA, LNKSTA_MARK), 1678 GPIO_FN(LNKSTA),
1675 PINMUX_GPIO(GPIO_FN_MDIO, MDIO_MARK), 1679 GPIO_FN(MDIO),
1676 PINMUX_GPIO(GPIO_FN_MDC, MDC_MARK), 1680 GPIO_FN(MDC),
1677 1681
1678 /* System */ 1682 /* System */
1679 PINMUX_GPIO(GPIO_FN_PDSTATUS, PDSTATUS_MARK), 1683 GPIO_FN(PDSTATUS),
1680 PINMUX_GPIO(GPIO_FN_STATUS2, STATUS2_MARK), 1684 GPIO_FN(STATUS2),
1681 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), 1685 GPIO_FN(STATUS0),
1682 1686
1683 /* VOU */ 1687 /* VOU */
1684 PINMUX_GPIO(GPIO_FN_DV_D15, DV_D15_MARK), 1688 GPIO_FN(DV_D15),
1685 PINMUX_GPIO(GPIO_FN_DV_D14, DV_D14_MARK), 1689 GPIO_FN(DV_D14),
1686 PINMUX_GPIO(GPIO_FN_DV_D13, DV_D13_MARK), 1690 GPIO_FN(DV_D13),
1687 PINMUX_GPIO(GPIO_FN_DV_D12, DV_D12_MARK), 1691 GPIO_FN(DV_D12),
1688 PINMUX_GPIO(GPIO_FN_DV_D11, DV_D11_MARK), 1692 GPIO_FN(DV_D11),
1689 PINMUX_GPIO(GPIO_FN_DV_D10, DV_D10_MARK), 1693 GPIO_FN(DV_D10),
1690 PINMUX_GPIO(GPIO_FN_DV_D9, DV_D9_MARK), 1694 GPIO_FN(DV_D9),
1691 PINMUX_GPIO(GPIO_FN_DV_D8, DV_D8_MARK), 1695 GPIO_FN(DV_D8),
1692 PINMUX_GPIO(GPIO_FN_DV_D7, DV_D7_MARK), 1696 GPIO_FN(DV_D7),
1693 PINMUX_GPIO(GPIO_FN_DV_D6, DV_D6_MARK), 1697 GPIO_FN(DV_D6),
1694 PINMUX_GPIO(GPIO_FN_DV_D5, DV_D5_MARK), 1698 GPIO_FN(DV_D5),
1695 PINMUX_GPIO(GPIO_FN_DV_D4, DV_D4_MARK), 1699 GPIO_FN(DV_D4),
1696 PINMUX_GPIO(GPIO_FN_DV_D3, DV_D3_MARK), 1700 GPIO_FN(DV_D3),
1697 PINMUX_GPIO(GPIO_FN_DV_D2, DV_D2_MARK), 1701 GPIO_FN(DV_D2),
1698 PINMUX_GPIO(GPIO_FN_DV_D1, DV_D1_MARK), 1702 GPIO_FN(DV_D1),
1699 PINMUX_GPIO(GPIO_FN_DV_D0, DV_D0_MARK), 1703 GPIO_FN(DV_D0),
1700 PINMUX_GPIO(GPIO_FN_DV_CLKI, DV_CLKI_MARK), 1704 GPIO_FN(DV_CLKI),
1701 PINMUX_GPIO(GPIO_FN_DV_CLK, DV_CLK_MARK), 1705 GPIO_FN(DV_CLK),
1702 PINMUX_GPIO(GPIO_FN_DV_VSYNC, DV_VSYNC_MARK), 1706 GPIO_FN(DV_VSYNC),
1703 PINMUX_GPIO(GPIO_FN_DV_HSYNC, DV_HSYNC_MARK), 1707 GPIO_FN(DV_HSYNC),
1704 1708
1705 /* MSIOF0 */ 1709 /* MSIOF0 */
1706 PINMUX_GPIO(GPIO_FN_MSIOF0_RXD, MSIOF0_RXD_MARK), 1710 GPIO_FN(MSIOF0_RXD),
1707 PINMUX_GPIO(GPIO_FN_MSIOF0_TXD, MSIOF0_TXD_MARK), 1711 GPIO_FN(MSIOF0_TXD),
1708 PINMUX_GPIO(GPIO_FN_MSIOF0_MCK, MSIOF0_MCK_MARK), 1712 GPIO_FN(MSIOF0_MCK),
1709 PINMUX_GPIO(GPIO_FN_MSIOF0_TSCK, MSIOF0_TSCK_MARK), 1713 GPIO_FN(MSIOF0_TSCK),
1710 PINMUX_GPIO(GPIO_FN_MSIOF0_SS1, MSIOF0_SS1_MARK), 1714 GPIO_FN(MSIOF0_SS1),
1711 PINMUX_GPIO(GPIO_FN_MSIOF0_SS2, MSIOF0_SS2_MARK), 1715 GPIO_FN(MSIOF0_SS2),
1712 PINMUX_GPIO(GPIO_FN_MSIOF0_TSYNC, MSIOF0_TSYNC_MARK), 1716 GPIO_FN(MSIOF0_TSYNC),
1713 PINMUX_GPIO(GPIO_FN_MSIOF0_RSCK, MSIOF0_RSCK_MARK), 1717 GPIO_FN(MSIOF0_RSCK),
1714 PINMUX_GPIO(GPIO_FN_MSIOF0_RSYNC, MSIOF0_RSYNC_MARK), 1718 GPIO_FN(MSIOF0_RSYNC),
1715 1719
1716 /* MSIOF1 */ 1720 /* MSIOF1 */
1717 PINMUX_GPIO(GPIO_FN_MSIOF1_RXD, MSIOF1_RXD_MARK), 1721 GPIO_FN(MSIOF1_RXD),
1718 PINMUX_GPIO(GPIO_FN_MSIOF1_TXD, MSIOF1_TXD_MARK), 1722 GPIO_FN(MSIOF1_TXD),
1719 PINMUX_GPIO(GPIO_FN_MSIOF1_MCK, MSIOF1_MCK_MARK), 1723 GPIO_FN(MSIOF1_MCK),
1720 PINMUX_GPIO(GPIO_FN_MSIOF1_TSCK, MSIOF1_TSCK_MARK), 1724 GPIO_FN(MSIOF1_TSCK),
1721 PINMUX_GPIO(GPIO_FN_MSIOF1_SS1, MSIOF1_SS1_MARK), 1725 GPIO_FN(MSIOF1_SS1),
1722 PINMUX_GPIO(GPIO_FN_MSIOF1_SS2, MSIOF1_SS2_MARK), 1726 GPIO_FN(MSIOF1_SS2),
1723 PINMUX_GPIO(GPIO_FN_MSIOF1_TSYNC, MSIOF1_TSYNC_MARK), 1727 GPIO_FN(MSIOF1_TSYNC),
1724 PINMUX_GPIO(GPIO_FN_MSIOF1_RSCK, MSIOF1_RSCK_MARK), 1728 GPIO_FN(MSIOF1_RSCK),
1725 PINMUX_GPIO(GPIO_FN_MSIOF1_RSYNC, MSIOF1_RSYNC_MARK), 1729 GPIO_FN(MSIOF1_RSYNC),
1726 1730
1727 /* DMAC */ 1731 /* DMAC */
1728 PINMUX_GPIO(GPIO_FN_DMAC_DACK0, DMAC_DACK0_MARK), 1732 GPIO_FN(DMAC_DACK0),
1729 PINMUX_GPIO(GPIO_FN_DMAC_DREQ0, DMAC_DREQ0_MARK), 1733 GPIO_FN(DMAC_DREQ0),
1730 PINMUX_GPIO(GPIO_FN_DMAC_DACK1, DMAC_DACK1_MARK), 1734 GPIO_FN(DMAC_DACK1),
1731 PINMUX_GPIO(GPIO_FN_DMAC_DREQ1, DMAC_DREQ1_MARK), 1735 GPIO_FN(DMAC_DREQ1),
1732 1736
1733 /* SDHI0 */ 1737 /* SDHI0 */
1734 PINMUX_GPIO(GPIO_FN_SDHI0CD, SDHI0CD_MARK), 1738 GPIO_FN(SDHI0CD),
1735 PINMUX_GPIO(GPIO_FN_SDHI0WP, SDHI0WP_MARK), 1739 GPIO_FN(SDHI0WP),
1736 PINMUX_GPIO(GPIO_FN_SDHI0CMD, SDHI0CMD_MARK), 1740 GPIO_FN(SDHI0CMD),
1737 PINMUX_GPIO(GPIO_FN_SDHI0CLK, SDHI0CLK_MARK), 1741 GPIO_FN(SDHI0CLK),
1738 PINMUX_GPIO(GPIO_FN_SDHI0D3, SDHI0D3_MARK), 1742 GPIO_FN(SDHI0D3),
1739 PINMUX_GPIO(GPIO_FN_SDHI0D2, SDHI0D2_MARK), 1743 GPIO_FN(SDHI0D2),
1740 PINMUX_GPIO(GPIO_FN_SDHI0D1, SDHI0D1_MARK), 1744 GPIO_FN(SDHI0D1),
1741 PINMUX_GPIO(GPIO_FN_SDHI0D0, SDHI0D0_MARK), 1745 GPIO_FN(SDHI0D0),
1742 1746
1743 /* SDHI1 */ 1747 /* SDHI1 */
1744 PINMUX_GPIO(GPIO_FN_SDHI1CD, SDHI1CD_MARK), 1748 GPIO_FN(SDHI1CD),
1745 PINMUX_GPIO(GPIO_FN_SDHI1WP, SDHI1WP_MARK), 1749 GPIO_FN(SDHI1WP),
1746 PINMUX_GPIO(GPIO_FN_SDHI1CMD, SDHI1CMD_MARK), 1750 GPIO_FN(SDHI1CMD),
1747 PINMUX_GPIO(GPIO_FN_SDHI1CLK, SDHI1CLK_MARK), 1751 GPIO_FN(SDHI1CLK),
1748 PINMUX_GPIO(GPIO_FN_SDHI1D3, SDHI1D3_MARK), 1752 GPIO_FN(SDHI1D3),
1749 PINMUX_GPIO(GPIO_FN_SDHI1D2, SDHI1D2_MARK), 1753 GPIO_FN(SDHI1D2),
1750 PINMUX_GPIO(GPIO_FN_SDHI1D1, SDHI1D1_MARK), 1754 GPIO_FN(SDHI1D1),
1751 PINMUX_GPIO(GPIO_FN_SDHI1D0, SDHI1D0_MARK), 1755 GPIO_FN(SDHI1D0),
1752 1756
1753 /* MMC */ 1757 /* MMC */
1754 PINMUX_GPIO(GPIO_FN_MMC_D7, MMC_D7_MARK), 1758 GPIO_FN(MMC_D7),
1755 PINMUX_GPIO(GPIO_FN_MMC_D6, MMC_D6_MARK), 1759 GPIO_FN(MMC_D6),
1756 PINMUX_GPIO(GPIO_FN_MMC_D5, MMC_D5_MARK), 1760 GPIO_FN(MMC_D5),
1757 PINMUX_GPIO(GPIO_FN_MMC_D4, MMC_D4_MARK), 1761 GPIO_FN(MMC_D4),
1758 PINMUX_GPIO(GPIO_FN_MMC_D3, MMC_D3_MARK), 1762 GPIO_FN(MMC_D3),
1759 PINMUX_GPIO(GPIO_FN_MMC_D2, MMC_D2_MARK), 1763 GPIO_FN(MMC_D2),
1760 PINMUX_GPIO(GPIO_FN_MMC_D1, MMC_D1_MARK), 1764 GPIO_FN(MMC_D1),
1761 PINMUX_GPIO(GPIO_FN_MMC_D0, MMC_D0_MARK), 1765 GPIO_FN(MMC_D0),
1762 PINMUX_GPIO(GPIO_FN_MMC_CLK, MMC_CLK_MARK), 1766 GPIO_FN(MMC_CLK),
1763 PINMUX_GPIO(GPIO_FN_MMC_CMD, MMC_CMD_MARK), 1767 GPIO_FN(MMC_CMD),
1764 1768
1765 /* IrDA */ 1769 /* IrDA */
1766 PINMUX_GPIO(GPIO_FN_IRDA_OUT, IRDA_OUT_MARK), 1770 GPIO_FN(IRDA_OUT),
1767 PINMUX_GPIO(GPIO_FN_IRDA_IN, IRDA_IN_MARK), 1771 GPIO_FN(IRDA_IN),
1768 1772
1769 /* TSIF */ 1773 /* TSIF */
1770 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDAT, TSIF_TS0_SDAT_MARK), 1774 GPIO_FN(TSIF_TS0_SDAT),
1771 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SCK, TSIF_TS0_SCK_MARK), 1775 GPIO_FN(TSIF_TS0_SCK),
1772 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SDEN, TSIF_TS0_SDEN_MARK), 1776 GPIO_FN(TSIF_TS0_SDEN),
1773 PINMUX_GPIO(GPIO_FN_TSIF_TS0_SPSYNC, TSIF_TS0_SPSYNC_MARK), 1777 GPIO_FN(TSIF_TS0_SPSYNC),
1774 1778
1775 /* IRQ */ 1779 /* IRQ */
1776 PINMUX_GPIO(GPIO_FN_INTC_IRQ7, INTC_IRQ7_MARK), 1780 GPIO_FN(INTC_IRQ7),
1777 PINMUX_GPIO(GPIO_FN_INTC_IRQ6, INTC_IRQ6_MARK), 1781 GPIO_FN(INTC_IRQ6),
1778 PINMUX_GPIO(GPIO_FN_INTC_IRQ5, INTC_IRQ5_MARK), 1782 GPIO_FN(INTC_IRQ5),
1779 PINMUX_GPIO(GPIO_FN_INTC_IRQ4, INTC_IRQ4_MARK), 1783 GPIO_FN(INTC_IRQ4),
1780 PINMUX_GPIO(GPIO_FN_INTC_IRQ3, INTC_IRQ3_MARK), 1784 GPIO_FN(INTC_IRQ3),
1781 PINMUX_GPIO(GPIO_FN_INTC_IRQ2, INTC_IRQ2_MARK), 1785 GPIO_FN(INTC_IRQ2),
1782 PINMUX_GPIO(GPIO_FN_INTC_IRQ1, INTC_IRQ1_MARK), 1786 GPIO_FN(INTC_IRQ1),
1783 PINMUX_GPIO(GPIO_FN_INTC_IRQ0, INTC_IRQ0_MARK), 1787 GPIO_FN(INTC_IRQ0),
1784}; 1788};
1785 1789
1786static struct pinmux_cfg_reg pinmux_config_regs[] = { 1790static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1787 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) { 1791 { PINMUX_CFG_REG("PACR", 0xa4050100, 16, 2) {
1788 PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN, 1792 PTA7_FN, PTA7_OUT, PTA7_IN_PU, PTA7_IN,
1789 PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN, 1793 PTA6_FN, PTA6_OUT, PTA6_IN_PU, PTA6_IN,
@@ -2107,7 +2111,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2107 {} 2111 {}
2108}; 2112};
2109 2113
2110static struct pinmux_data_reg pinmux_data_regs[] = { 2114static const struct pinmux_data_reg pinmux_data_regs[] = {
2111 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) { 2115 { PINMUX_DATA_REG("PADR", 0xa4050120, 8) {
2112 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, 2116 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
2113 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } 2117 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -2203,20 +2207,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2203 { }, 2207 { },
2204}; 2208};
2205 2209
2206struct sh_pfc_soc_info sh7724_pinmux_info = { 2210const struct sh_pfc_soc_info sh7724_pinmux_info = {
2207 .name = "sh7724_pfc", 2211 .name = "sh7724_pfc",
2208 .reserved_id = PINMUX_RESERVED,
2209 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2210 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 2212 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2211 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 2213 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
2212 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 2214 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2213 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2214 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2215 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2215 2216
2216 .first_gpio = GPIO_PTA7, 2217 .pins = pinmux_pins,
2217 .last_gpio = GPIO_FN_INTC_IRQ0, 2218 .nr_pins = ARRAY_SIZE(pinmux_pins),
2219 .func_gpios = pinmux_func_gpios,
2220 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2218 2221
2219 .gpios = pinmux_gpios,
2220 .cfg_regs = pinmux_config_regs, 2222 .cfg_regs = pinmux_config_regs,
2221 .data_regs = pinmux_data_regs, 2223 .data_regs = pinmux_data_regs,
2222 2224
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
index 23d76d262c32..2fd5b7d4cb94 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -14,11 +14,6 @@
14 14
15#include "sh_pfc.h" 15#include "sh_pfc.h"
16 16
17#define CPU_32_PORT(fn, pfx, sfx) \
18 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
19 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
20 PORT_1(fn, pfx##31, sfx)
21
22#define CPU_32_PORT5(fn, pfx, sfx) \ 17#define CPU_32_PORT5(fn, pfx, sfx) \
23 PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \ 18 PORT_1(fn, pfx##0, sfx), PORT_1(fn, pfx##1, sfx), \
24 PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \ 19 PORT_1(fn, pfx##2, sfx), PORT_1(fn, pfx##3, sfx), \
@@ -29,11 +24,11 @@
29 24
30/* GPSR0 - GPSR5 */ 25/* GPSR0 - GPSR5 */
31#define CPU_ALL_PORT(fn, pfx, sfx) \ 26#define CPU_ALL_PORT(fn, pfx, sfx) \
32 CPU_32_PORT(fn, pfx##_0_, sfx), \ 27 PORT_32(fn, pfx##_0_, sfx), \
33 CPU_32_PORT(fn, pfx##_1_, sfx), \ 28 PORT_32(fn, pfx##_1_, sfx), \
34 CPU_32_PORT(fn, pfx##_2_, sfx), \ 29 PORT_32(fn, pfx##_2_, sfx), \
35 CPU_32_PORT(fn, pfx##_3_, sfx), \ 30 PORT_32(fn, pfx##_3_, sfx), \
36 CPU_32_PORT(fn, pfx##_4_, sfx), \ 31 PORT_32(fn, pfx##_4_, sfx), \
37 CPU_32_PORT5(fn, pfx##_5_, sfx) 32 CPU_32_PORT5(fn, pfx##_5_, sfx)
38 33
39#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) 34#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA)
@@ -47,20 +42,8 @@
47#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) 42#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused)
48#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) 43#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused)
49 44
50#define PORT_10_REV(fn, pfx, sfx) \ 45#define GP_INOUTSEL(bank) PORT_32_REV(_GP_INOUTSEL, _##bank##_, unused)
51 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ 46#define GP_INDT(bank) PORT_32_REV(_GP_INDT, _##bank##_, unused)
52 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
53 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
54 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
55 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
56
57#define CPU_32_PORT_REV(fn, pfx, sfx) \
58 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
59 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
60 PORT_10_REV(fn, pfx, sfx)
61
62#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused)
63#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused)
64 47
65#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) 48#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
66#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ 49#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
@@ -609,7 +592,7 @@ enum {
609 PINMUX_MARK_END, 592 PINMUX_MARK_END,
610}; 593};
611 594
612static pinmux_enum_t pinmux_data[] = { 595static const pinmux_enum_t pinmux_data[] = {
613 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 596 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
614 597
615 PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT), 598 PINMUX_DATA(CLKOUT_MARK, FN_CLKOUT),
@@ -1384,9 +1367,13 @@ static pinmux_enum_t pinmux_data[] = {
1384 PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT), 1367 PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT),
1385}; 1368};
1386 1369
1387static struct pinmux_gpio pinmux_gpios[] = { 1370static struct sh_pfc_pin pinmux_pins[] = {
1388 PINMUX_GPIO_GP_ALL(), 1371 PINMUX_GPIO_GP_ALL(),
1372};
1373
1374#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
1389 1375
1376static const struct pinmux_func pinmux_func_gpios[] = {
1390 GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0), 1377 GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0),
1391 GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1), 1378 GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1),
1392 GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0), 1379 GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0),
@@ -1665,7 +1652,7 @@ static struct pinmux_gpio pinmux_gpios[] = {
1665 GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C), 1652 GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C),
1666}; 1653};
1667 1654
1668static struct pinmux_cfg_reg pinmux_config_regs[] = { 1655static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1669 { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) { 1656 { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) {
1670 GP_0_31_FN, FN_IP2_2_0, 1657 GP_0_31_FN, FN_IP2_2_0,
1671 GP_0_30_FN, FN_IP1_31_29, 1658 GP_0_30_FN, FN_IP1_31_29,
@@ -2434,7 +2421,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2434 { }, 2421 { },
2435}; 2422};
2436 2423
2437static struct pinmux_data_reg pinmux_data_regs[] = { 2424static const struct pinmux_data_reg pinmux_data_regs[] = {
2438 /* GPIO 0 - 5*/ 2425 /* GPIO 0 - 5*/
2439 { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } }, 2426 { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } },
2440 { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } }, 2427 { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } },
@@ -2451,22 +2438,20 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2451 { }, 2438 { },
2452}; 2439};
2453 2440
2454struct sh_pfc_soc_info sh7734_pinmux_info = { 2441const struct sh_pfc_soc_info sh7734_pinmux_info = {
2455 .name = "sh7734_pfc", 2442 .name = "sh7734_pfc",
2456 2443
2457 .unlock_reg = 0xFFFC0000, 2444 .unlock_reg = 0xFFFC0000,
2458 2445
2459 .reserved_id = PINMUX_RESERVED,
2460 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2461 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 2446 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2462 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 2447 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2463 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2464 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2448 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2465 2449
2466 .first_gpio = GPIO_GP_0_0, 2450 .pins = pinmux_pins,
2467 .last_gpio = GPIO_FN_ST_CLKOUT, 2451 .nr_pins = ARRAY_SIZE(pinmux_pins),
2452 .func_gpios = pinmux_func_gpios,
2453 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2468 2454
2469 .gpios = pinmux_gpios,
2470 .cfg_regs = pinmux_config_regs, 2455 .cfg_regs = pinmux_config_regs,
2471 .data_regs = pinmux_data_regs, 2456 .data_regs = pinmux_data_regs,
2472 2457
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
index 5ed74cd0ba99..e074230e6243 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
@@ -526,7 +526,7 @@ enum {
526 PINMUX_MARK_END, 526 PINMUX_MARK_END,
527}; 527};
528 528
529static pinmux_enum_t pinmux_data[] = { 529static const pinmux_enum_t pinmux_data[] = {
530 /* PTA GPIO */ 530 /* PTA GPIO */
531 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT), 531 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
532 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT), 532 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
@@ -1114,7 +1114,7 @@ static pinmux_enum_t pinmux_data[] = {
1114 PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN), 1114 PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN),
1115}; 1115};
1116 1116
1117static struct pinmux_gpio pinmux_gpios[] = { 1117static struct sh_pfc_pin pinmux_pins[] = {
1118 /* PTA */ 1118 /* PTA */
1119 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA), 1119 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
1120 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA), 1120 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
@@ -1370,359 +1370,363 @@ static struct pinmux_gpio pinmux_gpios[] = {
1370 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA), 1370 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
1371 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA), 1371 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
1372 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA), 1372 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
1373};
1374
1375#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
1373 1376
1377static const struct pinmux_func pinmux_func_gpios[] = {
1374 /* PTA (mobule: LBSC, RGMII) */ 1378 /* PTA (mobule: LBSC, RGMII) */
1375 PINMUX_GPIO(GPIO_FN_BS, BS_MARK), 1379 GPIO_FN(BS),
1376 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK), 1380 GPIO_FN(RDWR),
1377 PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK), 1381 GPIO_FN(WE1),
1378 PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK), 1382 GPIO_FN(RDY),
1379 PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK), 1383 GPIO_FN(ET0_MDC),
1380 PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDIO_MARK), 1384 GPIO_FN(ET0_MDIO),
1381 PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK), 1385 GPIO_FN(ET1_MDC),
1382 PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDIO_MARK), 1386 GPIO_FN(ET1_MDIO),
1383 1387
1384 /* PTB (mobule: INTC, ONFI, TMU) */ 1388 /* PTB (mobule: INTC, ONFI, TMU) */
1385 PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK), 1389 GPIO_FN(IRQ15),
1386 PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK), 1390 GPIO_FN(IRQ14),
1387 PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK), 1391 GPIO_FN(IRQ13),
1388 PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK), 1392 GPIO_FN(IRQ12),
1389 PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK), 1393 GPIO_FN(IRQ11),
1390 PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK), 1394 GPIO_FN(IRQ10),
1391 PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK), 1395 GPIO_FN(IRQ9),
1392 PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK), 1396 GPIO_FN(IRQ8),
1393 PINMUX_GPIO(GPIO_FN_ON_NRE, ON_NRE_MARK), 1397 GPIO_FN(ON_NRE),
1394 PINMUX_GPIO(GPIO_FN_ON_NWE, ON_NWE_MARK), 1398 GPIO_FN(ON_NWE),
1395 PINMUX_GPIO(GPIO_FN_ON_NWP, ON_NWP_MARK), 1399 GPIO_FN(ON_NWP),
1396 PINMUX_GPIO(GPIO_FN_ON_NCE0, ON_NCE0_MARK), 1400 GPIO_FN(ON_NCE0),
1397 PINMUX_GPIO(GPIO_FN_ON_R_B0, ON_R_B0_MARK), 1401 GPIO_FN(ON_R_B0),
1398 PINMUX_GPIO(GPIO_FN_ON_ALE, ON_ALE_MARK), 1402 GPIO_FN(ON_ALE),
1399 PINMUX_GPIO(GPIO_FN_ON_CLE, ON_CLE_MARK), 1403 GPIO_FN(ON_CLE),
1400 PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), 1404 GPIO_FN(TCLK),
1401 1405
1402 /* PTC (mobule: IRQ, PWMU) */ 1406 /* PTC (mobule: IRQ, PWMU) */
1403 PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK), 1407 GPIO_FN(IRQ7),
1404 PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK), 1408 GPIO_FN(IRQ6),
1405 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK), 1409 GPIO_FN(IRQ5),
1406 PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK), 1410 GPIO_FN(IRQ4),
1407 PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), 1411 GPIO_FN(IRQ3),
1408 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), 1412 GPIO_FN(IRQ2),
1409 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), 1413 GPIO_FN(IRQ1),
1410 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), 1414 GPIO_FN(IRQ0),
1411 PINMUX_GPIO(GPIO_FN_PWMU0, PWMU0_MARK), 1415 GPIO_FN(PWMU0),
1412 PINMUX_GPIO(GPIO_FN_PWMU1, PWMU1_MARK), 1416 GPIO_FN(PWMU1),
1413 PINMUX_GPIO(GPIO_FN_PWMU2, PWMU2_MARK), 1417 GPIO_FN(PWMU2),
1414 PINMUX_GPIO(GPIO_FN_PWMU3, PWMU3_MARK), 1418 GPIO_FN(PWMU3),
1415 PINMUX_GPIO(GPIO_FN_PWMU4, PWMU4_MARK), 1419 GPIO_FN(PWMU4),
1416 PINMUX_GPIO(GPIO_FN_PWMU5, PWMU5_MARK), 1420 GPIO_FN(PWMU5),
1417 1421
1418 /* PTD (mobule: SPI0, DMAC) */ 1422 /* PTD (mobule: SPI0, DMAC) */
1419 PINMUX_GPIO(GPIO_FN_SP0_MOSI, SP0_MOSI_MARK), 1423 GPIO_FN(SP0_MOSI),
1420 PINMUX_GPIO(GPIO_FN_SP0_MISO, SP0_MISO_MARK), 1424 GPIO_FN(SP0_MISO),
1421 PINMUX_GPIO(GPIO_FN_SP0_SCK, SP0_SCK_MARK), 1425 GPIO_FN(SP0_SCK),
1422 PINMUX_GPIO(GPIO_FN_SP0_SCK_FB, SP0_SCK_FB_MARK), 1426 GPIO_FN(SP0_SCK_FB),
1423 PINMUX_GPIO(GPIO_FN_SP0_SS0, SP0_SS0_MARK), 1427 GPIO_FN(SP0_SS0),
1424 PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK), 1428 GPIO_FN(SP0_SS1),
1425 PINMUX_GPIO(GPIO_FN_SP0_SS2, SP0_SS2_MARK), 1429 GPIO_FN(SP0_SS2),
1426 PINMUX_GPIO(GPIO_FN_SP0_SS3, SP0_SS3_MARK), 1430 GPIO_FN(SP0_SS3),
1427 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 1431 GPIO_FN(DREQ0),
1428 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), 1432 GPIO_FN(DACK0),
1429 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK), 1433 GPIO_FN(TEND0),
1430 1434
1431 /* PTE (mobule: RMII) */ 1435 /* PTE (mobule: RMII) */
1432 PINMUX_GPIO(GPIO_FN_RMII0_CRS_DV, RMII0_CRS_DV_MARK), 1436 GPIO_FN(RMII0_CRS_DV),
1433 PINMUX_GPIO(GPIO_FN_RMII0_TXD1, RMII0_TXD1_MARK), 1437 GPIO_FN(RMII0_TXD1),
1434 PINMUX_GPIO(GPIO_FN_RMII0_TXD0, RMII0_TXD0_MARK), 1438 GPIO_FN(RMII0_TXD0),
1435 PINMUX_GPIO(GPIO_FN_RMII0_TXEN, RMII0_TXEN_MARK), 1439 GPIO_FN(RMII0_TXEN),
1436 PINMUX_GPIO(GPIO_FN_RMII0_REFCLK, RMII0_REFCLK_MARK), 1440 GPIO_FN(RMII0_REFCLK),
1437 PINMUX_GPIO(GPIO_FN_RMII0_RXD1, RMII0_RXD1_MARK), 1441 GPIO_FN(RMII0_RXD1),
1438 PINMUX_GPIO(GPIO_FN_RMII0_RXD0, RMII0_RXD0_MARK), 1442 GPIO_FN(RMII0_RXD0),
1439 PINMUX_GPIO(GPIO_FN_RMII0_RX_ER, RMII0_RX_ER_MARK), 1443 GPIO_FN(RMII0_RX_ER),
1440 1444
1441 /* PTF (mobule: RMII, SerMux) */ 1445 /* PTF (mobule: RMII, SerMux) */
1442 PINMUX_GPIO(GPIO_FN_RMII1_CRS_DV, RMII1_CRS_DV_MARK), 1446 GPIO_FN(RMII1_CRS_DV),
1443 PINMUX_GPIO(GPIO_FN_RMII1_TXD1, RMII1_TXD1_MARK), 1447 GPIO_FN(RMII1_TXD1),
1444 PINMUX_GPIO(GPIO_FN_RMII1_TXD0, RMII1_TXD0_MARK), 1448 GPIO_FN(RMII1_TXD0),
1445 PINMUX_GPIO(GPIO_FN_RMII1_TXEN, RMII1_TXEN_MARK), 1449 GPIO_FN(RMII1_TXEN),
1446 PINMUX_GPIO(GPIO_FN_RMII1_REFCLK, RMII1_REFCLK_MARK), 1450 GPIO_FN(RMII1_REFCLK),
1447 PINMUX_GPIO(GPIO_FN_RMII1_RXD1, RMII1_RXD1_MARK), 1451 GPIO_FN(RMII1_RXD1),
1448 PINMUX_GPIO(GPIO_FN_RMII1_RXD0, RMII1_RXD0_MARK), 1452 GPIO_FN(RMII1_RXD0),
1449 PINMUX_GPIO(GPIO_FN_RMII1_RX_ER, RMII1_RX_ER_MARK), 1453 GPIO_FN(RMII1_RX_ER),
1450 PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK), 1454 GPIO_FN(RAC_RI),
1451 1455
1452 /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */ 1456 /* PTG (mobule: system, LBSC, LPC, WDT, LPC, eMMC) */
1453 PINMUX_GPIO(GPIO_FN_BOOTFMS, BOOTFMS_MARK), 1457 GPIO_FN(BOOTFMS),
1454 PINMUX_GPIO(GPIO_FN_BOOTWP, BOOTWP_MARK), 1458 GPIO_FN(BOOTWP),
1455 PINMUX_GPIO(GPIO_FN_A25, A25_MARK), 1459 GPIO_FN(A25),
1456 PINMUX_GPIO(GPIO_FN_A24, A24_MARK), 1460 GPIO_FN(A24),
1457 PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK), 1461 GPIO_FN(SERIRQ),
1458 PINMUX_GPIO(GPIO_FN_WDTOVF, WDTOVF_MARK), 1462 GPIO_FN(WDTOVF),
1459 PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK), 1463 GPIO_FN(LPCPD),
1460 PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK), 1464 GPIO_FN(LDRQ),
1461 PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK), 1465 GPIO_FN(MMCCLK),
1462 PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK), 1466 GPIO_FN(MMCCMD),
1463 1467
1464 /* PTH (mobule: SPI1, LPC, DMAC, ADC) */ 1468 /* PTH (mobule: SPI1, LPC, DMAC, ADC) */
1465 PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK), 1469 GPIO_FN(SP1_MOSI),
1466 PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK), 1470 GPIO_FN(SP1_MISO),
1467 PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK), 1471 GPIO_FN(SP1_SCK),
1468 PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK), 1472 GPIO_FN(SP1_SCK_FB),
1469 PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK), 1473 GPIO_FN(SP1_SS0),
1470 PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK), 1474 GPIO_FN(SP1_SS1),
1471 PINMUX_GPIO(GPIO_FN_WP, WP_MARK), 1475 GPIO_FN(WP),
1472 PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK), 1476 GPIO_FN(FMS0),
1473 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK), 1477 GPIO_FN(TEND1),
1474 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 1478 GPIO_FN(DREQ1),
1475 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), 1479 GPIO_FN(DACK1),
1476 PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK), 1480 GPIO_FN(ADTRG1),
1477 PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK), 1481 GPIO_FN(ADTRG0),
1478 1482
1479 /* PTI (mobule: LBSC, SDHI) */ 1483 /* PTI (mobule: LBSC, SDHI) */
1480 PINMUX_GPIO(GPIO_FN_D15, D15_MARK), 1484 GPIO_FN(D15),
1481 PINMUX_GPIO(GPIO_FN_D14, D14_MARK), 1485 GPIO_FN(D14),
1482 PINMUX_GPIO(GPIO_FN_D13, D13_MARK), 1486 GPIO_FN(D13),
1483 PINMUX_GPIO(GPIO_FN_D12, D12_MARK), 1487 GPIO_FN(D12),
1484 PINMUX_GPIO(GPIO_FN_D11, D11_MARK), 1488 GPIO_FN(D11),
1485 PINMUX_GPIO(GPIO_FN_D10, D10_MARK), 1489 GPIO_FN(D10),
1486 PINMUX_GPIO(GPIO_FN_D9, D9_MARK), 1490 GPIO_FN(D9),
1487 PINMUX_GPIO(GPIO_FN_D8, D8_MARK), 1491 GPIO_FN(D8),
1488 PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK), 1492 GPIO_FN(SD_WP),
1489 PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK), 1493 GPIO_FN(SD_CD),
1490 PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK), 1494 GPIO_FN(SD_CLK),
1491 PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK), 1495 GPIO_FN(SD_CMD),
1492 PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK), 1496 GPIO_FN(SD_D3),
1493 PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK), 1497 GPIO_FN(SD_D2),
1494 PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK), 1498 GPIO_FN(SD_D1),
1495 PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK), 1499 GPIO_FN(SD_D0),
1496 1500
1497 /* PTJ (mobule: SCIF234, SERMUX) */ 1501 /* PTJ (mobule: SCIF234, SERMUX) */
1498 PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK), 1502 GPIO_FN(RTS3),
1499 PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK), 1503 GPIO_FN(CTS3),
1500 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), 1504 GPIO_FN(TXD3),
1501 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), 1505 GPIO_FN(RXD3),
1502 PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK), 1506 GPIO_FN(RTS4),
1503 PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK), 1507 GPIO_FN(RXD4),
1504 PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK), 1508 GPIO_FN(TXD4),
1505 1509
1506 /* PTK (mobule: SERMUX, LBSC, SCIF) */ 1510 /* PTK (mobule: SERMUX, LBSC, SCIF) */
1507 PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK), 1511 GPIO_FN(COM2_TXD),
1508 PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK), 1512 GPIO_FN(COM2_RXD),
1509 PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK), 1513 GPIO_FN(COM2_RTS),
1510 PINMUX_GPIO(GPIO_FN_COM2_CTS, COM2_CTS_MARK), 1514 GPIO_FN(COM2_CTS),
1511 PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK), 1515 GPIO_FN(COM2_DTR),
1512 PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK), 1516 GPIO_FN(COM2_DSR),
1513 PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK), 1517 GPIO_FN(COM2_DCD),
1514 PINMUX_GPIO(GPIO_FN_CLKOUT, CLKOUT_MARK), 1518 GPIO_FN(CLKOUT),
1515 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), 1519 GPIO_FN(SCK2),
1516 PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK), 1520 GPIO_FN(SCK4),
1517 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), 1521 GPIO_FN(SCK3),
1518 1522
1519 /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */ 1523 /* PTL (mobule: SERMUX, SCIF, LBSC, AUD) */
1520 PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK), 1524 GPIO_FN(RAC_RXD),
1521 PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK), 1525 GPIO_FN(RAC_RTS),
1522 PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK), 1526 GPIO_FN(RAC_CTS),
1523 PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK), 1527 GPIO_FN(RAC_DTR),
1524 PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK), 1528 GPIO_FN(RAC_DSR),
1525 PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK), 1529 GPIO_FN(RAC_DCD),
1526 PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK), 1530 GPIO_FN(RAC_TXD),
1527 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), 1531 GPIO_FN(RXD2),
1528 PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK), 1532 GPIO_FN(CS5),
1529 PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK), 1533 GPIO_FN(CS6),
1530 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK), 1534 GPIO_FN(AUDSYNC),
1531 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK), 1535 GPIO_FN(AUDCK),
1532 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), 1536 GPIO_FN(TXD2),
1533 1537
1534 /* PTM (mobule: LBSC, IIC) */ 1538 /* PTM (mobule: LBSC, IIC) */
1535 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), 1539 GPIO_FN(CS4),
1536 PINMUX_GPIO(GPIO_FN_RD, RD_MARK), 1540 GPIO_FN(RD),
1537 PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK), 1541 GPIO_FN(WE0),
1538 PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK), 1542 GPIO_FN(CS0),
1539 PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK), 1543 GPIO_FN(SDA6),
1540 PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK), 1544 GPIO_FN(SCL6),
1541 PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK), 1545 GPIO_FN(SDA7),
1542 PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK), 1546 GPIO_FN(SCL7),
1543 1547
1544 /* PTN (mobule: USB, JMC, SGPIO, WDT) */ 1548 /* PTN (mobule: USB, JMC, SGPIO, WDT) */
1545 PINMUX_GPIO(GPIO_FN_VBUS_EN, VBUS_EN_MARK), 1549 GPIO_FN(VBUS_EN),
1546 PINMUX_GPIO(GPIO_FN_VBUS_OC, VBUS_OC_MARK), 1550 GPIO_FN(VBUS_OC),
1547 PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK), 1551 GPIO_FN(JMCTCK),
1548 PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK), 1552 GPIO_FN(JMCTMS),
1549 PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK), 1553 GPIO_FN(JMCTDO),
1550 PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK), 1554 GPIO_FN(JMCTDI),
1551 PINMUX_GPIO(GPIO_FN_JMCTRST, JMCTRST_MARK), 1555 GPIO_FN(JMCTRST),
1552 PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK), 1556 GPIO_FN(SGPIO1_CLK),
1553 PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK), 1557 GPIO_FN(SGPIO1_LOAD),
1554 PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK), 1558 GPIO_FN(SGPIO1_DI),
1555 PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK), 1559 GPIO_FN(SGPIO1_DO),
1556 PINMUX_GPIO(GPIO_FN_SUB_CLKIN, SUB_CLKIN_MARK), 1560 GPIO_FN(SUB_CLKIN),
1557 1561
1558 /* PTO (mobule: SGPIO, SerMux) */ 1562 /* PTO (mobule: SGPIO, SerMux) */
1559 PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK), 1563 GPIO_FN(SGPIO0_CLK),
1560 PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK), 1564 GPIO_FN(SGPIO0_LOAD),
1561 PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK), 1565 GPIO_FN(SGPIO0_DI),
1562 PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK), 1566 GPIO_FN(SGPIO0_DO),
1563 PINMUX_GPIO(GPIO_FN_SGPIO2_CLK, SGPIO2_CLK_MARK), 1567 GPIO_FN(SGPIO2_CLK),
1564 PINMUX_GPIO(GPIO_FN_SGPIO2_LOAD, SGPIO2_LOAD_MARK), 1568 GPIO_FN(SGPIO2_LOAD),
1565 PINMUX_GPIO(GPIO_FN_SGPIO2_DI, SGPIO2_DI_MARK), 1569 GPIO_FN(SGPIO2_DI),
1566 PINMUX_GPIO(GPIO_FN_SGPIO2_DO, SGPIO2_DO_MARK), 1570 GPIO_FN(SGPIO2_DO),
1567 PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK), 1571 GPIO_FN(COM1_TXD),
1568 PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK), 1572 GPIO_FN(COM1_RXD),
1569 PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK), 1573 GPIO_FN(COM1_RTS),
1570 PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK), 1574 GPIO_FN(COM1_CTS),
1571 1575
1572 /* PTP (mobule: EVC, ADC) */ 1576 /* PTP (mobule: EVC, ADC) */
1573 1577
1574 /* PTQ (mobule: LPC) */ 1578 /* PTQ (mobule: LPC) */
1575 PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK), 1579 GPIO_FN(LAD3),
1576 PINMUX_GPIO(GPIO_FN_LAD2, LAD2_MARK), 1580 GPIO_FN(LAD2),
1577 PINMUX_GPIO(GPIO_FN_LAD1, LAD1_MARK), 1581 GPIO_FN(LAD1),
1578 PINMUX_GPIO(GPIO_FN_LAD0, LAD0_MARK), 1582 GPIO_FN(LAD0),
1579 PINMUX_GPIO(GPIO_FN_LFRAME, LFRAME_MARK), 1583 GPIO_FN(LFRAME),
1580 PINMUX_GPIO(GPIO_FN_LRESET, LRESET_MARK), 1584 GPIO_FN(LRESET),
1581 PINMUX_GPIO(GPIO_FN_LCLK, LCLK_MARK), 1585 GPIO_FN(LCLK),
1582 1586
1583 /* PTR (mobule: GRA, IIC) */ 1587 /* PTR (mobule: GRA, IIC) */
1584 PINMUX_GPIO(GPIO_FN_DDC3, DDC3_MARK), 1588 GPIO_FN(DDC3),
1585 PINMUX_GPIO(GPIO_FN_DDC2, DDC2_MARK), 1589 GPIO_FN(DDC2),
1586 PINMUX_GPIO(GPIO_FN_SDA8, SDA8_MARK), 1590 GPIO_FN(SDA8),
1587 PINMUX_GPIO(GPIO_FN_SCL8, SCL8_MARK), 1591 GPIO_FN(SCL8),
1588 PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK), 1592 GPIO_FN(SDA2),
1589 PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK), 1593 GPIO_FN(SCL2),
1590 PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK), 1594 GPIO_FN(SDA1),
1591 PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK), 1595 GPIO_FN(SCL1),
1592 PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK), 1596 GPIO_FN(SDA0),
1593 PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK), 1597 GPIO_FN(SCL0),
1594 1598
1595 /* PTS (mobule: GRA, IIC) */ 1599 /* PTS (mobule: GRA, IIC) */
1596 PINMUX_GPIO(GPIO_FN_DDC1, DDC1_MARK), 1600 GPIO_FN(DDC1),
1597 PINMUX_GPIO(GPIO_FN_DDC0, DDC0_MARK), 1601 GPIO_FN(DDC0),
1598 PINMUX_GPIO(GPIO_FN_SDA9, SDA9_MARK), 1602 GPIO_FN(SDA9),
1599 PINMUX_GPIO(GPIO_FN_SCL9, SCL9_MARK), 1603 GPIO_FN(SCL9),
1600 PINMUX_GPIO(GPIO_FN_SDA5, SDA5_MARK), 1604 GPIO_FN(SDA5),
1601 PINMUX_GPIO(GPIO_FN_SCL5, SCL5_MARK), 1605 GPIO_FN(SCL5),
1602 PINMUX_GPIO(GPIO_FN_SDA4, SDA4_MARK), 1606 GPIO_FN(SDA4),
1603 PINMUX_GPIO(GPIO_FN_SCL4, SCL4_MARK), 1607 GPIO_FN(SCL4),
1604 PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK), 1608 GPIO_FN(SDA3),
1605 PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK), 1609 GPIO_FN(SCL3),
1606 1610
1607 /* PTT (mobule: PWMX, AUD) */ 1611 /* PTT (mobule: PWMX, AUD) */
1608 PINMUX_GPIO(GPIO_FN_PWMX7, PWMX7_MARK), 1612 GPIO_FN(PWMX7),
1609 PINMUX_GPIO(GPIO_FN_PWMX6, PWMX6_MARK), 1613 GPIO_FN(PWMX6),
1610 PINMUX_GPIO(GPIO_FN_PWMX5, PWMX5_MARK), 1614 GPIO_FN(PWMX5),
1611 PINMUX_GPIO(GPIO_FN_PWMX4, PWMX4_MARK), 1615 GPIO_FN(PWMX4),
1612 PINMUX_GPIO(GPIO_FN_PWMX3, PWMX3_MARK), 1616 GPIO_FN(PWMX3),
1613 PINMUX_GPIO(GPIO_FN_PWMX2, PWMX2_MARK), 1617 GPIO_FN(PWMX2),
1614 PINMUX_GPIO(GPIO_FN_PWMX1, PWMX1_MARK), 1618 GPIO_FN(PWMX1),
1615 PINMUX_GPIO(GPIO_FN_PWMX0, PWMX0_MARK), 1619 GPIO_FN(PWMX0),
1616 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK), 1620 GPIO_FN(AUDATA3),
1617 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK), 1621 GPIO_FN(AUDATA2),
1618 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK), 1622 GPIO_FN(AUDATA1),
1619 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK), 1623 GPIO_FN(AUDATA0),
1620 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), 1624 GPIO_FN(STATUS1),
1621 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), 1625 GPIO_FN(STATUS0),
1622 1626
1623 /* PTU (mobule: LPC, APM) */ 1627 /* PTU (mobule: LPC, APM) */
1624 PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK), 1628 GPIO_FN(LGPIO7),
1625 PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK), 1629 GPIO_FN(LGPIO6),
1626 PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK), 1630 GPIO_FN(LGPIO5),
1627 PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK), 1631 GPIO_FN(LGPIO4),
1628 PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK), 1632 GPIO_FN(LGPIO3),
1629 PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK), 1633 GPIO_FN(LGPIO2),
1630 PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK), 1634 GPIO_FN(LGPIO1),
1631 PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK), 1635 GPIO_FN(LGPIO0),
1632 PINMUX_GPIO(GPIO_FN_APMONCTL_O, APMONCTL_O_MARK), 1636 GPIO_FN(APMONCTL_O),
1633 PINMUX_GPIO(GPIO_FN_APMPWBTOUT_O, APMPWBTOUT_O_MARK), 1637 GPIO_FN(APMPWBTOUT_O),
1634 PINMUX_GPIO(GPIO_FN_APMSCI_O, APMSCI_O_MARK), 1638 GPIO_FN(APMSCI_O),
1635 PINMUX_GPIO(GPIO_FN_APMVDDON, APMVDDON_MARK), 1639 GPIO_FN(APMVDDON),
1636 PINMUX_GPIO(GPIO_FN_APMSLPBTN, APMSLPBTN_MARK), 1640 GPIO_FN(APMSLPBTN),
1637 PINMUX_GPIO(GPIO_FN_APMPWRBTN, APMPWRBTN_MARK), 1641 GPIO_FN(APMPWRBTN),
1638 PINMUX_GPIO(GPIO_FN_APMS5N, APMS5N_MARK), 1642 GPIO_FN(APMS5N),
1639 PINMUX_GPIO(GPIO_FN_APMS3N, APMS3N_MARK), 1643 GPIO_FN(APMS3N),
1640 1644
1641 /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */ 1645 /* PTV (mobule: LBSC, SerMux, R-SPI, EVC, GRA) */
1642 PINMUX_GPIO(GPIO_FN_A23, A23_MARK), 1646 GPIO_FN(A23),
1643 PINMUX_GPIO(GPIO_FN_A22, A22_MARK), 1647 GPIO_FN(A22),
1644 PINMUX_GPIO(GPIO_FN_A21, A21_MARK), 1648 GPIO_FN(A21),
1645 PINMUX_GPIO(GPIO_FN_A20, A20_MARK), 1649 GPIO_FN(A20),
1646 PINMUX_GPIO(GPIO_FN_A19, A19_MARK), 1650 GPIO_FN(A19),
1647 PINMUX_GPIO(GPIO_FN_A18, A18_MARK), 1651 GPIO_FN(A18),
1648 PINMUX_GPIO(GPIO_FN_A17, A17_MARK), 1652 GPIO_FN(A17),
1649 PINMUX_GPIO(GPIO_FN_A16, A16_MARK), 1653 GPIO_FN(A16),
1650 PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK), 1654 GPIO_FN(COM2_RI),
1651 PINMUX_GPIO(GPIO_FN_R_SPI_MOSI, R_SPI_MOSI_MARK), 1655 GPIO_FN(R_SPI_MOSI),
1652 PINMUX_GPIO(GPIO_FN_R_SPI_MISO, R_SPI_MISO_MARK), 1656 GPIO_FN(R_SPI_MISO),
1653 PINMUX_GPIO(GPIO_FN_R_SPI_RSPCK, R_SPI_RSPCK_MARK), 1657 GPIO_FN(R_SPI_RSPCK),
1654 PINMUX_GPIO(GPIO_FN_R_SPI_SSL0, R_SPI_SSL0_MARK), 1658 GPIO_FN(R_SPI_SSL0),
1655 PINMUX_GPIO(GPIO_FN_R_SPI_SSL1, R_SPI_SSL1_MARK), 1659 GPIO_FN(R_SPI_SSL1),
1656 PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK), 1660 GPIO_FN(EVENT7),
1657 PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK), 1661 GPIO_FN(EVENT6),
1658 PINMUX_GPIO(GPIO_FN_VBIOS_DI, VBIOS_DI_MARK), 1662 GPIO_FN(VBIOS_DI),
1659 PINMUX_GPIO(GPIO_FN_VBIOS_DO, VBIOS_DO_MARK), 1663 GPIO_FN(VBIOS_DO),
1660 PINMUX_GPIO(GPIO_FN_VBIOS_CLK, VBIOS_CLK_MARK), 1664 GPIO_FN(VBIOS_CLK),
1661 PINMUX_GPIO(GPIO_FN_VBIOS_CS, VBIOS_CS_MARK), 1665 GPIO_FN(VBIOS_CS),
1662 1666
1663 /* PTW (mobule: LBSC, EVC, SCIF) */ 1667 /* PTW (mobule: LBSC, EVC, SCIF) */
1664 PINMUX_GPIO(GPIO_FN_A16, A16_MARK), 1668 GPIO_FN(A16),
1665 PINMUX_GPIO(GPIO_FN_A15, A15_MARK), 1669 GPIO_FN(A15),
1666 PINMUX_GPIO(GPIO_FN_A14, A14_MARK), 1670 GPIO_FN(A14),
1667 PINMUX_GPIO(GPIO_FN_A13, A13_MARK), 1671 GPIO_FN(A13),
1668 PINMUX_GPIO(GPIO_FN_A12, A12_MARK), 1672 GPIO_FN(A12),
1669 PINMUX_GPIO(GPIO_FN_A11, A11_MARK), 1673 GPIO_FN(A11),
1670 PINMUX_GPIO(GPIO_FN_A10, A10_MARK), 1674 GPIO_FN(A10),
1671 PINMUX_GPIO(GPIO_FN_A9, A9_MARK), 1675 GPIO_FN(A9),
1672 PINMUX_GPIO(GPIO_FN_A8, A8_MARK), 1676 GPIO_FN(A8),
1673 PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK), 1677 GPIO_FN(EVENT5),
1674 PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK), 1678 GPIO_FN(EVENT4),
1675 PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK), 1679 GPIO_FN(EVENT3),
1676 PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK), 1680 GPIO_FN(EVENT2),
1677 PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK), 1681 GPIO_FN(EVENT1),
1678 PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK), 1682 GPIO_FN(EVENT0),
1679 PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK), 1683 GPIO_FN(CTS4),
1680 PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK), 1684 GPIO_FN(CTS2),
1681 1685
1682 /* PTX (mobule: LBSC) */ 1686 /* PTX (mobule: LBSC) */
1683 PINMUX_GPIO(GPIO_FN_A7, A7_MARK), 1687 GPIO_FN(A7),
1684 PINMUX_GPIO(GPIO_FN_A6, A6_MARK), 1688 GPIO_FN(A6),
1685 PINMUX_GPIO(GPIO_FN_A5, A5_MARK), 1689 GPIO_FN(A5),
1686 PINMUX_GPIO(GPIO_FN_A4, A4_MARK), 1690 GPIO_FN(A4),
1687 PINMUX_GPIO(GPIO_FN_A3, A3_MARK), 1691 GPIO_FN(A3),
1688 PINMUX_GPIO(GPIO_FN_A2, A2_MARK), 1692 GPIO_FN(A2),
1689 PINMUX_GPIO(GPIO_FN_A1, A1_MARK), 1693 GPIO_FN(A1),
1690 PINMUX_GPIO(GPIO_FN_A0, A0_MARK), 1694 GPIO_FN(A0),
1691 PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK), 1695 GPIO_FN(RTS2),
1692 PINMUX_GPIO(GPIO_FN_SIM_D, SIM_D_MARK), 1696 GPIO_FN(SIM_D),
1693 PINMUX_GPIO(GPIO_FN_SIM_CLK, SIM_CLK_MARK), 1697 GPIO_FN(SIM_CLK),
1694 PINMUX_GPIO(GPIO_FN_SIM_RST, SIM_RST_MARK), 1698 GPIO_FN(SIM_RST),
1695 1699
1696 /* PTY (mobule: LBSC) */ 1700 /* PTY (mobule: LBSC) */
1697 PINMUX_GPIO(GPIO_FN_D7, D7_MARK), 1701 GPIO_FN(D7),
1698 PINMUX_GPIO(GPIO_FN_D6, D6_MARK), 1702 GPIO_FN(D6),
1699 PINMUX_GPIO(GPIO_FN_D5, D5_MARK), 1703 GPIO_FN(D5),
1700 PINMUX_GPIO(GPIO_FN_D4, D4_MARK), 1704 GPIO_FN(D4),
1701 PINMUX_GPIO(GPIO_FN_D3, D3_MARK), 1705 GPIO_FN(D3),
1702 PINMUX_GPIO(GPIO_FN_D2, D2_MARK), 1706 GPIO_FN(D2),
1703 PINMUX_GPIO(GPIO_FN_D1, D1_MARK), 1707 GPIO_FN(D1),
1704 PINMUX_GPIO(GPIO_FN_D0, D0_MARK), 1708 GPIO_FN(D0),
1705 1709
1706 /* PTZ (mobule: eMMC, ONFI) */ 1710 /* PTZ (mobule: eMMC, ONFI) */
1707 PINMUX_GPIO(GPIO_FN_MMCDAT7, MMCDAT7_MARK), 1711 GPIO_FN(MMCDAT7),
1708 PINMUX_GPIO(GPIO_FN_MMCDAT6, MMCDAT6_MARK), 1712 GPIO_FN(MMCDAT6),
1709 PINMUX_GPIO(GPIO_FN_MMCDAT5, MMCDAT5_MARK), 1713 GPIO_FN(MMCDAT5),
1710 PINMUX_GPIO(GPIO_FN_MMCDAT4, MMCDAT4_MARK), 1714 GPIO_FN(MMCDAT4),
1711 PINMUX_GPIO(GPIO_FN_MMCDAT3, MMCDAT3_MARK), 1715 GPIO_FN(MMCDAT3),
1712 PINMUX_GPIO(GPIO_FN_MMCDAT2, MMCDAT2_MARK), 1716 GPIO_FN(MMCDAT2),
1713 PINMUX_GPIO(GPIO_FN_MMCDAT1, MMCDAT1_MARK), 1717 GPIO_FN(MMCDAT1),
1714 PINMUX_GPIO(GPIO_FN_MMCDAT0, MMCDAT0_MARK), 1718 GPIO_FN(MMCDAT0),
1715 PINMUX_GPIO(GPIO_FN_ON_DQ7, ON_DQ7_MARK), 1719 GPIO_FN(ON_DQ7),
1716 PINMUX_GPIO(GPIO_FN_ON_DQ6, ON_DQ6_MARK), 1720 GPIO_FN(ON_DQ6),
1717 PINMUX_GPIO(GPIO_FN_ON_DQ5, ON_DQ5_MARK), 1721 GPIO_FN(ON_DQ5),
1718 PINMUX_GPIO(GPIO_FN_ON_DQ4, ON_DQ4_MARK), 1722 GPIO_FN(ON_DQ4),
1719 PINMUX_GPIO(GPIO_FN_ON_DQ3, ON_DQ3_MARK), 1723 GPIO_FN(ON_DQ3),
1720 PINMUX_GPIO(GPIO_FN_ON_DQ2, ON_DQ2_MARK), 1724 GPIO_FN(ON_DQ2),
1721 PINMUX_GPIO(GPIO_FN_ON_DQ1, ON_DQ1_MARK), 1725 GPIO_FN(ON_DQ1),
1722 PINMUX_GPIO(GPIO_FN_ON_DQ0, ON_DQ0_MARK), 1726 GPIO_FN(ON_DQ0),
1723}; 1727};
1724 1728
1725static struct pinmux_cfg_reg pinmux_config_regs[] = { 1729static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1726 { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) { 1730 { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
1727 PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU, 1731 PTA7_FN, PTA7_OUT, PTA7_IN, PTA7_IN_PU,
1728 PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU, 1732 PTA6_FN, PTA6_OUT, PTA6_IN, PTA6_IN_PU,
@@ -2152,7 +2156,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
2152 {} 2156 {}
2153}; 2157};
2154 2158
2155static struct pinmux_data_reg pinmux_data_regs[] = { 2159static const struct pinmux_data_reg pinmux_data_regs[] = {
2156 { PINMUX_DATA_REG("PADR", 0xffec0034, 8) { 2160 { PINMUX_DATA_REG("PADR", 0xffec0034, 8) {
2157 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA, 2161 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
2158 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA } 2162 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
@@ -2260,20 +2264,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
2260 { }, 2264 { },
2261}; 2265};
2262 2266
2263struct sh_pfc_soc_info sh7757_pinmux_info = { 2267const struct sh_pfc_soc_info sh7757_pinmux_info = {
2264 .name = "sh7757_pfc", 2268 .name = "sh7757_pfc",
2265 .reserved_id = PINMUX_RESERVED,
2266 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
2267 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 2269 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2268 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 2270 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
2269 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 2271 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2270 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2271 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2272 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2272 2273
2273 .first_gpio = GPIO_PTA0, 2274 .pins = pinmux_pins,
2274 .last_gpio = GPIO_FN_ON_DQ0, 2275 .nr_pins = ARRAY_SIZE(pinmux_pins),
2276 .func_gpios = pinmux_func_gpios,
2277 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
2275 2278
2276 .gpios = pinmux_gpios,
2277 .cfg_regs = pinmux_config_regs, 2279 .cfg_regs = pinmux_config_regs,
2278 .data_regs = pinmux_data_regs, 2280 .data_regs = pinmux_data_regs,
2279 2281
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
index 3b1825d925bb..c176b794f240 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
@@ -355,7 +355,7 @@ enum {
355 PINMUX_MARK_END, 355 PINMUX_MARK_END,
356}; 356};
357 357
358static pinmux_enum_t pinmux_data[] = { 358static const pinmux_enum_t pinmux_data[] = {
359 359
360 /* PA GPIO */ 360 /* PA GPIO */
361 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), 361 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
@@ -702,7 +702,7 @@ static pinmux_enum_t pinmux_data[] = {
702 PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1), 702 PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1),
703}; 703};
704 704
705static struct pinmux_gpio pinmux_gpios[] = { 705static struct sh_pfc_pin pinmux_pins[] = {
706 /* PA */ 706 /* PA */
707 PINMUX_GPIO(GPIO_PA7, PA7_DATA), 707 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
708 PINMUX_GPIO(GPIO_PA6, PA6_DATA), 708 PINMUX_GPIO(GPIO_PA6, PA6_DATA),
@@ -845,176 +845,180 @@ static struct pinmux_gpio pinmux_gpios[] = {
845 PINMUX_GPIO(GPIO_PR2, PR2_DATA), 845 PINMUX_GPIO(GPIO_PR2, PR2_DATA),
846 PINMUX_GPIO(GPIO_PR1, PR1_DATA), 846 PINMUX_GPIO(GPIO_PR1, PR1_DATA),
847 PINMUX_GPIO(GPIO_PR0, PR0_DATA), 847 PINMUX_GPIO(GPIO_PR0, PR0_DATA),
848};
849
850#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
848 851
852static const struct pinmux_func pinmux_func_gpios[] = {
849 /* FN */ 853 /* FN */
850 PINMUX_GPIO(GPIO_FN_D63_AD31, D63_AD31_MARK), 854 GPIO_FN(D63_AD31),
851 PINMUX_GPIO(GPIO_FN_D62_AD30, D62_AD30_MARK), 855 GPIO_FN(D62_AD30),
852 PINMUX_GPIO(GPIO_FN_D61_AD29, D61_AD29_MARK), 856 GPIO_FN(D61_AD29),
853 PINMUX_GPIO(GPIO_FN_D60_AD28, D60_AD28_MARK), 857 GPIO_FN(D60_AD28),
854 PINMUX_GPIO(GPIO_FN_D59_AD27, D59_AD27_MARK), 858 GPIO_FN(D59_AD27),
855 PINMUX_GPIO(GPIO_FN_D58_AD26, D58_AD26_MARK), 859 GPIO_FN(D58_AD26),
856 PINMUX_GPIO(GPIO_FN_D57_AD25, D57_AD25_MARK), 860 GPIO_FN(D57_AD25),
857 PINMUX_GPIO(GPIO_FN_D56_AD24, D56_AD24_MARK), 861 GPIO_FN(D56_AD24),
858 PINMUX_GPIO(GPIO_FN_D55_AD23, D55_AD23_MARK), 862 GPIO_FN(D55_AD23),
859 PINMUX_GPIO(GPIO_FN_D54_AD22, D54_AD22_MARK), 863 GPIO_FN(D54_AD22),
860 PINMUX_GPIO(GPIO_FN_D53_AD21, D53_AD21_MARK), 864 GPIO_FN(D53_AD21),
861 PINMUX_GPIO(GPIO_FN_D52_AD20, D52_AD20_MARK), 865 GPIO_FN(D52_AD20),
862 PINMUX_GPIO(GPIO_FN_D51_AD19, D51_AD19_MARK), 866 GPIO_FN(D51_AD19),
863 PINMUX_GPIO(GPIO_FN_D50_AD18, D50_AD18_MARK), 867 GPIO_FN(D50_AD18),
864 PINMUX_GPIO(GPIO_FN_D49_AD17_DB5, D49_AD17_DB5_MARK), 868 GPIO_FN(D49_AD17_DB5),
865 PINMUX_GPIO(GPIO_FN_D48_AD16_DB4, D48_AD16_DB4_MARK), 869 GPIO_FN(D48_AD16_DB4),
866 PINMUX_GPIO(GPIO_FN_D47_AD15_DB3, D47_AD15_DB3_MARK), 870 GPIO_FN(D47_AD15_DB3),
867 PINMUX_GPIO(GPIO_FN_D46_AD14_DB2, D46_AD14_DB2_MARK), 871 GPIO_FN(D46_AD14_DB2),
868 PINMUX_GPIO(GPIO_FN_D45_AD13_DB1, D45_AD13_DB1_MARK), 872 GPIO_FN(D45_AD13_DB1),
869 PINMUX_GPIO(GPIO_FN_D44_AD12_DB0, D44_AD12_DB0_MARK), 873 GPIO_FN(D44_AD12_DB0),
870 PINMUX_GPIO(GPIO_FN_D43_AD11_DG5, D43_AD11_DG5_MARK), 874 GPIO_FN(D43_AD11_DG5),
871 PINMUX_GPIO(GPIO_FN_D42_AD10_DG4, D42_AD10_DG4_MARK), 875 GPIO_FN(D42_AD10_DG4),
872 PINMUX_GPIO(GPIO_FN_D41_AD9_DG3, D41_AD9_DG3_MARK), 876 GPIO_FN(D41_AD9_DG3),
873 PINMUX_GPIO(GPIO_FN_D40_AD8_DG2, D40_AD8_DG2_MARK), 877 GPIO_FN(D40_AD8_DG2),
874 PINMUX_GPIO(GPIO_FN_D39_AD7_DG1, D39_AD7_DG1_MARK), 878 GPIO_FN(D39_AD7_DG1),
875 PINMUX_GPIO(GPIO_FN_D38_AD6_DG0, D38_AD6_DG0_MARK), 879 GPIO_FN(D38_AD6_DG0),
876 PINMUX_GPIO(GPIO_FN_D37_AD5_DR5, D37_AD5_DR5_MARK), 880 GPIO_FN(D37_AD5_DR5),
877 PINMUX_GPIO(GPIO_FN_D36_AD4_DR4, D36_AD4_DR4_MARK), 881 GPIO_FN(D36_AD4_DR4),
878 PINMUX_GPIO(GPIO_FN_D35_AD3_DR3, D35_AD3_DR3_MARK), 882 GPIO_FN(D35_AD3_DR3),
879 PINMUX_GPIO(GPIO_FN_D34_AD2_DR2, D34_AD2_DR2_MARK), 883 GPIO_FN(D34_AD2_DR2),
880 PINMUX_GPIO(GPIO_FN_D33_AD1_DR1, D33_AD1_DR1_MARK), 884 GPIO_FN(D33_AD1_DR1),
881 PINMUX_GPIO(GPIO_FN_D32_AD0_DR0, D32_AD0_DR0_MARK), 885 GPIO_FN(D32_AD0_DR0),
882 PINMUX_GPIO(GPIO_FN_REQ1, REQ1_MARK), 886 GPIO_FN(REQ1),
883 PINMUX_GPIO(GPIO_FN_REQ2, REQ2_MARK), 887 GPIO_FN(REQ2),
884 PINMUX_GPIO(GPIO_FN_REQ3, REQ3_MARK), 888 GPIO_FN(REQ3),
885 PINMUX_GPIO(GPIO_FN_GNT1, GNT1_MARK), 889 GPIO_FN(GNT1),
886 PINMUX_GPIO(GPIO_FN_GNT2, GNT2_MARK), 890 GPIO_FN(GNT2),
887 PINMUX_GPIO(GPIO_FN_GNT3, GNT3_MARK), 891 GPIO_FN(GNT3),
888 PINMUX_GPIO(GPIO_FN_MMCCLK, MMCCLK_MARK), 892 GPIO_FN(MMCCLK),
889 PINMUX_GPIO(GPIO_FN_D31, D31_MARK), 893 GPIO_FN(D31),
890 PINMUX_GPIO(GPIO_FN_D30, D30_MARK), 894 GPIO_FN(D30),
891 PINMUX_GPIO(GPIO_FN_D29, D29_MARK), 895 GPIO_FN(D29),
892 PINMUX_GPIO(GPIO_FN_D28, D28_MARK), 896 GPIO_FN(D28),
893 PINMUX_GPIO(GPIO_FN_D27, D27_MARK), 897 GPIO_FN(D27),
894 PINMUX_GPIO(GPIO_FN_D26, D26_MARK), 898 GPIO_FN(D26),
895 PINMUX_GPIO(GPIO_FN_D25, D25_MARK), 899 GPIO_FN(D25),
896 PINMUX_GPIO(GPIO_FN_D24, D24_MARK), 900 GPIO_FN(D24),
897 PINMUX_GPIO(GPIO_FN_D23, D23_MARK), 901 GPIO_FN(D23),
898 PINMUX_GPIO(GPIO_FN_D22, D22_MARK), 902 GPIO_FN(D22),
899 PINMUX_GPIO(GPIO_FN_D21, D21_MARK), 903 GPIO_FN(D21),
900 PINMUX_GPIO(GPIO_FN_D20, D20_MARK), 904 GPIO_FN(D20),
901 PINMUX_GPIO(GPIO_FN_D19, D19_MARK), 905 GPIO_FN(D19),
902 PINMUX_GPIO(GPIO_FN_D18, D18_MARK), 906 GPIO_FN(D18),
903 PINMUX_GPIO(GPIO_FN_D17, D17_MARK), 907 GPIO_FN(D17),
904 PINMUX_GPIO(GPIO_FN_D16, D16_MARK), 908 GPIO_FN(D16),
905 PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), 909 GPIO_FN(SCIF1_SCK),
906 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), 910 GPIO_FN(SCIF1_RXD),
907 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), 911 GPIO_FN(SCIF1_TXD),
908 PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), 912 GPIO_FN(SCIF0_CTS),
909 PINMUX_GPIO(GPIO_FN_INTD, INTD_MARK), 913 GPIO_FN(INTD),
910 PINMUX_GPIO(GPIO_FN_FCE, FCE_MARK), 914 GPIO_FN(FCE),
911 PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), 915 GPIO_FN(SCIF0_RTS),
912 PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK), 916 GPIO_FN(HSPI_CS),
913 PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK), 917 GPIO_FN(FSE),
914 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), 918 GPIO_FN(SCIF0_SCK),
915 PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK), 919 GPIO_FN(HSPI_CLK),
916 PINMUX_GPIO(GPIO_FN_FRE, FRE_MARK), 920 GPIO_FN(FRE),
917 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), 921 GPIO_FN(SCIF0_RXD),
918 PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK), 922 GPIO_FN(HSPI_RX),
919 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), 923 GPIO_FN(FRB),
920 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), 924 GPIO_FN(SCIF0_TXD),
921 PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK), 925 GPIO_FN(HSPI_TX),
922 PINMUX_GPIO(GPIO_FN_FWE, FWE_MARK), 926 GPIO_FN(FWE),
923 PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), 927 GPIO_FN(SCIF5_TXD),
924 PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK), 928 GPIO_FN(HAC1_SYNC),
925 PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK), 929 GPIO_FN(SSI1_WS),
926 PINMUX_GPIO(GPIO_FN_SIOF_TXD_PJ, SIOF_TXD_PJ_MARK), 930 GPIO_FN(SIOF_TXD_PJ),
927 PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK), 931 GPIO_FN(HAC0_SDOUT),
928 PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK), 932 GPIO_FN(SSI0_SDATA),
929 PINMUX_GPIO(GPIO_FN_SIOF_RXD_PJ, SIOF_RXD_PJ_MARK), 933 GPIO_FN(SIOF_RXD_PJ),
930 PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK), 934 GPIO_FN(HAC0_SDIN),
931 PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK), 935 GPIO_FN(SSI0_SCK),
932 PINMUX_GPIO(GPIO_FN_SIOF_SYNC_PJ, SIOF_SYNC_PJ_MARK), 936 GPIO_FN(SIOF_SYNC_PJ),
933 PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK), 937 GPIO_FN(HAC0_SYNC),
934 PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK), 938 GPIO_FN(SSI0_WS),
935 PINMUX_GPIO(GPIO_FN_SIOF_MCLK_PJ, SIOF_MCLK_PJ_MARK), 939 GPIO_FN(SIOF_MCLK_PJ),
936 PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK), 940 GPIO_FN(HAC_RES),
937 PINMUX_GPIO(GPIO_FN_SIOF_SCK_PJ, SIOF_SCK_PJ_MARK), 941 GPIO_FN(SIOF_SCK_PJ),
938 PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK), 942 GPIO_FN(HAC0_BITCLK),
939 PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK), 943 GPIO_FN(SSI0_CLK),
940 PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK), 944 GPIO_FN(HAC1_BITCLK),
941 PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK), 945 GPIO_FN(SSI1_CLK),
942 PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), 946 GPIO_FN(TCLK),
943 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 947 GPIO_FN(IOIS16),
944 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), 948 GPIO_FN(STATUS0),
945 PINMUX_GPIO(GPIO_FN_DRAK0_PK3, DRAK0_PK3_MARK), 949 GPIO_FN(DRAK0_PK3),
946 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), 950 GPIO_FN(STATUS1),
947 PINMUX_GPIO(GPIO_FN_DRAK1_PK2, DRAK1_PK2_MARK), 951 GPIO_FN(DRAK1_PK2),
948 PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), 952 GPIO_FN(DACK2),
949 PINMUX_GPIO(GPIO_FN_SCIF2_TXD, SCIF2_TXD_MARK), 953 GPIO_FN(SCIF2_TXD),
950 PINMUX_GPIO(GPIO_FN_MMCCMD, MMCCMD_MARK), 954 GPIO_FN(MMCCMD),
951 PINMUX_GPIO(GPIO_FN_SIOF_TXD_PK, SIOF_TXD_PK_MARK), 955 GPIO_FN(SIOF_TXD_PK),
952 PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), 956 GPIO_FN(DACK3),
953 PINMUX_GPIO(GPIO_FN_SCIF2_SCK, SCIF2_SCK_MARK), 957 GPIO_FN(SCIF2_SCK),
954 PINMUX_GPIO(GPIO_FN_MMCDAT, MMCDAT_MARK), 958 GPIO_FN(MMCDAT),
955 PINMUX_GPIO(GPIO_FN_SIOF_SCK_PK, SIOF_SCK_PK_MARK), 959 GPIO_FN(SIOF_SCK_PK),
956 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 960 GPIO_FN(DREQ0),
957 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 961 GPIO_FN(DREQ1),
958 PINMUX_GPIO(GPIO_FN_DRAK0_PK1, DRAK0_PK1_MARK), 962 GPIO_FN(DRAK0_PK1),
959 PINMUX_GPIO(GPIO_FN_DRAK1_PK0, DRAK1_PK0_MARK), 963 GPIO_FN(DRAK1_PK0),
960 PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), 964 GPIO_FN(DREQ2),
961 PINMUX_GPIO(GPIO_FN_INTB, INTB_MARK), 965 GPIO_FN(INTB),
962 PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), 966 GPIO_FN(DREQ3),
963 PINMUX_GPIO(GPIO_FN_INTC, INTC_MARK), 967 GPIO_FN(INTC),
964 PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), 968 GPIO_FN(DRAK2),
965 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), 969 GPIO_FN(CE2A),
966 PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK), 970 GPIO_FN(IRL4),
967 PINMUX_GPIO(GPIO_FN_FD4, FD4_MARK), 971 GPIO_FN(FD4),
968 PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK), 972 GPIO_FN(IRL5),
969 PINMUX_GPIO(GPIO_FN_FD5, FD5_MARK), 973 GPIO_FN(FD5),
970 PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK), 974 GPIO_FN(IRL6),
971 PINMUX_GPIO(GPIO_FN_FD6, FD6_MARK), 975 GPIO_FN(FD6),
972 PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK), 976 GPIO_FN(IRL7),
973 PINMUX_GPIO(GPIO_FN_FD7, FD7_MARK), 977 GPIO_FN(FD7),
974 PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), 978 GPIO_FN(DRAK3),
975 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), 979 GPIO_FN(CE2B),
976 PINMUX_GPIO(GPIO_FN_BREQ_BSACK, BREQ_BSACK_MARK), 980 GPIO_FN(BREQ_BSACK),
977 PINMUX_GPIO(GPIO_FN_BACK_BSREQ, BACK_BSREQ_MARK), 981 GPIO_FN(BACK_BSREQ),
978 PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), 982 GPIO_FN(SCIF5_RXD),
979 PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK), 983 GPIO_FN(HAC1_SDIN),
980 PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK), 984 GPIO_FN(SSI1_SCK),
981 PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), 985 GPIO_FN(SCIF5_SCK),
982 PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK), 986 GPIO_FN(HAC1_SDOUT),
983 PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK), 987 GPIO_FN(SSI1_SDATA),
984 PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK), 988 GPIO_FN(SCIF3_TXD),
985 PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK), 989 GPIO_FN(FCLE),
986 PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK), 990 GPIO_FN(SCIF3_RXD),
987 PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK), 991 GPIO_FN(FALE),
988 PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK), 992 GPIO_FN(SCIF3_SCK),
989 PINMUX_GPIO(GPIO_FN_FD0, FD0_MARK), 993 GPIO_FN(FD0),
990 PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), 994 GPIO_FN(SCIF4_TXD),
991 PINMUX_GPIO(GPIO_FN_FD1, FD1_MARK), 995 GPIO_FN(FD1),
992 PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), 996 GPIO_FN(SCIF4_RXD),
993 PINMUX_GPIO(GPIO_FN_FD2, FD2_MARK), 997 GPIO_FN(FD2),
994 PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), 998 GPIO_FN(SCIF4_SCK),
995 PINMUX_GPIO(GPIO_FN_FD3, FD3_MARK), 999 GPIO_FN(FD3),
996 PINMUX_GPIO(GPIO_FN_DEVSEL_DCLKOUT, DEVSEL_DCLKOUT_MARK), 1000 GPIO_FN(DEVSEL_DCLKOUT),
997 PINMUX_GPIO(GPIO_FN_STOP_CDE, STOP_CDE_MARK), 1001 GPIO_FN(STOP_CDE),
998 PINMUX_GPIO(GPIO_FN_LOCK_ODDF, LOCK_ODDF_MARK), 1002 GPIO_FN(LOCK_ODDF),
999 PINMUX_GPIO(GPIO_FN_TRDY_DISPL, TRDY_DISPL_MARK), 1003 GPIO_FN(TRDY_DISPL),
1000 PINMUX_GPIO(GPIO_FN_IRDY_HSYNC, IRDY_HSYNC_MARK), 1004 GPIO_FN(IRDY_HSYNC),
1001 PINMUX_GPIO(GPIO_FN_PCIFRAME_VSYNC, PCIFRAME_VSYNC_MARK), 1005 GPIO_FN(PCIFRAME_VSYNC),
1002 PINMUX_GPIO(GPIO_FN_INTA, INTA_MARK), 1006 GPIO_FN(INTA),
1003 PINMUX_GPIO(GPIO_FN_GNT0_GNTIN, GNT0_GNTIN_MARK), 1007 GPIO_FN(GNT0_GNTIN),
1004 PINMUX_GPIO(GPIO_FN_REQ0_REQOUT, REQ0_REQOUT_MARK), 1008 GPIO_FN(REQ0_REQOUT),
1005 PINMUX_GPIO(GPIO_FN_PERR, PERR_MARK), 1009 GPIO_FN(PERR),
1006 PINMUX_GPIO(GPIO_FN_SERR, SERR_MARK), 1010 GPIO_FN(SERR),
1007 PINMUX_GPIO(GPIO_FN_WE7_CBE3, WE7_CBE3_MARK), 1011 GPIO_FN(WE7_CBE3),
1008 PINMUX_GPIO(GPIO_FN_WE6_CBE2, WE6_CBE2_MARK), 1012 GPIO_FN(WE6_CBE2),
1009 PINMUX_GPIO(GPIO_FN_WE5_CBE1, WE5_CBE1_MARK), 1013 GPIO_FN(WE5_CBE1),
1010 PINMUX_GPIO(GPIO_FN_WE4_CBE0, WE4_CBE0_MARK), 1014 GPIO_FN(WE4_CBE0),
1011 PINMUX_GPIO(GPIO_FN_SCIF2_RXD, SCIF2_RXD_MARK), 1015 GPIO_FN(SCIF2_RXD),
1012 PINMUX_GPIO(GPIO_FN_SIOF_RXD, SIOF_RXD_MARK), 1016 GPIO_FN(SIOF_RXD),
1013 PINMUX_GPIO(GPIO_FN_MRESETOUT, MRESETOUT_MARK), 1017 GPIO_FN(MRESETOUT),
1014 PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), 1018 GPIO_FN(IRQOUT),
1015}; 1019};
1016 1020
1017static struct pinmux_cfg_reg pinmux_config_regs[] = { 1021static const struct pinmux_cfg_reg pinmux_config_regs[] = {
1018 { PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) { 1022 { PINMUX_CFG_REG("PACR", 0xffe70000, 16, 2) {
1019 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, 1023 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
1020 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, 1024 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
@@ -1214,7 +1218,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
1214 {} 1218 {}
1215}; 1219};
1216 1220
1217static struct pinmux_data_reg pinmux_data_regs[] = { 1221static const struct pinmux_data_reg pinmux_data_regs[] = {
1218 { PINMUX_DATA_REG("PADR", 0xffe70020, 8) { 1222 { PINMUX_DATA_REG("PADR", 0xffe70020, 8) {
1219 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, 1223 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
1220 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } 1224 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
@@ -1282,20 +1286,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
1282 { }, 1286 { },
1283}; 1287};
1284 1288
1285struct sh_pfc_soc_info sh7785_pinmux_info = { 1289const struct sh_pfc_soc_info sh7785_pinmux_info = {
1286 .name = "sh7785_pfc", 1290 .name = "sh7785_pfc",
1287 .reserved_id = PINMUX_RESERVED,
1288 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1289 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 1291 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1290 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 1292 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1291 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 1293 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
1292 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
1293 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 1294 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
1294 1295
1295 .first_gpio = GPIO_PA7, 1296 .pins = pinmux_pins,
1296 .last_gpio = GPIO_FN_IRQOUT, 1297 .nr_pins = ARRAY_SIZE(pinmux_pins),
1298 .func_gpios = pinmux_func_gpios,
1299 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
1297 1300
1298 .gpios = pinmux_gpios,
1299 .cfg_regs = pinmux_config_regs, 1301 .cfg_regs = pinmux_config_regs,
1300 .data_regs = pinmux_data_regs, 1302 .data_regs = pinmux_data_regs,
1301 1303
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
index 1e18b58f9e5f..8ae0e32844e9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
@@ -191,7 +191,7 @@ enum {
191 PINMUX_MARK_END, 191 PINMUX_MARK_END,
192}; 192};
193 193
194static pinmux_enum_t pinmux_data[] = { 194static const pinmux_enum_t pinmux_data[] = {
195 195
196 /* PA GPIO */ 196 /* PA GPIO */
197 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), 197 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
@@ -427,7 +427,7 @@ static pinmux_enum_t pinmux_data[] = {
427 PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN), 427 PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
428}; 428};
429 429
430static struct pinmux_gpio pinmux_gpios[] = { 430static struct sh_pfc_pin pinmux_pins[] = {
431 /* PA */ 431 /* PA */
432 PINMUX_GPIO(GPIO_PA7, PA7_DATA), 432 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
433 PINMUX_GPIO(GPIO_PA6, PA6_DATA), 433 PINMUX_GPIO(GPIO_PA6, PA6_DATA),
@@ -505,147 +505,151 @@ static struct pinmux_gpio pinmux_gpios[] = {
505 PINMUX_GPIO(GPIO_PJ3, PJ3_DATA), 505 PINMUX_GPIO(GPIO_PJ3, PJ3_DATA),
506 PINMUX_GPIO(GPIO_PJ2, PJ2_DATA), 506 PINMUX_GPIO(GPIO_PJ2, PJ2_DATA),
507 PINMUX_GPIO(GPIO_PJ1, PJ1_DATA), 507 PINMUX_GPIO(GPIO_PJ1, PJ1_DATA),
508};
509
510#define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins)
508 511
512static const struct pinmux_func pinmux_func_gpios[] = {
509 /* FN */ 513 /* FN */
510 PINMUX_GPIO(GPIO_FN_CDE, CDE_MARK), 514 GPIO_FN(CDE),
511 PINMUX_GPIO(GPIO_FN_ETH_MAGIC, ETH_MAGIC_MARK), 515 GPIO_FN(ETH_MAGIC),
512 PINMUX_GPIO(GPIO_FN_DISP, DISP_MARK), 516 GPIO_FN(DISP),
513 PINMUX_GPIO(GPIO_FN_ETH_LINK, ETH_LINK_MARK), 517 GPIO_FN(ETH_LINK),
514 PINMUX_GPIO(GPIO_FN_DR5, DR5_MARK), 518 GPIO_FN(DR5),
515 PINMUX_GPIO(GPIO_FN_ETH_TX_ER, ETH_TX_ER_MARK), 519 GPIO_FN(ETH_TX_ER),
516 PINMUX_GPIO(GPIO_FN_DR4, DR4_MARK), 520 GPIO_FN(DR4),
517 PINMUX_GPIO(GPIO_FN_ETH_TX_EN, ETH_TX_EN_MARK), 521 GPIO_FN(ETH_TX_EN),
518 PINMUX_GPIO(GPIO_FN_DR3, DR3_MARK), 522 GPIO_FN(DR3),
519 PINMUX_GPIO(GPIO_FN_ETH_TXD3, ETH_TXD3_MARK), 523 GPIO_FN(ETH_TXD3),
520 PINMUX_GPIO(GPIO_FN_DR2, DR2_MARK), 524 GPIO_FN(DR2),
521 PINMUX_GPIO(GPIO_FN_ETH_TXD2, ETH_TXD2_MARK), 525 GPIO_FN(ETH_TXD2),
522 PINMUX_GPIO(GPIO_FN_DR1, DR1_MARK), 526 GPIO_FN(DR1),
523 PINMUX_GPIO(GPIO_FN_ETH_TXD1, ETH_TXD1_MARK), 527 GPIO_FN(ETH_TXD1),
524 PINMUX_GPIO(GPIO_FN_DR0, DR0_MARK), 528 GPIO_FN(DR0),
525 PINMUX_GPIO(GPIO_FN_ETH_TXD0, ETH_TXD0_MARK), 529 GPIO_FN(ETH_TXD0),
526 PINMUX_GPIO(GPIO_FN_VSYNC, VSYNC_MARK), 530 GPIO_FN(VSYNC),
527 PINMUX_GPIO(GPIO_FN_HSPI_CLK, HSPI_CLK_MARK), 531 GPIO_FN(HSPI_CLK),
528 PINMUX_GPIO(GPIO_FN_ODDF, ODDF_MARK), 532 GPIO_FN(ODDF),
529 PINMUX_GPIO(GPIO_FN_HSPI_CS, HSPI_CS_MARK), 533 GPIO_FN(HSPI_CS),
530 PINMUX_GPIO(GPIO_FN_DG5, DG5_MARK), 534 GPIO_FN(DG5),
531 PINMUX_GPIO(GPIO_FN_ETH_MDIO, ETH_MDIO_MARK), 535 GPIO_FN(ETH_MDIO),
532 PINMUX_GPIO(GPIO_FN_DG4, DG4_MARK), 536 GPIO_FN(DG4),
533 PINMUX_GPIO(GPIO_FN_ETH_RX_CLK, ETH_RX_CLK_MARK), 537 GPIO_FN(ETH_RX_CLK),
534 PINMUX_GPIO(GPIO_FN_DG3, DG3_MARK), 538 GPIO_FN(DG3),
535 PINMUX_GPIO(GPIO_FN_ETH_MDC, ETH_MDC_MARK), 539 GPIO_FN(ETH_MDC),
536 PINMUX_GPIO(GPIO_FN_DG2, DG2_MARK), 540 GPIO_FN(DG2),
537 PINMUX_GPIO(GPIO_FN_ETH_COL, ETH_COL_MARK), 541 GPIO_FN(ETH_COL),
538 PINMUX_GPIO(GPIO_FN_DG1, DG1_MARK), 542 GPIO_FN(DG1),
539 PINMUX_GPIO(GPIO_FN_ETH_TX_CLK, ETH_TX_CLK_MARK), 543 GPIO_FN(ETH_TX_CLK),
540 PINMUX_GPIO(GPIO_FN_DG0, DG0_MARK), 544 GPIO_FN(DG0),
541 PINMUX_GPIO(GPIO_FN_ETH_CRS, ETH_CRS_MARK), 545 GPIO_FN(ETH_CRS),
542 PINMUX_GPIO(GPIO_FN_DCLKIN, DCLKIN_MARK), 546 GPIO_FN(DCLKIN),
543 PINMUX_GPIO(GPIO_FN_HSPI_RX, HSPI_RX_MARK), 547 GPIO_FN(HSPI_RX),
544 PINMUX_GPIO(GPIO_FN_HSYNC, HSYNC_MARK), 548 GPIO_FN(HSYNC),
545 PINMUX_GPIO(GPIO_FN_HSPI_TX, HSPI_TX_MARK), 549 GPIO_FN(HSPI_TX),
546 PINMUX_GPIO(GPIO_FN_DB5, DB5_MARK), 550 GPIO_FN(DB5),
547 PINMUX_GPIO(GPIO_FN_ETH_RXD3, ETH_RXD3_MARK), 551 GPIO_FN(ETH_RXD3),
548 PINMUX_GPIO(GPIO_FN_DB4, DB4_MARK), 552 GPIO_FN(DB4),
549 PINMUX_GPIO(GPIO_FN_ETH_RXD2, ETH_RXD2_MARK), 553 GPIO_FN(ETH_RXD2),
550 PINMUX_GPIO(GPIO_FN_DB3, DB3_MARK), 554 GPIO_FN(DB3),
551 PINMUX_GPIO(GPIO_FN_ETH_RXD1, ETH_RXD1_MARK), 555 GPIO_FN(ETH_RXD1),
552 PINMUX_GPIO(GPIO_FN_DB2, DB2_MARK), 556 GPIO_FN(DB2),
553 PINMUX_GPIO(GPIO_FN_ETH_RXD0, ETH_RXD0_MARK), 557 GPIO_FN(ETH_RXD0),
554 PINMUX_GPIO(GPIO_FN_DB1, DB1_MARK), 558 GPIO_FN(DB1),
555 PINMUX_GPIO(GPIO_FN_ETH_RX_DV, ETH_RX_DV_MARK), 559 GPIO_FN(ETH_RX_DV),
556 PINMUX_GPIO(GPIO_FN_DB0, DB0_MARK), 560 GPIO_FN(DB0),
557 PINMUX_GPIO(GPIO_FN_ETH_RX_ER, ETH_RX_ER_MARK), 561 GPIO_FN(ETH_RX_ER),
558 PINMUX_GPIO(GPIO_FN_DCLKOUT, DCLKOUT_MARK), 562 GPIO_FN(DCLKOUT),
559 PINMUX_GPIO(GPIO_FN_SCIF1_SCK, SCIF1_SCK_MARK), 563 GPIO_FN(SCIF1_SCK),
560 PINMUX_GPIO(GPIO_FN_SCIF1_RXD, SCIF1_RXD_MARK), 564 GPIO_FN(SCIF1_RXD),
561 PINMUX_GPIO(GPIO_FN_SCIF1_TXD, SCIF1_TXD_MARK), 565 GPIO_FN(SCIF1_TXD),
562 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), 566 GPIO_FN(DACK1),
563 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), 567 GPIO_FN(BACK),
564 PINMUX_GPIO(GPIO_FN_FALE, FALE_MARK), 568 GPIO_FN(FALE),
565 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), 569 GPIO_FN(DACK0),
566 PINMUX_GPIO(GPIO_FN_FCLE, FCLE_MARK), 570 GPIO_FN(FCLE),
567 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 571 GPIO_FN(DREQ1),
568 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), 572 GPIO_FN(BREQ),
569 PINMUX_GPIO(GPIO_FN_USB_OVC1, USB_OVC1_MARK), 573 GPIO_FN(USB_OVC1),
570 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 574 GPIO_FN(DREQ0),
571 PINMUX_GPIO(GPIO_FN_USB_OVC0, USB_OVC0_MARK), 575 GPIO_FN(USB_OVC0),
572 PINMUX_GPIO(GPIO_FN_USB_PENC1, USB_PENC1_MARK), 576 GPIO_FN(USB_PENC1),
573 PINMUX_GPIO(GPIO_FN_USB_PENC0, USB_PENC0_MARK), 577 GPIO_FN(USB_PENC0),
574 PINMUX_GPIO(GPIO_FN_HAC1_SDOUT, HAC1_SDOUT_MARK), 578 GPIO_FN(HAC1_SDOUT),
575 PINMUX_GPIO(GPIO_FN_SSI1_SDATA, SSI1_SDATA_MARK), 579 GPIO_FN(SSI1_SDATA),
576 PINMUX_GPIO(GPIO_FN_SDIF1CMD, SDIF1CMD_MARK), 580 GPIO_FN(SDIF1CMD),
577 PINMUX_GPIO(GPIO_FN_HAC1_SDIN, HAC1_SDIN_MARK), 581 GPIO_FN(HAC1_SDIN),
578 PINMUX_GPIO(GPIO_FN_SSI1_SCK, SSI1_SCK_MARK), 582 GPIO_FN(SSI1_SCK),
579 PINMUX_GPIO(GPIO_FN_SDIF1CD, SDIF1CD_MARK), 583 GPIO_FN(SDIF1CD),
580 PINMUX_GPIO(GPIO_FN_HAC1_SYNC, HAC1_SYNC_MARK), 584 GPIO_FN(HAC1_SYNC),
581 PINMUX_GPIO(GPIO_FN_SSI1_WS, SSI1_WS_MARK), 585 GPIO_FN(SSI1_WS),
582 PINMUX_GPIO(GPIO_FN_SDIF1WP, SDIF1WP_MARK), 586 GPIO_FN(SDIF1WP),
583 PINMUX_GPIO(GPIO_FN_HAC1_BITCLK, HAC1_BITCLK_MARK), 587 GPIO_FN(HAC1_BITCLK),
584 PINMUX_GPIO(GPIO_FN_SSI1_CLK, SSI1_CLK_MARK), 588 GPIO_FN(SSI1_CLK),
585 PINMUX_GPIO(GPIO_FN_SDIF1CLK, SDIF1CLK_MARK), 589 GPIO_FN(SDIF1CLK),
586 PINMUX_GPIO(GPIO_FN_HAC0_SDOUT, HAC0_SDOUT_MARK), 590 GPIO_FN(HAC0_SDOUT),
587 PINMUX_GPIO(GPIO_FN_SSI0_SDATA, SSI0_SDATA_MARK), 591 GPIO_FN(SSI0_SDATA),
588 PINMUX_GPIO(GPIO_FN_SDIF1D3, SDIF1D3_MARK), 592 GPIO_FN(SDIF1D3),
589 PINMUX_GPIO(GPIO_FN_HAC0_SDIN, HAC0_SDIN_MARK), 593 GPIO_FN(HAC0_SDIN),
590 PINMUX_GPIO(GPIO_FN_SSI0_SCK, SSI0_SCK_MARK), 594 GPIO_FN(SSI0_SCK),
591 PINMUX_GPIO(GPIO_FN_SDIF1D2, SDIF1D2_MARK), 595 GPIO_FN(SDIF1D2),
592 PINMUX_GPIO(GPIO_FN_HAC0_SYNC, HAC0_SYNC_MARK), 596 GPIO_FN(HAC0_SYNC),
593 PINMUX_GPIO(GPIO_FN_SSI0_WS, SSI0_WS_MARK), 597 GPIO_FN(SSI0_WS),
594 PINMUX_GPIO(GPIO_FN_SDIF1D1, SDIF1D1_MARK), 598 GPIO_FN(SDIF1D1),
595 PINMUX_GPIO(GPIO_FN_HAC0_BITCLK, HAC0_BITCLK_MARK), 599 GPIO_FN(HAC0_BITCLK),
596 PINMUX_GPIO(GPIO_FN_SSI0_CLK, SSI0_CLK_MARK), 600 GPIO_FN(SSI0_CLK),
597 PINMUX_GPIO(GPIO_FN_SDIF1D0, SDIF1D0_MARK), 601 GPIO_FN(SDIF1D0),
598 PINMUX_GPIO(GPIO_FN_SCIF3_SCK, SCIF3_SCK_MARK), 602 GPIO_FN(SCIF3_SCK),
599 PINMUX_GPIO(GPIO_FN_SSI2_SDATA, SSI2_SDATA_MARK), 603 GPIO_FN(SSI2_SDATA),
600 PINMUX_GPIO(GPIO_FN_SCIF3_RXD, SCIF3_RXD_MARK), 604 GPIO_FN(SCIF3_RXD),
601 PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK), 605 GPIO_FN(TCLK),
602 PINMUX_GPIO(GPIO_FN_SSI2_SCK, SSI2_SCK_MARK), 606 GPIO_FN(SSI2_SCK),
603 PINMUX_GPIO(GPIO_FN_SCIF3_TXD, SCIF3_TXD_MARK), 607 GPIO_FN(SCIF3_TXD),
604 PINMUX_GPIO(GPIO_FN_HAC_RES, HAC_RES_MARK), 608 GPIO_FN(HAC_RES),
605 PINMUX_GPIO(GPIO_FN_SSI2_WS, SSI2_WS_MARK), 609 GPIO_FN(SSI2_WS),
606 PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), 610 GPIO_FN(DACK3),
607 PINMUX_GPIO(GPIO_FN_SDIF0CMD, SDIF0CMD_MARK), 611 GPIO_FN(SDIF0CMD),
608 PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), 612 GPIO_FN(DACK2),
609 PINMUX_GPIO(GPIO_FN_SDIF0CD, SDIF0CD_MARK), 613 GPIO_FN(SDIF0CD),
610 PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), 614 GPIO_FN(DREQ3),
611 PINMUX_GPIO(GPIO_FN_SDIF0WP, SDIF0WP_MARK), 615 GPIO_FN(SDIF0WP),
612 PINMUX_GPIO(GPIO_FN_SCIF0_CTS, SCIF0_CTS_MARK), 616 GPIO_FN(SCIF0_CTS),
613 PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), 617 GPIO_FN(DREQ2),
614 PINMUX_GPIO(GPIO_FN_SDIF0CLK, SDIF0CLK_MARK), 618 GPIO_FN(SDIF0CLK),
615 PINMUX_GPIO(GPIO_FN_SCIF0_RTS, SCIF0_RTS_MARK), 619 GPIO_FN(SCIF0_RTS),
616 PINMUX_GPIO(GPIO_FN_IRL7, IRL7_MARK), 620 GPIO_FN(IRL7),
617 PINMUX_GPIO(GPIO_FN_SDIF0D3, SDIF0D3_MARK), 621 GPIO_FN(SDIF0D3),
618 PINMUX_GPIO(GPIO_FN_SCIF0_SCK, SCIF0_SCK_MARK), 622 GPIO_FN(SCIF0_SCK),
619 PINMUX_GPIO(GPIO_FN_IRL6, IRL6_MARK), 623 GPIO_FN(IRL6),
620 PINMUX_GPIO(GPIO_FN_SDIF0D2, SDIF0D2_MARK), 624 GPIO_FN(SDIF0D2),
621 PINMUX_GPIO(GPIO_FN_SCIF0_RXD, SCIF0_RXD_MARK), 625 GPIO_FN(SCIF0_RXD),
622 PINMUX_GPIO(GPIO_FN_IRL5, IRL5_MARK), 626 GPIO_FN(IRL5),
623 PINMUX_GPIO(GPIO_FN_SDIF0D1, SDIF0D1_MARK), 627 GPIO_FN(SDIF0D1),
624 PINMUX_GPIO(GPIO_FN_SCIF0_TXD, SCIF0_TXD_MARK), 628 GPIO_FN(SCIF0_TXD),
625 PINMUX_GPIO(GPIO_FN_IRL4, IRL4_MARK), 629 GPIO_FN(IRL4),
626 PINMUX_GPIO(GPIO_FN_SDIF0D0, SDIF0D0_MARK), 630 GPIO_FN(SDIF0D0),
627 PINMUX_GPIO(GPIO_FN_SCIF5_SCK, SCIF5_SCK_MARK), 631 GPIO_FN(SCIF5_SCK),
628 PINMUX_GPIO(GPIO_FN_FRB, FRB_MARK), 632 GPIO_FN(FRB),
629 PINMUX_GPIO(GPIO_FN_SCIF5_RXD, SCIF5_RXD_MARK), 633 GPIO_FN(SCIF5_RXD),
630 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 634 GPIO_FN(IOIS16),
631 PINMUX_GPIO(GPIO_FN_SCIF5_TXD, SCIF5_TXD_MARK), 635 GPIO_FN(SCIF5_TXD),
632 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), 636 GPIO_FN(CE2B),
633 PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), 637 GPIO_FN(DRAK3),
634 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), 638 GPIO_FN(CE2A),
635 PINMUX_GPIO(GPIO_FN_SCIF4_SCK, SCIF4_SCK_MARK), 639 GPIO_FN(SCIF4_SCK),
636 PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), 640 GPIO_FN(DRAK2),
637 PINMUX_GPIO(GPIO_FN_SSI3_WS, SSI3_WS_MARK), 641 GPIO_FN(SSI3_WS),
638 PINMUX_GPIO(GPIO_FN_SCIF4_RXD, SCIF4_RXD_MARK), 642 GPIO_FN(SCIF4_RXD),
639 PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK), 643 GPIO_FN(DRAK1),
640 PINMUX_GPIO(GPIO_FN_SSI3_SDATA, SSI3_SDATA_MARK), 644 GPIO_FN(SSI3_SDATA),
641 PINMUX_GPIO(GPIO_FN_FSTATUS, FSTATUS_MARK), 645 GPIO_FN(FSTATUS),
642 PINMUX_GPIO(GPIO_FN_SCIF4_TXD, SCIF4_TXD_MARK), 646 GPIO_FN(SCIF4_TXD),
643 PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK), 647 GPIO_FN(DRAK0),
644 PINMUX_GPIO(GPIO_FN_SSI3_SCK, SSI3_SCK_MARK), 648 GPIO_FN(SSI3_SCK),
645 PINMUX_GPIO(GPIO_FN_FSE, FSE_MARK), 649 GPIO_FN(FSE),
646}; 650};
647 651
648static struct pinmux_cfg_reg pinmux_config_regs[] = { 652static const struct pinmux_cfg_reg pinmux_config_regs[] = {
649 { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) { 653 { PINMUX_CFG_REG("PACR", 0xffcc0000, 16, 2) {
650 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, 654 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
651 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, 655 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
@@ -775,7 +779,7 @@ static struct pinmux_cfg_reg pinmux_config_regs[] = {
775 {} 779 {}
776}; 780};
777 781
778static struct pinmux_data_reg pinmux_data_regs[] = { 782static const struct pinmux_data_reg pinmux_data_regs[] = {
779 { PINMUX_DATA_REG("PADR", 0xffcc0020, 8) { 783 { PINMUX_DATA_REG("PADR", 0xffcc0020, 8) {
780 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, 784 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
781 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA } 785 PA3_DATA, PA2_DATA, PA1_DATA, PA0_DATA }
@@ -815,20 +819,18 @@ static struct pinmux_data_reg pinmux_data_regs[] = {
815 { }, 819 { },
816}; 820};
817 821
818struct sh_pfc_soc_info sh7786_pinmux_info = { 822const struct sh_pfc_soc_info sh7786_pinmux_info = {
819 .name = "sh7786_pfc", 823 .name = "sh7786_pfc",
820 .reserved_id = PINMUX_RESERVED,
821 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
822 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 824 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
823 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END }, 825 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
824 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 826 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
825 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
826 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 827 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
827 828
828 .first_gpio = GPIO_PA7, 829 .pins = pinmux_pins,
829 .last_gpio = GPIO_FN_IRL4, 830 .nr_pins = ARRAY_SIZE(pinmux_pins),
831 .func_gpios = pinmux_func_gpios,
832 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
830 833
831 .gpios = pinmux_gpios,
832 .cfg_regs = pinmux_config_regs, 834 .cfg_regs = pinmux_config_regs,
833 .data_regs = pinmux_data_regs, 835 .data_regs = pinmux_data_regs,
834 836
diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c
index ccf6918b03c6..6594c8c48747 100644
--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c
+++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c
@@ -147,7 +147,7 @@ enum {
147 PINMUX_MARK_END, 147 PINMUX_MARK_END,
148}; 148};
149 149
150static pinmux_enum_t shx3_pinmux_data[] = { 150static const pinmux_enum_t shx3_pinmux_data[] = {
151 151
152 /* PA GPIO */ 152 /* PA GPIO */
153 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU), 153 PINMUX_DATA(PA7_DATA, PA7_IN, PA7_OUT, PA7_IN_PU),
@@ -306,7 +306,7 @@ static pinmux_enum_t shx3_pinmux_data[] = {
306 PINMUX_DATA(IRQOUT_MARK, PH0_FN), 306 PINMUX_DATA(IRQOUT_MARK, PH0_FN),
307}; 307};
308 308
309static struct pinmux_gpio shx3_pinmux_gpios[] = { 309static struct sh_pfc_pin shx3_pinmux_pins[] = {
310 /* PA */ 310 /* PA */
311 PINMUX_GPIO(GPIO_PA7, PA7_DATA), 311 PINMUX_GPIO(GPIO_PA7, PA7_DATA),
312 PINMUX_GPIO(GPIO_PA6, PA6_DATA), 312 PINMUX_GPIO(GPIO_PA6, PA6_DATA),
@@ -384,73 +384,77 @@ static struct pinmux_gpio shx3_pinmux_gpios[] = {
384 PINMUX_GPIO(GPIO_PH2, PH2_DATA), 384 PINMUX_GPIO(GPIO_PH2, PH2_DATA),
385 PINMUX_GPIO(GPIO_PH1, PH1_DATA), 385 PINMUX_GPIO(GPIO_PH1, PH1_DATA),
386 PINMUX_GPIO(GPIO_PH0, PH0_DATA), 386 PINMUX_GPIO(GPIO_PH0, PH0_DATA),
387};
388
389#define PINMUX_FN_BASE ARRAY_SIZE(shx3_pinmux_pins)
387 390
391static const struct pinmux_func shx3_pinmux_func_gpios[] = {
388 /* FN */ 392 /* FN */
389 PINMUX_GPIO(GPIO_FN_D31, D31_MARK), 393 GPIO_FN(D31),
390 PINMUX_GPIO(GPIO_FN_D30, D30_MARK), 394 GPIO_FN(D30),
391 PINMUX_GPIO(GPIO_FN_D29, D29_MARK), 395 GPIO_FN(D29),
392 PINMUX_GPIO(GPIO_FN_D28, D28_MARK), 396 GPIO_FN(D28),
393 PINMUX_GPIO(GPIO_FN_D27, D27_MARK), 397 GPIO_FN(D27),
394 PINMUX_GPIO(GPIO_FN_D26, D26_MARK), 398 GPIO_FN(D26),
395 PINMUX_GPIO(GPIO_FN_D25, D25_MARK), 399 GPIO_FN(D25),
396 PINMUX_GPIO(GPIO_FN_D24, D24_MARK), 400 GPIO_FN(D24),
397 PINMUX_GPIO(GPIO_FN_D23, D23_MARK), 401 GPIO_FN(D23),
398 PINMUX_GPIO(GPIO_FN_D22, D22_MARK), 402 GPIO_FN(D22),
399 PINMUX_GPIO(GPIO_FN_D21, D21_MARK), 403 GPIO_FN(D21),
400 PINMUX_GPIO(GPIO_FN_D20, D20_MARK), 404 GPIO_FN(D20),
401 PINMUX_GPIO(GPIO_FN_D19, D19_MARK), 405 GPIO_FN(D19),
402 PINMUX_GPIO(GPIO_FN_D18, D18_MARK), 406 GPIO_FN(D18),
403 PINMUX_GPIO(GPIO_FN_D17, D17_MARK), 407 GPIO_FN(D17),
404 PINMUX_GPIO(GPIO_FN_D16, D16_MARK), 408 GPIO_FN(D16),
405 PINMUX_GPIO(GPIO_FN_BACK, BACK_MARK), 409 GPIO_FN(BACK),
406 PINMUX_GPIO(GPIO_FN_BREQ, BREQ_MARK), 410 GPIO_FN(BREQ),
407 PINMUX_GPIO(GPIO_FN_WE3, WE3_MARK), 411 GPIO_FN(WE3),
408 PINMUX_GPIO(GPIO_FN_WE2, WE2_MARK), 412 GPIO_FN(WE2),
409 PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK), 413 GPIO_FN(CS6),
410 PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK), 414 GPIO_FN(CS5),
411 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK), 415 GPIO_FN(CS4),
412 PINMUX_GPIO(GPIO_FN_CLKOUTENB, CLKOUTENB_MARK), 416 GPIO_FN(CLKOUTENB),
413 PINMUX_GPIO(GPIO_FN_DACK3, DACK3_MARK), 417 GPIO_FN(DACK3),
414 PINMUX_GPIO(GPIO_FN_DACK2, DACK2_MARK), 418 GPIO_FN(DACK2),
415 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK), 419 GPIO_FN(DACK1),
416 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK), 420 GPIO_FN(DACK0),
417 PINMUX_GPIO(GPIO_FN_DREQ3, DREQ3_MARK), 421 GPIO_FN(DREQ3),
418 PINMUX_GPIO(GPIO_FN_DREQ2, DREQ2_MARK), 422 GPIO_FN(DREQ2),
419 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK), 423 GPIO_FN(DREQ1),
420 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK), 424 GPIO_FN(DREQ0),
421 PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK), 425 GPIO_FN(IRQ3),
422 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK), 426 GPIO_FN(IRQ2),
423 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK), 427 GPIO_FN(IRQ1),
424 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK), 428 GPIO_FN(IRQ0),
425 PINMUX_GPIO(GPIO_FN_DRAK3, DRAK3_MARK), 429 GPIO_FN(DRAK3),
426 PINMUX_GPIO(GPIO_FN_DRAK2, DRAK2_MARK), 430 GPIO_FN(DRAK2),
427 PINMUX_GPIO(GPIO_FN_DRAK1, DRAK1_MARK), 431 GPIO_FN(DRAK1),
428 PINMUX_GPIO(GPIO_FN_DRAK0, DRAK0_MARK), 432 GPIO_FN(DRAK0),
429 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK), 433 GPIO_FN(SCK3),
430 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK), 434 GPIO_FN(SCK2),
431 PINMUX_GPIO(GPIO_FN_SCK1, SCK1_MARK), 435 GPIO_FN(SCK1),
432 PINMUX_GPIO(GPIO_FN_SCK0, SCK0_MARK), 436 GPIO_FN(SCK0),
433 PINMUX_GPIO(GPIO_FN_IRL3, IRL3_MARK), 437 GPIO_FN(IRL3),
434 PINMUX_GPIO(GPIO_FN_IRL2, IRL2_MARK), 438 GPIO_FN(IRL2),
435 PINMUX_GPIO(GPIO_FN_IRL1, IRL1_MARK), 439 GPIO_FN(IRL1),
436 PINMUX_GPIO(GPIO_FN_IRL0, IRL0_MARK), 440 GPIO_FN(IRL0),
437 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK), 441 GPIO_FN(TXD3),
438 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK), 442 GPIO_FN(TXD2),
439 PINMUX_GPIO(GPIO_FN_TXD1, TXD1_MARK), 443 GPIO_FN(TXD1),
440 PINMUX_GPIO(GPIO_FN_TXD0, TXD0_MARK), 444 GPIO_FN(TXD0),
441 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK), 445 GPIO_FN(RXD3),
442 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK), 446 GPIO_FN(RXD2),
443 PINMUX_GPIO(GPIO_FN_RXD1, RXD1_MARK), 447 GPIO_FN(RXD1),
444 PINMUX_GPIO(GPIO_FN_RXD0, RXD0_MARK), 448 GPIO_FN(RXD0),
445 PINMUX_GPIO(GPIO_FN_CE2B, CE2B_MARK), 449 GPIO_FN(CE2B),
446 PINMUX_GPIO(GPIO_FN_CE2A, CE2A_MARK), 450 GPIO_FN(CE2A),
447 PINMUX_GPIO(GPIO_FN_IOIS16, IOIS16_MARK), 451 GPIO_FN(IOIS16),
448 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK), 452 GPIO_FN(STATUS1),
449 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK), 453 GPIO_FN(STATUS0),
450 PINMUX_GPIO(GPIO_FN_IRQOUT, IRQOUT_MARK), 454 GPIO_FN(IRQOUT),
451}; 455};
452 456
453static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = { 457static const struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
454 { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) { 458 { PINMUX_CFG_REG("PABCR", 0xffc70000, 32, 2) {
455 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU, 459 PA7_FN, PA7_OUT, PA7_IN, PA7_IN_PU,
456 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU, 460 PA6_FN, PA6_OUT, PA6_IN, PA6_IN_PU,
@@ -526,7 +530,7 @@ static struct pinmux_cfg_reg shx3_pinmux_config_regs[] = {
526 { }, 530 { },
527}; 531};
528 532
529static struct pinmux_data_reg shx3_pinmux_data_regs[] = { 533static const struct pinmux_data_reg shx3_pinmux_data_regs[] = {
530 { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) { 534 { PINMUX_DATA_REG("PABDR", 0xffc70010, 32) {
531 0, 0, 0, 0, 0, 0, 0, 0, 535 0, 0, 0, 0, 0, 0, 0, 0,
532 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA, 536 PA7_DATA, PA6_DATA, PA5_DATA, PA4_DATA,
@@ -562,19 +566,17 @@ static struct pinmux_data_reg shx3_pinmux_data_regs[] = {
562 { }, 566 { },
563}; 567};
564 568
565struct sh_pfc_soc_info shx3_pinmux_info = { 569const struct sh_pfc_soc_info shx3_pinmux_info = {
566 .name = "shx3_pfc", 570 .name = "shx3_pfc",
567 .reserved_id = PINMUX_RESERVED,
568 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
569 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 571 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
570 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, 572 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN,
571 PINMUX_INPUT_PULLUP_END }, 573 PINMUX_INPUT_PULLUP_END },
572 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 574 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
573 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
574 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 575 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
575 .first_gpio = GPIO_PA7, 576 .pins = shx3_pinmux_pins,
576 .last_gpio = GPIO_FN_STATUS0, 577 .nr_pins = ARRAY_SIZE(shx3_pinmux_pins),
577 .gpios = shx3_pinmux_gpios, 578 .func_gpios = shx3_pinmux_func_gpios,
579 .nr_func_gpios = ARRAY_SIZE(shx3_pinmux_func_gpios),
578 .gpio_data = shx3_pinmux_data, 580 .gpio_data = shx3_pinmux_data,
579 .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data), 581 .gpio_data_size = ARRAY_SIZE(shx3_pinmux_data),
580 .cfg_regs = shx3_pinmux_config_regs, 582 .cfg_regs = shx3_pinmux_config_regs,
diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/sh-pfc/pinctrl.c
index 11e0e1374d65..3492ec9a33b7 100644
--- a/drivers/pinctrl/sh-pfc/pinctrl.c
+++ b/drivers/pinctrl/sh-pfc/pinctrl.c
@@ -9,7 +9,6 @@
9 */ 9 */
10 10
11#define DRV_NAME "sh-pfc" 11#define DRV_NAME "sh-pfc"
12#define pr_fmt(fmt) KBUILD_MODNAME " pinctrl: " fmt
13 12
14#include <linux/device.h> 13#include <linux/device.h>
15#include <linux/err.h> 14#include <linux/err.h>
@@ -24,25 +23,28 @@
24#include <linux/spinlock.h> 23#include <linux/spinlock.h>
25 24
26#include "core.h" 25#include "core.h"
26#include "../core.h"
27#include "../pinconf.h"
28
29struct sh_pfc_pin_config {
30 u32 type;
31};
27 32
28struct sh_pfc_pinctrl { 33struct sh_pfc_pinctrl {
29 struct pinctrl_dev *pctl; 34 struct pinctrl_dev *pctl;
30 struct sh_pfc *pfc; 35 struct pinctrl_desc pctl_desc;
31
32 struct pinmux_gpio **functions;
33 unsigned int nr_functions;
34 36
35 struct pinctrl_pin_desc *pads; 37 struct sh_pfc *pfc;
36 unsigned int nr_pads;
37 38
38 spinlock_t lock; 39 struct pinctrl_pin_desc *pins;
40 struct sh_pfc_pin_config *configs;
39}; 41};
40 42
41static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev) 43static int sh_pfc_get_groups_count(struct pinctrl_dev *pctldev)
42{ 44{
43 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 45 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
44 46
45 return pmx->nr_pads; 47 return pmx->pfc->info->nr_groups;
46} 48}
47 49
48static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev, 50static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
@@ -50,16 +52,16 @@ static const char *sh_pfc_get_group_name(struct pinctrl_dev *pctldev,
50{ 52{
51 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 53 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
52 54
53 return pmx->pads[selector].name; 55 return pmx->pfc->info->groups[selector].name;
54} 56}
55 57
56static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned group, 58static int sh_pfc_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
57 const unsigned **pins, unsigned *num_pins) 59 const unsigned **pins, unsigned *num_pins)
58{ 60{
59 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 61 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
60 62
61 *pins = &pmx->pads[group].number; 63 *pins = pmx->pfc->info->groups[selector].pins;
62 *num_pins = 1; 64 *num_pins = pmx->pfc->info->groups[selector].nr_pins;
63 65
64 return 0; 66 return 0;
65} 67}
@@ -70,7 +72,7 @@ static void sh_pfc_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
70 seq_printf(s, "%s", DRV_NAME); 72 seq_printf(s, "%s", DRV_NAME);
71} 73}
72 74
73static struct pinctrl_ops sh_pfc_pinctrl_ops = { 75static const struct pinctrl_ops sh_pfc_pinctrl_ops = {
74 .get_groups_count = sh_pfc_get_groups_count, 76 .get_groups_count = sh_pfc_get_groups_count,
75 .get_group_name = sh_pfc_get_group_name, 77 .get_group_name = sh_pfc_get_group_name,
76 .get_group_pins = sh_pfc_get_group_pins, 78 .get_group_pins = sh_pfc_get_group_pins,
@@ -81,7 +83,7 @@ static int sh_pfc_get_functions_count(struct pinctrl_dev *pctldev)
81{ 83{
82 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 84 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
83 85
84 return pmx->nr_functions; 86 return pmx->pfc->info->nr_functions;
85} 87}
86 88
87static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev, 89static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
@@ -89,136 +91,113 @@ static const char *sh_pfc_get_function_name(struct pinctrl_dev *pctldev,
89{ 91{
90 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 92 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
91 93
92 return pmx->functions[selector]->name; 94 return pmx->pfc->info->functions[selector].name;
93} 95}
94 96
95static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev, unsigned func, 97static int sh_pfc_get_function_groups(struct pinctrl_dev *pctldev,
98 unsigned selector,
96 const char * const **groups, 99 const char * const **groups,
97 unsigned * const num_groups) 100 unsigned * const num_groups)
98{ 101{
99 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 102 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
100 103
101 *groups = &pmx->functions[func]->name; 104 *groups = pmx->pfc->info->functions[selector].groups;
102 *num_groups = 1; 105 *num_groups = pmx->pfc->info->functions[selector].nr_groups;
103 106
104 return 0; 107 return 0;
105} 108}
106 109
107static int sh_pfc_noop_enable(struct pinctrl_dev *pctldev, unsigned func, 110static int sh_pfc_func_enable(struct pinctrl_dev *pctldev, unsigned selector,
108 unsigned group) 111 unsigned group)
109{ 112{
110 return 0; 113 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
111} 114 struct sh_pfc *pfc = pmx->pfc;
115 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
116 unsigned long flags;
117 unsigned int i;
118 int ret = 0;
112 119
113static void sh_pfc_noop_disable(struct pinctrl_dev *pctldev, unsigned func, 120 spin_lock_irqsave(&pfc->lock, flags);
114 unsigned group)
115{
116}
117 121
118static int sh_pfc_config_function(struct sh_pfc *pfc, unsigned offset) 122 for (i = 0; i < grp->nr_pins; ++i) {
119{ 123 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
120 if (sh_pfc_config_gpio(pfc, offset, 124 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
121 PINMUX_TYPE_FUNCTION,
122 GPIO_CFG_DRYRUN) != 0)
123 return -EINVAL;
124 125
125 if (sh_pfc_config_gpio(pfc, offset, 126 if (cfg->type != PINMUX_TYPE_NONE) {
126 PINMUX_TYPE_FUNCTION, 127 ret = -EBUSY;
127 GPIO_CFG_REQ) != 0) 128 goto done;
128 return -EINVAL; 129 }
130 }
129 131
130 return 0; 132 for (i = 0; i < grp->nr_pins; ++i) {
133 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
134 if (ret < 0)
135 break;
136 }
137
138done:
139 spin_unlock_irqrestore(&pfc->lock, flags);
140 return ret;
131} 141}
132 142
133static int sh_pfc_reconfig_pin(struct sh_pfc *pfc, unsigned offset, 143static void sh_pfc_func_disable(struct pinctrl_dev *pctldev, unsigned selector,
134 int new_type) 144 unsigned group)
135{ 145{
146 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
147 struct sh_pfc *pfc = pmx->pfc;
148 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group];
136 unsigned long flags; 149 unsigned long flags;
137 int pinmux_type; 150 unsigned int i;
138 int ret = -EINVAL;
139 151
140 spin_lock_irqsave(&pfc->lock, flags); 152 spin_lock_irqsave(&pfc->lock, flags);
141 153
142 pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; 154 for (i = 0; i < grp->nr_pins; ++i) {
155 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
156 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
143 157
144 /* 158 cfg->type = PINMUX_TYPE_NONE;
145 * See if the present config needs to first be de-configured.
146 */
147 switch (pinmux_type) {
148 case PINMUX_TYPE_GPIO:
149 break;
150 case PINMUX_TYPE_OUTPUT:
151 case PINMUX_TYPE_INPUT:
152 case PINMUX_TYPE_INPUT_PULLUP:
153 case PINMUX_TYPE_INPUT_PULLDOWN:
154 sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
155 break;
156 default:
157 goto err;
158 } 159 }
159 160
160 /*
161 * Dry run
162 */
163 if (sh_pfc_config_gpio(pfc, offset, new_type,
164 GPIO_CFG_DRYRUN) != 0)
165 goto err;
166
167 /*
168 * Request
169 */
170 if (sh_pfc_config_gpio(pfc, offset, new_type,
171 GPIO_CFG_REQ) != 0)
172 goto err;
173
174 pfc->info->gpios[offset].flags &= ~PINMUX_FLAG_TYPE;
175 pfc->info->gpios[offset].flags |= new_type;
176
177 ret = 0;
178
179err:
180 spin_unlock_irqrestore(&pfc->lock, flags); 161 spin_unlock_irqrestore(&pfc->lock, flags);
181
182 return ret;
183} 162}
184 163
185
186static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev, 164static int sh_pfc_gpio_request_enable(struct pinctrl_dev *pctldev,
187 struct pinctrl_gpio_range *range, 165 struct pinctrl_gpio_range *range,
188 unsigned offset) 166 unsigned offset)
189{ 167{
190 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 168 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
191 struct sh_pfc *pfc = pmx->pfc; 169 struct sh_pfc *pfc = pmx->pfc;
170 int idx = sh_pfc_get_pin_index(pfc, offset);
171 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
192 unsigned long flags; 172 unsigned long flags;
193 int ret, pinmux_type; 173 int ret;
194 174
195 spin_lock_irqsave(&pfc->lock, flags); 175 spin_lock_irqsave(&pfc->lock, flags);
196 176
197 pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE; 177 if (cfg->type != PINMUX_TYPE_NONE) {
178 dev_err(pfc->dev,
179 "Pin %u is busy, can't configure it as GPIO.\n",
180 offset);
181 ret = -EBUSY;
182 goto done;
183 }
198 184
199 switch (pinmux_type) { 185 if (!pfc->gpio) {
200 case PINMUX_TYPE_FUNCTION: 186 /* If GPIOs are handled externally the pin mux type need to be
201 pr_notice_once("Use of GPIO API for function requests is " 187 * set to GPIO here.
202 "deprecated, convert to pinctrl\n"); 188 */
203 /* handle for now */ 189 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
204 ret = sh_pfc_config_function(pfc, offset);
205 if (unlikely(ret < 0))
206 goto err;
207 190
208 break; 191 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
209 case PINMUX_TYPE_GPIO: 192 if (ret < 0)
210 case PINMUX_TYPE_INPUT: 193 goto done;
211 case PINMUX_TYPE_OUTPUT:
212 break;
213 default:
214 pr_err("Unsupported mux type (%d), bailing...\n", pinmux_type);
215 ret = -ENOTSUPP;
216 goto err;
217 } 194 }
218 195
196 cfg->type = PINMUX_TYPE_GPIO;
197
219 ret = 0; 198 ret = 0;
220 199
221err: 200done:
222 spin_unlock_irqrestore(&pfc->lock, flags); 201 spin_unlock_irqrestore(&pfc->lock, flags);
223 202
224 return ret; 203 return ret;
@@ -230,15 +209,12 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
230{ 209{
231 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 210 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
232 struct sh_pfc *pfc = pmx->pfc; 211 struct sh_pfc *pfc = pmx->pfc;
212 int idx = sh_pfc_get_pin_index(pfc, offset);
213 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
233 unsigned long flags; 214 unsigned long flags;
234 int pinmux_type;
235 215
236 spin_lock_irqsave(&pfc->lock, flags); 216 spin_lock_irqsave(&pfc->lock, flags);
237 217 cfg->type = PINMUX_TYPE_NONE;
238 pinmux_type = pfc->info->gpios[offset].flags & PINMUX_FLAG_TYPE;
239
240 sh_pfc_config_gpio(pfc, offset, pinmux_type, GPIO_CFG_FREE);
241
242 spin_unlock_irqrestore(&pfc->lock, flags); 218 spin_unlock_irqrestore(&pfc->lock, flags);
243} 219}
244 220
@@ -247,207 +223,242 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
247 unsigned offset, bool input) 223 unsigned offset, bool input)
248{ 224{
249 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 225 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
250 int type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT; 226 struct sh_pfc *pfc = pmx->pfc;
227 int new_type = input ? PINMUX_TYPE_INPUT : PINMUX_TYPE_OUTPUT;
228 int idx = sh_pfc_get_pin_index(pfc, offset);
229 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
230 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
231 unsigned long flags;
232 unsigned int dir;
233 int ret;
234
235 /* Check if the requested direction is supported by the pin. Not all SoC
236 * provide pin config data, so perform the check conditionally.
237 */
238 if (pin->configs) {
239 dir = input ? SH_PFC_PIN_CFG_INPUT : SH_PFC_PIN_CFG_OUTPUT;
240 if (!(pin->configs & dir))
241 return -EINVAL;
242 }
243
244 spin_lock_irqsave(&pfc->lock, flags);
245
246 ret = sh_pfc_config_mux(pfc, pin->enum_id, new_type);
247 if (ret < 0)
248 goto done;
249
250 cfg->type = new_type;
251 251
252 return sh_pfc_reconfig_pin(pmx->pfc, offset, type); 252done:
253 spin_unlock_irqrestore(&pfc->lock, flags);
254 return ret;
253} 255}
254 256
255static struct pinmux_ops sh_pfc_pinmux_ops = { 257static const struct pinmux_ops sh_pfc_pinmux_ops = {
256 .get_functions_count = sh_pfc_get_functions_count, 258 .get_functions_count = sh_pfc_get_functions_count,
257 .get_function_name = sh_pfc_get_function_name, 259 .get_function_name = sh_pfc_get_function_name,
258 .get_function_groups = sh_pfc_get_function_groups, 260 .get_function_groups = sh_pfc_get_function_groups,
259 .enable = sh_pfc_noop_enable, 261 .enable = sh_pfc_func_enable,
260 .disable = sh_pfc_noop_disable, 262 .disable = sh_pfc_func_disable,
261 .gpio_request_enable = sh_pfc_gpio_request_enable, 263 .gpio_request_enable = sh_pfc_gpio_request_enable,
262 .gpio_disable_free = sh_pfc_gpio_disable_free, 264 .gpio_disable_free = sh_pfc_gpio_disable_free,
263 .gpio_set_direction = sh_pfc_gpio_set_direction, 265 .gpio_set_direction = sh_pfc_gpio_set_direction,
264}; 266};
265 267
266static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin, 268/* Check whether the requested parameter is supported for a pin. */
267 unsigned long *config) 269static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
270 enum pin_config_param param)
268{ 271{
269 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev); 272 int idx = sh_pfc_get_pin_index(pfc, _pin);
270 struct sh_pfc *pfc = pmx->pfc; 273 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
271 274
272 *config = pfc->info->gpios[pin].flags & PINMUX_FLAG_TYPE; 275 switch (param) {
276 case PIN_CONFIG_BIAS_DISABLE:
277 return true;
273 278
274 return 0; 279 case PIN_CONFIG_BIAS_PULL_UP:
275} 280 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
276 281
277static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin, 282 case PIN_CONFIG_BIAS_PULL_DOWN:
278 unsigned long config) 283 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
279{
280 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
281
282 /* Validate the new type */
283 if (config >= PINMUX_FLAG_TYPE)
284 return -EINVAL;
285 284
286 return sh_pfc_reconfig_pin(pmx->pfc, pin, config); 285 default:
286 return false;
287 }
287} 288}
288 289
289static void sh_pfc_pinconf_dbg_show(struct pinctrl_dev *pctldev, 290static int sh_pfc_pinconf_get(struct pinctrl_dev *pctldev, unsigned _pin,
290 struct seq_file *s, unsigned pin) 291 unsigned long *config)
291{ 292{
292 const char *pinmux_type_str[] = { 293 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
293 [PINMUX_TYPE_NONE] = "none", 294 struct sh_pfc *pfc = pmx->pfc;
294 [PINMUX_TYPE_FUNCTION] = "function", 295 enum pin_config_param param = pinconf_to_config_param(*config);
295 [PINMUX_TYPE_GPIO] = "gpio", 296 unsigned long flags;
296 [PINMUX_TYPE_OUTPUT] = "output", 297 unsigned int bias;
297 [PINMUX_TYPE_INPUT] = "input",
298 [PINMUX_TYPE_INPUT_PULLUP] = "input bias pull up",
299 [PINMUX_TYPE_INPUT_PULLDOWN] = "input bias pull down",
300 };
301 unsigned long config;
302 int rc;
303
304 rc = sh_pfc_pinconf_get(pctldev, pin, &config);
305 if (unlikely(rc != 0))
306 return;
307
308 seq_printf(s, " %s", pinmux_type_str[config]);
309}
310 298
311static struct pinconf_ops sh_pfc_pinconf_ops = { 299 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
312 .pin_config_get = sh_pfc_pinconf_get, 300 return -ENOTSUPP;
313 .pin_config_set = sh_pfc_pinconf_set,
314 .pin_config_dbg_show = sh_pfc_pinconf_dbg_show,
315};
316 301
317static struct pinctrl_gpio_range sh_pfc_gpio_range = { 302 switch (param) {
318 .name = DRV_NAME, 303 case PIN_CONFIG_BIAS_DISABLE:
319 .id = 0, 304 case PIN_CONFIG_BIAS_PULL_UP:
320}; 305 case PIN_CONFIG_BIAS_PULL_DOWN:
306 if (!pfc->info->ops || !pfc->info->ops->get_bias)
307 return -ENOTSUPP;
321 308
322static struct pinctrl_desc sh_pfc_pinctrl_desc = { 309 spin_lock_irqsave(&pfc->lock, flags);
323 .name = DRV_NAME, 310 bias = pfc->info->ops->get_bias(pfc, _pin);
324 .owner = THIS_MODULE, 311 spin_unlock_irqrestore(&pfc->lock, flags);
325 .pctlops = &sh_pfc_pinctrl_ops,
326 .pmxops = &sh_pfc_pinmux_ops,
327 .confops = &sh_pfc_pinconf_ops,
328};
329 312
330static void sh_pfc_map_one_gpio(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx, 313 if (bias != param)
331 struct pinmux_gpio *gpio, unsigned offset) 314 return -EINVAL;
332{
333 struct pinmux_data_reg *dummy;
334 unsigned long flags;
335 int bit;
336
337 gpio->flags &= ~PINMUX_FLAG_TYPE;
338 315
339 if (sh_pfc_get_data_reg(pfc, offset, &dummy, &bit) == 0) 316 *config = 0;
340 gpio->flags |= PINMUX_TYPE_GPIO; 317 break;
341 else {
342 gpio->flags |= PINMUX_TYPE_FUNCTION;
343 318
344 spin_lock_irqsave(&pmx->lock, flags); 319 default:
345 pmx->nr_functions++; 320 return -ENOTSUPP;
346 spin_unlock_irqrestore(&pmx->lock, flags);
347 } 321 }
322
323 return 0;
348} 324}
349 325
350/* pinmux ranges -> pinctrl pin descs */ 326static int sh_pfc_pinconf_set(struct pinctrl_dev *pctldev, unsigned _pin,
351static int sh_pfc_map_gpios(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) 327 unsigned long config)
352{ 328{
329 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
330 struct sh_pfc *pfc = pmx->pfc;
331 enum pin_config_param param = pinconf_to_config_param(config);
353 unsigned long flags; 332 unsigned long flags;
354 int i;
355 333
356 pmx->nr_pads = pfc->info->last_gpio - pfc->info->first_gpio + 1; 334 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
335 return -ENOTSUPP;
357 336
358 pmx->pads = devm_kzalloc(pfc->dev, sizeof(*pmx->pads) * pmx->nr_pads, 337 switch (param) {
359 GFP_KERNEL); 338 case PIN_CONFIG_BIAS_PULL_UP:
360 if (unlikely(!pmx->pads)) { 339 case PIN_CONFIG_BIAS_PULL_DOWN:
361 pmx->nr_pads = 0; 340 case PIN_CONFIG_BIAS_DISABLE:
362 return -ENOMEM; 341 if (!pfc->info->ops || !pfc->info->ops->set_bias)
363 } 342 return -ENOTSUPP;
364 343
365 spin_lock_irqsave(&pfc->lock, flags); 344 spin_lock_irqsave(&pfc->lock, flags);
345 pfc->info->ops->set_bias(pfc, _pin, param);
346 spin_unlock_irqrestore(&pfc->lock, flags);
366 347
367 /* 348 break;
368 * We don't necessarily have a 1:1 mapping between pin and linux
369 * GPIO number, as the latter maps to the associated enum_id.
370 * Care needs to be taken to translate back to pin space when
371 * dealing with any pin configurations.
372 */
373 for (i = 0; i < pmx->nr_pads; i++) {
374 struct pinctrl_pin_desc *pin = pmx->pads + i;
375 struct pinmux_gpio *gpio = pfc->info->gpios + i;
376 349
377 pin->number = pfc->info->first_gpio + i; 350 default:
378 pin->name = gpio->name; 351 return -ENOTSUPP;
352 }
379 353
380 /* XXX */ 354 return 0;
381 if (unlikely(!gpio->enum_id)) 355}
382 continue;
383 356
384 sh_pfc_map_one_gpio(pfc, pmx, gpio, i); 357static int sh_pfc_pinconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
385 } 358 unsigned long config)
359{
360 struct sh_pfc_pinctrl *pmx = pinctrl_dev_get_drvdata(pctldev);
361 const unsigned int *pins;
362 unsigned int num_pins;
363 unsigned int i;
386 364
387 spin_unlock_irqrestore(&pfc->lock, flags); 365 pins = pmx->pfc->info->groups[group].pins;
366 num_pins = pmx->pfc->info->groups[group].nr_pins;
388 367
389 sh_pfc_pinctrl_desc.pins = pmx->pads; 368 for (i = 0; i < num_pins; ++i)
390 sh_pfc_pinctrl_desc.npins = pmx->nr_pads; 369 sh_pfc_pinconf_set(pctldev, pins[i], config);
391 370
392 return 0; 371 return 0;
393} 372}
394 373
395static int sh_pfc_map_functions(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx) 374static const struct pinconf_ops sh_pfc_pinconf_ops = {
375 .is_generic = true,
376 .pin_config_get = sh_pfc_pinconf_get,
377 .pin_config_set = sh_pfc_pinconf_set,
378 .pin_config_group_set = sh_pfc_pinconf_group_set,
379 .pin_config_config_dbg_show = pinconf_generic_dump_config,
380};
381
382/* PFC ranges -> pinctrl pin descs */
383static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
396{ 384{
397 unsigned long flags; 385 const struct pinmux_range *ranges;
398 int i, fn; 386 struct pinmux_range def_range;
387 unsigned int nr_ranges;
388 unsigned int nr_pins;
389 unsigned int i;
390
391 if (pfc->info->ranges == NULL) {
392 def_range.begin = 0;
393 def_range.end = pfc->info->nr_pins - 1;
394 ranges = &def_range;
395 nr_ranges = 1;
396 } else {
397 ranges = pfc->info->ranges;
398 nr_ranges = pfc->info->nr_ranges;
399 }
399 400
400 pmx->functions = devm_kzalloc(pfc->dev, pmx->nr_functions * 401 pmx->pins = devm_kzalloc(pfc->dev,
401 sizeof(*pmx->functions), GFP_KERNEL); 402 sizeof(*pmx->pins) * pfc->info->nr_pins,
402 if (unlikely(!pmx->functions)) 403 GFP_KERNEL);
404 if (unlikely(!pmx->pins))
403 return -ENOMEM; 405 return -ENOMEM;
404 406
405 spin_lock_irqsave(&pmx->lock, flags); 407 pmx->configs = devm_kzalloc(pfc->dev,
406 408 sizeof(*pmx->configs) * pfc->info->nr_pins,
407 for (i = fn = 0; i < pmx->nr_pads; i++) { 409 GFP_KERNEL);
408 struct pinmux_gpio *gpio = pfc->info->gpios + i; 410 if (unlikely(!pmx->configs))
411 return -ENOMEM;
409 412
410 if ((gpio->flags & PINMUX_FLAG_TYPE) == PINMUX_TYPE_FUNCTION) 413 for (i = 0, nr_pins = 0; i < nr_ranges; ++i) {
411 pmx->functions[fn++] = gpio; 414 const struct pinmux_range *range = &ranges[i];
415 unsigned int number;
416
417 for (number = range->begin; number <= range->end;
418 number++, nr_pins++) {
419 struct sh_pfc_pin_config *cfg = &pmx->configs[nr_pins];
420 struct pinctrl_pin_desc *pin = &pmx->pins[nr_pins];
421 const struct sh_pfc_pin *info =
422 &pfc->info->pins[nr_pins];
423
424 pin->number = number;
425 pin->name = info->name;
426 cfg->type = PINMUX_TYPE_NONE;
427 }
412 } 428 }
413 429
414 spin_unlock_irqrestore(&pmx->lock, flags); 430 pfc->nr_pins = ranges[nr_ranges-1].end + 1;
415 431
416 return 0; 432 return nr_ranges;
417} 433}
418 434
419int sh_pfc_register_pinctrl(struct sh_pfc *pfc) 435int sh_pfc_register_pinctrl(struct sh_pfc *pfc)
420{ 436{
421 struct sh_pfc_pinctrl *pmx; 437 struct sh_pfc_pinctrl *pmx;
422 int ret; 438 int nr_ranges;
423 439
424 pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL); 440 pmx = devm_kzalloc(pfc->dev, sizeof(*pmx), GFP_KERNEL);
425 if (unlikely(!pmx)) 441 if (unlikely(!pmx))
426 return -ENOMEM; 442 return -ENOMEM;
427 443
428 spin_lock_init(&pmx->lock);
429
430 pmx->pfc = pfc; 444 pmx->pfc = pfc;
431 pfc->pinctrl = pmx; 445 pfc->pinctrl = pmx;
432 446
433 ret = sh_pfc_map_gpios(pfc, pmx); 447 nr_ranges = sh_pfc_map_pins(pfc, pmx);
434 if (unlikely(ret != 0)) 448 if (unlikely(nr_ranges < 0))
435 return ret; 449 return nr_ranges;
436 450
437 ret = sh_pfc_map_functions(pfc, pmx); 451 pmx->pctl_desc.name = DRV_NAME;
438 if (unlikely(ret != 0)) 452 pmx->pctl_desc.owner = THIS_MODULE;
439 return ret; 453 pmx->pctl_desc.pctlops = &sh_pfc_pinctrl_ops;
454 pmx->pctl_desc.pmxops = &sh_pfc_pinmux_ops;
455 pmx->pctl_desc.confops = &sh_pfc_pinconf_ops;
456 pmx->pctl_desc.pins = pmx->pins;
457 pmx->pctl_desc.npins = pfc->info->nr_pins;
440 458
441 pmx->pctl = pinctrl_register(&sh_pfc_pinctrl_desc, pfc->dev, pmx); 459 pmx->pctl = pinctrl_register(&pmx->pctl_desc, pfc->dev, pmx);
442 if (IS_ERR(pmx->pctl)) 460 if (pmx->pctl == NULL)
443 return PTR_ERR(pmx->pctl); 461 return -EINVAL;
444
445 sh_pfc_gpio_range.npins = pfc->info->last_gpio
446 - pfc->info->first_gpio + 1;
447 sh_pfc_gpio_range.base = pfc->info->first_gpio;
448 sh_pfc_gpio_range.pin_base = pfc->info->first_gpio;
449
450 pinctrl_add_gpio_range(pmx->pctl, &sh_pfc_gpio_range);
451 462
452 return 0; 463 return 0;
453} 464}
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 13049c4c8d30..3b785fc428d5 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -15,7 +15,8 @@
15#include <asm-generic/gpio.h> 15#include <asm-generic/gpio.h>
16 16
17typedef unsigned short pinmux_enum_t; 17typedef unsigned short pinmux_enum_t;
18typedef unsigned short pinmux_flag_t; 18
19#define SH_PFC_MARK_INVALID ((pinmux_enum_t)-1)
19 20
20enum { 21enum {
21 PINMUX_TYPE_NONE, 22 PINMUX_TYPE_NONE,
@@ -30,44 +31,81 @@ enum {
30 PINMUX_FLAG_TYPE, /* must be last */ 31 PINMUX_FLAG_TYPE, /* must be last */
31}; 32};
32 33
33#define PINMUX_FLAG_DBIT_SHIFT 5 34#define SH_PFC_PIN_CFG_INPUT (1 << 0)
34#define PINMUX_FLAG_DBIT (0x1f << PINMUX_FLAG_DBIT_SHIFT) 35#define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
35#define PINMUX_FLAG_DREG_SHIFT 10 36#define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
36#define PINMUX_FLAG_DREG (0x3f << PINMUX_FLAG_DREG_SHIFT) 37#define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
37 38
38struct pinmux_gpio { 39struct sh_pfc_pin {
39 pinmux_enum_t enum_id; 40 const pinmux_enum_t enum_id;
40 pinmux_flag_t flags;
41 const char *name; 41 const char *name;
42 unsigned int configs;
42}; 43};
43 44
44#define PINMUX_GPIO(gpio, data_or_mark) \ 45#define SH_PFC_PIN_GROUP(n) \
45 [gpio] = { .name = __stringify(gpio), .enum_id = data_or_mark, .flags = PINMUX_TYPE_NONE } 46 { \
47 .name = #n, \
48 .pins = n##_pins, \
49 .mux = n##_mux, \
50 .nr_pins = ARRAY_SIZE(n##_pins), \
51 }
52
53struct sh_pfc_pin_group {
54 const char *name;
55 const unsigned int *pins;
56 const unsigned int *mux;
57 unsigned int nr_pins;
58};
59
60#define SH_PFC_FUNCTION(n) \
61 { \
62 .name = #n, \
63 .groups = n##_groups, \
64 .nr_groups = ARRAY_SIZE(n##_groups), \
65 }
66
67struct sh_pfc_function {
68 const char *name;
69 const char * const *groups;
70 unsigned int nr_groups;
71};
72
73struct pinmux_func {
74 const pinmux_enum_t enum_id;
75 const char *name;
76};
77
78#define PINMUX_GPIO(gpio, data_or_mark) \
79 [gpio] = { \
80 .name = __stringify(gpio), \
81 .enum_id = data_or_mark, \
82 }
83#define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
84 [gpio - (base)] = { \
85 .name = __stringify(gpio), \
86 .enum_id = data_or_mark, \
87 }
46 88
47#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0 89#define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
48 90
49struct pinmux_cfg_reg { 91struct pinmux_cfg_reg {
50 unsigned long reg, reg_width, field_width; 92 unsigned long reg, reg_width, field_width;
51 unsigned long *cnt; 93 const pinmux_enum_t *enum_ids;
52 pinmux_enum_t *enum_ids; 94 const unsigned long *var_field_width;
53 unsigned long *var_field_width;
54}; 95};
55 96
56#define PINMUX_CFG_REG(name, r, r_width, f_width) \ 97#define PINMUX_CFG_REG(name, r, r_width, f_width) \
57 .reg = r, .reg_width = r_width, .field_width = f_width, \ 98 .reg = r, .reg_width = r_width, .field_width = f_width, \
58 .cnt = (unsigned long [r_width / f_width]) {}, \
59 .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) 99 .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
60 100
61#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ 101#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
62 .reg = r, .reg_width = r_width, \ 102 .reg = r, .reg_width = r_width, \
63 .cnt = (unsigned long [r_width]) {}, \
64 .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \ 103 .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
65 .enum_ids = (pinmux_enum_t []) 104 .enum_ids = (pinmux_enum_t [])
66 105
67struct pinmux_data_reg { 106struct pinmux_data_reg {
68 unsigned long reg, reg_width, reg_shadow; 107 unsigned long reg, reg_width;
69 pinmux_enum_t *enum_ids; 108 const pinmux_enum_t *enum_ids;
70 void __iomem *mapped_reg;
71}; 109};
72 110
73#define PINMUX_DATA_REG(name, r, r_width) \ 111#define PINMUX_DATA_REG(name, r, r_width) \
@@ -76,11 +114,11 @@ struct pinmux_data_reg {
76 114
77struct pinmux_irq { 115struct pinmux_irq {
78 int irq; 116 int irq;
79 pinmux_enum_t *enum_ids; 117 unsigned short *gpios;
80}; 118};
81 119
82#define PINMUX_IRQ(irq_nr, ids...) \ 120#define PINMUX_IRQ(irq_nr, ids...) \
83 { .irq = irq_nr, .enum_ids = (pinmux_enum_t []) { ids, 0 } } \ 121 { .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \
84 122
85struct pinmux_range { 123struct pinmux_range {
86 pinmux_enum_t begin; 124 pinmux_enum_t begin;
@@ -88,33 +126,49 @@ struct pinmux_range {
88 pinmux_enum_t force; 126 pinmux_enum_t force;
89}; 127};
90 128
129struct sh_pfc;
130
131struct sh_pfc_soc_operations {
132 unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
133 void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
134 unsigned int bias);
135};
136
91struct sh_pfc_soc_info { 137struct sh_pfc_soc_info {
92 char *name; 138 const char *name;
93 pinmux_enum_t reserved_id; 139 const struct sh_pfc_soc_operations *ops;
94 struct pinmux_range data; 140
95 struct pinmux_range input; 141 struct pinmux_range input;
96 struct pinmux_range input_pd; 142 struct pinmux_range input_pd;
97 struct pinmux_range input_pu; 143 struct pinmux_range input_pu;
98 struct pinmux_range output; 144 struct pinmux_range output;
99 struct pinmux_range mark;
100 struct pinmux_range function; 145 struct pinmux_range function;
101 146
102 unsigned first_gpio, last_gpio; 147 const struct sh_pfc_pin *pins;
148 unsigned int nr_pins;
149 const struct pinmux_range *ranges;
150 unsigned int nr_ranges;
151 const struct sh_pfc_pin_group *groups;
152 unsigned int nr_groups;
153 const struct sh_pfc_function *functions;
154 unsigned int nr_functions;
155
156 const struct pinmux_func *func_gpios;
157 unsigned int nr_func_gpios;
103 158
104 struct pinmux_gpio *gpios; 159 const struct pinmux_cfg_reg *cfg_regs;
105 struct pinmux_cfg_reg *cfg_regs; 160 const struct pinmux_data_reg *data_regs;
106 struct pinmux_data_reg *data_regs;
107 161
108 pinmux_enum_t *gpio_data; 162 const pinmux_enum_t *gpio_data;
109 unsigned int gpio_data_size; 163 unsigned int gpio_data_size;
110 164
111 struct pinmux_irq *gpio_irq; 165 const struct pinmux_irq *gpio_irq;
112 unsigned int gpio_irq_size; 166 unsigned int gpio_irq_size;
113 167
114 unsigned long unlock_reg; 168 unsigned long unlock_reg;
115}; 169};
116 170
117enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE }; 171enum { GPIO_CFG_REQ, GPIO_CFG_FREE };
118 172
119/* helper macro for port */ 173/* helper macro for port */
120#define PORT_1(fn, pfx, sfx) fn(pfx, sfx) 174#define PORT_1(fn, pfx, sfx) fn(pfx, sfx)
@@ -126,6 +180,23 @@ enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
126 PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \ 180 PORT_1(fn, pfx##6, sfx), PORT_1(fn, pfx##7, sfx), \
127 PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx) 181 PORT_1(fn, pfx##8, sfx), PORT_1(fn, pfx##9, sfx)
128 182
183#define PORT_10_REV(fn, pfx, sfx) \
184 PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \
185 PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \
186 PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \
187 PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \
188 PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx)
189
190#define PORT_32(fn, pfx, sfx) \
191 PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \
192 PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \
193 PORT_1(fn, pfx##31, sfx)
194
195#define PORT_32_REV(fn, pfx, sfx) \
196 PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \
197 PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \
198 PORT_10_REV(fn, pfx, sfx)
199
129#define PORT_90(fn, pfx, sfx) \ 200#define PORT_90(fn, pfx, sfx) \
130 PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \ 201 PORT_10(fn, pfx##1, sfx), PORT_10(fn, pfx##2, sfx), \
131 PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \ 202 PORT_10(fn, pfx##3, sfx), PORT_10(fn, pfx##4, sfx), \
@@ -137,7 +208,7 @@ enum { GPIO_CFG_DRYRUN, GPIO_CFG_REQ, GPIO_CFG_FREE };
137#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA) 208#define _GPIO_PORT(pfx, sfx) PINMUX_GPIO(GPIO_PORT##pfx, PORT##pfx##_DATA)
138#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str) 209#define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
139#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused) 210#define GPIO_PORT_ALL() CPU_ALL_PORT(_GPIO_PORT, , unused)
140#define GPIO_FN(str) PINMUX_GPIO(GPIO_FN_##str, str##_MARK) 211#define GPIO_FN(str) PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
141 212
142/* helper macro for pinmux_enum_t */ 213/* helper macro for pinmux_enum_t */
143#define PORT_DATA_I(nr) \ 214#define PORT_DATA_I(nr) \
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c
index 6a7dae70db08..116da0412c4b 100644
--- a/drivers/pinctrl/spear/pinctrl-spear.c
+++ b/drivers/pinctrl/spear/pinctrl-spear.c
@@ -198,7 +198,7 @@ static void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
198 kfree(map); 198 kfree(map);
199} 199}
200 200
201static struct pinctrl_ops spear_pinctrl_ops = { 201static const struct pinctrl_ops spear_pinctrl_ops = {
202 .get_groups_count = spear_pinctrl_get_groups_cnt, 202 .get_groups_count = spear_pinctrl_get_groups_cnt,
203 .get_group_name = spear_pinctrl_get_group_name, 203 .get_group_name = spear_pinctrl_get_group_name,
204 .get_group_pins = spear_pinctrl_get_group_pins, 204 .get_group_pins = spear_pinctrl_get_group_pins,
@@ -340,7 +340,7 @@ static void gpio_disable_free(struct pinctrl_dev *pctldev,
340 gpio_request_endisable(pctldev, range, offset, false); 340 gpio_request_endisable(pctldev, range, offset, false);
341} 341}
342 342
343static struct pinmux_ops spear_pinmux_ops = { 343static const struct pinmux_ops spear_pinmux_ops = {
344 .get_functions_count = spear_pinctrl_get_funcs_count, 344 .get_functions_count = spear_pinctrl_get_funcs_count,
345 .get_function_name = spear_pinctrl_get_func_name, 345 .get_function_name = spear_pinctrl_get_func_name,
346 .get_function_groups = spear_pinctrl_get_func_groups, 346 .get_function_groups = spear_pinctrl_get_func_groups,
diff --git a/include/linux/pinctrl/pinctrl.h b/include/linux/pinctrl/pinctrl.h
index 778804df293f..2c2a9e8d8578 100644
--- a/include/linux/pinctrl/pinctrl.h
+++ b/include/linux/pinctrl/pinctrl.h
@@ -118,9 +118,9 @@ struct pinctrl_desc {
118 const char *name; 118 const char *name;
119 struct pinctrl_pin_desc const *pins; 119 struct pinctrl_pin_desc const *pins;
120 unsigned int npins; 120 unsigned int npins;
121 struct pinctrl_ops *pctlops; 121 const struct pinctrl_ops *pctlops;
122 struct pinmux_ops *pmxops; 122 const struct pinmux_ops *pmxops;
123 struct pinconf_ops *confops; 123 const struct pinconf_ops *confops;
124 struct module *owner; 124 struct module *owner;
125}; 125};
126 126
diff --git a/include/linux/platform_data/gpio-rcar.h b/include/linux/platform_data/gpio-rcar.h
new file mode 100644
index 000000000000..b253f77a7ddf
--- /dev/null
+++ b/include/linux/platform_data/gpio-rcar.h
@@ -0,0 +1,26 @@
1/*
2 * Renesas R-Car GPIO Support
3 *
4 * Copyright (C) 2013 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __GPIO_RCAR_H__
17#define __GPIO_RCAR_H__
18
19struct gpio_rcar_config {
20 unsigned int gpio_base;
21 unsigned int irq_base;
22 unsigned int number_of_pins;
23 const char *pctl_name;
24};
25
26#endif /* __GPIO_RCAR_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-13 04:38:12 -0500