diff options
author | Linus Walleij <linus.walleij@linaro.org> | 2013-06-15 16:01:13 -0400 |
---|---|---|
committer | Linus Walleij <linus.walleij@linaro.org> | 2013-10-16 08:09:49 -0400 |
commit | d7057e1de8d6c180eb2ecd90b0cab9d1a8a4d8ab (patch) | |
tree | f5e2c6f263a1d142de054ab9f9546ad702351e14 | |
parent | 50564a794d64ace92c189d7cb5b591a60d3de9c2 (diff) |
ARM: integrator: delete non-devicetree boot path
The Device Tree boot path now supports everything the ATAG
boot can provide, and the two are equivalent. This deletes
the ATAG boot path from the Integrator/AP and
Integrator/CP platforms to move them on to the future.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
-rw-r--r-- | arch/arm/Kconfig | 1 | ||||
-rw-r--r-- | arch/arm/mach-integrator/core.c | 57 | ||||
-rw-r--r-- | arch/arm/mach-integrator/integrator_ap.c | 135 | ||||
-rw-r--r-- | arch/arm/mach-integrator/integrator_cp.c | 173 | ||||
-rw-r--r-- | arch/arm/mach-integrator/pci_v3.c | 122 |
5 files changed, 25 insertions, 463 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1ad6fb6c094d..d9ce86857791 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -317,6 +317,7 @@ config ARCH_INTEGRATOR | |||
317 | select NEED_MACH_MEMORY_H | 317 | select NEED_MACH_MEMORY_H |
318 | select PLAT_VERSATILE | 318 | select PLAT_VERSATILE |
319 | select SPARSE_IRQ | 319 | select SPARSE_IRQ |
320 | select USE_OF | ||
320 | select VERSATILE_FPGA_IRQ | 321 | select VERSATILE_FPGA_IRQ |
321 | help | 322 | help |
322 | Support for ARM's Integrator platform. | 323 | Support for ARM's Integrator platform. |
diff --git a/arch/arm/mach-integrator/core.c b/arch/arm/mach-integrator/core.c index c07c821fb6b3..4698942f3ed3 100644 --- a/arch/arm/mach-integrator/core.c +++ b/arch/arm/mach-integrator/core.c | |||
@@ -34,63 +34,6 @@ | |||
34 | 34 | ||
35 | #include "common.h" | 35 | #include "common.h" |
36 | 36 | ||
37 | #ifdef CONFIG_ATAGS | ||
38 | |||
39 | #define INTEGRATOR_RTC_IRQ { IRQ_RTCINT } | ||
40 | #define INTEGRATOR_UART0_IRQ { IRQ_UARTINT0 } | ||
41 | #define INTEGRATOR_UART1_IRQ { IRQ_UARTINT1 } | ||
42 | #define KMI0_IRQ { IRQ_KMIINT0 } | ||
43 | #define KMI1_IRQ { IRQ_KMIINT1 } | ||
44 | |||
45 | static AMBA_APB_DEVICE(rtc, "rtc", 0, | ||
46 | INTEGRATOR_RTC_BASE, INTEGRATOR_RTC_IRQ, NULL); | ||
47 | |||
48 | static AMBA_APB_DEVICE(uart0, "uart0", 0, | ||
49 | INTEGRATOR_UART0_BASE, INTEGRATOR_UART0_IRQ, NULL); | ||
50 | |||
51 | static AMBA_APB_DEVICE(uart1, "uart1", 0, | ||
52 | INTEGRATOR_UART1_BASE, INTEGRATOR_UART1_IRQ, NULL); | ||
53 | |||
54 | static AMBA_APB_DEVICE(kmi0, "kmi0", 0, KMI0_BASE, KMI0_IRQ, NULL); | ||
55 | static AMBA_APB_DEVICE(kmi1, "kmi1", 0, KMI1_BASE, KMI1_IRQ, NULL); | ||
56 | |||
57 | static struct amba_device *amba_devs[] __initdata = { | ||
58 | &rtc_device, | ||
59 | &uart0_device, | ||
60 | &uart1_device, | ||
61 | &kmi0_device, | ||
62 | &kmi1_device, | ||
63 | }; | ||
64 | |||
65 | int __init integrator_init(bool is_cp) | ||
66 | { | ||
67 | int i; | ||
68 | |||
69 | /* | ||
70 | * The Integrator/AP lacks necessary AMBA PrimeCell IDs, so we need to | ||
71 | * hard-code them. The Integator/CP and forward have proper cell IDs. | ||
72 | * Else we leave them undefined to the bus driver can autoprobe them. | ||
73 | */ | ||
74 | if (!is_cp && IS_ENABLED(CONFIG_ARCH_INTEGRATOR_AP)) { | ||
75 | rtc_device.periphid = 0x00041030; | ||
76 | uart0_device.periphid = 0x00041010; | ||
77 | uart1_device.periphid = 0x00041010; | ||
78 | kmi0_device.periphid = 0x00041050; | ||
79 | kmi1_device.periphid = 0x00041050; | ||
80 | uart0_device.dev.platform_data = &ap_uart_data; | ||
81 | uart1_device.dev.platform_data = &ap_uart_data; | ||
82 | } | ||
83 | |||
84 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | ||
85 | struct amba_device *d = amba_devs[i]; | ||
86 | amba_device_register(d, &iomem_resource); | ||
87 | } | ||
88 | |||
89 | return 0; | ||
90 | } | ||
91 | |||
92 | #endif | ||
93 | |||
94 | static DEFINE_RAW_SPINLOCK(cm_lock); | 37 | static DEFINE_RAW_SPINLOCK(cm_lock); |
95 | 38 | ||
96 | /** | 39 | /** |
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c index f5fbd8adef0c..563f1c63c25c 100644 --- a/arch/arm/mach-integrator/integrator_ap.c +++ b/arch/arm/mach-integrator/integrator_ap.c | |||
@@ -402,8 +402,6 @@ void __init ap_init_early(void) | |||
402 | { | 402 | { |
403 | } | 403 | } |
404 | 404 | ||
405 | #ifdef CONFIG_OF | ||
406 | |||
407 | static void __init ap_of_timer_init(void) | 405 | static void __init ap_of_timer_init(void) |
408 | { | 406 | { |
409 | struct device_node *node; | 407 | struct device_node *node; |
@@ -564,136 +562,3 @@ DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)") | |||
564 | .restart = integrator_restart, | 562 | .restart = integrator_restart, |
565 | .dt_compat = ap_dt_board_compat, | 563 | .dt_compat = ap_dt_board_compat, |
566 | MACHINE_END | 564 | MACHINE_END |
567 | |||
568 | #endif | ||
569 | |||
570 | #ifdef CONFIG_ATAGS | ||
571 | |||
572 | /* | ||
573 | * For the ATAG boot some static mappings are needed. This will | ||
574 | * go away with the ATAG support down the road. | ||
575 | */ | ||
576 | |||
577 | static struct map_desc ap_io_desc_atag[] __initdata = { | ||
578 | { | ||
579 | .virtual = IO_ADDRESS(INTEGRATOR_SC_BASE), | ||
580 | .pfn = __phys_to_pfn(INTEGRATOR_SC_BASE), | ||
581 | .length = SZ_4K, | ||
582 | .type = MT_DEVICE | ||
583 | }, | ||
584 | }; | ||
585 | |||
586 | static void __init ap_map_io_atag(void) | ||
587 | { | ||
588 | iotable_init(ap_io_desc_atag, ARRAY_SIZE(ap_io_desc_atag)); | ||
589 | ap_map_io(); | ||
590 | } | ||
591 | |||
592 | /* | ||
593 | * This is where non-devicetree initialization code is collected and stashed | ||
594 | * for eventual deletion. | ||
595 | */ | ||
596 | |||
597 | static struct platform_device pci_v3_device = { | ||
598 | .name = "pci-v3", | ||
599 | .id = 0, | ||
600 | }; | ||
601 | |||
602 | static struct resource cfi_flash_resource = { | ||
603 | .start = INTEGRATOR_FLASH_BASE, | ||
604 | .end = INTEGRATOR_FLASH_BASE + INTEGRATOR_FLASH_SIZE - 1, | ||
605 | .flags = IORESOURCE_MEM, | ||
606 | }; | ||
607 | |||
608 | static struct platform_device cfi_flash_device = { | ||
609 | .name = "physmap-flash", | ||
610 | .id = 0, | ||
611 | .dev = { | ||
612 | .platform_data = &ap_flash_data, | ||
613 | }, | ||
614 | .num_resources = 1, | ||
615 | .resource = &cfi_flash_resource, | ||
616 | }; | ||
617 | |||
618 | static void __init ap_timer_init(void) | ||
619 | { | ||
620 | struct clk *clk; | ||
621 | unsigned long rate; | ||
622 | |||
623 | clk = clk_get_sys("ap_timer", NULL); | ||
624 | BUG_ON(IS_ERR(clk)); | ||
625 | clk_prepare_enable(clk); | ||
626 | rate = clk_get_rate(clk); | ||
627 | |||
628 | writel(0, TIMER0_VA_BASE + TIMER_CTRL); | ||
629 | writel(0, TIMER1_VA_BASE + TIMER_CTRL); | ||
630 | writel(0, TIMER2_VA_BASE + TIMER_CTRL); | ||
631 | |||
632 | integrator_clocksource_init(rate, (void __iomem *)TIMER2_VA_BASE); | ||
633 | integrator_clockevent_init(rate, (void __iomem *)TIMER1_VA_BASE, | ||
634 | IRQ_TIMERINT1); | ||
635 | } | ||
636 | |||
637 | #define INTEGRATOR_SC_VALID_INT 0x003fffff | ||
638 | |||
639 | static void __init ap_init_irq(void) | ||
640 | { | ||
641 | /* Disable all interrupts initially. */ | ||
642 | /* Do the core module ones */ | ||
643 | writel(-1, VA_CMIC_BASE + IRQ_ENABLE_CLEAR); | ||
644 | |||
645 | /* do the header card stuff next */ | ||
646 | writel(-1, VA_IC_BASE + IRQ_ENABLE_CLEAR); | ||
647 | writel(-1, VA_IC_BASE + FIQ_ENABLE_CLEAR); | ||
648 | |||
649 | fpga_irq_init(VA_IC_BASE, "SC", IRQ_PIC_START, | ||
650 | -1, INTEGRATOR_SC_VALID_INT, NULL); | ||
651 | integrator_clk_init(false); | ||
652 | } | ||
653 | |||
654 | static void __init ap_init(void) | ||
655 | { | ||
656 | unsigned long sc_dec; | ||
657 | int i; | ||
658 | |||
659 | platform_device_register(&pci_v3_device); | ||
660 | platform_device_register(&cfi_flash_device); | ||
661 | |||
662 | ap_syscon_base = __io_address(INTEGRATOR_SC_BASE); | ||
663 | sc_dec = readl(ap_syscon_base + INTEGRATOR_SC_DEC_OFFSET); | ||
664 | for (i = 0; i < 4; i++) { | ||
665 | struct lm_device *lmdev; | ||
666 | |||
667 | if ((sc_dec & (16 << i)) == 0) | ||
668 | continue; | ||
669 | |||
670 | lmdev = kzalloc(sizeof(struct lm_device), GFP_KERNEL); | ||
671 | if (!lmdev) | ||
672 | continue; | ||
673 | |||
674 | lmdev->resource.start = 0xc0000000 + 0x10000000 * i; | ||
675 | lmdev->resource.end = lmdev->resource.start + 0x0fffffff; | ||
676 | lmdev->resource.flags = IORESOURCE_MEM; | ||
677 | lmdev->irq = IRQ_AP_EXPINT0 + i; | ||
678 | lmdev->id = i; | ||
679 | |||
680 | lm_device_register(lmdev); | ||
681 | } | ||
682 | |||
683 | integrator_init(false); | ||
684 | } | ||
685 | |||
686 | MACHINE_START(INTEGRATOR, "ARM-Integrator") | ||
687 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | ||
688 | .atag_offset = 0x100, | ||
689 | .reserve = integrator_reserve, | ||
690 | .map_io = ap_map_io_atag, | ||
691 | .init_early = ap_init_early, | ||
692 | .init_irq = ap_init_irq, | ||
693 | .handle_irq = fpga_handle_irq, | ||
694 | .init_time = ap_timer_init, | ||
695 | .init_machine = ap_init, | ||
696 | .restart = integrator_restart, | ||
697 | MACHINE_END | ||
698 | |||
699 | #endif | ||
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 8c60fcb08a98..871c25dee7fe 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c | |||
@@ -249,7 +249,6 @@ static void __init intcp_init_early(void) | |||
249 | #endif | 249 | #endif |
250 | } | 250 | } |
251 | 251 | ||
252 | #ifdef CONFIG_OF | ||
253 | static const struct of_device_id fpga_irq_of_match[] __initconst = { | 252 | static const struct of_device_id fpga_irq_of_match[] __initconst = { |
254 | { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, }, | 253 | { .compatible = "arm,versatile-fpga-irq", .data = fpga_irq_of_init, }, |
255 | { /* Sentinel */ } | 254 | { /* Sentinel */ } |
@@ -354,175 +353,3 @@ DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)") | |||
354 | .restart = integrator_restart, | 353 | .restart = integrator_restart, |
355 | .dt_compat = intcp_dt_board_compat, | 354 | .dt_compat = intcp_dt_board_compat, |
356 | MACHINE_END | 355 | MACHINE_END |
357 | |||
358 | #endif | ||
359 | |||
360 | #ifdef CONFIG_ATAGS | ||
361 | |||
362 | /* | ||
363 | * For the ATAG boot some static mappings are needed. This will | ||
364 | * go away with the ATAG support down the road. | ||
365 | */ | ||
366 | |||
367 | static struct map_desc intcp_io_desc_atag[] __initdata = { | ||
368 | { | ||
369 | .virtual = IO_ADDRESS(INTEGRATOR_CP_CTL_BASE), | ||
370 | .pfn = __phys_to_pfn(INTEGRATOR_CP_CTL_BASE), | ||
371 | .length = SZ_4K, | ||
372 | .type = MT_DEVICE | ||
373 | }, | ||
374 | }; | ||
375 | |||
376 | static void __init intcp_map_io_atag(void) | ||
377 | { | ||
378 | iotable_init(intcp_io_desc_atag, ARRAY_SIZE(intcp_io_desc_atag)); | ||
379 | intcp_con_base = __io_address(INTEGRATOR_CP_CTL_BASE); | ||
380 | intcp_map_io(); | ||
381 | } | ||
382 | |||
383 | |||
384 | /* | ||
385 | * This is where non-devicetree initialization code is collected and stashed | ||
386 | * for eventual deletion. | ||
387 | */ | ||
388 | |||
389 | #define INTCP_FLASH_SIZE SZ_32M | ||
390 | |||
391 | static struct resource intcp_flash_resource = { | ||
392 | .start = INTCP_PA_FLASH_BASE, | ||
393 | .end = INTCP_PA_FLASH_BASE + INTCP_FLASH_SIZE - 1, | ||
394 | .flags = IORESOURCE_MEM, | ||
395 | }; | ||
396 | |||
397 | static struct platform_device intcp_flash_device = { | ||
398 | .name = "physmap-flash", | ||
399 | .id = 0, | ||
400 | .dev = { | ||
401 | .platform_data = &intcp_flash_data, | ||
402 | }, | ||
403 | .num_resources = 1, | ||
404 | .resource = &intcp_flash_resource, | ||
405 | }; | ||
406 | |||
407 | #define INTCP_ETH_SIZE 0x10 | ||
408 | |||
409 | static struct resource smc91x_resources[] = { | ||
410 | [0] = { | ||
411 | .start = INTEGRATOR_CP_ETH_BASE, | ||
412 | .end = INTEGRATOR_CP_ETH_BASE + INTCP_ETH_SIZE - 1, | ||
413 | .flags = IORESOURCE_MEM, | ||
414 | }, | ||
415 | [1] = { | ||
416 | .start = IRQ_CP_ETHINT, | ||
417 | .end = IRQ_CP_ETHINT, | ||
418 | .flags = IORESOURCE_IRQ, | ||
419 | }, | ||
420 | }; | ||
421 | |||
422 | static struct platform_device smc91x_device = { | ||
423 | .name = "smc91x", | ||
424 | .id = 0, | ||
425 | .num_resources = ARRAY_SIZE(smc91x_resources), | ||
426 | .resource = smc91x_resources, | ||
427 | }; | ||
428 | |||
429 | static struct platform_device *intcp_devs[] __initdata = { | ||
430 | &intcp_flash_device, | ||
431 | &smc91x_device, | ||
432 | }; | ||
433 | |||
434 | #define INTCP_VA_CIC_BASE __io_address(INTEGRATOR_HDR_BASE + 0x40) | ||
435 | #define INTCP_VA_PIC_BASE __io_address(INTEGRATOR_IC_BASE) | ||
436 | #define INTCP_VA_SIC_BASE __io_address(INTEGRATOR_CP_SIC_BASE) | ||
437 | |||
438 | static void __init intcp_init_irq(void) | ||
439 | { | ||
440 | u32 pic_mask, cic_mask, sic_mask; | ||
441 | |||
442 | /* These masks are for the HW IRQ registers */ | ||
443 | pic_mask = ~((~0u) << (11 - 0)); | ||
444 | pic_mask |= (~((~0u) << (29 - 22))) << 22; | ||
445 | cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START)); | ||
446 | sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START)); | ||
447 | |||
448 | /* | ||
449 | * Disable all interrupt sources | ||
450 | */ | ||
451 | writel(0xffffffff, INTCP_VA_PIC_BASE + IRQ_ENABLE_CLEAR); | ||
452 | writel(0xffffffff, INTCP_VA_PIC_BASE + FIQ_ENABLE_CLEAR); | ||
453 | writel(0xffffffff, INTCP_VA_CIC_BASE + IRQ_ENABLE_CLEAR); | ||
454 | writel(0xffffffff, INTCP_VA_CIC_BASE + FIQ_ENABLE_CLEAR); | ||
455 | writel(sic_mask, INTCP_VA_SIC_BASE + IRQ_ENABLE_CLEAR); | ||
456 | writel(sic_mask, INTCP_VA_SIC_BASE + FIQ_ENABLE_CLEAR); | ||
457 | |||
458 | fpga_irq_init(INTCP_VA_PIC_BASE, "PIC", IRQ_PIC_START, | ||
459 | -1, pic_mask, NULL); | ||
460 | |||
461 | fpga_irq_init(INTCP_VA_CIC_BASE, "CIC", IRQ_CIC_START, | ||
462 | -1, cic_mask, NULL); | ||
463 | |||
464 | fpga_irq_init(INTCP_VA_SIC_BASE, "SIC", IRQ_SIC_START, | ||
465 | IRQ_CP_CPPLDINT, sic_mask, NULL); | ||
466 | |||
467 | integrator_clk_init(true); | ||
468 | } | ||
469 | |||
470 | #define TIMER0_VA_BASE __io_address(INTEGRATOR_TIMER0_BASE) | ||
471 | #define TIMER1_VA_BASE __io_address(INTEGRATOR_TIMER1_BASE) | ||
472 | #define TIMER2_VA_BASE __io_address(INTEGRATOR_TIMER2_BASE) | ||
473 | |||
474 | static void __init cp_timer_init(void) | ||
475 | { | ||
476 | writel(0, TIMER0_VA_BASE + TIMER_CTRL); | ||
477 | writel(0, TIMER1_VA_BASE + TIMER_CTRL); | ||
478 | writel(0, TIMER2_VA_BASE + TIMER_CTRL); | ||
479 | |||
480 | sp804_clocksource_init(TIMER2_VA_BASE, "timer2"); | ||
481 | sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1"); | ||
482 | } | ||
483 | |||
484 | #define INTEGRATOR_CP_MMC_IRQS { IRQ_CP_MMCIINT0, IRQ_CP_MMCIINT1 } | ||
485 | #define INTEGRATOR_CP_AACI_IRQS { IRQ_CP_AACIINT } | ||
486 | |||
487 | static AMBA_APB_DEVICE(mmc, "mmci", 0, INTEGRATOR_CP_MMC_BASE, | ||
488 | INTEGRATOR_CP_MMC_IRQS, &mmc_data); | ||
489 | |||
490 | static AMBA_APB_DEVICE(aaci, "aaci", 0, INTEGRATOR_CP_AACI_BASE, | ||
491 | INTEGRATOR_CP_AACI_IRQS, NULL); | ||
492 | |||
493 | static AMBA_AHB_DEVICE(clcd, "clcd", 0, INTCP_PA_CLCD_BASE, | ||
494 | { IRQ_CP_CLCDCINT }, &clcd_data); | ||
495 | |||
496 | static struct amba_device *amba_devs[] __initdata = { | ||
497 | &mmc_device, | ||
498 | &aaci_device, | ||
499 | &clcd_device, | ||
500 | }; | ||
501 | |||
502 | static void __init intcp_init(void) | ||
503 | { | ||
504 | int i; | ||
505 | |||
506 | platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs)); | ||
507 | |||
508 | for (i = 0; i < ARRAY_SIZE(amba_devs); i++) { | ||
509 | struct amba_device *d = amba_devs[i]; | ||
510 | amba_device_register(d, &iomem_resource); | ||
511 | } | ||
512 | integrator_init(true); | ||
513 | } | ||
514 | |||
515 | MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") | ||
516 | /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ | ||
517 | .atag_offset = 0x100, | ||
518 | .reserve = integrator_reserve, | ||
519 | .map_io = intcp_map_io_atag, | ||
520 | .init_early = intcp_init_early, | ||
521 | .init_irq = intcp_init_irq, | ||
522 | .handle_irq = fpga_handle_irq, | ||
523 | .init_time = cp_timer_init, | ||
524 | .init_machine = intcp_init, | ||
525 | .restart = integrator_restart, | ||
526 | MACHINE_END | ||
527 | |||
528 | #endif | ||
diff --git a/arch/arm/mach-integrator/pci_v3.c b/arch/arm/mach-integrator/pci_v3.c index 2d10793fa2a0..67406fc46004 100644 --- a/arch/arm/mach-integrator/pci_v3.c +++ b/arch/arm/mach-integrator/pci_v3.c | |||
@@ -809,32 +809,6 @@ static u8 __init pci_v3_swizzle(struct pci_dev *dev, u8 *pinp) | |||
809 | return pci_common_swizzle(dev, pinp); | 809 | return pci_common_swizzle(dev, pinp); |
810 | } | 810 | } |
811 | 811 | ||
812 | static int irq_tab[4] __initdata = { | ||
813 | IRQ_AP_PCIINT0, IRQ_AP_PCIINT1, IRQ_AP_PCIINT2, IRQ_AP_PCIINT3 | ||
814 | }; | ||
815 | |||
816 | /* | ||
817 | * map the specified device/slot/pin to an IRQ. This works out such | ||
818 | * that slot 9 pin 1 is INT0, pin 2 is INT1, and slot 10 pin 1 is INT1. | ||
819 | */ | ||
820 | static int __init pci_v3_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) | ||
821 | { | ||
822 | int intnr = ((slot - 9) + (pin - 1)) & 3; | ||
823 | |||
824 | return irq_tab[intnr]; | ||
825 | } | ||
826 | |||
827 | static struct hw_pci pci_v3 __initdata = { | ||
828 | .swizzle = pci_v3_swizzle, | ||
829 | .setup = pci_v3_setup, | ||
830 | .nr_controllers = 1, | ||
831 | .ops = &pci_v3_ops, | ||
832 | .preinit = pci_v3_preinit, | ||
833 | .postinit = pci_v3_postinit, | ||
834 | }; | ||
835 | |||
836 | #ifdef CONFIG_OF | ||
837 | |||
838 | static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin) | 812 | static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin) |
839 | { | 813 | { |
840 | struct of_irq oirq; | 814 | struct of_irq oirq; |
@@ -851,14 +825,36 @@ static int __init pci_v3_map_irq_dt(const struct pci_dev *dev, u8 slot, u8 pin) | |||
851 | oirq.size); | 825 | oirq.size); |
852 | } | 826 | } |
853 | 827 | ||
854 | static int __init pci_v3_dtprobe(struct platform_device *pdev, | 828 | static struct hw_pci pci_v3 __initdata = { |
855 | struct device_node *np) | 829 | .swizzle = pci_v3_swizzle, |
830 | .setup = pci_v3_setup, | ||
831 | .nr_controllers = 1, | ||
832 | .ops = &pci_v3_ops, | ||
833 | .preinit = pci_v3_preinit, | ||
834 | .postinit = pci_v3_postinit, | ||
835 | }; | ||
836 | |||
837 | static int __init pci_v3_probe(struct platform_device *pdev) | ||
856 | { | 838 | { |
839 | struct device_node *np = pdev->dev.of_node; | ||
857 | struct of_pci_range_parser parser; | 840 | struct of_pci_range_parser parser; |
858 | struct of_pci_range range; | 841 | struct of_pci_range range; |
859 | struct resource *res; | 842 | struct resource *res; |
860 | int irq, ret; | 843 | int irq, ret; |
861 | 844 | ||
845 | /* Remap the Integrator system controller */ | ||
846 | ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100); | ||
847 | if (!ap_syscon_base) { | ||
848 | dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n"); | ||
849 | return -ENODEV; | ||
850 | } | ||
851 | |||
852 | /* Device tree probe path */ | ||
853 | if (!np) { | ||
854 | dev_err(&pdev->dev, "no device tree node for PCIv3\n"); | ||
855 | return -ENODEV; | ||
856 | } | ||
857 | |||
862 | if (of_pci_range_parser_init(&parser, np)) | 858 | if (of_pci_range_parser_init(&parser, np)) |
863 | return -EINVAL; | 859 | return -EINVAL; |
864 | 860 | ||
@@ -925,76 +921,6 @@ static int __init pci_v3_dtprobe(struct platform_device *pdev, | |||
925 | return 0; | 921 | return 0; |
926 | } | 922 | } |
927 | 923 | ||
928 | #else | ||
929 | |||
930 | static inline int pci_v3_dtprobe(struct platform_device *pdev, | ||
931 | struct device_node *np) | ||
932 | { | ||
933 | return -EINVAL; | ||
934 | } | ||
935 | |||
936 | #endif | ||
937 | |||
938 | static int __init pci_v3_probe(struct platform_device *pdev) | ||
939 | { | ||
940 | struct device_node *np = pdev->dev.of_node; | ||
941 | int ret; | ||
942 | |||
943 | /* Remap the Integrator system controller */ | ||
944 | ap_syscon_base = ioremap(INTEGRATOR_SC_BASE, 0x100); | ||
945 | if (!ap_syscon_base) { | ||
946 | dev_err(&pdev->dev, "unable to remap the AP syscon for PCIv3\n"); | ||
947 | return -ENODEV; | ||
948 | } | ||
949 | |||
950 | /* Device tree probe path */ | ||
951 | if (np) | ||
952 | return pci_v3_dtprobe(pdev, np); | ||
953 | |||
954 | pci_v3_base = devm_ioremap(&pdev->dev, PHYS_PCI_V3_BASE, SZ_64K); | ||
955 | if (!pci_v3_base) { | ||
956 | dev_err(&pdev->dev, "unable to remap PCIv3 base\n"); | ||
957 | return -ENODEV; | ||
958 | } | ||
959 | |||
960 | ret = devm_request_irq(&pdev->dev, IRQ_AP_V3INT, v3_irq, 0, "V3", NULL); | ||
961 | if (ret) { | ||
962 | dev_err(&pdev->dev, "unable to grab PCI error interrupt: %d\n", | ||
963 | ret); | ||
964 | return -ENODEV; | ||
965 | } | ||
966 | |||
967 | conf_mem.name = "PCIv3 config"; | ||
968 | conf_mem.start = PHYS_PCI_CONFIG_BASE; | ||
969 | conf_mem.end = PHYS_PCI_CONFIG_BASE + SZ_16M - 1; | ||
970 | conf_mem.flags = IORESOURCE_MEM; | ||
971 | |||
972 | io_mem.name = "PCIv3 I/O"; | ||
973 | io_mem.start = PHYS_PCI_IO_BASE; | ||
974 | io_mem.end = PHYS_PCI_IO_BASE + SZ_16M - 1; | ||
975 | io_mem.flags = IORESOURCE_MEM; | ||
976 | |||
977 | non_mem_pci = 0x00000000; | ||
978 | non_mem_pci_sz = SZ_256M; | ||
979 | non_mem.name = "PCIv3 non-prefetched mem"; | ||
980 | non_mem.start = PHYS_PCI_MEM_BASE; | ||
981 | non_mem.end = PHYS_PCI_MEM_BASE + SZ_256M - 1; | ||
982 | non_mem.flags = IORESOURCE_MEM; | ||
983 | |||
984 | pre_mem_pci = 0x10000000; | ||
985 | pre_mem_pci_sz = SZ_256M; | ||
986 | pre_mem.name = "PCIv3 prefetched mem"; | ||
987 | pre_mem.start = PHYS_PCI_PRE_BASE + SZ_256M; | ||
988 | pre_mem.end = PHYS_PCI_PRE_BASE + SZ_256M - 1; | ||
989 | pre_mem.flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; | ||
990 | |||
991 | pci_v3.map_irq = pci_v3_map_irq; | ||
992 | |||
993 | pci_common_init_dev(&pdev->dev, &pci_v3); | ||
994 | |||
995 | return 0; | ||
996 | } | ||
997 | |||
998 | static const struct of_device_id pci_ids[] = { | 924 | static const struct of_device_id pci_ids[] = { |
999 | { .compatible = "v3,v360epc-pci", }, | 925 | { .compatible = "v3,v360epc-pci", }, |
1000 | {}, | 926 | {}, |