diff options
author | Andy Fleming <afleming@freescale.com> | 2007-02-09 18:28:31 -0500 |
---|---|---|
committer | Kumar Gala <galak@kernel.crashing.org> | 2007-02-13 13:36:23 -0500 |
commit | c2882bb12cbd8a4170e673e6a33c6be047b75bc1 (patch) | |
tree | d322358127d91e2db639109ea7efff5cddffca48 | |
parent | 54c66f6d781e03dc0b23956234963c4911e6d1c0 (diff) |
[POWERPC] 85xx: Add support for the 8568 MDS board
Add support for the MPC8568 MDS reference board
Signed-off-by: Andrew Fleming <afleming@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
-rw-r--r-- | arch/powerpc/boot/dts/mpc8568mds.dts | 380 | ||||
-rw-r--r-- | arch/powerpc/platforms/85xx/Kconfig | 13 | ||||
-rw-r--r-- | arch/powerpc/platforms/85xx/Makefile | 1 | ||||
-rw-r--r-- | arch/powerpc/platforms/85xx/mpc8568_mds.c | 246 |
4 files changed, 640 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/dts/mpc8568mds.dts new file mode 100644 index 000000000000..06d24653e422 --- /dev/null +++ b/arch/powerpc/boot/dts/mpc8568mds.dts | |||
@@ -0,0 +1,380 @@ | |||
1 | /* | ||
2 | * MPC8568E MDS Device Tree Source | ||
3 | * | ||
4 | * Copyright 2007 Freescale Semiconductor Inc. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms of the GNU General Public License as published by the | ||
8 | * Free Software Foundation; either version 2 of the License, or (at your | ||
9 | * option) any later version. | ||
10 | */ | ||
11 | |||
12 | |||
13 | /* | ||
14 | /memreserve/ 00000000 1000000; | ||
15 | */ | ||
16 | |||
17 | / { | ||
18 | model = "MPC8568EMDS"; | ||
19 | compatible = "MPC85xxMDS"; | ||
20 | #address-cells = <1>; | ||
21 | #size-cells = <1>; | ||
22 | linux,phandle = <100>; | ||
23 | |||
24 | cpus { | ||
25 | #cpus = <1>; | ||
26 | #address-cells = <1>; | ||
27 | #size-cells = <0>; | ||
28 | linux,phandle = <200>; | ||
29 | |||
30 | PowerPC,8568@0 { | ||
31 | device_type = "cpu"; | ||
32 | reg = <0>; | ||
33 | d-cache-line-size = <20>; // 32 bytes | ||
34 | i-cache-line-size = <20>; // 32 bytes | ||
35 | d-cache-size = <8000>; // L1, 32K | ||
36 | i-cache-size = <8000>; // L1, 32K | ||
37 | timebase-frequency = <0>; | ||
38 | bus-frequency = <0>; | ||
39 | clock-frequency = <0>; | ||
40 | 32-bit; | ||
41 | linux,phandle = <201>; | ||
42 | }; | ||
43 | }; | ||
44 | |||
45 | memory { | ||
46 | device_type = "memory"; | ||
47 | linux,phandle = <300>; | ||
48 | reg = <00000000 10000000>; | ||
49 | }; | ||
50 | |||
51 | bcsr@f8000000 { | ||
52 | device_type = "board-control"; | ||
53 | reg = <f8000000 8000>; | ||
54 | }; | ||
55 | |||
56 | soc8568@e0000000 { | ||
57 | #address-cells = <1>; | ||
58 | #size-cells = <1>; | ||
59 | #interrupt-cells = <2>; | ||
60 | device_type = "soc"; | ||
61 | ranges = <0 e0000000 00100000>; | ||
62 | reg = <e0000000 00100000>; | ||
63 | bus-frequency = <0>; | ||
64 | |||
65 | i2c@3000 { | ||
66 | device_type = "i2c"; | ||
67 | compatible = "fsl-i2c"; | ||
68 | reg = <3000 100>; | ||
69 | interrupts = <1b 2>; | ||
70 | interrupt-parent = <40000>; | ||
71 | dfsrr; | ||
72 | }; | ||
73 | |||
74 | i2c@3100 { | ||
75 | device_type = "i2c"; | ||
76 | compatible = "fsl-i2c"; | ||
77 | reg = <3100 100>; | ||
78 | interrupts = <1b 2>; | ||
79 | interrupt-parent = <40000>; | ||
80 | dfsrr; | ||
81 | }; | ||
82 | |||
83 | mdio@24520 { | ||
84 | #address-cells = <1>; | ||
85 | #size-cells = <0>; | ||
86 | device_type = "mdio"; | ||
87 | compatible = "gianfar"; | ||
88 | reg = <24520 20>; | ||
89 | linux,phandle = <24520>; | ||
90 | ethernet-phy@0 { | ||
91 | linux,phandle = <2452000>; | ||
92 | interrupt-parent = <40000>; | ||
93 | interrupts = <31 1>; | ||
94 | reg = <0>; | ||
95 | device_type = "ethernet-phy"; | ||
96 | }; | ||
97 | ethernet-phy@1 { | ||
98 | linux,phandle = <2452001>; | ||
99 | interrupt-parent = <40000>; | ||
100 | interrupts = <32 1>; | ||
101 | reg = <1>; | ||
102 | device_type = "ethernet-phy"; | ||
103 | }; | ||
104 | |||
105 | ethernet-phy@2 { | ||
106 | linux,phandle = <2452002>; | ||
107 | interrupt-parent = <40000>; | ||
108 | interrupts = <31 1>; | ||
109 | reg = <2>; | ||
110 | device_type = "ethernet-phy"; | ||
111 | }; | ||
112 | ethernet-phy@3 { | ||
113 | linux,phandle = <2452003>; | ||
114 | interrupt-parent = <40000>; | ||
115 | interrupts = <32 1>; | ||
116 | reg = <3>; | ||
117 | device_type = "ethernet-phy"; | ||
118 | }; | ||
119 | }; | ||
120 | |||
121 | ethernet@24000 { | ||
122 | #address-cells = <1>; | ||
123 | #size-cells = <0>; | ||
124 | device_type = "network"; | ||
125 | model = "eTSEC"; | ||
126 | compatible = "gianfar"; | ||
127 | reg = <24000 1000>; | ||
128 | mac-address = [ 00 00 00 00 00 00 ]; | ||
129 | interrupts = <d 2 e 2 12 2>; | ||
130 | interrupt-parent = <40000>; | ||
131 | phy-handle = <2452002>; | ||
132 | }; | ||
133 | |||
134 | ethernet@25000 { | ||
135 | #address-cells = <1>; | ||
136 | #size-cells = <0>; | ||
137 | device_type = "network"; | ||
138 | model = "eTSEC"; | ||
139 | compatible = "gianfar"; | ||
140 | reg = <25000 1000>; | ||
141 | mac-address = [ 00 00 00 00 00 00]; | ||
142 | interrupts = <13 2 14 2 18 2>; | ||
143 | interrupt-parent = <40000>; | ||
144 | phy-handle = <2452003>; | ||
145 | }; | ||
146 | |||
147 | serial@4500 { | ||
148 | device_type = "serial"; | ||
149 | compatible = "ns16550"; | ||
150 | reg = <4500 100>; | ||
151 | clock-frequency = <0>; | ||
152 | interrupts = <1a 2>; | ||
153 | interrupt-parent = <40000>; | ||
154 | }; | ||
155 | |||
156 | serial@4600 { | ||
157 | device_type = "serial"; | ||
158 | compatible = "ns16550"; | ||
159 | reg = <4600 100>; | ||
160 | clock-frequency = <0>; | ||
161 | interrupts = <1a 2>; | ||
162 | interrupt-parent = <40000>; | ||
163 | }; | ||
164 | |||
165 | crypto@30000 { | ||
166 | device_type = "crypto"; | ||
167 | model = "SEC2"; | ||
168 | compatible = "talitos"; | ||
169 | reg = <30000 f000>; | ||
170 | interrupts = <1d 2>; | ||
171 | interrupt-parent = <40000>; | ||
172 | num-channels = <4>; | ||
173 | channel-fifo-len = <18>; | ||
174 | exec-units-mask = <000000fe>; | ||
175 | descriptor-types-mask = <012b0ebf>; | ||
176 | }; | ||
177 | |||
178 | pic@40000 { | ||
179 | linux,phandle = <40000>; | ||
180 | clock-frequency = <0>; | ||
181 | interrupt-controller; | ||
182 | #address-cells = <0>; | ||
183 | #interrupt-cells = <2>; | ||
184 | reg = <40000 40000>; | ||
185 | built-in; | ||
186 | compatible = "chrp,open-pic"; | ||
187 | device_type = "open-pic"; | ||
188 | big-endian; | ||
189 | }; | ||
190 | par_io@e0100 { | ||
191 | reg = <e0100 100>; | ||
192 | device_type = "par_io"; | ||
193 | num-ports = <7>; | ||
194 | |||
195 | ucc_pin@01 { | ||
196 | linux,phandle = <e010001>; | ||
197 | pio-map = < | ||
198 | /* port pin dir open_drain assignment has_irq */ | ||
199 | 4 0a 1 0 2 0 /* TxD0 */ | ||
200 | 4 09 1 0 2 0 /* TxD1 */ | ||
201 | 4 08 1 0 2 0 /* TxD2 */ | ||
202 | 4 07 1 0 2 0 /* TxD3 */ | ||
203 | 4 17 1 0 2 0 /* TxD4 */ | ||
204 | 4 16 1 0 2 0 /* TxD5 */ | ||
205 | 4 15 1 0 2 0 /* TxD6 */ | ||
206 | 4 14 1 0 2 0 /* TxD7 */ | ||
207 | 4 0f 2 0 2 0 /* RxD0 */ | ||
208 | 4 0e 2 0 2 0 /* RxD1 */ | ||
209 | 4 0d 2 0 2 0 /* RxD2 */ | ||
210 | 4 0c 2 0 2 0 /* RxD3 */ | ||
211 | 4 1d 2 0 2 0 /* RxD4 */ | ||
212 | 4 1c 2 0 2 0 /* RxD5 */ | ||
213 | 4 1b 2 0 2 0 /* RxD6 */ | ||
214 | 4 1a 2 0 2 0 /* RxD7 */ | ||
215 | 4 0b 1 0 2 0 /* TX_EN */ | ||
216 | 4 18 1 0 2 0 /* TX_ER */ | ||
217 | 4 0f 2 0 2 0 /* RX_DV */ | ||
218 | 4 1e 2 0 2 0 /* RX_ER */ | ||
219 | 4 11 2 0 2 0 /* RX_CLK */ | ||
220 | 4 13 1 0 2 0 /* GTX_CLK */ | ||
221 | 1 1f 2 0 3 0>; /* GTX125 */ | ||
222 | }; | ||
223 | ucc_pin@02 { | ||
224 | linux,phandle = <e010002>; | ||
225 | pio-map = < | ||
226 | /* port pin dir open_drain assignment has_irq */ | ||
227 | 5 0a 1 0 2 0 /* TxD0 */ | ||
228 | 5 09 1 0 2 0 /* TxD1 */ | ||
229 | 5 08 1 0 2 0 /* TxD2 */ | ||
230 | 5 07 1 0 2 0 /* TxD3 */ | ||
231 | 5 17 1 0 2 0 /* TxD4 */ | ||
232 | 5 16 1 0 2 0 /* TxD5 */ | ||
233 | 5 15 1 0 2 0 /* TxD6 */ | ||
234 | 5 14 1 0 2 0 /* TxD7 */ | ||
235 | 5 0f 2 0 2 0 /* RxD0 */ | ||
236 | 5 0e 2 0 2 0 /* RxD1 */ | ||
237 | 5 0d 2 0 2 0 /* RxD2 */ | ||
238 | 5 0c 2 0 2 0 /* RxD3 */ | ||
239 | 5 1d 2 0 2 0 /* RxD4 */ | ||
240 | 5 1c 2 0 2 0 /* RxD5 */ | ||
241 | 5 1b 2 0 2 0 /* RxD6 */ | ||
242 | 5 1a 2 0 2 0 /* RxD7 */ | ||
243 | 5 0b 1 0 2 0 /* TX_EN */ | ||
244 | 5 18 1 0 2 0 /* TX_ER */ | ||
245 | 5 10 2 0 2 0 /* RX_DV */ | ||
246 | 5 1e 2 0 2 0 /* RX_ER */ | ||
247 | 5 11 2 0 2 0 /* RX_CLK */ | ||
248 | 5 13 1 0 2 0 /* GTX_CLK */ | ||
249 | 1 1f 2 0 3 0 /* GTX125 */ | ||
250 | 4 06 3 0 2 0 /* MDIO */ | ||
251 | 4 05 1 0 2 0>; /* MDC */ | ||
252 | }; | ||
253 | }; | ||
254 | }; | ||
255 | |||
256 | qe@e0080000 { | ||
257 | #address-cells = <1>; | ||
258 | #size-cells = <1>; | ||
259 | device_type = "qe"; | ||
260 | model = "QE"; | ||
261 | ranges = <0 e0080000 00040000>; | ||
262 | reg = <e0080000 480>; | ||
263 | brg-frequency = <0>; | ||
264 | bus-frequency = <179A7B00>; | ||
265 | |||
266 | muram@10000 { | ||
267 | device_type = "muram"; | ||
268 | ranges = <0 00010000 0000c000>; | ||
269 | |||
270 | data-only@0{ | ||
271 | reg = <0 c000>; | ||
272 | }; | ||
273 | }; | ||
274 | |||
275 | spi@4c0 { | ||
276 | device_type = "spi"; | ||
277 | compatible = "fsl_spi"; | ||
278 | reg = <4c0 40>; | ||
279 | interrupts = <2>; | ||
280 | interrupt-parent = <80>; | ||
281 | mode = "cpu"; | ||
282 | }; | ||
283 | |||
284 | spi@500 { | ||
285 | device_type = "spi"; | ||
286 | compatible = "fsl_spi"; | ||
287 | reg = <500 40>; | ||
288 | interrupts = <1>; | ||
289 | interrupt-parent = <80>; | ||
290 | mode = "cpu"; | ||
291 | }; | ||
292 | |||
293 | ucc@2000 { | ||
294 | device_type = "network"; | ||
295 | compatible = "ucc_geth"; | ||
296 | model = "UCC"; | ||
297 | device-id = <1>; | ||
298 | reg = <2000 200>; | ||
299 | interrupts = <20>; | ||
300 | interrupt-parent = <80>; | ||
301 | mac-address = [ 00 04 9f 00 23 23 ]; | ||
302 | rx-clock = <0>; | ||
303 | tx-clock = <19>; | ||
304 | phy-handle = <212000>; | ||
305 | pio-handle = <e010001>; | ||
306 | }; | ||
307 | |||
308 | ucc@3000 { | ||
309 | device_type = "network"; | ||
310 | compatible = "ucc_geth"; | ||
311 | model = "UCC"; | ||
312 | device-id = <2>; | ||
313 | reg = <3000 200>; | ||
314 | interrupts = <21>; | ||
315 | interrupt-parent = <80>; | ||
316 | mac-address = [ 00 11 22 33 44 55 ]; | ||
317 | rx-clock = <0>; | ||
318 | tx-clock = <14>; | ||
319 | phy-handle = <212001>; | ||
320 | pio-handle = <e010002>; | ||
321 | }; | ||
322 | |||
323 | mdio@2120 { | ||
324 | #address-cells = <1>; | ||
325 | #size-cells = <0>; | ||
326 | reg = <2120 18>; | ||
327 | device_type = "mdio"; | ||
328 | compatible = "ucc_geth_phy"; | ||
329 | |||
330 | /* These are the same PHYs as on | ||
331 | * gianfar's MDIO bus */ | ||
332 | ethernet-phy@00 { | ||
333 | linux,phandle = <212000>; | ||
334 | interrupt-parent = <40000>; | ||
335 | interrupts = <31 1>; | ||
336 | reg = <0>; | ||
337 | device_type = "ethernet-phy"; | ||
338 | interface = <6>; //ENET_1000_GMII | ||
339 | }; | ||
340 | ethernet-phy@01 { | ||
341 | linux,phandle = <212001>; | ||
342 | interrupt-parent = <40000>; | ||
343 | interrupts = <32 1>; | ||
344 | reg = <1>; | ||
345 | device_type = "ethernet-phy"; | ||
346 | interface = <6>; | ||
347 | }; | ||
348 | ethernet-phy@02 { | ||
349 | linux,phandle = <212002>; | ||
350 | interrupt-parent = <40000>; | ||
351 | interrupts = <31 1>; | ||
352 | reg = <2>; | ||
353 | device_type = "ethernet-phy"; | ||
354 | interface = <6>; //ENET_1000_GMII | ||
355 | }; | ||
356 | ethernet-phy@03 { | ||
357 | linux,phandle = <212003>; | ||
358 | interrupt-parent = <40000>; | ||
359 | interrupts = <32 1>; | ||
360 | reg = <3>; | ||
361 | device_type = "ethernet-phy"; | ||
362 | interface = <6>; //ENET_1000_GMII | ||
363 | }; | ||
364 | }; | ||
365 | |||
366 | qeic@80 { | ||
367 | linux,phandle = <80>; | ||
368 | interrupt-controller; | ||
369 | device_type = "qeic"; | ||
370 | #address-cells = <0>; | ||
371 | #interrupt-cells = <1>; | ||
372 | reg = <80 80>; | ||
373 | built-in; | ||
374 | big-endian; | ||
375 | interrupts = <1e 2 1e 2>; //high:30 low:30 | ||
376 | interrupt-parent = <40000>; | ||
377 | }; | ||
378 | |||
379 | }; | ||
380 | }; | ||
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig index 0584f3c7e884..0efdd2f1babe 100644 --- a/arch/powerpc/platforms/85xx/Kconfig +++ b/arch/powerpc/platforms/85xx/Kconfig | |||
@@ -23,6 +23,13 @@ config MPC85xx_CDS | |||
23 | help | 23 | help |
24 | This option enables support for the MPC85xx CDS board | 24 | This option enables support for the MPC85xx CDS board |
25 | 25 | ||
26 | config MPC8568_MDS | ||
27 | bool "Freescale MPC8568 MDS" | ||
28 | select DEFAULT_UIMAGE | ||
29 | # select QUICC_ENGINE | ||
30 | help | ||
31 | This option enables support for the MPC8568 MDS board | ||
32 | |||
26 | endchoice | 33 | endchoice |
27 | 34 | ||
28 | config MPC8540 | 35 | config MPC8540 |
@@ -36,6 +43,12 @@ config MPC8560 | |||
36 | select PPC_INDIRECT_PCI | 43 | select PPC_INDIRECT_PCI |
37 | default y if MPC8560_ADS | 44 | default y if MPC8560_ADS |
38 | 45 | ||
46 | config MPC85xx | ||
47 | bool | ||
48 | select PPC_UDBG_16550 | ||
49 | select PPC_INDIRECT_PCI | ||
50 | default y if MPC8540_ADS || MPC85xx_CDS || MPC8560_ADS || MPC8568_MDS | ||
51 | |||
39 | config PPC_INDIRECT_PCI_BE | 52 | config PPC_INDIRECT_PCI_BE |
40 | bool | 53 | bool |
41 | depends on PPC_85xx | 54 | depends on PPC_85xx |
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile index 282f5d0d0152..e40e521816b8 100644 --- a/arch/powerpc/platforms/85xx/Makefile +++ b/arch/powerpc/platforms/85xx/Makefile | |||
@@ -5,3 +5,4 @@ obj-$(CONFIG_PPC_85xx) += misc.o pci.o | |||
5 | obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o | 5 | obj-$(CONFIG_MPC8540_ADS) += mpc85xx_ads.o |
6 | obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o | 6 | obj-$(CONFIG_MPC8560_ADS) += mpc85xx_ads.o |
7 | obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o | 7 | obj-$(CONFIG_MPC85xx_CDS) += mpc85xx_cds.o |
8 | obj-$(CONFIG_MPC8568_MDS) += mpc8568_mds.o | ||
diff --git a/arch/powerpc/platforms/85xx/mpc8568_mds.c b/arch/powerpc/platforms/85xx/mpc8568_mds.c new file mode 100644 index 000000000000..0861d1107bc8 --- /dev/null +++ b/arch/powerpc/platforms/85xx/mpc8568_mds.c | |||
@@ -0,0 +1,246 @@ | |||
1 | /* | ||
2 | * Copyright (C) Freescale Semicondutor, Inc. 2006-2007. All rights reserved. | ||
3 | * | ||
4 | * Author: Andy Fleming <afleming@freescale.com> | ||
5 | * | ||
6 | * Based on 83xx/mpc8360e_pb.c by: | ||
7 | * Li Yang <LeoLi@freescale.com> | ||
8 | * Yin Olivia <Hong-hua.Yin@freescale.com> | ||
9 | * | ||
10 | * Description: | ||
11 | * MPC8568E MDS PB board specific routines. | ||
12 | * | ||
13 | * This program is free software; you can redistribute it and/or modify it | ||
14 | * under the terms of the GNU General Public License as published by the | ||
15 | * Free Software Foundation; either version 2 of the License, or (at your | ||
16 | * option) any later version. | ||
17 | */ | ||
18 | |||
19 | #include <linux/stddef.h> | ||
20 | #include <linux/kernel.h> | ||
21 | #include <linux/init.h> | ||
22 | #include <linux/errno.h> | ||
23 | #include <linux/reboot.h> | ||
24 | #include <linux/pci.h> | ||
25 | #include <linux/kdev_t.h> | ||
26 | #include <linux/major.h> | ||
27 | #include <linux/console.h> | ||
28 | #include <linux/delay.h> | ||
29 | #include <linux/seq_file.h> | ||
30 | #include <linux/root_dev.h> | ||
31 | #include <linux/initrd.h> | ||
32 | #include <linux/module.h> | ||
33 | #include <linux/fsl_devices.h> | ||
34 | |||
35 | #include <asm/of_device.h> | ||
36 | #include <asm/of_platform.h> | ||
37 | #include <asm/system.h> | ||
38 | #include <asm/atomic.h> | ||
39 | #include <asm/time.h> | ||
40 | #include <asm/io.h> | ||
41 | #include <asm/machdep.h> | ||
42 | #include <asm/bootinfo.h> | ||
43 | #include <asm/pci-bridge.h> | ||
44 | #include <asm/mpc85xx.h> | ||
45 | #include <asm/irq.h> | ||
46 | #include <mm/mmu_decl.h> | ||
47 | #include <asm/prom.h> | ||
48 | #include <asm/udbg.h> | ||
49 | #include <sysdev/fsl_soc.h> | ||
50 | #include <asm/qe.h> | ||
51 | #include <asm/qe_ic.h> | ||
52 | #include <asm/mpic.h> | ||
53 | |||
54 | #include "mpc85xx.h" | ||
55 | |||
56 | #undef DEBUG | ||
57 | #ifdef DEBUG | ||
58 | #define DBG(fmt...) udbg_printf(fmt) | ||
59 | #else | ||
60 | #define DBG(fmt...) | ||
61 | #endif | ||
62 | |||
63 | #ifndef CONFIG_PCI | ||
64 | unsigned long isa_io_base = 0; | ||
65 | unsigned long isa_mem_base = 0; | ||
66 | #endif | ||
67 | |||
68 | /* ************************************************************************ | ||
69 | * | ||
70 | * Setup the architecture | ||
71 | * | ||
72 | */ | ||
73 | static void __init mpc8568_mds_setup_arch(void) | ||
74 | { | ||
75 | struct device_node *np; | ||
76 | static u8 *bcsr_regs = NULL; | ||
77 | |||
78 | |||
79 | if (ppc_md.progress) | ||
80 | ppc_md.progress("mpc8568_mds_setup_arch()", 0); | ||
81 | |||
82 | np = of_find_node_by_type(NULL, "cpu"); | ||
83 | if (np != NULL) { | ||
84 | const unsigned int *fp = | ||
85 | get_property(np, "clock-frequency", NULL); | ||
86 | if (fp != NULL) | ||
87 | loops_per_jiffy = *fp / HZ; | ||
88 | else | ||
89 | loops_per_jiffy = 50000000 / HZ; | ||
90 | of_node_put(np); | ||
91 | } | ||
92 | |||
93 | /* Map BCSR area */ | ||
94 | np = of_find_node_by_name(NULL, "bcsr"); | ||
95 | if (np != NULL) { | ||
96 | struct resource res; | ||
97 | |||
98 | of_address_to_resource(np, 0, &res); | ||
99 | bcsr_regs = ioremap(res.start, res.end - res.start +1); | ||
100 | of_node_put(np); | ||
101 | } | ||
102 | |||
103 | #ifdef CONFIG_PCI | ||
104 | for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;) { | ||
105 | add_bridge(np); | ||
106 | } | ||
107 | of_node_put(np); | ||
108 | #endif | ||
109 | |||
110 | #ifdef CONFIG_QUICC_ENGINE | ||
111 | if ((np = of_find_node_by_name(NULL, "qe")) != NULL) { | ||
112 | qe_reset(); | ||
113 | of_node_put(np); | ||
114 | } | ||
115 | |||
116 | if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) { | ||
117 | struct device_node *ucc = NULL; | ||
118 | |||
119 | par_io_init(np); | ||
120 | of_node_put(np); | ||
121 | |||
122 | for ( ;(ucc = of_find_node_by_name(ucc, "ucc")) != NULL;) | ||
123 | par_io_of_config(ucc); | ||
124 | |||
125 | of_node_put(ucc); | ||
126 | } | ||
127 | |||
128 | if (bcsr_regs) { | ||
129 | u8 bcsr_phy; | ||
130 | |||
131 | /* Reset the Ethernet PHY */ | ||
132 | bcsr_phy = in_be8(&bcsr_regs[9]); | ||
133 | bcsr_phy &= ~0x20; | ||
134 | out_be8(&bcsr_regs[9], bcsr_phy); | ||
135 | |||
136 | udelay(1000); | ||
137 | |||
138 | bcsr_phy = in_be8(&bcsr_regs[9]); | ||
139 | bcsr_phy |= 0x20; | ||
140 | out_be8(&bcsr_regs[9], bcsr_phy); | ||
141 | |||
142 | iounmap(bcsr_regs); | ||
143 | } | ||
144 | |||
145 | #endif /* CONFIG_QUICC_ENGINE */ | ||
146 | } | ||
147 | |||
148 | static struct of_device_id mpc8568_ids[] = { | ||
149 | { .type = "soc", }, | ||
150 | { .compatible = "soc", }, | ||
151 | { .type = "qe", }, | ||
152 | {}, | ||
153 | }; | ||
154 | |||
155 | static int __init mpc8568_publish_devices(void) | ||
156 | { | ||
157 | if (!machine_is(mpc8568_mds)) | ||
158 | return 0; | ||
159 | |||
160 | /* Publish the QE devices */ | ||
161 | of_platform_bus_probe(NULL,mpc8568_ids,NULL); | ||
162 | |||
163 | return 0; | ||
164 | } | ||
165 | device_initcall(mpc8568_publish_devices); | ||
166 | |||
167 | static void __init mpc8568_mds_pic_init(void) | ||
168 | { | ||
169 | struct mpic *mpic; | ||
170 | struct resource r; | ||
171 | struct device_node *np = NULL; | ||
172 | |||
173 | np = of_find_node_by_type(NULL, "open-pic"); | ||
174 | if (!np) | ||
175 | return; | ||
176 | |||
177 | if (of_address_to_resource(np, 0, &r)) { | ||
178 | printk(KERN_ERR "Failed to map mpic register space\n"); | ||
179 | of_node_put(np); | ||
180 | return; | ||
181 | } | ||
182 | |||
183 | mpic = mpic_alloc(np, r.start, | ||
184 | MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, | ||
185 | 4, 0, " OpenPIC "); | ||
186 | BUG_ON(mpic == NULL); | ||
187 | of_node_put(np); | ||
188 | |||
189 | /* Internal Interrupts */ | ||
190 | mpic_assign_isu(mpic, 0, r.start + 0x10200); | ||
191 | mpic_assign_isu(mpic, 1, r.start + 0x10280); | ||
192 | mpic_assign_isu(mpic, 2, r.start + 0x10300); | ||
193 | mpic_assign_isu(mpic, 3, r.start + 0x10380); | ||
194 | mpic_assign_isu(mpic, 4, r.start + 0x10400); | ||
195 | mpic_assign_isu(mpic, 5, r.start + 0x10480); | ||
196 | mpic_assign_isu(mpic, 6, r.start + 0x10500); | ||
197 | mpic_assign_isu(mpic, 7, r.start + 0x10580); | ||
198 | mpic_assign_isu(mpic, 8, r.start + 0x10600); | ||
199 | mpic_assign_isu(mpic, 9, r.start + 0x10680); | ||
200 | mpic_assign_isu(mpic, 10, r.start + 0x10700); | ||
201 | mpic_assign_isu(mpic, 11, r.start + 0x10780); | ||
202 | |||
203 | /* External Interrupts */ | ||
204 | mpic_assign_isu(mpic, 12, r.start + 0x10000); | ||
205 | mpic_assign_isu(mpic, 13, r.start + 0x10080); | ||
206 | mpic_assign_isu(mpic, 14, r.start + 0x10100); | ||
207 | |||
208 | mpic_init(mpic); | ||
209 | |||
210 | |||
211 | #ifdef CONFIG_QUICC_ENGINE | ||
212 | np = of_find_node_by_type(NULL, "qeic"); | ||
213 | if (!np) | ||
214 | return; | ||
215 | |||
216 | qe_ic_init(np, 0); | ||
217 | of_node_put(np); | ||
218 | #endif /* CONFIG_QUICC_ENGINE */ | ||
219 | } | ||
220 | |||
221 | |||
222 | static int __init mpc8568_mds_probe(void) | ||
223 | { | ||
224 | char *model = of_get_flat_dt_prop(of_get_flat_dt_root(), | ||
225 | "model", NULL); | ||
226 | if (model == NULL) | ||
227 | return 0; | ||
228 | if (strcmp(model, "MPC8568EMDS")) | ||
229 | return 0; | ||
230 | |||
231 | DBG("MPC8568EMDS found\n"); | ||
232 | |||
233 | return 1; | ||
234 | } | ||
235 | |||
236 | |||
237 | define_machine(mpc8568_mds) { | ||
238 | .name = "MPC8568E MDS", | ||
239 | .probe = mpc8568_mds_probe, | ||
240 | .setup_arch = mpc8568_mds_setup_arch, | ||
241 | .init_IRQ = mpc8568_mds_pic_init, | ||
242 | .get_irq = mpic_get_irq, | ||
243 | .restart = mpc85xx_restart, | ||
244 | .calibrate_decr = generic_calibrate_decr, | ||
245 | .progress = udbg_progress, | ||
246 | }; | ||