diff options
author | Brian King <brking@linux.vnet.ibm.com> | 2012-03-14 22:20:10 -0400 |
---|---|---|
committer | James Bottomley <JBottomley@Parallels.com> | 2012-03-28 10:04:47 -0400 |
commit | 89aad428317322044673cd9a3e1685a83abcba98 (patch) | |
tree | 44421af5c1c1bd61eee0cb8fb5f9b6f09c7ff2d1 | |
parent | a5fb407eed819e950e369060a822640582a1e538 (diff) |
[SCSI] ipr: Increase max concurrent oustanding commands
Increase the total number of max concurrent outstanding commands
for the most recent family of adapters in order to improve overall
adapter performance.
Signed-off-by: Brian King <brking@linux.vnet.ibm.com>
Signed-off-by: James Bottomley <JBottomley@Parallels.com>
-rw-r--r-- | drivers/scsi/ipr.c | 17 | ||||
-rw-r--r-- | drivers/scsi/ipr.h | 10 |
2 files changed, 23 insertions, 4 deletions
diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index 590997961a93..ada0af745a08 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c | |||
@@ -104,6 +104,7 @@ static DEFINE_SPINLOCK(ipr_driver_lock); | |||
104 | static const struct ipr_chip_cfg_t ipr_chip_cfg[] = { | 104 | static const struct ipr_chip_cfg_t ipr_chip_cfg[] = { |
105 | { /* Gemstone, Citrine, Obsidian, and Obsidian-E */ | 105 | { /* Gemstone, Citrine, Obsidian, and Obsidian-E */ |
106 | .mailbox = 0x0042C, | 106 | .mailbox = 0x0042C, |
107 | .max_cmds = 100, | ||
107 | .cache_line_size = 0x20, | 108 | .cache_line_size = 0x20, |
108 | .clear_isr = 1, | 109 | .clear_isr = 1, |
109 | { | 110 | { |
@@ -127,6 +128,7 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = { | |||
127 | }, | 128 | }, |
128 | { /* Snipe and Scamp */ | 129 | { /* Snipe and Scamp */ |
129 | .mailbox = 0x0052C, | 130 | .mailbox = 0x0052C, |
131 | .max_cmds = 100, | ||
130 | .cache_line_size = 0x20, | 132 | .cache_line_size = 0x20, |
131 | .clear_isr = 1, | 133 | .clear_isr = 1, |
132 | { | 134 | { |
@@ -150,6 +152,7 @@ static const struct ipr_chip_cfg_t ipr_chip_cfg[] = { | |||
150 | }, | 152 | }, |
151 | { /* CRoC */ | 153 | { /* CRoC */ |
152 | .mailbox = 0x00044, | 154 | .mailbox = 0x00044, |
155 | .max_cmds = 1000, | ||
153 | .cache_line_size = 0x20, | 156 | .cache_line_size = 0x20, |
154 | .clear_isr = 0, | 157 | .clear_isr = 0, |
155 | { | 158 | { |
@@ -8278,6 +8281,10 @@ static void ipr_free_cmd_blks(struct ipr_ioa_cfg *ioa_cfg) | |||
8278 | if (ioa_cfg->ipr_cmd_pool) | 8281 | if (ioa_cfg->ipr_cmd_pool) |
8279 | pci_pool_destroy (ioa_cfg->ipr_cmd_pool); | 8282 | pci_pool_destroy (ioa_cfg->ipr_cmd_pool); |
8280 | 8283 | ||
8284 | kfree(ioa_cfg->ipr_cmnd_list); | ||
8285 | kfree(ioa_cfg->ipr_cmnd_list_dma); | ||
8286 | ioa_cfg->ipr_cmnd_list = NULL; | ||
8287 | ioa_cfg->ipr_cmnd_list_dma = NULL; | ||
8281 | ioa_cfg->ipr_cmd_pool = NULL; | 8288 | ioa_cfg->ipr_cmd_pool = NULL; |
8282 | } | 8289 | } |
8283 | 8290 | ||
@@ -8358,6 +8365,14 @@ static int __devinit ipr_alloc_cmd_blks(struct ipr_ioa_cfg *ioa_cfg) | |||
8358 | if (!ioa_cfg->ipr_cmd_pool) | 8365 | if (!ioa_cfg->ipr_cmd_pool) |
8359 | return -ENOMEM; | 8366 | return -ENOMEM; |
8360 | 8367 | ||
8368 | ioa_cfg->ipr_cmnd_list = kcalloc(IPR_NUM_CMD_BLKS, sizeof(struct ipr_cmnd *), GFP_KERNEL); | ||
8369 | ioa_cfg->ipr_cmnd_list_dma = kcalloc(IPR_NUM_CMD_BLKS, sizeof(dma_addr_t), GFP_KERNEL); | ||
8370 | |||
8371 | if (!ioa_cfg->ipr_cmnd_list || !ioa_cfg->ipr_cmnd_list_dma) { | ||
8372 | ipr_free_cmd_blks(ioa_cfg); | ||
8373 | return -ENOMEM; | ||
8374 | } | ||
8375 | |||
8361 | for (i = 0; i < IPR_NUM_CMD_BLKS; i++) { | 8376 | for (i = 0; i < IPR_NUM_CMD_BLKS; i++) { |
8362 | ipr_cmd = pci_pool_alloc (ioa_cfg->ipr_cmd_pool, GFP_KERNEL, &dma_addr); | 8377 | ipr_cmd = pci_pool_alloc (ioa_cfg->ipr_cmd_pool, GFP_KERNEL, &dma_addr); |
8363 | 8378 | ||
@@ -8585,6 +8600,7 @@ static void __devinit ipr_init_ioa_cfg(struct ipr_ioa_cfg *ioa_cfg, | |||
8585 | host->max_channel = IPR_MAX_BUS_TO_SCAN; | 8600 | host->max_channel = IPR_MAX_BUS_TO_SCAN; |
8586 | host->unique_id = host->host_no; | 8601 | host->unique_id = host->host_no; |
8587 | host->max_cmd_len = IPR_MAX_CDB_LEN; | 8602 | host->max_cmd_len = IPR_MAX_CDB_LEN; |
8603 | host->can_queue = ioa_cfg->max_cmds; | ||
8588 | pci_set_drvdata(pdev, ioa_cfg); | 8604 | pci_set_drvdata(pdev, ioa_cfg); |
8589 | 8605 | ||
8590 | p = &ioa_cfg->chip_cfg->regs; | 8606 | p = &ioa_cfg->chip_cfg->regs; |
@@ -8770,6 +8786,7 @@ static int __devinit ipr_probe_ioa(struct pci_dev *pdev, | |||
8770 | ioa_cfg->sis64 = ioa_cfg->ipr_chip->sis_type == IPR_SIS64 ? 1 : 0; | 8786 | ioa_cfg->sis64 = ioa_cfg->ipr_chip->sis_type == IPR_SIS64 ? 1 : 0; |
8771 | ioa_cfg->chip_cfg = ioa_cfg->ipr_chip->cfg; | 8787 | ioa_cfg->chip_cfg = ioa_cfg->ipr_chip->cfg; |
8772 | ioa_cfg->clear_isr = ioa_cfg->chip_cfg->clear_isr; | 8788 | ioa_cfg->clear_isr = ioa_cfg->chip_cfg->clear_isr; |
8789 | ioa_cfg->max_cmds = ioa_cfg->chip_cfg->max_cmds; | ||
8773 | 8790 | ||
8774 | if (ipr_transop_timeout) | 8791 | if (ipr_transop_timeout) |
8775 | ioa_cfg->transop_timeout = ipr_transop_timeout; | 8792 | ioa_cfg->transop_timeout = ipr_transop_timeout; |
diff --git a/drivers/scsi/ipr.h b/drivers/scsi/ipr.h index 40cbee72b83c..a79de2aab469 100644 --- a/drivers/scsi/ipr.h +++ b/drivers/scsi/ipr.h | |||
@@ -53,7 +53,7 @@ | |||
53 | * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of | 53 | * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of |
54 | * ops the mid-layer can send to the adapter. | 54 | * ops the mid-layer can send to the adapter. |
55 | */ | 55 | */ |
56 | #define IPR_NUM_BASE_CMD_BLKS 100 | 56 | #define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds) |
57 | 57 | ||
58 | #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339 | 58 | #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339 |
59 | 59 | ||
@@ -153,7 +153,7 @@ | |||
153 | #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \ | 153 | #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \ |
154 | ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4) | 154 | ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4) |
155 | 155 | ||
156 | #define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS | 156 | #define IPR_MAX_COMMANDS 100 |
157 | #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \ | 157 | #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \ |
158 | IPR_NUM_INTERNAL_CMD_BLKS) | 158 | IPR_NUM_INTERNAL_CMD_BLKS) |
159 | 159 | ||
@@ -1305,6 +1305,7 @@ struct ipr_interrupts { | |||
1305 | 1305 | ||
1306 | struct ipr_chip_cfg_t { | 1306 | struct ipr_chip_cfg_t { |
1307 | u32 mailbox; | 1307 | u32 mailbox; |
1308 | u16 max_cmds; | ||
1308 | u8 cache_line_size; | 1309 | u8 cache_line_size; |
1309 | u8 clear_isr; | 1310 | u8 clear_isr; |
1310 | struct ipr_interrupt_offsets regs; | 1311 | struct ipr_interrupt_offsets regs; |
@@ -1503,8 +1504,9 @@ struct ipr_ioa_cfg { | |||
1503 | struct ata_host ata_host; | 1504 | struct ata_host ata_host; |
1504 | char ipr_cmd_label[8]; | 1505 | char ipr_cmd_label[8]; |
1505 | #define IPR_CMD_LABEL "ipr_cmd" | 1506 | #define IPR_CMD_LABEL "ipr_cmd" |
1506 | struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS]; | 1507 | u32 max_cmds; |
1507 | dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS]; | 1508 | struct ipr_cmnd **ipr_cmnd_list; |
1509 | dma_addr_t *ipr_cmnd_list_dma; | ||
1508 | }; /* struct ipr_ioa_cfg */ | 1510 | }; /* struct ipr_ioa_cfg */ |
1509 | 1511 | ||
1510 | struct ipr_cmnd { | 1512 | struct ipr_cmnd { |