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authorKumar Gala <galak@kernel.crashing.org>2011-05-09 15:13:13 -0400
committerKumar Gala <galak@kernel.crashing.org>2011-06-22 22:44:52 -0400
commit169296b38f06b981ee7163aaa1c03f03953cc37f (patch)
tree40f3c64b077b702c40b1f4a7c46fe5399a4467e0
parente181877d8674b7e157f6efe6567d2ab78c4b4955 (diff)
powerpc/85xx: Updates to P4080DS device tree
* Added BSD dual-license * Moved mpic-parent to root so we dont need to duplicate everywhere * Added next level cache from L2 to CPC * Moved to 4-cell MPIC interrupt properties * Added 3 MSI banks * Added numerous missing nodes: soc-sram-error, guts, pins, clockgen, rcpm, sfp, serdes, etc. * Reworked PCIe interrupts to be at virtual bridge level Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat
-rw-r--r--arch/powerpc/boot/dts/p4080ds.dts329
1 files changed, 222 insertions, 107 deletions
diff --git a/arch/powerpc/boot/dts/p4080ds.dts b/arch/powerpc/boot/dts/p4080ds.dts
index 927f94d16e9b..5b083bbf5878 100644
--- a/arch/powerpc/boot/dts/p4080ds.dts
+++ b/arch/powerpc/boot/dts/p4080ds.dts
@@ -3,10 +3,33 @@
3 * 3 *
4 * Copyright 2009-2011 Freescale Semiconductor Inc. 4 * Copyright 2009-2011 Freescale Semiconductor Inc.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * Redistribution and use in source and binary forms, with or without
7 * under the terms of the GNU General Public License as published by the 7 * modification, are permitted provided that the following conditions are met:
8 * Free Software Foundation; either version 2 of the License, or (at your 8 * * Redistributions of source code must retain the above copyright
9 * option) any later version. 9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10 */ 33 */
11 34
12/dts-v1/; 35/dts-v1/;
@@ -16,6 +39,7 @@
16 compatible = "fsl,P4080DS"; 39 compatible = "fsl,P4080DS";
17 #address-cells = <2>; 40 #address-cells = <2>;
18 #size-cells = <2>; 41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
19 43
20 aliases { 44 aliases {
21 ccsr = &soc; 45 ccsr = &soc;
@@ -32,6 +56,9 @@
32 dma0 = &dma0; 56 dma0 = &dma0;
33 dma1 = &dma1; 57 dma1 = &dma1;
34 sdhc = &sdhc; 58 sdhc = &sdhc;
59 msi0 = &msi0;
60 msi1 = &msi1;
61 msi2 = &msi2;
35 62
36 crypto = &crypto; 63 crypto = &crypto;
37 sec_jr0 = &sec_jr0; 64 sec_jr0 = &sec_jr0;
@@ -56,6 +83,7 @@
56 reg = <0>; 83 reg = <0>;
57 next-level-cache = <&L2_0>; 84 next-level-cache = <&L2_0>;
58 L2_0: l2-cache { 85 L2_0: l2-cache {
86 next-level-cache = <&cpc>;
59 }; 87 };
60 }; 88 };
61 cpu1: PowerPC,4080@1 { 89 cpu1: PowerPC,4080@1 {
@@ -63,6 +91,7 @@
63 reg = <1>; 91 reg = <1>;
64 next-level-cache = <&L2_1>; 92 next-level-cache = <&L2_1>;
65 L2_1: l2-cache { 93 L2_1: l2-cache {
94 next-level-cache = <&cpc>;
66 }; 95 };
67 }; 96 };
68 cpu2: PowerPC,4080@2 { 97 cpu2: PowerPC,4080@2 {
@@ -70,6 +99,7 @@
70 reg = <2>; 99 reg = <2>;
71 next-level-cache = <&L2_2>; 100 next-level-cache = <&L2_2>;
72 L2_2: l2-cache { 101 L2_2: l2-cache {
102 next-level-cache = <&cpc>;
73 }; 103 };
74 }; 104 };
75 cpu3: PowerPC,4080@3 { 105 cpu3: PowerPC,4080@3 {
@@ -77,6 +107,7 @@
77 reg = <3>; 107 reg = <3>;
78 next-level-cache = <&L2_3>; 108 next-level-cache = <&L2_3>;
79 L2_3: l2-cache { 109 L2_3: l2-cache {
110 next-level-cache = <&cpc>;
80 }; 111 };
81 }; 112 };
82 cpu4: PowerPC,4080@4 { 113 cpu4: PowerPC,4080@4 {
@@ -84,6 +115,7 @@
84 reg = <4>; 115 reg = <4>;
85 next-level-cache = <&L2_4>; 116 next-level-cache = <&L2_4>;
86 L2_4: l2-cache { 117 L2_4: l2-cache {
118 next-level-cache = <&cpc>;
87 }; 119 };
88 }; 120 };
89 cpu5: PowerPC,4080@5 { 121 cpu5: PowerPC,4080@5 {
@@ -91,6 +123,7 @@
91 reg = <5>; 123 reg = <5>;
92 next-level-cache = <&L2_5>; 124 next-level-cache = <&L2_5>;
93 L2_5: l2-cache { 125 L2_5: l2-cache {
126 next-level-cache = <&cpc>;
94 }; 127 };
95 }; 128 };
96 cpu6: PowerPC,4080@6 { 129 cpu6: PowerPC,4080@6 {
@@ -98,6 +131,7 @@
98 reg = <6>; 131 reg = <6>;
99 next-level-cache = <&L2_6>; 132 next-level-cache = <&L2_6>;
100 L2_6: l2-cache { 133 L2_6: l2-cache {
134 next-level-cache = <&cpc>;
101 }; 135 };
102 }; 136 };
103 cpu7: PowerPC,4080@7 { 137 cpu7: PowerPC,4080@7 {
@@ -105,6 +139,7 @@
105 reg = <7>; 139 reg = <7>;
106 next-level-cache = <&L2_7>; 140 next-level-cache = <&L2_7>;
107 L2_7: l2-cache { 141 L2_7: l2-cache {
142 next-level-cache = <&cpc>;
108 }; 143 };
109 }; 144 };
110 }; 145 };
@@ -121,6 +156,11 @@
121 ranges = <0x00000000 0xf 0xfe000000 0x1000000>; 156 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
122 reg = <0xf 0xfe000000 0 0x00001000>; 157 reg = <0xf 0xfe000000 0 0x00001000>;
123 158
159 soc-sram-error {
160 compatible = "fsl,soc-sram-error";
161 interrupts = <16 2 1 29>;
162 };
163
124 corenet-law@0 { 164 corenet-law@0 {
125 compatible = "fsl,corenet-law"; 165 compatible = "fsl,corenet-law";
126 reg = <0x0 0x1000>; 166 reg = <0x0 0x1000>;
@@ -128,42 +168,132 @@
128 }; 168 };
129 169
130 memory-controller@8000 { 170 memory-controller@8000 {
131 compatible = "fsl,p4080-memory-controller"; 171 compatible = "fsl,qoriq-memory-controller-v4.4", "fsl,qoriq-memory-controller";
132 reg = <0x8000 0x1000>; 172 reg = <0x8000 0x1000>;
133 interrupt-parent = <&mpic>; 173 interrupts = <16 2 1 23>;
134 interrupts = <0x12 2>;
135 }; 174 };
136 175
137 memory-controller@9000 { 176 memory-controller@9000 {
138 compatible = "fsl,p4080-memory-controller"; 177 compatible = "fsl,qoriq-memory-controller-v4.4","fsl,qoriq-memory-controller";
139 reg = <0x9000 0x1000>; 178 reg = <0x9000 0x1000>;
140 interrupt-parent = <&mpic>; 179 interrupts = <16 2 1 22>;
141 interrupts = <0x12 2>; 180 };
181
182 cpc: l3-cache-controller@10000 {
183 compatible = "fsl,p4080-l3-cache-controller", "cache";
184 reg = <0x10000 0x1000
185 0x11000 0x1000>;
186 interrupts = <16 2 1 27
187 16 2 1 26>;
142 }; 188 };
143 189
144 corenet-cf@18000 { 190 corenet-cf@18000 {
145 compatible = "fsl,corenet-cf"; 191 compatible = "fsl,corenet-cf";
146 reg = <0x18000 0x1000>; 192 reg = <0x18000 0x1000>;
193 interrupts = <16 2 1 31>;
147 fsl,ccf-num-csdids = <32>; 194 fsl,ccf-num-csdids = <32>;
148 fsl,ccf-num-snoopids = <32>; 195 fsl,ccf-num-snoopids = <32>;
149 }; 196 };
150 197
151 iommu@20000 { 198 iommu@20000 {
152 compatible = "fsl,p4080-pamu"; 199 compatible = "fsl,pamu-v1.0", "fsl,pamu";
153 reg = <0x20000 0x10000>; 200 reg = <0x20000 0x5000>;
154 interrupts = <24 2>; 201 interrupts = <
155 interrupt-parent = <&mpic>; 202 24 2 0 0
203 16 2 1 30>;
156 }; 204 };
157 205
158 mpic: pic@40000 { 206 mpic: pic@40000 {
207 clock-frequency = <0>;
159 interrupt-controller; 208 interrupt-controller;
160 #address-cells = <0>; 209 #address-cells = <0>;
161 #interrupt-cells = <2>; 210 #interrupt-cells = <4>;
162 reg = <0x40000 0x40000>; 211 reg = <0x40000 0x40000>;
163 compatible = "chrp,open-pic"; 212 compatible = "fsl,mpic", "chrp,open-pic";
164 device_type = "open-pic"; 213 device_type = "open-pic";
165 }; 214 };
166 215
216 msi0: msi@41600 {
217 compatible = "fsl,mpic-msi";
218 reg = <0x41600 0x200>;
219 msi-available-ranges = <0 0x100>;
220 interrupts = <
221 0xe0 0 0 0
222 0xe1 0 0 0
223 0xe2 0 0 0
224 0xe3 0 0 0
225 0xe4 0 0 0
226 0xe5 0 0 0
227 0xe6 0 0 0
228 0xe7 0 0 0>;
229 };
230
231 msi1: msi@41800 {
232 compatible = "fsl,mpic-msi";
233 reg = <0x41800 0x200>;
234 msi-available-ranges = <0 0x100>;
235 interrupts = <
236 0xe8 0 0 0
237 0xe9 0 0 0
238 0xea 0 0 0
239 0xeb 0 0 0
240 0xec 0 0 0
241 0xed 0 0 0
242 0xee 0 0 0
243 0xef 0 0 0>;
244 };
245
246 msi2: msi@41a00 {
247 compatible = "fsl,mpic-msi";
248 reg = <0x41a00 0x200>;
249 msi-available-ranges = <0 0x100>;
250 interrupts = <
251 0xf0 0 0 0
252 0xf1 0 0 0
253 0xf2 0 0 0
254 0xf3 0 0 0
255 0xf4 0 0 0
256 0xf5 0 0 0
257 0xf6 0 0 0
258 0xf7 0 0 0>;
259 };
260
261 guts: global-utilities@e0000 {
262 compatible = "fsl,qoriq-device-config-1.0";
263 reg = <0xe0000 0xe00>;
264 fsl,has-rstcr;
265 #sleep-cells = <1>;
266 fsl,liodn-bits = <12>;
267 };
268
269 pins: global-utilities@e0e00 {
270 compatible = "fsl,qoriq-pin-control-1.0";
271 reg = <0xe0e00 0x200>;
272 #sleep-cells = <2>;
273 };
274
275 clockgen: global-utilities@e1000 {
276 compatible = "fsl,p4080-clockgen", "fsl,qoriq-clockgen-1.0";
277 reg = <0xe1000 0x1000>;
278 clock-frequency = <0>;
279 };
280
281 rcpm: global-utilities@e2000 {
282 compatible = "fsl,qoriq-rcpm-1.0";
283 reg = <0xe2000 0x1000>;
284 #sleep-cells = <1>;
285 };
286
287 sfp: sfp@e8000 {
288 compatible = "fsl,p4080-sfp", "fsl,qoriq-sfp-1.0";
289 reg = <0xe8000 0x1000>;
290 };
291
292 serdes: serdes@ea000 {
293 compatible = "fsl,p4080-serdes";
294 reg = <0xea000 0x1000>;
295 };
296
167 dma0: dma@100300 { 297 dma0: dma@100300 {
168 #address-cells = <1>; 298 #address-cells = <1>;
169 #size-cells = <1>; 299 #size-cells = <1>;
@@ -176,32 +306,28 @@
176 "fsl,eloplus-dma-channel"; 306 "fsl,eloplus-dma-channel";
177 reg = <0x0 0x80>; 307 reg = <0x0 0x80>;
178 cell-index = <0>; 308 cell-index = <0>;
179 interrupt-parent = <&mpic>; 309 interrupts = <28 2 0 0>;
180 interrupts = <28 2>;
181 }; 310 };
182 dma-channel@80 { 311 dma-channel@80 {
183 compatible = "fsl,p4080-dma-channel", 312 compatible = "fsl,p4080-dma-channel",
184 "fsl,eloplus-dma-channel"; 313 "fsl,eloplus-dma-channel";
185 reg = <0x80 0x80>; 314 reg = <0x80 0x80>;
186 cell-index = <1>; 315 cell-index = <1>;
187 interrupt-parent = <&mpic>; 316 interrupts = <29 2 0 0>;
188 interrupts = <29 2>;
189 }; 317 };
190 dma-channel@100 { 318 dma-channel@100 {
191 compatible = "fsl,p4080-dma-channel", 319 compatible = "fsl,p4080-dma-channel",
192 "fsl,eloplus-dma-channel"; 320 "fsl,eloplus-dma-channel";
193 reg = <0x100 0x80>; 321 reg = <0x100 0x80>;
194 cell-index = <2>; 322 cell-index = <2>;
195 interrupt-parent = <&mpic>; 323 interrupts = <30 2 0 0>;
196 interrupts = <30 2>;
197 }; 324 };
198 dma-channel@180 { 325 dma-channel@180 {
199 compatible = "fsl,p4080-dma-channel", 326 compatible = "fsl,p4080-dma-channel",
200 "fsl,eloplus-dma-channel"; 327 "fsl,eloplus-dma-channel";
201 reg = <0x180 0x80>; 328 reg = <0x180 0x80>;
202 cell-index = <3>; 329 cell-index = <3>;
203 interrupt-parent = <&mpic>; 330 interrupts = <31 2 0 0>;
204 interrupts = <31 2>;
205 }; 331 };
206 }; 332 };
207 333
@@ -217,32 +343,28 @@
217 "fsl,eloplus-dma-channel"; 343 "fsl,eloplus-dma-channel";
218 reg = <0x0 0x80>; 344 reg = <0x0 0x80>;
219 cell-index = <0>; 345 cell-index = <0>;
220 interrupt-parent = <&mpic>; 346 interrupts = <32 2 0 0>;
221 interrupts = <32 2>;
222 }; 347 };
223 dma-channel@80 { 348 dma-channel@80 {
224 compatible = "fsl,p4080-dma-channel", 349 compatible = "fsl,p4080-dma-channel",
225 "fsl,eloplus-dma-channel"; 350 "fsl,eloplus-dma-channel";
226 reg = <0x80 0x80>; 351 reg = <0x80 0x80>;
227 cell-index = <1>; 352 cell-index = <1>;
228 interrupt-parent = <&mpic>; 353 interrupts = <33 2 0 0>;
229 interrupts = <33 2>;
230 }; 354 };
231 dma-channel@100 { 355 dma-channel@100 {
232 compatible = "fsl,p4080-dma-channel", 356 compatible = "fsl,p4080-dma-channel",
233 "fsl,eloplus-dma-channel"; 357 "fsl,eloplus-dma-channel";
234 reg = <0x100 0x80>; 358 reg = <0x100 0x80>;
235 cell-index = <2>; 359 cell-index = <2>;
236 interrupt-parent = <&mpic>; 360 interrupts = <34 2 0 0>;
237 interrupts = <34 2>;
238 }; 361 };
239 dma-channel@180 { 362 dma-channel@180 {
240 compatible = "fsl,p4080-dma-channel", 363 compatible = "fsl,p4080-dma-channel",
241 "fsl,eloplus-dma-channel"; 364 "fsl,eloplus-dma-channel";
242 reg = <0x180 0x80>; 365 reg = <0x180 0x80>;
243 cell-index = <3>; 366 cell-index = <3>;
244 interrupt-parent = <&mpic>; 367 interrupts = <35 2 0 0>;
245 interrupts = <35 2>;
246 }; 368 };
247 }; 369 };
248 370
@@ -251,8 +373,7 @@
251 #size-cells = <0>; 373 #size-cells = <0>;
252 compatible = "fsl,p4080-espi", "fsl,mpc8536-espi"; 374 compatible = "fsl,p4080-espi", "fsl,mpc8536-espi";
253 reg = <0x110000 0x1000>; 375 reg = <0x110000 0x1000>;
254 interrupts = <53 0x2>; 376 interrupts = <53 0x2 0 0>;
255 interrupt-parent = <&mpic>;
256 fsl,espi-num-chipselects = <4>; 377 fsl,espi-num-chipselects = <4>;
257 378
258 flash@0 { 379 flash@0 {
@@ -286,10 +407,10 @@
286 sdhc: sdhc@114000 { 407 sdhc: sdhc@114000 {
287 compatible = "fsl,p4080-esdhc", "fsl,esdhc"; 408 compatible = "fsl,p4080-esdhc", "fsl,esdhc";
288 reg = <0x114000 0x1000>; 409 reg = <0x114000 0x1000>;
289 interrupts = <48 2>; 410 interrupts = <48 2 0 0>;
290 interrupt-parent = <&mpic>;
291 voltage-ranges = <3300 3300>; 411 voltage-ranges = <3300 3300>;
292 sdhci,auto-cmd12; 412 sdhci,auto-cmd12;
413 clock-frequency = <0>;
293 }; 414 };
294 415
295 i2c@118000 { 416 i2c@118000 {
@@ -298,8 +419,7 @@
298 cell-index = <0>; 419 cell-index = <0>;
299 compatible = "fsl-i2c"; 420 compatible = "fsl-i2c";
300 reg = <0x118000 0x100>; 421 reg = <0x118000 0x100>;
301 interrupts = <38 2>; 422 interrupts = <38 2 0 0>;
302 interrupt-parent = <&mpic>;
303 dfsrr; 423 dfsrr;
304 }; 424 };
305 425
@@ -309,8 +429,7 @@
309 cell-index = <1>; 429 cell-index = <1>;
310 compatible = "fsl-i2c"; 430 compatible = "fsl-i2c";
311 reg = <0x118100 0x100>; 431 reg = <0x118100 0x100>;
312 interrupts = <38 2>; 432 interrupts = <38 2 0 0>;
313 interrupt-parent = <&mpic>;
314 dfsrr; 433 dfsrr;
315 eeprom@51 { 434 eeprom@51 {
316 compatible = "at24,24c256"; 435 compatible = "at24,24c256";
@@ -323,8 +442,7 @@
323 rtc@68 { 442 rtc@68 {
324 compatible = "dallas,ds3232"; 443 compatible = "dallas,ds3232";
325 reg = <0x68>; 444 reg = <0x68>;
326 interrupts = <0 0x1>; 445 interrupts = <0x1 0x1 0 0>;
327 interrupt-parent = <&mpic>;
328 }; 446 };
329 }; 447 };
330 448
@@ -334,8 +452,7 @@
334 cell-index = <2>; 452 cell-index = <2>;
335 compatible = "fsl-i2c"; 453 compatible = "fsl-i2c";
336 reg = <0x119000 0x100>; 454 reg = <0x119000 0x100>;
337 interrupts = <39 2>; 455 interrupts = <39 2 0 0>;
338 interrupt-parent = <&mpic>;
339 dfsrr; 456 dfsrr;
340 }; 457 };
341 458
@@ -345,8 +462,7 @@
345 cell-index = <3>; 462 cell-index = <3>;
346 compatible = "fsl-i2c"; 463 compatible = "fsl-i2c";
347 reg = <0x119100 0x100>; 464 reg = <0x119100 0x100>;
348 interrupts = <39 2>; 465 interrupts = <39 2 0 0>;
349 interrupt-parent = <&mpic>;
350 dfsrr; 466 dfsrr;
351 }; 467 };
352 468
@@ -356,8 +472,7 @@
356 compatible = "ns16550"; 472 compatible = "ns16550";
357 reg = <0x11c500 0x100>; 473 reg = <0x11c500 0x100>;
358 clock-frequency = <0>; 474 clock-frequency = <0>;
359 interrupts = <36 2>; 475 interrupts = <36 2 0 0>;
360 interrupt-parent = <&mpic>;
361 }; 476 };
362 477
363 serial1: serial@11c600 { 478 serial1: serial@11c600 {
@@ -366,8 +481,7 @@
366 compatible = "ns16550"; 481 compatible = "ns16550";
367 reg = <0x11c600 0x100>; 482 reg = <0x11c600 0x100>;
368 clock-frequency = <0>; 483 clock-frequency = <0>;
369 interrupts = <36 2>; 484 interrupts = <36 2 0 0>;
370 interrupt-parent = <&mpic>;
371 }; 485 };
372 486
373 serial2: serial@11d500 { 487 serial2: serial@11d500 {
@@ -376,8 +490,7 @@
376 compatible = "ns16550"; 490 compatible = "ns16550";
377 reg = <0x11d500 0x100>; 491 reg = <0x11d500 0x100>;
378 clock-frequency = <0>; 492 clock-frequency = <0>;
379 interrupts = <37 2>; 493 interrupts = <37 2 0 0>;
380 interrupt-parent = <&mpic>;
381 }; 494 };
382 495
383 serial3: serial@11d600 { 496 serial3: serial@11d600 {
@@ -386,15 +499,13 @@
386 compatible = "ns16550"; 499 compatible = "ns16550";
387 reg = <0x11d600 0x100>; 500 reg = <0x11d600 0x100>;
388 clock-frequency = <0>; 501 clock-frequency = <0>;
389 interrupts = <37 2>; 502 interrupts = <37 2 0 0>;
390 interrupt-parent = <&mpic>;
391 }; 503 };
392 504
393 gpio0: gpio@130000 { 505 gpio0: gpio@130000 {
394 compatible = "fsl,p4080-gpio"; 506 compatible = "fsl,p4080-gpio", "fsl,qoriq-gpio";
395 reg = <0x130000 0x1000>; 507 reg = <0x130000 0x1000>;
396 interrupts = <55 2>; 508 interrupts = <55 2 0 0>;
397 interrupt-parent = <&mpic>;
398 #gpio-cells = <2>; 509 #gpio-cells = <2>;
399 gpio-controller; 510 gpio-controller;
400 }; 511 };
@@ -405,8 +516,7 @@
405 reg = <0x210000 0x1000>; 516 reg = <0x210000 0x1000>;
406 #address-cells = <1>; 517 #address-cells = <1>;
407 #size-cells = <0>; 518 #size-cells = <0>;
408 interrupt-parent = <&mpic>; 519 interrupts = <44 0x2 0 0>;
409 interrupts = <44 0x2>;
410 phy_type = "ulpi"; 520 phy_type = "ulpi";
411 }; 521 };
412 522
@@ -416,8 +526,7 @@
416 reg = <0x211000 0x1000>; 526 reg = <0x211000 0x1000>;
417 #address-cells = <1>; 527 #address-cells = <1>;
418 #size-cells = <0>; 528 #size-cells = <0>;
419 interrupt-parent = <&mpic>; 529 interrupts = <45 0x2 0 0>;
420 interrupts = <45 0x2>;
421 dr_mode = "host"; 530 dr_mode = "host";
422 phy_type = "ulpi"; 531 phy_type = "ulpi";
423 }; 532 };
@@ -429,34 +538,34 @@
429 reg = <0x300000 0x10000>; 538 reg = <0x300000 0x10000>;
430 ranges = <0 0x300000 0x10000>; 539 ranges = <0 0x300000 0x10000>;
431 interrupt-parent = <&mpic>; 540 interrupt-parent = <&mpic>;
432 interrupts = <92 2>; 541 interrupts = <92 2 0 0>;
433 542
434 sec_jr0: jr@1000 { 543 sec_jr0: jr@1000 {
435 compatible = "fsl,sec-v4.0-job-ring"; 544 compatible = "fsl,sec-v4.0-job-ring";
436 reg = <0x1000 0x1000>; 545 reg = <0x1000 0x1000>;
437 interrupt-parent = <&mpic>; 546 interrupt-parent = <&mpic>;
438 interrupts = <88 2>; 547 interrupts = <88 2 0 0>;
439 }; 548 };
440 549
441 sec_jr1: jr@2000 { 550 sec_jr1: jr@2000 {
442 compatible = "fsl,sec-v4.0-job-ring"; 551 compatible = "fsl,sec-v4.0-job-ring";
443 reg = <0x2000 0x1000>; 552 reg = <0x2000 0x1000>;
444 interrupt-parent = <&mpic>; 553 interrupt-parent = <&mpic>;
445 interrupts = <89 2>; 554 interrupts = <89 2 0 0>;
446 }; 555 };
447 556
448 sec_jr2: jr@3000 { 557 sec_jr2: jr@3000 {
449 compatible = "fsl,sec-v4.0-job-ring"; 558 compatible = "fsl,sec-v4.0-job-ring";
450 reg = <0x3000 0x1000>; 559 reg = <0x3000 0x1000>;
451 interrupt-parent = <&mpic>; 560 interrupt-parent = <&mpic>;
452 interrupts = <90 2>; 561 interrupts = <90 2 0 0>;
453 }; 562 };
454 563
455 sec_jr3: jr@4000 { 564 sec_jr3: jr@4000 {
456 compatible = "fsl,sec-v4.0-job-ring"; 565 compatible = "fsl,sec-v4.0-job-ring";
457 reg = <0x4000 0x1000>; 566 reg = <0x4000 0x1000>;
458 interrupt-parent = <&mpic>; 567 interrupt-parent = <&mpic>;
459 interrupts = <91 2>; 568 interrupts = <91 2 0 0>;
460 }; 569 };
461 570
462 rtic@6000 { 571 rtic@6000 {
@@ -492,7 +601,7 @@
492 compatible = "fsl,sec-v4.0-mon"; 601 compatible = "fsl,sec-v4.0-mon";
493 reg = <0x314000 0x1000>; 602 reg = <0x314000 0x1000>;
494 interrupt-parent = <&mpic>; 603 interrupt-parent = <&mpic>;
495 interrupts = <93 2>; 604 interrupts = <93 2 0 0>;
496 }; 605 };
497 }; 606 };
498 607
@@ -501,17 +610,21 @@
501 #size-cells = <2>; 610 #size-cells = <2>;
502 compatible = "fsl,rapidio-delta"; 611 compatible = "fsl,rapidio-delta";
503 reg = <0xf 0xfe0c0000 0 0x20000>; 612 reg = <0xf 0xfe0c0000 0 0x20000>;
504 ranges = <0 0 0xf 0xf5000000 0 0x01000000>; 613 ranges = <0 0 0xc 0x20000000 0 0x01000000>;
505 interrupt-parent = <&mpic>; 614 interrupts = <
506 /* err_irq bell_outb_irq bell_inb_irq 615 16 2 1 11 /* err_irq */
507 msg1_tx_irq msg1_rx_irq msg2_tx_irq msg2_rx_irq */ 616 56 2 0 0 /* bell_outb_irq */
508 interrupts = <16 2 56 2 57 2 60 2 61 2 62 2 63 2>; 617 57 2 0 0 /* bell_inb_irq */
618 60 2 0 0 /* msg1_tx_irq */
619 61 2 0 0 /* msg1_rx_irq */
620 62 2 0 0 /* msg2_tx_irq */
621 63 2 0 0>; /* msg2_rx_irq */
509 }; 622 };
510 623
511 localbus@ffe124000 { 624 localbus@ffe124000 {
512 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus"; 625 compatible = "fsl,p4080-elbc", "fsl,elbc", "simple-bus";
513 reg = <0xf 0xfe124000 0 0x1000>; 626 reg = <0xf 0xfe124000 0 0x1000>;
514 interrupts = <25 2>; 627 interrupts = <25 2 0 0>;
515 #address-cells = <2>; 628 #address-cells = <2>;
516 #size-cells = <1>; 629 #size-cells = <1>;
517 630
@@ -528,7 +641,6 @@
528 pci0: pcie@ffe200000 { 641 pci0: pcie@ffe200000 {
529 compatible = "fsl,p4080-pcie"; 642 compatible = "fsl,p4080-pcie";
530 device_type = "pci"; 643 device_type = "pci";
531 #interrupt-cells = <1>;
532 #size-cells = <2>; 644 #size-cells = <2>;
533 #address-cells = <3>; 645 #address-cells = <3>;
534 reg = <0xf 0xfe200000 0 0x1000>; 646 reg = <0xf 0xfe200000 0 0x1000>;
@@ -536,22 +648,23 @@
536 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 648 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
537 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; 649 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
538 clock-frequency = <0x1fca055>; 650 clock-frequency = <0x1fca055>;
539 interrupt-parent = <&mpic>; 651 fsl,msi = <&msi0>;
540 interrupts = <16 2>; 652 interrupts = <16 2 1 15>;
541
542 interrupt-map-mask = <0xf800 0 0 7>;
543 interrupt-map = <
544 /* IDSEL 0x0 */
545 0000 0 0 1 &mpic 40 1
546 0000 0 0 2 &mpic 1 1
547 0000 0 0 3 &mpic 2 1
548 0000 0 0 4 &mpic 3 1
549 >;
550 pcie@0 { 653 pcie@0 {
551 reg = <0 0 0 0 0>; 654 reg = <0 0 0 0 0>;
655 #interrupt-cells = <1>;
552 #size-cells = <2>; 656 #size-cells = <2>;
553 #address-cells = <3>; 657 #address-cells = <3>;
554 device_type = "pci"; 658 device_type = "pci";
659 interrupts = <16 2 1 15>;
660 interrupt-map-mask = <0xf800 0 0 7>;
661 interrupt-map = <
662 /* IDSEL 0x0 */
663 0000 0 0 1 &mpic 40 1 0 0
664 0000 0 0 2 &mpic 1 1 0 0
665 0000 0 0 3 &mpic 2 1 0 0
666 0000 0 0 4 &mpic 3 1 0 0
667 >;
555 ranges = <0x02000000 0 0xe0000000 668 ranges = <0x02000000 0 0xe0000000
556 0x02000000 0 0xe0000000 669 0x02000000 0 0xe0000000
557 0 0x20000000 670 0 0x20000000
@@ -565,7 +678,6 @@
565 pci1: pcie@ffe201000 { 678 pci1: pcie@ffe201000 {
566 compatible = "fsl,p4080-pcie"; 679 compatible = "fsl,p4080-pcie";
567 device_type = "pci"; 680 device_type = "pci";
568 #interrupt-cells = <1>;
569 #size-cells = <2>; 681 #size-cells = <2>;
570 #address-cells = <3>; 682 #address-cells = <3>;
571 reg = <0xf 0xfe201000 0 0x1000>; 683 reg = <0xf 0xfe201000 0 0x1000>;
@@ -573,21 +685,23 @@
573 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 685 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
574 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; 686 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
575 clock-frequency = <0x1fca055>; 687 clock-frequency = <0x1fca055>;
576 interrupt-parent = <&mpic>; 688 fsl,msi = <&msi1>;
577 interrupts = <16 2>; 689 interrupts = <16 2 1 14>;
578 interrupt-map-mask = <0xf800 0 0 7>;
579 interrupt-map = <
580 /* IDSEL 0x0 */
581 0000 0 0 1 &mpic 41 1
582 0000 0 0 2 &mpic 5 1
583 0000 0 0 3 &mpic 6 1
584 0000 0 0 4 &mpic 7 1
585 >;
586 pcie@0 { 690 pcie@0 {
587 reg = <0 0 0 0 0>; 691 reg = <0 0 0 0 0>;
692 #interrupt-cells = <1>;
588 #size-cells = <2>; 693 #size-cells = <2>;
589 #address-cells = <3>; 694 #address-cells = <3>;
590 device_type = "pci"; 695 device_type = "pci";
696 interrupts = <16 2 1 14>;
697 interrupt-map-mask = <0xf800 0 0 7>;
698 interrupt-map = <
699 /* IDSEL 0x0 */
700 0000 0 0 1 &mpic 41 1 0 0
701 0000 0 0 2 &mpic 5 1 0 0
702 0000 0 0 3 &mpic 6 1 0 0
703 0000 0 0 4 &mpic 7 1 0 0
704 >;
591 ranges = <0x02000000 0 0xe0000000 705 ranges = <0x02000000 0 0xe0000000
592 0x02000000 0 0xe0000000 706 0x02000000 0 0xe0000000
593 0 0x20000000 707 0 0x20000000
@@ -601,7 +715,6 @@
601 pci2: pcie@ffe202000 { 715 pci2: pcie@ffe202000 {
602 compatible = "fsl,p4080-pcie"; 716 compatible = "fsl,p4080-pcie";
603 device_type = "pci"; 717 device_type = "pci";
604 #interrupt-cells = <1>;
605 #size-cells = <2>; 718 #size-cells = <2>;
606 #address-cells = <3>; 719 #address-cells = <3>;
607 reg = <0xf 0xfe202000 0 0x1000>; 720 reg = <0xf 0xfe202000 0 0x1000>;
@@ -609,21 +722,23 @@
609 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 722 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
610 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; 723 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
611 clock-frequency = <0x1fca055>; 724 clock-frequency = <0x1fca055>;
612 interrupt-parent = <&mpic>; 725 fsl,msi = <&msi2>;
613 interrupts = <16 2>; 726 interrupts = <16 2 1 13>;
614 interrupt-map-mask = <0xf800 0 0 7>;
615 interrupt-map = <
616 /* IDSEL 0x0 */
617 0000 0 0 1 &mpic 42 1
618 0000 0 0 2 &mpic 9 1
619 0000 0 0 3 &mpic 10 1
620 0000 0 0 4 &mpic 11 1
621 >;
622 pcie@0 { 727 pcie@0 {
623 reg = <0 0 0 0 0>; 728 reg = <0 0 0 0 0>;
729 #interrupt-cells = <1>;
624 #size-cells = <2>; 730 #size-cells = <2>;
625 #address-cells = <3>; 731 #address-cells = <3>;
626 device_type = "pci"; 732 device_type = "pci";
733 interrupts = <16 2 1 13>;
734 interrupt-map-mask = <0xf800 0 0 7>;
735 interrupt-map = <
736 /* IDSEL 0x0 */
737 0000 0 0 1 &mpic 42 1 0 0
738 0000 0 0 2 &mpic 9 1 0 0
739 0000 0 0 3 &mpic 10 1 0 0
740 0000 0 0 4 &mpic 11 1 0 0
741 >;
627 ranges = <0x02000000 0 0xe0000000 742 ranges = <0x02000000 0 0xe0000000
628 0x02000000 0 0xe0000000 743 0x02000000 0 0xe0000000
629 0 0x20000000 744 0 0x20000000
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 15:00:39 -0500