aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorVitaly Bordug <vbordug@ru.mvista.com>2007-01-24 14:41:42 -0500
committerPaul Mackerras <paulus@samba.org>2007-02-06 22:03:17 -0500
commitdf34403dcaacef541a67c955aebc37c51f53ca7c (patch)
tree9d4159a85569a457a57f1ac352c373dd7d7a82ba
parentf2a0bd3753dad7ea4605ebd5435716b39e9f92bb (diff)
[POWERPC] 8xx: Add mpc885ads support and common mpc8xx files
This adds the core 8xx stuff and specifically mpc885ads board-specific bits to arch/powerpc. Respective Kconfig has been cleaned up from the stuff not yet ported over to avoid confusion. Updated and cleaned version. Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com> Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat
-rw-r--r--arch/powerpc/boot/dts/mpc885ads.dts185
-rw-r--r--arch/powerpc/configs/mpc885_ads_defconfig827
-rw-r--r--arch/powerpc/platforms/8xx/Kconfig300
-rw-r--r--arch/powerpc/platforms/8xx/Makefile5
-rw-r--r--arch/powerpc/platforms/8xx/m8xx_setup.c303
-rw-r--r--arch/powerpc/platforms/8xx/mpc885ads.h95
-rw-r--r--arch/powerpc/platforms/8xx/mpc885ads_setup.c387
-rw-r--r--arch/powerpc/platforms/Makefile1
8 files changed, 1846 insertions, 257 deletions
diff --git a/arch/powerpc/boot/dts/mpc885ads.dts b/arch/powerpc/boot/dts/mpc885ads.dts
new file mode 100644
index 000000000000..cf1a19f962c5
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc885ads.dts
@@ -0,0 +1,185 @@
1/*
2 * MPC885 ADS Device Tree Source
3 *
4 * Copyright 2006 MontaVista Software, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12
13/ {
14 model = "MPC885ADS";
15 compatible = "mpc8xx";
16 #address-cells = <1>;
17 #size-cells = <1>;
18 linux,phandle = <100>;
19
20 cpus {
21 #cpus = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 linux,phandle = <200>;
25
26 PowerPC,885@0 {
27 device_type = "cpu";
28 reg = <0>;
29 d-cache-line-size = <20>; // 32 bytes
30 i-cache-line-size = <20>; // 32 bytes
31 d-cache-size = <2000>; // L1, 8K
32 i-cache-size = <2000>; // L1, 8K
33 timebase-frequency = <0>;
34 bus-frequency = <0>;
35 clock-frequency = <0>;
36 32-bit;
37 interrupts = <f 2>; // decrementer interrupt
38 interrupt-parent = <ff000000>;
39 linux,phandle = <201>;
40 linux,boot-cpu;
41 };
42 };
43
44 memory {
45 device_type = "memory";
46 linux,phandle = <300>;
47 reg = <00000000 800000>;
48 };
49
50 soc885@ff000000 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 #interrupt-cells = <2>;
54 device_type = "soc";
55 ranges = <0 ff000000 00100000>;
56 reg = <ff000000 00000200>;
57 bus-frequency = <0>;
58 mdio@e80 {
59 device_type = "mdio";
60 compatible = "fs_enet";
61 reg = <e80 8>;
62 linux,phandle = <e80>;
63 #address-cells = <1>;
64 #size-cells = <0>;
65 ethernet-phy@0 {
66 linux,phandle = <e8000>;
67 reg = <0>;
68 device_type = "ethernet-phy";
69 };
70 ethernet-phy@1 {
71 linux,phandle = <e8001>;
72 reg = <1>;
73 device_type = "ethernet-phy";
74 };
75 ethernet-phy@2 {
76 linux,phandle = <e8002>;
77 reg = <2>;
78 device_type = "ethernet-phy";
79 };
80 };
81
82 fec@e00 {
83 device_type = "network";
84 compatible = "fs_enet";
85 model = "FEC";
86 device-id = <1>;
87 reg = <e00 188>;
88 mac-address = [ 00 00 0C 00 01 FD ];
89 interrupts = <3 1>;
90 interrupt-parent = <ff000000>;
91 phy-handle = <e8000>;
92 };
93
94 fec@1e00 {
95 device_type = "network";
96 compatible = "fs_enet";
97 model = "FEC";
98 device-id = <2>;
99 reg = <1e00 188>;
100 mac-address = [ 00 00 0C 00 02 FD ];
101 interrupts = <7 1>;
102 interrupt-parent = <ff000000>;
103 phy-handle = <e8001>;
104 };
105
106 pic@ff000000 {
107 linux,phandle = <ff000000>;
108 interrupt-controller;
109 #address-cells = <0>;
110 #interrupt-cells = <2>;
111 reg = <0 24>;
112 built-in;
113 device_type = "mpc8xx-pic";
114 compatible = "CPM";
115 };
116
117 cpm@ff000000 {
118 linux,phandle = <ff000000>;
119 #address-cells = <1>;
120 #size-cells = <1>;
121 #interrupt-cells = <2>;
122 device_type = "cpm";
123 model = "CPM";
124 ranges = <0 0 4000>;
125 reg = <860 f0>;
126 command-proc = <9c0>;
127 brg-frequency = <0>;
128 interrupts = <0 2>; // cpm error interrupt
129 interrupt-parent = <930>;
130
131 pic@930 {
132 linux,phandle = <930>;
133 interrupt-controller;
134 #address-cells = <0>;
135 #interrupt-cells = <2>;
136 interrupts = <5 2 0 2>;
137 interrupt-parent = <ff000000>;
138 reg = <930 20>;
139 built-in;
140 device_type = "cpm-pic";
141 compatible = "CPM";
142 };
143
144 smc@a80 {
145 device_type = "serial";
146 compatible = "cpm_uart";
147 model = "SMC";
148 device-id = <1>;
149 reg = <a80 10 3e80 40>;
150 clock-setup = <00ffffff 0>;
151 rx-clock = <1>;
152 tx-clock = <1>;
153 current-speed = <0>;
154 interrupts = <4 3>;
155 interrupt-parent = <930>;
156 };
157
158 smc@a90 {
159 device_type = "serial";
160 compatible = "cpm_uart";
161 model = "SMC";
162 device-id = <2>;
163 reg = <a90 20 3f80 40>;
164 clock-setup = <ff00ffff 90000>;
165 rx-clock = <2>;
166 tx-clock = <2>;
167 current-speed = <0>;
168 interrupts = <3 3>;
169 interrupt-parent = <930>;
170 };
171
172 scc@a40 {
173 device_type = "network";
174 compatible = "fs_enet";
175 model = "SCC";
176 device-id = <3>;
177 reg = <a40 18 3e00 80>;
178 mac-address = [ 00 00 0C 00 03 FD ];
179 interrupts = <1c 3>;
180 interrupt-parent = <930>;
181 phy-handle = <e8002>;
182 };
183 };
184 };
185};
diff --git a/arch/powerpc/configs/mpc885_ads_defconfig b/arch/powerpc/configs/mpc885_ads_defconfig
new file mode 100644
index 000000000000..e2c17d8da4fc
--- /dev/null
+++ b/arch/powerpc/configs/mpc885_ads_defconfig
@@ -0,0 +1,827 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.19-rc4
4# Fri Nov 10 21:30:40 2006
5#
6# CONFIG_PPC64 is not set
7CONFIG_PPC32=y
8CONFIG_PPC_MERGE=y
9CONFIG_MMU=y
10CONFIG_GENERIC_HARDIRQS=y
11CONFIG_IRQ_PER_CPU=y
12CONFIG_RWSEM_XCHGADD_ALGORITHM=y
13CONFIG_GENERIC_HWEIGHT=y
14CONFIG_GENERIC_CALIBRATE_DELAY=y
15CONFIG_GENERIC_FIND_NEXT_BIT=y
16CONFIG_PPC=y
17CONFIG_EARLY_PRINTK=y
18CONFIG_GENERIC_NVRAM=y
19CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
20CONFIG_ARCH_MAY_HAVE_PC_FDC=y
21CONFIG_PPC_OF=y
22# CONFIG_PPC_UDBG_16550 is not set
23# CONFIG_GENERIC_TBSYNC is not set
24CONFIG_AUDIT_ARCH=y
25# CONFIG_DEFAULT_UIMAGE is not set
26
27#
28# Processor support
29#
30# CONFIG_CLASSIC32 is not set
31# CONFIG_PPC_52xx is not set
32# CONFIG_PPC_82xx is not set
33# CONFIG_PPC_83xx is not set
34# CONFIG_PPC_85xx is not set
35# CONFIG_PPC_86xx is not set
36CONFIG_PPC_8xx=y
37# CONFIG_40x is not set
38# CONFIG_44x is not set
39# CONFIG_E200 is not set
40CONFIG_8xx=y
41CONFIG_NOT_COHERENT_CACHE=y
42CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
43
44#
45# Code maturity level options
46#
47CONFIG_EXPERIMENTAL=y
48CONFIG_BROKEN_ON_SMP=y
49CONFIG_INIT_ENV_ARG_LIMIT=32
50
51#
52# General setup
53#
54CONFIG_LOCALVERSION=""
55CONFIG_LOCALVERSION_AUTO=y
56# CONFIG_SWAP is not set
57CONFIG_SYSVIPC=y
58# CONFIG_IPC_NS is not set
59# CONFIG_POSIX_MQUEUE is not set
60# CONFIG_BSD_PROCESS_ACCT is not set
61# CONFIG_TASKSTATS is not set
62# CONFIG_UTS_NS is not set
63# CONFIG_AUDIT is not set
64# CONFIG_IKCONFIG is not set
65# CONFIG_RELAY is not set
66CONFIG_INITRAMFS_SOURCE=""
67# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
68CONFIG_SYSCTL=y
69CONFIG_EMBEDDED=y
70# CONFIG_SYSCTL_SYSCALL is not set
71CONFIG_KALLSYMS=y
72# CONFIG_KALLSYMS_EXTRA_PASS is not set
73# CONFIG_HOTPLUG is not set
74CONFIG_PRINTK=y
75# CONFIG_BUG is not set
76CONFIG_ELF_CORE=y
77# CONFIG_BASE_FULL is not set
78CONFIG_FUTEX=y
79# CONFIG_EPOLL is not set
80CONFIG_SHMEM=y
81CONFIG_SLAB=y
82# CONFIG_VM_EVENT_COUNTERS is not set
83CONFIG_RT_MUTEXES=y
84# CONFIG_TINY_SHMEM is not set
85CONFIG_BASE_SMALL=1
86# CONFIG_SLOB is not set
87
88#
89# Loadable module support
90#
91# CONFIG_MODULES is not set
92
93#
94# Block layer
95#
96CONFIG_BLOCK=y
97# CONFIG_LBD is not set
98# CONFIG_BLK_DEV_IO_TRACE is not set
99# CONFIG_LSF is not set
100
101#
102# IO Schedulers
103#
104CONFIG_IOSCHED_NOOP=y
105CONFIG_IOSCHED_AS=y
106CONFIG_IOSCHED_DEADLINE=y
107CONFIG_IOSCHED_CFQ=y
108CONFIG_DEFAULT_AS=y
109# CONFIG_DEFAULT_DEADLINE is not set
110# CONFIG_DEFAULT_CFQ is not set
111# CONFIG_DEFAULT_NOOP is not set
112CONFIG_DEFAULT_IOSCHED="anticipatory"
113# CONFIG_WANT_EARLY_SERIAL is not set
114CONFIG_EMBEDDEDBOOT=y
115# CONFIG_MPIC is not set
116
117#
118# Platform support
119#
120CONFIG_CPM1=y
121# CONFIG_MPC8XXFADS is not set
122# CONFIG_MPC86XADS is not set
123CONFIG_MPC885ADS=y
124
125#
126# MPC8xx CPM Options
127#
128
129#
130# Generic MPC8xx Options
131#
132CONFIG_8xx_COPYBACK=y
133# CONFIG_8xx_CPU6 is not set
134CONFIG_NO_UCODE_PATCH=y
135# CONFIG_USB_SOF_UCODE_PATCH is not set
136# CONFIG_I2C_SPI_UCODE_PATCH is not set
137# CONFIG_I2C_SPI_SMC1_UCODE_PATCH is not set
138
139#
140# Kernel options
141#
142# CONFIG_HIGHMEM is not set
143# CONFIG_HZ_100 is not set
144# CONFIG_HZ_250 is not set
145CONFIG_HZ_1000=y
146CONFIG_HZ=1000
147CONFIG_PREEMPT_NONE=y
148# CONFIG_PREEMPT_VOLUNTARY is not set
149# CONFIG_PREEMPT is not set
150CONFIG_BINFMT_ELF=y
151# CONFIG_BINFMT_MISC is not set
152CONFIG_MATH_EMULATION=y
153CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
154CONFIG_ARCH_FLATMEM_ENABLE=y
155CONFIG_ARCH_POPULATES_NODE_MAP=y
156CONFIG_SELECT_MEMORY_MODEL=y
157CONFIG_FLATMEM_MANUAL=y
158# CONFIG_DISCONTIGMEM_MANUAL is not set
159# CONFIG_SPARSEMEM_MANUAL is not set
160CONFIG_FLATMEM=y
161CONFIG_FLAT_NODE_MEM_MAP=y
162# CONFIG_SPARSEMEM_STATIC is not set
163CONFIG_SPLIT_PTLOCK_CPUS=4
164# CONFIG_RESOURCES_64BIT is not set
165# CONFIG_PROC_DEVICETREE is not set
166# CONFIG_CMDLINE_BOOL is not set
167# CONFIG_PM is not set
168# CONFIG_SECCOMP is not set
169CONFIG_ISA_DMA_API=y
170
171#
172# Bus options
173#
174# CONFIG_MPIC_WEIRD is not set
175# CONFIG_PPC_I8259 is not set
176CONFIG_FSL_SOC=y
177# CONFIG_PCI is not set
178# CONFIG_PCI_DOMAINS is not set
179# CONFIG_PCI_QSPAN is not set
180
181#
182# PCCARD (PCMCIA/CardBus) support
183#
184
185#
186# PCI Hotplug Support
187#
188
189#
190# Advanced setup
191#
192# CONFIG_ADVANCED_OPTIONS is not set
193
194#
195# Default settings for advanced configuration options are used
196#
197CONFIG_HIGHMEM_START=0xfe000000
198CONFIG_LOWMEM_SIZE=0x30000000
199CONFIG_KERNEL_START=0xc0000000
200CONFIG_TASK_SIZE=0x80000000
201CONFIG_CONSISTENT_START=0xff100000
202CONFIG_CONSISTENT_SIZE=0x00200000
203CONFIG_BOOT_LOAD=0x00400000
204
205#
206# Networking
207#
208CONFIG_NET=y
209
210#
211# Networking options
212#
213# CONFIG_NETDEBUG is not set
214CONFIG_PACKET=y
215# CONFIG_PACKET_MMAP is not set
216CONFIG_UNIX=y
217CONFIG_XFRM=y
218# CONFIG_XFRM_USER is not set
219# CONFIG_XFRM_SUB_POLICY is not set
220# CONFIG_NET_KEY is not set
221CONFIG_INET=y
222CONFIG_IP_MULTICAST=y
223# CONFIG_IP_ADVANCED_ROUTER is not set
224CONFIG_IP_FIB_HASH=y
225CONFIG_IP_PNP=y
226# CONFIG_IP_PNP_DHCP is not set
227# CONFIG_IP_PNP_BOOTP is not set
228# CONFIG_IP_PNP_RARP is not set
229# CONFIG_NET_IPIP is not set
230# CONFIG_NET_IPGRE is not set
231# CONFIG_IP_MROUTE is not set
232# CONFIG_ARPD is not set
233CONFIG_SYN_COOKIES=y
234# CONFIG_INET_AH is not set
235# CONFIG_INET_ESP is not set
236# CONFIG_INET_IPCOMP is not set
237# CONFIG_INET_XFRM_TUNNEL is not set
238# CONFIG_INET_TUNNEL is not set
239CONFIG_INET_XFRM_MODE_TRANSPORT=y
240CONFIG_INET_XFRM_MODE_TUNNEL=y
241CONFIG_INET_XFRM_MODE_BEET=y
242CONFIG_INET_DIAG=y
243CONFIG_INET_TCP_DIAG=y
244# CONFIG_TCP_CONG_ADVANCED is not set
245CONFIG_TCP_CONG_CUBIC=y
246CONFIG_DEFAULT_TCP_CONG="cubic"
247# CONFIG_IPV6 is not set
248# CONFIG_INET6_XFRM_TUNNEL is not set
249# CONFIG_INET6_TUNNEL is not set
250# CONFIG_NETWORK_SECMARK is not set
251# CONFIG_NETFILTER is not set
252
253#
254# DCCP Configuration (EXPERIMENTAL)
255#
256# CONFIG_IP_DCCP is not set
257
258#
259# SCTP Configuration (EXPERIMENTAL)
260#
261# CONFIG_IP_SCTP is not set
262
263#
264# TIPC Configuration (EXPERIMENTAL)
265#
266# CONFIG_TIPC is not set
267# CONFIG_ATM is not set
268# CONFIG_BRIDGE is not set
269# CONFIG_VLAN_8021Q is not set
270# CONFIG_DECNET is not set
271# CONFIG_LLC2 is not set
272# CONFIG_IPX is not set
273# CONFIG_ATALK is not set
274# CONFIG_X25 is not set
275# CONFIG_LAPB is not set
276# CONFIG_ECONET is not set
277# CONFIG_WAN_ROUTER is not set
278
279#
280# QoS and/or fair queueing
281#
282# CONFIG_NET_SCHED is not set
283
284#
285# Network testing
286#
287# CONFIG_NET_PKTGEN is not set
288# CONFIG_HAMRADIO is not set
289# CONFIG_IRDA is not set
290# CONFIG_BT is not set
291# CONFIG_IEEE80211 is not set
292
293#
294# Device Drivers
295#
296
297#
298# Generic Driver Options
299#
300CONFIG_STANDALONE=y
301CONFIG_PREVENT_FIRMWARE_BUILD=y
302# CONFIG_SYS_HYPERVISOR is not set
303
304#
305# Connector - unified userspace <-> kernelspace linker
306#
307# CONFIG_CONNECTOR is not set
308
309#
310# Memory Technology Devices (MTD)
311#
312# CONFIG_MTD is not set
313
314#
315# Parallel port support
316#
317# CONFIG_PARPORT is not set
318
319#
320# Plug and Play support
321#
322
323#
324# Block devices
325#
326# CONFIG_BLK_DEV_FD is not set
327# CONFIG_BLK_DEV_COW_COMMON is not set
328CONFIG_BLK_DEV_LOOP=y
329# CONFIG_BLK_DEV_CRYPTOLOOP is not set
330# CONFIG_BLK_DEV_NBD is not set
331# CONFIG_BLK_DEV_RAM is not set
332# CONFIG_BLK_DEV_INITRD is not set
333# CONFIG_CDROM_PKTCDVD is not set
334# CONFIG_ATA_OVER_ETH is not set
335
336#
337# Misc devices
338#
339# CONFIG_TIFM_CORE is not set
340
341#
342# ATA/ATAPI/MFM/RLL support
343#
344# CONFIG_IDE is not set
345
346#
347# SCSI device support
348#
349# CONFIG_RAID_ATTRS is not set
350# CONFIG_SCSI is not set
351# CONFIG_SCSI_NETLINK is not set
352
353#
354# Serial ATA (prod) and Parallel ATA (experimental) drivers
355#
356# CONFIG_ATA is not set
357
358#
359# Multi-device support (RAID and LVM)
360#
361# CONFIG_MD is not set
362
363#
364# Fusion MPT device support
365#
366# CONFIG_FUSION is not set
367
368#
369# IEEE 1394 (FireWire) support
370#
371
372#
373# I2O device support
374#
375
376#
377# Macintosh device drivers
378#
379# CONFIG_WINDFARM is not set
380
381#
382# Network device support
383#
384CONFIG_NETDEVICES=y
385# CONFIG_DUMMY is not set
386# CONFIG_BONDING is not set
387# CONFIG_EQUALIZER is not set
388# CONFIG_TUN is not set
389
390#
391# PHY device support
392#
393CONFIG_PHYLIB=y
394
395#
396# MII PHY device drivers
397#
398# CONFIG_MARVELL_PHY is not set
399CONFIG_DAVICOM_PHY=y
400# CONFIG_QSEMI_PHY is not set
401# CONFIG_LXT_PHY is not set
402# CONFIG_CICADA_PHY is not set
403# CONFIG_VITESSE_PHY is not set
404# CONFIG_SMSC_PHY is not set
405CONFIG_FIXED_PHY=y
406CONFIG_FIXED_MII_10_FDX=y
407# CONFIG_FIXED_MII_100_FDX is not set
408
409#
410# Ethernet (10 or 100Mbit)
411#
412CONFIG_NET_ETHERNET=y
413CONFIG_MII=y
414# CONFIG_FEC_8XX is not set
415CONFIG_FS_ENET=y
416CONFIG_FS_ENET_HAS_SCC=y
417CONFIG_FS_ENET_HAS_FEC=y
418
419#
420# Ethernet (1000 Mbit)
421#
422
423#
424# Ethernet (10000 Mbit)
425#
426
427#
428# Token Ring devices
429#
430
431#
432# Wireless LAN (non-hamradio)
433#
434# CONFIG_NET_RADIO is not set
435
436#
437# Wan interfaces
438#
439# CONFIG_WAN is not set
440# CONFIG_PPP is not set
441# CONFIG_SLIP is not set
442# CONFIG_SHAPER is not set
443# CONFIG_NETCONSOLE is not set
444# CONFIG_NETPOLL is not set
445# CONFIG_NET_POLL_CONTROLLER is not set
446
447#
448# ISDN subsystem
449#
450# CONFIG_ISDN is not set
451
452#
453# Telephony Support
454#
455# CONFIG_PHONE is not set
456
457#
458# Input device support
459#
460CONFIG_INPUT=y
461# CONFIG_INPUT_FF_MEMLESS is not set
462
463#
464# Userland interfaces
465#
466CONFIG_INPUT_MOUSEDEV=y
467CONFIG_INPUT_MOUSEDEV_PSAUX=y
468CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
469CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
470# CONFIG_INPUT_JOYDEV is not set
471# CONFIG_INPUT_TSDEV is not set
472# CONFIG_INPUT_EVDEV is not set
473# CONFIG_INPUT_EVBUG is not set
474
475#
476# Input Device Drivers
477#
478CONFIG_INPUT_KEYBOARD=y
479CONFIG_KEYBOARD_ATKBD=y
480# CONFIG_KEYBOARD_SUNKBD is not set
481# CONFIG_KEYBOARD_LKKBD is not set
482# CONFIG_KEYBOARD_XTKBD is not set
483# CONFIG_KEYBOARD_NEWTON is not set
484# CONFIG_KEYBOARD_STOWAWAY is not set
485CONFIG_INPUT_MOUSE=y
486CONFIG_MOUSE_PS2=y
487# CONFIG_MOUSE_SERIAL is not set
488# CONFIG_MOUSE_VSXXXAA is not set
489# CONFIG_INPUT_JOYSTICK is not set
490# CONFIG_INPUT_TOUCHSCREEN is not set
491# CONFIG_INPUT_MISC is not set
492
493#
494# Hardware I/O ports
495#
496CONFIG_SERIO=y
497CONFIG_SERIO_I8042=y
498CONFIG_SERIO_SERPORT=y
499CONFIG_SERIO_LIBPS2=y
500# CONFIG_SERIO_RAW is not set
501# CONFIG_GAMEPORT is not set
502
503#
504# Character devices
505#
506# CONFIG_VT is not set
507# CONFIG_SERIAL_NONSTANDARD is not set
508
509#
510# Serial drivers
511#
512# CONFIG_SERIAL_8250 is not set
513
514#
515# Non-8250 serial port support
516#
517CONFIG_SERIAL_CORE=y
518CONFIG_SERIAL_CORE_CONSOLE=y
519CONFIG_SERIAL_CPM=y
520CONFIG_SERIAL_CPM_CONSOLE=y
521# CONFIG_SERIAL_CPM_SCC1 is not set
522# CONFIG_SERIAL_CPM_SCC2 is not set
523# CONFIG_SERIAL_CPM_SCC3 is not set
524# CONFIG_SERIAL_CPM_SCC4 is not set
525CONFIG_SERIAL_CPM_SMC1=y
526CONFIG_SERIAL_CPM_SMC2=y
527CONFIG_UNIX98_PTYS=y
528# CONFIG_LEGACY_PTYS is not set
529
530#
531# IPMI
532#
533# CONFIG_IPMI_HANDLER is not set
534
535#
536# Watchdog Cards
537#
538# CONFIG_WATCHDOG is not set
539CONFIG_HW_RANDOM=y
540# CONFIG_NVRAM is not set
541CONFIG_GEN_RTC=y
542# CONFIG_GEN_RTC_X is not set
543# CONFIG_DTLK is not set
544# CONFIG_R3964 is not set
545
546#
547# Ftape, the floppy tape device driver
548#
549# CONFIG_RAW_DRIVER is not set
550
551#
552# TPM devices
553#
554# CONFIG_TCG_TPM is not set
555
556#
557# I2C support
558#
559# CONFIG_I2C is not set
560
561#
562# SPI support
563#
564# CONFIG_SPI is not set
565# CONFIG_SPI_MASTER is not set
566
567#
568# Dallas's 1-wire bus
569#
570# CONFIG_W1 is not set
571
572#
573# Hardware Monitoring support
574#
575CONFIG_HWMON=y
576# CONFIG_HWMON_VID is not set
577# CONFIG_SENSORS_ABITUGURU is not set
578# CONFIG_SENSORS_F71805F is not set
579# CONFIG_SENSORS_VT1211 is not set
580# CONFIG_HWMON_DEBUG_CHIP is not set
581
582#
583# Multimedia devices
584#
585# CONFIG_VIDEO_DEV is not set
586
587#
588# Digital Video Broadcasting Devices
589#
590# CONFIG_DVB is not set
591
592#
593# Graphics support
594#
595CONFIG_FIRMWARE_EDID=y
596# CONFIG_FB is not set
597# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
598
599#
600# Sound
601#
602# CONFIG_SOUND is not set
603
604#
605# USB support
606#
607# CONFIG_USB_ARCH_HAS_HCD is not set
608# CONFIG_USB_ARCH_HAS_OHCI is not set
609# CONFIG_USB_ARCH_HAS_EHCI is not set
610
611#
612# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
613#
614
615#
616# USB Gadget Support
617#
618# CONFIG_USB_GADGET is not set
619
620#
621# MMC/SD Card support
622#
623# CONFIG_MMC is not set
624
625#
626# LED devices
627#
628# CONFIG_NEW_LEDS is not set
629
630#
631# LED drivers
632#
633
634#
635# LED Triggers
636#
637
638#
639# InfiniBand support
640#
641
642#
643# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
644#
645
646#
647# Real Time Clock
648#
649# CONFIG_RTC_CLASS is not set
650
651#
652# DMA Engine support
653#
654# CONFIG_DMA_ENGINE is not set
655
656#
657# DMA Clients
658#
659
660#
661# DMA Devices
662#
663
664#
665# File systems
666#
667CONFIG_EXT2_FS=y
668CONFIG_EXT2_FS_XATTR=y
669# CONFIG_EXT2_FS_POSIX_ACL is not set
670# CONFIG_EXT2_FS_SECURITY is not set
671# CONFIG_EXT2_FS_XIP is not set
672CONFIG_EXT3_FS=y
673CONFIG_EXT3_FS_XATTR=y
674# CONFIG_EXT3_FS_POSIX_ACL is not set
675# CONFIG_EXT3_FS_SECURITY is not set
676# CONFIG_EXT4DEV_FS is not set
677CONFIG_JBD=y
678# CONFIG_JBD_DEBUG is not set
679CONFIG_FS_MBCACHE=y
680# CONFIG_REISERFS_FS is not set
681# CONFIG_JFS_FS is not set
682# CONFIG_FS_POSIX_ACL is not set
683# CONFIG_XFS_FS is not set
684# CONFIG_GFS2_FS is not set
685# CONFIG_OCFS2_FS is not set
686# CONFIG_MINIX_FS is not set
687# CONFIG_ROMFS_FS is not set
688CONFIG_INOTIFY=y
689CONFIG_INOTIFY_USER=y
690# CONFIG_QUOTA is not set
691CONFIG_DNOTIFY=y
692# CONFIG_AUTOFS_FS is not set
693# CONFIG_AUTOFS4_FS is not set
694# CONFIG_FUSE_FS is not set
695
696#
697# CD-ROM/DVD Filesystems
698#
699# CONFIG_ISO9660_FS is not set
700# CONFIG_UDF_FS is not set
701
702#
703# DOS/FAT/NT Filesystems
704#
705# CONFIG_MSDOS_FS is not set
706# CONFIG_VFAT_FS is not set
707# CONFIG_NTFS_FS is not set
708
709#
710# Pseudo filesystems
711#
712CONFIG_PROC_FS=y
713# CONFIG_PROC_KCORE is not set
714CONFIG_PROC_SYSCTL=y
715CONFIG_SYSFS=y
716CONFIG_TMPFS=y
717# CONFIG_TMPFS_POSIX_ACL is not set
718# CONFIG_HUGETLB_PAGE is not set
719CONFIG_RAMFS=y
720# CONFIG_CONFIGFS_FS is not set
721
722#
723# Miscellaneous filesystems
724#
725# CONFIG_ADFS_FS is not set
726# CONFIG_AFFS_FS is not set
727# CONFIG_HFS_FS is not set
728# CONFIG_HFSPLUS_FS is not set
729# CONFIG_BEFS_FS is not set
730# CONFIG_BFS_FS is not set
731# CONFIG_EFS_FS is not set
732CONFIG_CRAMFS=y
733# CONFIG_VXFS_FS is not set
734# CONFIG_HPFS_FS is not set
735# CONFIG_QNX4FS_FS is not set
736# CONFIG_SYSV_FS is not set
737# CONFIG_UFS_FS is not set
738
739#
740# Network File Systems
741#
742CONFIG_NFS_FS=y
743CONFIG_NFS_V3=y
744# CONFIG_NFS_V3_ACL is not set
745# CONFIG_NFS_V4 is not set
746# CONFIG_NFS_DIRECTIO is not set
747# CONFIG_NFSD is not set
748CONFIG_ROOT_NFS=y
749CONFIG_LOCKD=y
750CONFIG_LOCKD_V4=y
751CONFIG_NFS_COMMON=y
752CONFIG_SUNRPC=y
753# CONFIG_RPCSEC_GSS_KRB5 is not set
754# CONFIG_RPCSEC_GSS_SPKM3 is not set
755# CONFIG_SMB_FS is not set
756# CONFIG_CIFS is not set
757# CONFIG_NCP_FS is not set
758# CONFIG_CODA_FS is not set
759# CONFIG_AFS_FS is not set
760# CONFIG_9P_FS is not set
761
762#
763# Partition Types
764#
765CONFIG_PARTITION_ADVANCED=y
766# CONFIG_ACORN_PARTITION is not set
767# CONFIG_OSF_PARTITION is not set
768# CONFIG_AMIGA_PARTITION is not set
769# CONFIG_ATARI_PARTITION is not set
770# CONFIG_MAC_PARTITION is not set
771CONFIG_MSDOS_PARTITION=y
772# CONFIG_BSD_DISKLABEL is not set
773# CONFIG_MINIX_SUBPARTITION is not set
774# CONFIG_SOLARIS_X86_PARTITION is not set
775# CONFIG_UNIXWARE_DISKLABEL is not set
776# CONFIG_LDM_PARTITION is not set
777# CONFIG_SGI_PARTITION is not set
778# CONFIG_ULTRIX_PARTITION is not set
779# CONFIG_SUN_PARTITION is not set
780# CONFIG_KARMA_PARTITION is not set
781# CONFIG_EFI_PARTITION is not set
782
783#
784# Native Language Support
785#
786# CONFIG_NLS is not set
787
788#
789# Library routines
790#
791CONFIG_CRC_CCITT=y
792# CONFIG_CRC16 is not set
793CONFIG_CRC32=y
794# CONFIG_LIBCRC32C is not set
795CONFIG_ZLIB_INFLATE=y
796CONFIG_PLIST=y
797
798#
799# Instrumentation Support
800#
801# CONFIG_PROFILING is not set
802
803#
804# Kernel hacking
805#
806# CONFIG_PRINTK_TIME is not set
807CONFIG_ENABLE_MUST_CHECK=y
808# CONFIG_MAGIC_SYSRQ is not set
809# CONFIG_UNUSED_SYMBOLS is not set
810# CONFIG_DEBUG_KERNEL is not set
811CONFIG_LOG_BUF_SHIFT=14
812# CONFIG_DEBUG_FS is not set
813# CONFIG_UNWIND_INFO is not set
814# CONFIG_HEADERS_CHECK is not set
815# CONFIG_BOOTX_TEXT is not set
816# CONFIG_PPC_EARLY_DEBUG is not set
817
818#
819# Security options
820#
821# CONFIG_KEYS is not set
822# CONFIG_SECURITY is not set
823
824#
825# Cryptographic options
826#
827# CONFIG_CRYPTO is not set
diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig
index c8c0ba3cf8e8..beea6834bb7e 100644
--- a/arch/powerpc/platforms/8xx/Kconfig
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -1,105 +1,16 @@
1menu "Platform support"
2 depends on PPC_8xx
3
1config FADS 4config FADS
2 bool 5 bool
3 6
7config CPM1
8 bool
9
4choice 10choice
5 prompt "8xx Machine Type" 11 prompt "8xx Machine Type"
6 depends on 8xx 12 depends on 8xx
7 default RPXLITE 13 default MPC885ADS
8
9config RPXLITE
10 bool "RPX-Lite"
11 ---help---
12 Single-board computers based around the PowerPC MPC8xx chips and
13 intended for embedded applications. The following types are
14 supported:
15
16 RPX-Lite:
17 Embedded Planet RPX Lite. PC104 form-factor SBC based on the MPC823.
18
19 RPX-Classic:
20 Embedded Planet RPX Classic Low-fat. Credit-card-size SBC based on
21 the MPC 860
22
23 BSE-IP:
24 Bright Star Engineering ip-Engine.
25
26 TQM823L:
27 TQM850L:
28 TQM855L:
29 TQM860L:
30 MPC8xx based family of mini modules, half credit card size,
31 up to 64 MB of RAM, 8 MB Flash, (Fast) Ethernet, 2 x serial ports,
32 2 x CAN bus interface, ...
33 Manufacturer: TQ Components, www.tq-group.de
34 Date of Release: October (?) 1999
35 End of Life: not yet :-)
36 URL:
37 - module: <http://www.denx.de/PDF/TQM8xxLHWM201.pdf>
38 - starter kit: <http://www.denx.de/PDF/STK8xxLHWM201.pdf>
39 - images: <http://www.denx.de/embedded-ppc-en.html>
40
41 FPS850L:
42 FingerPrint Sensor System (based on TQM850L)
43 Manufacturer: IKENDI AG, <http://www.ikendi.com/>
44 Date of Release: November 1999
45 End of life: end 2000 ?
46 URL: see TQM850L
47
48 IVMS8:
49 MPC860 based board used in the "Integrated Voice Mail System",
50 Small Version (8 voice channels)
51 Manufacturer: Speech Design, <http://www.speech-design.de/>
52 Date of Release: December 2000 (?)
53 End of life: -
54 URL: <http://www.speech-design.de/>
55
56 IVML24:
57 MPC860 based board used in the "Integrated Voice Mail System",
58 Large Version (24 voice channels)
59 Manufacturer: Speech Design, <http://www.speech-design.de/>
60 Date of Release: March 2001 (?)
61 End of life: -
62 URL: <http://www.speech-design.de/>
63
64 HERMES:
65 Hermes-Pro ISDN/LAN router with integrated 8 x hub
66 Manufacturer: Multidata Gesellschaft fur Datentechnik und Informatik
67 <http://www.multidata.de/>
68 Date of Release: 2000 (?)
69 End of life: -
70 URL: <http://www.multidata.de/english/products/hpro.htm>
71
72 IP860:
73 VMEBus IP (Industry Pack) carrier board with MPC860
74 Manufacturer: MicroSys GmbH, <http://www.microsys.de/>
75 Date of Release: ?
76 End of life: -
77 URL: <http://www.microsys.de/html/ip860.html>
78
79 PCU_E:
80 PCU = Peripheral Controller Unit, Extended
81 Manufacturer: Siemens AG, ICN (Information and Communication Networks)
82 <http://www.siemens.de/page/1,3771,224315-1-999_2_226207-0,00.html>
83 Date of Release: April 2001
84 End of life: August 2001
85 URL: n. a.
86
87config RPXCLASSIC
88 bool "RPX-Classic"
89 help
90 The RPX-Classic is a single-board computer based on the Motorola
91 MPC860. It features 16MB of DRAM and a variable amount of flash,
92 I2C EEPROM, thermal monitoring, a PCMCIA slot, a DIP switch and two
93 LEDs. Variants with Ethernet ports exist. Say Y here to support it
94 directly.
95
96config BSEIP
97 bool "BSE-IP"
98 help
99 Say Y here to support the Bright Star Engineering ipEngine SBC.
100 This is a credit-card-sized device featuring a MPC823 processor,
101 26MB DRAM, 4MB flash, Ethernet, a 16K-gate FPGA, USB, an LCD/video
102 controller, and two RS232 ports.
103 14
104config MPC8XXFADS 15config MPC8XXFADS
105 bool "FADS" 16 bool "FADS"
@@ -107,110 +18,58 @@ config MPC8XXFADS
107 18
108config MPC86XADS 19config MPC86XADS
109 bool "MPC86XADS" 20 bool "MPC86XADS"
21 select CPM1
110 help 22 help
111 MPC86x Application Development System by Freescale Semiconductor. 23 MPC86x Application Development System by Freescale Semiconductor.
112 The MPC86xADS is meant to serve as a platform for s/w and h/w 24 The MPC86xADS is meant to serve as a platform for s/w and h/w
113 development around the MPC86X processor families. 25 development around the MPC86X processor families.
114 select FADS
115 26
116config MPC885ADS 27config MPC885ADS
117 bool "MPC885ADS" 28 bool "MPC885ADS"
29 select CPM1
118 help 30 help
119 Freescale Semiconductor MPC885 Application Development System (ADS). 31 Freescale Semiconductor MPC885 Application Development System (ADS).
120 Also known as DUET. 32 Also known as DUET.
121 The MPC885ADS is meant to serve as a platform for s/w and h/w 33 The MPC885ADS is meant to serve as a platform for s/w and h/w
122 development around the MPC885 processor family. 34 development around the MPC885 processor family.
123 35
124config TQM823L 36endchoice
125 bool "TQM823L"
126 help
127 Say Y here to support the TQM823L, one of an MPC8xx-based family of
128 mini SBCs (half credit-card size) from TQ Components first released
129 in late 1999. Technical references are at
130 <http://www.denx.de/PDF/TQM8xxLHWM201.pdf>, and
131 <http://www.denx.de/PDF/STK8xxLHWM201.pdf>, and an image at
132 <http://www.denx.de/embedded-ppc-en.html>.
133
134config TQM850L
135 bool "TQM850L"
136 help
137 Say Y here to support the TQM850L, one of an MPC8xx-based family of
138 mini SBCs (half credit-card size) from TQ Components first released
139 in late 1999. Technical references are at
140 <http://www.denx.de/PDF/TQM8xxLHWM201.pdf>, and
141 <http://www.denx.de/PDF/STK8xxLHWM201.pdf>, and an image at
142 <http://www.denx.de/embedded-ppc-en.html>.
143
144config TQM855L
145 bool "TQM855L"
146 help
147 Say Y here to support the TQM855L, one of an MPC8xx-based family of
148 mini SBCs (half credit-card size) from TQ Components first released
149 in late 1999. Technical references are at
150 <http://www.denx.de/PDF/TQM8xxLHWM201.pdf>, and
151 <http://www.denx.de/PDF/STK8xxLHWM201.pdf>, and an image at
152 <http://www.denx.de/embedded-ppc-en.html>.
153
154config TQM860L
155 bool "TQM860L"
156 help
157 Say Y here to support the TQM860L, one of an MPC8xx-based family of
158 mini SBCs (half credit-card size) from TQ Components first released
159 in late 1999. Technical references are at
160 <http://www.denx.de/PDF/TQM8xxLHWM201.pdf>, and
161 <http://www.denx.de/PDF/STK8xxLHWM201.pdf>, and an image at
162 <http://www.denx.de/embedded-ppc-en.html>.
163
164config FPS850L
165 bool "FPS850L"
166
167config IVMS8
168 bool "IVMS8"
169 help
170 Say Y here to support the Integrated Voice-Mail Small 8-channel SBC
171 from Speech Design, released March 2001. The manufacturer's website
172 is at <http://www.speech-design.de/>.
173
174config IVML24
175 bool "IVML24"
176 help
177 Say Y here to support the Integrated Voice-Mail Large 24-channel SBC
178 from Speech Design, released March 2001. The manufacturer's website
179 is at <http://www.speech-design.de/>.
180
181config HERMES_PRO
182 bool "HERMES"
183
184config IP860
185 bool "IP860"
186
187config LWMON
188 bool "LWMON"
189
190config PCU_E
191 bool "PCU_E"
192
193config CCM
194 bool "CCM"
195
196config LANTEC
197 bool "LANTEC"
198 37
199config MBX 38menu "Freescale Ethernet driver platform-specific options"
200 bool "MBX" 39 depends on (FS_ENET && MPC885ADS)
201 help 40
202 MBX is a line of Motorola single-board computer based around the 41 config MPC8xx_SECOND_ETH
203 MPC821 and MPC860 processors, and intended for embedded-controller 42 bool "Second Ethernet channel"
204 applications. Say Y here to support these boards directly. 43 depends on MPC885ADS
44 default y
45 help
46 This enables support for second Ethernet on MPC885ADS and MPC86xADS boards.
47 The latter will use SCC1, for 885ADS you can select it below.
48
49 choice
50 prompt "Second Ethernet channel"
51 depends on MPC8xx_SECOND_ETH
52 default MPC8xx_SECOND_ETH_FEC2
53
54 config MPC8xx_SECOND_ETH_FEC2
55 bool "FEC2"
56 depends on MPC885ADS
57 help
58 Enable FEC2 to serve as 2-nd Ethernet channel. Note that SMC2
59 (often 2-nd UART) will not work if this is enabled.
60
61 config MPC8xx_SECOND_ETH_SCC3
62 bool "SCC3"
63 depends on MPC885ADS
64 help
65 Enable SCC3 to serve as 2-nd Ethernet channel. Note that SMC1
66 (often 1-nd UART) will not work if this is enabled.
67
68 endchoice
205 69
206config WINCEPT 70endmenu
207 bool "WinCept"
208 help
209 The Wincept 100/110 is a Motorola single-board computer based on the
210 MPC821 PowerPC, introduced in 1998 and designed to be used in
211 thin-client machines. Say Y to support it directly.
212 71
213endchoice 72endmenu
214 73
215# 74#
216# MPC8xx Communication options 75# MPC8xx Communication options
@@ -219,79 +78,6 @@ endchoice
219menu "MPC8xx CPM Options" 78menu "MPC8xx CPM Options"
220 depends on 8xx 79 depends on 8xx
221 80
222config SCC_ENET
223 bool "CPM SCC Ethernet"
224 depends on NET_ETHERNET
225 help
226 Enable Ethernet support via the Motorola MPC8xx serial
227 communications controller.
228
229choice
230 prompt "SCC used for Ethernet"
231 depends on SCC_ENET
232 default SCC1_ENET
233
234config SCC1_ENET
235 bool "SCC1"
236 help
237 Use MPC8xx serial communications controller 1 to drive Ethernet
238 (default).
239
240config SCC2_ENET
241 bool "SCC2"
242 help
243 Use MPC8xx serial communications controller 2 to drive Ethernet.
244
245config SCC3_ENET
246 bool "SCC3"
247 help
248 Use MPC8xx serial communications controller 3 to drive Ethernet.
249
250endchoice
251
252config FEC_ENET
253 bool "860T FEC Ethernet"
254 depends on NET_ETHERNET
255 help
256 Enable Ethernet support via the Fast Ethernet Controller (FCC) on
257 the Motorola MPC8260.
258
259config USE_MDIO
260 bool "Use MDIO for PHY configuration"
261 depends on FEC_ENET
262 help
263 On some boards the hardware configuration of the ethernet PHY can be
264 used without any software interaction over the MDIO interface, so
265 all MII code can be omitted. Say N here if unsure or if you don't
266 need link status reports.
267
268config FEC_AM79C874
269 bool "Support AMD79C874 PHY"
270 depends on USE_MDIO
271
272config FEC_LXT970
273 bool "Support LXT970 PHY"
274 depends on USE_MDIO
275
276config FEC_LXT971
277 bool "Support LXT971 PHY"
278 depends on USE_MDIO
279
280config FEC_QS6612
281 bool "Support QS6612 PHY"
282 depends on USE_MDIO
283
284config ENET_BIG_BUFFERS
285 bool "Use Big CPM Ethernet Buffers"
286 depends on SCC_ENET || FEC_ENET
287 help
288 Allocate large buffers for MPC8xx Ethernet. Increases throughput
289 and decreases the likelihood of dropped packets, but costs memory.
290
291config HTDMSOUND
292 bool "Embedded Planet HIOX Audio"
293 depends on SOUND=y
294
295# This doesn't really belong here, but it is convenient to ask 81# This doesn't really belong here, but it is convenient to ask
296# 8xx specific questions. 82# 8xx specific questions.
297comment "Generic MPC8xx Options" 83comment "Generic MPC8xx Options"
diff --git a/arch/powerpc/platforms/8xx/Makefile b/arch/powerpc/platforms/8xx/Makefile
new file mode 100644
index 000000000000..1b59ffa92521
--- /dev/null
+++ b/arch/powerpc/platforms/8xx/Makefile
@@ -0,0 +1,5 @@
1#
2# Makefile for the PowerPC 8xx linux kernel.
3#
4obj-$(CONFIG_PPC_8xx) += m8xx_setup.o
5obj-$(CONFIG_MPC885ADS) += mpc885ads_setup.o
diff --git a/arch/powerpc/platforms/8xx/m8xx_setup.c b/arch/powerpc/platforms/8xx/m8xx_setup.c
new file mode 100644
index 000000000000..9ed7125f0150
--- /dev/null
+++ b/arch/powerpc/platforms/8xx/m8xx_setup.c
@@ -0,0 +1,303 @@
1/*
2 * Copyright (C) 1995 Linus Torvalds
3 * Adapted from 'alpha' version by Gary Thomas
4 * Modified by Cort Dougan (cort@cs.nmt.edu)
5 * Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
6 * Further modified for generic 8xx by Dan.
7 */
8
9/*
10 * bootup setup stuff..
11 */
12
13#include <linux/errno.h>
14#include <linux/sched.h>
15#include <linux/kernel.h>
16#include <linux/mm.h>
17#include <linux/stddef.h>
18#include <linux/unistd.h>
19#include <linux/ptrace.h>
20#include <linux/slab.h>
21#include <linux/user.h>
22#include <linux/a.out.h>
23#include <linux/tty.h>
24#include <linux/major.h>
25#include <linux/interrupt.h>
26#include <linux/reboot.h>
27#include <linux/init.h>
28#include <linux/initrd.h>
29#include <linux/ioport.h>
30#include <linux/bootmem.h>
31#include <linux/seq_file.h>
32#include <linux/root_dev.h>
33#include <linux/time.h>
34#include <linux/rtc.h>
35
36#include <asm/mmu.h>
37#include <asm/reg.h>
38#include <asm/residual.h>
39#include <asm/io.h>
40#include <asm/pgtable.h>
41#include <asm/mpc8xx.h>
42#include <asm/8xx_immap.h>
43#include <asm/machdep.h>
44#include <asm/bootinfo.h>
45#include <asm/time.h>
46#include <asm/prom.h>
47#include <asm/fs_pd.h>
48#include <mm/mmu_decl.h>
49
50#include "sysdev/mpc8xx_pic.h"
51
52void m8xx_calibrate_decr(void);
53extern void m8xx_wdt_handler_install(bd_t *bp);
54extern int cpm_pic_init(void);
55extern int cpm_get_irq(void);
56
57/* A place holder for time base interrupts, if they are ever enabled. */
58irqreturn_t timebase_interrupt(int irq, void * dev)
59{
60 printk ("timebase_interrupt()\n");
61
62 return IRQ_HANDLED;
63}
64
65static struct irqaction tbint_irqaction = {
66 .handler = timebase_interrupt,
67 .mask = CPU_MASK_NONE,
68 .name = "tbint",
69};
70
71/* per-board overridable init_internal_rtc() function. */
72void __init __attribute__ ((weak))
73init_internal_rtc(void)
74{
75 sit8xx_t *sys_tmr = (sit8xx_t *) immr_map(im_sit);
76
77 /* Disable the RTC one second and alarm interrupts. */
78 clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
79
80 /* Enable the RTC */
81 setbits16(&sys_tmr->sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
82 immr_unmap(sys_tmr);
83}
84
85static int __init get_freq(char *name, unsigned long *val)
86{
87 struct device_node *cpu;
88 unsigned int *fp;
89 int found = 0;
90
91 /* The cpu node should have timebase and clock frequency properties */
92 cpu = of_find_node_by_type(NULL, "cpu");
93
94 if (cpu) {
95 fp = (unsigned int *)get_property(cpu, name, NULL);
96 if (fp) {
97 found = 1;
98 *val = *fp++;
99 }
100
101 of_node_put(cpu);
102 }
103
104 return found;
105}
106
107/* The decrementer counts at the system (internal) clock frequency divided by
108 * sixteen, or external oscillator divided by four. We force the processor
109 * to use system clock divided by sixteen.
110 */
111void __init mpc8xx_calibrate_decr(void)
112{
113 struct device_node *cpu;
114 cark8xx_t *clk_r1;
115 car8xx_t *clk_r2;
116 sitk8xx_t *sys_tmr1;
117 sit8xx_t *sys_tmr2;
118 int irq, virq;
119
120 clk_r1 = (cark8xx_t *) immr_map(im_clkrstk);
121
122 /* Unlock the SCCR. */
123 out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY);
124 out_be32(&clk_r1->cark_sccrk, KAPWR_KEY);
125 immr_unmap(clk_r1);
126
127 /* Force all 8xx processors to use divide by 16 processor clock. */
128 clk_r2 = (car8xx_t *) immr_map(im_clkrst);
129 setbits32(&clk_r2->car_sccr, 0x02000000);
130 immr_unmap(clk_r2);
131
132 /* Processor frequency is MHz.
133 */
134 ppc_tb_freq = 50000000;
135 if (!get_freq("bus-frequency", &ppc_tb_freq)) {
136 printk(KERN_ERR "WARNING: Estimating decrementer frequency "
137 "(not found)\n");
138 }
139 ppc_tb_freq /= 16;
140 ppc_proc_freq = 50000000;
141 if (!get_freq("clock-frequency", &ppc_proc_freq))
142 printk(KERN_ERR "WARNING: Estimating processor frequency"
143 "(not found)\n");
144
145 printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);
146
147 /* Perform some more timer/timebase initialization. This used
148 * to be done elsewhere, but other changes caused it to get
149 * called more than once....that is a bad thing.
150 *
151 * First, unlock all of the registers we are going to modify.
152 * To protect them from corruption during power down, registers
153 * that are maintained by keep alive power are "locked". To
154 * modify these registers we have to write the key value to
155 * the key location associated with the register.
156 * Some boards power up with these unlocked, while others
157 * are locked. Writing anything (including the unlock code?)
158 * to the unlocked registers will lock them again. So, here
159 * we guarantee the registers are locked, then we unlock them
160 * for our use.
161 */
162 sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk);
163 out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY);
164 out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY);
165 out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY);
166 out_be32(&sys_tmr1->sitk_tbscrk, KAPWR_KEY);
167 out_be32(&sys_tmr1->sitk_rtcsck, KAPWR_KEY);
168 out_be32(&sys_tmr1->sitk_tbk, KAPWR_KEY);
169 immr_unmap(sys_tmr1);
170
171 init_internal_rtc();
172
173 /* Enabling the decrementer also enables the timebase interrupts
174 * (or from the other point of view, to get decrementer interrupts
175 * we have to enable the timebase). The decrementer interrupt
176 * is wired into the vector table, nothing to do here for that.
177 */
178 cpu = of_find_node_by_type(NULL, "cpu");
179 virq= irq_of_parse_and_map(cpu, 0);
180 irq = irq_map[virq].hwirq;
181
182 sys_tmr2 = (sit8xx_t *) immr_map(im_sit);
183 out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |
184 (TBSCR_TBF | TBSCR_TBE));
185 immr_unmap(sys_tmr2);
186
187 if (setup_irq(virq, &tbint_irqaction))
188 panic("Could not allocate timer IRQ!");
189
190#ifdef CONFIG_8xx_WDT
191 /* Install watchdog timer handler early because it might be
192 * already enabled by the bootloader
193 */
194 m8xx_wdt_handler_install(binfo);
195#endif
196}
197
198/* The RTC on the MPC8xx is an internal register.
199 * We want to protect this during power down, so we need to unlock,
200 * modify, and re-lock.
201 */
202
203int mpc8xx_set_rtc_time(struct rtc_time *tm)
204{
205 sitk8xx_t *sys_tmr1;
206 sit8xx_t *sys_tmr2;
207 int time;
208
209 sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk);
210 sys_tmr2 = (sit8xx_t *) immr_map(im_sit);
211 time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday,
212 tm->tm_hour, tm->tm_min, tm->tm_sec);
213
214 out_be32(&sys_tmr1->sitk_rtck, KAPWR_KEY);
215 out_be32(&sys_tmr2->sit_rtc, time);
216 out_be32(&sys_tmr1->sitk_rtck, ~KAPWR_KEY);
217
218 immr_unmap(sys_tmr2);
219 immr_unmap(sys_tmr1);
220 return 0;
221}
222
223void mpc8xx_get_rtc_time(struct rtc_time *tm)
224{
225 unsigned long data;
226 sit8xx_t *sys_tmr = (sit8xx_t *) immr_map(im_sit);
227
228 /* Get time from the RTC. */
229 data = in_be32(&sys_tmr->sit_rtc);
230 to_tm(data, tm);
231 tm->tm_year -= 1900;
232 tm->tm_mon -= 1;
233 immr_unmap(sys_tmr);
234 return;
235}
236
237void mpc8xx_restart(char *cmd)
238{
239 __volatile__ unsigned char dummy;
240 car8xx_t * clk_r = (car8xx_t *) immr_map(im_clkrst);
241
242
243 local_irq_disable();
244
245 setbits32(&clk_r->car_plprcr, 0x00000080);
246 /* Clear the ME bit in MSR to cause checkstop on machine check
247 */
248 mtmsr(mfmsr() & ~0x1000);
249
250 dummy = in_8(&clk_r->res[0]);
251 printk("Restart failed\n");
252 while(1);
253}
254
255void mpc8xx_show_cpuinfo(struct seq_file *m)
256{
257 struct device_node *root;
258 uint memsize = total_memory;
259 const char *model = "";
260
261 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
262
263 root = of_find_node_by_path("/");
264 if (root)
265 model = get_property(root, "model", NULL);
266 seq_printf(m, "Machine\t\t: %s\n", model);
267 of_node_put(root);
268
269 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
270}
271
272static void cpm_cascade(unsigned int irq, struct irq_desc *desc)
273{
274 int cascade_irq;
275
276 if ((cascade_irq = cpm_get_irq()) >= 0) {
277 struct irq_desc *cdesc = irq_desc + cascade_irq;
278
279 generic_handle_irq(cascade_irq);
280 cdesc->chip->eoi(cascade_irq);
281 }
282 desc->chip->eoi(irq);
283}
284
285/* Initialize the internal interrupt controller. The number of
286 * interrupts supported can vary with the processor type, and the
287 * 82xx family can have up to 64.
288 * External interrupts can be either edge or level triggered, and
289 * need to be initialized by the appropriate driver.
290 */
291void __init m8xx_pic_init(void)
292{
293 int irq;
294
295 if (mpc8xx_pic_init()) {
296 printk(KERN_ERR "Failed interrupt 8xx controller initialization\n");
297 return;
298 }
299
300 irq = cpm_pic_init();
301 if (irq != NO_IRQ)
302 set_irq_chained_handler(irq, cpm_cascade);
303}
diff --git a/arch/powerpc/platforms/8xx/mpc885ads.h b/arch/powerpc/platforms/8xx/mpc885ads.h
new file mode 100644
index 000000000000..30cbebfe84c5
--- /dev/null
+++ b/arch/powerpc/platforms/8xx/mpc885ads.h
@@ -0,0 +1,95 @@
1/*
2 * A collection of structures, addresses, and values associated with
3 * the Freescale MPC885ADS board.
4 * Copied from the FADS stuff.
5 *
6 * Author: MontaVista Software, Inc.
7 * source@mvista.com
8 *
9 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is licensed
11 * "as is" without any warranty of any kind, whether express or implied.
12 */
13
14#ifdef __KERNEL__
15#ifndef __ASM_MPC885ADS_H__
16#define __ASM_MPC885ADS_H__
17
18#include <asm/ppcboot.h>
19#include <sysdev/fsl_soc.h>
20
21/* U-Boot maps BCSR to 0xff080000 */
22#define BCSR_ADDR ((uint)0xff080000)
23#define BCSR_SIZE ((uint)32)
24#define BCSR0 ((uint)(BCSR_ADDR + 0x00))
25#define BCSR1 ((uint)(BCSR_ADDR + 0x04))
26#define BCSR2 ((uint)(BCSR_ADDR + 0x08))
27#define BCSR3 ((uint)(BCSR_ADDR + 0x0c))
28#define BCSR4 ((uint)(BCSR_ADDR + 0x10))
29
30#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
31#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
32
33#define IMAP_ADDR (get_immrbase())
34#define IMAP_SIZE ((uint)(64 * 1024))
35
36#define MPC8xx_CPM_OFFSET (0x9c0)
37#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET)
38#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver
39
40#define PCMCIA_MEM_ADDR (uint)0xff020000)
41#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
42
43/* Bits of interest in the BCSRs.
44 */
45#define BCSR1_ETHEN ((uint)0x20000000)
46#define BCSR1_IRDAEN ((uint)0x10000000)
47#define BCSR1_RS232EN_1 ((uint)0x01000000)
48#define BCSR1_PCCEN ((uint)0x00800000)
49#define BCSR1_PCCVCC0 ((uint)0x00400000)
50#define BCSR1_PCCVPP0 ((uint)0x00200000)
51#define BCSR1_PCCVPP1 ((uint)0x00100000)
52#define BCSR1_PCCVPP_MASK (BCSR1_PCCVPP0 | BCSR1_PCCVPP1)
53#define BCSR1_RS232EN_2 ((uint)0x00040000)
54#define BCSR1_PCCVCC1 ((uint)0x00010000)
55#define BCSR1_PCCVCC_MASK (BCSR1_PCCVCC0 | BCSR1_PCCVCC1)
56
57#define BCSR4_ETH10_RST ((uint)0x80000000) /* 10Base-T PHY reset*/
58#define BCSR4_USB_LO_SPD ((uint)0x04000000)
59#define BCSR4_USB_VCC ((uint)0x02000000)
60#define BCSR4_USB_FULL_SPD ((uint)0x00040000)
61#define BCSR4_USB_EN ((uint)0x00020000)
62
63#define BCSR5_MII2_EN 0x40
64#define BCSR5_MII2_RST 0x20
65#define BCSR5_T1_RST 0x10
66#define BCSR5_ATM155_RST 0x08
67#define BCSR5_ATM25_RST 0x04
68#define BCSR5_MII1_EN 0x02
69#define BCSR5_MII1_RST 0x01
70
71/* Interrupt level assignments */
72#define PHY_INTERRUPT SIU_IRQ7 /* PHY link change interrupt */
73#define SIU_INT_FEC1 SIU_LEVEL1 /* FEC1 interrupt */
74#define SIU_INT_FEC2 SIU_LEVEL3 /* FEC2 interrupt */
75#define FEC_INTERRUPT SIU_INT_FEC1 /* FEC interrupt */
76
77/* We don't use the 8259 */
78#define NR_8259_INTS 0
79
80/* CPM Ethernet through SCC3 */
81#define PA_ENET_RXD ((ushort)0x0040)
82#define PA_ENET_TXD ((ushort)0x0080)
83#define PE_ENET_TCLK ((uint)0x00004000)
84#define PE_ENET_RCLK ((uint)0x00008000)
85#define PE_ENET_TENA ((uint)0x00000010)
86#define PC_ENET_CLSN ((ushort)0x0400)
87#define PC_ENET_RENA ((ushort)0x0800)
88
89/* Control bits in the SICR to route TCLK (CLK5) and RCLK (CLK6) to
90 * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero */
91#define SICR_ENET_MASK ((uint)0x00ff0000)
92#define SICR_ENET_CLKRT ((uint)0x002c0000)
93
94#endif /* __ASM_MPC885ADS_H__ */
95#endif /* __KERNEL__ */
diff --git a/arch/powerpc/platforms/8xx/mpc885ads_setup.c b/arch/powerpc/platforms/8xx/mpc885ads_setup.c
new file mode 100644
index 000000000000..c5fefdf66c0a
--- /dev/null
+++ b/arch/powerpc/platforms/8xx/mpc885ads_setup.c
@@ -0,0 +1,387 @@
1/*arch/ppc/platforms/mpc885ads-setup.c
2 *
3 * Platform setup for the Freescale mpc885ads board
4 *
5 * Vitaly Bordug <vbordug@ru.mvista.com>
6 *
7 * Copyright 2005 MontaVista Software Inc.
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14#include <linux/init.h>
15#include <linux/module.h>
16#include <linux/param.h>
17#include <linux/string.h>
18#include <linux/ioport.h>
19#include <linux/device.h>
20#include <linux/delay.h>
21#include <linux/root_dev.h>
22
23#include <linux/fs_enet_pd.h>
24#include <linux/fs_uart_pd.h>
25#include <linux/mii.h>
26
27#include <asm/delay.h>
28#include <asm/io.h>
29#include <asm/machdep.h>
30#include <asm/page.h>
31#include <asm/processor.h>
32#include <asm/system.h>
33#include <asm/time.h>
34#include <asm/ppcboot.h>
35#include <asm/mpc8xx.h>
36#include <asm/8xx_immap.h>
37#include <asm/commproc.h>
38#include <asm/fs_pd.h>
39#include <asm/prom.h>
40
41extern void cpm_reset(void);
42extern void mpc8xx_show_cpuinfo(struct seq_file*);
43extern void mpc8xx_restart(char *cmd);
44extern void mpc8xx_calibrate_decr(void);
45extern int mpc8xx_set_rtc_time(struct rtc_time *tm);
46extern void mpc8xx_get_rtc_time(struct rtc_time *tm);
47extern void m8xx_pic_init(void);
48extern unsigned int mpc8xx_get_irq(void);
49
50static void init_smc1_uart_ioports(struct fs_uart_platform_info* fpi);
51static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi);
52static void init_scc3_ioports(struct fs_platform_info* ptr);
53
54void __init mpc885ads_board_setup(void)
55{
56 cpm8xx_t *cp;
57 unsigned int *bcsr_io;
58 u8 tmpval8;
59
60#ifdef CONFIG_FS_ENET
61 iop8xx_t *io_port;
62#endif
63
64 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
65 cp = (cpm8xx_t *)immr_map(im_cpm);
66
67 if (bcsr_io == NULL) {
68 printk(KERN_CRIT "Could not remap BCSR\n");
69 return;
70 }
71#ifdef CONFIG_SERIAL_CPM_SMC1
72 clrbits32(bcsr_io, BCSR1_RS232EN_1);
73 clrbits32(&cp->cp_simode, 0xe0000000 >> 17); /* brg1 */
74 tmpval8 = in_8(&(cp->cp_smc[0].smc_smcm)) | (SMCM_RX | SMCM_TX);
75 out_8(&(cp->cp_smc[0].smc_smcm), tmpval8);
76 clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN); /* brg1 */
77#else
78 setbits32(bcsr_io,BCSR1_RS232EN_1);
79 out_be16(&cp->cp_smc[0].smc_smcmr, 0);
80 out_8(&cp->cp_smc[0].smc_smce, 0);
81#endif
82
83#ifdef CONFIG_SERIAL_CPM_SMC2
84 clrbits32(bcsr_io,BCSR1_RS232EN_2);
85 clrbits32(&cp->cp_simode, 0xe0000000 >> 1);
86 setbits32(&cp->cp_simode, 0x20000000 >> 1); /* brg2 */
87 tmpval8 = in_8(&(cp->cp_smc[1].smc_smcm)) | (SMCM_RX | SMCM_TX);
88 out_8(&(cp->cp_smc[1].smc_smcm), tmpval8);
89 clrbits16(&cp->cp_smc[1].smc_smcmr, SMCMR_REN | SMCMR_TEN);
90
91 init_smc2_uart_ioports(0);
92#else
93 setbits32(bcsr_io,BCSR1_RS232EN_2);
94 out_be16(&cp->cp_smc[1].smc_smcmr, 0);
95 out_8(&cp->cp_smc[1].smc_smce, 0);
96#endif
97 immr_unmap(cp);
98 iounmap(bcsr_io);
99
100#ifdef CONFIG_FS_ENET
101 /* use MDC for MII (common) */
102 io_port = (iop8xx_t*)immr_map(im_ioport);
103 setbits16(&io_port->iop_pdpar, 0x0080);
104 clrbits16(&io_port->iop_pddir, 0x0080);
105
106 bcsr_io = ioremap(BCSR5, sizeof(unsigned long));
107 clrbits32(bcsr_io,BCSR5_MII1_EN);
108 clrbits32(bcsr_io,BCSR5_MII1_RST);
109#ifndef CONFIG_FC_ENET_HAS_SCC
110 clrbits32(bcsr_io,BCSR5_MII2_EN);
111 clrbits32(bcsr_io,BCSR5_MII2_RST);
112
113#endif
114 iounmap(bcsr_io);
115 immr_unmap(io_port);
116
117#endif
118}
119
120
121static void init_fec1_ioports(struct fs_platform_info* ptr)
122{
123 cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm);
124 iop8xx_t *io_port = (iop8xx_t *)immr_map(im_ioport);
125
126 /* configure FEC1 pins */
127 setbits16(&io_port->iop_papar, 0xf830);
128 setbits16(&io_port->iop_padir, 0x0830);
129 clrbits16(&io_port->iop_padir, 0xf000);
130
131 setbits32(&cp->cp_pbpar, 0x00001001);
132 clrbits32(&cp->cp_pbdir, 0x00001001);
133
134 setbits16(&io_port->iop_pcpar, 0x000c);
135 clrbits16(&io_port->iop_pcdir, 0x000c);
136
137 setbits32(&cp->cp_pepar, 0x00000003);
138 setbits32(&cp->cp_pedir, 0x00000003);
139 clrbits32(&cp->cp_peso, 0x00000003);
140 clrbits32(&cp->cp_cptr, 0x00000100);
141
142 immr_unmap(io_port);
143 immr_unmap(cp);
144}
145
146
147static void init_fec2_ioports(struct fs_platform_info* ptr)
148{
149 cpm8xx_t *cp = (cpm8xx_t *)immr_map(im_cpm);
150 iop8xx_t *io_port = (iop8xx_t *)immr_map(im_ioport);
151
152 /* configure FEC2 pins */
153 setbits32(&cp->cp_pepar, 0x0003fffc);
154 setbits32(&cp->cp_pedir, 0x0003fffc);
155 clrbits32(&cp->cp_peso, 0x000087fc);
156 setbits32(&cp->cp_peso, 0x00037800);
157 clrbits32(&cp->cp_cptr, 0x00000080);
158
159 immr_unmap(io_port);
160 immr_unmap(cp);
161}
162
163void init_fec_ioports(struct fs_platform_info *fpi)
164{
165 int fec_no = fs_get_fec_index(fpi->fs_no);
166
167 switch (fec_no) {
168 case 0:
169 init_fec1_ioports(fpi);
170 break;
171 case 1:
172 init_fec2_ioports(fpi);
173 break;
174 default:
175 printk(KERN_ERR "init_fec_ioports: invalid FEC number\n");
176 return;
177 }
178}
179
180static void init_scc3_ioports(struct fs_platform_info* fpi)
181{
182 unsigned *bcsr_io;
183 iop8xx_t *io_port;
184 cpm8xx_t *cp;
185
186 bcsr_io = ioremap(BCSR_ADDR, BCSR_SIZE);
187 io_port = (iop8xx_t *)immr_map(im_ioport);
188 cp = (cpm8xx_t *)immr_map(im_cpm);
189
190 if (bcsr_io == NULL) {
191 printk(KERN_CRIT "Could not remap BCSR\n");
192 return;
193 }
194
195 /* Enable the PHY.
196 */
197 clrbits32(bcsr_io+4, BCSR4_ETH10_RST);
198 udelay(1000);
199 setbits32(bcsr_io+4, BCSR4_ETH10_RST);
200 /* Configure port A pins for Txd and Rxd.
201 */
202 setbits16(&io_port->iop_papar, PA_ENET_RXD | PA_ENET_TXD);
203 clrbits16(&io_port->iop_padir, PA_ENET_RXD | PA_ENET_TXD);
204
205 /* Configure port C pins to enable CLSN and RENA.
206 */
207 clrbits16(&io_port->iop_pcpar, PC_ENET_CLSN | PC_ENET_RENA);
208 clrbits16(&io_port->iop_pcdir, PC_ENET_CLSN | PC_ENET_RENA);
209 setbits16(&io_port->iop_pcso, PC_ENET_CLSN | PC_ENET_RENA);
210
211 /* Configure port E for TCLK and RCLK.
212 */
213 setbits32(&cp->cp_pepar, PE_ENET_TCLK | PE_ENET_RCLK);
214 clrbits32(&cp->cp_pepar, PE_ENET_TENA);
215 clrbits32(&cp->cp_pedir,
216 PE_ENET_TCLK | PE_ENET_RCLK | PE_ENET_TENA);
217 clrbits32(&cp->cp_peso, PE_ENET_TCLK | PE_ENET_RCLK);
218 setbits32(&cp->cp_peso, PE_ENET_TENA);
219
220 /* Configure Serial Interface clock routing.
221 * First, clear all SCC bits to zero, then set the ones we want.
222 */
223 clrbits32(&cp->cp_sicr, SICR_ENET_MASK);
224 setbits32(&cp->cp_sicr, SICR_ENET_CLKRT);
225
226 /* Disable Rx and Tx. SMC1 sshould be stopped if SCC3 eternet are used.
227 */
228 clrbits16(&cp->cp_smc[0].smc_smcmr, SMCMR_REN | SMCMR_TEN);
229 /* On the MPC885ADS SCC ethernet PHY is initialized in the full duplex mode
230 * by H/W setting after reset. SCC ethernet controller support only half duplex.
231 * This discrepancy of modes causes a lot of carrier lost errors.
232 */
233
234 /* In the original SCC enet driver the following code is placed at
235 the end of the initialization */
236 setbits32(&cp->cp_pepar, PE_ENET_TENA);
237 clrbits32(&cp->cp_pedir, PE_ENET_TENA);
238 setbits32(&cp->cp_peso, PE_ENET_TENA);
239
240 setbits32(bcsr_io+4, BCSR1_ETHEN);
241 iounmap(bcsr_io);
242 immr_unmap(io_port);
243 immr_unmap(cp);
244}
245
246void init_scc_ioports(struct fs_platform_info *fpi)
247{
248 int scc_no = fs_get_scc_index(fpi->fs_no);
249
250 switch (scc_no) {
251 case 2:
252 init_scc3_ioports(fpi);
253 break;
254 default:
255 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
256 return;
257 }
258}
259
260
261
262static void init_smc1_uart_ioports(struct fs_uart_platform_info* ptr)
263{
264 unsigned *bcsr_io;
265 cpm8xx_t *cp;
266
267 cp = (cpm8xx_t *)immr_map(im_cpm);
268 setbits32(&cp->cp_pepar, 0x000000c0);
269 clrbits32(&cp->cp_pedir, 0x000000c0);
270 clrbits32(&cp->cp_peso, 0x00000040);
271 setbits32(&cp->cp_peso, 0x00000080);
272 immr_unmap(cp);
273
274 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
275
276 if (bcsr_io == NULL) {
277 printk(KERN_CRIT "Could not remap BCSR1\n");
278 return;
279 }
280 clrbits32(bcsr_io,BCSR1_RS232EN_1);
281 iounmap(bcsr_io);
282}
283
284static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi)
285{
286 unsigned *bcsr_io;
287 cpm8xx_t *cp;
288
289 cp = (cpm8xx_t *)immr_map(im_cpm);
290 setbits32(&cp->cp_pepar, 0x00000c00);
291 clrbits32(&cp->cp_pedir, 0x00000c00);
292 clrbits32(&cp->cp_peso, 0x00000400);
293 setbits32(&cp->cp_peso, 0x00000800);
294 immr_unmap(cp);
295
296 bcsr_io = ioremap(BCSR1, sizeof(unsigned long));
297
298 if (bcsr_io == NULL) {
299 printk(KERN_CRIT "Could not remap BCSR1\n");
300 return;
301 }
302 clrbits32(bcsr_io,BCSR1_RS232EN_2);
303 iounmap(bcsr_io);
304}
305
306void init_smc_ioports(struct fs_uart_platform_info *data)
307{
308 int smc_no = fs_uart_id_fsid2smc(data->fs_no);
309
310 switch (smc_no) {
311 case 0:
312 init_smc1_uart_ioports(data);
313 data->brg = data->clk_rx;
314 break;
315 case 1:
316 init_smc2_uart_ioports(data);
317 data->brg = data->clk_rx;
318 break;
319 default:
320 printk(KERN_ERR "init_scc_ioports: invalid SCC number\n");
321 return;
322 }
323}
324
325int platform_device_skip(char *model, int id)
326{
327#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
328 const char *dev = "FEC";
329 int n = 2;
330#else
331 const char *dev = "SCC";
332 int n = 3;
333#endif
334
335 if (!strcmp(model, dev) && n == id)
336 return 1;
337
338 return 0;
339}
340
341static void __init mpc885ads_setup_arch(void)
342{
343 struct device_node *cpu;
344
345 cpu = of_find_node_by_type(NULL, "cpu");
346 if (cpu != 0) {
347 const unsigned int *fp;
348
349 fp = get_property(cpu, "clock-frequency", NULL);
350 if (fp != 0)
351 loops_per_jiffy = *fp / HZ;
352 else
353 loops_per_jiffy = 50000000 / HZ;
354 of_node_put(cpu);
355 }
356
357 cpm_reset();
358
359 mpc885ads_board_setup();
360
361 ROOT_DEV = Root_NFS;
362}
363
364static int __init mpc885ads_probe(void)
365{
366 char *model = of_get_flat_dt_prop(of_get_flat_dt_root(),
367 "model", NULL);
368 if (model == NULL)
369 return 0;
370 if (strcmp(model, "MPC885ADS"))
371 return 0;
372
373 return 1;
374}
375
376define_machine(mpc885_ads) {
377 .name = "MPC885 ADS",
378 .probe = mpc885ads_probe,
379 .setup_arch = mpc885ads_setup_arch,
380 .init_IRQ = m8xx_pic_init,
381 .show_cpuinfo = mpc8xx_show_cpuinfo,
382 .get_irq = mpc8xx_get_irq,
383 .restart = mpc8xx_restart,
384 .calibrate_decr = mpc8xx_calibrate_decr,
385 .set_rtc_time = mpc8xx_set_rtc_time,
386 .get_rtc_time = mpc8xx_get_rtc_time,
387};
diff --git a/arch/powerpc/platforms/Makefile b/arch/powerpc/platforms/Makefile
index 507d1b98f270..7f03ea9ab366 100644
--- a/arch/powerpc/platforms/Makefile
+++ b/arch/powerpc/platforms/Makefile
@@ -8,6 +8,7 @@ endif
8obj-$(CONFIG_PPC_MPC52xx) += 52xx/ 8obj-$(CONFIG_PPC_MPC52xx) += 52xx/
9obj-$(CONFIG_PPC_CHRP) += chrp/ 9obj-$(CONFIG_PPC_CHRP) += chrp/
10obj-$(CONFIG_4xx) += 4xx/ 10obj-$(CONFIG_4xx) += 4xx/
11obj-$(CONFIG_PPC_8xx) += 8xx/
11obj-$(CONFIG_PPC_83xx) += 83xx/ 12obj-$(CONFIG_PPC_83xx) += 83xx/
12obj-$(CONFIG_PPC_85xx) += 85xx/ 13obj-$(CONFIG_PPC_85xx) += 85xx/
13obj-$(CONFIG_PPC_86xx) += 86xx/ 14obj-$(CONFIG_PPC_86xx) += 86xx/
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-23 19:56:23 -0500