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authorLinus Torvalds <torvalds@linux-foundation.org>2009-01-12 19:25:35 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2009-01-12 19:25:35 -0500
commit9219a3b9889dbc7dae68e472f239672ff48860b0 (patch)
treec6446d63dd7ffb0f118804e354eee3d80041717e
parent23ead7291269db3be71b442324381c8d63e5d0b3 (diff)
parentcde15b5927fea3e1b4de0b277008cf273d8b000b (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (37 commits) MIPS: Only write c0_framemask on CPUs which have this register. MIPS: Alchemy: new userspace suspend interface for development boards. MIPS: Alchemy: dbdma suspend/resume support. MIPS: Alchemy: Fix up PM code on Au1550/Au1200 MIPS: Alchemy: move calc_clock function. MIPS: Alchemy: RTC counter clocksource / clockevent support. MIPS: make cp0 counter clocksource/event usable as fallback. MIPS: Alchemy: remove cpu_table. MIPS: Alchemy: remove get/set_au1x00_lcd_clock(). MIPS: Print irq handler description MIPS: Alchemy: pb1200: update CPLD cascade irq handler. MIPS: Alchemy: update core interrupt code. MIPS: Alchemy: move commandline mangling out of common code MIPS: Alchemy: devboards: consolidate files MIPS: Alchemy: Move development board code to common subdirectory MIPS: Add Cavium OCTEON to arch/mips/Kconfig MIPS: Add defconfig for Cavium OCTEON. MIPS: Adjust the dma-common.c platform hooks. MIPS: Add Cavium OCTEON slot into proper tlb category. MIPS: Compute branch returns for Cavium OCTEON specific branch instructions. ...
Diffstat
-rw-r--r--arch/mips/Kconfig71
-rw-r--r--arch/mips/Makefile40
-rw-r--r--arch/mips/alchemy/Kconfig5
-rw-r--r--arch/mips/alchemy/common/Makefile4
-rw-r--r--arch/mips/alchemy/common/au1xxx_irqmap.c205
-rw-r--r--arch/mips/alchemy/common/clocks.c65
-rw-r--r--arch/mips/alchemy/common/cputable.c52
-rw-r--r--arch/mips/alchemy/common/dbdma.c65
-rw-r--r--arch/mips/alchemy/common/irq.c745
-rw-r--r--arch/mips/alchemy/common/power.c406
-rw-r--r--arch/mips/alchemy/common/reset.c2
-rw-r--r--arch/mips/alchemy/common/setup.c71
-rw-r--r--arch/mips/alchemy/common/sleeper.S118
-rw-r--r--arch/mips/alchemy/common/time.c311
-rw-r--r--arch/mips/alchemy/db1x00/init.c62
-rw-r--r--arch/mips/alchemy/devboards/Makefile18
-rw-r--r--arch/mips/alchemy/devboards/db1x00/Makefile (renamed from arch/mips/alchemy/db1x00/Makefile)2
-rw-r--r--arch/mips/alchemy/devboards/db1x00/board_setup.c (renamed from arch/mips/alchemy/db1x00/board_setup.c)37
-rw-r--r--arch/mips/alchemy/devboards/db1x00/irqmap.c (renamed from arch/mips/alchemy/db1x00/irqmap.c)24
-rw-r--r--arch/mips/alchemy/devboards/pb1000/Makefile (renamed from arch/mips/alchemy/pb1000/Makefile)2
-rw-r--r--arch/mips/alchemy/devboards/pb1000/board_setup.c (renamed from arch/mips/alchemy/pb1000/board_setup.c)30
-rw-r--r--arch/mips/alchemy/devboards/pb1100/Makefile (renamed from arch/mips/alchemy/pb1100/Makefile)2
-rw-r--r--arch/mips/alchemy/devboards/pb1100/board_setup.c (renamed from arch/mips/alchemy/pb1100/board_setup.c)47
-rw-r--r--arch/mips/alchemy/devboards/pb1200/Makefile (renamed from arch/mips/alchemy/pb1200/Makefile)3
-rw-r--r--arch/mips/alchemy/devboards/pb1200/board_setup.c (renamed from arch/mips/alchemy/pb1200/board_setup.c)34
-rw-r--r--arch/mips/alchemy/devboards/pb1200/irqmap.c (renamed from arch/mips/alchemy/pb1200/irqmap.c)94
-rw-r--r--arch/mips/alchemy/devboards/pb1200/platform.c (renamed from arch/mips/alchemy/pb1200/platform.c)0
-rw-r--r--arch/mips/alchemy/devboards/pb1500/Makefile (renamed from arch/mips/alchemy/pb1500/Makefile)2
-rw-r--r--arch/mips/alchemy/devboards/pb1500/board_setup.c (renamed from arch/mips/alchemy/pb1500/board_setup.c)44
-rw-r--r--arch/mips/alchemy/devboards/pb1550/Makefile (renamed from arch/mips/alchemy/pb1550/Makefile)2
-rw-r--r--arch/mips/alchemy/devboards/pb1550/board_setup.c (renamed from arch/mips/alchemy/pb1550/board_setup.c)34
-rw-r--r--arch/mips/alchemy/devboards/pm.c229
-rw-r--r--arch/mips/alchemy/devboards/prom.c (renamed from arch/mips/alchemy/pb1550/init.c)26
-rw-r--r--arch/mips/alchemy/mtx-1/board_setup.c12
-rw-r--r--arch/mips/alchemy/mtx-1/init.c2
-rw-r--r--arch/mips/alchemy/mtx-1/irqmap.c18
-rw-r--r--arch/mips/alchemy/pb1000/init.c57
-rw-r--r--arch/mips/alchemy/pb1000/irqmap.c38
-rw-r--r--arch/mips/alchemy/pb1100/init.c60
-rw-r--r--arch/mips/alchemy/pb1100/irqmap.c40
-rw-r--r--arch/mips/alchemy/pb1200/init.c58
-rw-r--r--arch/mips/alchemy/pb1500/init.c58
-rw-r--r--arch/mips/alchemy/pb1500/irqmap.c46
-rw-r--r--arch/mips/alchemy/pb1550/irqmap.c43
-rw-r--r--arch/mips/alchemy/xxs1500/board_setup.c12
-rw-r--r--arch/mips/alchemy/xxs1500/init.c2
-rw-r--r--arch/mips/alchemy/xxs1500/irqmap.c31
-rw-r--r--arch/mips/cavium-octeon/Kconfig85
-rw-r--r--arch/mips/cavium-octeon/Makefile16
-rw-r--r--arch/mips/cavium-octeon/csrc-octeon.c58
-rw-r--r--arch/mips/cavium-octeon/dma-octeon.c32
-rw-r--r--arch/mips/cavium-octeon/executive/Makefile13
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-bootmem.c586
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-l2c.c734
-rw-r--r--arch/mips/cavium-octeon/executive/cvmx-sysinfo.c116
-rw-r--r--arch/mips/cavium-octeon/executive/octeon-model.c358
-rw-r--r--arch/mips/cavium-octeon/flash_setup.c84
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c497
-rw-r--r--arch/mips/cavium-octeon/octeon-memcpy.S521
-rw-r--r--arch/mips/cavium-octeon/serial.c136
-rw-r--r--arch/mips/cavium-octeon/setup.c929
-rw-r--r--arch/mips/cavium-octeon/smp.c211
-rw-r--r--arch/mips/configs/cavium-octeon_defconfig943
-rw-r--r--arch/mips/include/asm/cpu-features.h3
-rw-r--r--arch/mips/include/asm/cpu.h14
-rw-r--r--arch/mips/include/asm/hazards.h4
-rw-r--r--arch/mips/include/asm/io.h14
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h89
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h5
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h78
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h64
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/irq.h244
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h131
-rw-r--r--arch/mips/include/asm/mach-cavium-octeon/war.h26
-rw-r--r--arch/mips/include/asm/mach-generic/dma-coherence.h26
-rw-r--r--arch/mips/include/asm/mach-ip27/dma-coherence.h26
-rw-r--r--arch/mips/include/asm/mach-ip32/dma-coherence.h26
-rw-r--r--arch/mips/include/asm/mach-jazz/dma-coherence.h26
-rw-r--r--arch/mips/include/asm/mach-lemote/dma-coherence.h26
-rw-r--r--arch/mips/include/asm/mipsregs.h22
-rw-r--r--arch/mips/include/asm/module.h2
-rw-r--r--arch/mips/include/asm/octeon/cvmx-asm.h128
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootinfo.h262
-rw-r--r--arch/mips/include/asm/octeon/cvmx-bootmem.h288
-rw-r--r--arch/mips/include/asm/octeon/cvmx-ciu-defs.h1616
-rw-r--r--arch/mips/include/asm/octeon/cvmx-gpio-defs.h219
-rw-r--r--arch/mips/include/asm/octeon/cvmx-iob-defs.h530
-rw-r--r--arch/mips/include/asm/octeon/cvmx-ipd-defs.h877
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2c-defs.h963
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2c.h325
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2d-defs.h369
-rw-r--r--arch/mips/include/asm/octeon/cvmx-l2t-defs.h141
-rw-r--r--arch/mips/include/asm/octeon/cvmx-led-defs.h240
-rw-r--r--arch/mips/include/asm/octeon/cvmx-mio-defs.h2004
-rw-r--r--arch/mips/include/asm/octeon/cvmx-packet.h61
-rw-r--r--arch/mips/include/asm/octeon/cvmx-pow-defs.h698
-rw-r--r--arch/mips/include/asm/octeon/cvmx-spinlock.h232
-rw-r--r--arch/mips/include/asm/octeon/cvmx-sysinfo.h152
-rw-r--r--arch/mips/include/asm/octeon/cvmx.h505
-rw-r--r--arch/mips/include/asm/octeon/octeon-feature.h119
-rw-r--r--arch/mips/include/asm/octeon/octeon-model.h321
-rw-r--r--arch/mips/include/asm/octeon/octeon.h248
-rw-r--r--arch/mips/include/asm/processor.h69
-rw-r--r--arch/mips/include/asm/ptrace.h4
-rw-r--r--arch/mips/include/asm/smp.h3
-rw-r--r--arch/mips/include/asm/stackframe.h17
-rw-r--r--arch/mips/include/asm/time.h24
-rw-r--r--arch/mips/kernel/Makefile5
-rw-r--r--arch/mips/kernel/asm-offsets.c31
-rw-r--r--arch/mips/kernel/branch.c33
-rw-r--r--arch/mips/kernel/cevt-r4k.c2
-rw-r--r--arch/mips/kernel/cpu-probe.c31
-rw-r--r--arch/mips/kernel/csrc-r4k.c2
-rw-r--r--arch/mips/kernel/genex.S4
-rw-r--r--arch/mips/kernel/irq.c1
-rw-r--r--arch/mips/kernel/octeon_switch.S506
-rw-r--r--arch/mips/kernel/ptrace32.c64
-rw-r--r--arch/mips/kernel/traps.c21
-rw-r--r--arch/mips/lib/Makefile1
-rw-r--r--arch/mips/mm/Makefile1
-rw-r--r--arch/mips/mm/c-octeon.c307
-rw-r--r--arch/mips/mm/cache.c6
-rw-r--r--arch/mips/mm/cex-oct.S70
-rw-r--r--arch/mips/mm/dma-default.c25
-rw-r--r--arch/mips/mm/tlb-r4k.c5
-rw-r--r--arch/mips/mm/tlbex.c1
126 files changed, 18974 insertions, 2031 deletions
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a5255e7c79e0..52c80c2a57f2 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -595,6 +595,44 @@ config WR_PPMC
595 This enables support for the Wind River MIPS32 4KC PPMC evaluation 595 This enables support for the Wind River MIPS32 4KC PPMC evaluation
596 board, which is based on GT64120 bridge chip. 596 board, which is based on GT64120 bridge chip.
597 597
598config CAVIUM_OCTEON_SIMULATOR
599 bool "Support for the Cavium Networks Octeon Simulator"
600 select CEVT_R4K
601 select 64BIT_PHYS_ADDR
602 select DMA_COHERENT
603 select SYS_SUPPORTS_64BIT_KERNEL
604 select SYS_SUPPORTS_BIG_ENDIAN
605 select SYS_SUPPORTS_HIGHMEM
606 select CPU_CAVIUM_OCTEON
607 help
608 The Octeon simulator is software performance model of the Cavium
609 Octeon Processor. It supports simulating Octeon processors on x86
610 hardware.
611
612config CAVIUM_OCTEON_REFERENCE_BOARD
613 bool "Support for the Cavium Networks Octeon reference board"
614 select CEVT_R4K
615 select 64BIT_PHYS_ADDR
616 select DMA_COHERENT
617 select SYS_SUPPORTS_64BIT_KERNEL
618 select SYS_SUPPORTS_BIG_ENDIAN
619 select SYS_SUPPORTS_HIGHMEM
620 select SYS_HAS_EARLY_PRINTK
621 select CPU_CAVIUM_OCTEON
622 select SWAP_IO_SPACE
623 help
624 This option supports all of the Octeon reference boards from Cavium
625 Networks. It builds a kernel that dynamically determines the Octeon
626 CPU type and supports all known board reference implementations.
627 Some of the supported boards are:
628 EBT3000
629 EBH3000
630 EBH3100
631 Thunder
632 Kodama
633 Hikari
634 Say Y here for most Octeon reference boards.
635
598endchoice 636endchoice
599 637
600source "arch/mips/alchemy/Kconfig" 638source "arch/mips/alchemy/Kconfig"
@@ -607,6 +645,7 @@ source "arch/mips/sgi-ip27/Kconfig"
607source "arch/mips/sibyte/Kconfig" 645source "arch/mips/sibyte/Kconfig"
608source "arch/mips/txx9/Kconfig" 646source "arch/mips/txx9/Kconfig"
609source "arch/mips/vr41xx/Kconfig" 647source "arch/mips/vr41xx/Kconfig"
648source "arch/mips/cavium-octeon/Kconfig"
610 649
611endmenu 650endmenu
612 651
@@ -682,7 +721,11 @@ config CEVT_DS1287
682config CEVT_GT641XX 721config CEVT_GT641XX
683 bool 722 bool
684 723
724config CEVT_R4K_LIB
725 bool
726
685config CEVT_R4K 727config CEVT_R4K
728 select CEVT_R4K_LIB
686 bool 729 bool
687 730
688config CEVT_SB1250 731config CEVT_SB1250
@@ -697,7 +740,11 @@ config CSRC_BCM1480
697config CSRC_IOASIC 740config CSRC_IOASIC
698 bool 741 bool
699 742
743config CSRC_R4K_LIB
744 bool
745
700config CSRC_R4K 746config CSRC_R4K
747 select CSRC_R4K_LIB
701 bool 748 bool
702 749
703config CSRC_SB1250 750config CSRC_SB1250
@@ -835,6 +882,9 @@ config IRQ_GT641XX
835config IRQ_GIC 882config IRQ_GIC
836 bool 883 bool
837 884
885config IRQ_CPU_OCTEON
886 bool
887
838config MIPS_BOARDS_GEN 888config MIPS_BOARDS_GEN
839 bool 889 bool
840 890
@@ -924,7 +974,7 @@ config BOOT_ELF32
924config MIPS_L1_CACHE_SHIFT 974config MIPS_L1_CACHE_SHIFT
925 int 975 int
926 default "4" if MACH_DECSTATION || MIKROTIK_RB532 976 default "4" if MACH_DECSTATION || MIKROTIK_RB532
927 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM 977 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON
928 default "4" if PMC_MSP4200_EVAL 978 default "4" if PMC_MSP4200_EVAL
929 default "5" 979 default "5"
930 980
@@ -1185,6 +1235,23 @@ config CPU_SB1
1185 select CPU_SUPPORTS_HIGHMEM 1235 select CPU_SUPPORTS_HIGHMEM
1186 select WEAK_ORDERING 1236 select WEAK_ORDERING
1187 1237
1238config CPU_CAVIUM_OCTEON
1239 bool "Cavium Octeon processor"
1240 select IRQ_CPU
1241 select IRQ_CPU_OCTEON
1242 select CPU_HAS_PREFETCH
1243 select CPU_SUPPORTS_64BIT_KERNEL
1244 select SYS_SUPPORTS_SMP
1245 select NR_CPUS_DEFAULT_16
1246 select WEAK_ORDERING
1247 select WEAK_REORDERING_BEYOND_LLSC
1248 select CPU_SUPPORTS_HIGHMEM
1249 help
1250 The Cavium Octeon processor is a highly integrated chip containing
1251 many ethernet hardware widgets for networking tasks. The processor
1252 can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
1253 Full details can be found at http://www.caviumnetworks.com.
1254
1188endchoice 1255endchoice
1189 1256
1190config SYS_HAS_CPU_LOONGSON2 1257config SYS_HAS_CPU_LOONGSON2
@@ -1285,7 +1352,7 @@ config CPU_MIPSR1
1285 1352
1286config CPU_MIPSR2 1353config CPU_MIPSR2
1287 bool 1354 bool
1288 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 1355 default y if CPU_MIPS32_R2 || CPU_MIPS64_R2 || CPU_CAVIUM_OCTEON
1289 1356
1290config SYS_SUPPORTS_32BIT_KERNEL 1357config SYS_SUPPORTS_32BIT_KERNEL
1291 bool 1358 bool
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 28c55f608913..21b00e95daef 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -144,6 +144,10 @@ cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \
144cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap 144cflags-$(CONFIG_CPU_R8000) += -march=r8000 -Wa,--trap
145cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \ 145cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \
146 -Wa,--trap 146 -Wa,--trap
147cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap
148ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
149cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
150endif
147 151
148cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) 152cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
149cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) 153cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
@@ -184,84 +188,84 @@ cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00
184# 188#
185# AMD Alchemy Pb1000 eval board 189# AMD Alchemy Pb1000 eval board
186# 190#
187libs-$(CONFIG_MIPS_PB1000) += arch/mips/alchemy/pb1000/ 191core-$(CONFIG_MIPS_PB1000) += arch/mips/alchemy/devboards/
188cflags-$(CONFIG_MIPS_PB1000) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 192cflags-$(CONFIG_MIPS_PB1000) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
189load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000 193load-$(CONFIG_MIPS_PB1000) += 0xffffffff80100000
190 194
191# 195#
192# AMD Alchemy Pb1100 eval board 196# AMD Alchemy Pb1100 eval board
193# 197#
194libs-$(CONFIG_MIPS_PB1100) += arch/mips/alchemy/pb1100/ 198core-$(CONFIG_MIPS_PB1100) += arch/mips/alchemy/devboards/
195cflags-$(CONFIG_MIPS_PB1100) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 199cflags-$(CONFIG_MIPS_PB1100) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
196load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000 200load-$(CONFIG_MIPS_PB1100) += 0xffffffff80100000
197 201
198# 202#
199# AMD Alchemy Pb1500 eval board 203# AMD Alchemy Pb1500 eval board
200# 204#
201libs-$(CONFIG_MIPS_PB1500) += arch/mips/alchemy/pb1500/ 205core-$(CONFIG_MIPS_PB1500) += arch/mips/alchemy/devboards/
202cflags-$(CONFIG_MIPS_PB1500) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 206cflags-$(CONFIG_MIPS_PB1500) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
203load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000 207load-$(CONFIG_MIPS_PB1500) += 0xffffffff80100000
204 208
205# 209#
206# AMD Alchemy Pb1550 eval board 210# AMD Alchemy Pb1550 eval board
207# 211#
208libs-$(CONFIG_MIPS_PB1550) += arch/mips/alchemy/pb1550/ 212core-$(CONFIG_MIPS_PB1550) += arch/mips/alchemy/devboards/
209cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 213cflags-$(CONFIG_MIPS_PB1550) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
210load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000 214load-$(CONFIG_MIPS_PB1550) += 0xffffffff80100000
211 215
212# 216#
213# AMD Alchemy Pb1200 eval board 217# AMD Alchemy Pb1200 eval board
214# 218#
215libs-$(CONFIG_MIPS_PB1200) += arch/mips/alchemy/pb1200/ 219core-$(CONFIG_MIPS_PB1200) += arch/mips/alchemy/devboards/
216cflags-$(CONFIG_MIPS_PB1200) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00 220cflags-$(CONFIG_MIPS_PB1200) += -I$(srctree)/arch/mips/include/asm/mach-pb1x00
217load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000 221load-$(CONFIG_MIPS_PB1200) += 0xffffffff80100000
218 222
219# 223#
220# AMD Alchemy Db1000 eval board 224# AMD Alchemy Db1000 eval board
221# 225#
222libs-$(CONFIG_MIPS_DB1000) += arch/mips/alchemy/db1x00/ 226core-$(CONFIG_MIPS_DB1000) += arch/mips/alchemy/devboards/
223cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 227cflags-$(CONFIG_MIPS_DB1000) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
224load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000 228load-$(CONFIG_MIPS_DB1000) += 0xffffffff80100000
225 229
226# 230#
227# AMD Alchemy Db1100 eval board 231# AMD Alchemy Db1100 eval board
228# 232#
229libs-$(CONFIG_MIPS_DB1100) += arch/mips/alchemy/db1x00/ 233core-$(CONFIG_MIPS_DB1100) += arch/mips/alchemy/devboards/
230cflags-$(CONFIG_MIPS_DB1100) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 234cflags-$(CONFIG_MIPS_DB1100) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
231load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000 235load-$(CONFIG_MIPS_DB1100) += 0xffffffff80100000
232 236
233# 237#
234# AMD Alchemy Db1500 eval board 238# AMD Alchemy Db1500 eval board
235# 239#
236libs-$(CONFIG_MIPS_DB1500) += arch/mips/alchemy/db1x00/ 240core-$(CONFIG_MIPS_DB1500) += arch/mips/alchemy/devboards/
237cflags-$(CONFIG_MIPS_DB1500) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 241cflags-$(CONFIG_MIPS_DB1500) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
238load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000 242load-$(CONFIG_MIPS_DB1500) += 0xffffffff80100000
239 243
240# 244#
241# AMD Alchemy Db1550 eval board 245# AMD Alchemy Db1550 eval board
242# 246#
243libs-$(CONFIG_MIPS_DB1550) += arch/mips/alchemy/db1x00/ 247core-$(CONFIG_MIPS_DB1550) += arch/mips/alchemy/devboards/
244cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 248cflags-$(CONFIG_MIPS_DB1550) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
245load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000 249load-$(CONFIG_MIPS_DB1550) += 0xffffffff80100000
246 250
247# 251#
248# AMD Alchemy Db1200 eval board 252# AMD Alchemy Db1200 eval board
249# 253#
250libs-$(CONFIG_MIPS_DB1200) += arch/mips/alchemy/pb1200/ 254core-$(CONFIG_MIPS_DB1200) += arch/mips/alchemy/devboards/
251cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 255cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
252load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 256load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000
253 257
254# 258#
255# AMD Alchemy Bosporus eval board 259# AMD Alchemy Bosporus eval board
256# 260#
257libs-$(CONFIG_MIPS_BOSPORUS) += arch/mips/alchemy/db1x00/ 261core-$(CONFIG_MIPS_BOSPORUS) += arch/mips/alchemy/devboards/
258cflags-$(CONFIG_MIPS_BOSPORUS) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 262cflags-$(CONFIG_MIPS_BOSPORUS) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
259load-$(CONFIG_MIPS_BOSPORUS) += 0xffffffff80100000 263load-$(CONFIG_MIPS_BOSPORUS) += 0xffffffff80100000
260 264
261# 265#
262# AMD Alchemy Mirage eval board 266# AMD Alchemy Mirage eval board
263# 267#
264libs-$(CONFIG_MIPS_MIRAGE) += arch/mips/alchemy/db1x00/ 268core-$(CONFIG_MIPS_MIRAGE) += arch/mips/alchemy/devboards/
265cflags-$(CONFIG_MIPS_MIRAGE) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 269cflags-$(CONFIG_MIPS_MIRAGE) += -I$(srctree)/arch/mips/include/asm/mach-db1x00
266load-$(CONFIG_MIPS_MIRAGE) += 0xffffffff80100000 270load-$(CONFIG_MIPS_MIRAGE) += 0xffffffff80100000
267 271
@@ -586,6 +590,18 @@ core-$(CONFIG_TOSHIBA_RBTX4927) += arch/mips/txx9/rbtx4927/
586core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/ 590core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/
587core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/ 591core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/
588 592
593#
594# Cavium Octeon
595#
596core-$(CONFIG_CPU_CAVIUM_OCTEON) += arch/mips/cavium-octeon/
597cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -I$(srctree)/arch/mips/include/asm/mach-cavium-octeon
598core-$(CONFIG_CPU_CAVIUM_OCTEON) += arch/mips/cavium-octeon/executive/
599ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
600load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff84100000
601else
602load-$(CONFIG_CPU_CAVIUM_OCTEON) += 0xffffffff81100000
603endif
604
589cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic 605cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
590drivers-$(CONFIG_PCI) += arch/mips/pci/ 606drivers-$(CONFIG_PCI) += arch/mips/pci/
591 607
diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig
index e4a057d80ab6..7f8ef13d0014 100644
--- a/arch/mips/alchemy/Kconfig
+++ b/arch/mips/alchemy/Kconfig
@@ -128,9 +128,10 @@ config SOC_AU1200
128config SOC_AU1X00 128config SOC_AU1X00
129 bool 129 bool
130 select 64BIT_PHYS_ADDR 130 select 64BIT_PHYS_ADDR
131 select CEVT_R4K 131 select CEVT_R4K_LIB
132 select CSRC_R4K 132 select CSRC_R4K_LIB
133 select IRQ_CPU 133 select IRQ_CPU
134 select SYS_HAS_CPU_MIPS32_R1 134 select SYS_HAS_CPU_MIPS32_R1
135 select SYS_SUPPORTS_32BIT_KERNEL 135 select SYS_SUPPORTS_32BIT_KERNEL
136 select SYS_SUPPORTS_APM_EMULATION 136 select SYS_SUPPORTS_APM_EMULATION
137 select GENERIC_HARDIRQS_NO__DO_IRQ
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index df48fd65bbf3..d50d4764eafe 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -6,8 +6,8 @@
6# 6#
7 7
8obj-y += prom.o irq.o puts.o time.o reset.o \ 8obj-y += prom.o irq.o puts.o time.o reset.o \
9 au1xxx_irqmap.o clocks.o platform.o power.o setup.o \ 9 clocks.o platform.o power.o setup.o \
10 sleeper.o cputable.o dma.o dbdma.o gpio.o 10 sleeper.o dma.o dbdma.o gpio.o
11 11
12obj-$(CONFIG_PCI) += pci.o 12obj-$(CONFIG_PCI) += pci.o
13 13
diff --git a/arch/mips/alchemy/common/au1xxx_irqmap.c b/arch/mips/alchemy/common/au1xxx_irqmap.c
deleted file mode 100644
index c7ca1596394c..000000000000
--- a/arch/mips/alchemy/common/au1xxx_irqmap.c
+++ /dev/null
@@ -1,205 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx processor specific IRQ tables
4 *
5 * Copyright 2004 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28#include <linux/init.h>
29#include <linux/kernel.h>
30
31#include <au1000.h>
32
33/* The IC0 interrupt table. This is processor, rather than
34 * board dependent, so no reason to keep this info in the board
35 * dependent files.
36 *
37 * Careful if you change match 2 request!
38 * The interrupt handler is called directly from the low level dispatch code.
39 */
40struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
41
42#if defined(CONFIG_SOC_AU1000)
43 { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
44 { AU1000_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
45 { AU1000_UART2_INT, INTC_INT_HIGH_LEVEL, 0 },
46 { AU1000_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
47 { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 },
48 { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 },
49 { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },
50 { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },
51 { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },
52 { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },
53 { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },
54 { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },
55 { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },
56 { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },
57 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
58 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
59 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
60 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
61 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
62 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
63 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
64 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
65 { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 },
66 { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 },
67 { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
68 { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
69 { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
70 { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
71 { AU1000_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
72 { AU1000_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
73 { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
74
75#elif defined(CONFIG_SOC_AU1500)
76
77 { AU1500_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
78 { AU1000_PCI_INTA, INTC_INT_LOW_LEVEL, 0 },
79 { AU1000_PCI_INTB, INTC_INT_LOW_LEVEL, 0 },
80 { AU1500_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
81 { AU1000_PCI_INTC, INTC_INT_LOW_LEVEL, 0 },
82 { AU1000_PCI_INTD, INTC_INT_LOW_LEVEL, 0 },
83 { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },
84 { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },
85 { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },
86 { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },
87 { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },
88 { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },
89 { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },
90 { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },
91 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
92 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
93 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
94 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
95 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
96 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
97 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
98 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
99 { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
100 { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
101 { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
102 { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
103 { AU1500_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
104 { AU1500_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
105 { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
106
107#elif defined(CONFIG_SOC_AU1100)
108
109 { AU1100_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
110 { AU1100_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
111 { AU1100_SD_INT, INTC_INT_HIGH_LEVEL, 0 },
112 { AU1100_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
113 { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 },
114 { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 },
115 { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },
116 { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },
117 { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },
118 { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },
119 { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },
120 { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },
121 { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },
122 { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },
123 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
124 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
125 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
126 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
127 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
128 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
129 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
130 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
131 { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 },
132 { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 },
133 { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
134 { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
135 { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
136 { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
137 { AU1100_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
138 /* { AU1000_GPIO215_208_INT, INTC_INT_HIGH_LEVEL, 0 }, */
139 { AU1100_LCD_INT, INTC_INT_HIGH_LEVEL, 0 },
140 { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
141
142#elif defined(CONFIG_SOC_AU1550)
143
144 { AU1550_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
145 { AU1550_PCI_INTA, INTC_INT_LOW_LEVEL, 0 },
146 { AU1550_PCI_INTB, INTC_INT_LOW_LEVEL, 0 },
147 { AU1550_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 },
148 { AU1550_CRYPTO_INT, INTC_INT_HIGH_LEVEL, 0 },
149 { AU1550_PCI_INTC, INTC_INT_LOW_LEVEL, 0 },
150 { AU1550_PCI_INTD, INTC_INT_LOW_LEVEL, 0 },
151 { AU1550_PCI_RST_INT, INTC_INT_LOW_LEVEL, 0 },
152 { AU1550_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
153 { AU1550_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
154 { AU1550_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 },
155 { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 },
156 { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0 },
157 { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0 },
158 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
159 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
160 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
161 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
162 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
163 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
164 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
165 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
166 { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0 },
167 { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
168 { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
169 { AU1550_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
170 { AU1550_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
171 { AU1550_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
172
173#elif defined(CONFIG_SOC_AU1200)
174
175 { AU1200_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
176 { AU1200_SWT_INT, INTC_INT_RISE_EDGE, 0 },
177 { AU1200_SD_INT, INTC_INT_HIGH_LEVEL, 0 },
178 { AU1200_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 },
179 { AU1200_MAE_BE_INT, INTC_INT_HIGH_LEVEL, 0 },
180 { AU1200_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
181 { AU1200_MAE_FE_INT, INTC_INT_HIGH_LEVEL, 0 },
182 { AU1200_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 },
183 { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 },
184 { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0 },
185 { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0 },
186 { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
187 { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
188 { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
189 { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
190 { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
191 { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
192 { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
193 { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
194 { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0 },
195 { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 },
196 { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0 },
197 { AU1200_MAE_BOTH_INT, INTC_INT_HIGH_LEVEL, 0 },
198
199#else
200#error "Error: Unknown Alchemy SOC"
201#endif
202
203};
204
205int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map);
diff --git a/arch/mips/alchemy/common/clocks.c b/arch/mips/alchemy/common/clocks.c
index 043429d17c5f..d8991854530e 100644
--- a/arch/mips/alchemy/common/clocks.c
+++ b/arch/mips/alchemy/common/clocks.c
@@ -27,12 +27,21 @@
27 */ 27 */
28 28
29#include <linux/module.h> 29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <asm/time.h>
30#include <asm/mach-au1x00/au1000.h> 32#include <asm/mach-au1x00/au1000.h>
31 33
34/*
35 * I haven't found anyone that doesn't use a 12 MHz source clock,
36 * but just in case.....
37 */
38#define AU1000_SRC_CLK 12000000
39
32static unsigned int au1x00_clock; /* Hz */ 40static unsigned int au1x00_clock; /* Hz */
33static unsigned int lcd_clock; /* KHz */
34static unsigned long uart_baud_base; 41static unsigned long uart_baud_base;
35 42
43static DEFINE_SPINLOCK(time_lock);
44
36/* 45/*
37 * Set the au1000_clock 46 * Set the au1000_clock
38 */ 47 */
@@ -63,31 +72,45 @@ void set_au1x00_uart_baud_base(unsigned long new_baud_base)
63} 72}
64 73
65/* 74/*
66 * Calculate the Au1x00's LCD clock based on the current 75 * We read the real processor speed from the PLL. This is important
67 * cpu clock and the system bus clock, and try to keep it 76 * because it is more accurate than computing it from the 32 KHz
68 * below 40 MHz (the Pb1000 board can lock-up if the LCD 77 * counter, if it exists. If we don't have an accurate processor
69 * clock is over 40 MHz). 78 * speed, all of the peripherals that derive their clocks based on
79 * this advertised speed will introduce error and sometimes not work
80 * properly. This function is futher convoluted to still allow configurations
81 * to do that in case they have really, really old silicon with a
82 * write-only PLL register. -- Dan
70 */ 83 */
71void set_au1x00_lcd_clock(void) 84unsigned long au1xxx_calc_clock(void)
72{ 85{
73 unsigned int static_cfg0; 86 unsigned long cpu_speed;
74 unsigned int sys_busclk = (get_au1x00_speed() / 1000) / 87 unsigned long flags;
75 ((int)(au_readl(SYS_POWERCTRL) & 0x03) + 2);
76 88
77 static_cfg0 = au_readl(MEM_STCFG0); 89 spin_lock_irqsave(&time_lock, flags);
78 90
79 if (static_cfg0 & (1 << 11)) 91 /*
80 lcd_clock = sys_busclk / 5; /* note: BCLK switching fails with D5 */ 92 * On early Au1000, sys_cpupll was write-only. Since these
93 * silicon versions of Au1000 are not sold by AMD, we don't bend
94 * over backwards trying to determine the frequency.
95 */
96 if (au1xxx_cpu_has_pll_wo())
97#ifdef CONFIG_SOC_AU1000_FREQUENCY
98 cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
99#else
100 cpu_speed = 396000000;
101#endif
81 else 102 else
82 lcd_clock = sys_busclk / 4; 103 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
83 104
84 if (lcd_clock > 50000) /* Epson MAX */ 105 /* On Alchemy CPU:counter ratio is 1:1 */
85 printk(KERN_WARNING "warning: LCD clock too high (%u KHz)\n", 106 mips_hpt_frequency = cpu_speed;
86 lcd_clock); 107 /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */
87} 108 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)
109 & 0x03) + 2) * 16));
88 110
89unsigned int get_au1x00_lcd_clock(void) 111 spin_unlock_irqrestore(&time_lock, flags);
90{ 112
91 return lcd_clock; 113 set_au1x00_speed(cpu_speed);
114
115 return cpu_speed;
92} 116}
93EXPORT_SYMBOL(get_au1x00_lcd_clock);
diff --git a/arch/mips/alchemy/common/cputable.c b/arch/mips/alchemy/common/cputable.c
deleted file mode 100644
index ba6430bc2d03..000000000000
--- a/arch/mips/alchemy/common/cputable.c
+++ /dev/null
@@ -1,52 +0,0 @@
1/*
2 * arch/mips/au1000/common/cputable.c
3 *
4 * Copyright (C) 2004 Dan Malek (dan@embeddededge.com)
5 * Copied from PowerPC and updated for Alchemy Au1xxx processors.
6 *
7 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <asm/mach-au1x00/au1000.h>
16
17struct cpu_spec *cur_cpu_spec[NR_CPUS];
18
19/* With some thought, we can probably use the mask to reduce the
20 * size of the table.
21 */
22struct cpu_spec cpu_specs[] = {
23 { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0, 1 },
24 { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0, 1 },
25 { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0, 1 },
26 { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1, 0 },
27 { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1, 0 },
28 { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1, 0 },
29 { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1, 0 },
30 { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1, 0 },
31 { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1, 0 },
32 { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1, 0 },
33 { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1, 0 },
34 { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1, 0 },
35 { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1, 0 },
36 { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1, 0 },
37 { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0, 0 },
38 { 0xffffffff, 0x04030201, "Au1200 AC", 1, 0, 0 },
39 { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 }
40};
41
42void set_cpuspec(void)
43{
44 struct cpu_spec *sp;
45 u32 prid;
46
47 prid = read_c0_prid();
48 sp = cpu_specs;
49 while ((prid & sp->prid_mask) != sp->prid_value)
50 sp++;
51 cur_cpu_spec[0] = sp;
52}
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 601ee9180ee4..3ab6d80d150d 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -174,6 +174,11 @@ static dbdev_tab_t dbdev_tab[] = {
174 174
175#define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) 175#define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab)
176 176
177#ifdef CONFIG_PM
178static u32 au1xxx_dbdma_pm_regs[NUM_DBDMA_CHANS + 1][8];
179#endif
180
181
177static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; 182static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
178 183
179static dbdev_tab_t *find_dbdev_id(u32 id) 184static dbdev_tab_t *find_dbdev_id(u32 id)
@@ -975,4 +980,64 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
975 return nbytes; 980 return nbytes;
976} 981}
977 982
983#ifdef CONFIG_PM
984void au1xxx_dbdma_suspend(void)
985{
986 int i;
987 u32 addr;
988
989 addr = DDMA_GLOBAL_BASE;
990 au1xxx_dbdma_pm_regs[0][0] = au_readl(addr + 0x00);
991 au1xxx_dbdma_pm_regs[0][1] = au_readl(addr + 0x04);
992 au1xxx_dbdma_pm_regs[0][2] = au_readl(addr + 0x08);
993 au1xxx_dbdma_pm_regs[0][3] = au_readl(addr + 0x0c);
994
995 /* save channel configurations */
996 for (i = 1, addr = DDMA_CHANNEL_BASE; i < NUM_DBDMA_CHANS; i++) {
997 au1xxx_dbdma_pm_regs[i][0] = au_readl(addr + 0x00);
998 au1xxx_dbdma_pm_regs[i][1] = au_readl(addr + 0x04);
999 au1xxx_dbdma_pm_regs[i][2] = au_readl(addr + 0x08);
1000 au1xxx_dbdma_pm_regs[i][3] = au_readl(addr + 0x0c);
1001 au1xxx_dbdma_pm_regs[i][4] = au_readl(addr + 0x10);
1002 au1xxx_dbdma_pm_regs[i][5] = au_readl(addr + 0x14);
1003 au1xxx_dbdma_pm_regs[i][6] = au_readl(addr + 0x18);
1004
1005 /* halt channel */
1006 au_writel(au1xxx_dbdma_pm_regs[i][0] & ~1, addr + 0x00);
1007 au_sync();
1008 while (!(au_readl(addr + 0x14) & 1))
1009 au_sync();
1010
1011 addr += 0x100; /* next channel base */
1012 }
1013 /* disable channel interrupts */
1014 au_writel(0, DDMA_GLOBAL_BASE + 0x0c);
1015 au_sync();
1016}
1017
1018void au1xxx_dbdma_resume(void)
1019{
1020 int i;
1021 u32 addr;
1022
1023 addr = DDMA_GLOBAL_BASE;
1024 au_writel(au1xxx_dbdma_pm_regs[0][0], addr + 0x00);
1025 au_writel(au1xxx_dbdma_pm_regs[0][1], addr + 0x04);
1026 au_writel(au1xxx_dbdma_pm_regs[0][2], addr + 0x08);
1027 au_writel(au1xxx_dbdma_pm_regs[0][3], addr + 0x0c);
1028
1029 /* restore channel configurations */
1030 for (i = 1, addr = DDMA_CHANNEL_BASE; i < NUM_DBDMA_CHANS; i++) {
1031 au_writel(au1xxx_dbdma_pm_regs[i][0], addr + 0x00);
1032 au_writel(au1xxx_dbdma_pm_regs[i][1], addr + 0x04);
1033 au_writel(au1xxx_dbdma_pm_regs[i][2], addr + 0x08);
1034 au_writel(au1xxx_dbdma_pm_regs[i][3], addr + 0x0c);
1035 au_writel(au1xxx_dbdma_pm_regs[i][4], addr + 0x10);
1036 au_writel(au1xxx_dbdma_pm_regs[i][5], addr + 0x14);
1037 au_writel(au1xxx_dbdma_pm_regs[i][6], addr + 0x18);
1038 au_sync();
1039 addr += 0x100; /* next channel base */
1040 }
1041}
1042#endif /* CONFIG_PM */
978#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ 1043#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 40c6ceceb5f9..c88c821b4c36 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -24,6 +24,7 @@
24 * with this program; if not, write to the Free Software Foundation, Inc., 24 * with this program; if not, write to the Free Software Foundation, Inc.,
25 * 675 Mass Ave, Cambridge, MA 02139, USA. 25 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 */ 26 */
27
27#include <linux/bitops.h> 28#include <linux/bitops.h>
28#include <linux/init.h> 29#include <linux/init.h>
29#include <linux/interrupt.h> 30#include <linux/interrupt.h>
@@ -36,15 +37,172 @@
36#include <asm/mach-pb1x00/pb1000.h> 37#include <asm/mach-pb1x00/pb1000.h>
37#endif 38#endif
38 39
39#define EXT_INTC0_REQ0 2 /* IP 2 */ 40static int au1x_ic_settype(unsigned int irq, unsigned int flow_type);
40#define EXT_INTC0_REQ1 3 /* IP 3 */ 41
41#define EXT_INTC1_REQ0 4 /* IP 4 */ 42/* per-processor fixed function irqs */
42#define EXT_INTC1_REQ1 5 /* IP 5 */ 43struct au1xxx_irqmap au1xxx_ic0_map[] __initdata = {
43#define MIPS_TIMER_IP 7 /* IP 7 */ 44
44 45#if defined(CONFIG_SOC_AU1000)
45void (*board_init_irq)(void) __initdata = NULL; 46 { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
47 { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
48 { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
49 { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
50 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
51 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
52 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
53 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
54 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
55 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
56 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
57 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
58 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
59 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
60 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
61 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
62 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
63 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
64 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
65 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
66 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
67 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
68 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
69 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
70 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
71 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
72 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
73 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
74 { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
75 { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
76 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
77
78#elif defined(CONFIG_SOC_AU1500)
79
80 { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
81 { AU1000_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
82 { AU1000_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
83 { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
84 { AU1000_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
85 { AU1000_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
86 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
87 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
88 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
89 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
90 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
91 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
92 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
93 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
94 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
95 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
96 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
97 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
98 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
99 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
100 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
101 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
102 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
103 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
104 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
105 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
106 { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
107 { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
108 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
109
110#elif defined(CONFIG_SOC_AU1100)
111
112 { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
113 { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
114 { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
115 { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
116 { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
117 { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
118 { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 },
119 { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 },
120 { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 },
121 { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 },
122 { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 },
123 { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 },
124 { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 },
125 { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 },
126 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
127 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
128 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
129 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
130 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
131 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
132 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
133 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
134 { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
135 { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
136 { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
137 { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
138 { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
139 { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 },
140 { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
141 { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
142 { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 },
143
144#elif defined(CONFIG_SOC_AU1550)
145
146 { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
147 { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 },
148 { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 },
149 { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
150 { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
151 { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 },
152 { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 },
153 { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
154 { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
155 { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
156 { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
157 { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
158 { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
159 { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
160 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
161 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
162 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
163 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
164 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
165 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
166 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
167 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
168 { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
169 { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
170 { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
171 { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 },
172 { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
173 { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
174
175#elif defined(CONFIG_SOC_AU1200)
176
177 { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
178 { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 },
179 { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
180 { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
181 { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
182 { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
183 { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
184 { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
185 { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
186 { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
187 { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
188 { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 },
189 { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
190 { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
191 { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 },
192 { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 },
193 { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 },
194 { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 },
195 { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 },
196 { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 },
197 { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
198 { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
199 { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 },
200
201#else
202#error "Error: Unknown Alchemy SOC"
203#endif
204};
46 205
47static DEFINE_SPINLOCK(irq_lock);
48 206
49#ifdef CONFIG_PM 207#ifdef CONFIG_PM
50 208
@@ -130,67 +288,47 @@ void restore_au1xxx_intctl(void)
130#endif /* CONFIG_PM */ 288#endif /* CONFIG_PM */
131 289
132 290
133inline void local_enable_irq(unsigned int irq_nr) 291static void au1x_ic0_unmask(unsigned int irq_nr)
134{ 292{
135 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 293 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
136 294 au_writel(1 << bit, IC0_MASKSET);
137 if (bit >= 32) { 295 au_writel(1 << bit, IC0_WAKESET);
138 au_writel(1 << (bit - 32), IC1_MASKSET);
139 au_writel(1 << (bit - 32), IC1_WAKESET);
140 } else {
141 au_writel(1 << bit, IC0_MASKSET);
142 au_writel(1 << bit, IC0_WAKESET);
143 }
144 au_sync(); 296 au_sync();
145} 297}
146 298
147 299static void au1x_ic1_unmask(unsigned int irq_nr)
148inline void local_disable_irq(unsigned int irq_nr)
149{ 300{
150 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 301 unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
302 au_writel(1 << bit, IC1_MASKSET);
303 au_writel(1 << bit, IC1_WAKESET);
151 304
152 if (bit >= 32) { 305/* very hacky. does the pb1000 cpld auto-disable this int?
153 au_writel(1 << (bit - 32), IC1_MASKCLR); 306 * nowhere in the current kernel sources is it disabled. --mlau
154 au_writel(1 << (bit - 32), IC1_WAKECLR); 307 */
155 } else { 308#if defined(CONFIG_MIPS_PB1000)
156 au_writel(1 << bit, IC0_MASKCLR); 309 if (irq_nr == AU1000_GPIO_15)
157 au_writel(1 << bit, IC0_WAKECLR); 310 au_writel(0x4000, PB1000_MDR); /* enable int */
158 } 311#endif
159 au_sync(); 312 au_sync();
160} 313}
161 314
162 315static void au1x_ic0_mask(unsigned int irq_nr)
163static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
164{ 316{
165 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 317 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
166 318 au_writel(1 << bit, IC0_MASKCLR);
167 if (bit >= 32) { 319 au_writel(1 << bit, IC0_WAKECLR);
168 au_writel(1 << (bit - 32), IC1_RISINGCLR);
169 au_writel(1 << (bit - 32), IC1_MASKCLR);
170 } else {
171 au_writel(1 << bit, IC0_RISINGCLR);
172 au_writel(1 << bit, IC0_MASKCLR);
173 }
174 au_sync(); 320 au_sync();
175} 321}
176 322
177 323static void au1x_ic1_mask(unsigned int irq_nr)
178static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
179{ 324{
180 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 325 unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
181 326 au_writel(1 << bit, IC1_MASKCLR);
182 if (bit >= 32) { 327 au_writel(1 << bit, IC1_WAKECLR);
183 au_writel(1 << (bit - 32), IC1_FALLINGCLR);
184 au_writel(1 << (bit - 32), IC1_MASKCLR);
185 } else {
186 au_writel(1 << bit, IC0_FALLINGCLR);
187 au_writel(1 << bit, IC0_MASKCLR);
188 }
189 au_sync(); 328 au_sync();
190} 329}
191 330
192 331static void au1x_ic0_ack(unsigned int irq_nr)
193static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
194{ 332{
195 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 333 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
196 334
@@ -198,349 +336,229 @@ static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
198 * This may assume that we don't get interrupts from 336 * This may assume that we don't get interrupts from
199 * both edges at once, or if we do, that we don't care. 337 * both edges at once, or if we do, that we don't care.
200 */ 338 */
201 if (bit >= 32) { 339 au_writel(1 << bit, IC0_FALLINGCLR);
202 au_writel(1 << (bit - 32), IC1_FALLINGCLR); 340 au_writel(1 << bit, IC0_RISINGCLR);
203 au_writel(1 << (bit - 32), IC1_RISINGCLR);
204 au_writel(1 << (bit - 32), IC1_MASKCLR);
205 } else {
206 au_writel(1 << bit, IC0_FALLINGCLR);
207 au_writel(1 << bit, IC0_RISINGCLR);
208 au_writel(1 << bit, IC0_MASKCLR);
209 }
210 au_sync(); 341 au_sync();
211} 342}
212 343
213static inline void mask_and_ack_level_irq(unsigned int irq_nr) 344static void au1x_ic1_ack(unsigned int irq_nr)
214{ 345{
215 local_disable_irq(irq_nr); 346 unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
216 au_sync();
217#if defined(CONFIG_MIPS_PB1000)
218 if (irq_nr == AU1000_GPIO_15) {
219 au_writel(0x8000, PB1000_MDR); /* ack int */
220 au_sync();
221 }
222#endif
223}
224
225static void end_irq(unsigned int irq_nr)
226{
227 if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
228 local_enable_irq(irq_nr);
229 347
230#if defined(CONFIG_MIPS_PB1000) 348 /*
231 if (irq_nr == AU1000_GPIO_15) { 349 * This may assume that we don't get interrupts from
232 au_writel(0x4000, PB1000_MDR); /* enable int */ 350 * both edges at once, or if we do, that we don't care.
233 au_sync(); 351 */
234 } 352 au_writel(1 << bit, IC1_FALLINGCLR);
235#endif 353 au_writel(1 << bit, IC1_RISINGCLR);
354 au_sync();
236} 355}
237 356
238unsigned long save_local_and_disable(int controller) 357static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
239{ 358{
240 int i; 359 unsigned int bit = irq - AU1000_INTC1_INT_BASE;
241 unsigned long flags, mask; 360 unsigned long wakemsk, flags;
242
243 spin_lock_irqsave(&irq_lock, flags);
244 if (controller) {
245 mask = au_readl(IC1_MASKSET);
246 for (i = 32; i < 64; i++)
247 local_disable_irq(i);
248 } else {
249 mask = au_readl(IC0_MASKSET);
250 for (i = 0; i < 32; i++)
251 local_disable_irq(i);
252 }
253 spin_unlock_irqrestore(&irq_lock, flags);
254
255 return mask;
256}
257 361
258void restore_local_and_enable(int controller, unsigned long mask) 362 /* only GPIO 0-7 can act as wakeup source: */
259{ 363 if ((irq < AU1000_GPIO_0) || (irq > AU1000_GPIO_7))
260 int i; 364 return -EINVAL;
261 unsigned long flags, new_mask;
262
263 spin_lock_irqsave(&irq_lock, flags);
264 for (i = 0; i < 32; i++)
265 if (mask & (1 << i)) {
266 if (controller)
267 local_enable_irq(i + 32);
268 else
269 local_enable_irq(i);
270 }
271 365
272 if (controller) 366 local_irq_save(flags);
273 new_mask = au_readl(IC1_MASKSET); 367 wakemsk = au_readl(SYS_WAKEMSK);
368 if (on)
369 wakemsk |= 1 << bit;
274 else 370 else
275 new_mask = au_readl(IC0_MASKSET); 371 wakemsk &= ~(1 << bit);
372 au_writel(wakemsk, SYS_WAKEMSK);
373 au_sync();
374 local_irq_restore(flags);
276 375
277 spin_unlock_irqrestore(&irq_lock, flags); 376 return 0;
278} 377}
279 378
280 379/*
281static struct irq_chip rise_edge_irq_type = { 380 * irq_chips for both ICs; this way the mask handlers can be
282 .name = "Au1000 Rise Edge", 381 * as short as possible.
283 .ack = mask_and_ack_rise_edge_irq, 382 *
284 .mask = local_disable_irq, 383 * NOTE: the ->ack() callback is used by the handle_edge_irq
285 .mask_ack = mask_and_ack_rise_edge_irq, 384 * flowhandler only, the ->mask_ack() one by handle_level_irq,
286 .unmask = local_enable_irq, 385 * so no need for an irq_chip for each type of irq (level/edge).
287 .end = end_irq, 386 */
288}; 387static struct irq_chip au1x_ic0_chip = {
289 388 .name = "Alchemy-IC0",
290static struct irq_chip fall_edge_irq_type = { 389 .ack = au1x_ic0_ack, /* edge */
291 .name = "Au1000 Fall Edge", 390 .mask = au1x_ic0_mask,
292 .ack = mask_and_ack_fall_edge_irq, 391 .mask_ack = au1x_ic0_mask, /* level */
293 .mask = local_disable_irq, 392 .unmask = au1x_ic0_unmask,
294 .mask_ack = mask_and_ack_fall_edge_irq, 393 .set_type = au1x_ic_settype,
295 .unmask = local_enable_irq,
296 .end = end_irq,
297};
298
299static struct irq_chip either_edge_irq_type = {
300 .name = "Au1000 Rise or Fall Edge",
301 .ack = mask_and_ack_either_edge_irq,
302 .mask = local_disable_irq,
303 .mask_ack = mask_and_ack_either_edge_irq,
304 .unmask = local_enable_irq,
305 .end = end_irq,
306}; 394};
307 395
308static struct irq_chip level_irq_type = { 396static struct irq_chip au1x_ic1_chip = {
309 .name = "Au1000 Level", 397 .name = "Alchemy-IC1",
310 .ack = mask_and_ack_level_irq, 398 .ack = au1x_ic1_ack, /* edge */
311 .mask = local_disable_irq, 399 .mask = au1x_ic1_mask,
312 .mask_ack = mask_and_ack_level_irq, 400 .mask_ack = au1x_ic1_mask, /* level */
313 .unmask = local_enable_irq, 401 .unmask = au1x_ic1_unmask,
314 .end = end_irq, 402 .set_type = au1x_ic_settype,
403 .set_wake = au1x_ic1_setwake,
315}; 404};
316 405
317static void __init setup_local_irq(unsigned int irq_nr, int type, int int_req) 406static int au1x_ic_settype(unsigned int irq, unsigned int flow_type)
318{ 407{
319 unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; 408 struct irq_chip *chip;
320 409 unsigned long icr[6];
321 if (irq_nr > AU1000_MAX_INTR) 410 unsigned int bit, ic;
322 return; 411 int ret;
323 412
324 /* Config2[n], Config1[n], Config0[n] */ 413 if (irq >= AU1000_INTC1_INT_BASE) {
325 if (bit >= 32) { 414 bit = irq - AU1000_INTC1_INT_BASE;
326 switch (type) { 415 chip = &au1x_ic1_chip;
327 case INTC_INT_RISE_EDGE: /* 0:0:1 */ 416 ic = 1;
328 au_writel(1 << (bit - 32), IC1_CFG2CLR);
329 au_writel(1 << (bit - 32), IC1_CFG1CLR);
330 au_writel(1 << (bit - 32), IC1_CFG0SET);
331 set_irq_chip(irq_nr, &rise_edge_irq_type);
332 break;
333 case INTC_INT_FALL_EDGE: /* 0:1:0 */
334 au_writel(1 << (bit - 32), IC1_CFG2CLR);
335 au_writel(1 << (bit - 32), IC1_CFG1SET);
336 au_writel(1 << (bit - 32), IC1_CFG0CLR);
337 set_irq_chip(irq_nr, &fall_edge_irq_type);
338 break;
339 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
340 au_writel(1 << (bit - 32), IC1_CFG2CLR);
341 au_writel(1 << (bit - 32), IC1_CFG1SET);
342 au_writel(1 << (bit - 32), IC1_CFG0SET);
343 set_irq_chip(irq_nr, &either_edge_irq_type);
344 break;
345 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
346 au_writel(1 << (bit - 32), IC1_CFG2SET);
347 au_writel(1 << (bit - 32), IC1_CFG1CLR);
348 au_writel(1 << (bit - 32), IC1_CFG0SET);
349 set_irq_chip(irq_nr, &level_irq_type);
350 break;
351 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
352 au_writel(1 << (bit - 32), IC1_CFG2SET);
353 au_writel(1 << (bit - 32), IC1_CFG1SET);
354 au_writel(1 << (bit - 32), IC1_CFG0CLR);
355 set_irq_chip(irq_nr, &level_irq_type);
356 break;
357 case INTC_INT_DISABLED: /* 0:0:0 */
358 au_writel(1 << (bit - 32), IC1_CFG0CLR);
359 au_writel(1 << (bit - 32), IC1_CFG1CLR);
360 au_writel(1 << (bit - 32), IC1_CFG2CLR);
361 break;
362 default: /* disable the interrupt */
363 printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
364 type, irq_nr);
365 au_writel(1 << (bit - 32), IC1_CFG0CLR);
366 au_writel(1 << (bit - 32), IC1_CFG1CLR);
367 au_writel(1 << (bit - 32), IC1_CFG2CLR);
368 return;
369 }
370 if (int_req) /* assign to interrupt request 1 */
371 au_writel(1 << (bit - 32), IC1_ASSIGNCLR);
372 else /* assign to interrupt request 0 */
373 au_writel(1 << (bit - 32), IC1_ASSIGNSET);
374 au_writel(1 << (bit - 32), IC1_SRCSET);
375 au_writel(1 << (bit - 32), IC1_MASKCLR);
376 au_writel(1 << (bit - 32), IC1_WAKECLR);
377 } else { 417 } else {
378 switch (type) { 418 bit = irq - AU1000_INTC0_INT_BASE;
379 case INTC_INT_RISE_EDGE: /* 0:0:1 */ 419 chip = &au1x_ic0_chip;
380 au_writel(1 << bit, IC0_CFG2CLR); 420 ic = 0;
381 au_writel(1 << bit, IC0_CFG1CLR); 421 }
382 au_writel(1 << bit, IC0_CFG0SET); 422
383 set_irq_chip(irq_nr, &rise_edge_irq_type); 423 if (bit > 31)
384 break; 424 return -EINVAL;
385 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 425
386 au_writel(1 << bit, IC0_CFG2CLR); 426 icr[0] = ic ? IC1_CFG0SET : IC0_CFG0SET;
387 au_writel(1 << bit, IC0_CFG1SET); 427 icr[1] = ic ? IC1_CFG1SET : IC0_CFG1SET;
388 au_writel(1 << bit, IC0_CFG0CLR); 428 icr[2] = ic ? IC1_CFG2SET : IC0_CFG2SET;
389 set_irq_chip(irq_nr, &fall_edge_irq_type); 429 icr[3] = ic ? IC1_CFG0CLR : IC0_CFG0CLR;
390 break; 430 icr[4] = ic ? IC1_CFG1CLR : IC0_CFG1CLR;
391 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 431 icr[5] = ic ? IC1_CFG2CLR : IC0_CFG2CLR;
392 au_writel(1 << bit, IC0_CFG2CLR); 432
393 au_writel(1 << bit, IC0_CFG1SET); 433 ret = 0;
394 au_writel(1 << bit, IC0_CFG0SET); 434
395 set_irq_chip(irq_nr, &either_edge_irq_type); 435 switch (flow_type) { /* cfgregs 2:1:0 */
396 break; 436 case IRQ_TYPE_EDGE_RISING: /* 0:0:1 */
397 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 437 au_writel(1 << bit, icr[5]);
398 au_writel(1 << bit, IC0_CFG2SET); 438 au_writel(1 << bit, icr[4]);
399 au_writel(1 << bit, IC0_CFG1CLR); 439 au_writel(1 << bit, icr[0]);
400 au_writel(1 << bit, IC0_CFG0SET); 440 set_irq_chip_and_handler_name(irq, chip,
401 set_irq_chip(irq_nr, &level_irq_type); 441 handle_edge_irq, "riseedge");
402 break; 442 break;
403 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 443 case IRQ_TYPE_EDGE_FALLING: /* 0:1:0 */
404 au_writel(1 << bit, IC0_CFG2SET); 444 au_writel(1 << bit, icr[5]);
405 au_writel(1 << bit, IC0_CFG1SET); 445 au_writel(1 << bit, icr[1]);
406 au_writel(1 << bit, IC0_CFG0CLR); 446 au_writel(1 << bit, icr[3]);
407 set_irq_chip(irq_nr, &level_irq_type); 447 set_irq_chip_and_handler_name(irq, chip,
408 break; 448 handle_edge_irq, "falledge");
409 case INTC_INT_DISABLED: /* 0:0:0 */ 449 break;
410 au_writel(1 << bit, IC0_CFG0CLR); 450 case IRQ_TYPE_EDGE_BOTH: /* 0:1:1 */
411 au_writel(1 << bit, IC0_CFG1CLR); 451 au_writel(1 << bit, icr[5]);
412 au_writel(1 << bit, IC0_CFG2CLR); 452 au_writel(1 << bit, icr[1]);
413 break; 453 au_writel(1 << bit, icr[0]);
414 default: /* disable the interrupt */ 454 set_irq_chip_and_handler_name(irq, chip,
415 printk(KERN_WARNING "unexpected int type %d (irq %d)\n", 455 handle_edge_irq, "bothedge");
416 type, irq_nr); 456 break;
417 au_writel(1 << bit, IC0_CFG0CLR); 457 case IRQ_TYPE_LEVEL_HIGH: /* 1:0:1 */
418 au_writel(1 << bit, IC0_CFG1CLR); 458 au_writel(1 << bit, icr[2]);
419 au_writel(1 << bit, IC0_CFG2CLR); 459 au_writel(1 << bit, icr[4]);
420 return; 460 au_writel(1 << bit, icr[0]);
421 } 461 set_irq_chip_and_handler_name(irq, chip,
422 if (int_req) /* assign to interrupt request 1 */ 462 handle_level_irq, "hilevel");
423 au_writel(1 << bit, IC0_ASSIGNCLR); 463 break;
424 else /* assign to interrupt request 0 */ 464 case IRQ_TYPE_LEVEL_LOW: /* 1:1:0 */
425 au_writel(1 << bit, IC0_ASSIGNSET); 465 au_writel(1 << bit, icr[2]);
426 au_writel(1 << bit, IC0_SRCSET); 466 au_writel(1 << bit, icr[1]);
427 au_writel(1 << bit, IC0_MASKCLR); 467 au_writel(1 << bit, icr[3]);
428 au_writel(1 << bit, IC0_WAKECLR); 468 set_irq_chip_and_handler_name(irq, chip,
469 handle_level_irq, "lowlevel");
470 break;
471 case IRQ_TYPE_NONE: /* 0:0:0 */
472 au_writel(1 << bit, icr[5]);
473 au_writel(1 << bit, icr[4]);
474 au_writel(1 << bit, icr[3]);
475 /* set at least chip so we can call set_irq_type() on it */
476 set_irq_chip(irq, chip);
477 break;
478 default:
479 ret = -EINVAL;
429 } 480 }
430 au_sync(); 481 au_sync();
431}
432 482
433/* 483 return ret;
434 * Interrupts are nested. Even if an interrupt handler is registered 484}
435 * as "fast", we might get another interrupt before we return from
436 * intcX_reqX_irqdispatch().
437 */
438 485
439static void intc0_req0_irqdispatch(void) 486asmlinkage void plat_irq_dispatch(void)
440{ 487{
441 static unsigned long intc0_req0; 488 unsigned int pending = read_c0_status() & read_c0_cause();
442 unsigned int bit; 489 unsigned long s, off, bit;
443
444 intc0_req0 |= au_readl(IC0_REQ0INT);
445 490
446 if (!intc0_req0) 491 if (pending & CAUSEF_IP7) {
492 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
447 return; 493 return;
448 494 } else if (pending & CAUSEF_IP2) {
495 s = IC0_REQ0INT;
496 off = AU1000_INTC0_INT_BASE;
497 } else if (pending & CAUSEF_IP3) {
498 s = IC0_REQ1INT;
499 off = AU1000_INTC0_INT_BASE;
500 } else if (pending & CAUSEF_IP4) {
501 s = IC1_REQ0INT;
502 off = AU1000_INTC1_INT_BASE;
503 } else if (pending & CAUSEF_IP5) {
504 s = IC1_REQ1INT;
505 off = AU1000_INTC1_INT_BASE;
506 } else
507 goto spurious;
508
509 bit = 0;
510 s = au_readl(s);
511 if (unlikely(!s)) {
512spurious:
513 spurious_interrupt();
514 return;
515 }
449#ifdef AU1000_USB_DEV_REQ_INT 516#ifdef AU1000_USB_DEV_REQ_INT
450 /* 517 /*
451 * Because of the tight timing of SETUP token to reply 518 * Because of the tight timing of SETUP token to reply
452 * transactions, the USB devices-side packet complete 519 * transactions, the USB devices-side packet complete
453 * interrupt needs the highest priority. 520 * interrupt needs the highest priority.
454 */ 521 */
455 if ((intc0_req0 & (1 << AU1000_USB_DEV_REQ_INT))) { 522 bit = 1 << (AU1000_USB_DEV_REQ_INT - AU1000_INTC0_INT_BASE);
456 intc0_req0 &= ~(1 << AU1000_USB_DEV_REQ_INT); 523 if ((pending & CAUSEF_IP2) && (s & bit)) {
457 do_IRQ(AU1000_USB_DEV_REQ_INT); 524 do_IRQ(AU1000_USB_DEV_REQ_INT);
458 return; 525 return;
459 } 526 }
460#endif 527#endif
461 bit = __ffs(intc0_req0); 528 do_IRQ(__ffs(s) + off);
462 intc0_req0 &= ~(1 << bit);
463 do_IRQ(AU1000_INTC0_INT_BASE + bit);
464} 529}
465 530
466 531/* setup edge/level and assign request 0/1 */
467static void intc0_req1_irqdispatch(void) 532void __init au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count)
468{
469 static unsigned long intc0_req1;
470 unsigned int bit;
471
472 intc0_req1 |= au_readl(IC0_REQ1INT);
473
474 if (!intc0_req1)
475 return;
476
477 bit = __ffs(intc0_req1);
478 intc0_req1 &= ~(1 << bit);
479 do_IRQ(AU1000_INTC0_INT_BASE + bit);
480}
481
482
483/*
484 * Interrupt Controller 1:
485 * interrupts 32 - 63
486 */
487static void intc1_req0_irqdispatch(void)
488{ 533{
489 static unsigned long intc1_req0; 534 unsigned int bit, irq_nr;
490 unsigned int bit; 535
491 536 while (count--) {
492 intc1_req0 |= au_readl(IC1_REQ0INT); 537 irq_nr = map[count].im_irq;
493 538
494 if (!intc1_req0) 539 if (((irq_nr < AU1000_INTC0_INT_BASE) ||
495 return; 540 (irq_nr >= AU1000_INTC0_INT_BASE + 32)) &&
496 541 ((irq_nr < AU1000_INTC1_INT_BASE) ||
497 bit = __ffs(intc1_req0); 542 (irq_nr >= AU1000_INTC1_INT_BASE + 32)))
498 intc1_req0 &= ~(1 << bit); 543 continue;
499 do_IRQ(AU1000_INTC1_INT_BASE + bit); 544
500} 545 if (irq_nr >= AU1000_INTC1_INT_BASE) {
501 546 bit = irq_nr - AU1000_INTC1_INT_BASE;
502 547 if (map[count].im_request)
503static void intc1_req1_irqdispatch(void) 548 au_writel(1 << bit, IC1_ASSIGNCLR);
504{ 549 } else {
505 static unsigned long intc1_req1; 550 bit = irq_nr - AU1000_INTC0_INT_BASE;
506 unsigned int bit; 551 if (map[count].im_request)
507 552 au_writel(1 << bit, IC0_ASSIGNCLR);
508 intc1_req1 |= au_readl(IC1_REQ1INT); 553 }
509
510 if (!intc1_req1)
511 return;
512
513 bit = __ffs(intc1_req1);
514 intc1_req1 &= ~(1 << bit);
515 do_IRQ(AU1000_INTC1_INT_BASE + bit);
516}
517
518asmlinkage void plat_irq_dispatch(void)
519{
520 unsigned int pending = read_c0_status() & read_c0_cause();
521 554
522 if (pending & CAUSEF_IP7) 555 au1x_ic_settype(irq_nr, map[count].im_type);
523 do_IRQ(MIPS_CPU_IRQ_BASE + 7); 556 }
524 else if (pending & CAUSEF_IP2)
525 intc0_req0_irqdispatch();
526 else if (pending & CAUSEF_IP3)
527 intc0_req1_irqdispatch();
528 else if (pending & CAUSEF_IP4)
529 intc1_req0_irqdispatch();
530 else if (pending & CAUSEF_IP5)
531 intc1_req1_irqdispatch();
532 else
533 spurious_interrupt();
534} 557}
535 558
536void __init arch_init_irq(void) 559void __init arch_init_irq(void)
537{ 560{
538 int i; 561 int i;
539 struct au1xxx_irqmap *imp;
540 extern struct au1xxx_irqmap au1xxx_irq_map[];
541 extern struct au1xxx_irqmap au1xxx_ic0_map[];
542 extern int au1xxx_nr_irqs;
543 extern int au1xxx_ic0_nr_irqs;
544 562
545 /* 563 /*
546 * Initialize interrupt controllers to a safe state. 564 * Initialize interrupt controllers to a safe state.
@@ -569,28 +587,25 @@ void __init arch_init_irq(void)
569 587
570 mips_cpu_irq_init(); 588 mips_cpu_irq_init();
571 589
572 /* 590 /* register all 64 possible IC0+IC1 irq sources as type "none".
573 * Initialize IC0, which is fixed per processor. 591 * Use set_irq_type() to set edge/level behaviour at runtime.
574 */ 592 */
575 imp = au1xxx_ic0_map; 593 for (i = AU1000_INTC0_INT_BASE;
576 for (i = 0; i < au1xxx_ic0_nr_irqs; i++) { 594 (i < AU1000_INTC0_INT_BASE + 32); i++)
577 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request); 595 au1x_ic_settype(i, IRQ_TYPE_NONE);
578 imp++; 596
579 } 597 for (i = AU1000_INTC1_INT_BASE;
598 (i < AU1000_INTC1_INT_BASE + 32); i++)
599 au1x_ic_settype(i, IRQ_TYPE_NONE);
580 600
581 /* 601 /*
582 * Now set up the irq mapping for the board. 602 * Initialize IC0, which is fixed per processor.
583 */ 603 */
584 imp = au1xxx_irq_map; 604 au1xxx_setup_irqmap(au1xxx_ic0_map, ARRAY_SIZE(au1xxx_ic0_map));
585 for (i = 0; i < au1xxx_nr_irqs; i++) {
586 setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
587 imp++;
588 }
589
590 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4);
591 605
592 /* Board specific IRQ initialization. 606 /* Boards can register additional (GPIO-based) IRQs.
593 */ 607 */
594 if (board_init_irq) 608 board_init_irq();
595 board_init_irq(); 609
610 set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);
596} 611}
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index bd854a6d1d89..6ab7b42aa1be 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -35,25 +35,12 @@
35#include <linux/jiffies.h> 35#include <linux/jiffies.h>
36 36
37#include <asm/uaccess.h> 37#include <asm/uaccess.h>
38#include <asm/cacheflush.h>
39#include <asm/mach-au1x00/au1000.h> 38#include <asm/mach-au1x00/au1000.h>
40 39#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
41#ifdef CONFIG_PM 40#include <asm/mach-au1x00/au1xxx_dbdma.h>
42
43#define DEBUG 1
44#ifdef DEBUG
45#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__, ## args)
46#else
47#define DPRINTK(fmt, args...)
48#endif 41#endif
49 42
50static void au1000_calibrate_delay(void); 43#ifdef CONFIG_PM
51
52extern unsigned long save_local_and_disable(int controller);
53extern void restore_local_and_enable(int controller, unsigned long mask);
54extern void local_enable_irq(unsigned int irq_nr);
55
56static DEFINE_SPINLOCK(pm_lock);
57 44
58/* 45/*
59 * We need to save/restore a bunch of core registers that are 46 * We need to save/restore a bunch of core registers that are
@@ -65,29 +52,16 @@ static DEFINE_SPINLOCK(pm_lock);
65 * We only have to save/restore registers that aren't otherwise 52 * We only have to save/restore registers that aren't otherwise
66 * done as part of a driver pm_* function. 53 * done as part of a driver pm_* function.
67 */ 54 */
68static unsigned int sleep_aux_pll_cntrl; 55static unsigned int sleep_uart0_inten;
69static unsigned int sleep_cpu_pll_cntrl; 56static unsigned int sleep_uart0_fifoctl;
70static unsigned int sleep_pin_function; 57static unsigned int sleep_uart0_linectl;
71static unsigned int sleep_uart0_inten; 58static unsigned int sleep_uart0_clkdiv;
72static unsigned int sleep_uart0_fifoctl; 59static unsigned int sleep_uart0_enable;
73static unsigned int sleep_uart0_linectl; 60static unsigned int sleep_usb[2];
74static unsigned int sleep_uart0_clkdiv; 61static unsigned int sleep_sys_clocks[5];
75static unsigned int sleep_uart0_enable; 62static unsigned int sleep_sys_pinfunc;
76static unsigned int sleep_usbhost_enable; 63static unsigned int sleep_static_memctlr[4][3];
77static unsigned int sleep_usbdev_enable;
78static unsigned int sleep_static_memctlr[4][3];
79 64
80/*
81 * Define this to cause the value you write to /proc/sys/pm/sleep to
82 * set the TOY timer for the amount of time you want to sleep.
83 * This is done mainly for testing, but may be useful in other cases.
84 * The value is number of 32KHz ticks to sleep.
85 */
86#define SLEEP_TEST_TIMEOUT 1
87#ifdef SLEEP_TEST_TIMEOUT
88static int sleep_ticks;
89void wakeup_counter0_set(int ticks);
90#endif
91 65
92static void save_core_regs(void) 66static void save_core_regs(void)
93{ 67{
@@ -105,31 +79,45 @@ static void save_core_regs(void)
105 sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR); 79 sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR);
106 sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK); 80 sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK);
107 sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL); 81 sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL);
82 au_sync();
108 83
84#ifndef CONFIG_SOC_AU1200
109 /* Shutdown USB host/device. */ 85 /* Shutdown USB host/device. */
110 sleep_usbhost_enable = au_readl(USB_HOST_CONFIG); 86 sleep_usb[0] = au_readl(USB_HOST_CONFIG);
111 87
112 /* There appears to be some undocumented reset register.... */ 88 /* There appears to be some undocumented reset register.... */
113 au_writel(0, 0xb0100004); au_sync(); 89 au_writel(0, 0xb0100004);
114 au_writel(0, USB_HOST_CONFIG); au_sync(); 90 au_sync();
91 au_writel(0, USB_HOST_CONFIG);
92 au_sync();
115 93
116 sleep_usbdev_enable = au_readl(USBD_ENABLE); 94 sleep_usb[1] = au_readl(USBD_ENABLE);
117 au_writel(0, USBD_ENABLE); au_sync(); 95 au_writel(0, USBD_ENABLE);
96 au_sync();
97
98#else /* AU1200 */
99
100 /* enable access to OTG mmio so we can save OTG CAP/MUX.
101 * FIXME: write an OTG driver and move this stuff there!
102 */
103 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
104 au_sync();
105 sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */
106 sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */
107#endif
118 108
119 /* Save interrupt controller state. */ 109 /* Save interrupt controller state. */
120 save_au1xxx_intctl(); 110 save_au1xxx_intctl();
121 111
122 /* Clocks and PLLs. */ 112 /* Clocks and PLLs. */
123 sleep_aux_pll_cntrl = au_readl(SYS_AUXPLL); 113 sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0);
114 sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1);
115 sleep_sys_clocks[2] = au_readl(SYS_CLKSRC);
116 sleep_sys_clocks[3] = au_readl(SYS_CPUPLL);
117 sleep_sys_clocks[4] = au_readl(SYS_AUXPLL);
124 118
125 /* 119 /* pin mux config */
126 * We don't really need to do this one, but unless we 120 sleep_sys_pinfunc = au_readl(SYS_PINFUNC);
127 * write it again it won't have a valid value if we
128 * happen to read it.
129 */
130 sleep_cpu_pll_cntrl = au_readl(SYS_CPUPLL);
131
132 sleep_pin_function = au_readl(SYS_PINFUNC);
133 121
134 /* Save the static memory controller configuration. */ 122 /* Save the static memory controller configuration. */
135 sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0); 123 sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
@@ -144,16 +132,45 @@ static void save_core_regs(void)
144 sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3); 132 sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3);
145 sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); 133 sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3);
146 sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); 134 sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
135
136#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
137 au1xxx_dbdma_suspend();
138#endif
147} 139}
148 140
149static void restore_core_regs(void) 141static void restore_core_regs(void)
150{ 142{
151 extern void restore_au1xxx_intctl(void); 143 /* restore clock configuration. Writing CPUPLL last will
152 extern void wakeup_counter0_adjust(void); 144 * stall a bit and stabilize other clocks (unless this is
145 * one of those Au1000 with a write-only PLL, where we dont
146 * have a valid value)
147 */
148 au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0);
149 au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1);
150 au_writel(sleep_sys_clocks[2], SYS_CLKSRC);
151 au_writel(sleep_sys_clocks[4], SYS_AUXPLL);
152 if (!au1xxx_cpu_has_pll_wo())
153 au_writel(sleep_sys_clocks[3], SYS_CPUPLL);
154 au_sync();
153 155
154 au_writel(sleep_aux_pll_cntrl, SYS_AUXPLL); au_sync(); 156 au_writel(sleep_sys_pinfunc, SYS_PINFUNC);
155 au_writel(sleep_cpu_pll_cntrl, SYS_CPUPLL); au_sync(); 157 au_sync();
156 au_writel(sleep_pin_function, SYS_PINFUNC); au_sync(); 158
159#ifndef CONFIG_SOC_AU1200
160 au_writel(sleep_usb[0], USB_HOST_CONFIG);
161 au_writel(sleep_usb[1], USBD_ENABLE);
162 au_sync();
163#else
164 /* enable accces to OTG memory */
165 au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4);
166 au_sync();
167
168 /* restore OTG caps and port mux. */
169 au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */
170 au_sync();
171 au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */
172 au_sync();
173#endif
157 174
158 /* Restore the static memory controller configuration. */ 175 /* Restore the static memory controller configuration. */
159 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); 176 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
@@ -184,282 +201,17 @@ static void restore_core_regs(void)
184 } 201 }
185 202
186 restore_au1xxx_intctl(); 203 restore_au1xxx_intctl();
187 wakeup_counter0_adjust();
188}
189
190unsigned long suspend_mode;
191 204
192void wakeup_from_suspend(void) 205#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
193{ 206 au1xxx_dbdma_resume();
194 suspend_mode = 0; 207#endif
195} 208}
196 209
197int au_sleep(void) 210void au_sleep(void)
198{ 211{
199 unsigned long wakeup, flags;
200 extern void save_and_sleep(void);
201
202 spin_lock_irqsave(&pm_lock, flags);
203
204 save_core_regs(); 212 save_core_regs();
205 213 au1xxx_save_and_sleep();
206 flush_cache_all();
207
208 /**
209 ** The code below is all system dependent and we should probably
210 ** have a function call out of here to set this up. You need
211 ** to configure the GPIO or timer interrupts that will bring
212 ** you out of sleep.
213 ** For testing, the TOY counter wakeup is useful.
214 **/
215#if 0
216 au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
217
218 /* GPIO 6 can cause a wake up event */
219 wakeup = au_readl(SYS_WAKEMSK);
220 wakeup &= ~(1 << 8); /* turn off match20 wakeup */
221 wakeup |= 1 << 6; /* turn on GPIO 6 wakeup */
222#else
223 /* For testing, allow match20 to wake us up. */
224#ifdef SLEEP_TEST_TIMEOUT
225 wakeup_counter0_set(sleep_ticks);
226#endif
227 wakeup = 1 << 8; /* turn on match20 wakeup */
228 wakeup = 0;
229#endif
230 au_writel(1, SYS_WAKESRC); /* clear cause */
231 au_sync();
232 au_writel(wakeup, SYS_WAKEMSK);
233 au_sync();
234
235 save_and_sleep();
236
237 /*
238 * After a wakeup, the cpu vectors back to 0x1fc00000, so
239 * it's up to the boot code to get us back here.
240 */
241 restore_core_regs(); 214 restore_core_regs();
242 spin_unlock_irqrestore(&pm_lock, flags);
243 return 0;
244}
245
246static int pm_do_sleep(ctl_table *ctl, int write, struct file *file,
247 void __user *buffer, size_t *len, loff_t *ppos)
248{
249#ifdef SLEEP_TEST_TIMEOUT
250#define TMPBUFLEN2 16
251 char buf[TMPBUFLEN2], *p;
252#endif
253
254 if (!write)
255 *len = 0;
256 else {
257#ifdef SLEEP_TEST_TIMEOUT
258 if (*len > TMPBUFLEN2 - 1)
259 return -EFAULT;
260 if (copy_from_user(buf, buffer, *len))
261 return -EFAULT;
262 buf[*len] = 0;
263 p = buf;
264 sleep_ticks = simple_strtoul(p, &p, 0);
265#endif
266
267 au_sleep();
268 }
269 return 0;
270}
271
272static int pm_do_freq(ctl_table *ctl, int write, struct file *file,
273 void __user *buffer, size_t *len, loff_t *ppos)
274{
275 int retval = 0, i;
276 unsigned long val, pll;
277#define TMPBUFLEN 64
278#define MAX_CPU_FREQ 396
279 char buf[TMPBUFLEN], *p;
280 unsigned long flags, intc0_mask, intc1_mask;
281 unsigned long old_baud_base, old_cpu_freq, old_clk, old_refresh;
282 unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh;
283 unsigned long baud_rate;
284
285 spin_lock_irqsave(&pm_lock, flags);
286 if (!write)
287 *len = 0;
288 else {
289 /* Parse the new frequency */
290 if (*len > TMPBUFLEN - 1) {
291 spin_unlock_irqrestore(&pm_lock, flags);
292 return -EFAULT;
293 }
294 if (copy_from_user(buf, buffer, *len)) {
295 spin_unlock_irqrestore(&pm_lock, flags);
296 return -EFAULT;
297 }
298 buf[*len] = 0;
299 p = buf;
300 val = simple_strtoul(p, &p, 0);
301 if (val > MAX_CPU_FREQ) {
302 spin_unlock_irqrestore(&pm_lock, flags);
303 return -EFAULT;
304 }
305
306 pll = val / 12;
307 if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */
308 /* Revisit this for higher speed CPUs */
309 spin_unlock_irqrestore(&pm_lock, flags);
310 return -EFAULT;
311 }
312
313 old_baud_base = get_au1x00_uart_baud_base();
314 old_cpu_freq = get_au1x00_speed();
315
316 new_cpu_freq = pll * 12 * 1000000;
317 new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL)
318 & 0x03) + 2) * 16));
319 set_au1x00_speed(new_cpu_freq);
320 set_au1x00_uart_baud_base(new_baud_base);
321
322 old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff;
323 new_refresh = ((old_refresh * new_cpu_freq) / old_cpu_freq) |
324 (au_readl(MEM_SDREFCFG) & ~0x1ffffff);
325
326 au_writel(pll, SYS_CPUPLL);
327 au_sync_delay(1);
328 au_writel(new_refresh, MEM_SDREFCFG);
329 au_sync_delay(1);
330
331 for (i = 0; i < 4; i++)
332 if (au_readl(UART_BASE + UART_MOD_CNTRL +
333 i * 0x00100000) == 3) {
334 old_clk = au_readl(UART_BASE + UART_CLK +
335 i * 0x00100000);
336 baud_rate = old_baud_base / old_clk;
337 /*
338 * We won't get an exact baud rate and the error
339 * could be significant enough that our new
340 * calculation will result in a clock that will
341 * give us a baud rate that's too far off from
342 * what we really want.
343 */
344 if (baud_rate > 100000)
345 baud_rate = 115200;
346 else if (baud_rate > 50000)
347 baud_rate = 57600;
348 else if (baud_rate > 30000)
349 baud_rate = 38400;
350 else if (baud_rate > 17000)
351 baud_rate = 19200;
352 else
353 baud_rate = 9600;
354 new_clk = new_baud_base / baud_rate;
355 au_writel(new_clk, UART_BASE + UART_CLK +
356 i * 0x00100000);
357 au_sync_delay(10);
358 }
359 }
360
361 /*
362 * We don't want _any_ interrupts other than match20. Otherwise our
363 * au1000_calibrate_delay() calculation will be off, potentially a lot.
364 */
365 intc0_mask = save_local_and_disable(0);
366 intc1_mask = save_local_and_disable(1);
367 local_enable_irq(AU1000_TOY_MATCH2_INT);
368 spin_unlock_irqrestore(&pm_lock, flags);
369 au1000_calibrate_delay();
370 restore_local_and_enable(0, intc0_mask);
371 restore_local_and_enable(1, intc1_mask);
372
373 return retval;
374} 215}
375 216
376
377static struct ctl_table pm_table[] = {
378 {
379 .ctl_name = CTL_UNNUMBERED,
380 .procname = "sleep",
381 .data = NULL,
382 .maxlen = 0,
383 .mode = 0600,
384 .proc_handler = &pm_do_sleep
385 },
386 {
387 .ctl_name = CTL_UNNUMBERED,
388 .procname = "freq",
389 .data = NULL,
390 .maxlen = 0,
391 .mode = 0600,
392 .proc_handler = &pm_do_freq
393 },
394 {}
395};
396
397static struct ctl_table pm_dir_table[] = {
398 {
399 .ctl_name = CTL_UNNUMBERED,
400 .procname = "pm",
401 .mode = 0555,
402 .child = pm_table
403 },
404 {}
405};
406
407/*
408 * Initialize power interface
409 */
410static int __init pm_init(void)
411{
412 register_sysctl_table(pm_dir_table);
413 return 0;
414}
415
416__initcall(pm_init);
417
418/*
419 * This is right out of init/main.c
420 */
421
422/*
423 * This is the number of bits of precision for the loops_per_jiffy.
424 * Each bit takes on average 1.5/HZ seconds. This (like the original)
425 * is a little better than 1%.
426 */
427#define LPS_PREC 8
428
429static void au1000_calibrate_delay(void)
430{
431 unsigned long ticks, loopbit;
432 int lps_precision = LPS_PREC;
433
434 loops_per_jiffy = 1 << 12;
435
436 while (loops_per_jiffy <<= 1) {
437 /* Wait for "start of" clock tick */
438 ticks = jiffies;
439 while (ticks == jiffies)
440 /* nothing */ ;
441 /* Go ... */
442 ticks = jiffies;
443 __delay(loops_per_jiffy);
444 ticks = jiffies - ticks;
445 if (ticks)
446 break;
447 }
448
449 /*
450 * Do a binary approximation to get loops_per_jiffy set to be equal
451 * one clock (up to lps_precision bits)
452 */
453 loops_per_jiffy >>= 1;
454 loopbit = loops_per_jiffy;
455 while (lps_precision-- && (loopbit >>= 1)) {
456 loops_per_jiffy |= loopbit;
457 ticks = jiffies;
458 while (ticks == jiffies);
459 ticks = jiffies;
460 __delay(loops_per_jiffy);
461 if (jiffies != ticks) /* longer than 1 tick */
462 loops_per_jiffy &= ~loopbit;
463 }
464}
465#endif /* CONFIG_PM */ 217#endif /* CONFIG_PM */
diff --git a/arch/mips/alchemy/common/reset.c b/arch/mips/alchemy/common/reset.c
index d555429c8d6f..0191c936cb5e 100644
--- a/arch/mips/alchemy/common/reset.c
+++ b/arch/mips/alchemy/common/reset.c
@@ -31,8 +31,6 @@
31 31
32#include <asm/mach-au1x00/au1000.h> 32#include <asm/mach-au1x00/au1000.h>
33 33
34extern int au_sleep(void);
35
36void au1000_restart(char *command) 34void au1000_restart(char *command)
37{ 35{
38 /* Set all integrated peripherals to disabled states */ 36 /* Set all integrated peripherals to disabled states */
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 1ac6b06f42a3..3f036b3d400e 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -35,7 +35,6 @@
35#include <asm/time.h> 35#include <asm/time.h>
36 36
37#include <au1000.h> 37#include <au1000.h>
38#include <prom.h>
39 38
40extern void __init board_setup(void); 39extern void __init board_setup(void);
41extern void au1000_restart(char *); 40extern void au1000_restart(char *);
@@ -45,80 +44,34 @@ extern void set_cpuspec(void);
45 44
46void __init plat_mem_setup(void) 45void __init plat_mem_setup(void)
47{ 46{
48 struct cpu_spec *sp; 47 unsigned long est_freq;
49 char *argptr;
50 unsigned long prid, cpufreq, bclk;
51 48
52 set_cpuspec(); 49 /* determine core clock */
53 sp = cur_cpu_spec[0]; 50 est_freq = au1xxx_calc_clock();
51 est_freq += 5000; /* round */
52 est_freq -= est_freq % 10000;
53 printk(KERN_INFO "(PRId %08x) @ %lu.%02lu MHz\n", read_c0_prid(),
54 est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000);
54 55
55 board_setup(); /* board specific setup */ 56 _machine_restart = au1000_restart;
56 57 _machine_halt = au1000_halt;
57 prid = read_c0_prid(); 58 pm_power_off = au1000_power_off;
58 if (sp->cpu_pll_wo)
59#ifdef CONFIG_SOC_AU1000_FREQUENCY
60 cpufreq = CONFIG_SOC_AU1000_FREQUENCY / 1000000;
61#else
62 cpufreq = 396;
63#endif
64 else
65 cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12;
66 printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq);
67 59
68 if (sp->cpu_bclk) { 60 board_setup(); /* board specific setup */
69 /* Enable BCLK switching */
70 bclk = au_readl(SYS_POWERCTRL);
71 au_writel(bclk | 0x60, SYS_POWERCTRL);
72 printk(KERN_INFO "BCLK switching enabled!\n");
73 }
74 61
75 if (sp->cpu_od) 62 if (au1xxx_cpu_needs_config_od())
76 /* Various early Au1xx0 errata corrected by this */ 63 /* Various early Au1xx0 errata corrected by this */
77 set_c0_config(1 << 19); /* Set Config[OD] */ 64 set_c0_config(1 << 19); /* Set Config[OD] */
78 else 65 else
79 /* Clear to obtain best system bus performance */ 66 /* Clear to obtain best system bus performance */
80 clear_c0_config(1 << 19); /* Clear Config[OD] */ 67 clear_c0_config(1 << 19); /* Clear Config[OD] */
81 68
82 argptr = prom_getcmdline();
83
84#ifdef CONFIG_SERIAL_8250_CONSOLE
85 argptr = strstr(argptr, "console=");
86 if (argptr == NULL) {
87 argptr = prom_getcmdline();
88 strcat(argptr, " console=ttyS0,115200");
89 }
90#endif
91
92#ifdef CONFIG_FB_AU1100
93 argptr = strstr(argptr, "video=");
94 if (argptr == NULL) {
95 argptr = prom_getcmdline();
96 /* default panel */
97 /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
98 }
99#endif
100
101#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
102 /* au1000 does not support vra, au1500 and au1100 do */
103 strcat(argptr, " au1000_audio=vra");
104 argptr = prom_getcmdline();
105#endif
106 _machine_restart = au1000_restart;
107 _machine_halt = au1000_halt;
108 pm_power_off = au1000_power_off;
109
110 /* IO/MEM resources. */ 69 /* IO/MEM resources. */
111 set_io_port_base(0); 70 set_io_port_base(0);
112 ioport_resource.start = IOPORT_RESOURCE_START; 71 ioport_resource.start = IOPORT_RESOURCE_START;
113 ioport_resource.end = IOPORT_RESOURCE_END; 72 ioport_resource.end = IOPORT_RESOURCE_END;
114 iomem_resource.start = IOMEM_RESOURCE_START; 73 iomem_resource.start = IOMEM_RESOURCE_START;
115 iomem_resource.end = IOMEM_RESOURCE_END; 74 iomem_resource.end = IOMEM_RESOURCE_END;
116
117 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
118 au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
119 au_sync();
120 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
121 au_writel(0, SYS_TOYTRIM);
122} 75}
123 76
124#if defined(CONFIG_64BIT_PHYS_ADDR) 77#if defined(CONFIG_64BIT_PHYS_ADDR)
diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S
index 3006e270c8bc..4f4b16741d12 100644
--- a/arch/mips/alchemy/common/sleeper.S
+++ b/arch/mips/alchemy/common/sleeper.S
@@ -15,16 +15,17 @@
15#include <asm/regdef.h> 15#include <asm/regdef.h>
16#include <asm/stackframe.h> 16#include <asm/stackframe.h>
17 17
18 .extern __flush_cache_all
19
18 .text 20 .text
19 .set macro 21 .set noreorder
20 .set noat 22 .set noat
21 .align 5 23 .align 5
22 24
23/* Save all of the processor general registers and go to sleep. 25/* Save all of the processor general registers and go to sleep.
24 * A wakeup condition will get us back here to restore the registers. 26 * A wakeup condition will get us back here to restore the registers.
25 */ 27 */
26LEAF(save_and_sleep) 28LEAF(au1xxx_save_and_sleep)
27
28 subu sp, PT_SIZE 29 subu sp, PT_SIZE
29 sw $1, PT_R1(sp) 30 sw $1, PT_R1(sp)
30 sw $2, PT_R2(sp) 31 sw $2, PT_R2(sp)
@@ -33,14 +34,6 @@ LEAF(save_and_sleep)
33 sw $5, PT_R5(sp) 34 sw $5, PT_R5(sp)
34 sw $6, PT_R6(sp) 35 sw $6, PT_R6(sp)
35 sw $7, PT_R7(sp) 36 sw $7, PT_R7(sp)
36 sw $8, PT_R8(sp)
37 sw $9, PT_R9(sp)
38 sw $10, PT_R10(sp)
39 sw $11, PT_R11(sp)
40 sw $12, PT_R12(sp)
41 sw $13, PT_R13(sp)
42 sw $14, PT_R14(sp)
43 sw $15, PT_R15(sp)
44 sw $16, PT_R16(sp) 37 sw $16, PT_R16(sp)
45 sw $17, PT_R17(sp) 38 sw $17, PT_R17(sp)
46 sw $18, PT_R18(sp) 39 sw $18, PT_R18(sp)
@@ -49,12 +42,9 @@ LEAF(save_and_sleep)
49 sw $21, PT_R21(sp) 42 sw $21, PT_R21(sp)
50 sw $22, PT_R22(sp) 43 sw $22, PT_R22(sp)
51 sw $23, PT_R23(sp) 44 sw $23, PT_R23(sp)
52 sw $24, PT_R24(sp)
53 sw $25, PT_R25(sp)
54 sw $26, PT_R26(sp) 45 sw $26, PT_R26(sp)
55 sw $27, PT_R27(sp) 46 sw $27, PT_R27(sp)
56 sw $28, PT_R28(sp) 47 sw $28, PT_R28(sp)
57 sw $29, PT_R29(sp)
58 sw $30, PT_R30(sp) 48 sw $30, PT_R30(sp)
59 sw $31, PT_R31(sp) 49 sw $31, PT_R31(sp)
60 mfc0 k0, CP0_STATUS 50 mfc0 k0, CP0_STATUS
@@ -66,20 +56,26 @@ LEAF(save_and_sleep)
66 mfc0 k0, CP0_CONFIG 56 mfc0 k0, CP0_CONFIG
67 sw k0, 0x14(sp) 57 sw k0, 0x14(sp)
68 58
59 /* flush caches to make sure context is in memory */
60 la t1, __flush_cache_all
61 lw t0, 0(t1)
62 jalr t0
63 nop
64
69 /* Now set up the scratch registers so the boot rom will 65 /* Now set up the scratch registers so the boot rom will
70 * return to this point upon wakeup. 66 * return to this point upon wakeup.
67 * sys_scratch0 : SP
68 * sys_scratch1 : RA
71 */ 69 */
72 la k0, 1f 70 lui t3, 0xb190 /* sys_xxx */
73 lui k1, 0xb190 71 sw sp, 0x0018(t3)
74 ori k1, 0x18 72 la k0, 3f /* resume path */
75 sw sp, 0(k1) 73 sw k0, 0x001c(t3)
76 ori k1, 0x1c
77 sw k0, 0(k1)
78 74
79/* Put SDRAM into self refresh. Preload instructions into cache, 75 /* Put SDRAM into self refresh: Preload instructions into cache,
80 * issue a precharge, then auto refresh, then sleep commands to it. 76 * issue a precharge, auto/self refresh, then sleep commands to it.
81 */ 77 */
82 la t0, sdsleep 78 la t0, 1f
83 .set mips3 79 .set mips3
84 cache 0x14, 0(t0) 80 cache 0x14, 0(t0)
85 cache 0x14, 32(t0) 81 cache 0x14, 32(t0)
@@ -87,24 +83,57 @@ LEAF(save_and_sleep)
87 cache 0x14, 96(t0) 83 cache 0x14, 96(t0)
88 .set mips0 84 .set mips0
89 85
90sdsleep: 861: lui a0, 0xb400 /* mem_xxx */
91 lui k0, 0xb400 87#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100) || \
92 sw zero, 0x001c(k0) /* Precharge */ 88 defined(CONFIG_SOC_AU1500)
93 sw zero, 0x0020(k0) /* Auto refresh */ 89 sw zero, 0x001c(a0) /* Precharge */
94 sw zero, 0x0030(k0) /* SDRAM sleep */ 90 sync
91 sw zero, 0x0020(a0) /* Auto Refresh */
92 sync
93 sw zero, 0x0030(a0) /* Sleep */
94 sync
95#endif
96
97#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
98 sw zero, 0x08c0(a0) /* Precharge */
95 sync 99 sync
100 sw zero, 0x08d0(a0) /* Self Refresh */
101 sync
102
103 /* wait for sdram to enter self-refresh mode */
104 lui t0, 0x0100
1052: lw t1, 0x0850(a0) /* mem_sdstat */
106 and t2, t1, t0
107 beq t2, zero, 2b
108 nop
96 109
97 lui k1, 0xb190 110 /* disable SDRAM clocks */
98 sw zero, 0x0078(k1) /* get ready to sleep */ 111 lui t0, 0xcfff
112 ori t0, t0, 0xffff
113 lw t1, 0x0840(a0) /* mem_sdconfiga */
114 and t1, t0, t1 /* clear CE[1:0] */
115 sw t1, 0x0840(a0) /* mem_sdconfiga */
99 sync 116 sync
100 sw zero, 0x007c(k1) /* Put processor to sleep */ 117#endif
118
119 /* put power supply and processor to sleep */
120 sw zero, 0x0078(t3) /* sys_slppwr */
121 sync
122 sw zero, 0x007c(t3) /* sys_sleep */
101 sync 123 sync
124 nop
125 nop
126 nop
127 nop
128 nop
129 nop
130 nop
131 nop
102 132
103 /* This is where we return upon wakeup. 133 /* This is where we return upon wakeup.
104 * Reload all of the registers and return. 134 * Reload all of the registers and return.
105 */ 135 */
1061: nop 1363: lw k0, 0x20(sp)
107 lw k0, 0x20(sp)
108 mtc0 k0, CP0_STATUS 137 mtc0 k0, CP0_STATUS
109 lw k0, 0x1c(sp) 138 lw k0, 0x1c(sp)
110 mtc0 k0, CP0_CONTEXT 139 mtc0 k0, CP0_CONTEXT
@@ -113,10 +142,11 @@ sdsleep:
113 lw k0, 0x14(sp) 142 lw k0, 0x14(sp)
114 mtc0 k0, CP0_CONFIG 143 mtc0 k0, CP0_CONFIG
115 144
116 /* We need to catch the ealry Alchemy SOCs with 145 /* We need to catch the early Alchemy SOCs with
117 * the write-only Config[OD] bit and set it back to one... 146 * the write-only Config[OD] bit and set it back to one...
118 */ 147 */
119 jal au1x00_fixup_config_od 148 jal au1x00_fixup_config_od
149 nop
120 lw $1, PT_R1(sp) 150 lw $1, PT_R1(sp)
121 lw $2, PT_R2(sp) 151 lw $2, PT_R2(sp)
122 lw $3, PT_R3(sp) 152 lw $3, PT_R3(sp)
@@ -124,14 +154,6 @@ sdsleep:
124 lw $5, PT_R5(sp) 154 lw $5, PT_R5(sp)
125 lw $6, PT_R6(sp) 155 lw $6, PT_R6(sp)
126 lw $7, PT_R7(sp) 156 lw $7, PT_R7(sp)
127 lw $8, PT_R8(sp)
128 lw $9, PT_R9(sp)
129 lw $10, PT_R10(sp)
130 lw $11, PT_R11(sp)
131 lw $12, PT_R12(sp)
132 lw $13, PT_R13(sp)
133 lw $14, PT_R14(sp)
134 lw $15, PT_R15(sp)
135 lw $16, PT_R16(sp) 157 lw $16, PT_R16(sp)
136 lw $17, PT_R17(sp) 158 lw $17, PT_R17(sp)
137 lw $18, PT_R18(sp) 159 lw $18, PT_R18(sp)
@@ -140,15 +162,11 @@ sdsleep:
140 lw $21, PT_R21(sp) 162 lw $21, PT_R21(sp)
141 lw $22, PT_R22(sp) 163 lw $22, PT_R22(sp)
142 lw $23, PT_R23(sp) 164 lw $23, PT_R23(sp)
143 lw $24, PT_R24(sp)
144 lw $25, PT_R25(sp)
145 lw $26, PT_R26(sp) 165 lw $26, PT_R26(sp)
146 lw $27, PT_R27(sp) 166 lw $27, PT_R27(sp)
147 lw $28, PT_R28(sp) 167 lw $28, PT_R28(sp)
148 lw $29, PT_R29(sp)
149 lw $30, PT_R30(sp) 168 lw $30, PT_R30(sp)
150 lw $31, PT_R31(sp) 169 lw $31, PT_R31(sp)
151 addiu sp, PT_SIZE
152
153 jr ra 170 jr ra
154END(save_and_sleep) 171 addiu sp, PT_SIZE
172END(au1xxx_save_and_sleep)
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index 563d9390a872..32880146cbc1 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -1,5 +1,7 @@
1/* 1/*
2 * Copyright (C) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
2 * 3 *
4 * Previous incarnations were:
3 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com> 5 * Copyright (C) 2001, 2006, 2008 MontaVista Software, <source@mvista.com>
4 * Copied and modified Carsten Langgaard's time.c 6 * Copied and modified Carsten Langgaard's time.c
5 * 7 *
@@ -23,244 +25,141 @@
23 * 25 *
24 * ######################################################################## 26 * ########################################################################
25 * 27 *
26 * Setting up the clock on the MIPS boards. 28 * Clocksource/event using the 32.768kHz-clocked Counter1 ('RTC' in the
27 * 29 * databooks). Firmware/Board init code must enable the counters in the
28 * We provide the clock interrupt processing and the timer offset compute 30 * counter control register, otherwise the CP0 counter clocksource/event
29 * functions. If CONFIG_PM is selected, we also ensure the 32KHz timer is 31 * will be installed instead (and use of 'wait' instruction is prohibited).
30 * available. -- Dan
31 */ 32 */
32 33
33#include <linux/types.h> 34#include <linux/clockchips.h>
34#include <linux/init.h> 35#include <linux/clocksource.h>
36#include <linux/interrupt.h>
35#include <linux/spinlock.h> 37#include <linux/spinlock.h>
36 38
37#include <asm/mipsregs.h>
38#include <asm/time.h> 39#include <asm/time.h>
39#include <asm/mach-au1x00/au1000.h> 40#include <asm/mach-au1x00/au1000.h>
40 41
41static int no_au1xxx_32khz; 42/* 32kHz clock enabled and detected */
42extern int allow_au1k_wait; /* default off for CP0 Counter */ 43#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S)
43
44#ifdef CONFIG_PM
45#if HZ < 100 || HZ > 1000
46#error "unsupported HZ value! Must be in [100,1000]"
47#endif
48#define MATCH20_INC (328 * 100 / HZ) /* magic number 328 is for HZ=100... */
49static unsigned long last_pc0, last_match20;
50#endif
51 44
52static DEFINE_SPINLOCK(time_lock); 45extern int allow_au1k_wait; /* default off for CP0 Counter */
53
54unsigned long wtimer;
55 46
56#ifdef CONFIG_PM 47static cycle_t au1x_counter1_read(void)
57static irqreturn_t counter0_irq(int irq, void *dev_id)
58{ 48{
59 unsigned long pc0; 49 return au_readl(SYS_RTCREAD);
60 int time_elapsed;
61 static int jiffie_drift;
62
63 if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
64 /* should never happen! */
65 printk(KERN_WARNING "counter 0 w status error\n");
66 return IRQ_NONE;
67 }
68
69 pc0 = au_readl(SYS_TOYREAD);
70 if (pc0 < last_match20)
71 /* counter overflowed */
72 time_elapsed = (0xffffffff - last_match20) + pc0;
73 else
74 time_elapsed = pc0 - last_match20;
75
76 while (time_elapsed > 0) {
77 do_timer(1);
78#ifndef CONFIG_SMP
79 update_process_times(user_mode(get_irq_regs()));
80#endif
81 time_elapsed -= MATCH20_INC;
82 last_match20 += MATCH20_INC;
83 jiffie_drift++;
84 }
85
86 last_pc0 = pc0;
87 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
88 au_sync();
89
90 /*
91 * Our counter ticks at 10.009765625 ms/tick, we we're running
92 * almost 10 uS too slow per tick.
93 */
94
95 if (jiffie_drift >= 999) {
96 jiffie_drift -= 999;
97 do_timer(1); /* increment jiffies by one */
98#ifndef CONFIG_SMP
99 update_process_times(user_mode(get_irq_regs()));
100#endif
101 }
102
103 return IRQ_HANDLED;
104} 50}
105 51
106struct irqaction counter0_action = { 52static struct clocksource au1x_counter1_clocksource = {
107 .handler = counter0_irq, 53 .name = "alchemy-counter1",
108 .flags = IRQF_DISABLED, 54 .read = au1x_counter1_read,
109 .name = "alchemy-toy", 55 .mask = CLOCKSOURCE_MASK(32),
110 .dev_id = NULL, 56 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
57 .rating = 100,
111}; 58};
112 59
113/* When we wakeup from sleep, we have to "catch up" on all of the 60static int au1x_rtcmatch2_set_next_event(unsigned long delta,
114 * timer ticks we have missed. 61 struct clock_event_device *cd)
115 */
116void wakeup_counter0_adjust(void)
117{ 62{
118 unsigned long pc0; 63 delta += au_readl(SYS_RTCREAD);
119 int time_elapsed; 64 /* wait for register access */
120 65 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21)
121 pc0 = au_readl(SYS_TOYREAD); 66 ;
122 if (pc0 < last_match20) 67 au_writel(delta, SYS_RTCMATCH2);
123 /* counter overflowed */
124 time_elapsed = (0xffffffff - last_match20) + pc0;
125 else
126 time_elapsed = pc0 - last_match20;
127
128 while (time_elapsed > 0) {
129 time_elapsed -= MATCH20_INC;
130 last_match20 += MATCH20_INC;
131 }
132
133 last_pc0 = pc0;
134 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
135 au_sync(); 68 au_sync();
136 69
70 return 0;
137} 71}
138 72
139/* This is just for debugging to set the timer for a sleep delay. */ 73static void au1x_rtcmatch2_set_mode(enum clock_event_mode mode,
140void wakeup_counter0_set(int ticks) 74 struct clock_event_device *cd)
141{ 75{
142 unsigned long pc0;
143
144 pc0 = au_readl(SYS_TOYREAD);
145 last_pc0 = pc0;
146 au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2);
147 au_sync();
148} 76}
149#endif
150 77
151/* 78static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id)
152 * I haven't found anyone that doesn't use a 12 MHz source clock,
153 * but just in case.....
154 */
155#define AU1000_SRC_CLK 12000000
156
157/*
158 * We read the real processor speed from the PLL. This is important
159 * because it is more accurate than computing it from the 32 KHz
160 * counter, if it exists. If we don't have an accurate processor
161 * speed, all of the peripherals that derive their clocks based on
162 * this advertised speed will introduce error and sometimes not work
163 * properly. This function is futher convoluted to still allow configurations
164 * to do that in case they have really, really old silicon with a
165 * write-only PLL register, that we need the 32 KHz when power management
166 * "wait" is enabled, and we need to detect if the 32 KHz isn't present
167 * but requested......got it? :-) -- Dan
168 */
169unsigned long calc_clock(void)
170{ 79{
171 unsigned long cpu_speed; 80 struct clock_event_device *cd = dev_id;
172 unsigned long flags; 81 cd->event_handler(cd);
173 unsigned long counter; 82 return IRQ_HANDLED;
174 83}
175 spin_lock_irqsave(&time_lock, flags);
176
177 /* Power management cares if we don't have a 32 KHz counter. */
178 no_au1xxx_32khz = 0;
179 counter = au_readl(SYS_COUNTER_CNTRL);
180 if (counter & SYS_CNTRL_E0) {
181 int trim_divide = 16;
182
183 au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
184
185 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
186 /* RTC now ticks at 32.768/16 kHz */
187 au_writel(trim_divide - 1, SYS_RTCTRIM);
188 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
189 84
190 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); 85static struct clock_event_device au1x_rtcmatch2_clockdev = {
191 au_writel(0, SYS_TOYWRITE); 86 .name = "rtcmatch2",
192 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); 87 .features = CLOCK_EVT_FEAT_ONESHOT,
193 } else 88 .rating = 100,
194 no_au1xxx_32khz = 1; 89 .irq = AU1000_RTC_MATCH2_INT,
90 .set_next_event = au1x_rtcmatch2_set_next_event,
91 .set_mode = au1x_rtcmatch2_set_mode,
92 .cpumask = CPU_MASK_ALL,
93};
195 94
196 /* 95static struct irqaction au1x_rtcmatch2_irqaction = {
197 * On early Au1000, sys_cpupll was write-only. Since these 96 .handler = au1x_rtcmatch2_irq,
198 * silicon versions of Au1000 are not sold by AMD, we don't bend 97 .flags = IRQF_DISABLED | IRQF_TIMER,
199 * over backwards trying to determine the frequency. 98 .name = "timer",
200 */ 99 .dev_id = &au1x_rtcmatch2_clockdev,
201 if (cur_cpu_spec[0]->cpu_pll_wo) 100};
202#ifdef CONFIG_SOC_AU1000_FREQUENCY
203 cpu_speed = CONFIG_SOC_AU1000_FREQUENCY;
204#else
205 cpu_speed = 396000000;
206#endif
207 else
208 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
209 /* On Alchemy CPU:counter ratio is 1:1 */
210 mips_hpt_frequency = cpu_speed;
211 /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */
212 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)
213 & 0x03) + 2) * 16));
214 spin_unlock_irqrestore(&time_lock, flags);
215 return cpu_speed;
216}
217 101
218void __init plat_time_init(void) 102void __init plat_time_init(void)
219{ 103{
220 unsigned int est_freq = calc_clock(); 104 struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
221 105 unsigned long t;
222 est_freq += 5000; /* round */ 106
223 est_freq -= est_freq%10000; 107 /* Check if firmware (YAMON, ...) has enabled 32kHz and clock
224 printk(KERN_INFO "CPU frequency %u.%02u MHz\n", 108 * has been detected. If so install the rtcmatch2 clocksource,
225 est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); 109 * otherwise don't bother. Note that both bits being set is by
226 set_au1x00_speed(est_freq); 110 * no means a definite guarantee that the counters actually work
227 set_au1x00_lcd_clock(); /* program the LCD clock */ 111 * (the 32S bit seems to be stuck set to 1 once a single clock-
112 * edge is detected, hence the timeouts).
113 */
114 if (CNTR_OK != (au_readl(SYS_COUNTER_CNTRL) & CNTR_OK))
115 goto cntr_err;
228 116
229#ifdef CONFIG_PM
230 /* 117 /*
231 * setup counter 0, since it keeps ticking after a 118 * setup counter 1 (RTC) to tick at full speed
232 * 'wait' instruction has been executed. The CP0 timer and
233 * counter 1 do NOT continue running after 'wait'
234 *
235 * It's too early to call request_irq() here, so we handle
236 * counter 0 interrupt as a special irq and it doesn't show
237 * up under /proc/interrupts.
238 *
239 * Check to ensure we really have a 32 KHz oscillator before
240 * we do this.
241 */ 119 */
242 if (no_au1xxx_32khz) 120 t = 0xffffff;
243 printk(KERN_WARNING "WARNING: no 32KHz clock found.\n"); 121 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && t--)
244 else { 122 asm volatile ("nop");
245 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); 123 if (!t)
246 au_writel(0, SYS_TOYWRITE); 124 goto cntr_err;
247 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
248
249 au_writel(au_readl(SYS_WAKEMSK) | (1 << 8), SYS_WAKEMSK);
250 au_writel(~0, SYS_WAKESRC);
251 au_sync();
252 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
253 125
254 /* Setup match20 to interrupt once every HZ */ 126 au_writel(0, SYS_RTCTRIM); /* 32.768 kHz */
255 last_pc0 = last_match20 = au_readl(SYS_TOYREAD); 127 au_sync();
256 au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
257 au_sync();
258 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
259 setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action);
260 128
261 /* We can use the real 'wait' instruction. */ 129 t = 0xffffff;
262 allow_au1k_wait = 1; 130 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && t--)
263 } 131 asm volatile ("nop");
132 if (!t)
133 goto cntr_err;
134 au_writel(0, SYS_RTCWRITE);
135 au_sync();
264 136
265#endif 137 t = 0xffffff;
138 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && t--)
139 asm volatile ("nop");
140 if (!t)
141 goto cntr_err;
142
143 /* register counter1 clocksource and event device */
144 clocksource_set_clock(&au1x_counter1_clocksource, 32768);
145 clocksource_register(&au1x_counter1_clocksource);
146
147 cd->shift = 32;
148 cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift);
149 cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd);
150 cd->min_delta_ns = clockevent_delta2ns(8, cd); /* ~0.25ms */
151 clockevents_register_device(cd);
152 setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction);
153
154 printk(KERN_INFO "Alchemy clocksource installed\n");
155
156 /* can now use 'wait' */
157 allow_au1k_wait = 1;
158 return;
159
160cntr_err:
161 /* counters unusable, use C0 counter */
162 r4k_clockevent_init();
163 init_r4k_clocksource();
164 allow_au1k_wait = 0;
266} 165}
diff --git a/arch/mips/alchemy/db1x00/init.c b/arch/mips/alchemy/db1x00/init.c
deleted file mode 100644
index 847413514964..000000000000
--- a/arch/mips/alchemy/db1x00/init.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * PB1000 board setup
4 *
5 * Copyright 2001, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30#include <linux/kernel.h>
31
32#include <asm/bootinfo.h>
33
34#include <prom.h>
35
36const char *get_system_type(void)
37{
38#ifdef CONFIG_MIPS_BOSPORUS
39 return "Alchemy Bosporus Gateway Reference";
40#else
41 return "Alchemy Db1x00";
42#endif
43}
44
45void __init prom_init(void)
46{
47 unsigned char *memsize_str;
48 unsigned long memsize;
49
50 prom_argc = fw_arg0;
51 prom_argv = (char **)fw_arg1;
52 prom_envp = (char **)fw_arg2;
53
54 prom_init_cmdline();
55
56 memsize_str = prom_getenv("memsize");
57 if (!memsize_str)
58 memsize = 0x04000000;
59 else
60 strict_strtol(memsize_str, 0, &memsize);
61 add_memory_region(0, memsize, BOOT_MEM_RAM);
62}
diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile
new file mode 100644
index 000000000000..730f9f2b30e8
--- /dev/null
+++ b/arch/mips/alchemy/devboards/Makefile
@@ -0,0 +1,18 @@
1#
2# Alchemy Develboards
3#
4
5obj-y += prom.o
6obj-$(CONFIG_PM) += pm.o
7obj-$(CONFIG_MIPS_PB1000) += pb1000/
8obj-$(CONFIG_MIPS_PB1100) += pb1100/
9obj-$(CONFIG_MIPS_PB1200) += pb1200/
10obj-$(CONFIG_MIPS_PB1500) += pb1500/
11obj-$(CONFIG_MIPS_PB1550) += pb1550/
12obj-$(CONFIG_MIPS_DB1000) += db1x00/
13obj-$(CONFIG_MIPS_DB1100) += db1x00/
14obj-$(CONFIG_MIPS_DB1200) += pb1200/
15obj-$(CONFIG_MIPS_DB1500) += db1x00/
16obj-$(CONFIG_MIPS_DB1550) += db1x00/
17obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/
18obj-$(CONFIG_MIPS_MIRAGE) += db1x00/
diff --git a/arch/mips/alchemy/db1x00/Makefile b/arch/mips/alchemy/devboards/db1x00/Makefile
index 274db3b55d82..432241ab8677 100644
--- a/arch/mips/alchemy/db1x00/Makefile
+++ b/arch/mips/alchemy/devboards/db1x00/Makefile
@@ -5,4 +5,4 @@
5# Makefile for the Alchemy Semiconductor DBAu1xx0 boards. 5# Makefile for the Alchemy Semiconductor DBAu1xx0 boards.
6# 6#
7 7
8lib-y := init.o board_setup.o irqmap.o 8obj-y := board_setup.o irqmap.o
diff --git a/arch/mips/alchemy/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c
index 9e5ccbbfcedd..a75ffbf99f25 100644
--- a/arch/mips/alchemy/db1x00/board_setup.c
+++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c
@@ -32,8 +32,20 @@
32#include <asm/mach-au1x00/au1000.h> 32#include <asm/mach-au1x00/au1000.h>
33#include <asm/mach-db1x00/db1x00.h> 33#include <asm/mach-db1x00/db1x00.h>
34 34
35#include <prom.h>
36
37
35static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; 38static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
36 39
40const char *get_system_type(void)
41{
42#ifdef CONFIG_MIPS_BOSPORUS
43 return "Alchemy Bosporus Gateway Reference";
44#else
45 return "Alchemy Db1x00";
46#endif
47}
48
37void board_reset(void) 49void board_reset(void)
38{ 50{
39 /* Hit BCSR.SW_RESET[RESET] */ 51 /* Hit BCSR.SW_RESET[RESET] */
@@ -43,6 +55,31 @@ void board_reset(void)
43void __init board_setup(void) 55void __init board_setup(void)
44{ 56{
45 u32 pin_func = 0; 57 u32 pin_func = 0;
58 char *argptr;
59
60 argptr = prom_getcmdline();
61#ifdef CONFIG_SERIAL_8250_CONSOLE
62 argptr = strstr(argptr, "console=");
63 if (argptr == NULL) {
64 argptr = prom_getcmdline();
65 strcat(argptr, " console=ttyS0,115200");
66 }
67#endif
68
69#ifdef CONFIG_FB_AU1100
70 argptr = strstr(argptr, "video=");
71 if (argptr == NULL) {
72 argptr = prom_getcmdline();
73 /* default panel */
74 /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
75 }
76#endif
77
78#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
79 /* au1000 does not support vra, au1500 and au1100 do */
80 strcat(argptr, " au1000_audio=vra");
81 argptr = prom_getcmdline();
82#endif
46 83
47 /* Not valid for Au1550 */ 84 /* Not valid for Au1550 */
48#if defined(CONFIG_IRDA) && \ 85#if defined(CONFIG_IRDA) && \
diff --git a/arch/mips/alchemy/db1x00/irqmap.c b/arch/mips/alchemy/devboards/db1x00/irqmap.c
index 94c090e8bf7a..0b09025087c6 100644
--- a/arch/mips/alchemy/db1x00/irqmap.c
+++ b/arch/mips/alchemy/devboards/db1x00/irqmap.c
@@ -27,6 +27,7 @@
27 */ 27 */
28 28
29#include <linux/init.h> 29#include <linux/init.h>
30#include <linux/interrupt.h>
30 31
31#include <asm/mach-au1x00/au1000.h> 32#include <asm/mach-au1x00/au1000.h>
32 33
@@ -66,21 +67,24 @@ struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
66 67
67#ifndef CONFIG_MIPS_MIRAGE 68#ifndef CONFIG_MIPS_MIRAGE
68#ifdef CONFIG_MIPS_DB1550 69#ifdef CONFIG_MIPS_DB1550
69 { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 0 IRQ# */ 70 { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 IRQ# */
70 { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 1 IRQ# */ 71 { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 IRQ# */
71#else 72#else
72 { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 0 Fully_Interted# */ 73 { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 Fully_Interted# */
73 { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 0 STSCHG# */ 74 { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 STSCHG# */
74 { AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 0 IRQ# */ 75 { AU1000_GPIO_2, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 0 IRQ# */
75 76
76 { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 1 Fully_Interted# */ 77 { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 Fully_Interted# */
77 { AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 1 STSCHG# */ 78 { AU1000_GPIO_4, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 STSCHG# */
78 { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card 1 IRQ# */ 79 { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card 1 IRQ# */
79#endif 80#endif
80#else 81#else
81 { AU1000_GPIO_7, INTC_INT_RISE_EDGE, 0 }, /* touchscreen pen down */ 82 { AU1000_GPIO_7, IRQF_TRIGGER_RISING, 0 }, /* touchscreen pen down */
82#endif 83#endif
83 84
84}; 85};
85 86
86int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); 87void __init board_init_irq(void)
88{
89 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
90}
diff --git a/arch/mips/alchemy/pb1000/Makefile b/arch/mips/alchemy/devboards/pb1000/Makefile
index 99bbec0ca41b..97c6615ba2bb 100644
--- a/arch/mips/alchemy/pb1000/Makefile
+++ b/arch/mips/alchemy/devboards/pb1000/Makefile
@@ -5,4 +5,4 @@
5# Makefile for the Alchemy Semiconductor Pb1000 board. 5# Makefile for the Alchemy Semiconductor Pb1000 board.
6# 6#
7 7
8lib-y := init.o board_setup.o irqmap.o 8obj-y := board_setup.o
diff --git a/arch/mips/alchemy/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c
index 25df167a95b3..aed2fdecc709 100644
--- a/arch/mips/alchemy/pb1000/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c
@@ -23,22 +23,48 @@
23 * 675 Mass Ave, Cambridge, MA 02139, USA. 23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */ 24 */
25 25
26#include <linux/init.h>
27#include <linux/delay.h> 26#include <linux/delay.h>
28 27#include <linux/init.h>
28#include <linux/interrupt.h>
29#include <asm/mach-au1x00/au1000.h> 29#include <asm/mach-au1x00/au1000.h>
30#include <asm/mach-pb1x00/pb1000.h> 30#include <asm/mach-pb1x00/pb1000.h>
31#include <prom.h>
32
33
34struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
35 { AU1000_GPIO_15, IRQF_TRIGGER_LOW, 0 },
36};
37
38
39const char *get_system_type(void)
40{
41 return "Alchemy Pb1000";
42}
31 43
32void board_reset(void) 44void board_reset(void)
33{ 45{
34} 46}
35 47
48void __init board_init_irq(void)
49{
50 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
51}
52
36void __init board_setup(void) 53void __init board_setup(void)
37{ 54{
38 u32 pin_func, static_cfg0; 55 u32 pin_func, static_cfg0;
39 u32 sys_freqctrl, sys_clksrc; 56 u32 sys_freqctrl, sys_clksrc;
40 u32 prid = read_c0_prid(); 57 u32 prid = read_c0_prid();
41 58
59#ifdef CONFIG_SERIAL_8250_CONSOLE
60 char *argptr = prom_getcmdline();
61 argptr = strstr(argptr, "console=");
62 if (argptr == NULL) {
63 argptr = prom_getcmdline();
64 strcat(argptr, " console=ttyS0,115200");
65 }
66#endif
67
42 /* Set AUX clock to 12 MHz * 8 = 96 MHz */ 68 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
43 au_writel(8, SYS_AUXPLL); 69 au_writel(8, SYS_AUXPLL);
44 au_writel(0, SYS_PINSTATERD); 70 au_writel(0, SYS_PINSTATERD);
diff --git a/arch/mips/alchemy/pb1100/Makefile b/arch/mips/alchemy/devboards/pb1100/Makefile
index 793e97c49e46..c586dd7e91dc 100644
--- a/arch/mips/alchemy/pb1100/Makefile
+++ b/arch/mips/alchemy/devboards/pb1100/Makefile
@@ -5,4 +5,4 @@
5# Makefile for the Alchemy Semiconductor Pb1100 board. 5# Makefile for the Alchemy Semiconductor Pb1100 board.
6# 6#
7 7
8lib-y := init.o board_setup.o irqmap.o 8obj-y := board_setup.o
diff --git a/arch/mips/alchemy/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c
index c0bfd59a7a36..4df57fae15d4 100644
--- a/arch/mips/alchemy/pb1100/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c
@@ -25,19 +25,66 @@
25 25
26#include <linux/init.h> 26#include <linux/init.h>
27#include <linux/delay.h> 27#include <linux/delay.h>
28#include <linux/interrupt.h>
28 29
29#include <asm/mach-au1x00/au1000.h> 30#include <asm/mach-au1x00/au1000.h>
30#include <asm/mach-pb1x00/pb1100.h> 31#include <asm/mach-pb1x00/pb1100.h>
31 32
33#include <prom.h>
34
35
36struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
37 { AU1000_GPIO_9, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card Fully_Inserted# */
38 { AU1000_GPIO_10, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card STSCHG# */
39 { AU1000_GPIO_11, IRQF_TRIGGER_LOW, 0 }, /* PCMCIA Card IRQ# */
40 { AU1000_GPIO_13, IRQF_TRIGGER_LOW, 0 }, /* DC_IRQ# */
41};
42
43
44const char *get_system_type(void)
45{
46 return "Alchemy Pb1100";
47}
48
32void board_reset(void) 49void board_reset(void)
33{ 50{
34 /* Hit BCSR.RST_VDDI[SOFT_RESET] */ 51 /* Hit BCSR.RST_VDDI[SOFT_RESET] */
35 au_writel(0x00000000, PB1100_RST_VDDI); 52 au_writel(0x00000000, PB1100_RST_VDDI);
36} 53}
37 54
55void __init board_init_irq(void)
56{
57 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
58}
59
38void __init board_setup(void) 60void __init board_setup(void)
39{ 61{
40 volatile void __iomem *base = (volatile void __iomem *)0xac000000UL; 62 volatile void __iomem *base = (volatile void __iomem *)0xac000000UL;
63 char *argptr;
64
65 argptr = prom_getcmdline();
66#ifdef CONFIG_SERIAL_8250_CONSOLE
67 argptr = strstr(argptr, "console=");
68 if (argptr == NULL) {
69 argptr = prom_getcmdline();
70 strcat(argptr, " console=ttyS0,115200");
71 }
72#endif
73
74#ifdef CONFIG_FB_AU1100
75 argptr = strstr(argptr, "video=");
76 if (argptr == NULL) {
77 argptr = prom_getcmdline();
78 /* default panel */
79 /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
80 }
81#endif
82
83#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
84 /* au1000 does not support vra, au1500 and au1100 do */
85 strcat(argptr, " au1000_audio=vra");
86 argptr = prom_getcmdline();
87#endif
41 88
42 /* Set AUX clock to 12 MHz * 8 = 96 MHz */ 89 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
43 au_writel(8, SYS_AUXPLL); 90 au_writel(8, SYS_AUXPLL);
diff --git a/arch/mips/alchemy/pb1200/Makefile b/arch/mips/alchemy/devboards/pb1200/Makefile
index d678adf7ce85..c8c3a99fb68a 100644
--- a/arch/mips/alchemy/pb1200/Makefile
+++ b/arch/mips/alchemy/devboards/pb1200/Makefile
@@ -2,7 +2,6 @@
2# Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards. 2# Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards.
3# 3#
4 4
5lib-y := init.o board_setup.o irqmap.o 5obj-y := board_setup.o irqmap.o platform.o
6obj-y += platform.o
7 6
8EXTRA_CFLAGS += -Werror 7EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c
index 6cb2115059ad..94e6b7e7753d 100644
--- a/arch/mips/alchemy/pb1200/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c
@@ -30,8 +30,11 @@
30#include <prom.h> 30#include <prom.h>
31#include <au1xxx.h> 31#include <au1xxx.h>
32 32
33extern void _board_init_irq(void); 33
34extern void (*board_init_irq)(void); 34const char *get_system_type(void)
35{
36 return "Alchemy Pb1200";
37}
35 38
36void board_reset(void) 39void board_reset(void)
37{ 40{
@@ -41,7 +44,19 @@ void board_reset(void)
41 44
42void __init board_setup(void) 45void __init board_setup(void)
43{ 46{
44 char *argptr = NULL; 47 char *argptr;
48
49 argptr = prom_getcmdline();
50#ifdef CONFIG_SERIAL_8250_CONSOLE
51 argptr = strstr(argptr, "console=");
52 if (argptr == NULL) {
53 argptr = prom_getcmdline();
54 strcat(argptr, " console=ttyS0,115200");
55 }
56#endif
57#ifdef CONFIG_FB_AU1200
58 strcat(argptr, " video=au1200fb:panel:bs");
59#endif
45 60
46#if 0 61#if 0
47 { 62 {
@@ -99,16 +114,6 @@ void __init board_setup(void)
99 } 114 }
100#endif 115#endif
101 116
102#ifdef CONFIG_FB_AU1200
103 argptr = prom_getcmdline();
104#ifdef CONFIG_MIPS_PB1200
105 strcat(argptr, " video=au1200fb:panel:bs");
106#endif
107#ifdef CONFIG_MIPS_DB1200
108 strcat(argptr, " video=au1200fb:panel:bs");
109#endif
110#endif
111
112 /* 117 /*
113 * The Pb1200 development board uses external MUX for PSC0 to 118 * The Pb1200 development board uses external MUX for PSC0 to
114 * support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI 119 * support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
@@ -124,9 +129,6 @@ void __init board_setup(void)
124#ifdef CONFIG_MIPS_DB1200 129#ifdef CONFIG_MIPS_DB1200
125 printk(KERN_INFO "AMD Alchemy Db1200 Board\n"); 130 printk(KERN_INFO "AMD Alchemy Db1200 Board\n");
126#endif 131#endif
127
128 /* Setup Pb1200 External Interrupt Controller */
129 board_init_irq = _board_init_irq;
130} 132}
131 133
132int board_au1200fb_panel(void) 134int board_au1200fb_panel(void)
diff --git a/arch/mips/alchemy/pb1200/irqmap.c b/arch/mips/alchemy/devboards/pb1200/irqmap.c
index 2a505ad8715b..fe47498da280 100644
--- a/arch/mips/alchemy/pb1200/irqmap.c
+++ b/arch/mips/alchemy/devboards/pb1200/irqmap.c
@@ -40,91 +40,65 @@
40 40
41struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { 41struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
42 /* This is external interrupt cascade */ 42 /* This is external interrupt cascade */
43 { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 }, 43 { AU1000_GPIO_7, IRQF_TRIGGER_LOW, 0 },
44}; 44};
45 45
46int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
47 46
48/* 47/*
49 * Support for External interrupts on the Pb1200 Development platform. 48 * Support for External interrupts on the Pb1200 Development platform.
50 */ 49 */
51static volatile int pb1200_cascade_en;
52 50
53irqreturn_t pb1200_cascade_handler(int irq, void *dev_id) 51static void pb1200_cascade_handler(unsigned int irq, struct irq_desc *d)
54{ 52{
55 unsigned short bisr = bcsr->int_status; 53 unsigned short bisr = bcsr->int_status;
56 int extirq_nr = 0;
57
58 /* Clear all the edge interrupts. This has no effect on level. */
59 bcsr->int_status = bisr;
60 for ( ; bisr; bisr &= bisr - 1) {
61 extirq_nr = PB1200_INT_BEGIN + __ffs(bisr);
62 /* Ack and dispatch IRQ */
63 do_IRQ(extirq_nr);
64 }
65
66 return IRQ_RETVAL(1);
67}
68 54
69inline void pb1200_enable_irq(unsigned int irq_nr) 55 for ( ; bisr; bisr &= bisr - 1)
70{ 56 generic_handle_irq(PB1200_INT_BEGIN + __ffs(bisr));
71 bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
72 bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN);
73} 57}
74 58
75inline void pb1200_disable_irq(unsigned int irq_nr) 59/* NOTE: both the enable and mask bits must be cleared, otherwise the
60 * CPLD generates tons of spurious interrupts (at least on the DB1200).
61 */
62static void pb1200_mask_irq(unsigned int irq_nr)
76{ 63{
77 bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN); 64 bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
78 bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN); 65 bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN);
66 au_sync();
79} 67}
80 68
81static unsigned int pb1200_setup_cascade(void) 69static void pb1200_maskack_irq(unsigned int irq_nr)
82{
83 return request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
84 0, "Pb1200 Cascade", &pb1200_cascade_handler);
85}
86
87static unsigned int pb1200_startup_irq(unsigned int irq)
88{ 70{
89 if (++pb1200_cascade_en == 1) { 71 bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
90 int res; 72 bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN);
91 73 bcsr->int_status = 1 << (irq_nr - PB1200_INT_BEGIN); /* ack */
92 res = pb1200_setup_cascade(); 74 au_sync();
93 if (res)
94 return res;
95 }
96
97 pb1200_enable_irq(irq);
98
99 return 0;
100} 75}
101 76
102static void pb1200_shutdown_irq(unsigned int irq) 77static void pb1200_unmask_irq(unsigned int irq_nr)
103{ 78{
104 pb1200_disable_irq(irq); 79 bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN);
105 if (--pb1200_cascade_en == 0) 80 bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
106 free_irq(AU1000_GPIO_7, &pb1200_cascade_handler); 81 au_sync();
107} 82}
108 83
109static struct irq_chip external_irq_type = { 84static struct irq_chip pb1200_cpld_irq_type = {
110#ifdef CONFIG_MIPS_PB1200 85#ifdef CONFIG_MIPS_PB1200
111 .name = "Pb1200 Ext", 86 .name = "Pb1200 Ext",
112#endif 87#endif
113#ifdef CONFIG_MIPS_DB1200 88#ifdef CONFIG_MIPS_DB1200
114 .name = "Db1200 Ext", 89 .name = "Db1200 Ext",
115#endif 90#endif
116 .startup = pb1200_startup_irq, 91 .mask = pb1200_mask_irq,
117 .shutdown = pb1200_shutdown_irq, 92 .mask_ack = pb1200_maskack_irq,
118 .ack = pb1200_disable_irq, 93 .unmask = pb1200_unmask_irq,
119 .mask = pb1200_disable_irq,
120 .mask_ack = pb1200_disable_irq,
121 .unmask = pb1200_enable_irq,
122}; 94};
123 95
124void _board_init_irq(void) 96void __init board_init_irq(void)
125{ 97{
126 unsigned int irq; 98 unsigned int irq;
127 99
100 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
101
128#ifdef CONFIG_MIPS_PB1200 102#ifdef CONFIG_MIPS_PB1200
129 /* We have a problem with CPLD rev 3. */ 103 /* We have a problem with CPLD rev 3. */
130 if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) { 104 if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) {
@@ -146,15 +120,15 @@ void _board_init_irq(void)
146 panic("Game over. Your score is 0."); 120 panic("Game over. Your score is 0.");
147 } 121 }
148#endif 122#endif
123 /* mask & disable & ack all */
124 bcsr->intclr_mask = 0xffff;
125 bcsr->intclr = 0xffff;
126 bcsr->int_status = 0xffff;
127 au_sync();
149 128
150 for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++) { 129 for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++)
151 set_irq_chip_and_handler(irq, &external_irq_type, 130 set_irq_chip_and_handler_name(irq, &pb1200_cpld_irq_type,
152 handle_level_irq); 131 handle_level_irq, "level");
153 pb1200_disable_irq(irq);
154 }
155 132
156 /* 133 set_irq_chained_handler(AU1000_GPIO_7, pb1200_cascade_handler);
157 * GPIO_7 can not be hooked here, so it is hooked upon first
158 * request of any source attached to the cascade.
159 */
160} 134}
diff --git a/arch/mips/alchemy/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c
index 95303297c534..95303297c534 100644
--- a/arch/mips/alchemy/pb1200/platform.c
+++ b/arch/mips/alchemy/devboards/pb1200/platform.c
diff --git a/arch/mips/alchemy/pb1500/Makefile b/arch/mips/alchemy/devboards/pb1500/Makefile
index 602f38df20bb..173b419a7479 100644
--- a/arch/mips/alchemy/pb1500/Makefile
+++ b/arch/mips/alchemy/devboards/pb1500/Makefile
@@ -5,4 +5,4 @@
5# Makefile for the Alchemy Semiconductor Pb1500 board. 5# Makefile for the Alchemy Semiconductor Pb1500 board.
6# 6#
7 7
8lib-y := init.o board_setup.o irqmap.o 8obj-y := board_setup.o
diff --git a/arch/mips/alchemy/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c
index 035771c6e5b8..fed3b093156a 100644
--- a/arch/mips/alchemy/pb1500/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c
@@ -25,20 +25,64 @@
25 25
26#include <linux/init.h> 26#include <linux/init.h>
27#include <linux/delay.h> 27#include <linux/delay.h>
28#include <linux/interrupt.h>
28 29
29#include <asm/mach-au1x00/au1000.h> 30#include <asm/mach-au1x00/au1000.h>
30#include <asm/mach-pb1x00/pb1500.h> 31#include <asm/mach-pb1x00/pb1500.h>
31 32
33#include <prom.h>
34
35
36char irq_tab_alchemy[][5] __initdata = {
37 [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT370 */
38 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
39};
40
41struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
42 { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 },
43 { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 },
44 { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 },
45 { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 },
46 { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 },
47};
48
49
50const char *get_system_type(void)
51{
52 return "Alchemy Pb1500";
53}
54
32void board_reset(void) 55void board_reset(void)
33{ 56{
34 /* Hit BCSR.RST_VDDI[SOFT_RESET] */ 57 /* Hit BCSR.RST_VDDI[SOFT_RESET] */
35 au_writel(0x00000000, PB1500_RST_VDDI); 58 au_writel(0x00000000, PB1500_RST_VDDI);
36} 59}
37 60
61void __init board_init_irq(void)
62{
63 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
64}
65
38void __init board_setup(void) 66void __init board_setup(void)
39{ 67{
40 u32 pin_func; 68 u32 pin_func;
41 u32 sys_freqctrl, sys_clksrc; 69 u32 sys_freqctrl, sys_clksrc;
70 char *argptr;
71
72 argptr = prom_getcmdline();
73#ifdef CONFIG_SERIAL_8250_CONSOLE
74 argptr = strstr(argptr, "console=");
75 if (argptr == NULL) {
76 argptr = prom_getcmdline();
77 strcat(argptr, " console=ttyS0,115200");
78 }
79#endif
80
81#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
82 /* au1000 does not support vra, au1500 and au1100 do */
83 strcat(argptr, " au1000_audio=vra");
84 argptr = prom_getcmdline();
85#endif
42 86
43 sys_clksrc = sys_freqctrl = pin_func = 0; 87 sys_clksrc = sys_freqctrl = pin_func = 0;
44 /* Set AUX clock to 12 MHz * 8 = 96 MHz */ 88 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
diff --git a/arch/mips/alchemy/pb1550/Makefile b/arch/mips/alchemy/devboards/pb1550/Makefile
index 7d8beca87fa5..cff95bcdb2ca 100644
--- a/arch/mips/alchemy/pb1550/Makefile
+++ b/arch/mips/alchemy/devboards/pb1550/Makefile
@@ -5,4 +5,4 @@
5# Makefile for the Alchemy Semiconductor Pb1550 board. 5# Makefile for the Alchemy Semiconductor Pb1550 board.
6# 6#
7 7
8lib-y := init.o board_setup.o irqmap.o 8obj-y := board_setup.o
diff --git a/arch/mips/alchemy/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c
index 0ed76b64b6ab..b6e9e7d247a3 100644
--- a/arch/mips/alchemy/pb1550/board_setup.c
+++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c
@@ -28,20 +28,54 @@
28 */ 28 */
29 29
30#include <linux/init.h> 30#include <linux/init.h>
31#include <linux/interrupt.h>
31 32
32#include <asm/mach-au1x00/au1000.h> 33#include <asm/mach-au1x00/au1000.h>
33#include <asm/mach-pb1x00/pb1550.h> 34#include <asm/mach-pb1x00/pb1550.h>
34 35
36#include <prom.h>
37
38
39char irq_tab_alchemy[][5] __initdata = {
40 [12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */
41 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */
42};
43
44struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
45 { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 },
46 { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 },
47};
48
49const char *get_system_type(void)
50{
51 return "Alchemy Pb1550";
52}
53
35void board_reset(void) 54void board_reset(void)
36{ 55{
37 /* Hit BCSR.SYSTEM[RESET] */ 56 /* Hit BCSR.SYSTEM[RESET] */
38 au_writew(au_readw(0xAF00001C) & ~BCSR_SYSTEM_RESET, 0xAF00001C); 57 au_writew(au_readw(0xAF00001C) & ~BCSR_SYSTEM_RESET, 0xAF00001C);
39} 58}
40 59
60void __init board_init_irq(void)
61{
62 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
63}
64
41void __init board_setup(void) 65void __init board_setup(void)
42{ 66{
43 u32 pin_func; 67 u32 pin_func;
44 68
69#ifdef CONFIG_SERIAL_8250_CONSOLE
70 char *argptr;
71 argptr = prom_getcmdline();
72 argptr = strstr(argptr, "console=");
73 if (argptr == NULL) {
74 argptr = prom_getcmdline();
75 strcat(argptr, " console=ttyS0,115200");
76 }
77#endif
78
45 /* 79 /*
46 * Enable PSC1 SYNC for AC'97. Normaly done in audio driver, 80 * Enable PSC1 SYNC for AC'97. Normaly done in audio driver,
47 * but it is board specific code, so put it here. 81 * but it is board specific code, so put it here.
diff --git a/arch/mips/alchemy/devboards/pm.c b/arch/mips/alchemy/devboards/pm.c
new file mode 100644
index 000000000000..d5eb9c325ed0
--- /dev/null
+++ b/arch/mips/alchemy/devboards/pm.c
@@ -0,0 +1,229 @@
1/*
2 * Alchemy Development Board example suspend userspace interface.
3 *
4 * (c) 2008 Manuel Lauss <mano@roarinelk.homelinux.net>
5 */
6
7#include <linux/init.h>
8#include <linux/kobject.h>
9#include <linux/suspend.h>
10#include <linux/sysfs.h>
11#include <asm/mach-au1x00/au1000.h>
12
13/*
14 * Generic suspend userspace interface for Alchemy development boards.
15 * This code exports a few sysfs nodes under /sys/power/db1x/ which
16 * can be used by userspace to en/disable all au1x-provided wakeup
17 * sources and configure the timeout after which the the TOYMATCH2 irq
18 * is to trigger a wakeup.
19 */
20
21
22static unsigned long db1x_pm_sleep_secs;
23static unsigned long db1x_pm_wakemsk;
24static unsigned long db1x_pm_last_wakesrc;
25
26static int db1x_pm_enter(suspend_state_t state)
27{
28 /* enable GPIO based wakeup */
29 au_writel(1, SYS_PININPUTEN);
30
31 /* clear and setup wake cause and source */
32 au_writel(0, SYS_WAKEMSK);
33 au_sync();
34 au_writel(0, SYS_WAKESRC);
35 au_sync();
36
37 au_writel(db1x_pm_wakemsk, SYS_WAKEMSK);
38 au_sync();
39
40 /* setup 1Hz-timer-based wakeup: wait for reg access */
41 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20)
42 asm volatile ("nop");
43
44 au_writel(au_readl(SYS_TOYREAD) + db1x_pm_sleep_secs, SYS_TOYMATCH2);
45 au_sync();
46
47 /* wait for value to really hit the register */
48 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20)
49 asm volatile ("nop");
50
51 /* ...and now the sandman can come! */
52 au_sleep();
53
54 return 0;
55}
56
57static int db1x_pm_begin(suspend_state_t state)
58{
59 if (!db1x_pm_wakemsk) {
60 printk(KERN_ERR "db1x: no wakeup source activated!\n");
61 return -EINVAL;
62 }
63
64 return 0;
65}
66
67static void db1x_pm_end(void)
68{
69 /* read and store wakeup source, the clear the register. To
70 * be able to clear it, WAKEMSK must be cleared first.
71 */
72 db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC);
73
74 au_writel(0, SYS_WAKEMSK);
75 au_writel(0, SYS_WAKESRC);
76 au_sync();
77
78}
79
80static struct platform_suspend_ops db1x_pm_ops = {
81 .valid = suspend_valid_only_mem,
82 .begin = db1x_pm_begin,
83 .enter = db1x_pm_enter,
84 .end = db1x_pm_end,
85};
86
87#define ATTRCMP(x) (0 == strcmp(attr->attr.name, #x))
88
89static ssize_t db1x_pmattr_show(struct kobject *kobj,
90 struct kobj_attribute *attr,
91 char *buf)
92{
93 int idx;
94
95 if (ATTRCMP(timer_timeout))
96 return sprintf(buf, "%lu\n", db1x_pm_sleep_secs);
97
98 else if (ATTRCMP(timer))
99 return sprintf(buf, "%u\n",
100 !!(db1x_pm_wakemsk & SYS_WAKEMSK_M2));
101
102 else if (ATTRCMP(wakesrc))
103 return sprintf(buf, "%lu\n", db1x_pm_last_wakesrc);
104
105 else if (ATTRCMP(gpio0) || ATTRCMP(gpio1) || ATTRCMP(gpio2) ||
106 ATTRCMP(gpio3) || ATTRCMP(gpio4) || ATTRCMP(gpio5) ||
107 ATTRCMP(gpio6) || ATTRCMP(gpio7)) {
108 idx = (attr->attr.name)[4] - '0';
109 return sprintf(buf, "%d\n",
110 !!(db1x_pm_wakemsk & SYS_WAKEMSK_GPIO(idx)));
111
112 } else if (ATTRCMP(wakemsk)) {
113 return sprintf(buf, "%08lx\n", db1x_pm_wakemsk);
114 }
115
116 return -ENOENT;
117}
118
119static ssize_t db1x_pmattr_store(struct kobject *kobj,
120 struct kobj_attribute *attr,
121 const char *instr,
122 size_t bytes)
123{
124 unsigned long l;
125 int tmp;
126
127 if (ATTRCMP(timer_timeout)) {
128 tmp = strict_strtoul(instr, 0, &l);
129 if (tmp)
130 return tmp;
131
132 db1x_pm_sleep_secs = l;
133
134 } else if (ATTRCMP(timer)) {
135 if (instr[0] != '0')
136 db1x_pm_wakemsk |= SYS_WAKEMSK_M2;
137 else
138 db1x_pm_wakemsk &= ~SYS_WAKEMSK_M2;
139
140 } else if (ATTRCMP(gpio0) || ATTRCMP(gpio1) || ATTRCMP(gpio2) ||
141 ATTRCMP(gpio3) || ATTRCMP(gpio4) || ATTRCMP(gpio5) ||
142 ATTRCMP(gpio6) || ATTRCMP(gpio7)) {
143 tmp = (attr->attr.name)[4] - '0';
144 if (instr[0] != '0') {
145 db1x_pm_wakemsk |= SYS_WAKEMSK_GPIO(tmp);
146 } else {
147 db1x_pm_wakemsk &= ~SYS_WAKEMSK_GPIO(tmp);
148 }
149
150 } else if (ATTRCMP(wakemsk)) {
151 tmp = strict_strtoul(instr, 0, &l);
152 if (tmp)
153 return tmp;
154
155 db1x_pm_wakemsk = l & 0x0000003f;
156
157 } else
158 bytes = -ENOENT;
159
160 return bytes;
161}
162
163#define ATTR(x) \
164 static struct kobj_attribute x##_attribute = \
165 __ATTR(x, 0664, db1x_pmattr_show, \
166 db1x_pmattr_store);
167
168ATTR(gpio0) /* GPIO-based wakeup enable */
169ATTR(gpio1)
170ATTR(gpio2)
171ATTR(gpio3)
172ATTR(gpio4)
173ATTR(gpio5)
174ATTR(gpio6)
175ATTR(gpio7)
176ATTR(timer) /* TOYMATCH2-based wakeup enable */
177ATTR(timer_timeout) /* timer-based wakeup timeout value, in seconds */
178ATTR(wakesrc) /* contents of SYS_WAKESRC after last wakeup */
179ATTR(wakemsk) /* direct access to SYS_WAKEMSK */
180
181#define ATTR_LIST(x) & x ## _attribute.attr
182static struct attribute *db1x_pmattrs[] = {
183 ATTR_LIST(gpio0),
184 ATTR_LIST(gpio1),
185 ATTR_LIST(gpio2),
186 ATTR_LIST(gpio3),
187 ATTR_LIST(gpio4),
188 ATTR_LIST(gpio5),
189 ATTR_LIST(gpio6),
190 ATTR_LIST(gpio7),
191 ATTR_LIST(timer),
192 ATTR_LIST(timer_timeout),
193 ATTR_LIST(wakesrc),
194 ATTR_LIST(wakemsk),
195 NULL, /* terminator */
196};
197
198static struct attribute_group db1x_pmattr_group = {
199 .name = "db1x",
200 .attrs = db1x_pmattrs,
201};
202
203/*
204 * Initialize suspend interface
205 */
206static int __init pm_init(void)
207{
208 /* init TOY to tick at 1Hz if not already done. No need to wait
209 * for confirmation since there's plenty of time from here to
210 * the next suspend cycle.
211 */
212 if (au_readl(SYS_TOYTRIM) != 32767) {
213 au_writel(32767, SYS_TOYTRIM);
214 au_sync();
215 }
216
217 db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC);
218
219 au_writel(0, SYS_WAKESRC);
220 au_sync();
221 au_writel(0, SYS_WAKEMSK);
222 au_sync();
223
224 suspend_set_ops(&db1x_pm_ops);
225
226 return sysfs_create_group(power_kobj, &db1x_pmattr_group);
227}
228
229late_initcall(pm_init);
diff --git a/arch/mips/alchemy/pb1550/init.c b/arch/mips/alchemy/devboards/prom.c
index e1055a13a1a0..0042bd6b1d7d 100644
--- a/arch/mips/alchemy/pb1550/init.c
+++ b/arch/mips/alchemy/devboards/prom.c
@@ -1,9 +1,9 @@
1/* 1/*
2 * Common code used by all Alchemy develboards.
2 * 3 *
3 * BRIEF MODULE DESCRIPTION 4 * Extracted from files which had this to say:
4 * Pb1550 board setup
5 * 5 *
6 * Copyright 2001, 2008 MontaVista Software Inc. 6 * Copyright 2000, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com> 7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
@@ -29,15 +29,19 @@
29 29
30#include <linux/init.h> 30#include <linux/init.h>
31#include <linux/kernel.h> 31#include <linux/kernel.h>
32
33#include <asm/bootinfo.h> 32#include <asm/bootinfo.h>
34 33#include <asm/mach-au1x00/au1000.h>
35#include <prom.h> 34#include <prom.h>
36 35
37const char *get_system_type(void) 36#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_DB1000) || \
38{ 37 defined(CONFIG_MIPS_PB1100) || defined(CONFIG_MIPS_DB1100) || \
39 return "Alchemy Pb1550"; 38 defined(CONFIG_MIPS_PB1500) || defined(CONFIG_MIPS_DB1500) || \
40} 39 defined(CONFIG_MIPS_BOSPORUS) || defined(CONFIG_MIPS_MIRAGE)
40#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x04000000
41
42#else /* Au1550/Au1200-based develboards */
43#define ALCHEMY_BOARD_DEFAULT_MEMSIZE 0x08000000
44#endif
41 45
42void __init prom_init(void) 46void __init prom_init(void)
43{ 47{
@@ -51,8 +55,8 @@ void __init prom_init(void)
51 prom_init_cmdline(); 55 prom_init_cmdline();
52 memsize_str = prom_getenv("memsize"); 56 memsize_str = prom_getenv("memsize");
53 if (!memsize_str) 57 if (!memsize_str)
54 memsize = 0x08000000; 58 memsize = ALCHEMY_BOARD_DEFAULT_MEMSIZE;
55 else 59 else
56 strict_strtol(memsize_str, 0, &memsize); 60 strict_strtoul(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM); 61 add_memory_region(0, memsize, BOOT_MEM_RAM);
58} 62}
diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c
index 3f8079186cf2..8ed1ae12bc55 100644
--- a/arch/mips/alchemy/mtx-1/board_setup.c
+++ b/arch/mips/alchemy/mtx-1/board_setup.c
@@ -32,6 +32,8 @@
32 32
33#include <asm/mach-au1x00/au1000.h> 33#include <asm/mach-au1x00/au1000.h>
34 34
35#include <prom.h>
36
35extern int (*board_pci_idsel)(unsigned int devsel, int assert); 37extern int (*board_pci_idsel)(unsigned int devsel, int assert);
36int mtx1_pci_idsel(unsigned int devsel, int assert); 38int mtx1_pci_idsel(unsigned int devsel, int assert);
37 39
@@ -43,6 +45,16 @@ void board_reset(void)
43 45
44void __init board_setup(void) 46void __init board_setup(void)
45{ 47{
48#ifdef CONFIG_SERIAL_8250_CONSOLE
49 char *argptr;
50 argptr = prom_getcmdline();
51 argptr = strstr(argptr, "console=");
52 if (argptr == NULL) {
53 argptr = prom_getcmdline();
54 strcat(argptr, " console=ttyS0,115200");
55 }
56#endif
57
46#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) 58#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
47 /* Enable USB power switch */ 59 /* Enable USB power switch */
48 au_writel(au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR); 60 au_writel(au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR);
diff --git a/arch/mips/alchemy/mtx-1/init.c b/arch/mips/alchemy/mtx-1/init.c
index 3bae13c28954..5e871c8d9e96 100644
--- a/arch/mips/alchemy/mtx-1/init.c
+++ b/arch/mips/alchemy/mtx-1/init.c
@@ -55,6 +55,6 @@ void __init prom_init(void)
55 if (!memsize_str) 55 if (!memsize_str)
56 memsize = 0x04000000; 56 memsize = 0x04000000;
57 else 57 else
58 strict_strtol(memsize_str, 0, &memsize); 58 strict_strtoul(memsize_str, 0, &memsize);
59 add_memory_region(0, memsize, BOOT_MEM_RAM); 59 add_memory_region(0, memsize, BOOT_MEM_RAM);
60} 60}
diff --git a/arch/mips/alchemy/mtx-1/irqmap.c b/arch/mips/alchemy/mtx-1/irqmap.c
index f2bf02951e9c..f1ab12ab3433 100644
--- a/arch/mips/alchemy/mtx-1/irqmap.c
+++ b/arch/mips/alchemy/mtx-1/irqmap.c
@@ -27,7 +27,7 @@
27 */ 27 */
28 28
29#include <linux/init.h> 29#include <linux/init.h>
30 30#include <linux/interrupt.h>
31#include <asm/mach-au1x00/au1000.h> 31#include <asm/mach-au1x00/au1000.h>
32 32
33char irq_tab_alchemy[][5] __initdata = { 33char irq_tab_alchemy[][5] __initdata = {
@@ -42,11 +42,15 @@ char irq_tab_alchemy[][5] __initdata = {
42}; 42};
43 43
44struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { 44struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
45 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0 }, 45 { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 },
46 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, 46 { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 },
47 { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 }, 47 { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 },
48 { AU1500_GPIO_203, INTC_INT_LOW_LEVEL, 0 }, 48 { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 },
49 { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, 49 { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 },
50}; 50};
51 51
52int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); 52
53void __init board_init_irq(void)
54{
55 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
56}
diff --git a/arch/mips/alchemy/pb1000/init.c b/arch/mips/alchemy/pb1000/init.c
deleted file mode 100644
index 8a9c7d57208d..000000000000
--- a/arch/mips/alchemy/pb1000/init.c
+++ /dev/null
@@ -1,57 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Pb1000 board setup
4 *
5 * Copyright 2001, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30#include <linux/kernel.h>
31
32#include <asm/bootinfo.h>
33
34#include <prom.h>
35
36const char *get_system_type(void)
37{
38 return "Alchemy Pb1000";
39}
40
41void __init prom_init(void)
42{
43 unsigned char *memsize_str;
44 unsigned long memsize;
45
46 prom_argc = (int)fw_arg0;
47 prom_argv = (char **)fw_arg1;
48 prom_envp = (char **)fw_arg2;
49
50 prom_init_cmdline();
51 memsize_str = prom_getenv("memsize");
52 if (!memsize_str)
53 memsize = 0x04000000;
54 else
55 strict_strtol(memsize_str, 0, &memsize);
56 add_memory_region(0, memsize, BOOT_MEM_RAM);
57}
diff --git a/arch/mips/alchemy/pb1000/irqmap.c b/arch/mips/alchemy/pb1000/irqmap.c
deleted file mode 100644
index b3d56b0af321..000000000000
--- a/arch/mips/alchemy/pb1000/irqmap.c
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx irq map table
4 *
5 * Copyright 2003 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30#include <linux/interrupt.h>
31
32#include <asm/mach-au1x00/au1000.h>
33
34struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
35 { AU1000_GPIO_15, INTC_INT_LOW_LEVEL, 0 },
36};
37
38int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/alchemy/pb1100/init.c b/arch/mips/alchemy/pb1100/init.c
deleted file mode 100644
index 7c6792308bc5..000000000000
--- a/arch/mips/alchemy/pb1100/init.c
+++ /dev/null
@@ -1,60 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Pb1100 board setup
5 *
6 * Copyright 2002, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/init.h>
31#include <linux/kernel.h>
32
33#include <asm/bootinfo.h>
34
35#include <prom.h>
36
37const char *get_system_type(void)
38{
39 return "Alchemy Pb1100";
40}
41
42void __init prom_init(void)
43{
44 unsigned char *memsize_str;
45 unsigned long memsize;
46
47 prom_argc = fw_arg0;
48 prom_argv = (char **)fw_arg1;
49 prom_envp = (char **)fw_arg3;
50
51 prom_init_cmdline();
52
53 memsize_str = prom_getenv("memsize");
54 if (!memsize_str)
55 memsize = 0x04000000;
56 else
57 strict_strtol(memsize_str, 0, &memsize);
58
59 add_memory_region(0, memsize, BOOT_MEM_RAM);
60}
diff --git a/arch/mips/alchemy/pb1100/irqmap.c b/arch/mips/alchemy/pb1100/irqmap.c
deleted file mode 100644
index 9b7dd8b41283..000000000000
--- a/arch/mips/alchemy/pb1100/irqmap.c
+++ /dev/null
@@ -1,40 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xx0 IRQ map table
4 *
5 * Copyright 2003 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30
31#include <asm/mach-au1x00/au1000.h>
32
33struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
34 { AU1000_GPIO_9, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card Fully_Inserted# */
35 { AU1000_GPIO_10, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card STSCHG# */
36 { AU1000_GPIO_11, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card IRQ# */
37 { AU1000_GPIO_13, INTC_INT_LOW_LEVEL, 0 }, /* DC_IRQ# */
38};
39
40int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/alchemy/pb1200/init.c b/arch/mips/alchemy/pb1200/init.c
deleted file mode 100644
index e9b2a0fd48ae..000000000000
--- a/arch/mips/alchemy/pb1200/init.c
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PB1200 board setup
5 *
6 * Copyright 2001, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/init.h>
31#include <linux/kernel.h>
32
33#include <asm/bootinfo.h>
34
35#include <prom.h>
36
37const char *get_system_type(void)
38{
39 return "Alchemy Pb1200";
40}
41
42void __init prom_init(void)
43{
44 unsigned char *memsize_str;
45 unsigned long memsize;
46
47 prom_argc = (int)fw_arg0;
48 prom_argv = (char **)fw_arg1;
49 prom_envp = (char **)fw_arg2;
50
51 prom_init_cmdline();
52 memsize_str = prom_getenv("memsize");
53 if (!memsize_str)
54 memsize = 0x08000000;
55 else
56 strict_strtol(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58}
diff --git a/arch/mips/alchemy/pb1500/init.c b/arch/mips/alchemy/pb1500/init.c
deleted file mode 100644
index 3b6e395cf952..000000000000
--- a/arch/mips/alchemy/pb1500/init.c
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Pb1500 board setup
5 *
6 * Copyright 2001, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/init.h>
31#include <linux/kernel.h>
32
33#include <asm/bootinfo.h>
34
35#include <prom.h>
36
37const char *get_system_type(void)
38{
39 return "Alchemy Pb1500";
40}
41
42void __init prom_init(void)
43{
44 unsigned char *memsize_str;
45 unsigned long memsize;
46
47 prom_argc = (int)fw_arg0;
48 prom_argv = (char **)fw_arg1;
49 prom_envp = (char **)fw_arg2;
50
51 prom_init_cmdline();
52 memsize_str = prom_getenv("memsize");
53 if (!memsize_str)
54 memsize = 0x04000000;
55 else
56 strict_strtol(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58}
diff --git a/arch/mips/alchemy/pb1500/irqmap.c b/arch/mips/alchemy/pb1500/irqmap.c
deleted file mode 100644
index 39c4682766a8..000000000000
--- a/arch/mips/alchemy/pb1500/irqmap.c
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx irq map table
4 *
5 * Copyright 2003 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30
31#include <asm/mach-au1x00/au1000.h>
32
33char irq_tab_alchemy[][5] __initdata = {
34 [12] = { -1, INTA, INTX, INTX, INTX }, /* IDSEL 12 - HPT370 */
35 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot */
36};
37
38struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
39 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0 },
40 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 },
41 { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 },
42 { AU1500_GPIO_203, INTC_INT_LOW_LEVEL, 0 },
43 { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 },
44};
45
46int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/alchemy/pb1550/irqmap.c b/arch/mips/alchemy/pb1550/irqmap.c
deleted file mode 100644
index a02a4d1fa899..000000000000
--- a/arch/mips/alchemy/pb1550/irqmap.c
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xx0 IRQ map table
4 *
5 * Copyright 2003 Embedded Edge, LLC
6 * dan@embeddededge.com
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/init.h>
30
31#include <asm/mach-au1x00/au1000.h>
32
33char irq_tab_alchemy[][5] __initdata = {
34 [12] = { -1, INTB, INTC, INTD, INTA }, /* IDSEL 12 - PCI slot 2 (left) */
35 [13] = { -1, INTA, INTB, INTC, INTD }, /* IDSEL 13 - PCI slot 1 (right) */
36};
37
38struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
39 { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 },
40 { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 },
41};
42
43int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c
index 4c587acac5c3..a2634fabc50d 100644
--- a/arch/mips/alchemy/xxs1500/board_setup.c
+++ b/arch/mips/alchemy/xxs1500/board_setup.c
@@ -28,6 +28,8 @@
28 28
29#include <asm/mach-au1x00/au1000.h> 29#include <asm/mach-au1x00/au1000.h>
30 30
31#include <prom.h>
32
31void board_reset(void) 33void board_reset(void)
32{ 34{
33 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 35 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */
@@ -38,6 +40,16 @@ void __init board_setup(void)
38{ 40{
39 u32 pin_func; 41 u32 pin_func;
40 42
43#ifdef CONFIG_SERIAL_8250_CONSOLE
44 char *argptr;
45 argptr = prom_getcmdline();
46 argptr = strstr(argptr, "console=");
47 if (argptr == NULL) {
48 argptr = prom_getcmdline();
49 strcat(argptr, " console=ttyS0,115200");
50 }
51#endif
52
41 /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */ 53 /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */
42 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3; 54 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
43 pin_func |= SYS_PF_UR3; 55 pin_func |= SYS_PF_UR3;
diff --git a/arch/mips/alchemy/xxs1500/init.c b/arch/mips/alchemy/xxs1500/init.c
index 7516434760a1..456fa142c093 100644
--- a/arch/mips/alchemy/xxs1500/init.c
+++ b/arch/mips/alchemy/xxs1500/init.c
@@ -53,6 +53,6 @@ void __init prom_init(void)
53 if (!memsize_str) 53 if (!memsize_str)
54 memsize = 0x04000000; 54 memsize = 0x04000000;
55 else 55 else
56 strict_strtol(memsize_str, 0, &memsize); 56 strict_strtoul(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM); 57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58} 58}
diff --git a/arch/mips/alchemy/xxs1500/irqmap.c b/arch/mips/alchemy/xxs1500/irqmap.c
index edf06ed11870..0f0f3012e5fd 100644
--- a/arch/mips/alchemy/xxs1500/irqmap.c
+++ b/arch/mips/alchemy/xxs1500/irqmap.c
@@ -27,23 +27,26 @@
27 */ 27 */
28 28
29#include <linux/init.h> 29#include <linux/init.h>
30 30#include <linux/interrupt.h>
31#include <asm/mach-au1x00/au1000.h> 31#include <asm/mach-au1x00/au1000.h>
32 32
33struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { 33struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
34 { AU1500_GPIO_204, INTC_INT_HIGH_LEVEL, 0 }, 34 { AU1500_GPIO_204, IRQF_TRIGGER_HIGH, 0 },
35 { AU1500_GPIO_201, INTC_INT_LOW_LEVEL, 0 }, 35 { AU1500_GPIO_201, IRQF_TRIGGER_LOW, 0 },
36 { AU1500_GPIO_202, INTC_INT_LOW_LEVEL, 0 }, 36 { AU1500_GPIO_202, IRQF_TRIGGER_LOW, 0 },
37 { AU1500_GPIO_203, INTC_INT_LOW_LEVEL, 0 }, 37 { AU1500_GPIO_203, IRQF_TRIGGER_LOW, 0 },
38 { AU1500_GPIO_205, INTC_INT_LOW_LEVEL, 0 }, 38 { AU1500_GPIO_205, IRQF_TRIGGER_LOW, 0 },
39 { AU1500_GPIO_207, INTC_INT_LOW_LEVEL, 0 }, 39 { AU1500_GPIO_207, IRQF_TRIGGER_LOW, 0 },
40 40
41 { AU1000_GPIO_0, INTC_INT_LOW_LEVEL, 0 }, 41 { AU1000_GPIO_0, IRQF_TRIGGER_LOW, 0 },
42 { AU1000_GPIO_1, INTC_INT_LOW_LEVEL, 0 }, 42 { AU1000_GPIO_1, IRQF_TRIGGER_LOW, 0 },
43 { AU1000_GPIO_2, INTC_INT_LOW_LEVEL, 0 }, 43 { AU1000_GPIO_2, IRQF_TRIGGER_LOW, 0 },
44 { AU1000_GPIO_3, INTC_INT_LOW_LEVEL, 0 }, 44 { AU1000_GPIO_3, IRQF_TRIGGER_LOW, 0 },
45 { AU1000_GPIO_4, INTC_INT_LOW_LEVEL, 0 }, /* CF interrupt */ 45 { AU1000_GPIO_4, IRQF_TRIGGER_LOW, 0 }, /* CF interrupt */
46 { AU1000_GPIO_5, INTC_INT_LOW_LEVEL, 0 }, 46 { AU1000_GPIO_5, IRQF_TRIGGER_LOW, 0 },
47}; 47};
48 48
49int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); 49void __init board_init_irq(void)
50{
51 au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map));
52}
diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig
new file mode 100644
index 000000000000..094c17e38e16
--- /dev/null
+++ b/arch/mips/cavium-octeon/Kconfig
@@ -0,0 +1,85 @@
1config CAVIUM_OCTEON_SPECIFIC_OPTIONS
2 bool "Enable Octeon specific options"
3 depends on CPU_CAVIUM_OCTEON
4 default "y"
5
6config CAVIUM_OCTEON_2ND_KERNEL
7 bool "Build the kernel to be used as a 2nd kernel on the same chip"
8 depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
9 default "n"
10 help
11 This option configures this kernel to be linked at a different
12 address and use the 2nd uart for output. This allows a kernel built
13 with this option to be run at the same time as one built without this
14 option.
15
16config CAVIUM_OCTEON_HW_FIX_UNALIGNED
17 bool "Enable hardware fixups of unaligned loads and stores"
18 depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
19 default "y"
20 help
21 Configure the Octeon hardware to automatically fix unaligned loads
22 and stores. Normally unaligned accesses are fixed using a kernel
23 exception handler. This option enables the hardware automatic fixups,
24 which requires only an extra 3 cycles. Disable this option if you
25 are running code that relies on address exceptions on unaligned
26 accesses.
27
28config CAVIUM_OCTEON_CVMSEG_SIZE
29 int "Number of L1 cache lines reserved for CVMSEG memory"
30 depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
31 range 0 54
32 default 1
33 help
34 CVMSEG LM is a segment that accesses portions of the dcache as a
35 local memory; the larger CVMSEG is, the smaller the cache is.
36 This selects the size of CVMSEG LM, which is in cache blocks. The
37 legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is
38 between zero and 6192 bytes).
39
40config CAVIUM_OCTEON_LOCK_L2
41 bool "Lock often used kernel code in the L2"
42 depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
43 default "y"
44 help
45 Enable locking parts of the kernel into the L2 cache.
46
47config CAVIUM_OCTEON_LOCK_L2_TLB
48 bool "Lock the TLB handler in L2"
49 depends on CAVIUM_OCTEON_LOCK_L2
50 default "y"
51 help
52 Lock the low level TLB fast path into L2.
53
54config CAVIUM_OCTEON_LOCK_L2_EXCEPTION
55 bool "Lock the exception handler in L2"
56 depends on CAVIUM_OCTEON_LOCK_L2
57 default "y"
58 help
59 Lock the low level exception handler into L2.
60
61config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
62 bool "Lock the interrupt handler in L2"
63 depends on CAVIUM_OCTEON_LOCK_L2
64 default "y"
65 help
66 Lock the low level interrupt handler into L2.
67
68config CAVIUM_OCTEON_LOCK_L2_INTERRUPT
69 bool "Lock the 2nd level interrupt handler in L2"
70 depends on CAVIUM_OCTEON_LOCK_L2
71 default "y"
72 help
73 Lock the 2nd level interrupt handler in L2.
74
75config CAVIUM_OCTEON_LOCK_L2_MEMCPY
76 bool "Lock memcpy() in L2"
77 depends on CAVIUM_OCTEON_LOCK_L2
78 default "y"
79 help
80 Lock the kernel's implementation of memcpy() into L2.
81
82config ARCH_SPARSEMEM_ENABLE
83 def_bool y
84 select SPARSEMEM_STATIC
85 depends on CPU_CAVIUM_OCTEON
diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
new file mode 100644
index 000000000000..1c2a7faf5881
--- /dev/null
+++ b/arch/mips/cavium-octeon/Makefile
@@ -0,0 +1,16 @@
1#
2# Makefile for the Cavium Octeon specific kernel interface routines
3# under Linux.
4#
5# This file is subject to the terms and conditions of the GNU General Public
6# License. See the file "COPYING" in the main directory of this archive
7# for more details.
8#
9# Copyright (C) 2005-2008 Cavium Networks
10#
11
12obj-y := setup.o serial.o octeon-irq.o csrc-octeon.o
13obj-y += dma-octeon.o flash_setup.o
14obj-y += octeon-memcpy.o
15
16obj-$(CONFIG_SMP) += smp.o
diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c
new file mode 100644
index 000000000000..70fd92c31657
--- /dev/null
+++ b/arch/mips/cavium-octeon/csrc-octeon.c
@@ -0,0 +1,58 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2007 by Ralf Baechle
7 */
8#include <linux/clocksource.h>
9#include <linux/init.h>
10
11#include <asm/time.h>
12
13#include <asm/octeon/octeon.h>
14#include <asm/octeon/cvmx-ipd-defs.h>
15
16/*
17 * Set the current core's cvmcount counter to the value of the
18 * IPD_CLK_COUNT. We do this on all cores as they are brought
19 * on-line. This allows for a read from a local cpu register to
20 * access a synchronized counter.
21 *
22 */
23void octeon_init_cvmcount(void)
24{
25 unsigned long flags;
26 unsigned loops = 2;
27
28 /* Clobber loops so GCC will not unroll the following while loop. */
29 asm("" : "+r" (loops));
30
31 local_irq_save(flags);
32 /*
33 * Loop several times so we are executing from the cache,
34 * which should give more deterministic timing.
35 */
36 while (loops--)
37 write_c0_cvmcount(cvmx_read_csr(CVMX_IPD_CLK_COUNT));
38 local_irq_restore(flags);
39}
40
41static cycle_t octeon_cvmcount_read(void)
42{
43 return read_c0_cvmcount();
44}
45
46static struct clocksource clocksource_mips = {
47 .name = "OCTEON_CVMCOUNT",
48 .read = octeon_cvmcount_read,
49 .mask = CLOCKSOURCE_MASK(64),
50 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
51};
52
53void __init plat_time_init(void)
54{
55 clocksource_mips.rating = 300;
56 clocksource_set_clock(&clocksource_mips, mips_hpt_frequency);
57 clocksource_register(&clocksource_mips);
58}
diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
new file mode 100644
index 000000000000..01b1ef94b361
--- /dev/null
+++ b/arch/mips/cavium-octeon/dma-octeon.c
@@ -0,0 +1,32 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2000 Ani Joshi <ajoshi@unixbox.com>
7 * Copyright (C) 2000, 2001 Ralf Baechle <ralf@gnu.org>
8 * Copyright (C) 2005 Ilya A. Volynets-Evenbakh <ilya@total-knowledge.com>
9 * swiped from i386, and cloned for MIPS by Geert, polished by Ralf.
10 * IP32 changes by Ilya.
11 * Cavium Networks: Create new dma setup for Cavium Networks Octeon based on
12 * the kernels original.
13 */
14#include <linux/types.h>
15#include <linux/mm.h>
16
17#include <dma-coherence.h>
18
19dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
20{
21 /* Without PCI/PCIe this function can be called for Octeon internal
22 devices such as USB. These devices all support 64bit addressing */
23 mb();
24 return virt_to_phys(ptr);
25}
26
27void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
28{
29 /* Without PCI/PCIe this function can be called for Octeon internal
30 * devices such as USB. These devices all support 64bit addressing */
31 return;
32}
diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile
new file mode 100644
index 000000000000..80d6cb26766b
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/Makefile
@@ -0,0 +1,13 @@
1#
2# Makefile for the Cavium Octeon specific kernel interface routines
3# under Linux.
4#
5# This file is subject to the terms and conditions of the GNU General Public
6# License. See the file "COPYING" in the main directory of this archive
7# for more details.
8#
9# Copyright (C) 2005-2008 Cavium Networks
10#
11
12obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
13
diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
new file mode 100644
index 000000000000..4f5a08b37ccd
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c
@@ -0,0 +1,586 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Simple allocate only memory allocator. Used to allocate memory at
30 * application start time.
31 */
32
33#include <linux/kernel.h>
34
35#include <asm/octeon/cvmx.h>
36#include <asm/octeon/cvmx-spinlock.h>
37#include <asm/octeon/cvmx-bootmem.h>
38
39/*#define DEBUG */
40
41
42static struct cvmx_bootmem_desc *cvmx_bootmem_desc;
43
44/* See header file for descriptions of functions */
45
46/*
47 * Wrapper functions are provided for reading/writing the size and
48 * next block values as these may not be directly addressible (in 32
49 * bit applications, for instance.) Offsets of data elements in
50 * bootmem list, must match cvmx_bootmem_block_header_t.
51 */
52#define NEXT_OFFSET 0
53#define SIZE_OFFSET 8
54
55static void cvmx_bootmem_phy_set_size(uint64_t addr, uint64_t size)
56{
57 cvmx_write64_uint64((addr + SIZE_OFFSET) | (1ull << 63), size);
58}
59
60static void cvmx_bootmem_phy_set_next(uint64_t addr, uint64_t next)
61{
62 cvmx_write64_uint64((addr + NEXT_OFFSET) | (1ull << 63), next);
63}
64
65static uint64_t cvmx_bootmem_phy_get_size(uint64_t addr)
66{
67 return cvmx_read64_uint64((addr + SIZE_OFFSET) | (1ull << 63));
68}
69
70static uint64_t cvmx_bootmem_phy_get_next(uint64_t addr)
71{
72 return cvmx_read64_uint64((addr + NEXT_OFFSET) | (1ull << 63));
73}
74
75void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment,
76 uint64_t min_addr, uint64_t max_addr)
77{
78 int64_t address;
79 address =
80 cvmx_bootmem_phy_alloc(size, min_addr, max_addr, alignment, 0);
81
82 if (address > 0)
83 return cvmx_phys_to_ptr(address);
84 else
85 return NULL;
86}
87
88void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address,
89 uint64_t alignment)
90{
91 return cvmx_bootmem_alloc_range(size, alignment, address,
92 address + size);
93}
94
95void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment)
96{
97 return cvmx_bootmem_alloc_range(size, alignment, 0, 0);
98}
99
100int cvmx_bootmem_free_named(char *name)
101{
102 return cvmx_bootmem_phy_named_block_free(name, 0);
103}
104
105struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name)
106{
107 return cvmx_bootmem_phy_named_block_find(name, 0);
108}
109
110void cvmx_bootmem_lock(void)
111{
112 cvmx_spinlock_lock((cvmx_spinlock_t *) &(cvmx_bootmem_desc->lock));
113}
114
115void cvmx_bootmem_unlock(void)
116{
117 cvmx_spinlock_unlock((cvmx_spinlock_t *) &(cvmx_bootmem_desc->lock));
118}
119
120int cvmx_bootmem_init(void *mem_desc_ptr)
121{
122 /* Here we set the global pointer to the bootmem descriptor
123 * block. This pointer will be used directly, so we will set
124 * it up to be directly usable by the application. It is set
125 * up as follows for the various runtime/ABI combinations:
126 *
127 * Linux 64 bit: Set XKPHYS bit
128 * Linux 32 bit: use mmap to create mapping, use virtual address
129 * CVMX 64 bit: use physical address directly
130 * CVMX 32 bit: use physical address directly
131 *
132 * Note that the CVMX environment assumes the use of 1-1 TLB
133 * mappings so that the physical addresses can be used
134 * directly
135 */
136 if (!cvmx_bootmem_desc) {
137#if defined(CVMX_ABI_64)
138 /* Set XKPHYS bit */
139 cvmx_bootmem_desc = cvmx_phys_to_ptr(CAST64(mem_desc_ptr));
140#else
141 cvmx_bootmem_desc = (struct cvmx_bootmem_desc *) mem_desc_ptr;
142#endif
143 }
144
145 return 0;
146}
147
148/*
149 * The cvmx_bootmem_phy* functions below return 64 bit physical
150 * addresses, and expose more features that the cvmx_bootmem_functions
151 * above. These are required for full memory space access in 32 bit
152 * applications, as well as for using some advance features. Most
153 * applications should not need to use these.
154 */
155
156int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
157 uint64_t address_max, uint64_t alignment,
158 uint32_t flags)
159{
160
161 uint64_t head_addr;
162 uint64_t ent_addr;
163 /* points to previous list entry, NULL current entry is head of list */
164 uint64_t prev_addr = 0;
165 uint64_t new_ent_addr = 0;
166 uint64_t desired_min_addr;
167
168#ifdef DEBUG
169 cvmx_dprintf("cvmx_bootmem_phy_alloc: req_size: 0x%llx, "
170 "min_addr: 0x%llx, max_addr: 0x%llx, align: 0x%llx\n",
171 (unsigned long long)req_size,
172 (unsigned long long)address_min,
173 (unsigned long long)address_max,
174 (unsigned long long)alignment);
175#endif
176
177 if (cvmx_bootmem_desc->major_version > 3) {
178 cvmx_dprintf("ERROR: Incompatible bootmem descriptor "
179 "version: %d.%d at addr: %p\n",
180 (int)cvmx_bootmem_desc->major_version,
181 (int)cvmx_bootmem_desc->minor_version,
182 cvmx_bootmem_desc);
183 goto error_out;
184 }
185
186 /*
187 * Do a variety of checks to validate the arguments. The
188 * allocator code will later assume that these checks have
189 * been made. We validate that the requested constraints are
190 * not self-contradictory before we look through the list of
191 * available memory.
192 */
193
194 /* 0 is not a valid req_size for this allocator */
195 if (!req_size)
196 goto error_out;
197
198 /* Round req_size up to mult of minimum alignment bytes */
199 req_size = (req_size + (CVMX_BOOTMEM_ALIGNMENT_SIZE - 1)) &
200 ~(CVMX_BOOTMEM_ALIGNMENT_SIZE - 1);
201
202 /*
203 * Convert !0 address_min and 0 address_max to special case of
204 * range that specifies an exact memory block to allocate. Do
205 * this before other checks and adjustments so that this
206 * tranformation will be validated.
207 */
208 if (address_min && !address_max)
209 address_max = address_min + req_size;
210 else if (!address_min && !address_max)
211 address_max = ~0ull; /* If no limits given, use max limits */
212
213
214 /*
215 * Enforce minimum alignment (this also keeps the minimum free block
216 * req_size the same as the alignment req_size.
217 */
218 if (alignment < CVMX_BOOTMEM_ALIGNMENT_SIZE)
219 alignment = CVMX_BOOTMEM_ALIGNMENT_SIZE;
220
221 /*
222 * Adjust address minimum based on requested alignment (round
223 * up to meet alignment). Do this here so we can reject
224 * impossible requests up front. (NOP for address_min == 0)
225 */
226 if (alignment)
227 address_min = __ALIGN_MASK(address_min, (alignment - 1));
228
229 /*
230 * Reject inconsistent args. We have adjusted these, so this
231 * may fail due to our internal changes even if this check
232 * would pass for the values the user supplied.
233 */
234 if (req_size > address_max - address_min)
235 goto error_out;
236
237 /* Walk through the list entries - first fit found is returned */
238
239 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
240 cvmx_bootmem_lock();
241 head_addr = cvmx_bootmem_desc->head_addr;
242 ent_addr = head_addr;
243 for (; ent_addr;
244 prev_addr = ent_addr,
245 ent_addr = cvmx_bootmem_phy_get_next(ent_addr)) {
246 uint64_t usable_base, usable_max;
247 uint64_t ent_size = cvmx_bootmem_phy_get_size(ent_addr);
248
249 if (cvmx_bootmem_phy_get_next(ent_addr)
250 && ent_addr > cvmx_bootmem_phy_get_next(ent_addr)) {
251 cvmx_dprintf("Internal bootmem_alloc() error: ent: "
252 "0x%llx, next: 0x%llx\n",
253 (unsigned long long)ent_addr,
254 (unsigned long long)
255 cvmx_bootmem_phy_get_next(ent_addr));
256 goto error_out;
257 }
258
259 /*
260 * Determine if this is an entry that can satisify the
261 * request Check to make sure entry is large enough to
262 * satisfy request.
263 */
264 usable_base =
265 __ALIGN_MASK(max(address_min, ent_addr), alignment - 1);
266 usable_max = min(address_max, ent_addr + ent_size);
267 /*
268 * We should be able to allocate block at address
269 * usable_base.
270 */
271
272 desired_min_addr = usable_base;
273 /*
274 * Determine if request can be satisfied from the
275 * current entry.
276 */
277 if (!((ent_addr + ent_size) > usable_base
278 && ent_addr < address_max
279 && req_size <= usable_max - usable_base))
280 continue;
281 /*
282 * We have found an entry that has room to satisfy the
283 * request, so allocate it from this entry. If end
284 * CVMX_BOOTMEM_FLAG_END_ALLOC set, then allocate from
285 * the end of this block rather than the beginning.
286 */
287 if (flags & CVMX_BOOTMEM_FLAG_END_ALLOC) {
288 desired_min_addr = usable_max - req_size;
289 /*
290 * Align desired address down to required
291 * alignment.
292 */
293 desired_min_addr &= ~(alignment - 1);
294 }
295
296 /* Match at start of entry */
297 if (desired_min_addr == ent_addr) {
298 if (req_size < ent_size) {
299 /*
300 * big enough to create a new block
301 * from top portion of block.
302 */
303 new_ent_addr = ent_addr + req_size;
304 cvmx_bootmem_phy_set_next(new_ent_addr,
305 cvmx_bootmem_phy_get_next(ent_addr));
306 cvmx_bootmem_phy_set_size(new_ent_addr,
307 ent_size -
308 req_size);
309
310 /*
311 * Adjust next pointer as following
312 * code uses this.
313 */
314 cvmx_bootmem_phy_set_next(ent_addr,
315 new_ent_addr);
316 }
317
318 /*
319 * adjust prev ptr or head to remove this
320 * entry from list.
321 */
322 if (prev_addr)
323 cvmx_bootmem_phy_set_next(prev_addr,
324 cvmx_bootmem_phy_get_next(ent_addr));
325 else
326 /*
327 * head of list being returned, so
328 * update head ptr.
329 */
330 cvmx_bootmem_desc->head_addr =
331 cvmx_bootmem_phy_get_next(ent_addr);
332
333 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
334 cvmx_bootmem_unlock();
335 return desired_min_addr;
336 }
337 /*
338 * block returned doesn't start at beginning of entry,
339 * so we know that we will be splitting a block off
340 * the front of this one. Create a new block from the
341 * beginning, add to list, and go to top of loop
342 * again.
343 *
344 * create new block from high portion of
345 * block, so that top block starts at desired
346 * addr.
347 */
348 new_ent_addr = desired_min_addr;
349 cvmx_bootmem_phy_set_next(new_ent_addr,
350 cvmx_bootmem_phy_get_next
351 (ent_addr));
352 cvmx_bootmem_phy_set_size(new_ent_addr,
353 cvmx_bootmem_phy_get_size
354 (ent_addr) -
355 (desired_min_addr -
356 ent_addr));
357 cvmx_bootmem_phy_set_size(ent_addr,
358 desired_min_addr - ent_addr);
359 cvmx_bootmem_phy_set_next(ent_addr, new_ent_addr);
360 /* Loop again to handle actual alloc from new block */
361 }
362error_out:
363 /* We didn't find anything, so return error */
364 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
365 cvmx_bootmem_unlock();
366 return -1;
367}
368
369int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags)
370{
371 uint64_t cur_addr;
372 uint64_t prev_addr = 0; /* zero is invalid */
373 int retval = 0;
374
375#ifdef DEBUG
376 cvmx_dprintf("__cvmx_bootmem_phy_free addr: 0x%llx, size: 0x%llx\n",
377 (unsigned long long)phy_addr, (unsigned long long)size);
378#endif
379 if (cvmx_bootmem_desc->major_version > 3) {
380 cvmx_dprintf("ERROR: Incompatible bootmem descriptor "
381 "version: %d.%d at addr: %p\n",
382 (int)cvmx_bootmem_desc->major_version,
383 (int)cvmx_bootmem_desc->minor_version,
384 cvmx_bootmem_desc);
385 return 0;
386 }
387
388 /* 0 is not a valid size for this allocator */
389 if (!size)
390 return 0;
391
392 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
393 cvmx_bootmem_lock();
394 cur_addr = cvmx_bootmem_desc->head_addr;
395 if (cur_addr == 0 || phy_addr < cur_addr) {
396 /* add at front of list - special case with changing head ptr */
397 if (cur_addr && phy_addr + size > cur_addr)
398 goto bootmem_free_done; /* error, overlapping section */
399 else if (phy_addr + size == cur_addr) {
400 /* Add to front of existing first block */
401 cvmx_bootmem_phy_set_next(phy_addr,
402 cvmx_bootmem_phy_get_next
403 (cur_addr));
404 cvmx_bootmem_phy_set_size(phy_addr,
405 cvmx_bootmem_phy_get_size
406 (cur_addr) + size);
407 cvmx_bootmem_desc->head_addr = phy_addr;
408
409 } else {
410 /* New block before first block. OK if cur_addr is 0 */
411 cvmx_bootmem_phy_set_next(phy_addr, cur_addr);
412 cvmx_bootmem_phy_set_size(phy_addr, size);
413 cvmx_bootmem_desc->head_addr = phy_addr;
414 }
415 retval = 1;
416 goto bootmem_free_done;
417 }
418
419 /* Find place in list to add block */
420 while (cur_addr && phy_addr > cur_addr) {
421 prev_addr = cur_addr;
422 cur_addr = cvmx_bootmem_phy_get_next(cur_addr);
423 }
424
425 if (!cur_addr) {
426 /*
427 * We have reached the end of the list, add on to end,
428 * checking to see if we need to combine with last
429 * block
430 */
431 if (prev_addr + cvmx_bootmem_phy_get_size(prev_addr) ==
432 phy_addr) {
433 cvmx_bootmem_phy_set_size(prev_addr,
434 cvmx_bootmem_phy_get_size
435 (prev_addr) + size);
436 } else {
437 cvmx_bootmem_phy_set_next(prev_addr, phy_addr);
438 cvmx_bootmem_phy_set_size(phy_addr, size);
439 cvmx_bootmem_phy_set_next(phy_addr, 0);
440 }
441 retval = 1;
442 goto bootmem_free_done;
443 } else {
444 /*
445 * insert between prev and cur nodes, checking for
446 * merge with either/both.
447 */
448 if (prev_addr + cvmx_bootmem_phy_get_size(prev_addr) ==
449 phy_addr) {
450 /* Merge with previous */
451 cvmx_bootmem_phy_set_size(prev_addr,
452 cvmx_bootmem_phy_get_size
453 (prev_addr) + size);
454 if (phy_addr + size == cur_addr) {
455 /* Also merge with current */
456 cvmx_bootmem_phy_set_size(prev_addr,
457 cvmx_bootmem_phy_get_size(cur_addr) +
458 cvmx_bootmem_phy_get_size(prev_addr));
459 cvmx_bootmem_phy_set_next(prev_addr,
460 cvmx_bootmem_phy_get_next(cur_addr));
461 }
462 retval = 1;
463 goto bootmem_free_done;
464 } else if (phy_addr + size == cur_addr) {
465 /* Merge with current */
466 cvmx_bootmem_phy_set_size(phy_addr,
467 cvmx_bootmem_phy_get_size
468 (cur_addr) + size);
469 cvmx_bootmem_phy_set_next(phy_addr,
470 cvmx_bootmem_phy_get_next
471 (cur_addr));
472 cvmx_bootmem_phy_set_next(prev_addr, phy_addr);
473 retval = 1;
474 goto bootmem_free_done;
475 }
476
477 /* It is a standalone block, add in between prev and cur */
478 cvmx_bootmem_phy_set_size(phy_addr, size);
479 cvmx_bootmem_phy_set_next(phy_addr, cur_addr);
480 cvmx_bootmem_phy_set_next(prev_addr, phy_addr);
481
482 }
483 retval = 1;
484
485bootmem_free_done:
486 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
487 cvmx_bootmem_unlock();
488 return retval;
489
490}
491
492struct cvmx_bootmem_named_block_desc *
493 cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags)
494{
495 unsigned int i;
496 struct cvmx_bootmem_named_block_desc *named_block_array_ptr;
497
498#ifdef DEBUG
499 cvmx_dprintf("cvmx_bootmem_phy_named_block_find: %s\n", name);
500#endif
501 /*
502 * Lock the structure to make sure that it is not being
503 * changed while we are examining it.
504 */
505 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
506 cvmx_bootmem_lock();
507
508 /* Use XKPHYS for 64 bit linux */
509 named_block_array_ptr = (struct cvmx_bootmem_named_block_desc *)
510 cvmx_phys_to_ptr(cvmx_bootmem_desc->named_block_array_addr);
511
512#ifdef DEBUG
513 cvmx_dprintf
514 ("cvmx_bootmem_phy_named_block_find: named_block_array_ptr: %p\n",
515 named_block_array_ptr);
516#endif
517 if (cvmx_bootmem_desc->major_version == 3) {
518 for (i = 0;
519 i < cvmx_bootmem_desc->named_block_num_blocks; i++) {
520 if ((name && named_block_array_ptr[i].size
521 && !strncmp(name, named_block_array_ptr[i].name,
522 cvmx_bootmem_desc->named_block_name_len
523 - 1))
524 || (!name && !named_block_array_ptr[i].size)) {
525 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
526 cvmx_bootmem_unlock();
527
528 return &(named_block_array_ptr[i]);
529 }
530 }
531 } else {
532 cvmx_dprintf("ERROR: Incompatible bootmem descriptor "
533 "version: %d.%d at addr: %p\n",
534 (int)cvmx_bootmem_desc->major_version,
535 (int)cvmx_bootmem_desc->minor_version,
536 cvmx_bootmem_desc);
537 }
538 if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING))
539 cvmx_bootmem_unlock();
540
541 return NULL;
542}
543
544int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags)
545{
546 struct cvmx_bootmem_named_block_desc *named_block_ptr;
547
548 if (cvmx_bootmem_desc->major_version != 3) {
549 cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: "
550 "%d.%d at addr: %p\n",
551 (int)cvmx_bootmem_desc->major_version,
552 (int)cvmx_bootmem_desc->minor_version,
553 cvmx_bootmem_desc);
554 return 0;
555 }
556#ifdef DEBUG
557 cvmx_dprintf("cvmx_bootmem_phy_named_block_free: %s\n", name);
558#endif
559
560 /*
561 * Take lock here, as name lookup/block free/name free need to
562 * be atomic.
563 */
564 cvmx_bootmem_lock();
565
566 named_block_ptr =
567 cvmx_bootmem_phy_named_block_find(name,
568 CVMX_BOOTMEM_FLAG_NO_LOCKING);
569 if (named_block_ptr) {
570#ifdef DEBUG
571 cvmx_dprintf("cvmx_bootmem_phy_named_block_free: "
572 "%s, base: 0x%llx, size: 0x%llx\n",
573 name,
574 (unsigned long long)named_block_ptr->base_addr,
575 (unsigned long long)named_block_ptr->size);
576#endif
577 __cvmx_bootmem_phy_free(named_block_ptr->base_addr,
578 named_block_ptr->size,
579 CVMX_BOOTMEM_FLAG_NO_LOCKING);
580 named_block_ptr->size = 0;
581 /* Set size to zero to indicate block not used. */
582 }
583
584 cvmx_bootmem_unlock();
585 return named_block_ptr != NULL; /* 0 on failure, 1 on success */
586}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-l2c.c b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
new file mode 100644
index 000000000000..6abe56f1e097
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-l2c.c
@@ -0,0 +1,734 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Implementation of the Level 2 Cache (L2C) control, measurement, and
30 * debugging facilities.
31 */
32
33#include <asm/octeon/cvmx.h>
34#include <asm/octeon/cvmx-l2c.h>
35#include <asm/octeon/cvmx-spinlock.h>
36
37/*
38 * This spinlock is used internally to ensure that only one core is
39 * performing certain L2 operations at a time.
40 *
41 * NOTE: This only protects calls from within a single application -
42 * if multiple applications or operating systems are running, then it
43 * is up to the user program to coordinate between them.
44 */
45static cvmx_spinlock_t cvmx_l2c_spinlock;
46
47static inline int l2_size_half(void)
48{
49 uint64_t val = cvmx_read_csr(CVMX_L2D_FUS3);
50 return !!(val & (1ull << 34));
51}
52
53int cvmx_l2c_get_core_way_partition(uint32_t core)
54{
55 uint32_t field;
56
57 /* Validate the core number */
58 if (core >= cvmx_octeon_num_cores())
59 return -1;
60
61 /*
62 * Use the lower two bits of the coreNumber to determine the
63 * bit offset of the UMSK[] field in the L2C_SPAR register.
64 */
65 field = (core & 0x3) * 8;
66
67 /*
68 * Return the UMSK[] field from the appropriate L2C_SPAR
69 * register based on the coreNumber.
70 */
71
72 switch (core & 0xC) {
73 case 0x0:
74 return (cvmx_read_csr(CVMX_L2C_SPAR0) & (0xFF << field)) >>
75 field;
76 case 0x4:
77 return (cvmx_read_csr(CVMX_L2C_SPAR1) & (0xFF << field)) >>
78 field;
79 case 0x8:
80 return (cvmx_read_csr(CVMX_L2C_SPAR2) & (0xFF << field)) >>
81 field;
82 case 0xC:
83 return (cvmx_read_csr(CVMX_L2C_SPAR3) & (0xFF << field)) >>
84 field;
85 }
86 return 0;
87}
88
89int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask)
90{
91 uint32_t field;
92 uint32_t valid_mask;
93
94 valid_mask = (0x1 << cvmx_l2c_get_num_assoc()) - 1;
95
96 mask &= valid_mask;
97
98 /* A UMSK setting which blocks all L2C Ways is an error. */
99 if (mask == valid_mask)
100 return -1;
101
102 /* Validate the core number */
103 if (core >= cvmx_octeon_num_cores())
104 return -1;
105
106 /* Check to make sure current mask & new mask don't block all ways */
107 if (((mask | cvmx_l2c_get_core_way_partition(core)) & valid_mask) ==
108 valid_mask)
109 return -1;
110
111 /* Use the lower two bits of core to determine the bit offset of the
112 * UMSK[] field in the L2C_SPAR register.
113 */
114 field = (core & 0x3) * 8;
115
116 /* Assign the new mask setting to the UMSK[] field in the appropriate
117 * L2C_SPAR register based on the core_num.
118 *
119 */
120 switch (core & 0xC) {
121 case 0x0:
122 cvmx_write_csr(CVMX_L2C_SPAR0,
123 (cvmx_read_csr(CVMX_L2C_SPAR0) &
124 ~(0xFF << field)) | mask << field);
125 break;
126 case 0x4:
127 cvmx_write_csr(CVMX_L2C_SPAR1,
128 (cvmx_read_csr(CVMX_L2C_SPAR1) &
129 ~(0xFF << field)) | mask << field);
130 break;
131 case 0x8:
132 cvmx_write_csr(CVMX_L2C_SPAR2,
133 (cvmx_read_csr(CVMX_L2C_SPAR2) &
134 ~(0xFF << field)) | mask << field);
135 break;
136 case 0xC:
137 cvmx_write_csr(CVMX_L2C_SPAR3,
138 (cvmx_read_csr(CVMX_L2C_SPAR3) &
139 ~(0xFF << field)) | mask << field);
140 break;
141 }
142 return 0;
143}
144
145int cvmx_l2c_set_hw_way_partition(uint32_t mask)
146{
147 uint32_t valid_mask;
148
149 valid_mask = 0xff;
150
151 if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN38XX)) {
152 if (l2_size_half())
153 valid_mask = 0xf;
154 } else if (l2_size_half())
155 valid_mask = 0x3;
156
157 mask &= valid_mask;
158
159 /* A UMSK setting which blocks all L2C Ways is an error. */
160 if (mask == valid_mask)
161 return -1;
162 /* Check to make sure current mask & new mask don't block all ways */
163 if (((mask | cvmx_l2c_get_hw_way_partition()) & valid_mask) ==
164 valid_mask)
165 return -1;
166
167 cvmx_write_csr(CVMX_L2C_SPAR4,
168 (cvmx_read_csr(CVMX_L2C_SPAR4) & ~0xFF) | mask);
169 return 0;
170}
171
172int cvmx_l2c_get_hw_way_partition(void)
173{
174 return cvmx_read_csr(CVMX_L2C_SPAR4) & (0xFF);
175}
176
177void cvmx_l2c_config_perf(uint32_t counter, enum cvmx_l2c_event event,
178 uint32_t clear_on_read)
179{
180 union cvmx_l2c_pfctl pfctl;
181
182 pfctl.u64 = cvmx_read_csr(CVMX_L2C_PFCTL);
183
184 switch (counter) {
185 case 0:
186 pfctl.s.cnt0sel = event;
187 pfctl.s.cnt0ena = 1;
188 if (!cvmx_octeon_is_pass1())
189 pfctl.s.cnt0rdclr = clear_on_read;
190 break;
191 case 1:
192 pfctl.s.cnt1sel = event;
193 pfctl.s.cnt1ena = 1;
194 if (!cvmx_octeon_is_pass1())
195 pfctl.s.cnt1rdclr = clear_on_read;
196 break;
197 case 2:
198 pfctl.s.cnt2sel = event;
199 pfctl.s.cnt2ena = 1;
200 if (!cvmx_octeon_is_pass1())
201 pfctl.s.cnt2rdclr = clear_on_read;
202 break;
203 case 3:
204 default:
205 pfctl.s.cnt3sel = event;
206 pfctl.s.cnt3ena = 1;
207 if (!cvmx_octeon_is_pass1())
208 pfctl.s.cnt3rdclr = clear_on_read;
209 break;
210 }
211
212 cvmx_write_csr(CVMX_L2C_PFCTL, pfctl.u64);
213}
214
215uint64_t cvmx_l2c_read_perf(uint32_t counter)
216{
217 switch (counter) {
218 case 0:
219 return cvmx_read_csr(CVMX_L2C_PFC0);
220 case 1:
221 return cvmx_read_csr(CVMX_L2C_PFC1);
222 case 2:
223 return cvmx_read_csr(CVMX_L2C_PFC2);
224 case 3:
225 default:
226 return cvmx_read_csr(CVMX_L2C_PFC3);
227 }
228}
229
230/**
231 * @INTERNAL
232 * Helper function use to fault in cache lines for L2 cache locking
233 *
234 * @addr: Address of base of memory region to read into L2 cache
235 * @len: Length (in bytes) of region to fault in
236 */
237static void fault_in(uint64_t addr, int len)
238{
239 volatile char *ptr;
240 volatile char dummy;
241 /*
242 * Adjust addr and length so we get all cache lines even for
243 * small ranges spanning two cache lines
244 */
245 len += addr & CVMX_CACHE_LINE_MASK;
246 addr &= ~CVMX_CACHE_LINE_MASK;
247 ptr = (volatile char *)cvmx_phys_to_ptr(addr);
248 /*
249 * Invalidate L1 cache to make sure all loads result in data
250 * being in L2.
251 */
252 CVMX_DCACHE_INVALIDATE;
253 while (len > 0) {
254 dummy += *ptr;
255 len -= CVMX_CACHE_LINE_SIZE;
256 ptr += CVMX_CACHE_LINE_SIZE;
257 }
258}
259
260int cvmx_l2c_lock_line(uint64_t addr)
261{
262 int retval = 0;
263 union cvmx_l2c_dbg l2cdbg;
264 union cvmx_l2c_lckbase lckbase;
265 union cvmx_l2c_lckoff lckoff;
266 union cvmx_l2t_err l2t_err;
267 l2cdbg.u64 = 0;
268 lckbase.u64 = 0;
269 lckoff.u64 = 0;
270
271 cvmx_spinlock_lock(&cvmx_l2c_spinlock);
272
273 /* Clear l2t error bits if set */
274 l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
275 l2t_err.s.lckerr = 1;
276 l2t_err.s.lckerr2 = 1;
277 cvmx_write_csr(CVMX_L2T_ERR, l2t_err.u64);
278
279 addr &= ~CVMX_CACHE_LINE_MASK;
280
281 /* Set this core as debug core */
282 l2cdbg.s.ppnum = cvmx_get_core_num();
283 CVMX_SYNC;
284 cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
285 cvmx_read_csr(CVMX_L2C_DBG);
286
287 lckoff.s.lck_offset = 0; /* Only lock 1 line at a time */
288 cvmx_write_csr(CVMX_L2C_LCKOFF, lckoff.u64);
289 cvmx_read_csr(CVMX_L2C_LCKOFF);
290
291 if (((union cvmx_l2c_cfg) (cvmx_read_csr(CVMX_L2C_CFG))).s.idxalias) {
292 int alias_shift =
293 CVMX_L2C_IDX_ADDR_SHIFT + 2 * CVMX_L2_SET_BITS - 1;
294 uint64_t addr_tmp =
295 addr ^ (addr & ((1 << alias_shift) - 1)) >>
296 CVMX_L2_SET_BITS;
297 lckbase.s.lck_base = addr_tmp >> 7;
298 } else {
299 lckbase.s.lck_base = addr >> 7;
300 }
301
302 lckbase.s.lck_ena = 1;
303 cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
304 cvmx_read_csr(CVMX_L2C_LCKBASE); /* Make sure it gets there */
305
306 fault_in(addr, CVMX_CACHE_LINE_SIZE);
307
308 lckbase.s.lck_ena = 0;
309 cvmx_write_csr(CVMX_L2C_LCKBASE, lckbase.u64);
310 cvmx_read_csr(CVMX_L2C_LCKBASE); /* Make sure it gets there */
311
312 /* Stop being debug core */
313 cvmx_write_csr(CVMX_L2C_DBG, 0);
314 cvmx_read_csr(CVMX_L2C_DBG);
315
316 l2t_err.u64 = cvmx_read_csr(CVMX_L2T_ERR);
317 if (l2t_err.s.lckerr || l2t_err.s.lckerr2)
318 retval = 1; /* We were unable to lock the line */
319
320 cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
321
322 return retval;
323}
324
325int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len)
326{
327 int retval = 0;
328
329 /* Round start/end to cache line boundaries */
330 len += start & CVMX_CACHE_LINE_MASK;
331 start &= ~CVMX_CACHE_LINE_MASK;
332 len = (len + CVMX_CACHE_LINE_MASK) & ~CVMX_CACHE_LINE_MASK;
333
334 while (len) {
335 retval += cvmx_l2c_lock_line(start);
336 start += CVMX_CACHE_LINE_SIZE;
337 len -= CVMX_CACHE_LINE_SIZE;
338 }
339
340 return retval;
341}
342
343void cvmx_l2c_flush(void)
344{
345 uint64_t assoc, set;
346 uint64_t n_assoc, n_set;
347 union cvmx_l2c_dbg l2cdbg;
348
349 cvmx_spinlock_lock(&cvmx_l2c_spinlock);
350
351 l2cdbg.u64 = 0;
352 if (!OCTEON_IS_MODEL(OCTEON_CN30XX))
353 l2cdbg.s.ppnum = cvmx_get_core_num();
354 l2cdbg.s.finv = 1;
355 n_set = CVMX_L2_SETS;
356 n_assoc = l2_size_half() ? (CVMX_L2_ASSOC / 2) : CVMX_L2_ASSOC;
357 for (set = 0; set < n_set; set++) {
358 for (assoc = 0; assoc < n_assoc; assoc++) {
359 l2cdbg.s.set = assoc;
360 /* Enter debug mode, and make sure all other
361 ** writes complete before we enter debug
362 ** mode */
363 CVMX_SYNCW;
364 cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
365 cvmx_read_csr(CVMX_L2C_DBG);
366
367 CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG
368 (CVMX_MIPS_SPACE_XKPHYS,
369 set * CVMX_CACHE_LINE_SIZE), 0);
370 CVMX_SYNCW; /* Push STF out to L2 */
371 /* Exit debug mode */
372 CVMX_SYNC;
373 cvmx_write_csr(CVMX_L2C_DBG, 0);
374 cvmx_read_csr(CVMX_L2C_DBG);
375 }
376 }
377
378 cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
379}
380
381int cvmx_l2c_unlock_line(uint64_t address)
382{
383 int assoc;
384 union cvmx_l2c_tag tag;
385 union cvmx_l2c_dbg l2cdbg;
386 uint32_t tag_addr;
387
388 uint32_t index = cvmx_l2c_address_to_index(address);
389
390 cvmx_spinlock_lock(&cvmx_l2c_spinlock);
391 /* Compute portion of address that is stored in tag */
392 tag_addr =
393 ((address >> CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) &
394 ((1 << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT) - 1));
395 for (assoc = 0; assoc < CVMX_L2_ASSOC; assoc++) {
396 tag = cvmx_get_l2c_tag(assoc, index);
397
398 if (tag.s.V && (tag.s.addr == tag_addr)) {
399 l2cdbg.u64 = 0;
400 l2cdbg.s.ppnum = cvmx_get_core_num();
401 l2cdbg.s.set = assoc;
402 l2cdbg.s.finv = 1;
403
404 CVMX_SYNC;
405 /* Enter debug mode */
406 cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
407 cvmx_read_csr(CVMX_L2C_DBG);
408
409 CVMX_PREPARE_FOR_STORE(CVMX_ADD_SEG
410 (CVMX_MIPS_SPACE_XKPHYS,
411 address), 0);
412 CVMX_SYNC;
413 /* Exit debug mode */
414 cvmx_write_csr(CVMX_L2C_DBG, 0);
415 cvmx_read_csr(CVMX_L2C_DBG);
416 cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
417 return tag.s.L;
418 }
419 }
420 cvmx_spinlock_unlock(&cvmx_l2c_spinlock);
421 return 0;
422}
423
424int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len)
425{
426 int num_unlocked = 0;
427 /* Round start/end to cache line boundaries */
428 len += start & CVMX_CACHE_LINE_MASK;
429 start &= ~CVMX_CACHE_LINE_MASK;
430 len = (len + CVMX_CACHE_LINE_MASK) & ~CVMX_CACHE_LINE_MASK;
431 while (len > 0) {
432 num_unlocked += cvmx_l2c_unlock_line(start);
433 start += CVMX_CACHE_LINE_SIZE;
434 len -= CVMX_CACHE_LINE_SIZE;
435 }
436
437 return num_unlocked;
438}
439
440/*
441 * Internal l2c tag types. These are converted to a generic structure
442 * that can be used on all chips.
443 */
444union __cvmx_l2c_tag {
445 uint64_t u64;
446 struct cvmx_l2c_tag_cn50xx {
447 uint64_t reserved:40;
448 uint64_t V:1; /* Line valid */
449 uint64_t D:1; /* Line dirty */
450 uint64_t L:1; /* Line locked */
451 uint64_t U:1; /* Use, LRU eviction */
452 uint64_t addr:20; /* Phys mem addr (33..14) */
453 } cn50xx;
454 struct cvmx_l2c_tag_cn30xx {
455 uint64_t reserved:41;
456 uint64_t V:1; /* Line valid */
457 uint64_t D:1; /* Line dirty */
458 uint64_t L:1; /* Line locked */
459 uint64_t U:1; /* Use, LRU eviction */
460 uint64_t addr:19; /* Phys mem addr (33..15) */
461 } cn30xx;
462 struct cvmx_l2c_tag_cn31xx {
463 uint64_t reserved:42;
464 uint64_t V:1; /* Line valid */
465 uint64_t D:1; /* Line dirty */
466 uint64_t L:1; /* Line locked */
467 uint64_t U:1; /* Use, LRU eviction */
468 uint64_t addr:18; /* Phys mem addr (33..16) */
469 } cn31xx;
470 struct cvmx_l2c_tag_cn38xx {
471 uint64_t reserved:43;
472 uint64_t V:1; /* Line valid */
473 uint64_t D:1; /* Line dirty */
474 uint64_t L:1; /* Line locked */
475 uint64_t U:1; /* Use, LRU eviction */
476 uint64_t addr:17; /* Phys mem addr (33..17) */
477 } cn38xx;
478 struct cvmx_l2c_tag_cn58xx {
479 uint64_t reserved:44;
480 uint64_t V:1; /* Line valid */
481 uint64_t D:1; /* Line dirty */
482 uint64_t L:1; /* Line locked */
483 uint64_t U:1; /* Use, LRU eviction */
484 uint64_t addr:16; /* Phys mem addr (33..18) */
485 } cn58xx;
486 struct cvmx_l2c_tag_cn58xx cn56xx; /* 2048 sets */
487 struct cvmx_l2c_tag_cn31xx cn52xx; /* 512 sets */
488};
489
490/**
491 * @INTERNAL
492 * Function to read a L2C tag. This code make the current core
493 * the 'debug core' for the L2. This code must only be executed by
494 * 1 core at a time.
495 *
496 * @assoc: Association (way) of the tag to dump
497 * @index: Index of the cacheline
498 *
499 * Returns The Octeon model specific tag structure. This is
500 * translated by a wrapper function to a generic form that is
501 * easier for applications to use.
502 */
503static union __cvmx_l2c_tag __read_l2_tag(uint64_t assoc, uint64_t index)
504{
505
506 uint64_t debug_tag_addr = (((1ULL << 63) | (index << 7)) + 96);
507 uint64_t core = cvmx_get_core_num();
508 union __cvmx_l2c_tag tag_val;
509 uint64_t dbg_addr = CVMX_L2C_DBG;
510 unsigned long flags;
511
512 union cvmx_l2c_dbg debug_val;
513 debug_val.u64 = 0;
514 /*
515 * For low core count parts, the core number is always small enough
516 * to stay in the correct field and not set any reserved bits.
517 */
518 debug_val.s.ppnum = core;
519 debug_val.s.l2t = 1;
520 debug_val.s.set = assoc;
521 /*
522 * Make sure core is quiet (no prefetches, etc.) before
523 * entering debug mode.
524 */
525 CVMX_SYNC;
526 /* Flush L1 to make sure debug load misses L1 */
527 CVMX_DCACHE_INVALIDATE;
528
529 local_irq_save(flags);
530
531 /*
532 * The following must be done in assembly as when in debug
533 * mode all data loads from L2 return special debug data, not
534 * normal memory contents. Also, interrupts must be
535 * disabled, since if an interrupt occurs while in debug mode
536 * the ISR will get debug data from all its memory reads
537 * instead of the contents of memory
538 */
539
540 asm volatile (".set push \n"
541 " .set mips64 \n"
542 " .set noreorder \n"
543 /* Enter debug mode, wait for store */
544 " sd %[dbg_val], 0(%[dbg_addr]) \n"
545 " ld $0, 0(%[dbg_addr]) \n"
546 /* Read L2C tag data */
547 " ld %[tag_val], 0(%[tag_addr]) \n"
548 /* Exit debug mode, wait for store */
549 " sd $0, 0(%[dbg_addr]) \n"
550 " ld $0, 0(%[dbg_addr]) \n"
551 /* Invalidate dcache to discard debug data */
552 " cache 9, 0($0) \n"
553 " .set pop" :
554 [tag_val] "=r"(tag_val.u64) : [dbg_addr] "r"(dbg_addr),
555 [dbg_val] "r"(debug_val.u64),
556 [tag_addr] "r"(debug_tag_addr) : "memory");
557
558 local_irq_restore(flags);
559 return tag_val;
560
561}
562
563union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index)
564{
565 union __cvmx_l2c_tag tmp_tag;
566 union cvmx_l2c_tag tag;
567 tag.u64 = 0;
568
569 if ((int)association >= cvmx_l2c_get_num_assoc()) {
570 cvmx_dprintf
571 ("ERROR: cvmx_get_l2c_tag association out of range\n");
572 return tag;
573 }
574 if ((int)index >= cvmx_l2c_get_num_sets()) {
575 cvmx_dprintf("ERROR: cvmx_get_l2c_tag "
576 "index out of range (arg: %d, max: %d\n",
577 index, cvmx_l2c_get_num_sets());
578 return tag;
579 }
580 /* __read_l2_tag is intended for internal use only */
581 tmp_tag = __read_l2_tag(association, index);
582
583 /*
584 * Convert all tag structure types to generic version, as it
585 * can represent all models.
586 */
587 if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX)) {
588 tag.s.V = tmp_tag.cn58xx.V;
589 tag.s.D = tmp_tag.cn58xx.D;
590 tag.s.L = tmp_tag.cn58xx.L;
591 tag.s.U = tmp_tag.cn58xx.U;
592 tag.s.addr = tmp_tag.cn58xx.addr;
593 } else if (OCTEON_IS_MODEL(OCTEON_CN38XX)) {
594 tag.s.V = tmp_tag.cn38xx.V;
595 tag.s.D = tmp_tag.cn38xx.D;
596 tag.s.L = tmp_tag.cn38xx.L;
597 tag.s.U = tmp_tag.cn38xx.U;
598 tag.s.addr = tmp_tag.cn38xx.addr;
599 } else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
600 || OCTEON_IS_MODEL(OCTEON_CN52XX)) {
601 tag.s.V = tmp_tag.cn31xx.V;
602 tag.s.D = tmp_tag.cn31xx.D;
603 tag.s.L = tmp_tag.cn31xx.L;
604 tag.s.U = tmp_tag.cn31xx.U;
605 tag.s.addr = tmp_tag.cn31xx.addr;
606 } else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) {
607 tag.s.V = tmp_tag.cn30xx.V;
608 tag.s.D = tmp_tag.cn30xx.D;
609 tag.s.L = tmp_tag.cn30xx.L;
610 tag.s.U = tmp_tag.cn30xx.U;
611 tag.s.addr = tmp_tag.cn30xx.addr;
612 } else if (OCTEON_IS_MODEL(OCTEON_CN50XX)) {
613 tag.s.V = tmp_tag.cn50xx.V;
614 tag.s.D = tmp_tag.cn50xx.D;
615 tag.s.L = tmp_tag.cn50xx.L;
616 tag.s.U = tmp_tag.cn50xx.U;
617 tag.s.addr = tmp_tag.cn50xx.addr;
618 } else {
619 cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
620 }
621
622 return tag;
623}
624
625uint32_t cvmx_l2c_address_to_index(uint64_t addr)
626{
627 uint64_t idx = addr >> CVMX_L2C_IDX_ADDR_SHIFT;
628 union cvmx_l2c_cfg l2c_cfg;
629 l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG);
630
631 if (l2c_cfg.s.idxalias) {
632 idx ^=
633 ((addr & CVMX_L2C_ALIAS_MASK) >>
634 CVMX_L2C_TAG_ADDR_ALIAS_SHIFT);
635 }
636 idx &= CVMX_L2C_IDX_MASK;
637 return idx;
638}
639
640int cvmx_l2c_get_cache_size_bytes(void)
641{
642 return cvmx_l2c_get_num_sets() * cvmx_l2c_get_num_assoc() *
643 CVMX_CACHE_LINE_SIZE;
644}
645
646/**
647 * Return log base 2 of the number of sets in the L2 cache
648 * Returns
649 */
650int cvmx_l2c_get_set_bits(void)
651{
652 int l2_set_bits;
653 if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN58XX))
654 l2_set_bits = 11; /* 2048 sets */
655 else if (OCTEON_IS_MODEL(OCTEON_CN38XX))
656 l2_set_bits = 10; /* 1024 sets */
657 else if (OCTEON_IS_MODEL(OCTEON_CN31XX)
658 || OCTEON_IS_MODEL(OCTEON_CN52XX))
659 l2_set_bits = 9; /* 512 sets */
660 else if (OCTEON_IS_MODEL(OCTEON_CN30XX))
661 l2_set_bits = 8; /* 256 sets */
662 else if (OCTEON_IS_MODEL(OCTEON_CN50XX))
663 l2_set_bits = 7; /* 128 sets */
664 else {
665 cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
666 l2_set_bits = 11; /* 2048 sets */
667 }
668 return l2_set_bits;
669
670}
671
672/* Return the number of sets in the L2 Cache */
673int cvmx_l2c_get_num_sets(void)
674{
675 return 1 << cvmx_l2c_get_set_bits();
676}
677
678/* Return the number of associations in the L2 Cache */
679int cvmx_l2c_get_num_assoc(void)
680{
681 int l2_assoc;
682 if (OCTEON_IS_MODEL(OCTEON_CN56XX) ||
683 OCTEON_IS_MODEL(OCTEON_CN52XX) ||
684 OCTEON_IS_MODEL(OCTEON_CN58XX) ||
685 OCTEON_IS_MODEL(OCTEON_CN50XX) || OCTEON_IS_MODEL(OCTEON_CN38XX))
686 l2_assoc = 8;
687 else if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
688 OCTEON_IS_MODEL(OCTEON_CN30XX))
689 l2_assoc = 4;
690 else {
691 cvmx_dprintf("Unsupported OCTEON Model in %s\n", __func__);
692 l2_assoc = 8;
693 }
694
695 /* Check to see if part of the cache is disabled */
696 if (cvmx_fuse_read(265))
697 l2_assoc = l2_assoc >> 2;
698 else if (cvmx_fuse_read(264))
699 l2_assoc = l2_assoc >> 1;
700
701 return l2_assoc;
702}
703
704/**
705 * Flush a line from the L2 cache
706 * This should only be called from one core at a time, as this routine
707 * sets the core to the 'debug' core in order to flush the line.
708 *
709 * @assoc: Association (or way) to flush
710 * @index: Index to flush
711 */
712void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index)
713{
714 union cvmx_l2c_dbg l2cdbg;
715
716 l2cdbg.u64 = 0;
717 l2cdbg.s.ppnum = cvmx_get_core_num();
718 l2cdbg.s.finv = 1;
719
720 l2cdbg.s.set = assoc;
721 /*
722 * Enter debug mode, and make sure all other writes complete
723 * before we enter debug mode.
724 */
725 asm volatile ("sync" : : : "memory");
726 cvmx_write_csr(CVMX_L2C_DBG, l2cdbg.u64);
727 cvmx_read_csr(CVMX_L2C_DBG);
728
729 CVMX_PREPARE_FOR_STORE(((1ULL << 63) + (index) * 128), 0);
730 /* Exit debug mode */
731 asm volatile ("sync" : : : "memory");
732 cvmx_write_csr(CVMX_L2C_DBG, 0);
733 cvmx_read_csr(CVMX_L2C_DBG);
734}
diff --git a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
new file mode 100644
index 000000000000..4812370706a1
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c
@@ -0,0 +1,116 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * This module provides system/board/application information obtained
30 * by the bootloader.
31 */
32
33#include <asm/octeon/cvmx.h>
34#include <asm/octeon/cvmx-spinlock.h>
35#include <asm/octeon/cvmx-sysinfo.h>
36
37/**
38 * This structure defines the private state maintained by sysinfo module.
39 *
40 */
41static struct {
42 struct cvmx_sysinfo sysinfo; /* system information */
43 cvmx_spinlock_t lock; /* mutex spinlock */
44
45} state = {
46 .lock = CVMX_SPINLOCK_UNLOCKED_INITIALIZER
47};
48
49
50/*
51 * Global variables that define the min/max of the memory region set
52 * up for 32 bit userspace access.
53 */
54uint64_t linux_mem32_min;
55uint64_t linux_mem32_max;
56uint64_t linux_mem32_wired;
57uint64_t linux_mem32_offset;
58
59/**
60 * This function returns the application information as obtained
61 * by the bootloader. This provides the core mask of the cores
62 * running the same application image, as well as the physical
63 * memory regions available to the core.
64 *
65 * Returns Pointer to the boot information structure
66 *
67 */
68struct cvmx_sysinfo *cvmx_sysinfo_get(void)
69{
70 return &(state.sysinfo);
71}
72
73/**
74 * This function is used in non-simple executive environments (such as
75 * Linux kernel, u-boot, etc.) to configure the minimal fields that
76 * are required to use simple executive files directly.
77 *
78 * Locking (if required) must be handled outside of this
79 * function
80 *
81 * @phy_mem_desc_ptr:
82 * Pointer to global physical memory descriptor
83 * (bootmem descriptor) @board_type: Octeon board
84 * type enumeration
85 *
86 * @board_rev_major:
87 * Board major revision
88 * @board_rev_minor:
89 * Board minor revision
90 * @cpu_clock_hz:
91 * CPU clock freqency in hertz
92 *
93 * Returns 0: Failure
94 * 1: success
95 */
96int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr,
97 uint16_t board_type,
98 uint8_t board_rev_major,
99 uint8_t board_rev_minor,
100 uint32_t cpu_clock_hz)
101{
102
103 /* The sysinfo structure was already initialized */
104 if (state.sysinfo.board_type)
105 return 0;
106
107 memset(&(state.sysinfo), 0x0, sizeof(state.sysinfo));
108 state.sysinfo.phy_mem_desc_ptr = phy_mem_desc_ptr;
109 state.sysinfo.board_type = board_type;
110 state.sysinfo.board_rev_major = board_rev_major;
111 state.sysinfo.board_rev_minor = board_rev_minor;
112 state.sysinfo.cpu_clock_hz = cpu_clock_hz;
113
114 return 1;
115}
116
diff --git a/arch/mips/cavium-octeon/executive/octeon-model.c b/arch/mips/cavium-octeon/executive/octeon-model.c
new file mode 100644
index 000000000000..9afc3794ed1b
--- /dev/null
+++ b/arch/mips/cavium-octeon/executive/octeon-model.c
@@ -0,0 +1,358 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * File defining functions for working with different Octeon
30 * models.
31 */
32#include <asm/octeon/octeon.h>
33
34/**
35 * Given the chip processor ID from COP0, this function returns a
36 * string representing the chip model number. The string is of the
37 * form CNXXXXpX.X-FREQ-SUFFIX.
38 * - XXXX = The chip model number
39 * - X.X = Chip pass number
40 * - FREQ = Current frequency in Mhz
41 * - SUFFIX = NSP, EXP, SCP, SSP, or CP
42 *
43 * @chip_id: Chip ID
44 *
45 * Returns Model string
46 */
47const char *octeon_model_get_string(uint32_t chip_id)
48{
49 static char buffer[32];
50 return octeon_model_get_string_buffer(chip_id, buffer);
51}
52
53/*
54 * Version of octeon_model_get_string() that takes buffer as argument,
55 * as running early in u-boot static/global variables don't work when
56 * running from flash.
57 */
58const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer)
59{
60 const char *family;
61 const char *core_model;
62 char pass[4];
63 int clock_mhz;
64 const char *suffix;
65 union cvmx_l2d_fus3 fus3;
66 int num_cores;
67 union cvmx_mio_fus_dat2 fus_dat2;
68 union cvmx_mio_fus_dat3 fus_dat3;
69 char fuse_model[10];
70 uint32_t fuse_data = 0;
71
72 fus3.u64 = cvmx_read_csr(CVMX_L2D_FUS3);
73 fus_dat2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2);
74 fus_dat3.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT3);
75
76 num_cores = cvmx_octeon_num_cores();
77
78 /* Make sure the non existant devices look disabled */
79 switch ((chip_id >> 8) & 0xff) {
80 case 6: /* CN50XX */
81 case 2: /* CN30XX */
82 fus_dat3.s.nodfa_dte = 1;
83 fus_dat3.s.nozip = 1;
84 break;
85 case 4: /* CN57XX or CN56XX */
86 fus_dat3.s.nodfa_dte = 1;
87 break;
88 default:
89 break;
90 }
91
92 /* Make a guess at the suffix */
93 /* NSP = everything */
94 /* EXP = No crypto */
95 /* SCP = No DFA, No zip */
96 /* CP = No DFA, No crypto, No zip */
97 if (fus_dat3.s.nodfa_dte) {
98 if (fus_dat2.s.nocrypto)
99 suffix = "CP";
100 else
101 suffix = "SCP";
102 } else if (fus_dat2.s.nocrypto)
103 suffix = "EXP";
104 else
105 suffix = "NSP";
106
107 /*
108 * Assume pass number is encoded using <5:3><2:0>. Exceptions
109 * will be fixed later.
110 */
111 sprintf(pass, "%u.%u", ((chip_id >> 3) & 7) + 1, chip_id & 7);
112
113 /*
114 * Use the number of cores to determine the last 2 digits of
115 * the model number. There are some exceptions that are fixed
116 * later.
117 */
118 switch (num_cores) {
119 case 16:
120 core_model = "60";
121 break;
122 case 15:
123 core_model = "58";
124 break;
125 case 14:
126 core_model = "55";
127 break;
128 case 13:
129 core_model = "52";
130 break;
131 case 12:
132 core_model = "50";
133 break;
134 case 11:
135 core_model = "48";
136 break;
137 case 10:
138 core_model = "45";
139 break;
140 case 9:
141 core_model = "42";
142 break;
143 case 8:
144 core_model = "40";
145 break;
146 case 7:
147 core_model = "38";
148 break;
149 case 6:
150 core_model = "34";
151 break;
152 case 5:
153 core_model = "32";
154 break;
155 case 4:
156 core_model = "30";
157 break;
158 case 3:
159 core_model = "25";
160 break;
161 case 2:
162 core_model = "20";
163 break;
164 case 1:
165 core_model = "10";
166 break;
167 default:
168 core_model = "XX";
169 break;
170 }
171
172 /* Now figure out the family, the first two digits */
173 switch ((chip_id >> 8) & 0xff) {
174 case 0: /* CN38XX, CN37XX or CN36XX */
175 if (fus3.cn38xx.crip_512k) {
176 /*
177 * For some unknown reason, the 16 core one is
178 * called 37 instead of 36.
179 */
180 if (num_cores >= 16)
181 family = "37";
182 else
183 family = "36";
184 } else
185 family = "38";
186 /*
187 * This series of chips didn't follow the standard
188 * pass numbering.
189 */
190 switch (chip_id & 0xf) {
191 case 0:
192 strcpy(pass, "1.X");
193 break;
194 case 1:
195 strcpy(pass, "2.X");
196 break;
197 case 3:
198 strcpy(pass, "3.X");
199 break;
200 default:
201 strcpy(pass, "X.X");
202 break;
203 }
204 break;
205 case 1: /* CN31XX or CN3020 */
206 if ((chip_id & 0x10) || fus3.cn31xx.crip_128k)
207 family = "30";
208 else
209 family = "31";
210 /*
211 * This series of chips didn't follow the standard
212 * pass numbering.
213 */
214 switch (chip_id & 0xf) {
215 case 0:
216 strcpy(pass, "1.0");
217 break;
218 case 2:
219 strcpy(pass, "1.1");
220 break;
221 default:
222 strcpy(pass, "X.X");
223 break;
224 }
225 break;
226 case 2: /* CN3010 or CN3005 */
227 family = "30";
228 /* A chip with half cache is an 05 */
229 if (fus3.cn30xx.crip_64k)
230 core_model = "05";
231 /*
232 * This series of chips didn't follow the standard
233 * pass numbering.
234 */
235 switch (chip_id & 0xf) {
236 case 0:
237 strcpy(pass, "1.0");
238 break;
239 case 2:
240 strcpy(pass, "1.1");
241 break;
242 default:
243 strcpy(pass, "X.X");
244 break;
245 }
246 break;
247 case 3: /* CN58XX */
248 family = "58";
249 /* Special case. 4 core, no crypto */
250 if ((num_cores == 4) && fus_dat2.cn38xx.nocrypto)
251 core_model = "29";
252
253 /* Pass 1 uses different encodings for pass numbers */
254 if ((chip_id & 0xFF) < 0x8) {
255 switch (chip_id & 0x3) {
256 case 0:
257 strcpy(pass, "1.0");
258 break;
259 case 1:
260 strcpy(pass, "1.1");
261 break;
262 case 3:
263 strcpy(pass, "1.2");
264 break;
265 default:
266 strcpy(pass, "1.X");
267 break;
268 }
269 }
270 break;
271 case 4: /* CN57XX, CN56XX, CN55XX, CN54XX */
272 if (fus_dat2.cn56xx.raid_en) {
273 if (fus3.cn56xx.crip_1024k)
274 family = "55";
275 else
276 family = "57";
277 if (fus_dat2.cn56xx.nocrypto)
278 suffix = "SP";
279 else
280 suffix = "SSP";
281 } else {
282 if (fus_dat2.cn56xx.nocrypto)
283 suffix = "CP";
284 else {
285 suffix = "NSP";
286 if (fus_dat3.s.nozip)
287 suffix = "SCP";
288 }
289 if (fus3.cn56xx.crip_1024k)
290 family = "54";
291 else
292 family = "56";
293 }
294 break;
295 case 6: /* CN50XX */
296 family = "50";
297 break;
298 case 7: /* CN52XX */
299 if (fus3.cn52xx.crip_256k)
300 family = "51";
301 else
302 family = "52";
303 break;
304 default:
305 family = "XX";
306 core_model = "XX";
307 strcpy(pass, "X.X");
308 suffix = "XXX";
309 break;
310 }
311
312 clock_mhz = octeon_get_clock_rate() / 1000000;
313
314 if (family[0] != '3') {
315 /* Check for model in fuses, overrides normal decode */
316 /* This is _not_ valid for Octeon CN3XXX models */
317 fuse_data |= cvmx_fuse_read_byte(51);
318 fuse_data = fuse_data << 8;
319 fuse_data |= cvmx_fuse_read_byte(50);
320 fuse_data = fuse_data << 8;
321 fuse_data |= cvmx_fuse_read_byte(49);
322 fuse_data = fuse_data << 8;
323 fuse_data |= cvmx_fuse_read_byte(48);
324 if (fuse_data & 0x7ffff) {
325 int model = fuse_data & 0x3fff;
326 int suffix = (fuse_data >> 14) & 0x1f;
327 if (suffix && model) {
328 /*
329 * Have both number and suffix in
330 * fuses, so both
331 */
332 sprintf(fuse_model, "%d%c",
333 model, 'A' + suffix - 1);
334 core_model = "";
335 family = fuse_model;
336 } else if (suffix && !model) {
337 /*
338 * Only have suffix, so add suffix to
339 * 'normal' model number.
340 */
341 sprintf(fuse_model, "%s%c", core_model,
342 'A' + suffix - 1);
343 core_model = fuse_model;
344 } else {
345 /*
346 * Don't have suffix, so just use
347 * model from fuses.
348 */
349 sprintf(fuse_model, "%d", model);
350 core_model = "";
351 family = fuse_model;
352 }
353 }
354 }
355 sprintf(buffer, "CN%s%sp%s-%d-%s",
356 family, core_model, pass, clock_mhz, suffix);
357 return buffer;
358}
diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c
new file mode 100644
index 000000000000..553d36cbcc42
--- /dev/null
+++ b/arch/mips/cavium-octeon/flash_setup.c
@@ -0,0 +1,84 @@
1/*
2 * Octeon Bootbus flash setup
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2007, 2008 Cavium Networks
9 */
10#include <linux/kernel.h>
11#include <linux/mtd/mtd.h>
12#include <linux/mtd/map.h>
13#include <linux/mtd/partitions.h>
14
15#include <asm/octeon/octeon.h>
16
17static struct map_info flash_map;
18static struct mtd_info *mymtd;
19#ifdef CONFIG_MTD_PARTITIONS
20static int nr_parts;
21static struct mtd_partition *parts;
22static const char *part_probe_types[] = {
23 "cmdlinepart",
24#ifdef CONFIG_MTD_REDBOOT_PARTS
25 "RedBoot",
26#endif
27 NULL
28};
29#endif
30
31/**
32 * Module/ driver initialization.
33 *
34 * Returns Zero on success
35 */
36static int __init flash_init(void)
37{
38 /*
39 * Read the bootbus region 0 setup to determine the base
40 * address of the flash.
41 */
42 union cvmx_mio_boot_reg_cfgx region_cfg;
43 region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(0));
44 if (region_cfg.s.en) {
45 /*
46 * The bootloader always takes the flash and sets its
47 * address so the entire flash fits below
48 * 0x1fc00000. This way the flash aliases to
49 * 0x1fc00000 for booting. Software can access the
50 * full flash at the true address, while core boot can
51 * access 4MB.
52 */
53 /* Use this name so old part lines work */
54 flash_map.name = "phys_mapped_flash";
55 flash_map.phys = region_cfg.s.base << 16;
56 flash_map.size = 0x1fc00000 - flash_map.phys;
57 flash_map.bankwidth = 1;
58 flash_map.virt = ioremap(flash_map.phys, flash_map.size);
59 pr_notice("Bootbus flash: Setting flash for %luMB flash at "
60 "0x%08lx\n", flash_map.size >> 20, flash_map.phys);
61 simple_map_init(&flash_map);
62 mymtd = do_map_probe("cfi_probe", &flash_map);
63 if (mymtd) {
64 mymtd->owner = THIS_MODULE;
65
66#ifdef CONFIG_MTD_PARTITIONS
67 nr_parts = parse_mtd_partitions(mymtd,
68 part_probe_types,
69 &parts, 0);
70 if (nr_parts > 0)
71 add_mtd_partitions(mymtd, parts, nr_parts);
72 else
73 add_mtd_device(mymtd);
74#else
75 add_mtd_device(mymtd);
76#endif
77 } else {
78 pr_err("Failed to register MTD device for flash\n");
79 }
80 }
81 return 0;
82}
83
84late_initcall(flash_init);
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
new file mode 100644
index 000000000000..fc72984a5dae
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -0,0 +1,497 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2008 Cavium Networks
7 */
8#include <linux/irq.h>
9#include <linux/interrupt.h>
10#include <linux/hardirq.h>
11
12#include <asm/octeon/octeon.h>
13
14DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
15DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
16DEFINE_SPINLOCK(octeon_irq_msi_lock);
17
18static void octeon_irq_core_ack(unsigned int irq)
19{
20 unsigned int bit = irq - OCTEON_IRQ_SW0;
21 /*
22 * We don't need to disable IRQs to make these atomic since
23 * they are already disabled earlier in the low level
24 * interrupt code.
25 */
26 clear_c0_status(0x100 << bit);
27 /* The two user interrupts must be cleared manually. */
28 if (bit < 2)
29 clear_c0_cause(0x100 << bit);
30}
31
32static void octeon_irq_core_eoi(unsigned int irq)
33{
34 irq_desc_t *desc = irq_desc + irq;
35 unsigned int bit = irq - OCTEON_IRQ_SW0;
36 /*
37 * If an IRQ is being processed while we are disabling it the
38 * handler will attempt to unmask the interrupt after it has
39 * been disabled.
40 */
41 if (desc->status & IRQ_DISABLED)
42 return;
43
44 /* There is a race here. We should fix it. */
45
46 /*
47 * We don't need to disable IRQs to make these atomic since
48 * they are already disabled earlier in the low level
49 * interrupt code.
50 */
51 set_c0_status(0x100 << bit);
52}
53
54static void octeon_irq_core_enable(unsigned int irq)
55{
56 unsigned long flags;
57 unsigned int bit = irq - OCTEON_IRQ_SW0;
58
59 /*
60 * We need to disable interrupts to make sure our updates are
61 * atomic.
62 */
63 local_irq_save(flags);
64 set_c0_status(0x100 << bit);
65 local_irq_restore(flags);
66}
67
68static void octeon_irq_core_disable_local(unsigned int irq)
69{
70 unsigned long flags;
71 unsigned int bit = irq - OCTEON_IRQ_SW0;
72 /*
73 * We need to disable interrupts to make sure our updates are
74 * atomic.
75 */
76 local_irq_save(flags);
77 clear_c0_status(0x100 << bit);
78 local_irq_restore(flags);
79}
80
81static void octeon_irq_core_disable(unsigned int irq)
82{
83#ifdef CONFIG_SMP
84 on_each_cpu((void (*)(void *)) octeon_irq_core_disable_local,
85 (void *) (long) irq, 1);
86#else
87 octeon_irq_core_disable_local(irq);
88#endif
89}
90
91static struct irq_chip octeon_irq_chip_core = {
92 .name = "Core",
93 .enable = octeon_irq_core_enable,
94 .disable = octeon_irq_core_disable,
95 .ack = octeon_irq_core_ack,
96 .eoi = octeon_irq_core_eoi,
97};
98
99
100static void octeon_irq_ciu0_ack(unsigned int irq)
101{
102 /*
103 * In order to avoid any locking accessing the CIU, we
104 * acknowledge CIU interrupts by disabling all of them. This
105 * way we can use a per core register and avoid any out of
106 * core locking requirements. This has the side affect that
107 * CIU interrupts can't be processed recursively.
108 *
109 * We don't need to disable IRQs to make these atomic since
110 * they are already disabled earlier in the low level
111 * interrupt code.
112 */
113 clear_c0_status(0x100 << 2);
114}
115
116static void octeon_irq_ciu0_eoi(unsigned int irq)
117{
118 /*
119 * Enable all CIU interrupts again. We don't need to disable
120 * IRQs to make these atomic since they are already disabled
121 * earlier in the low level interrupt code.
122 */
123 set_c0_status(0x100 << 2);
124}
125
126static void octeon_irq_ciu0_enable(unsigned int irq)
127{
128 int coreid = cvmx_get_core_num();
129 unsigned long flags;
130 uint64_t en0;
131 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
132
133 /*
134 * A read lock is used here to make sure only one core is ever
135 * updating the CIU enable bits at a time. During an enable
136 * the cores don't interfere with each other. During a disable
137 * the write lock stops any enables that might cause a
138 * problem.
139 */
140 read_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
141 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
142 en0 |= 1ull << bit;
143 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
144 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
145 read_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
146}
147
148static void octeon_irq_ciu0_disable(unsigned int irq)
149{
150 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
151 unsigned long flags;
152 uint64_t en0;
153#ifdef CONFIG_SMP
154 int cpu;
155 write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags);
156 for_each_online_cpu(cpu) {
157 int coreid = cpu_logical_map(cpu);
158 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
159 en0 &= ~(1ull << bit);
160 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
161 }
162 /*
163 * We need to do a read after the last update to make sure all
164 * of them are done.
165 */
166 cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
167 write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags);
168#else
169 int coreid = cvmx_get_core_num();
170 local_irq_save(flags);
171 en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
172 en0 &= ~(1ull << bit);
173 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
174 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
175 local_irq_restore(flags);
176#endif
177}
178
179#ifdef CONFIG_SMP
180static void octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest)
181{
182 int cpu;
183 int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */
184
185 write_lock(&octeon_irq_ciu0_rwlock);
186 for_each_online_cpu(cpu) {
187 int coreid = cpu_logical_map(cpu);
188 uint64_t en0 =
189 cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2));
190 if (cpumask_test_cpu(cpu, dest))
191 en0 |= 1ull << bit;
192 else
193 en0 &= ~(1ull << bit);
194 cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0);
195 }
196 /*
197 * We need to do a read after the last update to make sure all
198 * of them are done.
199 */
200 cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2));
201 write_unlock(&octeon_irq_ciu0_rwlock);
202}
203#endif
204
205static struct irq_chip octeon_irq_chip_ciu0 = {
206 .name = "CIU0",
207 .enable = octeon_irq_ciu0_enable,
208 .disable = octeon_irq_ciu0_disable,
209 .ack = octeon_irq_ciu0_ack,
210 .eoi = octeon_irq_ciu0_eoi,
211#ifdef CONFIG_SMP
212 .set_affinity = octeon_irq_ciu0_set_affinity,
213#endif
214};
215
216
217static void octeon_irq_ciu1_ack(unsigned int irq)
218{
219 /*
220 * In order to avoid any locking accessing the CIU, we
221 * acknowledge CIU interrupts by disabling all of them. This
222 * way we can use a per core register and avoid any out of
223 * core locking requirements. This has the side affect that
224 * CIU interrupts can't be processed recursively. We don't
225 * need to disable IRQs to make these atomic since they are
226 * already disabled earlier in the low level interrupt code.
227 */
228 clear_c0_status(0x100 << 3);
229}
230
231static void octeon_irq_ciu1_eoi(unsigned int irq)
232{
233 /*
234 * Enable all CIU interrupts again. We don't need to disable
235 * IRQs to make these atomic since they are already disabled
236 * earlier in the low level interrupt code.
237 */
238 set_c0_status(0x100 << 3);
239}
240
241static void octeon_irq_ciu1_enable(unsigned int irq)
242{
243 int coreid = cvmx_get_core_num();
244 unsigned long flags;
245 uint64_t en1;
246 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
247
248 /*
249 * A read lock is used here to make sure only one core is ever
250 * updating the CIU enable bits at a time. During an enable
251 * the cores don't interfere with each other. During a disable
252 * the write lock stops any enables that might cause a
253 * problem.
254 */
255 read_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
256 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
257 en1 |= 1ull << bit;
258 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
259 cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
260 read_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
261}
262
263static void octeon_irq_ciu1_disable(unsigned int irq)
264{
265 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
266 unsigned long flags;
267 uint64_t en1;
268#ifdef CONFIG_SMP
269 int cpu;
270 write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags);
271 for_each_online_cpu(cpu) {
272 int coreid = cpu_logical_map(cpu);
273 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
274 en1 &= ~(1ull << bit);
275 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
276 }
277 /*
278 * We need to do a read after the last update to make sure all
279 * of them are done.
280 */
281 cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
282 write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags);
283#else
284 int coreid = cvmx_get_core_num();
285 local_irq_save(flags);
286 en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
287 en1 &= ~(1ull << bit);
288 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
289 cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1));
290 local_irq_restore(flags);
291#endif
292}
293
294#ifdef CONFIG_SMP
295static void octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *dest)
296{
297 int cpu;
298 int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */
299
300 write_lock(&octeon_irq_ciu1_rwlock);
301 for_each_online_cpu(cpu) {
302 int coreid = cpu_logical_map(cpu);
303 uint64_t en1 =
304 cvmx_read_csr(CVMX_CIU_INTX_EN1
305 (coreid * 2 + 1));
306 if (cpumask_test_cpu(cpu, dest))
307 en1 |= 1ull << bit;
308 else
309 en1 &= ~(1ull << bit);
310 cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1);
311 }
312 /*
313 * We need to do a read after the last update to make sure all
314 * of them are done.
315 */
316 cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1));
317 write_unlock(&octeon_irq_ciu1_rwlock);
318}
319#endif
320
321static struct irq_chip octeon_irq_chip_ciu1 = {
322 .name = "CIU1",
323 .enable = octeon_irq_ciu1_enable,
324 .disable = octeon_irq_ciu1_disable,
325 .ack = octeon_irq_ciu1_ack,
326 .eoi = octeon_irq_ciu1_eoi,
327#ifdef CONFIG_SMP
328 .set_affinity = octeon_irq_ciu1_set_affinity,
329#endif
330};
331
332#ifdef CONFIG_PCI_MSI
333
334static void octeon_irq_msi_ack(unsigned int irq)
335{
336 if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
337 /* These chips have PCI */
338 cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
339 1ull << (irq - OCTEON_IRQ_MSI_BIT0));
340 } else {
341 /*
342 * These chips have PCIe. Thankfully the ACK doesn't
343 * need any locking.
344 */
345 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
346 1ull << (irq - OCTEON_IRQ_MSI_BIT0));
347 }
348}
349
350static void octeon_irq_msi_eoi(unsigned int irq)
351{
352 /* Nothing needed */
353}
354
355static void octeon_irq_msi_enable(unsigned int irq)
356{
357 if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
358 /*
359 * Octeon PCI doesn't have the ability to mask/unmask
360 * MSI interrupts individually. Instead of
361 * masking/unmasking them in groups of 16, we simple
362 * assume MSI devices are well behaved. MSI
363 * interrupts are always enable and the ACK is assumed
364 * to be enough.
365 */
366 } else {
367 /* These chips have PCIe. Note that we only support
368 * the first 64 MSI interrupts. Unfortunately all the
369 * MSI enables are in the same register. We use
370 * MSI0's lock to control access to them all.
371 */
372 uint64_t en;
373 unsigned long flags;
374 spin_lock_irqsave(&octeon_irq_msi_lock, flags);
375 en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
376 en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0);
377 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
378 cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
379 spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
380 }
381}
382
383static void octeon_irq_msi_disable(unsigned int irq)
384{
385 if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) {
386 /* See comment in enable */
387 } else {
388 /*
389 * These chips have PCIe. Note that we only support
390 * the first 64 MSI interrupts. Unfortunately all the
391 * MSI enables are in the same register. We use
392 * MSI0's lock to control access to them all.
393 */
394 uint64_t en;
395 unsigned long flags;
396 spin_lock_irqsave(&octeon_irq_msi_lock, flags);
397 en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
398 en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0));
399 cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en);
400 cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0);
401 spin_unlock_irqrestore(&octeon_irq_msi_lock, flags);
402 }
403}
404
405static struct irq_chip octeon_irq_chip_msi = {
406 .name = "MSI",
407 .enable = octeon_irq_msi_enable,
408 .disable = octeon_irq_msi_disable,
409 .ack = octeon_irq_msi_ack,
410 .eoi = octeon_irq_msi_eoi,
411};
412#endif
413
414void __init arch_init_irq(void)
415{
416 int irq;
417
418#ifdef CONFIG_SMP
419 /* Set the default affinity to the boot cpu. */
420 cpumask_clear(irq_default_affinity);
421 cpumask_set_cpu(smp_processor_id(), irq_default_affinity);
422#endif
423
424 if (NR_IRQS < OCTEON_IRQ_LAST)
425 pr_err("octeon_irq_init: NR_IRQS is set too low\n");
426
427 /* 0 - 15 reserved for i8259 master and slave controller. */
428
429 /* 17 - 23 Mips internal */
430 for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) {
431 set_irq_chip_and_handler(irq, &octeon_irq_chip_core,
432 handle_percpu_irq);
433 }
434
435 /* 24 - 87 CIU_INT_SUM0 */
436 for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) {
437 set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu0,
438 handle_percpu_irq);
439 }
440
441 /* 88 - 151 CIU_INT_SUM1 */
442 for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) {
443 set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu1,
444 handle_percpu_irq);
445 }
446
447#ifdef CONFIG_PCI_MSI
448 /* 152 - 215 PCI/PCIe MSI interrupts */
449 for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) {
450 set_irq_chip_and_handler(irq, &octeon_irq_chip_msi,
451 handle_percpu_irq);
452 }
453#endif
454 set_c0_status(0x300 << 2);
455}
456
457asmlinkage void plat_irq_dispatch(void)
458{
459 const unsigned long core_id = cvmx_get_core_num();
460 const uint64_t ciu_sum0_address = CVMX_CIU_INTX_SUM0(core_id * 2);
461 const uint64_t ciu_en0_address = CVMX_CIU_INTX_EN0(core_id * 2);
462 const uint64_t ciu_sum1_address = CVMX_CIU_INT_SUM1;
463 const uint64_t ciu_en1_address = CVMX_CIU_INTX_EN1(core_id * 2 + 1);
464 unsigned long cop0_cause;
465 unsigned long cop0_status;
466 uint64_t ciu_en;
467 uint64_t ciu_sum;
468
469 while (1) {
470 cop0_cause = read_c0_cause();
471 cop0_status = read_c0_status();
472 cop0_cause &= cop0_status;
473 cop0_cause &= ST0_IM;
474
475 if (unlikely(cop0_cause & STATUSF_IP2)) {
476 ciu_sum = cvmx_read_csr(ciu_sum0_address);
477 ciu_en = cvmx_read_csr(ciu_en0_address);
478 ciu_sum &= ciu_en;
479 if (likely(ciu_sum))
480 do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1);
481 else
482 spurious_interrupt();
483 } else if (unlikely(cop0_cause & STATUSF_IP3)) {
484 ciu_sum = cvmx_read_csr(ciu_sum1_address);
485 ciu_en = cvmx_read_csr(ciu_en1_address);
486 ciu_sum &= ciu_en;
487 if (likely(ciu_sum))
488 do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1);
489 else
490 spurious_interrupt();
491 } else if (likely(cop0_cause)) {
492 do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE);
493 } else {
494 break;
495 }
496 }
497}
diff --git a/arch/mips/cavium-octeon/octeon-memcpy.S b/arch/mips/cavium-octeon/octeon-memcpy.S
new file mode 100644
index 000000000000..88e0cddca205
--- /dev/null
+++ b/arch/mips/cavium-octeon/octeon-memcpy.S
@@ -0,0 +1,521 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Unified implementation of memcpy, memmove and the __copy_user backend.
7 *
8 * Copyright (C) 1998, 99, 2000, 01, 2002 Ralf Baechle (ralf@gnu.org)
9 * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc.
10 * Copyright (C) 2002 Broadcom, Inc.
11 * memcpy/copy_user author: Mark Vandevoorde
12 *
13 * Mnemonic names for arguments to memcpy/__copy_user
14 */
15
16#include <asm/asm.h>
17#include <asm/asm-offsets.h>
18#include <asm/regdef.h>
19
20#define dst a0
21#define src a1
22#define len a2
23
24/*
25 * Spec
26 *
27 * memcpy copies len bytes from src to dst and sets v0 to dst.
28 * It assumes that
29 * - src and dst don't overlap
30 * - src is readable
31 * - dst is writable
32 * memcpy uses the standard calling convention
33 *
34 * __copy_user copies up to len bytes from src to dst and sets a2 (len) to
35 * the number of uncopied bytes due to an exception caused by a read or write.
36 * __copy_user assumes that src and dst don't overlap, and that the call is
37 * implementing one of the following:
38 * copy_to_user
39 * - src is readable (no exceptions when reading src)
40 * copy_from_user
41 * - dst is writable (no exceptions when writing dst)
42 * __copy_user uses a non-standard calling convention; see
43 * arch/mips/include/asm/uaccess.h
44 *
45 * When an exception happens on a load, the handler must
46 # ensure that all of the destination buffer is overwritten to prevent
47 * leaking information to user mode programs.
48 */
49
50/*
51 * Implementation
52 */
53
54/*
55 * The exception handler for loads requires that:
56 * 1- AT contain the address of the byte just past the end of the source
57 * of the copy,
58 * 2- src_entry <= src < AT, and
59 * 3- (dst - src) == (dst_entry - src_entry),
60 * The _entry suffix denotes values when __copy_user was called.
61 *
62 * (1) is set up up by uaccess.h and maintained by not writing AT in copy_user
63 * (2) is met by incrementing src by the number of bytes copied
64 * (3) is met by not doing loads between a pair of increments of dst and src
65 *
66 * The exception handlers for stores adjust len (if necessary) and return.
67 * These handlers do not need to overwrite any data.
68 *
69 * For __rmemcpy and memmove an exception is always a kernel bug, therefore
70 * they're not protected.
71 */
72
73#define EXC(inst_reg,addr,handler) \
749: inst_reg, addr; \
75 .section __ex_table,"a"; \
76 PTR 9b, handler; \
77 .previous
78
79/*
80 * Only on the 64-bit kernel we can made use of 64-bit registers.
81 */
82#ifdef CONFIG_64BIT
83#define USE_DOUBLE
84#endif
85
86#ifdef USE_DOUBLE
87
88#define LOAD ld
89#define LOADL ldl
90#define LOADR ldr
91#define STOREL sdl
92#define STORER sdr
93#define STORE sd
94#define ADD daddu
95#define SUB dsubu
96#define SRL dsrl
97#define SRA dsra
98#define SLL dsll
99#define SLLV dsllv
100#define SRLV dsrlv
101#define NBYTES 8
102#define LOG_NBYTES 3
103
104/*
105 * As we are sharing code base with the mips32 tree (which use the o32 ABI
106 * register definitions). We need to redefine the register definitions from
107 * the n64 ABI register naming to the o32 ABI register naming.
108 */
109#undef t0
110#undef t1
111#undef t2
112#undef t3
113#define t0 $8
114#define t1 $9
115#define t2 $10
116#define t3 $11
117#define t4 $12
118#define t5 $13
119#define t6 $14
120#define t7 $15
121
122#else
123
124#define LOAD lw
125#define LOADL lwl
126#define LOADR lwr
127#define STOREL swl
128#define STORER swr
129#define STORE sw
130#define ADD addu
131#define SUB subu
132#define SRL srl
133#define SLL sll
134#define SRA sra
135#define SLLV sllv
136#define SRLV srlv
137#define NBYTES 4
138#define LOG_NBYTES 2
139
140#endif /* USE_DOUBLE */
141
142#ifdef CONFIG_CPU_LITTLE_ENDIAN
143#define LDFIRST LOADR
144#define LDREST LOADL
145#define STFIRST STORER
146#define STREST STOREL
147#define SHIFT_DISCARD SLLV
148#else
149#define LDFIRST LOADL
150#define LDREST LOADR
151#define STFIRST STOREL
152#define STREST STORER
153#define SHIFT_DISCARD SRLV
154#endif
155
156#define FIRST(unit) ((unit)*NBYTES)
157#define REST(unit) (FIRST(unit)+NBYTES-1)
158#define UNIT(unit) FIRST(unit)
159
160#define ADDRMASK (NBYTES-1)
161
162 .text
163 .set noreorder
164 .set noat
165
166/*
167 * A combined memcpy/__copy_user
168 * __copy_user sets len to 0 for success; else to an upper bound of
169 * the number of uncopied bytes.
170 * memcpy sets v0 to dst.
171 */
172 .align 5
173LEAF(memcpy) /* a0=dst a1=src a2=len */
174 move v0, dst /* return value */
175__memcpy:
176FEXPORT(__copy_user)
177 /*
178 * Note: dst & src may be unaligned, len may be 0
179 * Temps
180 */
181 #
182 # Octeon doesn't care if the destination is unaligned. The hardware
183 # can fix it faster than we can special case the assembly.
184 #
185 pref 0, 0(src)
186 sltu t0, len, NBYTES # Check if < 1 word
187 bnez t0, copy_bytes_checklen
188 and t0, src, ADDRMASK # Check if src unaligned
189 bnez t0, src_unaligned
190 sltu t0, len, 4*NBYTES # Check if < 4 words
191 bnez t0, less_than_4units
192 sltu t0, len, 8*NBYTES # Check if < 8 words
193 bnez t0, less_than_8units
194 sltu t0, len, 16*NBYTES # Check if < 16 words
195 bnez t0, cleanup_both_aligned
196 sltu t0, len, 128+1 # Check if len < 129
197 bnez t0, 1f # Skip prefetch if len is too short
198 sltu t0, len, 256+1 # Check if len < 257
199 bnez t0, 1f # Skip prefetch if len is too short
200 pref 0, 128(src) # We must not prefetch invalid addresses
201 #
202 # This is where we loop if there is more than 128 bytes left
2032: pref 0, 256(src) # We must not prefetch invalid addresses
204 #
205 # This is where we loop if we can't prefetch anymore
2061:
207EXC( LOAD t0, UNIT(0)(src), l_exc)
208EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
209EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
210EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
211 SUB len, len, 16*NBYTES
212EXC( STORE t0, UNIT(0)(dst), s_exc_p16u)
213EXC( STORE t1, UNIT(1)(dst), s_exc_p15u)
214EXC( STORE t2, UNIT(2)(dst), s_exc_p14u)
215EXC( STORE t3, UNIT(3)(dst), s_exc_p13u)
216EXC( LOAD t0, UNIT(4)(src), l_exc_copy)
217EXC( LOAD t1, UNIT(5)(src), l_exc_copy)
218EXC( LOAD t2, UNIT(6)(src), l_exc_copy)
219EXC( LOAD t3, UNIT(7)(src), l_exc_copy)
220EXC( STORE t0, UNIT(4)(dst), s_exc_p12u)
221EXC( STORE t1, UNIT(5)(dst), s_exc_p11u)
222EXC( STORE t2, UNIT(6)(dst), s_exc_p10u)
223 ADD src, src, 16*NBYTES
224EXC( STORE t3, UNIT(7)(dst), s_exc_p9u)
225 ADD dst, dst, 16*NBYTES
226EXC( LOAD t0, UNIT(-8)(src), l_exc_copy)
227EXC( LOAD t1, UNIT(-7)(src), l_exc_copy)
228EXC( LOAD t2, UNIT(-6)(src), l_exc_copy)
229EXC( LOAD t3, UNIT(-5)(src), l_exc_copy)
230EXC( STORE t0, UNIT(-8)(dst), s_exc_p8u)
231EXC( STORE t1, UNIT(-7)(dst), s_exc_p7u)
232EXC( STORE t2, UNIT(-6)(dst), s_exc_p6u)
233EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u)
234EXC( LOAD t0, UNIT(-4)(src), l_exc_copy)
235EXC( LOAD t1, UNIT(-3)(src), l_exc_copy)
236EXC( LOAD t2, UNIT(-2)(src), l_exc_copy)
237EXC( LOAD t3, UNIT(-1)(src), l_exc_copy)
238EXC( STORE t0, UNIT(-4)(dst), s_exc_p4u)
239EXC( STORE t1, UNIT(-3)(dst), s_exc_p3u)
240EXC( STORE t2, UNIT(-2)(dst), s_exc_p2u)
241EXC( STORE t3, UNIT(-1)(dst), s_exc_p1u)
242 sltu t0, len, 256+1 # See if we can prefetch more
243 beqz t0, 2b
244 sltu t0, len, 128 # See if we can loop more time
245 beqz t0, 1b
246 nop
247 #
248 # Jump here if there are less than 16*NBYTES left.
249 #
250cleanup_both_aligned:
251 beqz len, done
252 sltu t0, len, 8*NBYTES
253 bnez t0, less_than_8units
254 nop
255EXC( LOAD t0, UNIT(0)(src), l_exc)
256EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
257EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
258EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
259 SUB len, len, 8*NBYTES
260EXC( STORE t0, UNIT(0)(dst), s_exc_p8u)
261EXC( STORE t1, UNIT(1)(dst), s_exc_p7u)
262EXC( STORE t2, UNIT(2)(dst), s_exc_p6u)
263EXC( STORE t3, UNIT(3)(dst), s_exc_p5u)
264EXC( LOAD t0, UNIT(4)(src), l_exc_copy)
265EXC( LOAD t1, UNIT(5)(src), l_exc_copy)
266EXC( LOAD t2, UNIT(6)(src), l_exc_copy)
267EXC( LOAD t3, UNIT(7)(src), l_exc_copy)
268EXC( STORE t0, UNIT(4)(dst), s_exc_p4u)
269EXC( STORE t1, UNIT(5)(dst), s_exc_p3u)
270EXC( STORE t2, UNIT(6)(dst), s_exc_p2u)
271EXC( STORE t3, UNIT(7)(dst), s_exc_p1u)
272 ADD src, src, 8*NBYTES
273 beqz len, done
274 ADD dst, dst, 8*NBYTES
275 #
276 # Jump here if there are less than 8*NBYTES left.
277 #
278less_than_8units:
279 sltu t0, len, 4*NBYTES
280 bnez t0, less_than_4units
281 nop
282EXC( LOAD t0, UNIT(0)(src), l_exc)
283EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
284EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
285EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
286 SUB len, len, 4*NBYTES
287EXC( STORE t0, UNIT(0)(dst), s_exc_p4u)
288EXC( STORE t1, UNIT(1)(dst), s_exc_p3u)
289EXC( STORE t2, UNIT(2)(dst), s_exc_p2u)
290EXC( STORE t3, UNIT(3)(dst), s_exc_p1u)
291 ADD src, src, 4*NBYTES
292 beqz len, done
293 ADD dst, dst, 4*NBYTES
294 #
295 # Jump here if there are less than 4*NBYTES left. This means
296 # we may need to copy up to 3 NBYTES words.
297 #
298less_than_4units:
299 sltu t0, len, 1*NBYTES
300 bnez t0, copy_bytes_checklen
301 nop
302 #
303 # 1) Copy NBYTES, then check length again
304 #
305EXC( LOAD t0, 0(src), l_exc)
306 SUB len, len, NBYTES
307 sltu t1, len, 8
308EXC( STORE t0, 0(dst), s_exc_p1u)
309 ADD src, src, NBYTES
310 bnez t1, copy_bytes_checklen
311 ADD dst, dst, NBYTES
312 #
313 # 2) Copy NBYTES, then check length again
314 #
315EXC( LOAD t0, 0(src), l_exc)
316 SUB len, len, NBYTES
317 sltu t1, len, 8
318EXC( STORE t0, 0(dst), s_exc_p1u)
319 ADD src, src, NBYTES
320 bnez t1, copy_bytes_checklen
321 ADD dst, dst, NBYTES
322 #
323 # 3) Copy NBYTES, then check length again
324 #
325EXC( LOAD t0, 0(src), l_exc)
326 SUB len, len, NBYTES
327 ADD src, src, NBYTES
328 ADD dst, dst, NBYTES
329 b copy_bytes_checklen
330EXC( STORE t0, -8(dst), s_exc_p1u)
331
332src_unaligned:
333#define rem t8
334 SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter
335 beqz t0, cleanup_src_unaligned
336 and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES
3371:
338/*
339 * Avoid consecutive LD*'s to the same register since some mips
340 * implementations can't issue them in the same cycle.
341 * It's OK to load FIRST(N+1) before REST(N) because the two addresses
342 * are to the same unit (unless src is aligned, but it's not).
343 */
344EXC( LDFIRST t0, FIRST(0)(src), l_exc)
345EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy)
346 SUB len, len, 4*NBYTES
347EXC( LDREST t0, REST(0)(src), l_exc_copy)
348EXC( LDREST t1, REST(1)(src), l_exc_copy)
349EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy)
350EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy)
351EXC( LDREST t2, REST(2)(src), l_exc_copy)
352EXC( LDREST t3, REST(3)(src), l_exc_copy)
353 ADD src, src, 4*NBYTES
354EXC( STORE t0, UNIT(0)(dst), s_exc_p4u)
355EXC( STORE t1, UNIT(1)(dst), s_exc_p3u)
356EXC( STORE t2, UNIT(2)(dst), s_exc_p2u)
357EXC( STORE t3, UNIT(3)(dst), s_exc_p1u)
358 bne len, rem, 1b
359 ADD dst, dst, 4*NBYTES
360
361cleanup_src_unaligned:
362 beqz len, done
363 and rem, len, NBYTES-1 # rem = len % NBYTES
364 beq rem, len, copy_bytes
365 nop
3661:
367EXC( LDFIRST t0, FIRST(0)(src), l_exc)
368EXC( LDREST t0, REST(0)(src), l_exc_copy)
369 SUB len, len, NBYTES
370EXC( STORE t0, 0(dst), s_exc_p1u)
371 ADD src, src, NBYTES
372 bne len, rem, 1b
373 ADD dst, dst, NBYTES
374
375copy_bytes_checklen:
376 beqz len, done
377 nop
378copy_bytes:
379 /* 0 < len < NBYTES */
380#define COPY_BYTE(N) \
381EXC( lb t0, N(src), l_exc); \
382 SUB len, len, 1; \
383 beqz len, done; \
384EXC( sb t0, N(dst), s_exc_p1)
385
386 COPY_BYTE(0)
387 COPY_BYTE(1)
388#ifdef USE_DOUBLE
389 COPY_BYTE(2)
390 COPY_BYTE(3)
391 COPY_BYTE(4)
392 COPY_BYTE(5)
393#endif
394EXC( lb t0, NBYTES-2(src), l_exc)
395 SUB len, len, 1
396 jr ra
397EXC( sb t0, NBYTES-2(dst), s_exc_p1)
398done:
399 jr ra
400 nop
401 END(memcpy)
402
403l_exc_copy:
404 /*
405 * Copy bytes from src until faulting load address (or until a
406 * lb faults)
407 *
408 * When reached by a faulting LDFIRST/LDREST, THREAD_BUADDR($28)
409 * may be more than a byte beyond the last address.
410 * Hence, the lb below may get an exception.
411 *
412 * Assumes src < THREAD_BUADDR($28)
413 */
414 LOAD t0, TI_TASK($28)
415 nop
416 LOAD t0, THREAD_BUADDR(t0)
4171:
418EXC( lb t1, 0(src), l_exc)
419 ADD src, src, 1
420 sb t1, 0(dst) # can't fault -- we're copy_from_user
421 bne src, t0, 1b
422 ADD dst, dst, 1
423l_exc:
424 LOAD t0, TI_TASK($28)
425 nop
426 LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address
427 nop
428 SUB len, AT, t0 # len number of uncopied bytes
429 /*
430 * Here's where we rely on src and dst being incremented in tandem,
431 * See (3) above.
432 * dst += (fault addr - src) to put dst at first byte to clear
433 */
434 ADD dst, t0 # compute start address in a1
435 SUB dst, src
436 /*
437 * Clear len bytes starting at dst. Can't call __bzero because it
438 * might modify len. An inefficient loop for these rare times...
439 */
440 beqz len, done
441 SUB src, len, 1
4421: sb zero, 0(dst)
443 ADD dst, dst, 1
444 bnez src, 1b
445 SUB src, src, 1
446 jr ra
447 nop
448
449
450#define SEXC(n) \
451s_exc_p ## n ## u: \
452 jr ra; \
453 ADD len, len, n*NBYTES
454
455SEXC(16)
456SEXC(15)
457SEXC(14)
458SEXC(13)
459SEXC(12)
460SEXC(11)
461SEXC(10)
462SEXC(9)
463SEXC(8)
464SEXC(7)
465SEXC(6)
466SEXC(5)
467SEXC(4)
468SEXC(3)
469SEXC(2)
470SEXC(1)
471
472s_exc_p1:
473 jr ra
474 ADD len, len, 1
475s_exc:
476 jr ra
477 nop
478
479 .align 5
480LEAF(memmove)
481 ADD t0, a0, a2
482 ADD t1, a1, a2
483 sltu t0, a1, t0 # dst + len <= src -> memcpy
484 sltu t1, a0, t1 # dst >= src + len -> memcpy
485 and t0, t1
486 beqz t0, __memcpy
487 move v0, a0 /* return value */
488 beqz a2, r_out
489 END(memmove)
490
491 /* fall through to __rmemcpy */
492LEAF(__rmemcpy) /* a0=dst a1=src a2=len */
493 sltu t0, a1, a0
494 beqz t0, r_end_bytes_up # src >= dst
495 nop
496 ADD a0, a2 # dst = dst + len
497 ADD a1, a2 # src = src + len
498
499r_end_bytes:
500 lb t0, -1(a1)
501 SUB a2, a2, 0x1
502 sb t0, -1(a0)
503 SUB a1, a1, 0x1
504 bnez a2, r_end_bytes
505 SUB a0, a0, 0x1
506
507r_out:
508 jr ra
509 move a2, zero
510
511r_end_bytes_up:
512 lb t0, (a1)
513 SUB a2, a2, 0x1
514 sb t0, (a0)
515 ADD a1, a1, 0x1
516 bnez a2, r_end_bytes_up
517 ADD a0, a0, 0x1
518
519 jr ra
520 move a2, zero
521 END(__rmemcpy)
diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c
new file mode 100644
index 000000000000..8240728d485a
--- /dev/null
+++ b/arch/mips/cavium-octeon/serial.c
@@ -0,0 +1,136 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2007 Cavium Networks
7 */
8#include <linux/console.h>
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/platform_device.h>
12#include <linux/serial.h>
13#include <linux/serial_8250.h>
14#include <linux/serial_reg.h>
15#include <linux/tty.h>
16
17#include <asm/time.h>
18
19#include <asm/octeon/octeon.h>
20
21#ifdef CONFIG_GDB_CONSOLE
22#define DEBUG_UART 0
23#else
24#define DEBUG_UART 1
25#endif
26
27unsigned int octeon_serial_in(struct uart_port *up, int offset)
28{
29 int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
30 if (offset == UART_IIR && (rv & 0xf) == 7) {
31 /* Busy interrupt, read the USR (39) and try again. */
32 cvmx_read_csr((uint64_t)(up->membase + (39 << 3)));
33 rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3)));
34 }
35 return rv;
36}
37
38void octeon_serial_out(struct uart_port *up, int offset, int value)
39{
40 /*
41 * If bits 6 or 7 of the OCTEON UART's LCR are set, it quits
42 * working.
43 */
44 if (offset == UART_LCR)
45 value &= 0x9f;
46 cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value);
47}
48
49/*
50 * Allocated in .bss, so it is all zeroed.
51 */
52#define OCTEON_MAX_UARTS 3
53static struct plat_serial8250_port octeon_uart8250_data[OCTEON_MAX_UARTS + 1];
54static struct platform_device octeon_uart8250_device = {
55 .name = "serial8250",
56 .id = PLAT8250_DEV_PLATFORM,
57 .dev = {
58 .platform_data = octeon_uart8250_data,
59 },
60};
61
62static void __init octeon_uart_set_common(struct plat_serial8250_port *p)
63{
64 p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
65 p->type = PORT_OCTEON;
66 p->iotype = UPIO_MEM;
67 p->regshift = 3; /* I/O addresses are every 8 bytes */
68 p->uartclk = mips_hpt_frequency;
69 p->serial_in = octeon_serial_in;
70 p->serial_out = octeon_serial_out;
71}
72
73static int __init octeon_serial_init(void)
74{
75 int enable_uart0;
76 int enable_uart1;
77 int enable_uart2;
78 struct plat_serial8250_port *p;
79
80#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
81 /*
82 * If we are configured to run as the second of two kernels,
83 * disable uart0 and enable uart1. Uart0 is owned by the first
84 * kernel
85 */
86 enable_uart0 = 0;
87 enable_uart1 = 1;
88#else
89 /*
90 * We are configured for the first kernel. We'll enable uart0
91 * if the bootloader told us to use 0, otherwise will enable
92 * uart 1.
93 */
94 enable_uart0 = (octeon_get_boot_uart() == 0);
95 enable_uart1 = (octeon_get_boot_uart() == 1);
96#ifdef CONFIG_KGDB
97 enable_uart1 = 1;
98#endif
99#endif
100
101 /* Right now CN52XX is the only chip with a third uart */
102 enable_uart2 = OCTEON_IS_MODEL(OCTEON_CN52XX);
103
104 p = octeon_uart8250_data;
105 if (enable_uart0) {
106 /* Add a ttyS device for hardware uart 0 */
107 octeon_uart_set_common(p);
108 p->membase = (void *) CVMX_MIO_UARTX_RBR(0);
109 p->mapbase = CVMX_MIO_UARTX_RBR(0) & ((1ull << 49) - 1);
110 p->irq = OCTEON_IRQ_UART0;
111 p++;
112 }
113
114 if (enable_uart1) {
115 /* Add a ttyS device for hardware uart 1 */
116 octeon_uart_set_common(p);
117 p->membase = (void *) CVMX_MIO_UARTX_RBR(1);
118 p->mapbase = CVMX_MIO_UARTX_RBR(1) & ((1ull << 49) - 1);
119 p->irq = OCTEON_IRQ_UART1;
120 p++;
121 }
122 if (enable_uart2) {
123 /* Add a ttyS device for hardware uart 2 */
124 octeon_uart_set_common(p);
125 p->membase = (void *) CVMX_MIO_UART2_RBR;
126 p->mapbase = CVMX_MIO_UART2_RBR & ((1ull << 49) - 1);
127 p->irq = OCTEON_IRQ_UART2;
128 p++;
129 }
130
131 BUG_ON(p > &octeon_uart8250_data[OCTEON_MAX_UARTS]);
132
133 return platform_device_register(&octeon_uart8250_device);
134}
135
136device_initcall(octeon_serial_init);
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
new file mode 100644
index 000000000000..e085feddb4a4
--- /dev/null
+++ b/arch/mips/cavium-octeon/setup.c
@@ -0,0 +1,929 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2007 Cavium Networks
7 * Copyright (C) 2008 Wind River Systems
8 */
9#include <linux/init.h>
10#include <linux/console.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/irq.h>
15#include <linux/serial.h>
16#include <linux/types.h>
17#include <linux/string.h> /* for memset */
18#include <linux/serial.h>
19#include <linux/tty.h>
20#include <linux/time.h>
21#include <linux/platform_device.h>
22#include <linux/serial_core.h>
23#include <linux/serial_8250.h>
24#include <linux/string.h>
25
26#include <asm/processor.h>
27#include <asm/reboot.h>
28#include <asm/smp-ops.h>
29#include <asm/system.h>
30#include <asm/irq_cpu.h>
31#include <asm/mipsregs.h>
32#include <asm/bootinfo.h>
33#include <asm/sections.h>
34#include <asm/time.h>
35
36#include <asm/octeon/octeon.h>
37
38#ifdef CONFIG_CAVIUM_DECODE_RSL
39extern void cvmx_interrupt_rsl_decode(void);
40extern int __cvmx_interrupt_ecc_report_single_bit_errors;
41extern void cvmx_interrupt_rsl_enable(void);
42#endif
43
44extern struct plat_smp_ops octeon_smp_ops;
45
46#ifdef CONFIG_PCI
47extern void pci_console_init(const char *arg);
48#endif
49
50#ifdef CONFIG_CAVIUM_RESERVE32
51extern uint64_t octeon_reserve32_memory;
52#endif
53static unsigned long long MAX_MEMORY = 512ull << 20;
54
55struct octeon_boot_descriptor *octeon_boot_desc_ptr;
56
57struct cvmx_bootinfo *octeon_bootinfo;
58EXPORT_SYMBOL(octeon_bootinfo);
59
60#ifdef CONFIG_CAVIUM_RESERVE32
61uint64_t octeon_reserve32_memory;
62EXPORT_SYMBOL(octeon_reserve32_memory);
63#endif
64
65static int octeon_uart;
66
67extern asmlinkage void handle_int(void);
68extern asmlinkage void plat_irq_dispatch(void);
69
70/**
71 * Return non zero if we are currently running in the Octeon simulator
72 *
73 * Returns
74 */
75int octeon_is_simulation(void)
76{
77 return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM;
78}
79EXPORT_SYMBOL(octeon_is_simulation);
80
81/**
82 * Return true if Octeon is in PCI Host mode. This means
83 * Linux can control the PCI bus.
84 *
85 * Returns Non zero if Octeon in host mode.
86 */
87int octeon_is_pci_host(void)
88{
89#ifdef CONFIG_PCI
90 return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST;
91#else
92 return 0;
93#endif
94}
95
96/**
97 * Get the clock rate of Octeon
98 *
99 * Returns Clock rate in HZ
100 */
101uint64_t octeon_get_clock_rate(void)
102{
103 if (octeon_is_simulation())
104 octeon_bootinfo->eclock_hz = 6000000;
105 return octeon_bootinfo->eclock_hz;
106}
107EXPORT_SYMBOL(octeon_get_clock_rate);
108
109/**
110 * Write to the LCD display connected to the bootbus. This display
111 * exists on most Cavium evaluation boards. If it doesn't exist, then
112 * this function doesn't do anything.
113 *
114 * @s: String to write
115 */
116void octeon_write_lcd(const char *s)
117{
118 if (octeon_bootinfo->led_display_base_addr) {
119 void __iomem *lcd_address =
120 ioremap_nocache(octeon_bootinfo->led_display_base_addr,
121 8);
122 int i;
123 for (i = 0; i < 8; i++, s++) {
124 if (*s)
125 iowrite8(*s, lcd_address + i);
126 else
127 iowrite8(' ', lcd_address + i);
128 }
129 iounmap(lcd_address);
130 }
131}
132
133/**
134 * Return the console uart passed by the bootloader
135 *
136 * Returns uart (0 or 1)
137 */
138int octeon_get_boot_uart(void)
139{
140 int uart;
141#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
142 uart = 1;
143#else
144 uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ?
145 1 : 0;
146#endif
147 return uart;
148}
149
150/**
151 * Get the coremask Linux was booted on.
152 *
153 * Returns Core mask
154 */
155int octeon_get_boot_coremask(void)
156{
157 return octeon_boot_desc_ptr->core_mask;
158}
159
160/**
161 * Check the hardware BIST results for a CPU
162 */
163void octeon_check_cpu_bist(void)
164{
165 const int coreid = cvmx_get_core_num();
166 unsigned long long mask;
167 unsigned long long bist_val;
168
169 /* Check BIST results for COP0 registers */
170 mask = 0x1f00000000ull;
171 bist_val = read_octeon_c0_icacheerr();
172 if (bist_val & mask)
173 pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n",
174 coreid, bist_val);
175
176 bist_val = read_octeon_c0_dcacheerr();
177 if (bist_val & 1)
178 pr_err("Core%d L1 Dcache parity error: "
179 "CacheErr(dcache) = 0x%llx\n",
180 coreid, bist_val);
181
182 mask = 0xfc00000000000000ull;
183 bist_val = read_c0_cvmmemctl();
184 if (bist_val & mask)
185 pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n",
186 coreid, bist_val);
187
188 write_octeon_c0_dcacheerr(0);
189}
190
191#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB
192/**
193 * Called on every core to setup the wired tlb entry needed
194 * if CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB is set.
195 *
196 */
197static void octeon_hal_setup_per_cpu_reserved32(void *unused)
198{
199 /*
200 * The config has selected to wire the reserve32 memory for all
201 * userspace applications. We need to put a wired TLB entry in for each
202 * 512MB of reserve32 memory. We only handle double 256MB pages here,
203 * so reserve32 must be multiple of 512MB.
204 */
205 uint32_t size = CONFIG_CAVIUM_RESERVE32;
206 uint32_t entrylo0 =
207 0x7 | ((octeon_reserve32_memory & ((1ul << 40) - 1)) >> 6);
208 uint32_t entrylo1 = entrylo0 + (256 << 14);
209 uint32_t entryhi = (0x80000000UL - (CONFIG_CAVIUM_RESERVE32 << 20));
210 while (size >= 512) {
211#if 0
212 pr_info("CPU%d: Adding double wired TLB entry for 0x%lx\n",
213 smp_processor_id(), entryhi);
214#endif
215 add_wired_entry(entrylo0, entrylo1, entryhi, PM_256M);
216 entrylo0 += 512 << 14;
217 entrylo1 += 512 << 14;
218 entryhi += 512 << 20;
219 size -= 512;
220 }
221}
222#endif /* CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB */
223
224/**
225 * Called to release the named block which was used to made sure
226 * that nobody used the memory for something else during
227 * init. Now we'll free it so userspace apps can use this
228 * memory region with bootmem_alloc.
229 *
230 * This function is called only once from prom_free_prom_memory().
231 */
232void octeon_hal_setup_reserved32(void)
233{
234#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB
235 on_each_cpu(octeon_hal_setup_per_cpu_reserved32, NULL, 0, 1);
236#endif
237}
238
239/**
240 * Reboot Octeon
241 *
242 * @command: Command to pass to the bootloader. Currently ignored.
243 */
244static void octeon_restart(char *command)
245{
246 /* Disable all watchdogs before soft reset. They don't get cleared */
247#ifdef CONFIG_SMP
248 int cpu;
249 for_each_online_cpu(cpu)
250 cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0);
251#else
252 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
253#endif
254
255 mb();
256 while (1)
257 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
258}
259
260
261/**
262 * Permanently stop a core.
263 *
264 * @arg: Ignored.
265 */
266static void octeon_kill_core(void *arg)
267{
268 mb();
269 if (octeon_is_simulation()) {
270 /* The simulator needs the watchdog to stop for dead cores */
271 cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0);
272 /* A break instruction causes the simulator stop a core */
273 asm volatile ("sync\nbreak");
274 }
275}
276
277
278/**
279 * Halt the system
280 */
281static void octeon_halt(void)
282{
283 smp_call_function(octeon_kill_core, NULL, 0);
284
285 switch (octeon_bootinfo->board_type) {
286 case CVMX_BOARD_TYPE_NAO38:
287 /* Driving a 1 to GPIO 12 shuts off this board */
288 cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1);
289 cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000);
290 break;
291 default:
292 octeon_write_lcd("PowerOff");
293 break;
294 }
295
296 octeon_kill_core(NULL);
297}
298
299#if 0
300/**
301 * Platform time init specifics.
302 * Returns
303 */
304void __init plat_time_init(void)
305{
306 /* Nothing special here, but we are required to have one */
307}
308
309#endif
310
311/**
312 * Handle all the error condition interrupts that might occur.
313 *
314 */
315#ifdef CONFIG_CAVIUM_DECODE_RSL
316static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id)
317{
318 cvmx_interrupt_rsl_decode();
319 return IRQ_HANDLED;
320}
321#endif
322
323/**
324 * Return a string representing the system type
325 *
326 * Returns
327 */
328const char *octeon_board_type_string(void)
329{
330 static char name[80];
331 sprintf(name, "%s (%s)",
332 cvmx_board_type_to_string(octeon_bootinfo->board_type),
333 octeon_model_get_string(read_c0_prid()));
334 return name;
335}
336
337const char *get_system_type(void)
338 __attribute__ ((alias("octeon_board_type_string")));
339
340void octeon_user_io_init(void)
341{
342 union octeon_cvmemctl cvmmemctl;
343 union cvmx_iob_fau_timeout fau_timeout;
344 union cvmx_pow_nw_tim nm_tim;
345 uint64_t cvmctl;
346
347 /* Get the current settings for CP0_CVMMEMCTL_REG */
348 cvmmemctl.u64 = read_c0_cvmmemctl();
349 /* R/W If set, marked write-buffer entries time out the same
350 * as as other entries; if clear, marked write-buffer entries
351 * use the maximum timeout. */
352 cvmmemctl.s.dismarkwblongto = 1;
353 /* R/W If set, a merged store does not clear the write-buffer
354 * entry timeout state. */
355 cvmmemctl.s.dismrgclrwbto = 0;
356 /* R/W Two bits that are the MSBs of the resultant CVMSEG LM
357 * word location for an IOBDMA. The other 8 bits come from the
358 * SCRADDR field of the IOBDMA. */
359 cvmmemctl.s.iobdmascrmsb = 0;
360 /* R/W If set, SYNCWS and SYNCS only order marked stores; if
361 * clear, SYNCWS and SYNCS only order unmarked
362 * stores. SYNCWSMARKED has no effect when DISSYNCWS is
363 * set. */
364 cvmmemctl.s.syncwsmarked = 0;
365 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */
366 cvmmemctl.s.dissyncws = 0;
367 /* R/W If set, no stall happens on write buffer full. */
368 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2))
369 cvmmemctl.s.diswbfst = 1;
370 else
371 cvmmemctl.s.diswbfst = 0;
372 /* R/W If set (and SX set), supervisor-level loads/stores can
373 * use XKPHYS addresses with <48>==0 */
374 cvmmemctl.s.xkmemenas = 0;
375
376 /* R/W If set (and UX set), user-level loads/stores can use
377 * XKPHYS addresses with VA<48>==0 */
378 cvmmemctl.s.xkmemenau = 0;
379
380 /* R/W If set (and SX set), supervisor-level loads/stores can
381 * use XKPHYS addresses with VA<48>==1 */
382 cvmmemctl.s.xkioenas = 0;
383
384 /* R/W If set (and UX set), user-level loads/stores can use
385 * XKPHYS addresses with VA<48>==1 */
386 cvmmemctl.s.xkioenau = 0;
387
388 /* R/W If set, all stores act as SYNCW (NOMERGE must be set
389 * when this is set) RW, reset to 0. */
390 cvmmemctl.s.allsyncw = 0;
391
392 /* R/W If set, no stores merge, and all stores reach the
393 * coherent bus in order. */
394 cvmmemctl.s.nomerge = 0;
395 /* R/W Selects the bit in the counter used for DID time-outs 0
396 * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is
397 * between 1x and 2x this interval. For example, with
398 * DIDTTO=3, expiration interval is between 16K and 32K. */
399 cvmmemctl.s.didtto = 0;
400 /* R/W If set, the (mem) CSR clock never turns off. */
401 cvmmemctl.s.csrckalwys = 0;
402 /* R/W If set, mclk never turns off. */
403 cvmmemctl.s.mclkalwys = 0;
404 /* R/W Selects the bit in the counter used for write buffer
405 * flush time-outs (WBFLT+11) is the bit position in an
406 * internal counter used to determine expiration. The write
407 * buffer expires between 1x and 2x this interval. For
408 * example, with WBFLT = 0, a write buffer expires between 2K
409 * and 4K cycles after the write buffer entry is allocated. */
410 cvmmemctl.s.wbfltime = 0;
411 /* R/W If set, do not put Istream in the L2 cache. */
412 cvmmemctl.s.istrnol2 = 0;
413 /* R/W The write buffer threshold. */
414 cvmmemctl.s.wbthresh = 10;
415 /* R/W If set, CVMSEG is available for loads/stores in
416 * kernel/debug mode. */
417#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
418 cvmmemctl.s.cvmsegenak = 1;
419#else
420 cvmmemctl.s.cvmsegenak = 0;
421#endif
422 /* R/W If set, CVMSEG is available for loads/stores in
423 * supervisor mode. */
424 cvmmemctl.s.cvmsegenas = 0;
425 /* R/W If set, CVMSEG is available for loads/stores in user
426 * mode. */
427 cvmmemctl.s.cvmsegenau = 0;
428 /* R/W Size of local memory in cache blocks, 54 (6912 bytes)
429 * is max legal value. */
430 cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
431
432
433 if (smp_processor_id() == 0)
434 pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
435 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
436 CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
437
438 write_c0_cvmmemctl(cvmmemctl.u64);
439
440 /* Move the performance counter interrupts to IRQ 6 */
441 cvmctl = read_c0_cvmctl();
442 cvmctl &= ~(7 << 7);
443 cvmctl |= 6 << 7;
444 write_c0_cvmctl(cvmctl);
445
446 /* Set a default for the hardware timeouts */
447 fau_timeout.u64 = 0;
448 fau_timeout.s.tout_val = 0xfff;
449 /* Disable tagwait FAU timeout */
450 fau_timeout.s.tout_enb = 0;
451 cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64);
452
453 nm_tim.u64 = 0;
454 /* 4096 cycles */
455 nm_tim.s.nw_tim = 3;
456 cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64);
457
458 write_octeon_c0_icacheerr(0);
459 write_c0_derraddr1(0);
460}
461
462/**
463 * Early entry point for arch setup
464 */
465void __init prom_init(void)
466{
467 struct cvmx_sysinfo *sysinfo;
468 const int coreid = cvmx_get_core_num();
469 int i;
470 int argc;
471 struct uart_port octeon_port;
472#ifdef CONFIG_CAVIUM_RESERVE32
473 int64_t addr = -1;
474#endif
475 /*
476 * The bootloader passes a pointer to the boot descriptor in
477 * $a3, this is available as fw_arg3.
478 */
479 octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3;
480 octeon_bootinfo =
481 cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr);
482 cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr));
483
484 /*
485 * Only enable the LED controller if we're running on a CN38XX, CN58XX,
486 * or CN56XX. The CN30XX and CN31XX don't have an LED controller.
487 */
488 if (!octeon_is_simulation() &&
489 octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) {
490 cvmx_write_csr(CVMX_LED_EN, 0);
491 cvmx_write_csr(CVMX_LED_PRT, 0);
492 cvmx_write_csr(CVMX_LED_DBG, 0);
493 cvmx_write_csr(CVMX_LED_PRT_FMT, 0);
494 cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32);
495 cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32);
496 cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0);
497 cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0);
498 cvmx_write_csr(CVMX_LED_EN, 1);
499 }
500#ifdef CONFIG_CAVIUM_RESERVE32
501 /*
502 * We need to temporarily allocate all memory in the reserve32
503 * region. This makes sure the kernel doesn't allocate this
504 * memory when it is getting memory from the
505 * bootloader. Later, after the memory allocations are
506 * complete, the reserve32 will be freed.
507 */
508#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB
509 if (CONFIG_CAVIUM_RESERVE32 & 0x1ff)
510 pr_err("CAVIUM_RESERVE32 isn't a multiple of 512MB. "
511 "This is required if CAVIUM_RESERVE32_USE_WIRED_TLB "
512 "is set\n");
513 else
514 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
515 0, 0, 512 << 20,
516 "CAVIUM_RESERVE32", 0);
517#else
518 /*
519 * Allocate memory for RESERVED32 aligned on 2MB boundary. This
520 * is in case we later use hugetlb entries with it.
521 */
522 addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20,
523 0, 0, 2 << 20,
524 "CAVIUM_RESERVE32", 0);
525#endif
526 if (addr < 0)
527 pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n");
528 else
529 octeon_reserve32_memory = addr;
530#endif
531
532#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2
533 if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) {
534 pr_info("Skipping L2 locking due to reduced L2 cache size\n");
535 } else {
536 uint32_t ebase = read_c0_ebase() & 0x3ffff000;
537#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB
538 /* TLB refill */
539 cvmx_l2c_lock_mem_region(ebase, 0x100);
540#endif
541#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION
542 /* General exception */
543 cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80);
544#endif
545#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT
546 /* Interrupt handler */
547 cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80);
548#endif
549#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT
550 cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100);
551 cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80);
552#endif
553#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY
554 cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480);
555#endif
556 }
557#endif
558
559 sysinfo = cvmx_sysinfo_get();
560 memset(sysinfo, 0, sizeof(*sysinfo));
561 sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20;
562 sysinfo->phy_mem_desc_ptr =
563 cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr);
564 sysinfo->core_mask = octeon_bootinfo->core_mask;
565 sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr;
566 sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz;
567 sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2;
568 sysinfo->board_type = octeon_bootinfo->board_type;
569 sysinfo->board_rev_major = octeon_bootinfo->board_rev_major;
570 sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor;
571 memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base,
572 sizeof(sysinfo->mac_addr_base));
573 sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count;
574 memcpy(sysinfo->board_serial_number,
575 octeon_bootinfo->board_serial_number,
576 sizeof(sysinfo->board_serial_number));
577 sysinfo->compact_flash_common_base_addr =
578 octeon_bootinfo->compact_flash_common_base_addr;
579 sysinfo->compact_flash_attribute_base_addr =
580 octeon_bootinfo->compact_flash_attribute_base_addr;
581 sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr;
582 sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz;
583 sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags;
584
585
586 octeon_check_cpu_bist();
587
588 octeon_uart = octeon_get_boot_uart();
589
590 /*
591 * Disable All CIU Interrupts. The ones we need will be
592 * enabled later. Read the SUM register so we know the write
593 * completed.
594 */
595 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0);
596 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
597 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
598 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
599 cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2)));
600
601#ifdef CONFIG_SMP
602 octeon_write_lcd("LinuxSMP");
603#else
604 octeon_write_lcd("Linux");
605#endif
606
607#ifdef CONFIG_CAVIUM_GDB
608 /*
609 * When debugging the linux kernel, force the cores to enter
610 * the debug exception handler to break in.
611 */
612 if (octeon_get_boot_debug_flag()) {
613 cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num());
614 cvmx_read_csr(CVMX_CIU_DINT);
615 }
616#endif
617
618 /*
619 * BIST should always be enabled when doing a soft reset. L2
620 * Cache locking for instance is not cleared unless BIST is
621 * enabled. Unfortunately due to a chip errata G-200 for
622 * Cn38XX and CN31XX, BIST msut be disabled on these parts.
623 */
624 if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
625 OCTEON_IS_MODEL(OCTEON_CN31XX))
626 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0);
627 else
628 cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1);
629
630 /* Default to 64MB in the simulator to speed things up */
631 if (octeon_is_simulation())
632 MAX_MEMORY = 64ull << 20;
633
634 arcs_cmdline[0] = 0;
635 argc = octeon_boot_desc_ptr->argc;
636 for (i = 0; i < argc; i++) {
637 const char *arg =
638 cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]);
639 if ((strncmp(arg, "MEM=", 4) == 0) ||
640 (strncmp(arg, "mem=", 4) == 0)) {
641 sscanf(arg + 4, "%llu", &MAX_MEMORY);
642 MAX_MEMORY <<= 20;
643 if (MAX_MEMORY == 0)
644 MAX_MEMORY = 32ull << 30;
645 } else if (strcmp(arg, "ecc_verbose") == 0) {
646#ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC
647 __cvmx_interrupt_ecc_report_single_bit_errors = 1;
648 pr_notice("Reporting of single bit ECC errors is "
649 "turned on\n");
650#endif
651 } else if (strlen(arcs_cmdline) + strlen(arg) + 1 <
652 sizeof(arcs_cmdline) - 1) {
653 strcat(arcs_cmdline, " ");
654 strcat(arcs_cmdline, arg);
655 }
656 }
657
658 if (strstr(arcs_cmdline, "console=") == NULL) {
659#ifdef CONFIG_GDB_CONSOLE
660 strcat(arcs_cmdline, " console=gdb");
661#else
662#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
663 strcat(arcs_cmdline, " console=ttyS0,115200");
664#else
665 if (octeon_uart == 1)
666 strcat(arcs_cmdline, " console=ttyS1,115200");
667 else
668 strcat(arcs_cmdline, " console=ttyS0,115200");
669#endif
670#endif
671 }
672
673 if (octeon_is_simulation()) {
674 /*
675 * The simulator uses a mtdram device pre filled with
676 * the filesystem. Also specify the calibration delay
677 * to avoid calculating it every time.
678 */
679 strcat(arcs_cmdline, " rw root=1f00"
680 " lpj=60176 slram=root,0x40000000,+1073741824");
681 }
682
683 mips_hpt_frequency = octeon_get_clock_rate();
684
685 octeon_init_cvmcount();
686
687 _machine_restart = octeon_restart;
688 _machine_halt = octeon_halt;
689
690 memset(&octeon_port, 0, sizeof(octeon_port));
691 /*
692 * For early_serial_setup we don't set the port type or
693 * UPF_FIXED_TYPE.
694 */
695 octeon_port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ;
696 octeon_port.iotype = UPIO_MEM;
697 /* I/O addresses are every 8 bytes */
698 octeon_port.regshift = 3;
699 /* Clock rate of the chip */
700 octeon_port.uartclk = mips_hpt_frequency;
701 octeon_port.fifosize = 64;
702 octeon_port.mapbase = 0x0001180000000800ull + (1024 * octeon_uart);
703 octeon_port.membase = cvmx_phys_to_ptr(octeon_port.mapbase);
704 octeon_port.serial_in = octeon_serial_in;
705 octeon_port.serial_out = octeon_serial_out;
706#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL
707 octeon_port.line = 0;
708#else
709 octeon_port.line = octeon_uart;
710#endif
711 octeon_port.irq = 42 + octeon_uart;
712 early_serial_setup(&octeon_port);
713
714 octeon_user_io_init();
715 register_smp_ops(&octeon_smp_ops);
716}
717
718void __init plat_mem_setup(void)
719{
720 uint64_t mem_alloc_size;
721 uint64_t total;
722 int64_t memory;
723
724 total = 0;
725
726 /* First add the init memory we will be returning. */
727 memory = __pa_symbol(&__init_begin) & PAGE_MASK;
728 mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory;
729 if (mem_alloc_size > 0) {
730 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
731 total += mem_alloc_size;
732 }
733
734 /*
735 * The Mips memory init uses the first memory location for
736 * some memory vectors. When SPARSEMEM is in use, it doesn't
737 * verify that the size is big enough for the final
738 * vectors. Making the smallest chuck 4MB seems to be enough
739 * to consistantly work.
740 */
741 mem_alloc_size = 4 << 20;
742 if (mem_alloc_size > MAX_MEMORY)
743 mem_alloc_size = MAX_MEMORY;
744
745 /*
746 * When allocating memory, we want incrementing addresses from
747 * bootmem_alloc so the code in add_memory_region can merge
748 * regions next to each other.
749 */
750 cvmx_bootmem_lock();
751 while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX)
752 && (total < MAX_MEMORY)) {
753#if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR)
754 memory = cvmx_bootmem_phy_alloc(mem_alloc_size,
755 __pa_symbol(&__init_end), -1,
756 0x100000,
757 CVMX_BOOTMEM_FLAG_NO_LOCKING);
758#elif defined(CONFIG_HIGHMEM)
759 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31,
760 0x100000,
761 CVMX_BOOTMEM_FLAG_NO_LOCKING);
762#else
763 memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20,
764 0x100000,
765 CVMX_BOOTMEM_FLAG_NO_LOCKING);
766#endif
767 if (memory >= 0) {
768 /*
769 * This function automatically merges address
770 * regions next to each other if they are
771 * received in incrementing order.
772 */
773 add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM);
774 total += mem_alloc_size;
775 } else {
776 break;
777 }
778 }
779 cvmx_bootmem_unlock();
780
781#ifdef CONFIG_CAVIUM_RESERVE32
782 /*
783 * Now that we've allocated the kernel memory it is safe to
784 * free the reserved region. We free it here so that builtin
785 * drivers can use the memory.
786 */
787 if (octeon_reserve32_memory)
788 cvmx_bootmem_free_named("CAVIUM_RESERVE32");
789#endif /* CONFIG_CAVIUM_RESERVE32 */
790
791 if (total == 0)
792 panic("Unable to allocate memory from "
793 "cvmx_bootmem_phy_alloc\n");
794}
795
796
797int prom_putchar(char c)
798{
799 uint64_t lsrval;
800
801 /* Spin until there is room */
802 do {
803 lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart));
804 } while ((lsrval & 0x20) == 0);
805
806 /* Write the byte */
807 cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c);
808 return 1;
809}
810
811void prom_free_prom_memory(void)
812{
813#ifdef CONFIG_CAVIUM_DECODE_RSL
814 cvmx_interrupt_rsl_enable();
815
816 /* Add an interrupt handler for general failures. */
817 if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED,
818 "RML/RSL", octeon_rlm_interrupt)) {
819 panic("Unable to request_irq(OCTEON_IRQ_RML)\n");
820 }
821#endif
822
823 /* This call is here so that it is performed after any TLB
824 initializations. It needs to be after these in case the
825 CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */
826 octeon_hal_setup_reserved32();
827}
828
829static struct octeon_cf_data octeon_cf_data;
830
831static int __init octeon_cf_device_init(void)
832{
833 union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg;
834 unsigned long base_ptr, region_base, region_size;
835 struct platform_device *pd;
836 struct resource cf_resources[3];
837 unsigned int num_resources;
838 int i;
839 int ret = 0;
840
841 /* Setup octeon-cf platform device if present. */
842 base_ptr = 0;
843 if (octeon_bootinfo->major_version == 1
844 && octeon_bootinfo->minor_version >= 1) {
845 if (octeon_bootinfo->compact_flash_common_base_addr)
846 base_ptr =
847 octeon_bootinfo->compact_flash_common_base_addr;
848 } else {
849 base_ptr = 0x1d000800;
850 }
851
852 if (!base_ptr)
853 return ret;
854
855 /* Find CS0 region. */
856 for (i = 0; i < 8; i++) {
857 mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i));
858 region_base = mio_boot_reg_cfg.s.base << 16;
859 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
860 if (mio_boot_reg_cfg.s.en && base_ptr >= region_base
861 && base_ptr < region_base + region_size)
862 break;
863 }
864 if (i >= 7) {
865 /* i and i + 1 are CS0 and CS1, both must be less than 8. */
866 goto out;
867 }
868 octeon_cf_data.base_region = i;
869 octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width;
870 octeon_cf_data.base_region_bias = base_ptr - region_base;
871 memset(cf_resources, 0, sizeof(cf_resources));
872 num_resources = 0;
873 cf_resources[num_resources].flags = IORESOURCE_MEM;
874 cf_resources[num_resources].start = region_base;
875 cf_resources[num_resources].end = region_base + region_size - 1;
876 num_resources++;
877
878
879 if (!(base_ptr & 0xfffful)) {
880 /*
881 * Boot loader signals availability of DMA (true_ide
882 * mode) by setting low order bits of base_ptr to
883 * zero.
884 */
885
886 /* Asume that CS1 immediately follows. */
887 mio_boot_reg_cfg.u64 =
888 cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1));
889 region_base = mio_boot_reg_cfg.s.base << 16;
890 region_size = (mio_boot_reg_cfg.s.size + 1) << 16;
891 if (!mio_boot_reg_cfg.s.en)
892 goto out;
893
894 cf_resources[num_resources].flags = IORESOURCE_MEM;
895 cf_resources[num_resources].start = region_base;
896 cf_resources[num_resources].end = region_base + region_size - 1;
897 num_resources++;
898
899 octeon_cf_data.dma_engine = 0;
900 cf_resources[num_resources].flags = IORESOURCE_IRQ;
901 cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA;
902 cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA;
903 num_resources++;
904 } else {
905 octeon_cf_data.dma_engine = -1;
906 }
907
908 pd = platform_device_alloc("pata_octeon_cf", -1);
909 if (!pd) {
910 ret = -ENOMEM;
911 goto out;
912 }
913 pd->dev.platform_data = &octeon_cf_data;
914
915 ret = platform_device_add_resources(pd, cf_resources, num_resources);
916 if (ret)
917 goto fail;
918
919 ret = platform_device_add(pd);
920 if (ret)
921 goto fail;
922
923 return ret;
924fail:
925 platform_device_put(pd);
926out:
927 return ret;
928}
929device_initcall(octeon_cf_device_init);
diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c
new file mode 100644
index 000000000000..24e0ad63980a
--- /dev/null
+++ b/arch/mips/cavium-octeon/smp.c
@@ -0,0 +1,211 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2008 Cavium Networks
7 */
8#include <linux/init.h>
9#include <linux/delay.h>
10#include <linux/smp.h>
11#include <linux/interrupt.h>
12#include <linux/kernel_stat.h>
13#include <linux/sched.h>
14#include <linux/module.h>
15
16#include <asm/mmu_context.h>
17#include <asm/system.h>
18#include <asm/time.h>
19
20#include <asm/octeon/octeon.h>
21
22volatile unsigned long octeon_processor_boot = 0xff;
23volatile unsigned long octeon_processor_sp;
24volatile unsigned long octeon_processor_gp;
25
26static irqreturn_t mailbox_interrupt(int irq, void *dev_id)
27{
28 const int coreid = cvmx_get_core_num();
29 uint64_t action;
30
31 /* Load the mailbox register to figure out what we're supposed to do */
32 action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid));
33
34 /* Clear the mailbox to clear the interrupt */
35 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action);
36
37 if (action & SMP_CALL_FUNCTION)
38 smp_call_function_interrupt();
39
40 /* Check if we've been told to flush the icache */
41 if (action & SMP_ICACHE_FLUSH)
42 asm volatile ("synci 0($0)\n");
43 return IRQ_HANDLED;
44}
45
46/**
47 * Cause the function described by call_data to be executed on the passed
48 * cpu. When the function has finished, increment the finished field of
49 * call_data.
50 */
51void octeon_send_ipi_single(int cpu, unsigned int action)
52{
53 int coreid = cpu_logical_map(cpu);
54 /*
55 pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu,
56 coreid, action);
57 */
58 cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action);
59}
60
61static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action)
62{
63 unsigned int i;
64
65 for_each_cpu_mask(i, mask)
66 octeon_send_ipi_single(i, action);
67}
68
69/**
70 * Detect available CPUs, populate phys_cpu_present_map
71 */
72static void octeon_smp_setup(void)
73{
74 const int coreid = cvmx_get_core_num();
75 int cpus;
76 int id;
77
78 int core_mask = octeon_get_boot_coremask();
79
80 cpus_clear(cpu_possible_map);
81 __cpu_number_map[coreid] = 0;
82 __cpu_logical_map[0] = coreid;
83 cpu_set(0, cpu_possible_map);
84
85 cpus = 1;
86 for (id = 0; id < 16; id++) {
87 if ((id != coreid) && (core_mask & (1 << id))) {
88 cpu_set(cpus, cpu_possible_map);
89 __cpu_number_map[id] = cpus;
90 __cpu_logical_map[cpus] = id;
91 cpus++;
92 }
93 }
94}
95
96/**
97 * Firmware CPU startup hook
98 *
99 */
100static void octeon_boot_secondary(int cpu, struct task_struct *idle)
101{
102 int count;
103
104 pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu,
105 cpu_logical_map(cpu));
106
107 octeon_processor_sp = __KSTK_TOS(idle);
108 octeon_processor_gp = (unsigned long)(task_thread_info(idle));
109 octeon_processor_boot = cpu_logical_map(cpu);
110 mb();
111
112 count = 10000;
113 while (octeon_processor_sp && count) {
114 /* Waiting for processor to get the SP and GP */
115 udelay(1);
116 count--;
117 }
118 if (count == 0)
119 pr_err("Secondary boot timeout\n");
120}
121
122/**
123 * After we've done initial boot, this function is called to allow the
124 * board code to clean up state, if needed
125 */
126static void octeon_init_secondary(void)
127{
128 const int coreid = cvmx_get_core_num();
129 union cvmx_ciu_intx_sum0 interrupt_enable;
130
131 octeon_check_cpu_bist();
132 octeon_init_cvmcount();
133 /*
134 pr_info("SMP: CPU%d (CoreId %lu) started\n", cpu, coreid);
135 */
136 /* Enable Mailbox interrupts to this core. These are the only
137 interrupts allowed on line 3 */
138 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), 0xffffffff);
139 interrupt_enable.u64 = 0;
140 interrupt_enable.s.mbox = 0x3;
141 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), interrupt_enable.u64);
142 cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0);
143 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0);
144 cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0);
145 /* Enable core interrupt processing for 2,3 and 7 */
146 set_c0_status(0x8c01);
147}
148
149/**
150 * Callout to firmware before smp_init
151 *
152 */
153void octeon_prepare_cpus(unsigned int max_cpus)
154{
155 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff);
156 if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_SHARED,
157 "mailbox0", mailbox_interrupt)) {
158 panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n");
159 }
160 if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_SHARED,
161 "mailbox1", mailbox_interrupt)) {
162 panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n");
163 }
164}
165
166/**
167 * Last chance for the board code to finish SMP initialization before
168 * the CPU is "online".
169 */
170static void octeon_smp_finish(void)
171{
172#ifdef CONFIG_CAVIUM_GDB
173 unsigned long tmp;
174 /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
175 to be not masked by this core so we know the signal is received by
176 someone */
177 asm volatile ("dmfc0 %0, $22\n"
178 "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
179#endif
180
181 octeon_user_io_init();
182
183 /* to generate the first CPU timer interrupt */
184 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
185}
186
187/**
188 * Hook for after all CPUs are online
189 */
190static void octeon_cpus_done(void)
191{
192#ifdef CONFIG_CAVIUM_GDB
193 unsigned long tmp;
194 /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0
195 to be not masked by this core so we know the signal is received by
196 someone */
197 asm volatile ("dmfc0 %0, $22\n"
198 "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp));
199#endif
200}
201
202struct plat_smp_ops octeon_smp_ops = {
203 .send_ipi_single = octeon_send_ipi_single,
204 .send_ipi_mask = octeon_send_ipi_mask,
205 .init_secondary = octeon_init_secondary,
206 .smp_finish = octeon_smp_finish,
207 .cpus_done = octeon_cpus_done,
208 .boot_secondary = octeon_boot_secondary,
209 .smp_setup = octeon_smp_setup,
210 .prepare_cpus = octeon_prepare_cpus,
211};
diff --git a/arch/mips/configs/cavium-octeon_defconfig b/arch/mips/configs/cavium-octeon_defconfig
new file mode 100644
index 000000000000..7afaa28a3768
--- /dev/null
+++ b/arch/mips/configs/cavium-octeon_defconfig
@@ -0,0 +1,943 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.28-rc6
4# Wed Dec 3 11:00:58 2008
5#
6CONFIG_MIPS=y
7
8#
9# Machine selection
10#
11# CONFIG_MACH_ALCHEMY is not set
12# CONFIG_BASLER_EXCITE is not set
13# CONFIG_BCM47XX is not set
14# CONFIG_MIPS_COBALT is not set
15# CONFIG_MACH_DECSTATION is not set
16# CONFIG_MACH_JAZZ is not set
17# CONFIG_LASAT is not set
18# CONFIG_LEMOTE_FULONG is not set
19# CONFIG_MIPS_MALTA is not set
20# CONFIG_MIPS_SIM is not set
21# CONFIG_MACH_EMMA is not set
22# CONFIG_MACH_VR41XX is not set
23# CONFIG_NXP_STB220 is not set
24# CONFIG_NXP_STB225 is not set
25# CONFIG_PNX8550_JBS is not set
26# CONFIG_PNX8550_STB810 is not set
27# CONFIG_PMC_MSP is not set
28# CONFIG_PMC_YOSEMITE is not set
29# CONFIG_SGI_IP22 is not set
30# CONFIG_SGI_IP27 is not set
31# CONFIG_SGI_IP28 is not set
32# CONFIG_SGI_IP32 is not set
33# CONFIG_SIBYTE_CRHINE is not set
34# CONFIG_SIBYTE_CARMEL is not set
35# CONFIG_SIBYTE_CRHONE is not set
36# CONFIG_SIBYTE_RHONE is not set
37# CONFIG_SIBYTE_SWARM is not set
38# CONFIG_SIBYTE_LITTLESUR is not set
39# CONFIG_SIBYTE_SENTOSA is not set
40# CONFIG_SIBYTE_BIGSUR is not set
41# CONFIG_SNI_RM is not set
42# CONFIG_MACH_TX39XX is not set
43# CONFIG_MACH_TX49XX is not set
44# CONFIG_MIKROTIK_RB532 is not set
45# CONFIG_WR_PPMC is not set
46# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
47CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y
48CONFIG_CAVIUM_OCTEON_SPECIFIC_OPTIONS=y
49# CONFIG_CAVIUM_OCTEON_2ND_KERNEL is not set
50CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED=y
51CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=2
52CONFIG_CAVIUM_OCTEON_LOCK_L2=y
53CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y
54CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y
55CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y
56CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y
57CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y
58CONFIG_ARCH_SPARSEMEM_ENABLE=y
59CONFIG_RWSEM_GENERIC_SPINLOCK=y
60# CONFIG_ARCH_HAS_ILOG2_U32 is not set
61# CONFIG_ARCH_HAS_ILOG2_U64 is not set
62CONFIG_ARCH_SUPPORTS_OPROFILE=y
63CONFIG_GENERIC_FIND_NEXT_BIT=y
64CONFIG_GENERIC_HWEIGHT=y
65CONFIG_GENERIC_CALIBRATE_DELAY=y
66CONFIG_GENERIC_CLOCKEVENTS=y
67CONFIG_GENERIC_TIME=y
68CONFIG_GENERIC_CMOS_UPDATE=y
69CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y
70# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set
71CONFIG_CEVT_R4K=y
72CONFIG_CSRC_R4K=y
73CONFIG_DMA_COHERENT=y
74# CONFIG_EARLY_PRINTK is not set
75CONFIG_SYS_HAS_EARLY_PRINTK=y
76# CONFIG_HOTPLUG_CPU is not set
77# CONFIG_NO_IOPORT is not set
78CONFIG_CPU_BIG_ENDIAN=y
79# CONFIG_CPU_LITTLE_ENDIAN is not set
80CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
81CONFIG_IRQ_CPU=y
82CONFIG_IRQ_CPU_OCTEON=y
83CONFIG_SWAP_IO_SPACE=y
84CONFIG_MIPS_L1_CACHE_SHIFT=7
85
86#
87# CPU selection
88#
89# CONFIG_CPU_LOONGSON2 is not set
90# CONFIG_CPU_MIPS32_R1 is not set
91# CONFIG_CPU_MIPS32_R2 is not set
92# CONFIG_CPU_MIPS64_R1 is not set
93# CONFIG_CPU_MIPS64_R2 is not set
94# CONFIG_CPU_R3000 is not set
95# CONFIG_CPU_TX39XX is not set
96# CONFIG_CPU_VR41XX is not set
97# CONFIG_CPU_R4300 is not set
98# CONFIG_CPU_R4X00 is not set
99# CONFIG_CPU_TX49XX is not set
100# CONFIG_CPU_R5000 is not set
101# CONFIG_CPU_R5432 is not set
102# CONFIG_CPU_R5500 is not set
103# CONFIG_CPU_R6000 is not set
104# CONFIG_CPU_NEVADA is not set
105# CONFIG_CPU_R8000 is not set
106# CONFIG_CPU_R10000 is not set
107# CONFIG_CPU_RM7000 is not set
108# CONFIG_CPU_RM9000 is not set
109# CONFIG_CPU_SB1 is not set
110CONFIG_CPU_CAVIUM_OCTEON=y
111CONFIG_WEAK_ORDERING=y
112CONFIG_WEAK_REORDERING_BEYOND_LLSC=y
113CONFIG_CPU_MIPSR2=y
114CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y
115CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y
116
117#
118# Kernel type
119#
120# CONFIG_32BIT is not set
121CONFIG_64BIT=y
122CONFIG_PAGE_SIZE_4KB=y
123# CONFIG_PAGE_SIZE_8KB is not set
124# CONFIG_PAGE_SIZE_16KB is not set
125# CONFIG_PAGE_SIZE_64KB is not set
126CONFIG_CPU_HAS_PREFETCH=y
127CONFIG_MIPS_MT_DISABLED=y
128# CONFIG_MIPS_MT_SMP is not set
129# CONFIG_MIPS_MT_SMTC is not set
130CONFIG_64BIT_PHYS_ADDR=y
131CONFIG_CPU_HAS_SYNC=y
132CONFIG_GENERIC_HARDIRQS=y
133CONFIG_GENERIC_IRQ_PROBE=y
134CONFIG_IRQ_PER_CPU=y
135CONFIG_CPU_SUPPORTS_HIGHMEM=y
136CONFIG_SYS_SUPPORTS_HIGHMEM=y
137CONFIG_ARCH_FLATMEM_ENABLE=y
138CONFIG_ARCH_POPULATES_NODE_MAP=y
139CONFIG_SELECT_MEMORY_MODEL=y
140# CONFIG_FLATMEM_MANUAL is not set
141# CONFIG_DISCONTIGMEM_MANUAL is not set
142CONFIG_SPARSEMEM_MANUAL=y
143CONFIG_SPARSEMEM=y
144CONFIG_HAVE_MEMORY_PRESENT=y
145CONFIG_SPARSEMEM_STATIC=y
146CONFIG_PAGEFLAGS_EXTENDED=y
147CONFIG_SPLIT_PTLOCK_CPUS=4
148CONFIG_RESOURCES_64BIT=y
149CONFIG_PHYS_ADDR_T_64BIT=y
150CONFIG_ZONE_DMA_FLAG=0
151CONFIG_VIRT_TO_BUS=y
152CONFIG_UNEVICTABLE_LRU=y
153CONFIG_SMP=y
154CONFIG_SYS_SUPPORTS_SMP=y
155CONFIG_NR_CPUS_DEFAULT_16=y
156CONFIG_NR_CPUS=16
157# CONFIG_NO_HZ is not set
158# CONFIG_HIGH_RES_TIMERS is not set
159CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
160# CONFIG_HZ_48 is not set
161# CONFIG_HZ_100 is not set
162# CONFIG_HZ_128 is not set
163CONFIG_HZ_250=y
164# CONFIG_HZ_256 is not set
165# CONFIG_HZ_1000 is not set
166# CONFIG_HZ_1024 is not set
167CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
168CONFIG_HZ=250
169# CONFIG_PREEMPT_NONE is not set
170# CONFIG_PREEMPT_VOLUNTARY is not set
171CONFIG_PREEMPT=y
172# CONFIG_PREEMPT_RCU is not set
173# CONFIG_KEXEC is not set
174CONFIG_SECCOMP=y
175CONFIG_LOCKDEP_SUPPORT=y
176CONFIG_STACKTRACE_SUPPORT=y
177CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
178
179#
180# General setup
181#
182CONFIG_EXPERIMENTAL=y
183CONFIG_LOCK_KERNEL=y
184CONFIG_INIT_ENV_ARG_LIMIT=32
185CONFIG_LOCALVERSION=""
186CONFIG_LOCALVERSION_AUTO=y
187CONFIG_SWAP=y
188CONFIG_SYSVIPC=y
189CONFIG_SYSVIPC_SYSCTL=y
190CONFIG_POSIX_MQUEUE=y
191CONFIG_BSD_PROCESS_ACCT=y
192CONFIG_BSD_PROCESS_ACCT_V3=y
193# CONFIG_TASKSTATS is not set
194# CONFIG_AUDIT is not set
195CONFIG_IKCONFIG=y
196CONFIG_IKCONFIG_PROC=y
197CONFIG_LOG_BUF_SHIFT=14
198# CONFIG_CGROUPS is not set
199CONFIG_GROUP_SCHED=y
200CONFIG_FAIR_GROUP_SCHED=y
201# CONFIG_RT_GROUP_SCHED is not set
202CONFIG_USER_SCHED=y
203# CONFIG_CGROUP_SCHED is not set
204CONFIG_SYSFS_DEPRECATED=y
205CONFIG_SYSFS_DEPRECATED_V2=y
206CONFIG_RELAY=y
207# CONFIG_NAMESPACES is not set
208CONFIG_BLK_DEV_INITRD=y
209CONFIG_INITRAMFS_SOURCE=""
210# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
211CONFIG_SYSCTL=y
212CONFIG_EMBEDDED=y
213CONFIG_SYSCTL_SYSCALL=y
214CONFIG_KALLSYMS=y
215# CONFIG_KALLSYMS_ALL is not set
216# CONFIG_KALLSYMS_EXTRA_PASS is not set
217CONFIG_HOTPLUG=y
218CONFIG_PRINTK=y
219CONFIG_BUG=y
220CONFIG_ELF_CORE=y
221# CONFIG_PCSPKR_PLATFORM is not set
222CONFIG_COMPAT_BRK=y
223CONFIG_BASE_FULL=y
224CONFIG_FUTEX=y
225CONFIG_ANON_INODES=y
226CONFIG_EPOLL=y
227CONFIG_SIGNALFD=y
228CONFIG_TIMERFD=y
229CONFIG_EVENTFD=y
230CONFIG_SHMEM=y
231CONFIG_AIO=y
232CONFIG_VM_EVENT_COUNTERS=y
233CONFIG_SLAB=y
234# CONFIG_SLUB is not set
235# CONFIG_SLOB is not set
236# CONFIG_PROFILING is not set
237# CONFIG_MARKERS is not set
238CONFIG_HAVE_OPROFILE=y
239CONFIG_USE_GENERIC_SMP_HELPERS=y
240# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
241CONFIG_SLABINFO=y
242CONFIG_RT_MUTEXES=y
243# CONFIG_TINY_SHMEM is not set
244CONFIG_BASE_SMALL=0
245CONFIG_MODULES=y
246# CONFIG_MODULE_FORCE_LOAD is not set
247CONFIG_MODULE_UNLOAD=y
248# CONFIG_MODULE_FORCE_UNLOAD is not set
249# CONFIG_MODVERSIONS is not set
250# CONFIG_MODULE_SRCVERSION_ALL is not set
251CONFIG_KMOD=y
252CONFIG_STOP_MACHINE=y
253CONFIG_BLOCK=y
254# CONFIG_BLK_DEV_IO_TRACE is not set
255# CONFIG_BLK_DEV_BSG is not set
256# CONFIG_BLK_DEV_INTEGRITY is not set
257CONFIG_BLOCK_COMPAT=y
258
259#
260# IO Schedulers
261#
262CONFIG_IOSCHED_NOOP=y
263CONFIG_IOSCHED_AS=y
264CONFIG_IOSCHED_DEADLINE=y
265CONFIG_IOSCHED_CFQ=y
266# CONFIG_DEFAULT_AS is not set
267# CONFIG_DEFAULT_DEADLINE is not set
268CONFIG_DEFAULT_CFQ=y
269# CONFIG_DEFAULT_NOOP is not set
270CONFIG_DEFAULT_IOSCHED="cfq"
271CONFIG_CLASSIC_RCU=y
272# CONFIG_PROBE_INITRD_HEADER is not set
273# CONFIG_FREEZER is not set
274
275#
276# Bus options (PCI, PCMCIA, EISA, ISA, TC)
277#
278# CONFIG_ARCH_SUPPORTS_MSI is not set
279CONFIG_MMU=y
280# CONFIG_PCCARD is not set
281
282#
283# Executable file formats
284#
285CONFIG_BINFMT_ELF=y
286# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
287# CONFIG_HAVE_AOUT is not set
288# CONFIG_BINFMT_MISC is not set
289CONFIG_MIPS32_COMPAT=y
290CONFIG_COMPAT=y
291CONFIG_SYSVIPC_COMPAT=y
292CONFIG_MIPS32_O32=y
293CONFIG_MIPS32_N32=y
294CONFIG_BINFMT_ELF32=y
295
296#
297# Power management options
298#
299# CONFIG_PM is not set
300CONFIG_NET=y
301
302#
303# Networking options
304#
305CONFIG_PACKET=y
306CONFIG_PACKET_MMAP=y
307CONFIG_UNIX=y
308CONFIG_XFRM=y
309# CONFIG_XFRM_USER is not set
310# CONFIG_XFRM_SUB_POLICY is not set
311# CONFIG_XFRM_MIGRATE is not set
312# CONFIG_XFRM_STATISTICS is not set
313# CONFIG_NET_KEY is not set
314CONFIG_INET=y
315CONFIG_IP_MULTICAST=y
316CONFIG_IP_ADVANCED_ROUTER=y
317CONFIG_ASK_IP_FIB_HASH=y
318# CONFIG_IP_FIB_TRIE is not set
319CONFIG_IP_FIB_HASH=y
320CONFIG_IP_MULTIPLE_TABLES=y
321CONFIG_IP_ROUTE_MULTIPATH=y
322CONFIG_IP_ROUTE_VERBOSE=y
323CONFIG_IP_PNP=y
324CONFIG_IP_PNP_DHCP=y
325CONFIG_IP_PNP_BOOTP=y
326CONFIG_IP_PNP_RARP=y
327# CONFIG_NET_IPIP is not set
328# CONFIG_NET_IPGRE is not set
329CONFIG_IP_MROUTE=y
330CONFIG_IP_PIMSM_V1=y
331CONFIG_IP_PIMSM_V2=y
332# CONFIG_ARPD is not set
333CONFIG_SYN_COOKIES=y
334# CONFIG_INET_AH is not set
335# CONFIG_INET_ESP is not set
336# CONFIG_INET_IPCOMP is not set
337# CONFIG_INET_XFRM_TUNNEL is not set
338# CONFIG_INET_TUNNEL is not set
339CONFIG_INET_XFRM_MODE_TRANSPORT=y
340CONFIG_INET_XFRM_MODE_TUNNEL=y
341CONFIG_INET_XFRM_MODE_BEET=y
342# CONFIG_INET_LRO is not set
343CONFIG_INET_DIAG=y
344CONFIG_INET_TCP_DIAG=y
345# CONFIG_TCP_CONG_ADVANCED is not set
346CONFIG_TCP_CONG_CUBIC=y
347CONFIG_DEFAULT_TCP_CONG="cubic"
348# CONFIG_TCP_MD5SIG is not set
349# CONFIG_IPV6 is not set
350# CONFIG_NETLABEL is not set
351# CONFIG_NETWORK_SECMARK is not set
352# CONFIG_NETFILTER is not set
353# CONFIG_IP_DCCP is not set
354# CONFIG_IP_SCTP is not set
355# CONFIG_TIPC is not set
356# CONFIG_ATM is not set
357# CONFIG_BRIDGE is not set
358# CONFIG_NET_DSA is not set
359# CONFIG_VLAN_8021Q is not set
360# CONFIG_DECNET is not set
361# CONFIG_LLC2 is not set
362# CONFIG_IPX is not set
363# CONFIG_ATALK is not set
364# CONFIG_X25 is not set
365# CONFIG_LAPB is not set
366# CONFIG_ECONET is not set
367# CONFIG_WAN_ROUTER is not set
368# CONFIG_NET_SCHED is not set
369
370#
371# Network testing
372#
373# CONFIG_NET_PKTGEN is not set
374# CONFIG_HAMRADIO is not set
375# CONFIG_CAN is not set
376# CONFIG_IRDA is not set
377# CONFIG_BT is not set
378# CONFIG_AF_RXRPC is not set
379# CONFIG_PHONET is not set
380CONFIG_FIB_RULES=y
381# CONFIG_WIRELESS is not set
382# CONFIG_RFKILL is not set
383# CONFIG_NET_9P is not set
384
385#
386# Device Drivers
387#
388
389#
390# Generic Driver Options
391#
392CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
393CONFIG_STANDALONE=y
394CONFIG_PREVENT_FIRMWARE_BUILD=y
395# CONFIG_FW_LOADER is not set
396# CONFIG_DEBUG_DRIVER is not set
397# CONFIG_DEBUG_DEVRES is not set
398# CONFIG_SYS_HYPERVISOR is not set
399# CONFIG_CONNECTOR is not set
400CONFIG_MTD=y
401# CONFIG_MTD_DEBUG is not set
402# CONFIG_MTD_CONCAT is not set
403CONFIG_MTD_PARTITIONS=y
404# CONFIG_MTD_REDBOOT_PARTS is not set
405# CONFIG_MTD_CMDLINE_PARTS is not set
406# CONFIG_MTD_AR7_PARTS is not set
407
408#
409# User Modules And Translation Layers
410#
411CONFIG_MTD_CHAR=y
412CONFIG_MTD_BLKDEVS=y
413CONFIG_MTD_BLOCK=y
414# CONFIG_FTL is not set
415# CONFIG_NFTL is not set
416# CONFIG_INFTL is not set
417# CONFIG_RFD_FTL is not set
418# CONFIG_SSFDC is not set
419# CONFIG_MTD_OOPS is not set
420
421#
422# RAM/ROM/Flash chip drivers
423#
424CONFIG_MTD_CFI=y
425# CONFIG_MTD_JEDECPROBE is not set
426CONFIG_MTD_GEN_PROBE=y
427# CONFIG_MTD_CFI_ADV_OPTIONS is not set
428CONFIG_MTD_MAP_BANK_WIDTH_1=y
429CONFIG_MTD_MAP_BANK_WIDTH_2=y
430CONFIG_MTD_MAP_BANK_WIDTH_4=y
431# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
432# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
433# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
434CONFIG_MTD_CFI_I1=y
435CONFIG_MTD_CFI_I2=y
436# CONFIG_MTD_CFI_I4 is not set
437# CONFIG_MTD_CFI_I8 is not set
438# CONFIG_MTD_CFI_INTELEXT is not set
439CONFIG_MTD_CFI_AMDSTD=y
440# CONFIG_MTD_CFI_STAA is not set
441CONFIG_MTD_CFI_UTIL=y
442# CONFIG_MTD_RAM is not set
443# CONFIG_MTD_ROM is not set
444# CONFIG_MTD_ABSENT is not set
445
446#
447# Mapping drivers for chip access
448#
449# CONFIG_MTD_COMPLEX_MAPPINGS is not set
450CONFIG_MTD_PHYSMAP=y
451CONFIG_MTD_PHYSMAP_START=0x8000000
452CONFIG_MTD_PHYSMAP_LEN=0x0
453CONFIG_MTD_PHYSMAP_BANKWIDTH=2
454# CONFIG_MTD_PLATRAM is not set
455
456#
457# Self-contained MTD device drivers
458#
459# CONFIG_MTD_SLRAM is not set
460# CONFIG_MTD_PHRAM is not set
461# CONFIG_MTD_MTDRAM is not set
462# CONFIG_MTD_BLOCK2MTD is not set
463
464#
465# Disk-On-Chip Device Drivers
466#
467# CONFIG_MTD_DOC2000 is not set
468# CONFIG_MTD_DOC2001 is not set
469# CONFIG_MTD_DOC2001PLUS is not set
470# CONFIG_MTD_NAND is not set
471# CONFIG_MTD_ONENAND is not set
472
473#
474# UBI - Unsorted block images
475#
476# CONFIG_MTD_UBI is not set
477# CONFIG_PARPORT is not set
478CONFIG_BLK_DEV=y
479# CONFIG_BLK_DEV_COW_COMMON is not set
480CONFIG_BLK_DEV_LOOP=y
481# CONFIG_BLK_DEV_CRYPTOLOOP is not set
482# CONFIG_BLK_DEV_NBD is not set
483# CONFIG_BLK_DEV_RAM is not set
484# CONFIG_CDROM_PKTCDVD is not set
485# CONFIG_ATA_OVER_ETH is not set
486# CONFIG_BLK_DEV_HD is not set
487# CONFIG_MISC_DEVICES is not set
488CONFIG_HAVE_IDE=y
489# CONFIG_IDE is not set
490
491#
492# SCSI device support
493#
494# CONFIG_RAID_ATTRS is not set
495# CONFIG_SCSI is not set
496# CONFIG_SCSI_DMA is not set
497# CONFIG_SCSI_NETLINK is not set
498# CONFIG_ATA is not set
499# CONFIG_MD is not set
500CONFIG_NETDEVICES=y
501# CONFIG_DUMMY is not set
502# CONFIG_BONDING is not set
503# CONFIG_MACVLAN is not set
504# CONFIG_EQUALIZER is not set
505# CONFIG_TUN is not set
506# CONFIG_VETH is not set
507# CONFIG_PHYLIB is not set
508CONFIG_NET_ETHERNET=y
509CONFIG_MII=y
510# CONFIG_AX88796 is not set
511# CONFIG_SMC91X is not set
512# CONFIG_DM9000 is not set
513# CONFIG_IBM_NEW_EMAC_ZMII is not set
514# CONFIG_IBM_NEW_EMAC_RGMII is not set
515# CONFIG_IBM_NEW_EMAC_TAH is not set
516# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
517# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
518# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
519# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
520# CONFIG_B44 is not set
521CONFIG_NETDEV_1000=y
522# CONFIG_NETDEV_10000 is not set
523
524#
525# Wireless LAN
526#
527# CONFIG_WLAN_PRE80211 is not set
528# CONFIG_WLAN_80211 is not set
529# CONFIG_IWLWIFI_LEDS is not set
530# CONFIG_WAN is not set
531# CONFIG_PPP is not set
532# CONFIG_SLIP is not set
533# CONFIG_NETCONSOLE is not set
534# CONFIG_NETPOLL is not set
535# CONFIG_NET_POLL_CONTROLLER is not set
536# CONFIG_ISDN is not set
537# CONFIG_PHONE is not set
538
539#
540# Input device support
541#
542# CONFIG_INPUT is not set
543
544#
545# Hardware I/O ports
546#
547# CONFIG_SERIO is not set
548# CONFIG_GAMEPORT is not set
549
550#
551# Character devices
552#
553# CONFIG_VT is not set
554CONFIG_DEVKMEM=y
555# CONFIG_SERIAL_NONSTANDARD is not set
556
557#
558# Serial drivers
559#
560CONFIG_SERIAL_8250=y
561CONFIG_SERIAL_8250_CONSOLE=y
562CONFIG_SERIAL_8250_NR_UARTS=2
563CONFIG_SERIAL_8250_RUNTIME_UARTS=2
564# CONFIG_SERIAL_8250_EXTENDED is not set
565
566#
567# Non-8250 serial port support
568#
569CONFIG_SERIAL_CORE=y
570CONFIG_SERIAL_CORE_CONSOLE=y
571CONFIG_UNIX98_PTYS=y
572CONFIG_LEGACY_PTYS=y
573CONFIG_LEGACY_PTY_COUNT=256
574# CONFIG_IPMI_HANDLER is not set
575# CONFIG_HW_RANDOM is not set
576# CONFIG_R3964 is not set
577# CONFIG_RAW_DRIVER is not set
578# CONFIG_TCG_TPM is not set
579# CONFIG_I2C is not set
580# CONFIG_SPI is not set
581# CONFIG_W1 is not set
582# CONFIG_POWER_SUPPLY is not set
583# CONFIG_HWMON is not set
584# CONFIG_THERMAL is not set
585# CONFIG_THERMAL_HWMON is not set
586CONFIG_WATCHDOG=y
587# CONFIG_WATCHDOG_NOWAYOUT is not set
588
589#
590# Watchdog Device Drivers
591#
592# CONFIG_SOFT_WATCHDOG is not set
593CONFIG_SSB_POSSIBLE=y
594
595#
596# Sonics Silicon Backplane
597#
598# CONFIG_SSB is not set
599
600#
601# Multifunction device drivers
602#
603# CONFIG_MFD_CORE is not set
604# CONFIG_MFD_SM501 is not set
605# CONFIG_HTC_PASIC3 is not set
606# CONFIG_MFD_TMIO is not set
607# CONFIG_REGULATOR is not set
608
609#
610# Multimedia devices
611#
612
613#
614# Multimedia core support
615#
616# CONFIG_VIDEO_DEV is not set
617# CONFIG_DVB_CORE is not set
618# CONFIG_VIDEO_MEDIA is not set
619
620#
621# Multimedia drivers
622#
623# CONFIG_DAB is not set
624
625#
626# Graphics support
627#
628# CONFIG_VGASTATE is not set
629# CONFIG_VIDEO_OUTPUT_CONTROL is not set
630# CONFIG_FB is not set
631# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
632
633#
634# Display device support
635#
636# CONFIG_DISPLAY_SUPPORT is not set
637# CONFIG_SOUND is not set
638# CONFIG_USB_SUPPORT is not set
639# CONFIG_MMC is not set
640# CONFIG_MEMSTICK is not set
641# CONFIG_NEW_LEDS is not set
642# CONFIG_ACCESSIBILITY is not set
643CONFIG_RTC_LIB=y
644# CONFIG_RTC_CLASS is not set
645# CONFIG_DMADEVICES is not set
646# CONFIG_UIO is not set
647# CONFIG_STAGING is not set
648CONFIG_STAGING_EXCLUDE_BUILD=y
649
650#
651# File systems
652#
653# CONFIG_EXT2_FS is not set
654# CONFIG_EXT3_FS is not set
655# CONFIG_EXT4_FS is not set
656# CONFIG_REISERFS_FS is not set
657# CONFIG_JFS_FS is not set
658# CONFIG_FS_POSIX_ACL is not set
659CONFIG_FILE_LOCKING=y
660# CONFIG_XFS_FS is not set
661# CONFIG_GFS2_FS is not set
662# CONFIG_OCFS2_FS is not set
663CONFIG_DNOTIFY=y
664CONFIG_INOTIFY=y
665CONFIG_INOTIFY_USER=y
666# CONFIG_QUOTA is not set
667# CONFIG_AUTOFS_FS is not set
668# CONFIG_AUTOFS4_FS is not set
669# CONFIG_FUSE_FS is not set
670
671#
672# CD-ROM/DVD Filesystems
673#
674# CONFIG_ISO9660_FS is not set
675# CONFIG_UDF_FS is not set
676
677#
678# DOS/FAT/NT Filesystems
679#
680# CONFIG_MSDOS_FS is not set
681# CONFIG_VFAT_FS is not set
682# CONFIG_NTFS_FS is not set
683
684#
685# Pseudo filesystems
686#
687CONFIG_PROC_FS=y
688CONFIG_PROC_KCORE=y
689CONFIG_PROC_SYSCTL=y
690CONFIG_PROC_PAGE_MONITOR=y
691CONFIG_SYSFS=y
692CONFIG_TMPFS=y
693# CONFIG_TMPFS_POSIX_ACL is not set
694# CONFIG_HUGETLB_PAGE is not set
695# CONFIG_CONFIGFS_FS is not set
696
697#
698# Miscellaneous filesystems
699#
700# CONFIG_ADFS_FS is not set
701# CONFIG_AFFS_FS is not set
702# CONFIG_HFS_FS is not set
703# CONFIG_HFSPLUS_FS is not set
704# CONFIG_BEFS_FS is not set
705# CONFIG_BFS_FS is not set
706# CONFIG_EFS_FS is not set
707# CONFIG_JFFS2_FS is not set
708# CONFIG_CRAMFS is not set
709# CONFIG_VXFS_FS is not set
710# CONFIG_MINIX_FS is not set
711# CONFIG_OMFS_FS is not set
712# CONFIG_HPFS_FS is not set
713# CONFIG_QNX4FS_FS is not set
714# CONFIG_ROMFS_FS is not set
715# CONFIG_SYSV_FS is not set
716# CONFIG_UFS_FS is not set
717# CONFIG_NETWORK_FILESYSTEMS is not set
718
719#
720# Partition Types
721#
722# CONFIG_PARTITION_ADVANCED is not set
723CONFIG_MSDOS_PARTITION=y
724CONFIG_NLS=y
725CONFIG_NLS_DEFAULT="iso8859-1"
726CONFIG_NLS_CODEPAGE_437=y
727# CONFIG_NLS_CODEPAGE_737 is not set
728# CONFIG_NLS_CODEPAGE_775 is not set
729# CONFIG_NLS_CODEPAGE_850 is not set
730# CONFIG_NLS_CODEPAGE_852 is not set
731# CONFIG_NLS_CODEPAGE_855 is not set
732# CONFIG_NLS_CODEPAGE_857 is not set
733# CONFIG_NLS_CODEPAGE_860 is not set
734# CONFIG_NLS_CODEPAGE_861 is not set
735# CONFIG_NLS_CODEPAGE_862 is not set
736# CONFIG_NLS_CODEPAGE_863 is not set
737# CONFIG_NLS_CODEPAGE_864 is not set
738# CONFIG_NLS_CODEPAGE_865 is not set
739# CONFIG_NLS_CODEPAGE_866 is not set
740# CONFIG_NLS_CODEPAGE_869 is not set
741# CONFIG_NLS_CODEPAGE_936 is not set
742# CONFIG_NLS_CODEPAGE_950 is not set
743# CONFIG_NLS_CODEPAGE_932 is not set
744# CONFIG_NLS_CODEPAGE_949 is not set
745# CONFIG_NLS_CODEPAGE_874 is not set
746# CONFIG_NLS_ISO8859_8 is not set
747# CONFIG_NLS_CODEPAGE_1250 is not set
748# CONFIG_NLS_CODEPAGE_1251 is not set
749# CONFIG_NLS_ASCII is not set
750CONFIG_NLS_ISO8859_1=y
751# CONFIG_NLS_ISO8859_2 is not set
752# CONFIG_NLS_ISO8859_3 is not set
753# CONFIG_NLS_ISO8859_4 is not set
754# CONFIG_NLS_ISO8859_5 is not set
755# CONFIG_NLS_ISO8859_6 is not set
756# CONFIG_NLS_ISO8859_7 is not set
757# CONFIG_NLS_ISO8859_9 is not set
758# CONFIG_NLS_ISO8859_13 is not set
759# CONFIG_NLS_ISO8859_14 is not set
760# CONFIG_NLS_ISO8859_15 is not set
761# CONFIG_NLS_KOI8_R is not set
762# CONFIG_NLS_KOI8_U is not set
763# CONFIG_NLS_UTF8 is not set
764# CONFIG_DLM is not set
765
766#
767# Kernel hacking
768#
769CONFIG_TRACE_IRQFLAGS_SUPPORT=y
770# CONFIG_PRINTK_TIME is not set
771CONFIG_ENABLE_WARN_DEPRECATED=y
772CONFIG_ENABLE_MUST_CHECK=y
773CONFIG_FRAME_WARN=2048
774CONFIG_MAGIC_SYSRQ=y
775# CONFIG_UNUSED_SYMBOLS is not set
776CONFIG_DEBUG_FS=y
777# CONFIG_HEADERS_CHECK is not set
778CONFIG_DEBUG_KERNEL=y
779# CONFIG_DEBUG_SHIRQ is not set
780CONFIG_DETECT_SOFTLOCKUP=y
781# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
782CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
783CONFIG_SCHED_DEBUG=y
784# CONFIG_SCHEDSTATS is not set
785# CONFIG_TIMER_STATS is not set
786# CONFIG_DEBUG_OBJECTS is not set
787# CONFIG_DEBUG_SLAB is not set
788CONFIG_DEBUG_PREEMPT=y
789# CONFIG_DEBUG_RT_MUTEXES is not set
790# CONFIG_RT_MUTEX_TESTER is not set
791CONFIG_DEBUG_SPINLOCK=y
792# CONFIG_DEBUG_MUTEXES is not set
793# CONFIG_DEBUG_LOCK_ALLOC is not set
794# CONFIG_PROVE_LOCKING is not set
795# CONFIG_LOCK_STAT is not set
796CONFIG_DEBUG_SPINLOCK_SLEEP=y
797# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
798# CONFIG_DEBUG_KOBJECT is not set
799CONFIG_DEBUG_INFO=y
800# CONFIG_DEBUG_VM is not set
801# CONFIG_DEBUG_WRITECOUNT is not set
802# CONFIG_DEBUG_MEMORY_INIT is not set
803# CONFIG_DEBUG_LIST is not set
804# CONFIG_DEBUG_SG is not set
805# CONFIG_BOOT_PRINTK_DELAY is not set
806# CONFIG_RCU_TORTURE_TEST is not set
807# CONFIG_RCU_CPU_STALL_DETECTOR is not set
808# CONFIG_BACKTRACE_SELF_TEST is not set
809# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
810# CONFIG_FAULT_INJECTION is not set
811CONFIG_SYSCTL_SYSCALL_CHECK=y
812
813#
814# Tracers
815#
816# CONFIG_IRQSOFF_TRACER is not set
817# CONFIG_PREEMPT_TRACER is not set
818# CONFIG_SCHED_TRACER is not set
819# CONFIG_CONTEXT_SWITCH_TRACER is not set
820# CONFIG_BOOT_TRACER is not set
821# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
822# CONFIG_SAMPLES is not set
823CONFIG_HAVE_ARCH_KGDB=y
824# CONFIG_KGDB is not set
825CONFIG_CMDLINE=""
826# CONFIG_DEBUG_STACK_USAGE is not set
827# CONFIG_RUNTIME_DEBUG is not set
828
829#
830# Security options
831#
832# CONFIG_KEYS is not set
833CONFIG_SECURITY=y
834# CONFIG_SECURITYFS is not set
835CONFIG_SECURITY_NETWORK=y
836# CONFIG_SECURITY_NETWORK_XFRM is not set
837# CONFIG_SECURITY_FILE_CAPABILITIES is not set
838CONFIG_SECURITY_DEFAULT_MMAP_MIN_ADDR=0
839CONFIG_CRYPTO=y
840
841#
842# Crypto core or helper
843#
844# CONFIG_CRYPTO_FIPS is not set
845CONFIG_CRYPTO_ALGAPI=y
846CONFIG_CRYPTO_AEAD=y
847CONFIG_CRYPTO_BLKCIPHER=y
848CONFIG_CRYPTO_HASH=y
849CONFIG_CRYPTO_RNG=y
850CONFIG_CRYPTO_MANAGER=y
851# CONFIG_CRYPTO_GF128MUL is not set
852# CONFIG_CRYPTO_NULL is not set
853# CONFIG_CRYPTO_CRYPTD is not set
854# CONFIG_CRYPTO_AUTHENC is not set
855# CONFIG_CRYPTO_TEST is not set
856
857#
858# Authenticated Encryption with Associated Data
859#
860# CONFIG_CRYPTO_CCM is not set
861# CONFIG_CRYPTO_GCM is not set
862# CONFIG_CRYPTO_SEQIV is not set
863
864#
865# Block modes
866#
867CONFIG_CRYPTO_CBC=y
868# CONFIG_CRYPTO_CTR is not set
869# CONFIG_CRYPTO_CTS is not set
870# CONFIG_CRYPTO_ECB is not set
871# CONFIG_CRYPTO_LRW is not set
872# CONFIG_CRYPTO_PCBC is not set
873# CONFIG_CRYPTO_XTS is not set
874
875#
876# Hash modes
877#
878CONFIG_CRYPTO_HMAC=y
879# CONFIG_CRYPTO_XCBC is not set
880
881#
882# Digest
883#
884# CONFIG_CRYPTO_CRC32C is not set
885# CONFIG_CRYPTO_MD4 is not set
886CONFIG_CRYPTO_MD5=y
887# CONFIG_CRYPTO_MICHAEL_MIC is not set
888# CONFIG_CRYPTO_RMD128 is not set
889# CONFIG_CRYPTO_RMD160 is not set
890# CONFIG_CRYPTO_RMD256 is not set
891# CONFIG_CRYPTO_RMD320 is not set
892# CONFIG_CRYPTO_SHA1 is not set
893# CONFIG_CRYPTO_SHA256 is not set
894# CONFIG_CRYPTO_SHA512 is not set
895# CONFIG_CRYPTO_TGR192 is not set
896# CONFIG_CRYPTO_WP512 is not set
897
898#
899# Ciphers
900#
901# CONFIG_CRYPTO_AES is not set
902# CONFIG_CRYPTO_ANUBIS is not set
903# CONFIG_CRYPTO_ARC4 is not set
904# CONFIG_CRYPTO_BLOWFISH is not set
905# CONFIG_CRYPTO_CAMELLIA is not set
906# CONFIG_CRYPTO_CAST5 is not set
907# CONFIG_CRYPTO_CAST6 is not set
908CONFIG_CRYPTO_DES=y
909# CONFIG_CRYPTO_FCRYPT is not set
910# CONFIG_CRYPTO_KHAZAD is not set
911# CONFIG_CRYPTO_SALSA20 is not set
912# CONFIG_CRYPTO_SEED is not set
913# CONFIG_CRYPTO_SERPENT is not set
914# CONFIG_CRYPTO_TEA is not set
915# CONFIG_CRYPTO_TWOFISH is not set
916
917#
918# Compression
919#
920# CONFIG_CRYPTO_DEFLATE is not set
921# CONFIG_CRYPTO_LZO is not set
922
923#
924# Random Number Generation
925#
926# CONFIG_CRYPTO_ANSI_CPRNG is not set
927CONFIG_CRYPTO_HW=y
928
929#
930# Library routines
931#
932CONFIG_BITREVERSE=y
933# CONFIG_CRC_CCITT is not set
934# CONFIG_CRC16 is not set
935# CONFIG_CRC_T10DIF is not set
936# CONFIG_CRC_ITU_T is not set
937CONFIG_CRC32=y
938# CONFIG_CRC7 is not set
939# CONFIG_LIBCRC32C is not set
940CONFIG_PLIST=y
941CONFIG_HAS_IOMEM=y
942CONFIG_HAS_IOPORT=y
943CONFIG_HAS_DMA=y
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 12d12dfe73c0..a0d14f85b781 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -38,6 +38,9 @@
38#ifndef cpu_has_tx39_cache 38#ifndef cpu_has_tx39_cache
39#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE) 39#define cpu_has_tx39_cache (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
40#endif 40#endif
41#ifndef cpu_has_octeon_cache
42#define cpu_has_octeon_cache 0
43#endif
41#ifndef cpu_has_fpu 44#ifndef cpu_has_fpu
42#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 45#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
43#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 46#define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU)
diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h
index 229a786101d9..c018727c7ddc 100644
--- a/arch/mips/include/asm/cpu.h
+++ b/arch/mips/include/asm/cpu.h
@@ -33,6 +33,7 @@
33#define PRID_COMP_TOSHIBA 0x070000 33#define PRID_COMP_TOSHIBA 0x070000
34#define PRID_COMP_LSI 0x080000 34#define PRID_COMP_LSI 0x080000
35#define PRID_COMP_LEXRA 0x0b0000 35#define PRID_COMP_LEXRA 0x0b0000
36#define PRID_COMP_CAVIUM 0x0d0000
36 37
37 38
38/* 39/*
@@ -114,6 +115,18 @@
114#define PRID_IMP_BCM3302 0x9000 115#define PRID_IMP_BCM3302 0x9000
115 116
116/* 117/*
118 * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM
119 */
120
121#define PRID_IMP_CAVIUM_CN38XX 0x0000
122#define PRID_IMP_CAVIUM_CN31XX 0x0100
123#define PRID_IMP_CAVIUM_CN30XX 0x0200
124#define PRID_IMP_CAVIUM_CN58XX 0x0300
125#define PRID_IMP_CAVIUM_CN56XX 0x0400
126#define PRID_IMP_CAVIUM_CN50XX 0x0600
127#define PRID_IMP_CAVIUM_CN52XX 0x0700
128
129/*
117 * Definitions for 7:0 on legacy processors 130 * Definitions for 7:0 on legacy processors
118 */ 131 */
119 132
@@ -203,6 +216,7 @@ enum cpu_type_enum {
203 * MIPS64 class processors 216 * MIPS64 class processors
204 */ 217 */
205 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, 218 CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
219 CPU_CAVIUM_OCTEON,
206 220
207 CPU_LAST 221 CPU_LAST
208}; 222};
diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h
index 2de638f84c86..43baed16a109 100644
--- a/arch/mips/include/asm/hazards.h
+++ b/arch/mips/include/asm/hazards.h
@@ -42,7 +42,7 @@ ASMMACRO(_ehb,
42/* 42/*
43 * TLB hazards 43 * TLB hazards
44 */ 44 */
45#if defined(CONFIG_CPU_MIPSR2) 45#if defined(CONFIG_CPU_MIPSR2) && !defined(CONFIG_CPU_CAVIUM_OCTEON)
46 46
47/* 47/*
48 * MIPSR2 defines ehb for hazard avoidance 48 * MIPSR2 defines ehb for hazard avoidance
@@ -138,7 +138,7 @@ do { \
138 __instruction_hazard(); \ 138 __instruction_hazard(); \
139} while (0) 139} while (0)
140 140
141#elif defined(CONFIG_CPU_R10000) 141#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON)
142 142
143/* 143/*
144 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. 144 * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 501a40b9f18d..436878e4e063 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -295,6 +295,12 @@ static inline void iounmap(const volatile void __iomem *addr)
295#undef __IS_KSEG1 295#undef __IS_KSEG1
296} 296}
297 297
298#ifdef CONFIG_CPU_CAVIUM_OCTEON
299#define war_octeon_io_reorder_wmb() wmb()
300#else
301#define war_octeon_io_reorder_wmb() do { } while (0)
302#endif
303
298#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \ 304#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq) \
299 \ 305 \
300static inline void pfx##write##bwlq(type val, \ 306static inline void pfx##write##bwlq(type val, \
@@ -303,6 +309,8 @@ static inline void pfx##write##bwlq(type val, \
303 volatile type *__mem; \ 309 volatile type *__mem; \
304 type __val; \ 310 type __val; \
305 \ 311 \
312 war_octeon_io_reorder_wmb(); \
313 \
306 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \ 314 __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem)); \
307 \ 315 \
308 __val = pfx##ioswab##bwlq(__mem, val); \ 316 __val = pfx##ioswab##bwlq(__mem, val); \
@@ -370,6 +378,8 @@ static inline void pfx##out##bwlq##p(type val, unsigned long port) \
370 volatile type *__addr; \ 378 volatile type *__addr; \
371 type __val; \ 379 type __val; \
372 \ 380 \
381 war_octeon_io_reorder_wmb(); \
382 \
373 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \ 383 __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
374 \ 384 \
375 __val = pfx##ioswab##bwlq(__addr, val); \ 385 __val = pfx##ioswab##bwlq(__addr, val); \
@@ -504,8 +514,12 @@ BUILDSTRING(q, u64)
504#endif 514#endif
505 515
506 516
517#ifdef CONFIG_CPU_CAVIUM_OCTEON
518#define mmiowb() wmb()
519#else
507/* Depends on MIPS II instruction set */ 520/* Depends on MIPS II instruction set */
508#define mmiowb() asm volatile ("sync" ::: "memory") 521#define mmiowb() asm volatile ("sync" ::: "memory")
522#endif
509 523
510static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count) 524static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
511{ 525{
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index 0d302bad4492..62f91f50b5b5 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -91,14 +91,57 @@ static inline u32 au_readl(unsigned long reg)
91 return *(volatile u32 *)reg; 91 return *(volatile u32 *)reg;
92} 92}
93 93
94/* Early Au1000 have a write-only SYS_CPUPLL register. */
95static inline int au1xxx_cpu_has_pll_wo(void)
96{
97 switch (read_c0_prid()) {
98 case 0x00030100: /* Au1000 DA */
99 case 0x00030201: /* Au1000 HA */
100 case 0x00030202: /* Au1000 HB */
101 return 1;
102 }
103 return 0;
104}
105
106/* does CPU need CONFIG[OD] set to fix tons of errata? */
107static inline int au1xxx_cpu_needs_config_od(void)
108{
109 /*
110 * c0_config.od (bit 19) was write only (and read as 0) on the
111 * early revisions of Alchemy SOCs. It disables the bus trans-
112 * action overlapping and needs to be set to fix various errata.
113 */
114 switch (read_c0_prid()) {
115 case 0x00030100: /* Au1000 DA */
116 case 0x00030201: /* Au1000 HA */
117 case 0x00030202: /* Au1000 HB */
118 case 0x01030200: /* Au1500 AB */
119 /*
120 * Au1100/Au1200 errata actually keep silence about this bit,
121 * so we set it just in case for those revisions that require
122 * it to be set according to the (now gone) cpu_table.
123 */
124 case 0x02030200: /* Au1100 AB */
125 case 0x02030201: /* Au1100 BA */
126 case 0x02030202: /* Au1100 BC */
127 case 0x04030201: /* Au1200 AC */
128 return 1;
129 }
130 return 0;
131}
94 132
95/* arch/mips/au1000/common/clocks.c */ 133/* arch/mips/au1000/common/clocks.c */
96extern void set_au1x00_speed(unsigned int new_freq); 134extern void set_au1x00_speed(unsigned int new_freq);
97extern unsigned int get_au1x00_speed(void); 135extern unsigned int get_au1x00_speed(void);
98extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); 136extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
99extern unsigned long get_au1x00_uart_baud_base(void); 137extern unsigned long get_au1x00_uart_baud_base(void);
100extern void set_au1x00_lcd_clock(void); 138extern unsigned long au1xxx_calc_clock(void);
101extern unsigned int get_au1x00_lcd_clock(void); 139
140/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
141void au1xxx_save_and_sleep(void);
142void au_sleep(void);
143void save_au1xxx_intctl(void);
144void restore_au1xxx_intctl(void);
102 145
103/* 146/*
104 * Every board describes its IRQ mapping with this table. 147 * Every board describes its IRQ mapping with this table.
@@ -109,10 +152,11 @@ struct au1xxx_irqmap {
109 int im_request; 152 int im_request;
110}; 153};
111 154
112/* 155/* core calls this function to let boards initialize other IRQ sources */
113 * init_IRQ looks for a table with this name. 156void board_init_irq(void);
114 */ 157
115extern struct au1xxx_irqmap au1xxx_irq_map[]; 158/* boards call this to register additional (GPIO) interrupts */
159void au1xxx_setup_irqmap(struct au1xxx_irqmap *map, int count);
116 160
117#endif /* !defined (_LANGUAGE_ASSEMBLY) */ 161#endif /* !defined (_LANGUAGE_ASSEMBLY) */
118 162
@@ -505,15 +549,6 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
505 549
506#define IC1_TESTBIT 0xB1800080 550#define IC1_TESTBIT 0xB1800080
507 551
508/* Interrupt Configuration Modes */
509#define INTC_INT_DISABLED 0x0
510#define INTC_INT_RISE_EDGE 0x1
511#define INTC_INT_FALL_EDGE 0x2
512#define INTC_INT_RISE_AND_FALL_EDGE 0x3
513#define INTC_INT_HIGH_LEVEL 0x5
514#define INTC_INT_LOW_LEVEL 0x6
515#define INTC_INT_HIGH_AND_LOW_LEVEL 0x7
516
517/* Interrupt Numbers */ 552/* Interrupt Numbers */
518/* Au1000 */ 553/* Au1000 */
519#ifdef CONFIG_SOC_AU1000 554#ifdef CONFIG_SOC_AU1000
@@ -1525,6 +1560,10 @@ enum soc_au1200_ints {
1525#define SYS_SLPPWR 0xB1900078 1560#define SYS_SLPPWR 0xB1900078
1526#define SYS_SLEEP 0xB190007C 1561#define SYS_SLEEP 0xB190007C
1527 1562
1563#define SYS_WAKEMSK_D2 (1 << 9)
1564#define SYS_WAKEMSK_M2 (1 << 8)
1565#define SYS_WAKEMSK_GPIO(x) (1 << (x))
1566
1528/* Clock Controller */ 1567/* Clock Controller */
1529#define SYS_FREQCTRL0 0xB1900020 1568#define SYS_FREQCTRL0 0xB1900020
1530# define SYS_FC_FRDIV2_BIT 22 1569# define SYS_FC_FRDIV2_BIT 22
@@ -1749,24 +1788,4 @@ static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
1749 1788
1750#endif 1789#endif
1751 1790
1752/*
1753 * Processor information based on PRID.
1754 * Copied from PowerPC.
1755 */
1756#ifndef _LANGUAGE_ASSEMBLY
1757struct cpu_spec {
1758 /* CPU is matched via (PRID & prid_mask) == prid_value */
1759 unsigned int prid_mask;
1760 unsigned int prid_value;
1761
1762 char *cpu_name;
1763 unsigned char cpu_od; /* Set Config[OD] */
1764 unsigned char cpu_bclk; /* Enable BCLK switching */
1765 unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */
1766};
1767
1768extern struct cpu_spec cpu_specs[];
1769extern struct cpu_spec *cur_cpu_spec[];
1770#endif
1771
1772#endif 1791#endif
diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
index 44a67bf05dc1..06f68f43800a 100644
--- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
+++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h
@@ -357,6 +357,11 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
357u32 au1xxx_ddma_add_device(dbdev_tab_t *dev); 357u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
358extern void au1xxx_ddma_del_device(u32 devid); 358extern void au1xxx_ddma_del_device(u32 devid);
359void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp); 359void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
360#ifdef CONFIG_PM
361void au1xxx_dbdma_suspend(void);
362void au1xxx_dbdma_resume(void);
363#endif
364
360 365
361/* 366/*
362 * Some compatibilty macros -- needed to make changes to API 367 * Some compatibilty macros -- needed to make changes to API
diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
new file mode 100644
index 000000000000..04ce6e6569da
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -0,0 +1,78 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004 Cavium Networks
7 */
8#ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
9#define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H
10
11#include <linux/types.h>
12#include <asm/mipsregs.h>
13
14/*
15 * Cavium Octeons are MIPS64v2 processors
16 */
17#define cpu_dcache_line_size() 128
18#define cpu_icache_line_size() 128
19
20
21#define cpu_has_4kex 1
22#define cpu_has_3k_cache 0
23#define cpu_has_4k_cache 0
24#define cpu_has_tx39_cache 0
25#define cpu_has_fpu 0
26#define cpu_has_counter 1
27#define cpu_has_watch 1
28#define cpu_has_divec 1
29#define cpu_has_vce 0
30#define cpu_has_cache_cdex_p 0
31#define cpu_has_cache_cdex_s 0
32#define cpu_has_prefetch 1
33
34/*
35 * We should disable LL/SC on non SMP systems as it is faster to
36 * disable interrupts for atomic access than a LL/SC. Unfortunatly we
37 * cannot as this breaks asm/futex.h
38 */
39#define cpu_has_llsc 1
40#define cpu_has_vtag_icache 1
41#define cpu_has_dc_aliases 0
42#define cpu_has_ic_fills_f_dc 0
43#define cpu_has_64bits 1
44#define cpu_has_octeon_cache 1
45#define cpu_has_saa octeon_has_saa()
46#define cpu_has_mips32r1 0
47#define cpu_has_mips32r2 0
48#define cpu_has_mips64r1 0
49#define cpu_has_mips64r2 1
50#define cpu_has_dsp 0
51#define cpu_has_mipsmt 0
52#define cpu_has_userlocal 0
53#define cpu_has_vint 0
54#define cpu_has_veic 0
55#define ARCH_HAS_READ_CURRENT_TIMER 1
56#define ARCH_HAS_IRQ_PER_CPU 1
57#define ARCH_HAS_SPINLOCK_PREFETCH 1
58#define spin_lock_prefetch(x) prefetch(x)
59#define PREFETCH_STRIDE 128
60
61static inline int read_current_timer(unsigned long *result)
62{
63 asm volatile ("rdhwr %0,$31\n"
64#ifndef CONFIG_64BIT
65 "\tsll %0, 0"
66#endif
67 : "=r" (*result));
68 return 0;
69}
70
71static inline int octeon_has_saa(void)
72{
73 int id;
74 asm volatile ("mfc0 %0, $15,0" : "=r" (id));
75 return id >= 0x000d0300;
76}
77
78#endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
new file mode 100644
index 000000000000..f30fce92aabb
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h
@@ -0,0 +1,64 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
7 *
8 *
9 * Similar to mach-generic/dma-coherence.h except
10 * plat_device_is_coherent hard coded to return 1.
11 *
12 */
13#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
14#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H
15
16struct device;
17
18dma_addr_t octeon_map_dma_mem(struct device *, void *, size_t);
19void octeon_unmap_dma_mem(struct device *, dma_addr_t);
20
21static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
22 size_t size)
23{
24 return octeon_map_dma_mem(dev, addr, size);
25}
26
27static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
28 struct page *page)
29{
30 return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE);
31}
32
33static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
34{
35 return dma_addr;
36}
37
38static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
39{
40 octeon_unmap_dma_mem(dev, dma_addr);
41}
42
43static inline int plat_dma_supported(struct device *dev, u64 mask)
44{
45 return 1;
46}
47
48static inline void plat_extra_sync_for_device(struct device *dev)
49{
50 mb();
51}
52
53static inline int plat_device_is_coherent(struct device *dev)
54{
55 return 1;
56}
57
58static inline int plat_dma_mapping_error(struct device *dev,
59 dma_addr_t dma_addr)
60{
61 return dma_addr == -1;
62}
63
64#endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h
new file mode 100644
index 000000000000..d32220fbf4f1
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h
@@ -0,0 +1,244 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2008 Cavium Networks
7 */
8#ifndef __OCTEON_IRQ_H__
9#define __OCTEON_IRQ_H__
10
11#define NR_IRQS OCTEON_IRQ_LAST
12#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0
13
14/* 0 - 7 represent the i8259 master */
15#define OCTEON_IRQ_I8259M0 0
16#define OCTEON_IRQ_I8259M1 1
17#define OCTEON_IRQ_I8259M2 2
18#define OCTEON_IRQ_I8259M3 3
19#define OCTEON_IRQ_I8259M4 4
20#define OCTEON_IRQ_I8259M5 5
21#define OCTEON_IRQ_I8259M6 6
22#define OCTEON_IRQ_I8259M7 7
23/* 8 - 15 represent the i8259 slave */
24#define OCTEON_IRQ_I8259S0 8
25#define OCTEON_IRQ_I8259S1 9
26#define OCTEON_IRQ_I8259S2 10
27#define OCTEON_IRQ_I8259S3 11
28#define OCTEON_IRQ_I8259S4 12
29#define OCTEON_IRQ_I8259S5 13
30#define OCTEON_IRQ_I8259S6 14
31#define OCTEON_IRQ_I8259S7 15
32/* 16 - 23 represent the 8 MIPS standard interrupt sources */
33#define OCTEON_IRQ_SW0 16
34#define OCTEON_IRQ_SW1 17
35#define OCTEON_IRQ_CIU0 18
36#define OCTEON_IRQ_CIU1 19
37#define OCTEON_IRQ_CIU4 20
38#define OCTEON_IRQ_5 21
39#define OCTEON_IRQ_PERF 22
40#define OCTEON_IRQ_TIMER 23
41/* 24 - 87 represent the sources in CIU_INTX_EN0 */
42#define OCTEON_IRQ_WORKQ0 24
43#define OCTEON_IRQ_WORKQ1 25
44#define OCTEON_IRQ_WORKQ2 26
45#define OCTEON_IRQ_WORKQ3 27
46#define OCTEON_IRQ_WORKQ4 28
47#define OCTEON_IRQ_WORKQ5 29
48#define OCTEON_IRQ_WORKQ6 30
49#define OCTEON_IRQ_WORKQ7 31
50#define OCTEON_IRQ_WORKQ8 32
51#define OCTEON_IRQ_WORKQ9 33
52#define OCTEON_IRQ_WORKQ10 34
53#define OCTEON_IRQ_WORKQ11 35
54#define OCTEON_IRQ_WORKQ12 36
55#define OCTEON_IRQ_WORKQ13 37
56#define OCTEON_IRQ_WORKQ14 38
57#define OCTEON_IRQ_WORKQ15 39
58#define OCTEON_IRQ_GPIO0 40
59#define OCTEON_IRQ_GPIO1 41
60#define OCTEON_IRQ_GPIO2 42
61#define OCTEON_IRQ_GPIO3 43
62#define OCTEON_IRQ_GPIO4 44
63#define OCTEON_IRQ_GPIO5 45
64#define OCTEON_IRQ_GPIO6 46
65#define OCTEON_IRQ_GPIO7 47
66#define OCTEON_IRQ_GPIO8 48
67#define OCTEON_IRQ_GPIO9 49
68#define OCTEON_IRQ_GPIO10 50
69#define OCTEON_IRQ_GPIO11 51
70#define OCTEON_IRQ_GPIO12 52
71#define OCTEON_IRQ_GPIO13 53
72#define OCTEON_IRQ_GPIO14 54
73#define OCTEON_IRQ_GPIO15 55
74#define OCTEON_IRQ_MBOX0 56
75#define OCTEON_IRQ_MBOX1 57
76#define OCTEON_IRQ_UART0 58
77#define OCTEON_IRQ_UART1 59
78#define OCTEON_IRQ_PCI_INT0 60
79#define OCTEON_IRQ_PCI_INT1 61
80#define OCTEON_IRQ_PCI_INT2 62
81#define OCTEON_IRQ_PCI_INT3 63
82#define OCTEON_IRQ_PCI_MSI0 64
83#define OCTEON_IRQ_PCI_MSI1 65
84#define OCTEON_IRQ_PCI_MSI2 66
85#define OCTEON_IRQ_PCI_MSI3 67
86#define OCTEON_IRQ_RESERVED68 68 /* Summary of CIU_INT_SUM1 */
87#define OCTEON_IRQ_TWSI 69
88#define OCTEON_IRQ_RML 70
89#define OCTEON_IRQ_TRACE 71
90#define OCTEON_IRQ_GMX_DRP0 72
91#define OCTEON_IRQ_GMX_DRP1 73
92#define OCTEON_IRQ_IPD_DRP 74
93#define OCTEON_IRQ_KEY_ZERO 75
94#define OCTEON_IRQ_TIMER0 76
95#define OCTEON_IRQ_TIMER1 77
96#define OCTEON_IRQ_TIMER2 78
97#define OCTEON_IRQ_TIMER3 79
98#define OCTEON_IRQ_USB0 80
99#define OCTEON_IRQ_PCM 81
100#define OCTEON_IRQ_MPI 82
101#define OCTEON_IRQ_TWSI2 83
102#define OCTEON_IRQ_POWIQ 84
103#define OCTEON_IRQ_IPDPPTHR 85
104#define OCTEON_IRQ_MII0 86
105#define OCTEON_IRQ_BOOTDMA 87
106/* 88 - 151 represent the sources in CIU_INTX_EN1 */
107#define OCTEON_IRQ_WDOG0 88
108#define OCTEON_IRQ_WDOG1 89
109#define OCTEON_IRQ_WDOG2 90
110#define OCTEON_IRQ_WDOG3 91
111#define OCTEON_IRQ_WDOG4 92
112#define OCTEON_IRQ_WDOG5 93
113#define OCTEON_IRQ_WDOG6 94
114#define OCTEON_IRQ_WDOG7 95
115#define OCTEON_IRQ_WDOG8 96
116#define OCTEON_IRQ_WDOG9 97
117#define OCTEON_IRQ_WDOG10 98
118#define OCTEON_IRQ_WDOG11 99
119#define OCTEON_IRQ_WDOG12 100
120#define OCTEON_IRQ_WDOG13 101
121#define OCTEON_IRQ_WDOG14 102
122#define OCTEON_IRQ_WDOG15 103
123#define OCTEON_IRQ_UART2 104
124#define OCTEON_IRQ_USB1 105
125#define OCTEON_IRQ_MII1 106
126#define OCTEON_IRQ_RESERVED107 107
127#define OCTEON_IRQ_RESERVED108 108
128#define OCTEON_IRQ_RESERVED109 109
129#define OCTEON_IRQ_RESERVED110 110
130#define OCTEON_IRQ_RESERVED111 111
131#define OCTEON_IRQ_RESERVED112 112
132#define OCTEON_IRQ_RESERVED113 113
133#define OCTEON_IRQ_RESERVED114 114
134#define OCTEON_IRQ_RESERVED115 115
135#define OCTEON_IRQ_RESERVED116 116
136#define OCTEON_IRQ_RESERVED117 117
137#define OCTEON_IRQ_RESERVED118 118
138#define OCTEON_IRQ_RESERVED119 119
139#define OCTEON_IRQ_RESERVED120 120
140#define OCTEON_IRQ_RESERVED121 121
141#define OCTEON_IRQ_RESERVED122 122
142#define OCTEON_IRQ_RESERVED123 123
143#define OCTEON_IRQ_RESERVED124 124
144#define OCTEON_IRQ_RESERVED125 125
145#define OCTEON_IRQ_RESERVED126 126
146#define OCTEON_IRQ_RESERVED127 127
147#define OCTEON_IRQ_RESERVED128 128
148#define OCTEON_IRQ_RESERVED129 129
149#define OCTEON_IRQ_RESERVED130 130
150#define OCTEON_IRQ_RESERVED131 131
151#define OCTEON_IRQ_RESERVED132 132
152#define OCTEON_IRQ_RESERVED133 133
153#define OCTEON_IRQ_RESERVED134 134
154#define OCTEON_IRQ_RESERVED135 135
155#define OCTEON_IRQ_RESERVED136 136
156#define OCTEON_IRQ_RESERVED137 137
157#define OCTEON_IRQ_RESERVED138 138
158#define OCTEON_IRQ_RESERVED139 139
159#define OCTEON_IRQ_RESERVED140 140
160#define OCTEON_IRQ_RESERVED141 141
161#define OCTEON_IRQ_RESERVED142 142
162#define OCTEON_IRQ_RESERVED143 143
163#define OCTEON_IRQ_RESERVED144 144
164#define OCTEON_IRQ_RESERVED145 145
165#define OCTEON_IRQ_RESERVED146 146
166#define OCTEON_IRQ_RESERVED147 147
167#define OCTEON_IRQ_RESERVED148 148
168#define OCTEON_IRQ_RESERVED149 149
169#define OCTEON_IRQ_RESERVED150 150
170#define OCTEON_IRQ_RESERVED151 151
171
172#ifdef CONFIG_PCI_MSI
173/* 152 - 215 represent the MSI interrupts 0-63 */
174#define OCTEON_IRQ_MSI_BIT0 152
175#define OCTEON_IRQ_MSI_BIT1 153
176#define OCTEON_IRQ_MSI_BIT2 154
177#define OCTEON_IRQ_MSI_BIT3 155
178#define OCTEON_IRQ_MSI_BIT4 156
179#define OCTEON_IRQ_MSI_BIT5 157
180#define OCTEON_IRQ_MSI_BIT6 158
181#define OCTEON_IRQ_MSI_BIT7 159
182#define OCTEON_IRQ_MSI_BIT8 160
183#define OCTEON_IRQ_MSI_BIT9 161
184#define OCTEON_IRQ_MSI_BIT10 162
185#define OCTEON_IRQ_MSI_BIT11 163
186#define OCTEON_IRQ_MSI_BIT12 164
187#define OCTEON_IRQ_MSI_BIT13 165
188#define OCTEON_IRQ_MSI_BIT14 166
189#define OCTEON_IRQ_MSI_BIT15 167
190#define OCTEON_IRQ_MSI_BIT16 168
191#define OCTEON_IRQ_MSI_BIT17 169
192#define OCTEON_IRQ_MSI_BIT18 170
193#define OCTEON_IRQ_MSI_BIT19 171
194#define OCTEON_IRQ_MSI_BIT20 172
195#define OCTEON_IRQ_MSI_BIT21 173
196#define OCTEON_IRQ_MSI_BIT22 174
197#define OCTEON_IRQ_MSI_BIT23 175
198#define OCTEON_IRQ_MSI_BIT24 176
199#define OCTEON_IRQ_MSI_BIT25 177
200#define OCTEON_IRQ_MSI_BIT26 178
201#define OCTEON_IRQ_MSI_BIT27 179
202#define OCTEON_IRQ_MSI_BIT28 180
203#define OCTEON_IRQ_MSI_BIT29 181
204#define OCTEON_IRQ_MSI_BIT30 182
205#define OCTEON_IRQ_MSI_BIT31 183
206#define OCTEON_IRQ_MSI_BIT32 184
207#define OCTEON_IRQ_MSI_BIT33 185
208#define OCTEON_IRQ_MSI_BIT34 186
209#define OCTEON_IRQ_MSI_BIT35 187
210#define OCTEON_IRQ_MSI_BIT36 188
211#define OCTEON_IRQ_MSI_BIT37 189
212#define OCTEON_IRQ_MSI_BIT38 190
213#define OCTEON_IRQ_MSI_BIT39 191
214#define OCTEON_IRQ_MSI_BIT40 192
215#define OCTEON_IRQ_MSI_BIT41 193
216#define OCTEON_IRQ_MSI_BIT42 194
217#define OCTEON_IRQ_MSI_BIT43 195
218#define OCTEON_IRQ_MSI_BIT44 196
219#define OCTEON_IRQ_MSI_BIT45 197
220#define OCTEON_IRQ_MSI_BIT46 198
221#define OCTEON_IRQ_MSI_BIT47 199
222#define OCTEON_IRQ_MSI_BIT48 200
223#define OCTEON_IRQ_MSI_BIT49 201
224#define OCTEON_IRQ_MSI_BIT50 202
225#define OCTEON_IRQ_MSI_BIT51 203
226#define OCTEON_IRQ_MSI_BIT52 204
227#define OCTEON_IRQ_MSI_BIT53 205
228#define OCTEON_IRQ_MSI_BIT54 206
229#define OCTEON_IRQ_MSI_BIT55 207
230#define OCTEON_IRQ_MSI_BIT56 208
231#define OCTEON_IRQ_MSI_BIT57 209
232#define OCTEON_IRQ_MSI_BIT58 210
233#define OCTEON_IRQ_MSI_BIT59 211
234#define OCTEON_IRQ_MSI_BIT60 212
235#define OCTEON_IRQ_MSI_BIT61 213
236#define OCTEON_IRQ_MSI_BIT62 214
237#define OCTEON_IRQ_MSI_BIT63 215
238
239#define OCTEON_IRQ_LAST 216
240#else
241#define OCTEON_IRQ_LAST 152
242#endif
243
244#endif
diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
new file mode 100644
index 000000000000..0b2b5eb22e9b
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h
@@ -0,0 +1,131 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005-2008 Cavium Networks, Inc
7 */
8#ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
9#define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H
10
11
12#define CP0_CYCLE_COUNTER $9, 6
13#define CP0_CVMCTL_REG $9, 7
14#define CP0_CVMMEMCTL_REG $11,7
15#define CP0_PRID_REG $15, 0
16#define CP0_PRID_OCTEON_PASS1 0x000d0000
17#define CP0_PRID_OCTEON_CN30XX 0x000d0200
18
19.macro kernel_entry_setup
20 # Registers set by bootloader:
21 # (only 32 bits set by bootloader, all addresses are physical
22 # addresses, and need to have the appropriate memory region set
23 # by the kernel
24 # a0 = argc
25 # a1 = argv (kseg0 compat addr)
26 # a2 = 1 if init core, zero otherwise
27 # a3 = address of boot descriptor block
28 .set push
29 .set arch=octeon
30 # Read the cavium mem control register
31 dmfc0 v0, CP0_CVMMEMCTL_REG
32 # Clear the lower 6 bits, the CVMSEG size
33 dins v0, $0, 0, 6
34 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
35 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
36 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
37#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED
38 # Disable unaligned load/store support but leave HW fixup enabled
39 or v0, v0, 0x5001
40 xor v0, v0, 0x1001
41#else
42 # Disable unaligned load/store and HW fixup support
43 or v0, v0, 0x5001
44 xor v0, v0, 0x5001
45#endif
46 # Read the processor ID register
47 mfc0 v1, CP0_PRID_REG
48 # Disable instruction prefetching (Octeon Pass1 errata)
49 or v0, v0, 0x2000
50 # Skip reenable of prefetching for Octeon Pass1
51 beq v1, CP0_PRID_OCTEON_PASS1, skip
52 nop
53 # Reenable instruction prefetching, not on Pass1
54 xor v0, v0, 0x2000
55 # Strip off pass number off of processor id
56 srl v1, 8
57 sll v1, 8
58 # CN30XX needs some extra stuff turned off for better performance
59 bne v1, CP0_PRID_OCTEON_CN30XX, skip
60 nop
61 # CN30XX Use random Icache replacement
62 or v0, v0, 0x400
63 # CN30XX Disable instruction prefetching
64 or v0, v0, 0x2000
65skip:
66 # Write the cavium control register
67 dmtc0 v0, CP0_CVMCTL_REG
68 sync
69 # Flush dcache after config change
70 cache 9, 0($0)
71 # Get my core id
72 rdhwr v0, $0
73 # Jump the master to kernel_entry
74 bne a2, zero, octeon_main_processor
75 nop
76
77#ifdef CONFIG_SMP
78
79 #
80 # All cores other than the master need to wait here for SMP bootstrap
81 # to begin
82 #
83
84 # This is the variable where the next core to boot os stored
85 PTR_LA t0, octeon_processor_boot
86octeon_spin_wait_boot:
87 # Get the core id of the next to be booted
88 LONG_L t1, (t0)
89 # Keep looping if it isn't me
90 bne t1, v0, octeon_spin_wait_boot
91 nop
92 # Get my GP from the global variable
93 PTR_LA t0, octeon_processor_gp
94 LONG_L gp, (t0)
95 # Get my SP from the global variable
96 PTR_LA t0, octeon_processor_sp
97 LONG_L sp, (t0)
98 # Set the SP global variable to zero so the master knows we've started
99 LONG_S zero, (t0)
100#ifdef __OCTEON__
101 syncw
102 syncw
103#else
104 sync
105#endif
106 # Jump to the normal Linux SMP entry point
107 j smp_bootstrap
108 nop
109#else /* CONFIG_SMP */
110
111 #
112 # Someone tried to boot SMP with a non SMP kernel. All extra cores
113 # will halt here.
114 #
115octeon_wait_forever:
116 wait
117 b octeon_wait_forever
118 nop
119
120#endif /* CONFIG_SMP */
121octeon_main_processor:
122 .set pop
123.endm
124
125/*
126 * Do SMP slave processor setup necessary before we can savely execute C code.
127 */
128 .macro smp_slave_setup
129 .endm
130
131#endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
new file mode 100644
index 000000000000..c4712d7cc81d
--- /dev/null
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -0,0 +1,26 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
7 * Copyright (C) 2008 Cavium Networks <support@caviumnetworks.com>
8 */
9#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
10#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
11
12#define R4600_V1_INDEX_ICACHEOP_WAR 0
13#define R4600_V1_HIT_CACHEOP_WAR 0
14#define R4600_V2_HIT_CACHEOP_WAR 0
15#define R5432_CP0_INTERRUPT_WAR 0
16#define BCM1250_M3_WAR 0
17#define SIBYTE_1956_WAR 0
18#define MIPS4K_ICACHE_REFILL_WAR 0
19#define MIPS_CACHE_SYNC_WAR 0
20#define TX49XX_ICACHE_INDEX_INV_WAR 0
21#define RM9000_CDEX_SMP_WAR 0
22#define ICACHE_REFILLS_WORKAROUND_WAR 0
23#define R10000_LLSC_WAR 0
24#define MIPS34K_MISSED_ITLB_WAR 0
25
26#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */
diff --git a/arch/mips/include/asm/mach-generic/dma-coherence.h b/arch/mips/include/asm/mach-generic/dma-coherence.h
index 76e04e7feb84..36c611b6c597 100644
--- a/arch/mips/include/asm/mach-generic/dma-coherence.h
+++ b/arch/mips/include/asm/mach-generic/dma-coherence.h
@@ -28,10 +28,34 @@ static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
28 return dma_addr; 28 return dma_addr;
29} 29}
30 30
31static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) 31static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
32{ 32{
33} 33}
34 34
35static inline int plat_dma_supported(struct device *dev, u64 mask)
36{
37 /*
38 * we fall back to GFP_DMA when the mask isn't all 1s,
39 * so we can't guarantee allocations that must be
40 * within a tighter range than GFP_DMA..
41 */
42 if (mask < DMA_BIT_MASK(24))
43 return 0;
44
45 return 1;
46}
47
48static inline void plat_extra_sync_for_device(struct device *dev)
49{
50 return;
51}
52
53static inline int plat_dma_mapping_error(struct device *dev,
54 dma_addr_t dma_addr)
55{
56 return 0;
57}
58
35static inline int plat_device_is_coherent(struct device *dev) 59static inline int plat_device_is_coherent(struct device *dev)
36{ 60{
37#ifdef CONFIG_DMA_COHERENT 61#ifdef CONFIG_DMA_COHERENT
diff --git a/arch/mips/include/asm/mach-ip27/dma-coherence.h b/arch/mips/include/asm/mach-ip27/dma-coherence.h
index ed7e6222dc15..4c21bfca10c3 100644
--- a/arch/mips/include/asm/mach-ip27/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip27/dma-coherence.h
@@ -38,10 +38,34 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
38 return dma_addr & ~(0xffUL << 56); 38 return dma_addr & ~(0xffUL << 56);
39} 39}
40 40
41static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) 41static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
42{ 42{
43} 43}
44 44
45static inline int plat_dma_supported(struct device *dev, u64 mask)
46{
47 /*
48 * we fall back to GFP_DMA when the mask isn't all 1s,
49 * so we can't guarantee allocations that must be
50 * within a tighter range than GFP_DMA..
51 */
52 if (mask < DMA_BIT_MASK(24))
53 return 0;
54
55 return 1;
56}
57
58static inline void plat_extra_sync_for_device(struct device *dev)
59{
60 return;
61}
62
63static inline int plat_dma_mapping_error(struct device *dev,
64 dma_addr_t dma_addr)
65{
66 return 0;
67}
68
45static inline int plat_device_is_coherent(struct device *dev) 69static inline int plat_device_is_coherent(struct device *dev)
46{ 70{
47 return 1; /* IP27 non-cohernet mode is unsupported */ 71 return 1; /* IP27 non-cohernet mode is unsupported */
diff --git a/arch/mips/include/asm/mach-ip32/dma-coherence.h b/arch/mips/include/asm/mach-ip32/dma-coherence.h
index a5511ebb2d53..7ae40f4b1c80 100644
--- a/arch/mips/include/asm/mach-ip32/dma-coherence.h
+++ b/arch/mips/include/asm/mach-ip32/dma-coherence.h
@@ -60,10 +60,34 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
60 return addr; 60 return addr;
61} 61}
62 62
63static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) 63static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
64{ 64{
65} 65}
66 66
67static inline int plat_dma_supported(struct device *dev, u64 mask)
68{
69 /*
70 * we fall back to GFP_DMA when the mask isn't all 1s,
71 * so we can't guarantee allocations that must be
72 * within a tighter range than GFP_DMA..
73 */
74 if (mask < DMA_BIT_MASK(24))
75 return 0;
76
77 return 1;
78}
79
80static inline void plat_extra_sync_for_device(struct device *dev)
81{
82 return;
83}
84
85static inline int plat_dma_mapping_error(struct device *dev,
86 dma_addr_t dma_addr)
87{
88 return 0;
89}
90
67static inline int plat_device_is_coherent(struct device *dev) 91static inline int plat_device_is_coherent(struct device *dev)
68{ 92{
69 return 0; /* IP32 is non-cohernet */ 93 return 0; /* IP32 is non-cohernet */
diff --git a/arch/mips/include/asm/mach-jazz/dma-coherence.h b/arch/mips/include/asm/mach-jazz/dma-coherence.h
index d66979a124a8..1c7cd27efa7b 100644
--- a/arch/mips/include/asm/mach-jazz/dma-coherence.h
+++ b/arch/mips/include/asm/mach-jazz/dma-coherence.h
@@ -27,11 +27,35 @@ static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
27 return vdma_log2phys(dma_addr); 27 return vdma_log2phys(dma_addr);
28} 28}
29 29
30static void plat_unmap_dma_mem(dma_addr_t dma_addr) 30static void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
31{ 31{
32 vdma_free(dma_addr); 32 vdma_free(dma_addr);
33} 33}
34 34
35static inline int plat_dma_supported(struct device *dev, u64 mask)
36{
37 /*
38 * we fall back to GFP_DMA when the mask isn't all 1s,
39 * so we can't guarantee allocations that must be
40 * within a tighter range than GFP_DMA..
41 */
42 if (mask < DMA_BIT_MASK(24))
43 return 0;
44
45 return 1;
46}
47
48static inline void plat_extra_sync_for_device(struct device *dev)
49{
50 return;
51}
52
53static inline int plat_dma_mapping_error(struct device *dev,
54 dma_addr_t dma_addr)
55{
56 return 0;
57}
58
35static inline int plat_device_is_coherent(struct device *dev) 59static inline int plat_device_is_coherent(struct device *dev)
36{ 60{
37 return 0; 61 return 0;
diff --git a/arch/mips/include/asm/mach-lemote/dma-coherence.h b/arch/mips/include/asm/mach-lemote/dma-coherence.h
index 7e914777ebc4..38fad7dfe7da 100644
--- a/arch/mips/include/asm/mach-lemote/dma-coherence.h
+++ b/arch/mips/include/asm/mach-lemote/dma-coherence.h
@@ -30,10 +30,34 @@ static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
30 return dma_addr & 0x7fffffff; 30 return dma_addr & 0x7fffffff;
31} 31}
32 32
33static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) 33static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
34{ 34{
35} 35}
36 36
37static inline int plat_dma_supported(struct device *dev, u64 mask)
38{
39 /*
40 * we fall back to GFP_DMA when the mask isn't all 1s,
41 * so we can't guarantee allocations that must be
42 * within a tighter range than GFP_DMA..
43 */
44 if (mask < DMA_BIT_MASK(24))
45 return 0;
46
47 return 1;
48}
49
50static inline void plat_extra_sync_for_device(struct device *dev)
51{
52 return;
53}
54
55static inline int plat_dma_mapping_error(struct device *dev,
56 dma_addr_t dma_addr)
57{
58 return 0;
59}
60
37static inline int plat_device_is_coherent(struct device *dev) 61static inline int plat_device_is_coherent(struct device *dev)
38{ 62{
39 return 0; 63 return 0;
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 9316324d070d..0417516503f6 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -1000,6 +1000,26 @@ do { \
1000#define read_c0_ebase() __read_32bit_c0_register($15, 1) 1000#define read_c0_ebase() __read_32bit_c0_register($15, 1)
1001#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1001#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1002 1002
1003
1004/* Cavium OCTEON (cnMIPS) */
1005#define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1006#define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1007
1008#define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1009#define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1010
1011#define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1012#define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1013/*
1014 * The cacheerr registers are not standardized. On OCTEON, they are
1015 * 64 bits wide.
1016 */
1017#define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1018#define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1019
1020#define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1021#define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1022
1003/* 1023/*
1004 * Macros to access the floating point coprocessor control registers 1024 * Macros to access the floating point coprocessor control registers
1005 */ 1025 */
@@ -1008,6 +1028,8 @@ do { \
1008 __asm__ __volatile__( \ 1028 __asm__ __volatile__( \
1009 ".set\tpush\n\t" \ 1029 ".set\tpush\n\t" \
1010 ".set\treorder\n\t" \ 1030 ".set\treorder\n\t" \
1031 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
1032 ".set\tmips1\n\t" \
1011 "cfc1\t%0,"STR(source)"\n\t" \ 1033 "cfc1\t%0,"STR(source)"\n\t" \
1012 ".set\tpop" \ 1034 ".set\tpop" \
1013 : "=r" (__res)); \ 1035 : "=r" (__res)); \
diff --git a/arch/mips/include/asm/module.h b/arch/mips/include/asm/module.h
index e2e09b2cd265..d94085a3eafb 100644
--- a/arch/mips/include/asm/module.h
+++ b/arch/mips/include/asm/module.h
@@ -116,6 +116,8 @@ search_module_dbetables(unsigned long addr)
116#define MODULE_PROC_FAMILY "SB1 " 116#define MODULE_PROC_FAMILY "SB1 "
117#elif defined CONFIG_CPU_LOONGSON2 117#elif defined CONFIG_CPU_LOONGSON2
118#define MODULE_PROC_FAMILY "LOONGSON2 " 118#define MODULE_PROC_FAMILY "LOONGSON2 "
119#elif defined CONFIG_CPU_CAVIUM_OCTEON
120#define MODULE_PROC_FAMILY "OCTEON "
119#else 121#else
120#error MODULE_PROC_FAMILY undefined for your processor configuration 122#error MODULE_PROC_FAMILY undefined for your processor configuration
121#endif 123#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-asm.h b/arch/mips/include/asm/octeon/cvmx-asm.h
new file mode 100644
index 000000000000..b21d3fc1ef91
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-asm.h
@@ -0,0 +1,128 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * This is file defines ASM primitives for the executive.
31 */
32#ifndef __CVMX_ASM_H__
33#define __CVMX_ASM_H__
34
35#include "octeon-model.h"
36
37/* other useful stuff */
38#define CVMX_SYNC asm volatile ("sync" : : : "memory")
39/* String version of SYNCW macro for using in inline asm constructs */
40#define CVMX_SYNCW_STR "syncw\nsyncw\n"
41#ifdef __OCTEON__
42
43/* Deprecated, will be removed in future release */
44#define CVMX_SYNCIO asm volatile ("nop")
45
46#define CVMX_SYNCIOBDMA asm volatile ("synciobdma" : : : "memory")
47
48/* Deprecated, will be removed in future release */
49#define CVMX_SYNCIOALL asm volatile ("nop")
50
51/*
52 * We actually use two syncw instructions in a row when we need a write
53 * memory barrier. This is because the CN3XXX series of Octeons have
54 * errata Core-401. This can cause a single syncw to not enforce
55 * ordering under very rare conditions. Even if it is rare, better safe
56 * than sorry.
57 */
58#define CVMX_SYNCW asm volatile ("syncw\n\tsyncw" : : : "memory")
59
60/*
61 * Define new sync instructions to be normal SYNC instructions for
62 * operating systems that use threads.
63 */
64#define CVMX_SYNCWS CVMX_SYNCW
65#define CVMX_SYNCS CVMX_SYNC
66#define CVMX_SYNCWS_STR CVMX_SYNCW_STR
67#else
68/*
69 * Not using a Cavium compiler, always use the slower sync so the
70 * assembler stays happy.
71 */
72/* Deprecated, will be removed in future release */
73#define CVMX_SYNCIO asm volatile ("nop")
74
75#define CVMX_SYNCIOBDMA asm volatile ("sync" : : : "memory")
76
77/* Deprecated, will be removed in future release */
78#define CVMX_SYNCIOALL asm volatile ("nop")
79
80#define CVMX_SYNCW asm volatile ("sync" : : : "memory")
81#define CVMX_SYNCWS CVMX_SYNCW
82#define CVMX_SYNCS CVMX_SYNC
83#define CVMX_SYNCWS_STR CVMX_SYNCW_STR
84#endif
85
86/*
87 * CVMX_PREPARE_FOR_STORE makes each byte of the block unpredictable
88 * (actually old value or zero) until that byte is stored to (by this or
89 * another processor. Note that the value of each byte is not only
90 * unpredictable, but may also change again - up until the point when one
91 * of the cores stores to the byte.
92 */
93#define CVMX_PREPARE_FOR_STORE(address, offset) \
94 asm volatile ("pref 30, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
95 [rbase] "d" (address))
96/*
97 * This is a command headed to the L2 controller to tell it to clear
98 * its dirty bit for a block. Basically, SW is telling HW that the
99 * current version of the block will not be used.
100 */
101#define CVMX_DONT_WRITE_BACK(address, offset) \
102 asm volatile ("pref 29, " CVMX_TMP_STR(offset) "(%[rbase])" : : \
103 [rbase] "d" (address))
104
105/* flush stores, invalidate entire icache */
106#define CVMX_ICACHE_INVALIDATE \
107 { CVMX_SYNC; asm volatile ("synci 0($0)" : : ); }
108
109/* flush stores, invalidate entire icache */
110#define CVMX_ICACHE_INVALIDATE2 \
111 { CVMX_SYNC; asm volatile ("cache 0, 0($0)" : : ); }
112
113/* complete prefetches, invalidate entire dcache */
114#define CVMX_DCACHE_INVALIDATE \
115 { CVMX_SYNC; asm volatile ("cache 9, 0($0)" : : ); }
116
117
118#define CVMX_POP(result, input) \
119 asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
120#define CVMX_DPOP(result, input) \
121 asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
122
123/* some new cop0-like stuff */
124#define CVMX_RDHWR(result, regstr) \
125 asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
126#define CVMX_RDHWRNV(result, regstr) \
127 asm ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
128#endif /* __CVMX_ASM_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
new file mode 100644
index 000000000000..692989acd8a9
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h
@@ -0,0 +1,262 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Header file containing the ABI with the bootloader.
30 */
31
32#ifndef __CVMX_BOOTINFO_H__
33#define __CVMX_BOOTINFO_H__
34
35/*
36 * Current major and minor versions of the CVMX bootinfo block that is
37 * passed from the bootloader to the application. This is versioned
38 * so that applications can properly handle multiple bootloader
39 * versions.
40 */
41#define CVMX_BOOTINFO_MAJ_VER 1
42#define CVMX_BOOTINFO_MIN_VER 2
43
44#if (CVMX_BOOTINFO_MAJ_VER == 1)
45#define CVMX_BOOTINFO_OCTEON_SERIAL_LEN 20
46/*
47 * This structure is populated by the bootloader. For binary
48 * compatibility the only changes that should be made are
49 * adding members to the end of the structure, and the minor
50 * version should be incremented at that time.
51 * If an incompatible change is made, the major version
52 * must be incremented, and the minor version should be reset
53 * to 0.
54 */
55struct cvmx_bootinfo {
56 uint32_t major_version;
57 uint32_t minor_version;
58
59 uint64_t stack_top;
60 uint64_t heap_base;
61 uint64_t heap_end;
62 uint64_t desc_vaddr;
63
64 uint32_t exception_base_addr;
65 uint32_t stack_size;
66 uint32_t flags;
67 uint32_t core_mask;
68 /* DRAM size in megabytes */
69 uint32_t dram_size;
70 /* physical address of free memory descriptor block*/
71 uint32_t phy_mem_desc_addr;
72 /* used to pass flags from app to debugger */
73 uint32_t debugger_flags_base_addr;
74
75 /* CPU clock speed, in hz */
76 uint32_t eclock_hz;
77
78 /* DRAM clock speed, in hz */
79 uint32_t dclock_hz;
80
81 uint32_t reserved0;
82 uint16_t board_type;
83 uint8_t board_rev_major;
84 uint8_t board_rev_minor;
85 uint16_t reserved1;
86 uint8_t reserved2;
87 uint8_t reserved3;
88 char board_serial_number[CVMX_BOOTINFO_OCTEON_SERIAL_LEN];
89 uint8_t mac_addr_base[6];
90 uint8_t mac_addr_count;
91#if (CVMX_BOOTINFO_MIN_VER >= 1)
92 /*
93 * Several boards support compact flash on the Octeon boot
94 * bus. The CF memory spaces may be mapped to different
95 * addresses on different boards. These are the physical
96 * addresses, so care must be taken to use the correct
97 * XKPHYS/KSEG0 addressing depending on the application's
98 * ABI. These values will be 0 if CF is not present.
99 */
100 uint64_t compact_flash_common_base_addr;
101 uint64_t compact_flash_attribute_base_addr;
102 /*
103 * Base address of the LED display (as on EBT3000 board)
104 * This will be 0 if LED display not present.
105 */
106 uint64_t led_display_base_addr;
107#endif
108#if (CVMX_BOOTINFO_MIN_VER >= 2)
109 /* DFA reference clock in hz (if applicable)*/
110 uint32_t dfa_ref_clock_hz;
111
112 /*
113 * flags indicating various configuration options. These
114 * flags supercede the 'flags' variable and should be used
115 * instead if available.
116 */
117 uint32_t config_flags;
118#endif
119
120};
121
122#define CVMX_BOOTINFO_CFG_FLAG_PCI_HOST (1ull << 0)
123#define CVMX_BOOTINFO_CFG_FLAG_PCI_TARGET (1ull << 1)
124#define CVMX_BOOTINFO_CFG_FLAG_DEBUG (1ull << 2)
125#define CVMX_BOOTINFO_CFG_FLAG_NO_MAGIC (1ull << 3)
126/* This flag is set if the TLB mappings are not contained in the
127 * 0x10000000 - 0x20000000 boot bus region. */
128#define CVMX_BOOTINFO_CFG_FLAG_OVERSIZE_TLB_MAPPING (1ull << 4)
129#define CVMX_BOOTINFO_CFG_FLAG_BREAK (1ull << 5)
130
131#endif /* (CVMX_BOOTINFO_MAJ_VER == 1) */
132
133/* Type defines for board and chip types */
134enum cvmx_board_types_enum {
135 CVMX_BOARD_TYPE_NULL = 0,
136 CVMX_BOARD_TYPE_SIM = 1,
137 CVMX_BOARD_TYPE_EBT3000 = 2,
138 CVMX_BOARD_TYPE_KODAMA = 3,
139 CVMX_BOARD_TYPE_NIAGARA = 4,
140 CVMX_BOARD_TYPE_NAC38 = 5, /* formerly NAO38 */
141 CVMX_BOARD_TYPE_THUNDER = 6,
142 CVMX_BOARD_TYPE_TRANTOR = 7,
143 CVMX_BOARD_TYPE_EBH3000 = 8,
144 CVMX_BOARD_TYPE_EBH3100 = 9,
145 CVMX_BOARD_TYPE_HIKARI = 10,
146 CVMX_BOARD_TYPE_CN3010_EVB_HS5 = 11,
147 CVMX_BOARD_TYPE_CN3005_EVB_HS5 = 12,
148 CVMX_BOARD_TYPE_KBP = 13,
149 /* Deprecated, CVMX_BOARD_TYPE_CN3010_EVB_HS5 supports the CN3020 */
150 CVMX_BOARD_TYPE_CN3020_EVB_HS5 = 14,
151 CVMX_BOARD_TYPE_EBT5800 = 15,
152 CVMX_BOARD_TYPE_NICPRO2 = 16,
153 CVMX_BOARD_TYPE_EBH5600 = 17,
154 CVMX_BOARD_TYPE_EBH5601 = 18,
155 CVMX_BOARD_TYPE_EBH5200 = 19,
156 CVMX_BOARD_TYPE_BBGW_REF = 20,
157 CVMX_BOARD_TYPE_NIC_XLE_4G = 21,
158 CVMX_BOARD_TYPE_EBT5600 = 22,
159 CVMX_BOARD_TYPE_EBH5201 = 23,
160 CVMX_BOARD_TYPE_MAX,
161
162 /*
163 * The range from CVMX_BOARD_TYPE_MAX to
164 * CVMX_BOARD_TYPE_CUST_DEFINED_MIN is reserved for future
165 * SDK use.
166 */
167
168 /*
169 * Set aside a range for customer boards. These numbers are managed
170 * by Cavium.
171 */
172 CVMX_BOARD_TYPE_CUST_DEFINED_MIN = 10000,
173 CVMX_BOARD_TYPE_CUST_WSX16 = 10001,
174 CVMX_BOARD_TYPE_CUST_NS0216 = 10002,
175 CVMX_BOARD_TYPE_CUST_NB5 = 10003,
176 CVMX_BOARD_TYPE_CUST_WMR500 = 10004,
177 CVMX_BOARD_TYPE_CUST_DEFINED_MAX = 20000,
178
179 /*
180 * Set aside a range for customer private use. The SDK won't
181 * use any numbers in this range.
182 */
183 CVMX_BOARD_TYPE_CUST_PRIVATE_MIN = 20001,
184 CVMX_BOARD_TYPE_CUST_PRIVATE_MAX = 30000,
185
186 /* The remaining range is reserved for future use. */
187};
188
189enum cvmx_chip_types_enum {
190 CVMX_CHIP_TYPE_NULL = 0,
191 CVMX_CHIP_SIM_TYPE_DEPRECATED = 1,
192 CVMX_CHIP_TYPE_OCTEON_SAMPLE = 2,
193 CVMX_CHIP_TYPE_MAX,
194};
195
196/* Compatability alias for NAC38 name change, planned to be removed
197 * from SDK 1.7 */
198#define CVMX_BOARD_TYPE_NAO38 CVMX_BOARD_TYPE_NAC38
199
200/* Functions to return string based on type */
201#define ENUM_BRD_TYPE_CASE(x) \
202 case x: return(#x + 16); /* Skip CVMX_BOARD_TYPE_ */
203static inline const char *cvmx_board_type_to_string(enum
204 cvmx_board_types_enum type)
205{
206 switch (type) {
207 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NULL)
208 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_SIM)
209 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT3000)
210 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KODAMA)
211 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIAGARA)
212 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NAC38)
213 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_THUNDER)
214 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_TRANTOR)
215 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3000)
216 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH3100)
217 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_HIKARI)
218 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3010_EVB_HS5)
219 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3005_EVB_HS5)
220 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_KBP)
221 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CN3020_EVB_HS5)
222 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5800)
223 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NICPRO2)
224 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5600)
225 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5601)
226 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5200)
227 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_BBGW_REF)
228 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G)
229 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600)
230 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201)
231 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX)
232
233 /* Customer boards listed here */
234 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MIN)
235 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WSX16)
236 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NS0216)
237 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_NB5)
238 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_WMR500)
239 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_DEFINED_MAX)
240
241 /* Customer private range */
242 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MIN)
243 ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CUST_PRIVATE_MAX)
244 }
245 return "Unsupported Board";
246}
247
248#define ENUM_CHIP_TYPE_CASE(x) \
249 case x: return(#x + 15); /* Skip CVMX_CHIP_TYPE */
250static inline const char *cvmx_chip_type_to_string(enum
251 cvmx_chip_types_enum type)
252{
253 switch (type) {
254 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_NULL)
255 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_SIM_TYPE_DEPRECATED)
256 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_OCTEON_SAMPLE)
257 ENUM_CHIP_TYPE_CASE(CVMX_CHIP_TYPE_MAX)
258 }
259 return "Unsupported Chip";
260}
261
262#endif /* __CVMX_BOOTINFO_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h
new file mode 100644
index 000000000000..1cbe4b55889d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h
@@ -0,0 +1,288 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Simple allocate only memory allocator. Used to allocate memory at
30 * application start time.
31 */
32
33#ifndef __CVMX_BOOTMEM_H__
34#define __CVMX_BOOTMEM_H__
35/* Must be multiple of 8, changing breaks ABI */
36#define CVMX_BOOTMEM_NAME_LEN 128
37
38/* Can change without breaking ABI */
39#define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64
40
41/* minimum alignment of bootmem alloced blocks */
42#define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull)
43
44/* Flags for cvmx_bootmem_phy_mem* functions */
45/* Allocate from end of block instead of beginning */
46#define CVMX_BOOTMEM_FLAG_END_ALLOC (1 << 0)
47
48/* Don't do any locking. */
49#define CVMX_BOOTMEM_FLAG_NO_LOCKING (1 << 1)
50
51/* First bytes of each free physical block of memory contain this structure,
52 * which is used to maintain the free memory list. Since the bootloader is
53 * only 32 bits, there is a union providing 64 and 32 bit versions. The
54 * application init code converts addresses to 64 bit addresses before the
55 * application starts.
56 */
57struct cvmx_bootmem_block_header {
58 /*
59 * Note: these are referenced from assembly routines in the
60 * bootloader, so this structure should not be changed
61 * without changing those routines as well.
62 */
63 uint64_t next_block_addr;
64 uint64_t size;
65
66};
67
68/*
69 * Structure for named memory blocks. Number of descriptors available
70 * can be changed without affecting compatiblity, but name length
71 * changes require a bump in the bootmem descriptor version Note: This
72 * structure must be naturally 64 bit aligned, as a single memory
73 * image will be used by both 32 and 64 bit programs.
74 */
75struct cvmx_bootmem_named_block_desc {
76 /* Base address of named block */
77 uint64_t base_addr;
78 /*
79 * Size actually allocated for named block (may differ from
80 * requested).
81 */
82 uint64_t size;
83 /* name of named block */
84 char name[CVMX_BOOTMEM_NAME_LEN];
85};
86
87/* Current descriptor versions */
88/* CVMX bootmem descriptor major version */
89#define CVMX_BOOTMEM_DESC_MAJ_VER 3
90
91/* CVMX bootmem descriptor minor version */
92#define CVMX_BOOTMEM_DESC_MIN_VER 0
93
94/* First three members of cvmx_bootmem_desc_t are left in original
95 * positions for backwards compatibility.
96 */
97struct cvmx_bootmem_desc {
98 /* spinlock to control access to list */
99 uint32_t lock;
100 /* flags for indicating various conditions */
101 uint32_t flags;
102 uint64_t head_addr;
103
104 /* Incremented when incompatible changes made */
105 uint32_t major_version;
106
107 /*
108 * Incremented changed when compatible changes made, reset to
109 * zero when major incremented.
110 */
111 uint32_t minor_version;
112
113 uint64_t app_data_addr;
114 uint64_t app_data_size;
115
116 /* number of elements in named blocks array */
117 uint32_t named_block_num_blocks;
118
119 /* length of name array in bootmem blocks */
120 uint32_t named_block_name_len;
121 /* address of named memory block descriptors */
122 uint64_t named_block_array_addr;
123
124};
125
126/**
127 * Initialize the boot alloc memory structures. This is
128 * normally called inside of cvmx_user_app_init()
129 *
130 * @mem_desc_ptr: Address of the free memory list
131 */
132extern int cvmx_bootmem_init(void *mem_desc_ptr);
133
134/**
135 * Allocate a block of memory from the free list that was passed
136 * to the application by the bootloader.
137 * This is an allocate-only algorithm, so freeing memory is not possible.
138 *
139 * @size: Size in bytes of block to allocate
140 * @alignment: Alignment required - must be power of 2
141 *
142 * Returns pointer to block of memory, NULL on error
143 */
144extern void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment);
145
146/**
147 * Allocate a block of memory from the free list that was
148 * passed to the application by the bootloader at a specific
149 * address. This is an allocate-only algorithm, so
150 * freeing memory is not possible. Allocation will fail if
151 * memory cannot be allocated at the specified address.
152 *
153 * @size: Size in bytes of block to allocate
154 * @address: Physical address to allocate memory at. If this memory is not
155 * available, the allocation fails.
156 * @alignment: Alignment required - must be power of 2
157 * Returns pointer to block of memory, NULL on error
158 */
159extern void *cvmx_bootmem_alloc_address(uint64_t size, uint64_t address,
160 uint64_t alignment);
161
162/**
163 * Allocate a block of memory from the free list that was
164 * passed to the application by the bootloader within a specified
165 * address range. This is an allocate-only algorithm, so
166 * freeing memory is not possible. Allocation will fail if
167 * memory cannot be allocated in the requested range.
168 *
169 * @size: Size in bytes of block to allocate
170 * @min_addr: defines the minimum address of the range
171 * @max_addr: defines the maximum address of the range
172 * @alignment: Alignment required - must be power of 2
173 * Returns pointer to block of memory, NULL on error
174 */
175extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment,
176 uint64_t min_addr, uint64_t max_addr);
177
178/**
179 * Frees a previously allocated named bootmem block.
180 *
181 * @name: name of block to free
182 *
183 * Returns 0 on failure,
184 * !0 on success
185 */
186extern int cvmx_bootmem_free_named(char *name);
187
188/**
189 * Finds a named bootmem block by name.
190 *
191 * @name: name of block to free
192 *
193 * Returns pointer to named block descriptor on success
194 * 0 on failure
195 */
196struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name);
197
198/**
199 * Allocates a block of physical memory from the free list, at
200 * (optional) requested address and alignment.
201 *
202 * @req_size: size of region to allocate. All requests are rounded up
203 * to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE bytes size
204 *
205 * @address_min: Minimum address that block can occupy.
206 *
207 * @address_max: Specifies the maximum address_min (inclusive) that
208 * the allocation can use.
209 *
210 * @alignment: Requested alignment of the block. If this alignment
211 * cannot be met, the allocation fails. This must be a
212 * power of 2. (Note: Alignment of
213 * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and
214 * internally enforced. Requested alignments of less than
215 * CVMX_BOOTMEM_ALIGNMENT_SIZE are set to
216 * CVMX_BOOTMEM_ALIGNMENT_SIZE.)
217 *
218 * @flags: Flags to control options for the allocation.
219 *
220 * Returns physical address of block allocated, or -1 on failure
221 */
222int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min,
223 uint64_t address_max, uint64_t alignment,
224 uint32_t flags);
225
226/**
227 * Finds a named memory block by name.
228 * Also used for finding an unused entry in the named block table.
229 *
230 * @name: Name of memory block to find. If NULL pointer given, then
231 * finds unused descriptor, if available.
232 *
233 * @flags: Flags to control options for the allocation.
234 *
235 * Returns Pointer to memory block descriptor, NULL if not found.
236 * If NULL returned when name parameter is NULL, then no memory
237 * block descriptors are available.
238 */
239struct cvmx_bootmem_named_block_desc *
240cvmx_bootmem_phy_named_block_find(char *name, uint32_t flags);
241
242/**
243 * Frees a named block.
244 *
245 * @name: name of block to free
246 * @flags: flags for passing options
247 *
248 * Returns 0 on failure
249 * 1 on success
250 */
251int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags);
252
253/**
254 * Frees a block to the bootmem allocator list. This must
255 * be used with care, as the size provided must match the size
256 * of the block that was allocated, or the list will become
257 * corrupted.
258 *
259 * IMPORTANT: This is only intended to be used as part of named block
260 * frees and initial population of the free memory list.
261 * *
262 *
263 * @phy_addr: physical address of block
264 * @size: size of block in bytes.
265 * @flags: flags for passing options
266 *
267 * Returns 1 on success,
268 * 0 on failure
269 */
270int __cvmx_bootmem_phy_free(uint64_t phy_addr, uint64_t size, uint32_t flags);
271
272/**
273 * Locks the bootmem allocator. This is useful in certain situations
274 * where multiple allocations must be made without being interrupted.
275 * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag.
276 *
277 */
278void cvmx_bootmem_lock(void);
279
280/**
281 * Unlocks the bootmem allocator. This is useful in certain situations
282 * where multiple allocations must be made without being interrupted.
283 * This should be used with the CVMX_BOOTMEM_FLAG_NO_LOCKING flag.
284 *
285 */
286void cvmx_bootmem_unlock(void);
287
288#endif /* __CVMX_BOOTMEM_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-ciu-defs.h b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
new file mode 100644
index 000000000000..f8f05b7764b7
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-ciu-defs.h
@@ -0,0 +1,1616 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_CIU_DEFS_H__
29#define __CVMX_CIU_DEFS_H__
30
31#define CVMX_CIU_BIST \
32 CVMX_ADD_IO_SEG(0x0001070000000730ull)
33#define CVMX_CIU_DINT \
34 CVMX_ADD_IO_SEG(0x0001070000000720ull)
35#define CVMX_CIU_FUSE \
36 CVMX_ADD_IO_SEG(0x0001070000000728ull)
37#define CVMX_CIU_GSTOP \
38 CVMX_ADD_IO_SEG(0x0001070000000710ull)
39#define CVMX_CIU_INTX_EN0(offset) \
40 CVMX_ADD_IO_SEG(0x0001070000000200ull + (((offset) & 63) * 16))
41#define CVMX_CIU_INTX_EN0_W1C(offset) \
42 CVMX_ADD_IO_SEG(0x0001070000002200ull + (((offset) & 63) * 16))
43#define CVMX_CIU_INTX_EN0_W1S(offset) \
44 CVMX_ADD_IO_SEG(0x0001070000006200ull + (((offset) & 63) * 16))
45#define CVMX_CIU_INTX_EN1(offset) \
46 CVMX_ADD_IO_SEG(0x0001070000000208ull + (((offset) & 63) * 16))
47#define CVMX_CIU_INTX_EN1_W1C(offset) \
48 CVMX_ADD_IO_SEG(0x0001070000002208ull + (((offset) & 63) * 16))
49#define CVMX_CIU_INTX_EN1_W1S(offset) \
50 CVMX_ADD_IO_SEG(0x0001070000006208ull + (((offset) & 63) * 16))
51#define CVMX_CIU_INTX_EN4_0(offset) \
52 CVMX_ADD_IO_SEG(0x0001070000000C80ull + (((offset) & 15) * 16))
53#define CVMX_CIU_INTX_EN4_0_W1C(offset) \
54 CVMX_ADD_IO_SEG(0x0001070000002C80ull + (((offset) & 15) * 16))
55#define CVMX_CIU_INTX_EN4_0_W1S(offset) \
56 CVMX_ADD_IO_SEG(0x0001070000006C80ull + (((offset) & 15) * 16))
57#define CVMX_CIU_INTX_EN4_1(offset) \
58 CVMX_ADD_IO_SEG(0x0001070000000C88ull + (((offset) & 15) * 16))
59#define CVMX_CIU_INTX_EN4_1_W1C(offset) \
60 CVMX_ADD_IO_SEG(0x0001070000002C88ull + (((offset) & 15) * 16))
61#define CVMX_CIU_INTX_EN4_1_W1S(offset) \
62 CVMX_ADD_IO_SEG(0x0001070000006C88ull + (((offset) & 15) * 16))
63#define CVMX_CIU_INTX_SUM0(offset) \
64 CVMX_ADD_IO_SEG(0x0001070000000000ull + (((offset) & 63) * 8))
65#define CVMX_CIU_INTX_SUM4(offset) \
66 CVMX_ADD_IO_SEG(0x0001070000000C00ull + (((offset) & 15) * 8))
67#define CVMX_CIU_INT_SUM1 \
68 CVMX_ADD_IO_SEG(0x0001070000000108ull)
69#define CVMX_CIU_MBOX_CLRX(offset) \
70 CVMX_ADD_IO_SEG(0x0001070000000680ull + (((offset) & 15) * 8))
71#define CVMX_CIU_MBOX_SETX(offset) \
72 CVMX_ADD_IO_SEG(0x0001070000000600ull + (((offset) & 15) * 8))
73#define CVMX_CIU_NMI \
74 CVMX_ADD_IO_SEG(0x0001070000000718ull)
75#define CVMX_CIU_PCI_INTA \
76 CVMX_ADD_IO_SEG(0x0001070000000750ull)
77#define CVMX_CIU_PP_DBG \
78 CVMX_ADD_IO_SEG(0x0001070000000708ull)
79#define CVMX_CIU_PP_POKEX(offset) \
80 CVMX_ADD_IO_SEG(0x0001070000000580ull + (((offset) & 15) * 8))
81#define CVMX_CIU_PP_RST \
82 CVMX_ADD_IO_SEG(0x0001070000000700ull)
83#define CVMX_CIU_QLM_DCOK \
84 CVMX_ADD_IO_SEG(0x0001070000000760ull)
85#define CVMX_CIU_QLM_JTGC \
86 CVMX_ADD_IO_SEG(0x0001070000000768ull)
87#define CVMX_CIU_QLM_JTGD \
88 CVMX_ADD_IO_SEG(0x0001070000000770ull)
89#define CVMX_CIU_SOFT_BIST \
90 CVMX_ADD_IO_SEG(0x0001070000000738ull)
91#define CVMX_CIU_SOFT_PRST \
92 CVMX_ADD_IO_SEG(0x0001070000000748ull)
93#define CVMX_CIU_SOFT_PRST1 \
94 CVMX_ADD_IO_SEG(0x0001070000000758ull)
95#define CVMX_CIU_SOFT_RST \
96 CVMX_ADD_IO_SEG(0x0001070000000740ull)
97#define CVMX_CIU_TIMX(offset) \
98 CVMX_ADD_IO_SEG(0x0001070000000480ull + (((offset) & 3) * 8))
99#define CVMX_CIU_WDOGX(offset) \
100 CVMX_ADD_IO_SEG(0x0001070000000500ull + (((offset) & 15) * 8))
101
102union cvmx_ciu_bist {
103 uint64_t u64;
104 struct cvmx_ciu_bist_s {
105 uint64_t reserved_4_63:60;
106 uint64_t bist:4;
107 } s;
108 struct cvmx_ciu_bist_s cn30xx;
109 struct cvmx_ciu_bist_s cn31xx;
110 struct cvmx_ciu_bist_s cn38xx;
111 struct cvmx_ciu_bist_s cn38xxp2;
112 struct cvmx_ciu_bist_cn50xx {
113 uint64_t reserved_2_63:62;
114 uint64_t bist:2;
115 } cn50xx;
116 struct cvmx_ciu_bist_cn52xx {
117 uint64_t reserved_3_63:61;
118 uint64_t bist:3;
119 } cn52xx;
120 struct cvmx_ciu_bist_cn52xx cn52xxp1;
121 struct cvmx_ciu_bist_s cn56xx;
122 struct cvmx_ciu_bist_s cn56xxp1;
123 struct cvmx_ciu_bist_s cn58xx;
124 struct cvmx_ciu_bist_s cn58xxp1;
125};
126
127union cvmx_ciu_dint {
128 uint64_t u64;
129 struct cvmx_ciu_dint_s {
130 uint64_t reserved_16_63:48;
131 uint64_t dint:16;
132 } s;
133 struct cvmx_ciu_dint_cn30xx {
134 uint64_t reserved_1_63:63;
135 uint64_t dint:1;
136 } cn30xx;
137 struct cvmx_ciu_dint_cn31xx {
138 uint64_t reserved_2_63:62;
139 uint64_t dint:2;
140 } cn31xx;
141 struct cvmx_ciu_dint_s cn38xx;
142 struct cvmx_ciu_dint_s cn38xxp2;
143 struct cvmx_ciu_dint_cn31xx cn50xx;
144 struct cvmx_ciu_dint_cn52xx {
145 uint64_t reserved_4_63:60;
146 uint64_t dint:4;
147 } cn52xx;
148 struct cvmx_ciu_dint_cn52xx cn52xxp1;
149 struct cvmx_ciu_dint_cn56xx {
150 uint64_t reserved_12_63:52;
151 uint64_t dint:12;
152 } cn56xx;
153 struct cvmx_ciu_dint_cn56xx cn56xxp1;
154 struct cvmx_ciu_dint_s cn58xx;
155 struct cvmx_ciu_dint_s cn58xxp1;
156};
157
158union cvmx_ciu_fuse {
159 uint64_t u64;
160 struct cvmx_ciu_fuse_s {
161 uint64_t reserved_16_63:48;
162 uint64_t fuse:16;
163 } s;
164 struct cvmx_ciu_fuse_cn30xx {
165 uint64_t reserved_1_63:63;
166 uint64_t fuse:1;
167 } cn30xx;
168 struct cvmx_ciu_fuse_cn31xx {
169 uint64_t reserved_2_63:62;
170 uint64_t fuse:2;
171 } cn31xx;
172 struct cvmx_ciu_fuse_s cn38xx;
173 struct cvmx_ciu_fuse_s cn38xxp2;
174 struct cvmx_ciu_fuse_cn31xx cn50xx;
175 struct cvmx_ciu_fuse_cn52xx {
176 uint64_t reserved_4_63:60;
177 uint64_t fuse:4;
178 } cn52xx;
179 struct cvmx_ciu_fuse_cn52xx cn52xxp1;
180 struct cvmx_ciu_fuse_cn56xx {
181 uint64_t reserved_12_63:52;
182 uint64_t fuse:12;
183 } cn56xx;
184 struct cvmx_ciu_fuse_cn56xx cn56xxp1;
185 struct cvmx_ciu_fuse_s cn58xx;
186 struct cvmx_ciu_fuse_s cn58xxp1;
187};
188
189union cvmx_ciu_gstop {
190 uint64_t u64;
191 struct cvmx_ciu_gstop_s {
192 uint64_t reserved_1_63:63;
193 uint64_t gstop:1;
194 } s;
195 struct cvmx_ciu_gstop_s cn30xx;
196 struct cvmx_ciu_gstop_s cn31xx;
197 struct cvmx_ciu_gstop_s cn38xx;
198 struct cvmx_ciu_gstop_s cn38xxp2;
199 struct cvmx_ciu_gstop_s cn50xx;
200 struct cvmx_ciu_gstop_s cn52xx;
201 struct cvmx_ciu_gstop_s cn52xxp1;
202 struct cvmx_ciu_gstop_s cn56xx;
203 struct cvmx_ciu_gstop_s cn56xxp1;
204 struct cvmx_ciu_gstop_s cn58xx;
205 struct cvmx_ciu_gstop_s cn58xxp1;
206};
207
208union cvmx_ciu_intx_en0 {
209 uint64_t u64;
210 struct cvmx_ciu_intx_en0_s {
211 uint64_t bootdma:1;
212 uint64_t mii:1;
213 uint64_t ipdppthr:1;
214 uint64_t powiq:1;
215 uint64_t twsi2:1;
216 uint64_t mpi:1;
217 uint64_t pcm:1;
218 uint64_t usb:1;
219 uint64_t timer:4;
220 uint64_t key_zero:1;
221 uint64_t ipd_drp:1;
222 uint64_t gmx_drp:2;
223 uint64_t trace:1;
224 uint64_t rml:1;
225 uint64_t twsi:1;
226 uint64_t reserved_44_44:1;
227 uint64_t pci_msi:4;
228 uint64_t pci_int:4;
229 uint64_t uart:2;
230 uint64_t mbox:2;
231 uint64_t gpio:16;
232 uint64_t workq:16;
233 } s;
234 struct cvmx_ciu_intx_en0_cn30xx {
235 uint64_t reserved_59_63:5;
236 uint64_t mpi:1;
237 uint64_t pcm:1;
238 uint64_t usb:1;
239 uint64_t timer:4;
240 uint64_t reserved_51_51:1;
241 uint64_t ipd_drp:1;
242 uint64_t reserved_49_49:1;
243 uint64_t gmx_drp:1;
244 uint64_t reserved_47_47:1;
245 uint64_t rml:1;
246 uint64_t twsi:1;
247 uint64_t reserved_44_44:1;
248 uint64_t pci_msi:4;
249 uint64_t pci_int:4;
250 uint64_t uart:2;
251 uint64_t mbox:2;
252 uint64_t gpio:16;
253 uint64_t workq:16;
254 } cn30xx;
255 struct cvmx_ciu_intx_en0_cn31xx {
256 uint64_t reserved_59_63:5;
257 uint64_t mpi:1;
258 uint64_t pcm:1;
259 uint64_t usb:1;
260 uint64_t timer:4;
261 uint64_t reserved_51_51:1;
262 uint64_t ipd_drp:1;
263 uint64_t reserved_49_49:1;
264 uint64_t gmx_drp:1;
265 uint64_t trace:1;
266 uint64_t rml:1;
267 uint64_t twsi:1;
268 uint64_t reserved_44_44:1;
269 uint64_t pci_msi:4;
270 uint64_t pci_int:4;
271 uint64_t uart:2;
272 uint64_t mbox:2;
273 uint64_t gpio:16;
274 uint64_t workq:16;
275 } cn31xx;
276 struct cvmx_ciu_intx_en0_cn38xx {
277 uint64_t reserved_56_63:8;
278 uint64_t timer:4;
279 uint64_t key_zero:1;
280 uint64_t ipd_drp:1;
281 uint64_t gmx_drp:2;
282 uint64_t trace:1;
283 uint64_t rml:1;
284 uint64_t twsi:1;
285 uint64_t reserved_44_44:1;
286 uint64_t pci_msi:4;
287 uint64_t pci_int:4;
288 uint64_t uart:2;
289 uint64_t mbox:2;
290 uint64_t gpio:16;
291 uint64_t workq:16;
292 } cn38xx;
293 struct cvmx_ciu_intx_en0_cn38xx cn38xxp2;
294 struct cvmx_ciu_intx_en0_cn30xx cn50xx;
295 struct cvmx_ciu_intx_en0_cn52xx {
296 uint64_t bootdma:1;
297 uint64_t mii:1;
298 uint64_t ipdppthr:1;
299 uint64_t powiq:1;
300 uint64_t twsi2:1;
301 uint64_t reserved_57_58:2;
302 uint64_t usb:1;
303 uint64_t timer:4;
304 uint64_t reserved_51_51:1;
305 uint64_t ipd_drp:1;
306 uint64_t reserved_49_49:1;
307 uint64_t gmx_drp:1;
308 uint64_t trace:1;
309 uint64_t rml:1;
310 uint64_t twsi:1;
311 uint64_t reserved_44_44:1;
312 uint64_t pci_msi:4;
313 uint64_t pci_int:4;
314 uint64_t uart:2;
315 uint64_t mbox:2;
316 uint64_t gpio:16;
317 uint64_t workq:16;
318 } cn52xx;
319 struct cvmx_ciu_intx_en0_cn52xx cn52xxp1;
320 struct cvmx_ciu_intx_en0_cn56xx {
321 uint64_t bootdma:1;
322 uint64_t mii:1;
323 uint64_t ipdppthr:1;
324 uint64_t powiq:1;
325 uint64_t twsi2:1;
326 uint64_t reserved_57_58:2;
327 uint64_t usb:1;
328 uint64_t timer:4;
329 uint64_t key_zero:1;
330 uint64_t ipd_drp:1;
331 uint64_t gmx_drp:2;
332 uint64_t trace:1;
333 uint64_t rml:1;
334 uint64_t twsi:1;
335 uint64_t reserved_44_44:1;
336 uint64_t pci_msi:4;
337 uint64_t pci_int:4;
338 uint64_t uart:2;
339 uint64_t mbox:2;
340 uint64_t gpio:16;
341 uint64_t workq:16;
342 } cn56xx;
343 struct cvmx_ciu_intx_en0_cn56xx cn56xxp1;
344 struct cvmx_ciu_intx_en0_cn38xx cn58xx;
345 struct cvmx_ciu_intx_en0_cn38xx cn58xxp1;
346};
347
348union cvmx_ciu_intx_en0_w1c {
349 uint64_t u64;
350 struct cvmx_ciu_intx_en0_w1c_s {
351 uint64_t bootdma:1;
352 uint64_t mii:1;
353 uint64_t ipdppthr:1;
354 uint64_t powiq:1;
355 uint64_t twsi2:1;
356 uint64_t reserved_57_58:2;
357 uint64_t usb:1;
358 uint64_t timer:4;
359 uint64_t key_zero:1;
360 uint64_t ipd_drp:1;
361 uint64_t gmx_drp:2;
362 uint64_t trace:1;
363 uint64_t rml:1;
364 uint64_t twsi:1;
365 uint64_t reserved_44_44:1;
366 uint64_t pci_msi:4;
367 uint64_t pci_int:4;
368 uint64_t uart:2;
369 uint64_t mbox:2;
370 uint64_t gpio:16;
371 uint64_t workq:16;
372 } s;
373 struct cvmx_ciu_intx_en0_w1c_cn52xx {
374 uint64_t bootdma:1;
375 uint64_t mii:1;
376 uint64_t ipdppthr:1;
377 uint64_t powiq:1;
378 uint64_t twsi2:1;
379 uint64_t reserved_57_58:2;
380 uint64_t usb:1;
381 uint64_t timer:4;
382 uint64_t reserved_51_51:1;
383 uint64_t ipd_drp:1;
384 uint64_t reserved_49_49:1;
385 uint64_t gmx_drp:1;
386 uint64_t trace:1;
387 uint64_t rml:1;
388 uint64_t twsi:1;
389 uint64_t reserved_44_44:1;
390 uint64_t pci_msi:4;
391 uint64_t pci_int:4;
392 uint64_t uart:2;
393 uint64_t mbox:2;
394 uint64_t gpio:16;
395 uint64_t workq:16;
396 } cn52xx;
397 struct cvmx_ciu_intx_en0_w1c_s cn56xx;
398 struct cvmx_ciu_intx_en0_w1c_cn58xx {
399 uint64_t reserved_56_63:8;
400 uint64_t timer:4;
401 uint64_t key_zero:1;
402 uint64_t ipd_drp:1;
403 uint64_t gmx_drp:2;
404 uint64_t trace:1;
405 uint64_t rml:1;
406 uint64_t twsi:1;
407 uint64_t reserved_44_44:1;
408 uint64_t pci_msi:4;
409 uint64_t pci_int:4;
410 uint64_t uart:2;
411 uint64_t mbox:2;
412 uint64_t gpio:16;
413 uint64_t workq:16;
414 } cn58xx;
415};
416
417union cvmx_ciu_intx_en0_w1s {
418 uint64_t u64;
419 struct cvmx_ciu_intx_en0_w1s_s {
420 uint64_t bootdma:1;
421 uint64_t mii:1;
422 uint64_t ipdppthr:1;
423 uint64_t powiq:1;
424 uint64_t twsi2:1;
425 uint64_t reserved_57_58:2;
426 uint64_t usb:1;
427 uint64_t timer:4;
428 uint64_t key_zero:1;
429 uint64_t ipd_drp:1;
430 uint64_t gmx_drp:2;
431 uint64_t trace:1;
432 uint64_t rml:1;
433 uint64_t twsi:1;
434 uint64_t reserved_44_44:1;
435 uint64_t pci_msi:4;
436 uint64_t pci_int:4;
437 uint64_t uart:2;
438 uint64_t mbox:2;
439 uint64_t gpio:16;
440 uint64_t workq:16;
441 } s;
442 struct cvmx_ciu_intx_en0_w1s_cn52xx {
443 uint64_t bootdma:1;
444 uint64_t mii:1;
445 uint64_t ipdppthr:1;
446 uint64_t powiq:1;
447 uint64_t twsi2:1;
448 uint64_t reserved_57_58:2;
449 uint64_t usb:1;
450 uint64_t timer:4;
451 uint64_t reserved_51_51:1;
452 uint64_t ipd_drp:1;
453 uint64_t reserved_49_49:1;
454 uint64_t gmx_drp:1;
455 uint64_t trace:1;
456 uint64_t rml:1;
457 uint64_t twsi:1;
458 uint64_t reserved_44_44:1;
459 uint64_t pci_msi:4;
460 uint64_t pci_int:4;
461 uint64_t uart:2;
462 uint64_t mbox:2;
463 uint64_t gpio:16;
464 uint64_t workq:16;
465 } cn52xx;
466 struct cvmx_ciu_intx_en0_w1s_s cn56xx;
467 struct cvmx_ciu_intx_en0_w1s_cn58xx {
468 uint64_t reserved_56_63:8;
469 uint64_t timer:4;
470 uint64_t key_zero:1;
471 uint64_t ipd_drp:1;
472 uint64_t gmx_drp:2;
473 uint64_t trace:1;
474 uint64_t rml:1;
475 uint64_t twsi:1;
476 uint64_t reserved_44_44:1;
477 uint64_t pci_msi:4;
478 uint64_t pci_int:4;
479 uint64_t uart:2;
480 uint64_t mbox:2;
481 uint64_t gpio:16;
482 uint64_t workq:16;
483 } cn58xx;
484};
485
486union cvmx_ciu_intx_en1 {
487 uint64_t u64;
488 struct cvmx_ciu_intx_en1_s {
489 uint64_t reserved_20_63:44;
490 uint64_t nand:1;
491 uint64_t mii1:1;
492 uint64_t usb1:1;
493 uint64_t uart2:1;
494 uint64_t wdog:16;
495 } s;
496 struct cvmx_ciu_intx_en1_cn30xx {
497 uint64_t reserved_1_63:63;
498 uint64_t wdog:1;
499 } cn30xx;
500 struct cvmx_ciu_intx_en1_cn31xx {
501 uint64_t reserved_2_63:62;
502 uint64_t wdog:2;
503 } cn31xx;
504 struct cvmx_ciu_intx_en1_cn38xx {
505 uint64_t reserved_16_63:48;
506 uint64_t wdog:16;
507 } cn38xx;
508 struct cvmx_ciu_intx_en1_cn38xx cn38xxp2;
509 struct cvmx_ciu_intx_en1_cn31xx cn50xx;
510 struct cvmx_ciu_intx_en1_cn52xx {
511 uint64_t reserved_20_63:44;
512 uint64_t nand:1;
513 uint64_t mii1:1;
514 uint64_t usb1:1;
515 uint64_t uart2:1;
516 uint64_t reserved_4_15:12;
517 uint64_t wdog:4;
518 } cn52xx;
519 struct cvmx_ciu_intx_en1_cn52xxp1 {
520 uint64_t reserved_19_63:45;
521 uint64_t mii1:1;
522 uint64_t usb1:1;
523 uint64_t uart2:1;
524 uint64_t reserved_4_15:12;
525 uint64_t wdog:4;
526 } cn52xxp1;
527 struct cvmx_ciu_intx_en1_cn56xx {
528 uint64_t reserved_12_63:52;
529 uint64_t wdog:12;
530 } cn56xx;
531 struct cvmx_ciu_intx_en1_cn56xx cn56xxp1;
532 struct cvmx_ciu_intx_en1_cn38xx cn58xx;
533 struct cvmx_ciu_intx_en1_cn38xx cn58xxp1;
534};
535
536union cvmx_ciu_intx_en1_w1c {
537 uint64_t u64;
538 struct cvmx_ciu_intx_en1_w1c_s {
539 uint64_t reserved_20_63:44;
540 uint64_t nand:1;
541 uint64_t mii1:1;
542 uint64_t usb1:1;
543 uint64_t uart2:1;
544 uint64_t wdog:16;
545 } s;
546 struct cvmx_ciu_intx_en1_w1c_cn52xx {
547 uint64_t reserved_20_63:44;
548 uint64_t nand:1;
549 uint64_t mii1:1;
550 uint64_t usb1:1;
551 uint64_t uart2:1;
552 uint64_t reserved_4_15:12;
553 uint64_t wdog:4;
554 } cn52xx;
555 struct cvmx_ciu_intx_en1_w1c_cn56xx {
556 uint64_t reserved_12_63:52;
557 uint64_t wdog:12;
558 } cn56xx;
559 struct cvmx_ciu_intx_en1_w1c_cn58xx {
560 uint64_t reserved_16_63:48;
561 uint64_t wdog:16;
562 } cn58xx;
563};
564
565union cvmx_ciu_intx_en1_w1s {
566 uint64_t u64;
567 struct cvmx_ciu_intx_en1_w1s_s {
568 uint64_t reserved_20_63:44;
569 uint64_t nand:1;
570 uint64_t mii1:1;
571 uint64_t usb1:1;
572 uint64_t uart2:1;
573 uint64_t wdog:16;
574 } s;
575 struct cvmx_ciu_intx_en1_w1s_cn52xx {
576 uint64_t reserved_20_63:44;
577 uint64_t nand:1;
578 uint64_t mii1:1;
579 uint64_t usb1:1;
580 uint64_t uart2:1;
581 uint64_t reserved_4_15:12;
582 uint64_t wdog:4;
583 } cn52xx;
584 struct cvmx_ciu_intx_en1_w1s_cn56xx {
585 uint64_t reserved_12_63:52;
586 uint64_t wdog:12;
587 } cn56xx;
588 struct cvmx_ciu_intx_en1_w1s_cn58xx {
589 uint64_t reserved_16_63:48;
590 uint64_t wdog:16;
591 } cn58xx;
592};
593
594union cvmx_ciu_intx_en4_0 {
595 uint64_t u64;
596 struct cvmx_ciu_intx_en4_0_s {
597 uint64_t bootdma:1;
598 uint64_t mii:1;
599 uint64_t ipdppthr:1;
600 uint64_t powiq:1;
601 uint64_t twsi2:1;
602 uint64_t mpi:1;
603 uint64_t pcm:1;
604 uint64_t usb:1;
605 uint64_t timer:4;
606 uint64_t key_zero:1;
607 uint64_t ipd_drp:1;
608 uint64_t gmx_drp:2;
609 uint64_t trace:1;
610 uint64_t rml:1;
611 uint64_t twsi:1;
612 uint64_t reserved_44_44:1;
613 uint64_t pci_msi:4;
614 uint64_t pci_int:4;
615 uint64_t uart:2;
616 uint64_t mbox:2;
617 uint64_t gpio:16;
618 uint64_t workq:16;
619 } s;
620 struct cvmx_ciu_intx_en4_0_cn50xx {
621 uint64_t reserved_59_63:5;
622 uint64_t mpi:1;
623 uint64_t pcm:1;
624 uint64_t usb:1;
625 uint64_t timer:4;
626 uint64_t reserved_51_51:1;
627 uint64_t ipd_drp:1;
628 uint64_t reserved_49_49:1;
629 uint64_t gmx_drp:1;
630 uint64_t reserved_47_47:1;
631 uint64_t rml:1;
632 uint64_t twsi:1;
633 uint64_t reserved_44_44:1;
634 uint64_t pci_msi:4;
635 uint64_t pci_int:4;
636 uint64_t uart:2;
637 uint64_t mbox:2;
638 uint64_t gpio:16;
639 uint64_t workq:16;
640 } cn50xx;
641 struct cvmx_ciu_intx_en4_0_cn52xx {
642 uint64_t bootdma:1;
643 uint64_t mii:1;
644 uint64_t ipdppthr:1;
645 uint64_t powiq:1;
646 uint64_t twsi2:1;
647 uint64_t reserved_57_58:2;
648 uint64_t usb:1;
649 uint64_t timer:4;
650 uint64_t reserved_51_51:1;
651 uint64_t ipd_drp:1;
652 uint64_t reserved_49_49:1;
653 uint64_t gmx_drp:1;
654 uint64_t trace:1;
655 uint64_t rml:1;
656 uint64_t twsi:1;
657 uint64_t reserved_44_44:1;
658 uint64_t pci_msi:4;
659 uint64_t pci_int:4;
660 uint64_t uart:2;
661 uint64_t mbox:2;
662 uint64_t gpio:16;
663 uint64_t workq:16;
664 } cn52xx;
665 struct cvmx_ciu_intx_en4_0_cn52xx cn52xxp1;
666 struct cvmx_ciu_intx_en4_0_cn56xx {
667 uint64_t bootdma:1;
668 uint64_t mii:1;
669 uint64_t ipdppthr:1;
670 uint64_t powiq:1;
671 uint64_t twsi2:1;
672 uint64_t reserved_57_58:2;
673 uint64_t usb:1;
674 uint64_t timer:4;
675 uint64_t key_zero:1;
676 uint64_t ipd_drp:1;
677 uint64_t gmx_drp:2;
678 uint64_t trace:1;
679 uint64_t rml:1;
680 uint64_t twsi:1;
681 uint64_t reserved_44_44:1;
682 uint64_t pci_msi:4;
683 uint64_t pci_int:4;
684 uint64_t uart:2;
685 uint64_t mbox:2;
686 uint64_t gpio:16;
687 uint64_t workq:16;
688 } cn56xx;
689 struct cvmx_ciu_intx_en4_0_cn56xx cn56xxp1;
690 struct cvmx_ciu_intx_en4_0_cn58xx {
691 uint64_t reserved_56_63:8;
692 uint64_t timer:4;
693 uint64_t key_zero:1;
694 uint64_t ipd_drp:1;
695 uint64_t gmx_drp:2;
696 uint64_t trace:1;
697 uint64_t rml:1;
698 uint64_t twsi:1;
699 uint64_t reserved_44_44:1;
700 uint64_t pci_msi:4;
701 uint64_t pci_int:4;
702 uint64_t uart:2;
703 uint64_t mbox:2;
704 uint64_t gpio:16;
705 uint64_t workq:16;
706 } cn58xx;
707 struct cvmx_ciu_intx_en4_0_cn58xx cn58xxp1;
708};
709
710union cvmx_ciu_intx_en4_0_w1c {
711 uint64_t u64;
712 struct cvmx_ciu_intx_en4_0_w1c_s {
713 uint64_t bootdma:1;
714 uint64_t mii:1;
715 uint64_t ipdppthr:1;
716 uint64_t powiq:1;
717 uint64_t twsi2:1;
718 uint64_t reserved_57_58:2;
719 uint64_t usb:1;
720 uint64_t timer:4;
721 uint64_t key_zero:1;
722 uint64_t ipd_drp:1;
723 uint64_t gmx_drp:2;
724 uint64_t trace:1;
725 uint64_t rml:1;
726 uint64_t twsi:1;
727 uint64_t reserved_44_44:1;
728 uint64_t pci_msi:4;
729 uint64_t pci_int:4;
730 uint64_t uart:2;
731 uint64_t mbox:2;
732 uint64_t gpio:16;
733 uint64_t workq:16;
734 } s;
735 struct cvmx_ciu_intx_en4_0_w1c_cn52xx {
736 uint64_t bootdma:1;
737 uint64_t mii:1;
738 uint64_t ipdppthr:1;
739 uint64_t powiq:1;
740 uint64_t twsi2:1;
741 uint64_t reserved_57_58:2;
742 uint64_t usb:1;
743 uint64_t timer:4;
744 uint64_t reserved_51_51:1;
745 uint64_t ipd_drp:1;
746 uint64_t reserved_49_49:1;
747 uint64_t gmx_drp:1;
748 uint64_t trace:1;
749 uint64_t rml:1;
750 uint64_t twsi:1;
751 uint64_t reserved_44_44:1;
752 uint64_t pci_msi:4;
753 uint64_t pci_int:4;
754 uint64_t uart:2;
755 uint64_t mbox:2;
756 uint64_t gpio:16;
757 uint64_t workq:16;
758 } cn52xx;
759 struct cvmx_ciu_intx_en4_0_w1c_s cn56xx;
760 struct cvmx_ciu_intx_en4_0_w1c_cn58xx {
761 uint64_t reserved_56_63:8;
762 uint64_t timer:4;
763 uint64_t key_zero:1;
764 uint64_t ipd_drp:1;
765 uint64_t gmx_drp:2;
766 uint64_t trace:1;
767 uint64_t rml:1;
768 uint64_t twsi:1;
769 uint64_t reserved_44_44:1;
770 uint64_t pci_msi:4;
771 uint64_t pci_int:4;
772 uint64_t uart:2;
773 uint64_t mbox:2;
774 uint64_t gpio:16;
775 uint64_t workq:16;
776 } cn58xx;
777};
778
779union cvmx_ciu_intx_en4_0_w1s {
780 uint64_t u64;
781 struct cvmx_ciu_intx_en4_0_w1s_s {
782 uint64_t bootdma:1;
783 uint64_t mii:1;
784 uint64_t ipdppthr:1;
785 uint64_t powiq:1;
786 uint64_t twsi2:1;
787 uint64_t reserved_57_58:2;
788 uint64_t usb:1;
789 uint64_t timer:4;
790 uint64_t key_zero:1;
791 uint64_t ipd_drp:1;
792 uint64_t gmx_drp:2;
793 uint64_t trace:1;
794 uint64_t rml:1;
795 uint64_t twsi:1;
796 uint64_t reserved_44_44:1;
797 uint64_t pci_msi:4;
798 uint64_t pci_int:4;
799 uint64_t uart:2;
800 uint64_t mbox:2;
801 uint64_t gpio:16;
802 uint64_t workq:16;
803 } s;
804 struct cvmx_ciu_intx_en4_0_w1s_cn52xx {
805 uint64_t bootdma:1;
806 uint64_t mii:1;
807 uint64_t ipdppthr:1;
808 uint64_t powiq:1;
809 uint64_t twsi2:1;
810 uint64_t reserved_57_58:2;
811 uint64_t usb:1;
812 uint64_t timer:4;
813 uint64_t reserved_51_51:1;
814 uint64_t ipd_drp:1;
815 uint64_t reserved_49_49:1;
816 uint64_t gmx_drp:1;
817 uint64_t trace:1;
818 uint64_t rml:1;
819 uint64_t twsi:1;
820 uint64_t reserved_44_44:1;
821 uint64_t pci_msi:4;
822 uint64_t pci_int:4;
823 uint64_t uart:2;
824 uint64_t mbox:2;
825 uint64_t gpio:16;
826 uint64_t workq:16;
827 } cn52xx;
828 struct cvmx_ciu_intx_en4_0_w1s_s cn56xx;
829 struct cvmx_ciu_intx_en4_0_w1s_cn58xx {
830 uint64_t reserved_56_63:8;
831 uint64_t timer:4;
832 uint64_t key_zero:1;
833 uint64_t ipd_drp:1;
834 uint64_t gmx_drp:2;
835 uint64_t trace:1;
836 uint64_t rml:1;
837 uint64_t twsi:1;
838 uint64_t reserved_44_44:1;
839 uint64_t pci_msi:4;
840 uint64_t pci_int:4;
841 uint64_t uart:2;
842 uint64_t mbox:2;
843 uint64_t gpio:16;
844 uint64_t workq:16;
845 } cn58xx;
846};
847
848union cvmx_ciu_intx_en4_1 {
849 uint64_t u64;
850 struct cvmx_ciu_intx_en4_1_s {
851 uint64_t reserved_20_63:44;
852 uint64_t nand:1;
853 uint64_t mii1:1;
854 uint64_t usb1:1;
855 uint64_t uart2:1;
856 uint64_t wdog:16;
857 } s;
858 struct cvmx_ciu_intx_en4_1_cn50xx {
859 uint64_t reserved_2_63:62;
860 uint64_t wdog:2;
861 } cn50xx;
862 struct cvmx_ciu_intx_en4_1_cn52xx {
863 uint64_t reserved_20_63:44;
864 uint64_t nand:1;
865 uint64_t mii1:1;
866 uint64_t usb1:1;
867 uint64_t uart2:1;
868 uint64_t reserved_4_15:12;
869 uint64_t wdog:4;
870 } cn52xx;
871 struct cvmx_ciu_intx_en4_1_cn52xxp1 {
872 uint64_t reserved_19_63:45;
873 uint64_t mii1:1;
874 uint64_t usb1:1;
875 uint64_t uart2:1;
876 uint64_t reserved_4_15:12;
877 uint64_t wdog:4;
878 } cn52xxp1;
879 struct cvmx_ciu_intx_en4_1_cn56xx {
880 uint64_t reserved_12_63:52;
881 uint64_t wdog:12;
882 } cn56xx;
883 struct cvmx_ciu_intx_en4_1_cn56xx cn56xxp1;
884 struct cvmx_ciu_intx_en4_1_cn58xx {
885 uint64_t reserved_16_63:48;
886 uint64_t wdog:16;
887 } cn58xx;
888 struct cvmx_ciu_intx_en4_1_cn58xx cn58xxp1;
889};
890
891union cvmx_ciu_intx_en4_1_w1c {
892 uint64_t u64;
893 struct cvmx_ciu_intx_en4_1_w1c_s {
894 uint64_t reserved_20_63:44;
895 uint64_t nand:1;
896 uint64_t mii1:1;
897 uint64_t usb1:1;
898 uint64_t uart2:1;
899 uint64_t wdog:16;
900 } s;
901 struct cvmx_ciu_intx_en4_1_w1c_cn52xx {
902 uint64_t reserved_20_63:44;
903 uint64_t nand:1;
904 uint64_t mii1:1;
905 uint64_t usb1:1;
906 uint64_t uart2:1;
907 uint64_t reserved_4_15:12;
908 uint64_t wdog:4;
909 } cn52xx;
910 struct cvmx_ciu_intx_en4_1_w1c_cn56xx {
911 uint64_t reserved_12_63:52;
912 uint64_t wdog:12;
913 } cn56xx;
914 struct cvmx_ciu_intx_en4_1_w1c_cn58xx {
915 uint64_t reserved_16_63:48;
916 uint64_t wdog:16;
917 } cn58xx;
918};
919
920union cvmx_ciu_intx_en4_1_w1s {
921 uint64_t u64;
922 struct cvmx_ciu_intx_en4_1_w1s_s {
923 uint64_t reserved_20_63:44;
924 uint64_t nand:1;
925 uint64_t mii1:1;
926 uint64_t usb1:1;
927 uint64_t uart2:1;
928 uint64_t wdog:16;
929 } s;
930 struct cvmx_ciu_intx_en4_1_w1s_cn52xx {
931 uint64_t reserved_20_63:44;
932 uint64_t nand:1;
933 uint64_t mii1:1;
934 uint64_t usb1:1;
935 uint64_t uart2:1;
936 uint64_t reserved_4_15:12;
937 uint64_t wdog:4;
938 } cn52xx;
939 struct cvmx_ciu_intx_en4_1_w1s_cn56xx {
940 uint64_t reserved_12_63:52;
941 uint64_t wdog:12;
942 } cn56xx;
943 struct cvmx_ciu_intx_en4_1_w1s_cn58xx {
944 uint64_t reserved_16_63:48;
945 uint64_t wdog:16;
946 } cn58xx;
947};
948
949union cvmx_ciu_intx_sum0 {
950 uint64_t u64;
951 struct cvmx_ciu_intx_sum0_s {
952 uint64_t bootdma:1;
953 uint64_t mii:1;
954 uint64_t ipdppthr:1;
955 uint64_t powiq:1;
956 uint64_t twsi2:1;
957 uint64_t mpi:1;
958 uint64_t pcm:1;
959 uint64_t usb:1;
960 uint64_t timer:4;
961 uint64_t key_zero:1;
962 uint64_t ipd_drp:1;
963 uint64_t gmx_drp:2;
964 uint64_t trace:1;
965 uint64_t rml:1;
966 uint64_t twsi:1;
967 uint64_t wdog_sum:1;
968 uint64_t pci_msi:4;
969 uint64_t pci_int:4;
970 uint64_t uart:2;
971 uint64_t mbox:2;
972 uint64_t gpio:16;
973 uint64_t workq:16;
974 } s;
975 struct cvmx_ciu_intx_sum0_cn30xx {
976 uint64_t reserved_59_63:5;
977 uint64_t mpi:1;
978 uint64_t pcm:1;
979 uint64_t usb:1;
980 uint64_t timer:4;
981 uint64_t reserved_51_51:1;
982 uint64_t ipd_drp:1;
983 uint64_t reserved_49_49:1;
984 uint64_t gmx_drp:1;
985 uint64_t reserved_47_47:1;
986 uint64_t rml:1;
987 uint64_t twsi:1;
988 uint64_t wdog_sum:1;
989 uint64_t pci_msi:4;
990 uint64_t pci_int:4;
991 uint64_t uart:2;
992 uint64_t mbox:2;
993 uint64_t gpio:16;
994 uint64_t workq:16;
995 } cn30xx;
996 struct cvmx_ciu_intx_sum0_cn31xx {
997 uint64_t reserved_59_63:5;
998 uint64_t mpi:1;
999 uint64_t pcm:1;
1000 uint64_t usb:1;
1001 uint64_t timer:4;
1002 uint64_t reserved_51_51:1;
1003 uint64_t ipd_drp:1;
1004 uint64_t reserved_49_49:1;
1005 uint64_t gmx_drp:1;
1006 uint64_t trace:1;
1007 uint64_t rml:1;
1008 uint64_t twsi:1;
1009 uint64_t wdog_sum:1;
1010 uint64_t pci_msi:4;
1011 uint64_t pci_int:4;
1012 uint64_t uart:2;
1013 uint64_t mbox:2;
1014 uint64_t gpio:16;
1015 uint64_t workq:16;
1016 } cn31xx;
1017 struct cvmx_ciu_intx_sum0_cn38xx {
1018 uint64_t reserved_56_63:8;
1019 uint64_t timer:4;
1020 uint64_t key_zero:1;
1021 uint64_t ipd_drp:1;
1022 uint64_t gmx_drp:2;
1023 uint64_t trace:1;
1024 uint64_t rml:1;
1025 uint64_t twsi:1;
1026 uint64_t wdog_sum:1;
1027 uint64_t pci_msi:4;
1028 uint64_t pci_int:4;
1029 uint64_t uart:2;
1030 uint64_t mbox:2;
1031 uint64_t gpio:16;
1032 uint64_t workq:16;
1033 } cn38xx;
1034 struct cvmx_ciu_intx_sum0_cn38xx cn38xxp2;
1035 struct cvmx_ciu_intx_sum0_cn30xx cn50xx;
1036 struct cvmx_ciu_intx_sum0_cn52xx {
1037 uint64_t bootdma:1;
1038 uint64_t mii:1;
1039 uint64_t ipdppthr:1;
1040 uint64_t powiq:1;
1041 uint64_t twsi2:1;
1042 uint64_t reserved_57_58:2;
1043 uint64_t usb:1;
1044 uint64_t timer:4;
1045 uint64_t reserved_51_51:1;
1046 uint64_t ipd_drp:1;
1047 uint64_t reserved_49_49:1;
1048 uint64_t gmx_drp:1;
1049 uint64_t trace:1;
1050 uint64_t rml:1;
1051 uint64_t twsi:1;
1052 uint64_t wdog_sum:1;
1053 uint64_t pci_msi:4;
1054 uint64_t pci_int:4;
1055 uint64_t uart:2;
1056 uint64_t mbox:2;
1057 uint64_t gpio:16;
1058 uint64_t workq:16;
1059 } cn52xx;
1060 struct cvmx_ciu_intx_sum0_cn52xx cn52xxp1;
1061 struct cvmx_ciu_intx_sum0_cn56xx {
1062 uint64_t bootdma:1;
1063 uint64_t mii:1;
1064 uint64_t ipdppthr:1;
1065 uint64_t powiq:1;
1066 uint64_t twsi2:1;
1067 uint64_t reserved_57_58:2;
1068 uint64_t usb:1;
1069 uint64_t timer:4;
1070 uint64_t key_zero:1;
1071 uint64_t ipd_drp:1;
1072 uint64_t gmx_drp:2;
1073 uint64_t trace:1;
1074 uint64_t rml:1;
1075 uint64_t twsi:1;
1076 uint64_t wdog_sum:1;
1077 uint64_t pci_msi:4;
1078 uint64_t pci_int:4;
1079 uint64_t uart:2;
1080 uint64_t mbox:2;
1081 uint64_t gpio:16;
1082 uint64_t workq:16;
1083 } cn56xx;
1084 struct cvmx_ciu_intx_sum0_cn56xx cn56xxp1;
1085 struct cvmx_ciu_intx_sum0_cn38xx cn58xx;
1086 struct cvmx_ciu_intx_sum0_cn38xx cn58xxp1;
1087};
1088
1089union cvmx_ciu_intx_sum4 {
1090 uint64_t u64;
1091 struct cvmx_ciu_intx_sum4_s {
1092 uint64_t bootdma:1;
1093 uint64_t mii:1;
1094 uint64_t ipdppthr:1;
1095 uint64_t powiq:1;
1096 uint64_t twsi2:1;
1097 uint64_t mpi:1;
1098 uint64_t pcm:1;
1099 uint64_t usb:1;
1100 uint64_t timer:4;
1101 uint64_t key_zero:1;
1102 uint64_t ipd_drp:1;
1103 uint64_t gmx_drp:2;
1104 uint64_t trace:1;
1105 uint64_t rml:1;
1106 uint64_t twsi:1;
1107 uint64_t wdog_sum:1;
1108 uint64_t pci_msi:4;
1109 uint64_t pci_int:4;
1110 uint64_t uart:2;
1111 uint64_t mbox:2;
1112 uint64_t gpio:16;
1113 uint64_t workq:16;
1114 } s;
1115 struct cvmx_ciu_intx_sum4_cn50xx {
1116 uint64_t reserved_59_63:5;
1117 uint64_t mpi:1;
1118 uint64_t pcm:1;
1119 uint64_t usb:1;
1120 uint64_t timer:4;
1121 uint64_t reserved_51_51:1;
1122 uint64_t ipd_drp:1;
1123 uint64_t reserved_49_49:1;
1124 uint64_t gmx_drp:1;
1125 uint64_t reserved_47_47:1;
1126 uint64_t rml:1;
1127 uint64_t twsi:1;
1128 uint64_t wdog_sum:1;
1129 uint64_t pci_msi:4;
1130 uint64_t pci_int:4;
1131 uint64_t uart:2;
1132 uint64_t mbox:2;
1133 uint64_t gpio:16;
1134 uint64_t workq:16;
1135 } cn50xx;
1136 struct cvmx_ciu_intx_sum4_cn52xx {
1137 uint64_t bootdma:1;
1138 uint64_t mii:1;
1139 uint64_t ipdppthr:1;
1140 uint64_t powiq:1;
1141 uint64_t twsi2:1;
1142 uint64_t reserved_57_58:2;
1143 uint64_t usb:1;
1144 uint64_t timer:4;
1145 uint64_t reserved_51_51:1;
1146 uint64_t ipd_drp:1;
1147 uint64_t reserved_49_49:1;
1148 uint64_t gmx_drp:1;
1149 uint64_t trace:1;
1150 uint64_t rml:1;
1151 uint64_t twsi:1;
1152 uint64_t wdog_sum:1;
1153 uint64_t pci_msi:4;
1154 uint64_t pci_int:4;
1155 uint64_t uart:2;
1156 uint64_t mbox:2;
1157 uint64_t gpio:16;
1158 uint64_t workq:16;
1159 } cn52xx;
1160 struct cvmx_ciu_intx_sum4_cn52xx cn52xxp1;
1161 struct cvmx_ciu_intx_sum4_cn56xx {
1162 uint64_t bootdma:1;
1163 uint64_t mii:1;
1164 uint64_t ipdppthr:1;
1165 uint64_t powiq:1;
1166 uint64_t twsi2:1;
1167 uint64_t reserved_57_58:2;
1168 uint64_t usb:1;
1169 uint64_t timer:4;
1170 uint64_t key_zero:1;
1171 uint64_t ipd_drp:1;
1172 uint64_t gmx_drp:2;
1173 uint64_t trace:1;
1174 uint64_t rml:1;
1175 uint64_t twsi:1;
1176 uint64_t wdog_sum:1;
1177 uint64_t pci_msi:4;
1178 uint64_t pci_int:4;
1179 uint64_t uart:2;
1180 uint64_t mbox:2;
1181 uint64_t gpio:16;
1182 uint64_t workq:16;
1183 } cn56xx;
1184 struct cvmx_ciu_intx_sum4_cn56xx cn56xxp1;
1185 struct cvmx_ciu_intx_sum4_cn58xx {
1186 uint64_t reserved_56_63:8;
1187 uint64_t timer:4;
1188 uint64_t key_zero:1;
1189 uint64_t ipd_drp:1;
1190 uint64_t gmx_drp:2;
1191 uint64_t trace:1;
1192 uint64_t rml:1;
1193 uint64_t twsi:1;
1194 uint64_t wdog_sum:1;
1195 uint64_t pci_msi:4;
1196 uint64_t pci_int:4;
1197 uint64_t uart:2;
1198 uint64_t mbox:2;
1199 uint64_t gpio:16;
1200 uint64_t workq:16;
1201 } cn58xx;
1202 struct cvmx_ciu_intx_sum4_cn58xx cn58xxp1;
1203};
1204
1205union cvmx_ciu_int_sum1 {
1206 uint64_t u64;
1207 struct cvmx_ciu_int_sum1_s {
1208 uint64_t reserved_20_63:44;
1209 uint64_t nand:1;
1210 uint64_t mii1:1;
1211 uint64_t usb1:1;
1212 uint64_t uart2:1;
1213 uint64_t wdog:16;
1214 } s;
1215 struct cvmx_ciu_int_sum1_cn30xx {
1216 uint64_t reserved_1_63:63;
1217 uint64_t wdog:1;
1218 } cn30xx;
1219 struct cvmx_ciu_int_sum1_cn31xx {
1220 uint64_t reserved_2_63:62;
1221 uint64_t wdog:2;
1222 } cn31xx;
1223 struct cvmx_ciu_int_sum1_cn38xx {
1224 uint64_t reserved_16_63:48;
1225 uint64_t wdog:16;
1226 } cn38xx;
1227 struct cvmx_ciu_int_sum1_cn38xx cn38xxp2;
1228 struct cvmx_ciu_int_sum1_cn31xx cn50xx;
1229 struct cvmx_ciu_int_sum1_cn52xx {
1230 uint64_t reserved_20_63:44;
1231 uint64_t nand:1;
1232 uint64_t mii1:1;
1233 uint64_t usb1:1;
1234 uint64_t uart2:1;
1235 uint64_t reserved_4_15:12;
1236 uint64_t wdog:4;
1237 } cn52xx;
1238 struct cvmx_ciu_int_sum1_cn52xxp1 {
1239 uint64_t reserved_19_63:45;
1240 uint64_t mii1:1;
1241 uint64_t usb1:1;
1242 uint64_t uart2:1;
1243 uint64_t reserved_4_15:12;
1244 uint64_t wdog:4;
1245 } cn52xxp1;
1246 struct cvmx_ciu_int_sum1_cn56xx {
1247 uint64_t reserved_12_63:52;
1248 uint64_t wdog:12;
1249 } cn56xx;
1250 struct cvmx_ciu_int_sum1_cn56xx cn56xxp1;
1251 struct cvmx_ciu_int_sum1_cn38xx cn58xx;
1252 struct cvmx_ciu_int_sum1_cn38xx cn58xxp1;
1253};
1254
1255union cvmx_ciu_mbox_clrx {
1256 uint64_t u64;
1257 struct cvmx_ciu_mbox_clrx_s {
1258 uint64_t reserved_32_63:32;
1259 uint64_t bits:32;
1260 } s;
1261 struct cvmx_ciu_mbox_clrx_s cn30xx;
1262 struct cvmx_ciu_mbox_clrx_s cn31xx;
1263 struct cvmx_ciu_mbox_clrx_s cn38xx;
1264 struct cvmx_ciu_mbox_clrx_s cn38xxp2;
1265 struct cvmx_ciu_mbox_clrx_s cn50xx;
1266 struct cvmx_ciu_mbox_clrx_s cn52xx;
1267 struct cvmx_ciu_mbox_clrx_s cn52xxp1;
1268 struct cvmx_ciu_mbox_clrx_s cn56xx;
1269 struct cvmx_ciu_mbox_clrx_s cn56xxp1;
1270 struct cvmx_ciu_mbox_clrx_s cn58xx;
1271 struct cvmx_ciu_mbox_clrx_s cn58xxp1;
1272};
1273
1274union cvmx_ciu_mbox_setx {
1275 uint64_t u64;
1276 struct cvmx_ciu_mbox_setx_s {
1277 uint64_t reserved_32_63:32;
1278 uint64_t bits:32;
1279 } s;
1280 struct cvmx_ciu_mbox_setx_s cn30xx;
1281 struct cvmx_ciu_mbox_setx_s cn31xx;
1282 struct cvmx_ciu_mbox_setx_s cn38xx;
1283 struct cvmx_ciu_mbox_setx_s cn38xxp2;
1284 struct cvmx_ciu_mbox_setx_s cn50xx;
1285 struct cvmx_ciu_mbox_setx_s cn52xx;
1286 struct cvmx_ciu_mbox_setx_s cn52xxp1;
1287 struct cvmx_ciu_mbox_setx_s cn56xx;
1288 struct cvmx_ciu_mbox_setx_s cn56xxp1;
1289 struct cvmx_ciu_mbox_setx_s cn58xx;
1290 struct cvmx_ciu_mbox_setx_s cn58xxp1;
1291};
1292
1293union cvmx_ciu_nmi {
1294 uint64_t u64;
1295 struct cvmx_ciu_nmi_s {
1296 uint64_t reserved_16_63:48;
1297 uint64_t nmi:16;
1298 } s;
1299 struct cvmx_ciu_nmi_cn30xx {
1300 uint64_t reserved_1_63:63;
1301 uint64_t nmi:1;
1302 } cn30xx;
1303 struct cvmx_ciu_nmi_cn31xx {
1304 uint64_t reserved_2_63:62;
1305 uint64_t nmi:2;
1306 } cn31xx;
1307 struct cvmx_ciu_nmi_s cn38xx;
1308 struct cvmx_ciu_nmi_s cn38xxp2;
1309 struct cvmx_ciu_nmi_cn31xx cn50xx;
1310 struct cvmx_ciu_nmi_cn52xx {
1311 uint64_t reserved_4_63:60;
1312 uint64_t nmi:4;
1313 } cn52xx;
1314 struct cvmx_ciu_nmi_cn52xx cn52xxp1;
1315 struct cvmx_ciu_nmi_cn56xx {
1316 uint64_t reserved_12_63:52;
1317 uint64_t nmi:12;
1318 } cn56xx;
1319 struct cvmx_ciu_nmi_cn56xx cn56xxp1;
1320 struct cvmx_ciu_nmi_s cn58xx;
1321 struct cvmx_ciu_nmi_s cn58xxp1;
1322};
1323
1324union cvmx_ciu_pci_inta {
1325 uint64_t u64;
1326 struct cvmx_ciu_pci_inta_s {
1327 uint64_t reserved_2_63:62;
1328 uint64_t intr:2;
1329 } s;
1330 struct cvmx_ciu_pci_inta_s cn30xx;
1331 struct cvmx_ciu_pci_inta_s cn31xx;
1332 struct cvmx_ciu_pci_inta_s cn38xx;
1333 struct cvmx_ciu_pci_inta_s cn38xxp2;
1334 struct cvmx_ciu_pci_inta_s cn50xx;
1335 struct cvmx_ciu_pci_inta_s cn52xx;
1336 struct cvmx_ciu_pci_inta_s cn52xxp1;
1337 struct cvmx_ciu_pci_inta_s cn56xx;
1338 struct cvmx_ciu_pci_inta_s cn56xxp1;
1339 struct cvmx_ciu_pci_inta_s cn58xx;
1340 struct cvmx_ciu_pci_inta_s cn58xxp1;
1341};
1342
1343union cvmx_ciu_pp_dbg {
1344 uint64_t u64;
1345 struct cvmx_ciu_pp_dbg_s {
1346 uint64_t reserved_16_63:48;
1347 uint64_t ppdbg:16;
1348 } s;
1349 struct cvmx_ciu_pp_dbg_cn30xx {
1350 uint64_t reserved_1_63:63;
1351 uint64_t ppdbg:1;
1352 } cn30xx;
1353 struct cvmx_ciu_pp_dbg_cn31xx {
1354 uint64_t reserved_2_63:62;
1355 uint64_t ppdbg:2;
1356 } cn31xx;
1357 struct cvmx_ciu_pp_dbg_s cn38xx;
1358 struct cvmx_ciu_pp_dbg_s cn38xxp2;
1359 struct cvmx_ciu_pp_dbg_cn31xx cn50xx;
1360 struct cvmx_ciu_pp_dbg_cn52xx {
1361 uint64_t reserved_4_63:60;
1362 uint64_t ppdbg:4;
1363 } cn52xx;
1364 struct cvmx_ciu_pp_dbg_cn52xx cn52xxp1;
1365 struct cvmx_ciu_pp_dbg_cn56xx {
1366 uint64_t reserved_12_63:52;
1367 uint64_t ppdbg:12;
1368 } cn56xx;
1369 struct cvmx_ciu_pp_dbg_cn56xx cn56xxp1;
1370 struct cvmx_ciu_pp_dbg_s cn58xx;
1371 struct cvmx_ciu_pp_dbg_s cn58xxp1;
1372};
1373
1374union cvmx_ciu_pp_pokex {
1375 uint64_t u64;
1376 struct cvmx_ciu_pp_pokex_s {
1377 uint64_t reserved_0_63:64;
1378 } s;
1379 struct cvmx_ciu_pp_pokex_s cn30xx;
1380 struct cvmx_ciu_pp_pokex_s cn31xx;
1381 struct cvmx_ciu_pp_pokex_s cn38xx;
1382 struct cvmx_ciu_pp_pokex_s cn38xxp2;
1383 struct cvmx_ciu_pp_pokex_s cn50xx;
1384 struct cvmx_ciu_pp_pokex_s cn52xx;
1385 struct cvmx_ciu_pp_pokex_s cn52xxp1;
1386 struct cvmx_ciu_pp_pokex_s cn56xx;
1387 struct cvmx_ciu_pp_pokex_s cn56xxp1;
1388 struct cvmx_ciu_pp_pokex_s cn58xx;
1389 struct cvmx_ciu_pp_pokex_s cn58xxp1;
1390};
1391
1392union cvmx_ciu_pp_rst {
1393 uint64_t u64;
1394 struct cvmx_ciu_pp_rst_s {
1395 uint64_t reserved_16_63:48;
1396 uint64_t rst:15;
1397 uint64_t rst0:1;
1398 } s;
1399 struct cvmx_ciu_pp_rst_cn30xx {
1400 uint64_t reserved_1_63:63;
1401 uint64_t rst0:1;
1402 } cn30xx;
1403 struct cvmx_ciu_pp_rst_cn31xx {
1404 uint64_t reserved_2_63:62;
1405 uint64_t rst:1;
1406 uint64_t rst0:1;
1407 } cn31xx;
1408 struct cvmx_ciu_pp_rst_s cn38xx;
1409 struct cvmx_ciu_pp_rst_s cn38xxp2;
1410 struct cvmx_ciu_pp_rst_cn31xx cn50xx;
1411 struct cvmx_ciu_pp_rst_cn52xx {
1412 uint64_t reserved_4_63:60;
1413 uint64_t rst:3;
1414 uint64_t rst0:1;
1415 } cn52xx;
1416 struct cvmx_ciu_pp_rst_cn52xx cn52xxp1;
1417 struct cvmx_ciu_pp_rst_cn56xx {
1418 uint64_t reserved_12_63:52;
1419 uint64_t rst:11;
1420 uint64_t rst0:1;
1421 } cn56xx;
1422 struct cvmx_ciu_pp_rst_cn56xx cn56xxp1;
1423 struct cvmx_ciu_pp_rst_s cn58xx;
1424 struct cvmx_ciu_pp_rst_s cn58xxp1;
1425};
1426
1427union cvmx_ciu_qlm_dcok {
1428 uint64_t u64;
1429 struct cvmx_ciu_qlm_dcok_s {
1430 uint64_t reserved_4_63:60;
1431 uint64_t qlm_dcok:4;
1432 } s;
1433 struct cvmx_ciu_qlm_dcok_cn52xx {
1434 uint64_t reserved_2_63:62;
1435 uint64_t qlm_dcok:2;
1436 } cn52xx;
1437 struct cvmx_ciu_qlm_dcok_cn52xx cn52xxp1;
1438 struct cvmx_ciu_qlm_dcok_s cn56xx;
1439 struct cvmx_ciu_qlm_dcok_s cn56xxp1;
1440};
1441
1442union cvmx_ciu_qlm_jtgc {
1443 uint64_t u64;
1444 struct cvmx_ciu_qlm_jtgc_s {
1445 uint64_t reserved_11_63:53;
1446 uint64_t clk_div:3;
1447 uint64_t reserved_6_7:2;
1448 uint64_t mux_sel:2;
1449 uint64_t bypass:4;
1450 } s;
1451 struct cvmx_ciu_qlm_jtgc_cn52xx {
1452 uint64_t reserved_11_63:53;
1453 uint64_t clk_div:3;
1454 uint64_t reserved_5_7:3;
1455 uint64_t mux_sel:1;
1456 uint64_t reserved_2_3:2;
1457 uint64_t bypass:2;
1458 } cn52xx;
1459 struct cvmx_ciu_qlm_jtgc_cn52xx cn52xxp1;
1460 struct cvmx_ciu_qlm_jtgc_s cn56xx;
1461 struct cvmx_ciu_qlm_jtgc_s cn56xxp1;
1462};
1463
1464union cvmx_ciu_qlm_jtgd {
1465 uint64_t u64;
1466 struct cvmx_ciu_qlm_jtgd_s {
1467 uint64_t capture:1;
1468 uint64_t shift:1;
1469 uint64_t update:1;
1470 uint64_t reserved_44_60:17;
1471 uint64_t select:4;
1472 uint64_t reserved_37_39:3;
1473 uint64_t shft_cnt:5;
1474 uint64_t shft_reg:32;
1475 } s;
1476 struct cvmx_ciu_qlm_jtgd_cn52xx {
1477 uint64_t capture:1;
1478 uint64_t shift:1;
1479 uint64_t update:1;
1480 uint64_t reserved_42_60:19;
1481 uint64_t select:2;
1482 uint64_t reserved_37_39:3;
1483 uint64_t shft_cnt:5;
1484 uint64_t shft_reg:32;
1485 } cn52xx;
1486 struct cvmx_ciu_qlm_jtgd_cn52xx cn52xxp1;
1487 struct cvmx_ciu_qlm_jtgd_s cn56xx;
1488 struct cvmx_ciu_qlm_jtgd_cn56xxp1 {
1489 uint64_t capture:1;
1490 uint64_t shift:1;
1491 uint64_t update:1;
1492 uint64_t reserved_37_60:24;
1493 uint64_t shft_cnt:5;
1494 uint64_t shft_reg:32;
1495 } cn56xxp1;
1496};
1497
1498union cvmx_ciu_soft_bist {
1499 uint64_t u64;
1500 struct cvmx_ciu_soft_bist_s {
1501 uint64_t reserved_1_63:63;
1502 uint64_t soft_bist:1;
1503 } s;
1504 struct cvmx_ciu_soft_bist_s cn30xx;
1505 struct cvmx_ciu_soft_bist_s cn31xx;
1506 struct cvmx_ciu_soft_bist_s cn38xx;
1507 struct cvmx_ciu_soft_bist_s cn38xxp2;
1508 struct cvmx_ciu_soft_bist_s cn50xx;
1509 struct cvmx_ciu_soft_bist_s cn52xx;
1510 struct cvmx_ciu_soft_bist_s cn52xxp1;
1511 struct cvmx_ciu_soft_bist_s cn56xx;
1512 struct cvmx_ciu_soft_bist_s cn56xxp1;
1513 struct cvmx_ciu_soft_bist_s cn58xx;
1514 struct cvmx_ciu_soft_bist_s cn58xxp1;
1515};
1516
1517union cvmx_ciu_soft_prst {
1518 uint64_t u64;
1519 struct cvmx_ciu_soft_prst_s {
1520 uint64_t reserved_3_63:61;
1521 uint64_t host64:1;
1522 uint64_t npi:1;
1523 uint64_t soft_prst:1;
1524 } s;
1525 struct cvmx_ciu_soft_prst_s cn30xx;
1526 struct cvmx_ciu_soft_prst_s cn31xx;
1527 struct cvmx_ciu_soft_prst_s cn38xx;
1528 struct cvmx_ciu_soft_prst_s cn38xxp2;
1529 struct cvmx_ciu_soft_prst_s cn50xx;
1530 struct cvmx_ciu_soft_prst_cn52xx {
1531 uint64_t reserved_1_63:63;
1532 uint64_t soft_prst:1;
1533 } cn52xx;
1534 struct cvmx_ciu_soft_prst_cn52xx cn52xxp1;
1535 struct cvmx_ciu_soft_prst_cn52xx cn56xx;
1536 struct cvmx_ciu_soft_prst_cn52xx cn56xxp1;
1537 struct cvmx_ciu_soft_prst_s cn58xx;
1538 struct cvmx_ciu_soft_prst_s cn58xxp1;
1539};
1540
1541union cvmx_ciu_soft_prst1 {
1542 uint64_t u64;
1543 struct cvmx_ciu_soft_prst1_s {
1544 uint64_t reserved_1_63:63;
1545 uint64_t soft_prst:1;
1546 } s;
1547 struct cvmx_ciu_soft_prst1_s cn52xx;
1548 struct cvmx_ciu_soft_prst1_s cn52xxp1;
1549 struct cvmx_ciu_soft_prst1_s cn56xx;
1550 struct cvmx_ciu_soft_prst1_s cn56xxp1;
1551};
1552
1553union cvmx_ciu_soft_rst {
1554 uint64_t u64;
1555 struct cvmx_ciu_soft_rst_s {
1556 uint64_t reserved_1_63:63;
1557 uint64_t soft_rst:1;
1558 } s;
1559 struct cvmx_ciu_soft_rst_s cn30xx;
1560 struct cvmx_ciu_soft_rst_s cn31xx;
1561 struct cvmx_ciu_soft_rst_s cn38xx;
1562 struct cvmx_ciu_soft_rst_s cn38xxp2;
1563 struct cvmx_ciu_soft_rst_s cn50xx;
1564 struct cvmx_ciu_soft_rst_s cn52xx;
1565 struct cvmx_ciu_soft_rst_s cn52xxp1;
1566 struct cvmx_ciu_soft_rst_s cn56xx;
1567 struct cvmx_ciu_soft_rst_s cn56xxp1;
1568 struct cvmx_ciu_soft_rst_s cn58xx;
1569 struct cvmx_ciu_soft_rst_s cn58xxp1;
1570};
1571
1572union cvmx_ciu_timx {
1573 uint64_t u64;
1574 struct cvmx_ciu_timx_s {
1575 uint64_t reserved_37_63:27;
1576 uint64_t one_shot:1;
1577 uint64_t len:36;
1578 } s;
1579 struct cvmx_ciu_timx_s cn30xx;
1580 struct cvmx_ciu_timx_s cn31xx;
1581 struct cvmx_ciu_timx_s cn38xx;
1582 struct cvmx_ciu_timx_s cn38xxp2;
1583 struct cvmx_ciu_timx_s cn50xx;
1584 struct cvmx_ciu_timx_s cn52xx;
1585 struct cvmx_ciu_timx_s cn52xxp1;
1586 struct cvmx_ciu_timx_s cn56xx;
1587 struct cvmx_ciu_timx_s cn56xxp1;
1588 struct cvmx_ciu_timx_s cn58xx;
1589 struct cvmx_ciu_timx_s cn58xxp1;
1590};
1591
1592union cvmx_ciu_wdogx {
1593 uint64_t u64;
1594 struct cvmx_ciu_wdogx_s {
1595 uint64_t reserved_46_63:18;
1596 uint64_t gstopen:1;
1597 uint64_t dstop:1;
1598 uint64_t cnt:24;
1599 uint64_t len:16;
1600 uint64_t state:2;
1601 uint64_t mode:2;
1602 } s;
1603 struct cvmx_ciu_wdogx_s cn30xx;
1604 struct cvmx_ciu_wdogx_s cn31xx;
1605 struct cvmx_ciu_wdogx_s cn38xx;
1606 struct cvmx_ciu_wdogx_s cn38xxp2;
1607 struct cvmx_ciu_wdogx_s cn50xx;
1608 struct cvmx_ciu_wdogx_s cn52xx;
1609 struct cvmx_ciu_wdogx_s cn52xxp1;
1610 struct cvmx_ciu_wdogx_s cn56xx;
1611 struct cvmx_ciu_wdogx_s cn56xxp1;
1612 struct cvmx_ciu_wdogx_s cn58xx;
1613 struct cvmx_ciu_wdogx_s cn58xxp1;
1614};
1615
1616#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-gpio-defs.h b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
new file mode 100644
index 000000000000..5fdd6ba48a05
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-gpio-defs.h
@@ -0,0 +1,219 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_GPIO_DEFS_H__
29#define __CVMX_GPIO_DEFS_H__
30
31#define CVMX_GPIO_BIT_CFGX(offset) \
32 CVMX_ADD_IO_SEG(0x0001070000000800ull + (((offset) & 15) * 8))
33#define CVMX_GPIO_BOOT_ENA \
34 CVMX_ADD_IO_SEG(0x00010700000008A8ull)
35#define CVMX_GPIO_CLK_GENX(offset) \
36 CVMX_ADD_IO_SEG(0x00010700000008C0ull + (((offset) & 3) * 8))
37#define CVMX_GPIO_DBG_ENA \
38 CVMX_ADD_IO_SEG(0x00010700000008A0ull)
39#define CVMX_GPIO_INT_CLR \
40 CVMX_ADD_IO_SEG(0x0001070000000898ull)
41#define CVMX_GPIO_RX_DAT \
42 CVMX_ADD_IO_SEG(0x0001070000000880ull)
43#define CVMX_GPIO_TX_CLR \
44 CVMX_ADD_IO_SEG(0x0001070000000890ull)
45#define CVMX_GPIO_TX_SET \
46 CVMX_ADD_IO_SEG(0x0001070000000888ull)
47#define CVMX_GPIO_XBIT_CFGX(offset) \
48 CVMX_ADD_IO_SEG(0x0001070000000900ull + (((offset) & 31) * 8) - 8 * 16)
49
50union cvmx_gpio_bit_cfgx {
51 uint64_t u64;
52 struct cvmx_gpio_bit_cfgx_s {
53 uint64_t reserved_15_63:49;
54 uint64_t clk_gen:1;
55 uint64_t clk_sel:2;
56 uint64_t fil_sel:4;
57 uint64_t fil_cnt:4;
58 uint64_t int_type:1;
59 uint64_t int_en:1;
60 uint64_t rx_xor:1;
61 uint64_t tx_oe:1;
62 } s;
63 struct cvmx_gpio_bit_cfgx_cn30xx {
64 uint64_t reserved_12_63:52;
65 uint64_t fil_sel:4;
66 uint64_t fil_cnt:4;
67 uint64_t int_type:1;
68 uint64_t int_en:1;
69 uint64_t rx_xor:1;
70 uint64_t tx_oe:1;
71 } cn30xx;
72 struct cvmx_gpio_bit_cfgx_cn30xx cn31xx;
73 struct cvmx_gpio_bit_cfgx_cn30xx cn38xx;
74 struct cvmx_gpio_bit_cfgx_cn30xx cn38xxp2;
75 struct cvmx_gpio_bit_cfgx_cn30xx cn50xx;
76 struct cvmx_gpio_bit_cfgx_s cn52xx;
77 struct cvmx_gpio_bit_cfgx_s cn52xxp1;
78 struct cvmx_gpio_bit_cfgx_s cn56xx;
79 struct cvmx_gpio_bit_cfgx_s cn56xxp1;
80 struct cvmx_gpio_bit_cfgx_cn30xx cn58xx;
81 struct cvmx_gpio_bit_cfgx_cn30xx cn58xxp1;
82};
83
84union cvmx_gpio_boot_ena {
85 uint64_t u64;
86 struct cvmx_gpio_boot_ena_s {
87 uint64_t reserved_12_63:52;
88 uint64_t boot_ena:4;
89 uint64_t reserved_0_7:8;
90 } s;
91 struct cvmx_gpio_boot_ena_s cn30xx;
92 struct cvmx_gpio_boot_ena_s cn31xx;
93 struct cvmx_gpio_boot_ena_s cn50xx;
94};
95
96union cvmx_gpio_clk_genx {
97 uint64_t u64;
98 struct cvmx_gpio_clk_genx_s {
99 uint64_t reserved_32_63:32;
100 uint64_t n:32;
101 } s;
102 struct cvmx_gpio_clk_genx_s cn52xx;
103 struct cvmx_gpio_clk_genx_s cn52xxp1;
104 struct cvmx_gpio_clk_genx_s cn56xx;
105 struct cvmx_gpio_clk_genx_s cn56xxp1;
106};
107
108union cvmx_gpio_dbg_ena {
109 uint64_t u64;
110 struct cvmx_gpio_dbg_ena_s {
111 uint64_t reserved_21_63:43;
112 uint64_t dbg_ena:21;
113 } s;
114 struct cvmx_gpio_dbg_ena_s cn30xx;
115 struct cvmx_gpio_dbg_ena_s cn31xx;
116 struct cvmx_gpio_dbg_ena_s cn50xx;
117};
118
119union cvmx_gpio_int_clr {
120 uint64_t u64;
121 struct cvmx_gpio_int_clr_s {
122 uint64_t reserved_16_63:48;
123 uint64_t type:16;
124 } s;
125 struct cvmx_gpio_int_clr_s cn30xx;
126 struct cvmx_gpio_int_clr_s cn31xx;
127 struct cvmx_gpio_int_clr_s cn38xx;
128 struct cvmx_gpio_int_clr_s cn38xxp2;
129 struct cvmx_gpio_int_clr_s cn50xx;
130 struct cvmx_gpio_int_clr_s cn52xx;
131 struct cvmx_gpio_int_clr_s cn52xxp1;
132 struct cvmx_gpio_int_clr_s cn56xx;
133 struct cvmx_gpio_int_clr_s cn56xxp1;
134 struct cvmx_gpio_int_clr_s cn58xx;
135 struct cvmx_gpio_int_clr_s cn58xxp1;
136};
137
138union cvmx_gpio_rx_dat {
139 uint64_t u64;
140 struct cvmx_gpio_rx_dat_s {
141 uint64_t reserved_24_63:40;
142 uint64_t dat:24;
143 } s;
144 struct cvmx_gpio_rx_dat_s cn30xx;
145 struct cvmx_gpio_rx_dat_s cn31xx;
146 struct cvmx_gpio_rx_dat_cn38xx {
147 uint64_t reserved_16_63:48;
148 uint64_t dat:16;
149 } cn38xx;
150 struct cvmx_gpio_rx_dat_cn38xx cn38xxp2;
151 struct cvmx_gpio_rx_dat_s cn50xx;
152 struct cvmx_gpio_rx_dat_cn38xx cn52xx;
153 struct cvmx_gpio_rx_dat_cn38xx cn52xxp1;
154 struct cvmx_gpio_rx_dat_cn38xx cn56xx;
155 struct cvmx_gpio_rx_dat_cn38xx cn56xxp1;
156 struct cvmx_gpio_rx_dat_cn38xx cn58xx;
157 struct cvmx_gpio_rx_dat_cn38xx cn58xxp1;
158};
159
160union cvmx_gpio_tx_clr {
161 uint64_t u64;
162 struct cvmx_gpio_tx_clr_s {
163 uint64_t reserved_24_63:40;
164 uint64_t clr:24;
165 } s;
166 struct cvmx_gpio_tx_clr_s cn30xx;
167 struct cvmx_gpio_tx_clr_s cn31xx;
168 struct cvmx_gpio_tx_clr_cn38xx {
169 uint64_t reserved_16_63:48;
170 uint64_t clr:16;
171 } cn38xx;
172 struct cvmx_gpio_tx_clr_cn38xx cn38xxp2;
173 struct cvmx_gpio_tx_clr_s cn50xx;
174 struct cvmx_gpio_tx_clr_cn38xx cn52xx;
175 struct cvmx_gpio_tx_clr_cn38xx cn52xxp1;
176 struct cvmx_gpio_tx_clr_cn38xx cn56xx;
177 struct cvmx_gpio_tx_clr_cn38xx cn56xxp1;
178 struct cvmx_gpio_tx_clr_cn38xx cn58xx;
179 struct cvmx_gpio_tx_clr_cn38xx cn58xxp1;
180};
181
182union cvmx_gpio_tx_set {
183 uint64_t u64;
184 struct cvmx_gpio_tx_set_s {
185 uint64_t reserved_24_63:40;
186 uint64_t set:24;
187 } s;
188 struct cvmx_gpio_tx_set_s cn30xx;
189 struct cvmx_gpio_tx_set_s cn31xx;
190 struct cvmx_gpio_tx_set_cn38xx {
191 uint64_t reserved_16_63:48;
192 uint64_t set:16;
193 } cn38xx;
194 struct cvmx_gpio_tx_set_cn38xx cn38xxp2;
195 struct cvmx_gpio_tx_set_s cn50xx;
196 struct cvmx_gpio_tx_set_cn38xx cn52xx;
197 struct cvmx_gpio_tx_set_cn38xx cn52xxp1;
198 struct cvmx_gpio_tx_set_cn38xx cn56xx;
199 struct cvmx_gpio_tx_set_cn38xx cn56xxp1;
200 struct cvmx_gpio_tx_set_cn38xx cn58xx;
201 struct cvmx_gpio_tx_set_cn38xx cn58xxp1;
202};
203
204union cvmx_gpio_xbit_cfgx {
205 uint64_t u64;
206 struct cvmx_gpio_xbit_cfgx_s {
207 uint64_t reserved_12_63:52;
208 uint64_t fil_sel:4;
209 uint64_t fil_cnt:4;
210 uint64_t reserved_2_3:2;
211 uint64_t rx_xor:1;
212 uint64_t tx_oe:1;
213 } s;
214 struct cvmx_gpio_xbit_cfgx_s cn30xx;
215 struct cvmx_gpio_xbit_cfgx_s cn31xx;
216 struct cvmx_gpio_xbit_cfgx_s cn50xx;
217};
218
219#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-iob-defs.h b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
new file mode 100644
index 000000000000..0ee36baec500
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-iob-defs.h
@@ -0,0 +1,530 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_IOB_DEFS_H__
29#define __CVMX_IOB_DEFS_H__
30
31#define CVMX_IOB_BIST_STATUS \
32 CVMX_ADD_IO_SEG(0x00011800F00007F8ull)
33#define CVMX_IOB_CTL_STATUS \
34 CVMX_ADD_IO_SEG(0x00011800F0000050ull)
35#define CVMX_IOB_DWB_PRI_CNT \
36 CVMX_ADD_IO_SEG(0x00011800F0000028ull)
37#define CVMX_IOB_FAU_TIMEOUT \
38 CVMX_ADD_IO_SEG(0x00011800F0000000ull)
39#define CVMX_IOB_I2C_PRI_CNT \
40 CVMX_ADD_IO_SEG(0x00011800F0000010ull)
41#define CVMX_IOB_INB_CONTROL_MATCH \
42 CVMX_ADD_IO_SEG(0x00011800F0000078ull)
43#define CVMX_IOB_INB_CONTROL_MATCH_ENB \
44 CVMX_ADD_IO_SEG(0x00011800F0000088ull)
45#define CVMX_IOB_INB_DATA_MATCH \
46 CVMX_ADD_IO_SEG(0x00011800F0000070ull)
47#define CVMX_IOB_INB_DATA_MATCH_ENB \
48 CVMX_ADD_IO_SEG(0x00011800F0000080ull)
49#define CVMX_IOB_INT_ENB \
50 CVMX_ADD_IO_SEG(0x00011800F0000060ull)
51#define CVMX_IOB_INT_SUM \
52 CVMX_ADD_IO_SEG(0x00011800F0000058ull)
53#define CVMX_IOB_N2C_L2C_PRI_CNT \
54 CVMX_ADD_IO_SEG(0x00011800F0000020ull)
55#define CVMX_IOB_N2C_RSP_PRI_CNT \
56 CVMX_ADD_IO_SEG(0x00011800F0000008ull)
57#define CVMX_IOB_OUTB_COM_PRI_CNT \
58 CVMX_ADD_IO_SEG(0x00011800F0000040ull)
59#define CVMX_IOB_OUTB_CONTROL_MATCH \
60 CVMX_ADD_IO_SEG(0x00011800F0000098ull)
61#define CVMX_IOB_OUTB_CONTROL_MATCH_ENB \
62 CVMX_ADD_IO_SEG(0x00011800F00000A8ull)
63#define CVMX_IOB_OUTB_DATA_MATCH \
64 CVMX_ADD_IO_SEG(0x00011800F0000090ull)
65#define CVMX_IOB_OUTB_DATA_MATCH_ENB \
66 CVMX_ADD_IO_SEG(0x00011800F00000A0ull)
67#define CVMX_IOB_OUTB_FPA_PRI_CNT \
68 CVMX_ADD_IO_SEG(0x00011800F0000048ull)
69#define CVMX_IOB_OUTB_REQ_PRI_CNT \
70 CVMX_ADD_IO_SEG(0x00011800F0000038ull)
71#define CVMX_IOB_P2C_REQ_PRI_CNT \
72 CVMX_ADD_IO_SEG(0x00011800F0000018ull)
73#define CVMX_IOB_PKT_ERR \
74 CVMX_ADD_IO_SEG(0x00011800F0000068ull)
75
76union cvmx_iob_bist_status {
77 uint64_t u64;
78 struct cvmx_iob_bist_status_s {
79 uint64_t reserved_18_63:46;
80 uint64_t icnrcb:1;
81 uint64_t icr0:1;
82 uint64_t icr1:1;
83 uint64_t icnr1:1;
84 uint64_t icnr0:1;
85 uint64_t ibdr0:1;
86 uint64_t ibdr1:1;
87 uint64_t ibr0:1;
88 uint64_t ibr1:1;
89 uint64_t icnrt:1;
90 uint64_t ibrq0:1;
91 uint64_t ibrq1:1;
92 uint64_t icrn0:1;
93 uint64_t icrn1:1;
94 uint64_t icrp0:1;
95 uint64_t icrp1:1;
96 uint64_t ibd:1;
97 uint64_t icd:1;
98 } s;
99 struct cvmx_iob_bist_status_s cn30xx;
100 struct cvmx_iob_bist_status_s cn31xx;
101 struct cvmx_iob_bist_status_s cn38xx;
102 struct cvmx_iob_bist_status_s cn38xxp2;
103 struct cvmx_iob_bist_status_s cn50xx;
104 struct cvmx_iob_bist_status_s cn52xx;
105 struct cvmx_iob_bist_status_s cn52xxp1;
106 struct cvmx_iob_bist_status_s cn56xx;
107 struct cvmx_iob_bist_status_s cn56xxp1;
108 struct cvmx_iob_bist_status_s cn58xx;
109 struct cvmx_iob_bist_status_s cn58xxp1;
110};
111
112union cvmx_iob_ctl_status {
113 uint64_t u64;
114 struct cvmx_iob_ctl_status_s {
115 uint64_t reserved_5_63:59;
116 uint64_t outb_mat:1;
117 uint64_t inb_mat:1;
118 uint64_t pko_enb:1;
119 uint64_t dwb_enb:1;
120 uint64_t fau_end:1;
121 } s;
122 struct cvmx_iob_ctl_status_s cn30xx;
123 struct cvmx_iob_ctl_status_s cn31xx;
124 struct cvmx_iob_ctl_status_s cn38xx;
125 struct cvmx_iob_ctl_status_s cn38xxp2;
126 struct cvmx_iob_ctl_status_s cn50xx;
127 struct cvmx_iob_ctl_status_s cn52xx;
128 struct cvmx_iob_ctl_status_s cn52xxp1;
129 struct cvmx_iob_ctl_status_s cn56xx;
130 struct cvmx_iob_ctl_status_s cn56xxp1;
131 struct cvmx_iob_ctl_status_s cn58xx;
132 struct cvmx_iob_ctl_status_s cn58xxp1;
133};
134
135union cvmx_iob_dwb_pri_cnt {
136 uint64_t u64;
137 struct cvmx_iob_dwb_pri_cnt_s {
138 uint64_t reserved_16_63:48;
139 uint64_t cnt_enb:1;
140 uint64_t cnt_val:15;
141 } s;
142 struct cvmx_iob_dwb_pri_cnt_s cn38xx;
143 struct cvmx_iob_dwb_pri_cnt_s cn38xxp2;
144 struct cvmx_iob_dwb_pri_cnt_s cn52xx;
145 struct cvmx_iob_dwb_pri_cnt_s cn52xxp1;
146 struct cvmx_iob_dwb_pri_cnt_s cn56xx;
147 struct cvmx_iob_dwb_pri_cnt_s cn56xxp1;
148 struct cvmx_iob_dwb_pri_cnt_s cn58xx;
149 struct cvmx_iob_dwb_pri_cnt_s cn58xxp1;
150};
151
152union cvmx_iob_fau_timeout {
153 uint64_t u64;
154 struct cvmx_iob_fau_timeout_s {
155 uint64_t reserved_13_63:51;
156 uint64_t tout_enb:1;
157 uint64_t tout_val:12;
158 } s;
159 struct cvmx_iob_fau_timeout_s cn30xx;
160 struct cvmx_iob_fau_timeout_s cn31xx;
161 struct cvmx_iob_fau_timeout_s cn38xx;
162 struct cvmx_iob_fau_timeout_s cn38xxp2;
163 struct cvmx_iob_fau_timeout_s cn50xx;
164 struct cvmx_iob_fau_timeout_s cn52xx;
165 struct cvmx_iob_fau_timeout_s cn52xxp1;
166 struct cvmx_iob_fau_timeout_s cn56xx;
167 struct cvmx_iob_fau_timeout_s cn56xxp1;
168 struct cvmx_iob_fau_timeout_s cn58xx;
169 struct cvmx_iob_fau_timeout_s cn58xxp1;
170};
171
172union cvmx_iob_i2c_pri_cnt {
173 uint64_t u64;
174 struct cvmx_iob_i2c_pri_cnt_s {
175 uint64_t reserved_16_63:48;
176 uint64_t cnt_enb:1;
177 uint64_t cnt_val:15;
178 } s;
179 struct cvmx_iob_i2c_pri_cnt_s cn38xx;
180 struct cvmx_iob_i2c_pri_cnt_s cn38xxp2;
181 struct cvmx_iob_i2c_pri_cnt_s cn52xx;
182 struct cvmx_iob_i2c_pri_cnt_s cn52xxp1;
183 struct cvmx_iob_i2c_pri_cnt_s cn56xx;
184 struct cvmx_iob_i2c_pri_cnt_s cn56xxp1;
185 struct cvmx_iob_i2c_pri_cnt_s cn58xx;
186 struct cvmx_iob_i2c_pri_cnt_s cn58xxp1;
187};
188
189union cvmx_iob_inb_control_match {
190 uint64_t u64;
191 struct cvmx_iob_inb_control_match_s {
192 uint64_t reserved_29_63:35;
193 uint64_t mask:8;
194 uint64_t opc:4;
195 uint64_t dst:9;
196 uint64_t src:8;
197 } s;
198 struct cvmx_iob_inb_control_match_s cn30xx;
199 struct cvmx_iob_inb_control_match_s cn31xx;
200 struct cvmx_iob_inb_control_match_s cn38xx;
201 struct cvmx_iob_inb_control_match_s cn38xxp2;
202 struct cvmx_iob_inb_control_match_s cn50xx;
203 struct cvmx_iob_inb_control_match_s cn52xx;
204 struct cvmx_iob_inb_control_match_s cn52xxp1;
205 struct cvmx_iob_inb_control_match_s cn56xx;
206 struct cvmx_iob_inb_control_match_s cn56xxp1;
207 struct cvmx_iob_inb_control_match_s cn58xx;
208 struct cvmx_iob_inb_control_match_s cn58xxp1;
209};
210
211union cvmx_iob_inb_control_match_enb {
212 uint64_t u64;
213 struct cvmx_iob_inb_control_match_enb_s {
214 uint64_t reserved_29_63:35;
215 uint64_t mask:8;
216 uint64_t opc:4;
217 uint64_t dst:9;
218 uint64_t src:8;
219 } s;
220 struct cvmx_iob_inb_control_match_enb_s cn30xx;
221 struct cvmx_iob_inb_control_match_enb_s cn31xx;
222 struct cvmx_iob_inb_control_match_enb_s cn38xx;
223 struct cvmx_iob_inb_control_match_enb_s cn38xxp2;
224 struct cvmx_iob_inb_control_match_enb_s cn50xx;
225 struct cvmx_iob_inb_control_match_enb_s cn52xx;
226 struct cvmx_iob_inb_control_match_enb_s cn52xxp1;
227 struct cvmx_iob_inb_control_match_enb_s cn56xx;
228 struct cvmx_iob_inb_control_match_enb_s cn56xxp1;
229 struct cvmx_iob_inb_control_match_enb_s cn58xx;
230 struct cvmx_iob_inb_control_match_enb_s cn58xxp1;
231};
232
233union cvmx_iob_inb_data_match {
234 uint64_t u64;
235 struct cvmx_iob_inb_data_match_s {
236 uint64_t data:64;
237 } s;
238 struct cvmx_iob_inb_data_match_s cn30xx;
239 struct cvmx_iob_inb_data_match_s cn31xx;
240 struct cvmx_iob_inb_data_match_s cn38xx;
241 struct cvmx_iob_inb_data_match_s cn38xxp2;
242 struct cvmx_iob_inb_data_match_s cn50xx;
243 struct cvmx_iob_inb_data_match_s cn52xx;
244 struct cvmx_iob_inb_data_match_s cn52xxp1;
245 struct cvmx_iob_inb_data_match_s cn56xx;
246 struct cvmx_iob_inb_data_match_s cn56xxp1;
247 struct cvmx_iob_inb_data_match_s cn58xx;
248 struct cvmx_iob_inb_data_match_s cn58xxp1;
249};
250
251union cvmx_iob_inb_data_match_enb {
252 uint64_t u64;
253 struct cvmx_iob_inb_data_match_enb_s {
254 uint64_t data:64;
255 } s;
256 struct cvmx_iob_inb_data_match_enb_s cn30xx;
257 struct cvmx_iob_inb_data_match_enb_s cn31xx;
258 struct cvmx_iob_inb_data_match_enb_s cn38xx;
259 struct cvmx_iob_inb_data_match_enb_s cn38xxp2;
260 struct cvmx_iob_inb_data_match_enb_s cn50xx;
261 struct cvmx_iob_inb_data_match_enb_s cn52xx;
262 struct cvmx_iob_inb_data_match_enb_s cn52xxp1;
263 struct cvmx_iob_inb_data_match_enb_s cn56xx;
264 struct cvmx_iob_inb_data_match_enb_s cn56xxp1;
265 struct cvmx_iob_inb_data_match_enb_s cn58xx;
266 struct cvmx_iob_inb_data_match_enb_s cn58xxp1;
267};
268
269union cvmx_iob_int_enb {
270 uint64_t u64;
271 struct cvmx_iob_int_enb_s {
272 uint64_t reserved_6_63:58;
273 uint64_t p_dat:1;
274 uint64_t np_dat:1;
275 uint64_t p_eop:1;
276 uint64_t p_sop:1;
277 uint64_t np_eop:1;
278 uint64_t np_sop:1;
279 } s;
280 struct cvmx_iob_int_enb_cn30xx {
281 uint64_t reserved_4_63:60;
282 uint64_t p_eop:1;
283 uint64_t p_sop:1;
284 uint64_t np_eop:1;
285 uint64_t np_sop:1;
286 } cn30xx;
287 struct cvmx_iob_int_enb_cn30xx cn31xx;
288 struct cvmx_iob_int_enb_cn30xx cn38xx;
289 struct cvmx_iob_int_enb_cn30xx cn38xxp2;
290 struct cvmx_iob_int_enb_s cn50xx;
291 struct cvmx_iob_int_enb_s cn52xx;
292 struct cvmx_iob_int_enb_s cn52xxp1;
293 struct cvmx_iob_int_enb_s cn56xx;
294 struct cvmx_iob_int_enb_s cn56xxp1;
295 struct cvmx_iob_int_enb_s cn58xx;
296 struct cvmx_iob_int_enb_s cn58xxp1;
297};
298
299union cvmx_iob_int_sum {
300 uint64_t u64;
301 struct cvmx_iob_int_sum_s {
302 uint64_t reserved_6_63:58;
303 uint64_t p_dat:1;
304 uint64_t np_dat:1;
305 uint64_t p_eop:1;
306 uint64_t p_sop:1;
307 uint64_t np_eop:1;
308 uint64_t np_sop:1;
309 } s;
310 struct cvmx_iob_int_sum_cn30xx {
311 uint64_t reserved_4_63:60;
312 uint64_t p_eop:1;
313 uint64_t p_sop:1;
314 uint64_t np_eop:1;
315 uint64_t np_sop:1;
316 } cn30xx;
317 struct cvmx_iob_int_sum_cn30xx cn31xx;
318 struct cvmx_iob_int_sum_cn30xx cn38xx;
319 struct cvmx_iob_int_sum_cn30xx cn38xxp2;
320 struct cvmx_iob_int_sum_s cn50xx;
321 struct cvmx_iob_int_sum_s cn52xx;
322 struct cvmx_iob_int_sum_s cn52xxp1;
323 struct cvmx_iob_int_sum_s cn56xx;
324 struct cvmx_iob_int_sum_s cn56xxp1;
325 struct cvmx_iob_int_sum_s cn58xx;
326 struct cvmx_iob_int_sum_s cn58xxp1;
327};
328
329union cvmx_iob_n2c_l2c_pri_cnt {
330 uint64_t u64;
331 struct cvmx_iob_n2c_l2c_pri_cnt_s {
332 uint64_t reserved_16_63:48;
333 uint64_t cnt_enb:1;
334 uint64_t cnt_val:15;
335 } s;
336 struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xx;
337 struct cvmx_iob_n2c_l2c_pri_cnt_s cn38xxp2;
338 struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xx;
339 struct cvmx_iob_n2c_l2c_pri_cnt_s cn52xxp1;
340 struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xx;
341 struct cvmx_iob_n2c_l2c_pri_cnt_s cn56xxp1;
342 struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xx;
343 struct cvmx_iob_n2c_l2c_pri_cnt_s cn58xxp1;
344};
345
346union cvmx_iob_n2c_rsp_pri_cnt {
347 uint64_t u64;
348 struct cvmx_iob_n2c_rsp_pri_cnt_s {
349 uint64_t reserved_16_63:48;
350 uint64_t cnt_enb:1;
351 uint64_t cnt_val:15;
352 } s;
353 struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xx;
354 struct cvmx_iob_n2c_rsp_pri_cnt_s cn38xxp2;
355 struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xx;
356 struct cvmx_iob_n2c_rsp_pri_cnt_s cn52xxp1;
357 struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xx;
358 struct cvmx_iob_n2c_rsp_pri_cnt_s cn56xxp1;
359 struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xx;
360 struct cvmx_iob_n2c_rsp_pri_cnt_s cn58xxp1;
361};
362
363union cvmx_iob_outb_com_pri_cnt {
364 uint64_t u64;
365 struct cvmx_iob_outb_com_pri_cnt_s {
366 uint64_t reserved_16_63:48;
367 uint64_t cnt_enb:1;
368 uint64_t cnt_val:15;
369 } s;
370 struct cvmx_iob_outb_com_pri_cnt_s cn38xx;
371 struct cvmx_iob_outb_com_pri_cnt_s cn38xxp2;
372 struct cvmx_iob_outb_com_pri_cnt_s cn52xx;
373 struct cvmx_iob_outb_com_pri_cnt_s cn52xxp1;
374 struct cvmx_iob_outb_com_pri_cnt_s cn56xx;
375 struct cvmx_iob_outb_com_pri_cnt_s cn56xxp1;
376 struct cvmx_iob_outb_com_pri_cnt_s cn58xx;
377 struct cvmx_iob_outb_com_pri_cnt_s cn58xxp1;
378};
379
380union cvmx_iob_outb_control_match {
381 uint64_t u64;
382 struct cvmx_iob_outb_control_match_s {
383 uint64_t reserved_26_63:38;
384 uint64_t mask:8;
385 uint64_t eot:1;
386 uint64_t dst:8;
387 uint64_t src:9;
388 } s;
389 struct cvmx_iob_outb_control_match_s cn30xx;
390 struct cvmx_iob_outb_control_match_s cn31xx;
391 struct cvmx_iob_outb_control_match_s cn38xx;
392 struct cvmx_iob_outb_control_match_s cn38xxp2;
393 struct cvmx_iob_outb_control_match_s cn50xx;
394 struct cvmx_iob_outb_control_match_s cn52xx;
395 struct cvmx_iob_outb_control_match_s cn52xxp1;
396 struct cvmx_iob_outb_control_match_s cn56xx;
397 struct cvmx_iob_outb_control_match_s cn56xxp1;
398 struct cvmx_iob_outb_control_match_s cn58xx;
399 struct cvmx_iob_outb_control_match_s cn58xxp1;
400};
401
402union cvmx_iob_outb_control_match_enb {
403 uint64_t u64;
404 struct cvmx_iob_outb_control_match_enb_s {
405 uint64_t reserved_26_63:38;
406 uint64_t mask:8;
407 uint64_t eot:1;
408 uint64_t dst:8;
409 uint64_t src:9;
410 } s;
411 struct cvmx_iob_outb_control_match_enb_s cn30xx;
412 struct cvmx_iob_outb_control_match_enb_s cn31xx;
413 struct cvmx_iob_outb_control_match_enb_s cn38xx;
414 struct cvmx_iob_outb_control_match_enb_s cn38xxp2;
415 struct cvmx_iob_outb_control_match_enb_s cn50xx;
416 struct cvmx_iob_outb_control_match_enb_s cn52xx;
417 struct cvmx_iob_outb_control_match_enb_s cn52xxp1;
418 struct cvmx_iob_outb_control_match_enb_s cn56xx;
419 struct cvmx_iob_outb_control_match_enb_s cn56xxp1;
420 struct cvmx_iob_outb_control_match_enb_s cn58xx;
421 struct cvmx_iob_outb_control_match_enb_s cn58xxp1;
422};
423
424union cvmx_iob_outb_data_match {
425 uint64_t u64;
426 struct cvmx_iob_outb_data_match_s {
427 uint64_t data:64;
428 } s;
429 struct cvmx_iob_outb_data_match_s cn30xx;
430 struct cvmx_iob_outb_data_match_s cn31xx;
431 struct cvmx_iob_outb_data_match_s cn38xx;
432 struct cvmx_iob_outb_data_match_s cn38xxp2;
433 struct cvmx_iob_outb_data_match_s cn50xx;
434 struct cvmx_iob_outb_data_match_s cn52xx;
435 struct cvmx_iob_outb_data_match_s cn52xxp1;
436 struct cvmx_iob_outb_data_match_s cn56xx;
437 struct cvmx_iob_outb_data_match_s cn56xxp1;
438 struct cvmx_iob_outb_data_match_s cn58xx;
439 struct cvmx_iob_outb_data_match_s cn58xxp1;
440};
441
442union cvmx_iob_outb_data_match_enb {
443 uint64_t u64;
444 struct cvmx_iob_outb_data_match_enb_s {
445 uint64_t data:64;
446 } s;
447 struct cvmx_iob_outb_data_match_enb_s cn30xx;
448 struct cvmx_iob_outb_data_match_enb_s cn31xx;
449 struct cvmx_iob_outb_data_match_enb_s cn38xx;
450 struct cvmx_iob_outb_data_match_enb_s cn38xxp2;
451 struct cvmx_iob_outb_data_match_enb_s cn50xx;
452 struct cvmx_iob_outb_data_match_enb_s cn52xx;
453 struct cvmx_iob_outb_data_match_enb_s cn52xxp1;
454 struct cvmx_iob_outb_data_match_enb_s cn56xx;
455 struct cvmx_iob_outb_data_match_enb_s cn56xxp1;
456 struct cvmx_iob_outb_data_match_enb_s cn58xx;
457 struct cvmx_iob_outb_data_match_enb_s cn58xxp1;
458};
459
460union cvmx_iob_outb_fpa_pri_cnt {
461 uint64_t u64;
462 struct cvmx_iob_outb_fpa_pri_cnt_s {
463 uint64_t reserved_16_63:48;
464 uint64_t cnt_enb:1;
465 uint64_t cnt_val:15;
466 } s;
467 struct cvmx_iob_outb_fpa_pri_cnt_s cn38xx;
468 struct cvmx_iob_outb_fpa_pri_cnt_s cn38xxp2;
469 struct cvmx_iob_outb_fpa_pri_cnt_s cn52xx;
470 struct cvmx_iob_outb_fpa_pri_cnt_s cn52xxp1;
471 struct cvmx_iob_outb_fpa_pri_cnt_s cn56xx;
472 struct cvmx_iob_outb_fpa_pri_cnt_s cn56xxp1;
473 struct cvmx_iob_outb_fpa_pri_cnt_s cn58xx;
474 struct cvmx_iob_outb_fpa_pri_cnt_s cn58xxp1;
475};
476
477union cvmx_iob_outb_req_pri_cnt {
478 uint64_t u64;
479 struct cvmx_iob_outb_req_pri_cnt_s {
480 uint64_t reserved_16_63:48;
481 uint64_t cnt_enb:1;
482 uint64_t cnt_val:15;
483 } s;
484 struct cvmx_iob_outb_req_pri_cnt_s cn38xx;
485 struct cvmx_iob_outb_req_pri_cnt_s cn38xxp2;
486 struct cvmx_iob_outb_req_pri_cnt_s cn52xx;
487 struct cvmx_iob_outb_req_pri_cnt_s cn52xxp1;
488 struct cvmx_iob_outb_req_pri_cnt_s cn56xx;
489 struct cvmx_iob_outb_req_pri_cnt_s cn56xxp1;
490 struct cvmx_iob_outb_req_pri_cnt_s cn58xx;
491 struct cvmx_iob_outb_req_pri_cnt_s cn58xxp1;
492};
493
494union cvmx_iob_p2c_req_pri_cnt {
495 uint64_t u64;
496 struct cvmx_iob_p2c_req_pri_cnt_s {
497 uint64_t reserved_16_63:48;
498 uint64_t cnt_enb:1;
499 uint64_t cnt_val:15;
500 } s;
501 struct cvmx_iob_p2c_req_pri_cnt_s cn38xx;
502 struct cvmx_iob_p2c_req_pri_cnt_s cn38xxp2;
503 struct cvmx_iob_p2c_req_pri_cnt_s cn52xx;
504 struct cvmx_iob_p2c_req_pri_cnt_s cn52xxp1;
505 struct cvmx_iob_p2c_req_pri_cnt_s cn56xx;
506 struct cvmx_iob_p2c_req_pri_cnt_s cn56xxp1;
507 struct cvmx_iob_p2c_req_pri_cnt_s cn58xx;
508 struct cvmx_iob_p2c_req_pri_cnt_s cn58xxp1;
509};
510
511union cvmx_iob_pkt_err {
512 uint64_t u64;
513 struct cvmx_iob_pkt_err_s {
514 uint64_t reserved_6_63:58;
515 uint64_t port:6;
516 } s;
517 struct cvmx_iob_pkt_err_s cn30xx;
518 struct cvmx_iob_pkt_err_s cn31xx;
519 struct cvmx_iob_pkt_err_s cn38xx;
520 struct cvmx_iob_pkt_err_s cn38xxp2;
521 struct cvmx_iob_pkt_err_s cn50xx;
522 struct cvmx_iob_pkt_err_s cn52xx;
523 struct cvmx_iob_pkt_err_s cn52xxp1;
524 struct cvmx_iob_pkt_err_s cn56xx;
525 struct cvmx_iob_pkt_err_s cn56xxp1;
526 struct cvmx_iob_pkt_err_s cn58xx;
527 struct cvmx_iob_pkt_err_s cn58xxp1;
528};
529
530#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-ipd-defs.h b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
new file mode 100644
index 000000000000..f8b8fc657d2c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-ipd-defs.h
@@ -0,0 +1,877 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_IPD_DEFS_H__
29#define __CVMX_IPD_DEFS_H__
30
31#define CVMX_IPD_1ST_MBUFF_SKIP \
32 CVMX_ADD_IO_SEG(0x00014F0000000000ull)
33#define CVMX_IPD_1st_NEXT_PTR_BACK \
34 CVMX_ADD_IO_SEG(0x00014F0000000150ull)
35#define CVMX_IPD_2nd_NEXT_PTR_BACK \
36 CVMX_ADD_IO_SEG(0x00014F0000000158ull)
37#define CVMX_IPD_BIST_STATUS \
38 CVMX_ADD_IO_SEG(0x00014F00000007F8ull)
39#define CVMX_IPD_BP_PRT_RED_END \
40 CVMX_ADD_IO_SEG(0x00014F0000000328ull)
41#define CVMX_IPD_CLK_COUNT \
42 CVMX_ADD_IO_SEG(0x00014F0000000338ull)
43#define CVMX_IPD_CTL_STATUS \
44 CVMX_ADD_IO_SEG(0x00014F0000000018ull)
45#define CVMX_IPD_INT_ENB \
46 CVMX_ADD_IO_SEG(0x00014F0000000160ull)
47#define CVMX_IPD_INT_SUM \
48 CVMX_ADD_IO_SEG(0x00014F0000000168ull)
49#define CVMX_IPD_NOT_1ST_MBUFF_SKIP \
50 CVMX_ADD_IO_SEG(0x00014F0000000008ull)
51#define CVMX_IPD_PACKET_MBUFF_SIZE \
52 CVMX_ADD_IO_SEG(0x00014F0000000010ull)
53#define CVMX_IPD_PKT_PTR_VALID \
54 CVMX_ADD_IO_SEG(0x00014F0000000358ull)
55#define CVMX_IPD_PORTX_BP_PAGE_CNT(offset) \
56 CVMX_ADD_IO_SEG(0x00014F0000000028ull + (((offset) & 63) * 8))
57#define CVMX_IPD_PORTX_BP_PAGE_CNT2(offset) \
58 CVMX_ADD_IO_SEG(0x00014F0000000368ull + (((offset) & 63) * 8) - 8 * 36)
59#define CVMX_IPD_PORT_BP_COUNTERS2_PAIRX(offset) \
60 CVMX_ADD_IO_SEG(0x00014F0000000388ull + (((offset) & 63) * 8) - 8 * 36)
61#define CVMX_IPD_PORT_BP_COUNTERS_PAIRX(offset) \
62 CVMX_ADD_IO_SEG(0x00014F00000001B8ull + (((offset) & 63) * 8))
63#define CVMX_IPD_PORT_QOS_INTX(offset) \
64 CVMX_ADD_IO_SEG(0x00014F0000000808ull + (((offset) & 7) * 8))
65#define CVMX_IPD_PORT_QOS_INT_ENBX(offset) \
66 CVMX_ADD_IO_SEG(0x00014F0000000848ull + (((offset) & 7) * 8))
67#define CVMX_IPD_PORT_QOS_X_CNT(offset) \
68 CVMX_ADD_IO_SEG(0x00014F0000000888ull + (((offset) & 511) * 8))
69#define CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL \
70 CVMX_ADD_IO_SEG(0x00014F0000000348ull)
71#define CVMX_IPD_PRC_PORT_PTR_FIFO_CTL \
72 CVMX_ADD_IO_SEG(0x00014F0000000350ull)
73#define CVMX_IPD_PTR_COUNT \
74 CVMX_ADD_IO_SEG(0x00014F0000000320ull)
75#define CVMX_IPD_PWP_PTR_FIFO_CTL \
76 CVMX_ADD_IO_SEG(0x00014F0000000340ull)
77#define CVMX_IPD_QOS0_RED_MARKS \
78 CVMX_ADD_IO_SEG(0x00014F0000000178ull)
79#define CVMX_IPD_QOS1_RED_MARKS \
80 CVMX_ADD_IO_SEG(0x00014F0000000180ull)
81#define CVMX_IPD_QOS2_RED_MARKS \
82 CVMX_ADD_IO_SEG(0x00014F0000000188ull)
83#define CVMX_IPD_QOS3_RED_MARKS \
84 CVMX_ADD_IO_SEG(0x00014F0000000190ull)
85#define CVMX_IPD_QOS4_RED_MARKS \
86 CVMX_ADD_IO_SEG(0x00014F0000000198ull)
87#define CVMX_IPD_QOS5_RED_MARKS \
88 CVMX_ADD_IO_SEG(0x00014F00000001A0ull)
89#define CVMX_IPD_QOS6_RED_MARKS \
90 CVMX_ADD_IO_SEG(0x00014F00000001A8ull)
91#define CVMX_IPD_QOS7_RED_MARKS \
92 CVMX_ADD_IO_SEG(0x00014F00000001B0ull)
93#define CVMX_IPD_QOSX_RED_MARKS(offset) \
94 CVMX_ADD_IO_SEG(0x00014F0000000178ull + (((offset) & 7) * 8))
95#define CVMX_IPD_QUE0_FREE_PAGE_CNT \
96 CVMX_ADD_IO_SEG(0x00014F0000000330ull)
97#define CVMX_IPD_RED_PORT_ENABLE \
98 CVMX_ADD_IO_SEG(0x00014F00000002D8ull)
99#define CVMX_IPD_RED_PORT_ENABLE2 \
100 CVMX_ADD_IO_SEG(0x00014F00000003A8ull)
101#define CVMX_IPD_RED_QUE0_PARAM \
102 CVMX_ADD_IO_SEG(0x00014F00000002E0ull)
103#define CVMX_IPD_RED_QUE1_PARAM \
104 CVMX_ADD_IO_SEG(0x00014F00000002E8ull)
105#define CVMX_IPD_RED_QUE2_PARAM \
106 CVMX_ADD_IO_SEG(0x00014F00000002F0ull)
107#define CVMX_IPD_RED_QUE3_PARAM \
108 CVMX_ADD_IO_SEG(0x00014F00000002F8ull)
109#define CVMX_IPD_RED_QUE4_PARAM \
110 CVMX_ADD_IO_SEG(0x00014F0000000300ull)
111#define CVMX_IPD_RED_QUE5_PARAM \
112 CVMX_ADD_IO_SEG(0x00014F0000000308ull)
113#define CVMX_IPD_RED_QUE6_PARAM \
114 CVMX_ADD_IO_SEG(0x00014F0000000310ull)
115#define CVMX_IPD_RED_QUE7_PARAM \
116 CVMX_ADD_IO_SEG(0x00014F0000000318ull)
117#define CVMX_IPD_RED_QUEX_PARAM(offset) \
118 CVMX_ADD_IO_SEG(0x00014F00000002E0ull + (((offset) & 7) * 8))
119#define CVMX_IPD_SUB_PORT_BP_PAGE_CNT \
120 CVMX_ADD_IO_SEG(0x00014F0000000148ull)
121#define CVMX_IPD_SUB_PORT_FCS \
122 CVMX_ADD_IO_SEG(0x00014F0000000170ull)
123#define CVMX_IPD_SUB_PORT_QOS_CNT \
124 CVMX_ADD_IO_SEG(0x00014F0000000800ull)
125#define CVMX_IPD_WQE_FPA_QUEUE \
126 CVMX_ADD_IO_SEG(0x00014F0000000020ull)
127#define CVMX_IPD_WQE_PTR_VALID \
128 CVMX_ADD_IO_SEG(0x00014F0000000360ull)
129
130union cvmx_ipd_1st_mbuff_skip {
131 uint64_t u64;
132 struct cvmx_ipd_1st_mbuff_skip_s {
133 uint64_t reserved_6_63:58;
134 uint64_t skip_sz:6;
135 } s;
136 struct cvmx_ipd_1st_mbuff_skip_s cn30xx;
137 struct cvmx_ipd_1st_mbuff_skip_s cn31xx;
138 struct cvmx_ipd_1st_mbuff_skip_s cn38xx;
139 struct cvmx_ipd_1st_mbuff_skip_s cn38xxp2;
140 struct cvmx_ipd_1st_mbuff_skip_s cn50xx;
141 struct cvmx_ipd_1st_mbuff_skip_s cn52xx;
142 struct cvmx_ipd_1st_mbuff_skip_s cn52xxp1;
143 struct cvmx_ipd_1st_mbuff_skip_s cn56xx;
144 struct cvmx_ipd_1st_mbuff_skip_s cn56xxp1;
145 struct cvmx_ipd_1st_mbuff_skip_s cn58xx;
146 struct cvmx_ipd_1st_mbuff_skip_s cn58xxp1;
147};
148
149union cvmx_ipd_1st_next_ptr_back {
150 uint64_t u64;
151 struct cvmx_ipd_1st_next_ptr_back_s {
152 uint64_t reserved_4_63:60;
153 uint64_t back:4;
154 } s;
155 struct cvmx_ipd_1st_next_ptr_back_s cn30xx;
156 struct cvmx_ipd_1st_next_ptr_back_s cn31xx;
157 struct cvmx_ipd_1st_next_ptr_back_s cn38xx;
158 struct cvmx_ipd_1st_next_ptr_back_s cn38xxp2;
159 struct cvmx_ipd_1st_next_ptr_back_s cn50xx;
160 struct cvmx_ipd_1st_next_ptr_back_s cn52xx;
161 struct cvmx_ipd_1st_next_ptr_back_s cn52xxp1;
162 struct cvmx_ipd_1st_next_ptr_back_s cn56xx;
163 struct cvmx_ipd_1st_next_ptr_back_s cn56xxp1;
164 struct cvmx_ipd_1st_next_ptr_back_s cn58xx;
165 struct cvmx_ipd_1st_next_ptr_back_s cn58xxp1;
166};
167
168union cvmx_ipd_2nd_next_ptr_back {
169 uint64_t u64;
170 struct cvmx_ipd_2nd_next_ptr_back_s {
171 uint64_t reserved_4_63:60;
172 uint64_t back:4;
173 } s;
174 struct cvmx_ipd_2nd_next_ptr_back_s cn30xx;
175 struct cvmx_ipd_2nd_next_ptr_back_s cn31xx;
176 struct cvmx_ipd_2nd_next_ptr_back_s cn38xx;
177 struct cvmx_ipd_2nd_next_ptr_back_s cn38xxp2;
178 struct cvmx_ipd_2nd_next_ptr_back_s cn50xx;
179 struct cvmx_ipd_2nd_next_ptr_back_s cn52xx;
180 struct cvmx_ipd_2nd_next_ptr_back_s cn52xxp1;
181 struct cvmx_ipd_2nd_next_ptr_back_s cn56xx;
182 struct cvmx_ipd_2nd_next_ptr_back_s cn56xxp1;
183 struct cvmx_ipd_2nd_next_ptr_back_s cn58xx;
184 struct cvmx_ipd_2nd_next_ptr_back_s cn58xxp1;
185};
186
187union cvmx_ipd_bist_status {
188 uint64_t u64;
189 struct cvmx_ipd_bist_status_s {
190 uint64_t reserved_18_63:46;
191 uint64_t csr_mem:1;
192 uint64_t csr_ncmd:1;
193 uint64_t pwq_wqed:1;
194 uint64_t pwq_wp1:1;
195 uint64_t pwq_pow:1;
196 uint64_t ipq_pbe1:1;
197 uint64_t ipq_pbe0:1;
198 uint64_t pbm3:1;
199 uint64_t pbm2:1;
200 uint64_t pbm1:1;
201 uint64_t pbm0:1;
202 uint64_t pbm_word:1;
203 uint64_t pwq1:1;
204 uint64_t pwq0:1;
205 uint64_t prc_off:1;
206 uint64_t ipd_old:1;
207 uint64_t ipd_new:1;
208 uint64_t pwp:1;
209 } s;
210 struct cvmx_ipd_bist_status_cn30xx {
211 uint64_t reserved_16_63:48;
212 uint64_t pwq_wqed:1;
213 uint64_t pwq_wp1:1;
214 uint64_t pwq_pow:1;
215 uint64_t ipq_pbe1:1;
216 uint64_t ipq_pbe0:1;
217 uint64_t pbm3:1;
218 uint64_t pbm2:1;
219 uint64_t pbm1:1;
220 uint64_t pbm0:1;
221 uint64_t pbm_word:1;
222 uint64_t pwq1:1;
223 uint64_t pwq0:1;
224 uint64_t prc_off:1;
225 uint64_t ipd_old:1;
226 uint64_t ipd_new:1;
227 uint64_t pwp:1;
228 } cn30xx;
229 struct cvmx_ipd_bist_status_cn30xx cn31xx;
230 struct cvmx_ipd_bist_status_cn30xx cn38xx;
231 struct cvmx_ipd_bist_status_cn30xx cn38xxp2;
232 struct cvmx_ipd_bist_status_cn30xx cn50xx;
233 struct cvmx_ipd_bist_status_s cn52xx;
234 struct cvmx_ipd_bist_status_s cn52xxp1;
235 struct cvmx_ipd_bist_status_s cn56xx;
236 struct cvmx_ipd_bist_status_s cn56xxp1;
237 struct cvmx_ipd_bist_status_cn30xx cn58xx;
238 struct cvmx_ipd_bist_status_cn30xx cn58xxp1;
239};
240
241union cvmx_ipd_bp_prt_red_end {
242 uint64_t u64;
243 struct cvmx_ipd_bp_prt_red_end_s {
244 uint64_t reserved_40_63:24;
245 uint64_t prt_enb:40;
246 } s;
247 struct cvmx_ipd_bp_prt_red_end_cn30xx {
248 uint64_t reserved_36_63:28;
249 uint64_t prt_enb:36;
250 } cn30xx;
251 struct cvmx_ipd_bp_prt_red_end_cn30xx cn31xx;
252 struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xx;
253 struct cvmx_ipd_bp_prt_red_end_cn30xx cn38xxp2;
254 struct cvmx_ipd_bp_prt_red_end_cn30xx cn50xx;
255 struct cvmx_ipd_bp_prt_red_end_s cn52xx;
256 struct cvmx_ipd_bp_prt_red_end_s cn52xxp1;
257 struct cvmx_ipd_bp_prt_red_end_s cn56xx;
258 struct cvmx_ipd_bp_prt_red_end_s cn56xxp1;
259 struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xx;
260 struct cvmx_ipd_bp_prt_red_end_cn30xx cn58xxp1;
261};
262
263union cvmx_ipd_clk_count {
264 uint64_t u64;
265 struct cvmx_ipd_clk_count_s {
266 uint64_t clk_cnt:64;
267 } s;
268 struct cvmx_ipd_clk_count_s cn30xx;
269 struct cvmx_ipd_clk_count_s cn31xx;
270 struct cvmx_ipd_clk_count_s cn38xx;
271 struct cvmx_ipd_clk_count_s cn38xxp2;
272 struct cvmx_ipd_clk_count_s cn50xx;
273 struct cvmx_ipd_clk_count_s cn52xx;
274 struct cvmx_ipd_clk_count_s cn52xxp1;
275 struct cvmx_ipd_clk_count_s cn56xx;
276 struct cvmx_ipd_clk_count_s cn56xxp1;
277 struct cvmx_ipd_clk_count_s cn58xx;
278 struct cvmx_ipd_clk_count_s cn58xxp1;
279};
280
281union cvmx_ipd_ctl_status {
282 uint64_t u64;
283 struct cvmx_ipd_ctl_status_s {
284 uint64_t reserved_15_63:49;
285 uint64_t no_wptr:1;
286 uint64_t pq_apkt:1;
287 uint64_t pq_nabuf:1;
288 uint64_t ipd_full:1;
289 uint64_t pkt_off:1;
290 uint64_t len_m8:1;
291 uint64_t reset:1;
292 uint64_t addpkt:1;
293 uint64_t naddbuf:1;
294 uint64_t pkt_lend:1;
295 uint64_t wqe_lend:1;
296 uint64_t pbp_en:1;
297 uint64_t opc_mode:2;
298 uint64_t ipd_en:1;
299 } s;
300 struct cvmx_ipd_ctl_status_cn30xx {
301 uint64_t reserved_10_63:54;
302 uint64_t len_m8:1;
303 uint64_t reset:1;
304 uint64_t addpkt:1;
305 uint64_t naddbuf:1;
306 uint64_t pkt_lend:1;
307 uint64_t wqe_lend:1;
308 uint64_t pbp_en:1;
309 uint64_t opc_mode:2;
310 uint64_t ipd_en:1;
311 } cn30xx;
312 struct cvmx_ipd_ctl_status_cn30xx cn31xx;
313 struct cvmx_ipd_ctl_status_cn30xx cn38xx;
314 struct cvmx_ipd_ctl_status_cn38xxp2 {
315 uint64_t reserved_9_63:55;
316 uint64_t reset:1;
317 uint64_t addpkt:1;
318 uint64_t naddbuf:1;
319 uint64_t pkt_lend:1;
320 uint64_t wqe_lend:1;
321 uint64_t pbp_en:1;
322 uint64_t opc_mode:2;
323 uint64_t ipd_en:1;
324 } cn38xxp2;
325 struct cvmx_ipd_ctl_status_s cn50xx;
326 struct cvmx_ipd_ctl_status_s cn52xx;
327 struct cvmx_ipd_ctl_status_s cn52xxp1;
328 struct cvmx_ipd_ctl_status_s cn56xx;
329 struct cvmx_ipd_ctl_status_s cn56xxp1;
330 struct cvmx_ipd_ctl_status_cn58xx {
331 uint64_t reserved_12_63:52;
332 uint64_t ipd_full:1;
333 uint64_t pkt_off:1;
334 uint64_t len_m8:1;
335 uint64_t reset:1;
336 uint64_t addpkt:1;
337 uint64_t naddbuf:1;
338 uint64_t pkt_lend:1;
339 uint64_t wqe_lend:1;
340 uint64_t pbp_en:1;
341 uint64_t opc_mode:2;
342 uint64_t ipd_en:1;
343 } cn58xx;
344 struct cvmx_ipd_ctl_status_cn58xx cn58xxp1;
345};
346
347union cvmx_ipd_int_enb {
348 uint64_t u64;
349 struct cvmx_ipd_int_enb_s {
350 uint64_t reserved_12_63:52;
351 uint64_t pq_sub:1;
352 uint64_t pq_add:1;
353 uint64_t bc_ovr:1;
354 uint64_t d_coll:1;
355 uint64_t c_coll:1;
356 uint64_t cc_ovr:1;
357 uint64_t dc_ovr:1;
358 uint64_t bp_sub:1;
359 uint64_t prc_par3:1;
360 uint64_t prc_par2:1;
361 uint64_t prc_par1:1;
362 uint64_t prc_par0:1;
363 } s;
364 struct cvmx_ipd_int_enb_cn30xx {
365 uint64_t reserved_5_63:59;
366 uint64_t bp_sub:1;
367 uint64_t prc_par3:1;
368 uint64_t prc_par2:1;
369 uint64_t prc_par1:1;
370 uint64_t prc_par0:1;
371 } cn30xx;
372 struct cvmx_ipd_int_enb_cn30xx cn31xx;
373 struct cvmx_ipd_int_enb_cn38xx {
374 uint64_t reserved_10_63:54;
375 uint64_t bc_ovr:1;
376 uint64_t d_coll:1;
377 uint64_t c_coll:1;
378 uint64_t cc_ovr:1;
379 uint64_t dc_ovr:1;
380 uint64_t bp_sub:1;
381 uint64_t prc_par3:1;
382 uint64_t prc_par2:1;
383 uint64_t prc_par1:1;
384 uint64_t prc_par0:1;
385 } cn38xx;
386 struct cvmx_ipd_int_enb_cn30xx cn38xxp2;
387 struct cvmx_ipd_int_enb_cn38xx cn50xx;
388 struct cvmx_ipd_int_enb_s cn52xx;
389 struct cvmx_ipd_int_enb_s cn52xxp1;
390 struct cvmx_ipd_int_enb_s cn56xx;
391 struct cvmx_ipd_int_enb_s cn56xxp1;
392 struct cvmx_ipd_int_enb_cn38xx cn58xx;
393 struct cvmx_ipd_int_enb_cn38xx cn58xxp1;
394};
395
396union cvmx_ipd_int_sum {
397 uint64_t u64;
398 struct cvmx_ipd_int_sum_s {
399 uint64_t reserved_12_63:52;
400 uint64_t pq_sub:1;
401 uint64_t pq_add:1;
402 uint64_t bc_ovr:1;
403 uint64_t d_coll:1;
404 uint64_t c_coll:1;
405 uint64_t cc_ovr:1;
406 uint64_t dc_ovr:1;
407 uint64_t bp_sub:1;
408 uint64_t prc_par3:1;
409 uint64_t prc_par2:1;
410 uint64_t prc_par1:1;
411 uint64_t prc_par0:1;
412 } s;
413 struct cvmx_ipd_int_sum_cn30xx {
414 uint64_t reserved_5_63:59;
415 uint64_t bp_sub:1;
416 uint64_t prc_par3:1;
417 uint64_t prc_par2:1;
418 uint64_t prc_par1:1;
419 uint64_t prc_par0:1;
420 } cn30xx;
421 struct cvmx_ipd_int_sum_cn30xx cn31xx;
422 struct cvmx_ipd_int_sum_cn38xx {
423 uint64_t reserved_10_63:54;
424 uint64_t bc_ovr:1;
425 uint64_t d_coll:1;
426 uint64_t c_coll:1;
427 uint64_t cc_ovr:1;
428 uint64_t dc_ovr:1;
429 uint64_t bp_sub:1;
430 uint64_t prc_par3:1;
431 uint64_t prc_par2:1;
432 uint64_t prc_par1:1;
433 uint64_t prc_par0:1;
434 } cn38xx;
435 struct cvmx_ipd_int_sum_cn30xx cn38xxp2;
436 struct cvmx_ipd_int_sum_cn38xx cn50xx;
437 struct cvmx_ipd_int_sum_s cn52xx;
438 struct cvmx_ipd_int_sum_s cn52xxp1;
439 struct cvmx_ipd_int_sum_s cn56xx;
440 struct cvmx_ipd_int_sum_s cn56xxp1;
441 struct cvmx_ipd_int_sum_cn38xx cn58xx;
442 struct cvmx_ipd_int_sum_cn38xx cn58xxp1;
443};
444
445union cvmx_ipd_not_1st_mbuff_skip {
446 uint64_t u64;
447 struct cvmx_ipd_not_1st_mbuff_skip_s {
448 uint64_t reserved_6_63:58;
449 uint64_t skip_sz:6;
450 } s;
451 struct cvmx_ipd_not_1st_mbuff_skip_s cn30xx;
452 struct cvmx_ipd_not_1st_mbuff_skip_s cn31xx;
453 struct cvmx_ipd_not_1st_mbuff_skip_s cn38xx;
454 struct cvmx_ipd_not_1st_mbuff_skip_s cn38xxp2;
455 struct cvmx_ipd_not_1st_mbuff_skip_s cn50xx;
456 struct cvmx_ipd_not_1st_mbuff_skip_s cn52xx;
457 struct cvmx_ipd_not_1st_mbuff_skip_s cn52xxp1;
458 struct cvmx_ipd_not_1st_mbuff_skip_s cn56xx;
459 struct cvmx_ipd_not_1st_mbuff_skip_s cn56xxp1;
460 struct cvmx_ipd_not_1st_mbuff_skip_s cn58xx;
461 struct cvmx_ipd_not_1st_mbuff_skip_s cn58xxp1;
462};
463
464union cvmx_ipd_packet_mbuff_size {
465 uint64_t u64;
466 struct cvmx_ipd_packet_mbuff_size_s {
467 uint64_t reserved_12_63:52;
468 uint64_t mb_size:12;
469 } s;
470 struct cvmx_ipd_packet_mbuff_size_s cn30xx;
471 struct cvmx_ipd_packet_mbuff_size_s cn31xx;
472 struct cvmx_ipd_packet_mbuff_size_s cn38xx;
473 struct cvmx_ipd_packet_mbuff_size_s cn38xxp2;
474 struct cvmx_ipd_packet_mbuff_size_s cn50xx;
475 struct cvmx_ipd_packet_mbuff_size_s cn52xx;
476 struct cvmx_ipd_packet_mbuff_size_s cn52xxp1;
477 struct cvmx_ipd_packet_mbuff_size_s cn56xx;
478 struct cvmx_ipd_packet_mbuff_size_s cn56xxp1;
479 struct cvmx_ipd_packet_mbuff_size_s cn58xx;
480 struct cvmx_ipd_packet_mbuff_size_s cn58xxp1;
481};
482
483union cvmx_ipd_pkt_ptr_valid {
484 uint64_t u64;
485 struct cvmx_ipd_pkt_ptr_valid_s {
486 uint64_t reserved_29_63:35;
487 uint64_t ptr:29;
488 } s;
489 struct cvmx_ipd_pkt_ptr_valid_s cn30xx;
490 struct cvmx_ipd_pkt_ptr_valid_s cn31xx;
491 struct cvmx_ipd_pkt_ptr_valid_s cn38xx;
492 struct cvmx_ipd_pkt_ptr_valid_s cn50xx;
493 struct cvmx_ipd_pkt_ptr_valid_s cn52xx;
494 struct cvmx_ipd_pkt_ptr_valid_s cn52xxp1;
495 struct cvmx_ipd_pkt_ptr_valid_s cn56xx;
496 struct cvmx_ipd_pkt_ptr_valid_s cn56xxp1;
497 struct cvmx_ipd_pkt_ptr_valid_s cn58xx;
498 struct cvmx_ipd_pkt_ptr_valid_s cn58xxp1;
499};
500
501union cvmx_ipd_portx_bp_page_cnt {
502 uint64_t u64;
503 struct cvmx_ipd_portx_bp_page_cnt_s {
504 uint64_t reserved_18_63:46;
505 uint64_t bp_enb:1;
506 uint64_t page_cnt:17;
507 } s;
508 struct cvmx_ipd_portx_bp_page_cnt_s cn30xx;
509 struct cvmx_ipd_portx_bp_page_cnt_s cn31xx;
510 struct cvmx_ipd_portx_bp_page_cnt_s cn38xx;
511 struct cvmx_ipd_portx_bp_page_cnt_s cn38xxp2;
512 struct cvmx_ipd_portx_bp_page_cnt_s cn50xx;
513 struct cvmx_ipd_portx_bp_page_cnt_s cn52xx;
514 struct cvmx_ipd_portx_bp_page_cnt_s cn52xxp1;
515 struct cvmx_ipd_portx_bp_page_cnt_s cn56xx;
516 struct cvmx_ipd_portx_bp_page_cnt_s cn56xxp1;
517 struct cvmx_ipd_portx_bp_page_cnt_s cn58xx;
518 struct cvmx_ipd_portx_bp_page_cnt_s cn58xxp1;
519};
520
521union cvmx_ipd_portx_bp_page_cnt2 {
522 uint64_t u64;
523 struct cvmx_ipd_portx_bp_page_cnt2_s {
524 uint64_t reserved_18_63:46;
525 uint64_t bp_enb:1;
526 uint64_t page_cnt:17;
527 } s;
528 struct cvmx_ipd_portx_bp_page_cnt2_s cn52xx;
529 struct cvmx_ipd_portx_bp_page_cnt2_s cn52xxp1;
530 struct cvmx_ipd_portx_bp_page_cnt2_s cn56xx;
531 struct cvmx_ipd_portx_bp_page_cnt2_s cn56xxp1;
532};
533
534union cvmx_ipd_port_bp_counters2_pairx {
535 uint64_t u64;
536 struct cvmx_ipd_port_bp_counters2_pairx_s {
537 uint64_t reserved_25_63:39;
538 uint64_t cnt_val:25;
539 } s;
540 struct cvmx_ipd_port_bp_counters2_pairx_s cn52xx;
541 struct cvmx_ipd_port_bp_counters2_pairx_s cn52xxp1;
542 struct cvmx_ipd_port_bp_counters2_pairx_s cn56xx;
543 struct cvmx_ipd_port_bp_counters2_pairx_s cn56xxp1;
544};
545
546union cvmx_ipd_port_bp_counters_pairx {
547 uint64_t u64;
548 struct cvmx_ipd_port_bp_counters_pairx_s {
549 uint64_t reserved_25_63:39;
550 uint64_t cnt_val:25;
551 } s;
552 struct cvmx_ipd_port_bp_counters_pairx_s cn30xx;
553 struct cvmx_ipd_port_bp_counters_pairx_s cn31xx;
554 struct cvmx_ipd_port_bp_counters_pairx_s cn38xx;
555 struct cvmx_ipd_port_bp_counters_pairx_s cn38xxp2;
556 struct cvmx_ipd_port_bp_counters_pairx_s cn50xx;
557 struct cvmx_ipd_port_bp_counters_pairx_s cn52xx;
558 struct cvmx_ipd_port_bp_counters_pairx_s cn52xxp1;
559 struct cvmx_ipd_port_bp_counters_pairx_s cn56xx;
560 struct cvmx_ipd_port_bp_counters_pairx_s cn56xxp1;
561 struct cvmx_ipd_port_bp_counters_pairx_s cn58xx;
562 struct cvmx_ipd_port_bp_counters_pairx_s cn58xxp1;
563};
564
565union cvmx_ipd_port_qos_x_cnt {
566 uint64_t u64;
567 struct cvmx_ipd_port_qos_x_cnt_s {
568 uint64_t wmark:32;
569 uint64_t cnt:32;
570 } s;
571 struct cvmx_ipd_port_qos_x_cnt_s cn52xx;
572 struct cvmx_ipd_port_qos_x_cnt_s cn52xxp1;
573 struct cvmx_ipd_port_qos_x_cnt_s cn56xx;
574 struct cvmx_ipd_port_qos_x_cnt_s cn56xxp1;
575};
576
577union cvmx_ipd_port_qos_intx {
578 uint64_t u64;
579 struct cvmx_ipd_port_qos_intx_s {
580 uint64_t intr:64;
581 } s;
582 struct cvmx_ipd_port_qos_intx_s cn52xx;
583 struct cvmx_ipd_port_qos_intx_s cn52xxp1;
584 struct cvmx_ipd_port_qos_intx_s cn56xx;
585 struct cvmx_ipd_port_qos_intx_s cn56xxp1;
586};
587
588union cvmx_ipd_port_qos_int_enbx {
589 uint64_t u64;
590 struct cvmx_ipd_port_qos_int_enbx_s {
591 uint64_t enb:64;
592 } s;
593 struct cvmx_ipd_port_qos_int_enbx_s cn52xx;
594 struct cvmx_ipd_port_qos_int_enbx_s cn52xxp1;
595 struct cvmx_ipd_port_qos_int_enbx_s cn56xx;
596 struct cvmx_ipd_port_qos_int_enbx_s cn56xxp1;
597};
598
599union cvmx_ipd_prc_hold_ptr_fifo_ctl {
600 uint64_t u64;
601 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s {
602 uint64_t reserved_39_63:25;
603 uint64_t max_pkt:3;
604 uint64_t praddr:3;
605 uint64_t ptr:29;
606 uint64_t cena:1;
607 uint64_t raddr:3;
608 } s;
609 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn30xx;
610 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn31xx;
611 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn38xx;
612 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn50xx;
613 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xx;
614 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn52xxp1;
615 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xx;
616 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn56xxp1;
617 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xx;
618 struct cvmx_ipd_prc_hold_ptr_fifo_ctl_s cn58xxp1;
619};
620
621union cvmx_ipd_prc_port_ptr_fifo_ctl {
622 uint64_t u64;
623 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s {
624 uint64_t reserved_44_63:20;
625 uint64_t max_pkt:7;
626 uint64_t ptr:29;
627 uint64_t cena:1;
628 uint64_t raddr:7;
629 } s;
630 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn30xx;
631 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn31xx;
632 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn38xx;
633 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn50xx;
634 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xx;
635 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn52xxp1;
636 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xx;
637 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn56xxp1;
638 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xx;
639 struct cvmx_ipd_prc_port_ptr_fifo_ctl_s cn58xxp1;
640};
641
642union cvmx_ipd_ptr_count {
643 uint64_t u64;
644 struct cvmx_ipd_ptr_count_s {
645 uint64_t reserved_19_63:45;
646 uint64_t pktv_cnt:1;
647 uint64_t wqev_cnt:1;
648 uint64_t pfif_cnt:3;
649 uint64_t pkt_pcnt:7;
650 uint64_t wqe_pcnt:7;
651 } s;
652 struct cvmx_ipd_ptr_count_s cn30xx;
653 struct cvmx_ipd_ptr_count_s cn31xx;
654 struct cvmx_ipd_ptr_count_s cn38xx;
655 struct cvmx_ipd_ptr_count_s cn38xxp2;
656 struct cvmx_ipd_ptr_count_s cn50xx;
657 struct cvmx_ipd_ptr_count_s cn52xx;
658 struct cvmx_ipd_ptr_count_s cn52xxp1;
659 struct cvmx_ipd_ptr_count_s cn56xx;
660 struct cvmx_ipd_ptr_count_s cn56xxp1;
661 struct cvmx_ipd_ptr_count_s cn58xx;
662 struct cvmx_ipd_ptr_count_s cn58xxp1;
663};
664
665union cvmx_ipd_pwp_ptr_fifo_ctl {
666 uint64_t u64;
667 struct cvmx_ipd_pwp_ptr_fifo_ctl_s {
668 uint64_t reserved_61_63:3;
669 uint64_t max_cnts:7;
670 uint64_t wraddr:8;
671 uint64_t praddr:8;
672 uint64_t ptr:29;
673 uint64_t cena:1;
674 uint64_t raddr:8;
675 } s;
676 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn30xx;
677 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn31xx;
678 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn38xx;
679 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn50xx;
680 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xx;
681 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn52xxp1;
682 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xx;
683 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn56xxp1;
684 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xx;
685 struct cvmx_ipd_pwp_ptr_fifo_ctl_s cn58xxp1;
686};
687
688union cvmx_ipd_qosx_red_marks {
689 uint64_t u64;
690 struct cvmx_ipd_qosx_red_marks_s {
691 uint64_t drop:32;
692 uint64_t pass:32;
693 } s;
694 struct cvmx_ipd_qosx_red_marks_s cn30xx;
695 struct cvmx_ipd_qosx_red_marks_s cn31xx;
696 struct cvmx_ipd_qosx_red_marks_s cn38xx;
697 struct cvmx_ipd_qosx_red_marks_s cn38xxp2;
698 struct cvmx_ipd_qosx_red_marks_s cn50xx;
699 struct cvmx_ipd_qosx_red_marks_s cn52xx;
700 struct cvmx_ipd_qosx_red_marks_s cn52xxp1;
701 struct cvmx_ipd_qosx_red_marks_s cn56xx;
702 struct cvmx_ipd_qosx_red_marks_s cn56xxp1;
703 struct cvmx_ipd_qosx_red_marks_s cn58xx;
704 struct cvmx_ipd_qosx_red_marks_s cn58xxp1;
705};
706
707union cvmx_ipd_que0_free_page_cnt {
708 uint64_t u64;
709 struct cvmx_ipd_que0_free_page_cnt_s {
710 uint64_t reserved_32_63:32;
711 uint64_t q0_pcnt:32;
712 } s;
713 struct cvmx_ipd_que0_free_page_cnt_s cn30xx;
714 struct cvmx_ipd_que0_free_page_cnt_s cn31xx;
715 struct cvmx_ipd_que0_free_page_cnt_s cn38xx;
716 struct cvmx_ipd_que0_free_page_cnt_s cn38xxp2;
717 struct cvmx_ipd_que0_free_page_cnt_s cn50xx;
718 struct cvmx_ipd_que0_free_page_cnt_s cn52xx;
719 struct cvmx_ipd_que0_free_page_cnt_s cn52xxp1;
720 struct cvmx_ipd_que0_free_page_cnt_s cn56xx;
721 struct cvmx_ipd_que0_free_page_cnt_s cn56xxp1;
722 struct cvmx_ipd_que0_free_page_cnt_s cn58xx;
723 struct cvmx_ipd_que0_free_page_cnt_s cn58xxp1;
724};
725
726union cvmx_ipd_red_port_enable {
727 uint64_t u64;
728 struct cvmx_ipd_red_port_enable_s {
729 uint64_t prb_dly:14;
730 uint64_t avg_dly:14;
731 uint64_t prt_enb:36;
732 } s;
733 struct cvmx_ipd_red_port_enable_s cn30xx;
734 struct cvmx_ipd_red_port_enable_s cn31xx;
735 struct cvmx_ipd_red_port_enable_s cn38xx;
736 struct cvmx_ipd_red_port_enable_s cn38xxp2;
737 struct cvmx_ipd_red_port_enable_s cn50xx;
738 struct cvmx_ipd_red_port_enable_s cn52xx;
739 struct cvmx_ipd_red_port_enable_s cn52xxp1;
740 struct cvmx_ipd_red_port_enable_s cn56xx;
741 struct cvmx_ipd_red_port_enable_s cn56xxp1;
742 struct cvmx_ipd_red_port_enable_s cn58xx;
743 struct cvmx_ipd_red_port_enable_s cn58xxp1;
744};
745
746union cvmx_ipd_red_port_enable2 {
747 uint64_t u64;
748 struct cvmx_ipd_red_port_enable2_s {
749 uint64_t reserved_4_63:60;
750 uint64_t prt_enb:4;
751 } s;
752 struct cvmx_ipd_red_port_enable2_s cn52xx;
753 struct cvmx_ipd_red_port_enable2_s cn52xxp1;
754 struct cvmx_ipd_red_port_enable2_s cn56xx;
755 struct cvmx_ipd_red_port_enable2_s cn56xxp1;
756};
757
758union cvmx_ipd_red_quex_param {
759 uint64_t u64;
760 struct cvmx_ipd_red_quex_param_s {
761 uint64_t reserved_49_63:15;
762 uint64_t use_pcnt:1;
763 uint64_t new_con:8;
764 uint64_t avg_con:8;
765 uint64_t prb_con:32;
766 } s;
767 struct cvmx_ipd_red_quex_param_s cn30xx;
768 struct cvmx_ipd_red_quex_param_s cn31xx;
769 struct cvmx_ipd_red_quex_param_s cn38xx;
770 struct cvmx_ipd_red_quex_param_s cn38xxp2;
771 struct cvmx_ipd_red_quex_param_s cn50xx;
772 struct cvmx_ipd_red_quex_param_s cn52xx;
773 struct cvmx_ipd_red_quex_param_s cn52xxp1;
774 struct cvmx_ipd_red_quex_param_s cn56xx;
775 struct cvmx_ipd_red_quex_param_s cn56xxp1;
776 struct cvmx_ipd_red_quex_param_s cn58xx;
777 struct cvmx_ipd_red_quex_param_s cn58xxp1;
778};
779
780union cvmx_ipd_sub_port_bp_page_cnt {
781 uint64_t u64;
782 struct cvmx_ipd_sub_port_bp_page_cnt_s {
783 uint64_t reserved_31_63:33;
784 uint64_t port:6;
785 uint64_t page_cnt:25;
786 } s;
787 struct cvmx_ipd_sub_port_bp_page_cnt_s cn30xx;
788 struct cvmx_ipd_sub_port_bp_page_cnt_s cn31xx;
789 struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xx;
790 struct cvmx_ipd_sub_port_bp_page_cnt_s cn38xxp2;
791 struct cvmx_ipd_sub_port_bp_page_cnt_s cn50xx;
792 struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xx;
793 struct cvmx_ipd_sub_port_bp_page_cnt_s cn52xxp1;
794 struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xx;
795 struct cvmx_ipd_sub_port_bp_page_cnt_s cn56xxp1;
796 struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xx;
797 struct cvmx_ipd_sub_port_bp_page_cnt_s cn58xxp1;
798};
799
800union cvmx_ipd_sub_port_fcs {
801 uint64_t u64;
802 struct cvmx_ipd_sub_port_fcs_s {
803 uint64_t reserved_40_63:24;
804 uint64_t port_bit2:4;
805 uint64_t reserved_32_35:4;
806 uint64_t port_bit:32;
807 } s;
808 struct cvmx_ipd_sub_port_fcs_cn30xx {
809 uint64_t reserved_3_63:61;
810 uint64_t port_bit:3;
811 } cn30xx;
812 struct cvmx_ipd_sub_port_fcs_cn30xx cn31xx;
813 struct cvmx_ipd_sub_port_fcs_cn38xx {
814 uint64_t reserved_32_63:32;
815 uint64_t port_bit:32;
816 } cn38xx;
817 struct cvmx_ipd_sub_port_fcs_cn38xx cn38xxp2;
818 struct cvmx_ipd_sub_port_fcs_cn30xx cn50xx;
819 struct cvmx_ipd_sub_port_fcs_s cn52xx;
820 struct cvmx_ipd_sub_port_fcs_s cn52xxp1;
821 struct cvmx_ipd_sub_port_fcs_s cn56xx;
822 struct cvmx_ipd_sub_port_fcs_s cn56xxp1;
823 struct cvmx_ipd_sub_port_fcs_cn38xx cn58xx;
824 struct cvmx_ipd_sub_port_fcs_cn38xx cn58xxp1;
825};
826
827union cvmx_ipd_sub_port_qos_cnt {
828 uint64_t u64;
829 struct cvmx_ipd_sub_port_qos_cnt_s {
830 uint64_t reserved_41_63:23;
831 uint64_t port_qos:9;
832 uint64_t cnt:32;
833 } s;
834 struct cvmx_ipd_sub_port_qos_cnt_s cn52xx;
835 struct cvmx_ipd_sub_port_qos_cnt_s cn52xxp1;
836 struct cvmx_ipd_sub_port_qos_cnt_s cn56xx;
837 struct cvmx_ipd_sub_port_qos_cnt_s cn56xxp1;
838};
839
840union cvmx_ipd_wqe_fpa_queue {
841 uint64_t u64;
842 struct cvmx_ipd_wqe_fpa_queue_s {
843 uint64_t reserved_3_63:61;
844 uint64_t wqe_pool:3;
845 } s;
846 struct cvmx_ipd_wqe_fpa_queue_s cn30xx;
847 struct cvmx_ipd_wqe_fpa_queue_s cn31xx;
848 struct cvmx_ipd_wqe_fpa_queue_s cn38xx;
849 struct cvmx_ipd_wqe_fpa_queue_s cn38xxp2;
850 struct cvmx_ipd_wqe_fpa_queue_s cn50xx;
851 struct cvmx_ipd_wqe_fpa_queue_s cn52xx;
852 struct cvmx_ipd_wqe_fpa_queue_s cn52xxp1;
853 struct cvmx_ipd_wqe_fpa_queue_s cn56xx;
854 struct cvmx_ipd_wqe_fpa_queue_s cn56xxp1;
855 struct cvmx_ipd_wqe_fpa_queue_s cn58xx;
856 struct cvmx_ipd_wqe_fpa_queue_s cn58xxp1;
857};
858
859union cvmx_ipd_wqe_ptr_valid {
860 uint64_t u64;
861 struct cvmx_ipd_wqe_ptr_valid_s {
862 uint64_t reserved_29_63:35;
863 uint64_t ptr:29;
864 } s;
865 struct cvmx_ipd_wqe_ptr_valid_s cn30xx;
866 struct cvmx_ipd_wqe_ptr_valid_s cn31xx;
867 struct cvmx_ipd_wqe_ptr_valid_s cn38xx;
868 struct cvmx_ipd_wqe_ptr_valid_s cn50xx;
869 struct cvmx_ipd_wqe_ptr_valid_s cn52xx;
870 struct cvmx_ipd_wqe_ptr_valid_s cn52xxp1;
871 struct cvmx_ipd_wqe_ptr_valid_s cn56xx;
872 struct cvmx_ipd_wqe_ptr_valid_s cn56xxp1;
873 struct cvmx_ipd_wqe_ptr_valid_s cn58xx;
874 struct cvmx_ipd_wqe_ptr_valid_s cn58xxp1;
875};
876
877#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c-defs.h b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
new file mode 100644
index 000000000000..337583842b51
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2c-defs.h
@@ -0,0 +1,963 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_L2C_DEFS_H__
29#define __CVMX_L2C_DEFS_H__
30
31#define CVMX_L2C_BST0 \
32 CVMX_ADD_IO_SEG(0x00011800800007F8ull)
33#define CVMX_L2C_BST1 \
34 CVMX_ADD_IO_SEG(0x00011800800007F0ull)
35#define CVMX_L2C_BST2 \
36 CVMX_ADD_IO_SEG(0x00011800800007E8ull)
37#define CVMX_L2C_CFG \
38 CVMX_ADD_IO_SEG(0x0001180080000000ull)
39#define CVMX_L2C_DBG \
40 CVMX_ADD_IO_SEG(0x0001180080000030ull)
41#define CVMX_L2C_DUT \
42 CVMX_ADD_IO_SEG(0x0001180080000050ull)
43#define CVMX_L2C_GRPWRR0 \
44 CVMX_ADD_IO_SEG(0x00011800800000C8ull)
45#define CVMX_L2C_GRPWRR1 \
46 CVMX_ADD_IO_SEG(0x00011800800000D0ull)
47#define CVMX_L2C_INT_EN \
48 CVMX_ADD_IO_SEG(0x0001180080000100ull)
49#define CVMX_L2C_INT_STAT \
50 CVMX_ADD_IO_SEG(0x00011800800000F8ull)
51#define CVMX_L2C_LCKBASE \
52 CVMX_ADD_IO_SEG(0x0001180080000058ull)
53#define CVMX_L2C_LCKOFF \
54 CVMX_ADD_IO_SEG(0x0001180080000060ull)
55#define CVMX_L2C_LFB0 \
56 CVMX_ADD_IO_SEG(0x0001180080000038ull)
57#define CVMX_L2C_LFB1 \
58 CVMX_ADD_IO_SEG(0x0001180080000040ull)
59#define CVMX_L2C_LFB2 \
60 CVMX_ADD_IO_SEG(0x0001180080000048ull)
61#define CVMX_L2C_LFB3 \
62 CVMX_ADD_IO_SEG(0x00011800800000B8ull)
63#define CVMX_L2C_OOB \
64 CVMX_ADD_IO_SEG(0x00011800800000D8ull)
65#define CVMX_L2C_OOB1 \
66 CVMX_ADD_IO_SEG(0x00011800800000E0ull)
67#define CVMX_L2C_OOB2 \
68 CVMX_ADD_IO_SEG(0x00011800800000E8ull)
69#define CVMX_L2C_OOB3 \
70 CVMX_ADD_IO_SEG(0x00011800800000F0ull)
71#define CVMX_L2C_PFC0 \
72 CVMX_ADD_IO_SEG(0x0001180080000098ull)
73#define CVMX_L2C_PFC1 \
74 CVMX_ADD_IO_SEG(0x00011800800000A0ull)
75#define CVMX_L2C_PFC2 \
76 CVMX_ADD_IO_SEG(0x00011800800000A8ull)
77#define CVMX_L2C_PFC3 \
78 CVMX_ADD_IO_SEG(0x00011800800000B0ull)
79#define CVMX_L2C_PFCTL \
80 CVMX_ADD_IO_SEG(0x0001180080000090ull)
81#define CVMX_L2C_PFCX(offset) \
82 CVMX_ADD_IO_SEG(0x0001180080000098ull + (((offset) & 3) * 8))
83#define CVMX_L2C_PPGRP \
84 CVMX_ADD_IO_SEG(0x00011800800000C0ull)
85#define CVMX_L2C_SPAR0 \
86 CVMX_ADD_IO_SEG(0x0001180080000068ull)
87#define CVMX_L2C_SPAR1 \
88 CVMX_ADD_IO_SEG(0x0001180080000070ull)
89#define CVMX_L2C_SPAR2 \
90 CVMX_ADD_IO_SEG(0x0001180080000078ull)
91#define CVMX_L2C_SPAR3 \
92 CVMX_ADD_IO_SEG(0x0001180080000080ull)
93#define CVMX_L2C_SPAR4 \
94 CVMX_ADD_IO_SEG(0x0001180080000088ull)
95
96union cvmx_l2c_bst0 {
97 uint64_t u64;
98 struct cvmx_l2c_bst0_s {
99 uint64_t reserved_24_63:40;
100 uint64_t dtbnk:1;
101 uint64_t wlb_msk:4;
102 uint64_t dtcnt:13;
103 uint64_t dt:1;
104 uint64_t stin_msk:1;
105 uint64_t wlb_dat:4;
106 } s;
107 struct cvmx_l2c_bst0_cn30xx {
108 uint64_t reserved_23_63:41;
109 uint64_t wlb_msk:4;
110 uint64_t reserved_15_18:4;
111 uint64_t dtcnt:9;
112 uint64_t dt:1;
113 uint64_t reserved_4_4:1;
114 uint64_t wlb_dat:4;
115 } cn30xx;
116 struct cvmx_l2c_bst0_cn31xx {
117 uint64_t reserved_23_63:41;
118 uint64_t wlb_msk:4;
119 uint64_t reserved_16_18:3;
120 uint64_t dtcnt:10;
121 uint64_t dt:1;
122 uint64_t stin_msk:1;
123 uint64_t wlb_dat:4;
124 } cn31xx;
125 struct cvmx_l2c_bst0_cn38xx {
126 uint64_t reserved_19_63:45;
127 uint64_t dtcnt:13;
128 uint64_t dt:1;
129 uint64_t stin_msk:1;
130 uint64_t wlb_dat:4;
131 } cn38xx;
132 struct cvmx_l2c_bst0_cn38xx cn38xxp2;
133 struct cvmx_l2c_bst0_cn50xx {
134 uint64_t reserved_24_63:40;
135 uint64_t dtbnk:1;
136 uint64_t wlb_msk:4;
137 uint64_t reserved_16_18:3;
138 uint64_t dtcnt:10;
139 uint64_t dt:1;
140 uint64_t stin_msk:1;
141 uint64_t wlb_dat:4;
142 } cn50xx;
143 struct cvmx_l2c_bst0_cn50xx cn52xx;
144 struct cvmx_l2c_bst0_cn50xx cn52xxp1;
145 struct cvmx_l2c_bst0_s cn56xx;
146 struct cvmx_l2c_bst0_s cn56xxp1;
147 struct cvmx_l2c_bst0_s cn58xx;
148 struct cvmx_l2c_bst0_s cn58xxp1;
149};
150
151union cvmx_l2c_bst1 {
152 uint64_t u64;
153 struct cvmx_l2c_bst1_s {
154 uint64_t reserved_9_63:55;
155 uint64_t l2t:9;
156 } s;
157 struct cvmx_l2c_bst1_cn30xx {
158 uint64_t reserved_16_63:48;
159 uint64_t vwdf:4;
160 uint64_t lrf:2;
161 uint64_t vab_vwcf:1;
162 uint64_t reserved_5_8:4;
163 uint64_t l2t:5;
164 } cn30xx;
165 struct cvmx_l2c_bst1_cn30xx cn31xx;
166 struct cvmx_l2c_bst1_cn38xx {
167 uint64_t reserved_16_63:48;
168 uint64_t vwdf:4;
169 uint64_t lrf:2;
170 uint64_t vab_vwcf:1;
171 uint64_t l2t:9;
172 } cn38xx;
173 struct cvmx_l2c_bst1_cn38xx cn38xxp2;
174 struct cvmx_l2c_bst1_cn38xx cn50xx;
175 struct cvmx_l2c_bst1_cn52xx {
176 uint64_t reserved_19_63:45;
177 uint64_t plc2:1;
178 uint64_t plc1:1;
179 uint64_t plc0:1;
180 uint64_t vwdf:4;
181 uint64_t reserved_11_11:1;
182 uint64_t ilc:1;
183 uint64_t vab_vwcf:1;
184 uint64_t l2t:9;
185 } cn52xx;
186 struct cvmx_l2c_bst1_cn52xx cn52xxp1;
187 struct cvmx_l2c_bst1_cn56xx {
188 uint64_t reserved_24_63:40;
189 uint64_t plc2:1;
190 uint64_t plc1:1;
191 uint64_t plc0:1;
192 uint64_t ilc:1;
193 uint64_t vwdf1:4;
194 uint64_t vwdf0:4;
195 uint64_t vab_vwcf1:1;
196 uint64_t reserved_10_10:1;
197 uint64_t vab_vwcf0:1;
198 uint64_t l2t:9;
199 } cn56xx;
200 struct cvmx_l2c_bst1_cn56xx cn56xxp1;
201 struct cvmx_l2c_bst1_cn38xx cn58xx;
202 struct cvmx_l2c_bst1_cn38xx cn58xxp1;
203};
204
205union cvmx_l2c_bst2 {
206 uint64_t u64;
207 struct cvmx_l2c_bst2_s {
208 uint64_t reserved_16_63:48;
209 uint64_t mrb:4;
210 uint64_t reserved_4_11:8;
211 uint64_t ipcbst:1;
212 uint64_t picbst:1;
213 uint64_t xrdmsk:1;
214 uint64_t xrddat:1;
215 } s;
216 struct cvmx_l2c_bst2_cn30xx {
217 uint64_t reserved_16_63:48;
218 uint64_t mrb:4;
219 uint64_t rmdf:4;
220 uint64_t reserved_4_7:4;
221 uint64_t ipcbst:1;
222 uint64_t reserved_2_2:1;
223 uint64_t xrdmsk:1;
224 uint64_t xrddat:1;
225 } cn30xx;
226 struct cvmx_l2c_bst2_cn30xx cn31xx;
227 struct cvmx_l2c_bst2_cn38xx {
228 uint64_t reserved_16_63:48;
229 uint64_t mrb:4;
230 uint64_t rmdf:4;
231 uint64_t rhdf:4;
232 uint64_t ipcbst:1;
233 uint64_t picbst:1;
234 uint64_t xrdmsk:1;
235 uint64_t xrddat:1;
236 } cn38xx;
237 struct cvmx_l2c_bst2_cn38xx cn38xxp2;
238 struct cvmx_l2c_bst2_cn30xx cn50xx;
239 struct cvmx_l2c_bst2_cn30xx cn52xx;
240 struct cvmx_l2c_bst2_cn30xx cn52xxp1;
241 struct cvmx_l2c_bst2_cn56xx {
242 uint64_t reserved_16_63:48;
243 uint64_t mrb:4;
244 uint64_t rmdb:4;
245 uint64_t rhdb:4;
246 uint64_t ipcbst:1;
247 uint64_t picbst:1;
248 uint64_t xrdmsk:1;
249 uint64_t xrddat:1;
250 } cn56xx;
251 struct cvmx_l2c_bst2_cn56xx cn56xxp1;
252 struct cvmx_l2c_bst2_cn56xx cn58xx;
253 struct cvmx_l2c_bst2_cn56xx cn58xxp1;
254};
255
256union cvmx_l2c_cfg {
257 uint64_t u64;
258 struct cvmx_l2c_cfg_s {
259 uint64_t reserved_20_63:44;
260 uint64_t bstrun:1;
261 uint64_t lbist:1;
262 uint64_t xor_bank:1;
263 uint64_t dpres1:1;
264 uint64_t dpres0:1;
265 uint64_t dfill_dis:1;
266 uint64_t fpexp:4;
267 uint64_t fpempty:1;
268 uint64_t fpen:1;
269 uint64_t idxalias:1;
270 uint64_t mwf_crd:4;
271 uint64_t rsp_arb_mode:1;
272 uint64_t rfb_arb_mode:1;
273 uint64_t lrf_arb_mode:1;
274 } s;
275 struct cvmx_l2c_cfg_cn30xx {
276 uint64_t reserved_14_63:50;
277 uint64_t fpexp:4;
278 uint64_t fpempty:1;
279 uint64_t fpen:1;
280 uint64_t idxalias:1;
281 uint64_t mwf_crd:4;
282 uint64_t rsp_arb_mode:1;
283 uint64_t rfb_arb_mode:1;
284 uint64_t lrf_arb_mode:1;
285 } cn30xx;
286 struct cvmx_l2c_cfg_cn30xx cn31xx;
287 struct cvmx_l2c_cfg_cn30xx cn38xx;
288 struct cvmx_l2c_cfg_cn30xx cn38xxp2;
289 struct cvmx_l2c_cfg_cn50xx {
290 uint64_t reserved_20_63:44;
291 uint64_t bstrun:1;
292 uint64_t lbist:1;
293 uint64_t reserved_14_17:4;
294 uint64_t fpexp:4;
295 uint64_t fpempty:1;
296 uint64_t fpen:1;
297 uint64_t idxalias:1;
298 uint64_t mwf_crd:4;
299 uint64_t rsp_arb_mode:1;
300 uint64_t rfb_arb_mode:1;
301 uint64_t lrf_arb_mode:1;
302 } cn50xx;
303 struct cvmx_l2c_cfg_cn50xx cn52xx;
304 struct cvmx_l2c_cfg_cn50xx cn52xxp1;
305 struct cvmx_l2c_cfg_s cn56xx;
306 struct cvmx_l2c_cfg_s cn56xxp1;
307 struct cvmx_l2c_cfg_cn58xx {
308 uint64_t reserved_20_63:44;
309 uint64_t bstrun:1;
310 uint64_t lbist:1;
311 uint64_t reserved_15_17:3;
312 uint64_t dfill_dis:1;
313 uint64_t fpexp:4;
314 uint64_t fpempty:1;
315 uint64_t fpen:1;
316 uint64_t idxalias:1;
317 uint64_t mwf_crd:4;
318 uint64_t rsp_arb_mode:1;
319 uint64_t rfb_arb_mode:1;
320 uint64_t lrf_arb_mode:1;
321 } cn58xx;
322 struct cvmx_l2c_cfg_cn58xxp1 {
323 uint64_t reserved_15_63:49;
324 uint64_t dfill_dis:1;
325 uint64_t fpexp:4;
326 uint64_t fpempty:1;
327 uint64_t fpen:1;
328 uint64_t idxalias:1;
329 uint64_t mwf_crd:4;
330 uint64_t rsp_arb_mode:1;
331 uint64_t rfb_arb_mode:1;
332 uint64_t lrf_arb_mode:1;
333 } cn58xxp1;
334};
335
336union cvmx_l2c_dbg {
337 uint64_t u64;
338 struct cvmx_l2c_dbg_s {
339 uint64_t reserved_15_63:49;
340 uint64_t lfb_enum:4;
341 uint64_t lfb_dmp:1;
342 uint64_t ppnum:4;
343 uint64_t set:3;
344 uint64_t finv:1;
345 uint64_t l2d:1;
346 uint64_t l2t:1;
347 } s;
348 struct cvmx_l2c_dbg_cn30xx {
349 uint64_t reserved_13_63:51;
350 uint64_t lfb_enum:2;
351 uint64_t lfb_dmp:1;
352 uint64_t reserved_5_9:5;
353 uint64_t set:2;
354 uint64_t finv:1;
355 uint64_t l2d:1;
356 uint64_t l2t:1;
357 } cn30xx;
358 struct cvmx_l2c_dbg_cn31xx {
359 uint64_t reserved_14_63:50;
360 uint64_t lfb_enum:3;
361 uint64_t lfb_dmp:1;
362 uint64_t reserved_7_9:3;
363 uint64_t ppnum:1;
364 uint64_t reserved_5_5:1;
365 uint64_t set:2;
366 uint64_t finv:1;
367 uint64_t l2d:1;
368 uint64_t l2t:1;
369 } cn31xx;
370 struct cvmx_l2c_dbg_s cn38xx;
371 struct cvmx_l2c_dbg_s cn38xxp2;
372 struct cvmx_l2c_dbg_cn50xx {
373 uint64_t reserved_14_63:50;
374 uint64_t lfb_enum:3;
375 uint64_t lfb_dmp:1;
376 uint64_t reserved_7_9:3;
377 uint64_t ppnum:1;
378 uint64_t set:3;
379 uint64_t finv:1;
380 uint64_t l2d:1;
381 uint64_t l2t:1;
382 } cn50xx;
383 struct cvmx_l2c_dbg_cn52xx {
384 uint64_t reserved_14_63:50;
385 uint64_t lfb_enum:3;
386 uint64_t lfb_dmp:1;
387 uint64_t reserved_8_9:2;
388 uint64_t ppnum:2;
389 uint64_t set:3;
390 uint64_t finv:1;
391 uint64_t l2d:1;
392 uint64_t l2t:1;
393 } cn52xx;
394 struct cvmx_l2c_dbg_cn52xx cn52xxp1;
395 struct cvmx_l2c_dbg_s cn56xx;
396 struct cvmx_l2c_dbg_s cn56xxp1;
397 struct cvmx_l2c_dbg_s cn58xx;
398 struct cvmx_l2c_dbg_s cn58xxp1;
399};
400
401union cvmx_l2c_dut {
402 uint64_t u64;
403 struct cvmx_l2c_dut_s {
404 uint64_t reserved_32_63:32;
405 uint64_t dtena:1;
406 uint64_t reserved_30_30:1;
407 uint64_t dt_vld:1;
408 uint64_t dt_tag:29;
409 } s;
410 struct cvmx_l2c_dut_s cn30xx;
411 struct cvmx_l2c_dut_s cn31xx;
412 struct cvmx_l2c_dut_s cn38xx;
413 struct cvmx_l2c_dut_s cn38xxp2;
414 struct cvmx_l2c_dut_s cn50xx;
415 struct cvmx_l2c_dut_s cn52xx;
416 struct cvmx_l2c_dut_s cn52xxp1;
417 struct cvmx_l2c_dut_s cn56xx;
418 struct cvmx_l2c_dut_s cn56xxp1;
419 struct cvmx_l2c_dut_s cn58xx;
420 struct cvmx_l2c_dut_s cn58xxp1;
421};
422
423union cvmx_l2c_grpwrr0 {
424 uint64_t u64;
425 struct cvmx_l2c_grpwrr0_s {
426 uint64_t plc1rmsk:32;
427 uint64_t plc0rmsk:32;
428 } s;
429 struct cvmx_l2c_grpwrr0_s cn52xx;
430 struct cvmx_l2c_grpwrr0_s cn52xxp1;
431 struct cvmx_l2c_grpwrr0_s cn56xx;
432 struct cvmx_l2c_grpwrr0_s cn56xxp1;
433};
434
435union cvmx_l2c_grpwrr1 {
436 uint64_t u64;
437 struct cvmx_l2c_grpwrr1_s {
438 uint64_t ilcrmsk:32;
439 uint64_t plc2rmsk:32;
440 } s;
441 struct cvmx_l2c_grpwrr1_s cn52xx;
442 struct cvmx_l2c_grpwrr1_s cn52xxp1;
443 struct cvmx_l2c_grpwrr1_s cn56xx;
444 struct cvmx_l2c_grpwrr1_s cn56xxp1;
445};
446
447union cvmx_l2c_int_en {
448 uint64_t u64;
449 struct cvmx_l2c_int_en_s {
450 uint64_t reserved_9_63:55;
451 uint64_t lck2ena:1;
452 uint64_t lckena:1;
453 uint64_t l2ddeden:1;
454 uint64_t l2dsecen:1;
455 uint64_t l2tdeden:1;
456 uint64_t l2tsecen:1;
457 uint64_t oob3en:1;
458 uint64_t oob2en:1;
459 uint64_t oob1en:1;
460 } s;
461 struct cvmx_l2c_int_en_s cn52xx;
462 struct cvmx_l2c_int_en_s cn52xxp1;
463 struct cvmx_l2c_int_en_s cn56xx;
464 struct cvmx_l2c_int_en_s cn56xxp1;
465};
466
467union cvmx_l2c_int_stat {
468 uint64_t u64;
469 struct cvmx_l2c_int_stat_s {
470 uint64_t reserved_9_63:55;
471 uint64_t lck2:1;
472 uint64_t lck:1;
473 uint64_t l2dded:1;
474 uint64_t l2dsec:1;
475 uint64_t l2tded:1;
476 uint64_t l2tsec:1;
477 uint64_t oob3:1;
478 uint64_t oob2:1;
479 uint64_t oob1:1;
480 } s;
481 struct cvmx_l2c_int_stat_s cn52xx;
482 struct cvmx_l2c_int_stat_s cn52xxp1;
483 struct cvmx_l2c_int_stat_s cn56xx;
484 struct cvmx_l2c_int_stat_s cn56xxp1;
485};
486
487union cvmx_l2c_lckbase {
488 uint64_t u64;
489 struct cvmx_l2c_lckbase_s {
490 uint64_t reserved_31_63:33;
491 uint64_t lck_base:27;
492 uint64_t reserved_1_3:3;
493 uint64_t lck_ena:1;
494 } s;
495 struct cvmx_l2c_lckbase_s cn30xx;
496 struct cvmx_l2c_lckbase_s cn31xx;
497 struct cvmx_l2c_lckbase_s cn38xx;
498 struct cvmx_l2c_lckbase_s cn38xxp2;
499 struct cvmx_l2c_lckbase_s cn50xx;
500 struct cvmx_l2c_lckbase_s cn52xx;
501 struct cvmx_l2c_lckbase_s cn52xxp1;
502 struct cvmx_l2c_lckbase_s cn56xx;
503 struct cvmx_l2c_lckbase_s cn56xxp1;
504 struct cvmx_l2c_lckbase_s cn58xx;
505 struct cvmx_l2c_lckbase_s cn58xxp1;
506};
507
508union cvmx_l2c_lckoff {
509 uint64_t u64;
510 struct cvmx_l2c_lckoff_s {
511 uint64_t reserved_10_63:54;
512 uint64_t lck_offset:10;
513 } s;
514 struct cvmx_l2c_lckoff_s cn30xx;
515 struct cvmx_l2c_lckoff_s cn31xx;
516 struct cvmx_l2c_lckoff_s cn38xx;
517 struct cvmx_l2c_lckoff_s cn38xxp2;
518 struct cvmx_l2c_lckoff_s cn50xx;
519 struct cvmx_l2c_lckoff_s cn52xx;
520 struct cvmx_l2c_lckoff_s cn52xxp1;
521 struct cvmx_l2c_lckoff_s cn56xx;
522 struct cvmx_l2c_lckoff_s cn56xxp1;
523 struct cvmx_l2c_lckoff_s cn58xx;
524 struct cvmx_l2c_lckoff_s cn58xxp1;
525};
526
527union cvmx_l2c_lfb0 {
528 uint64_t u64;
529 struct cvmx_l2c_lfb0_s {
530 uint64_t reserved_32_63:32;
531 uint64_t stcpnd:1;
532 uint64_t stpnd:1;
533 uint64_t stinv:1;
534 uint64_t stcfl:1;
535 uint64_t vam:1;
536 uint64_t inxt:4;
537 uint64_t itl:1;
538 uint64_t ihd:1;
539 uint64_t set:3;
540 uint64_t vabnum:4;
541 uint64_t sid:9;
542 uint64_t cmd:4;
543 uint64_t vld:1;
544 } s;
545 struct cvmx_l2c_lfb0_cn30xx {
546 uint64_t reserved_32_63:32;
547 uint64_t stcpnd:1;
548 uint64_t stpnd:1;
549 uint64_t stinv:1;
550 uint64_t stcfl:1;
551 uint64_t vam:1;
552 uint64_t reserved_25_26:2;
553 uint64_t inxt:2;
554 uint64_t itl:1;
555 uint64_t ihd:1;
556 uint64_t reserved_20_20:1;
557 uint64_t set:2;
558 uint64_t reserved_16_17:2;
559 uint64_t vabnum:2;
560 uint64_t sid:9;
561 uint64_t cmd:4;
562 uint64_t vld:1;
563 } cn30xx;
564 struct cvmx_l2c_lfb0_cn31xx {
565 uint64_t reserved_32_63:32;
566 uint64_t stcpnd:1;
567 uint64_t stpnd:1;
568 uint64_t stinv:1;
569 uint64_t stcfl:1;
570 uint64_t vam:1;
571 uint64_t reserved_26_26:1;
572 uint64_t inxt:3;
573 uint64_t itl:1;
574 uint64_t ihd:1;
575 uint64_t reserved_20_20:1;
576 uint64_t set:2;
577 uint64_t reserved_17_17:1;
578 uint64_t vabnum:3;
579 uint64_t sid:9;
580 uint64_t cmd:4;
581 uint64_t vld:1;
582 } cn31xx;
583 struct cvmx_l2c_lfb0_s cn38xx;
584 struct cvmx_l2c_lfb0_s cn38xxp2;
585 struct cvmx_l2c_lfb0_cn50xx {
586 uint64_t reserved_32_63:32;
587 uint64_t stcpnd:1;
588 uint64_t stpnd:1;
589 uint64_t stinv:1;
590 uint64_t stcfl:1;
591 uint64_t vam:1;
592 uint64_t reserved_26_26:1;
593 uint64_t inxt:3;
594 uint64_t itl:1;
595 uint64_t ihd:1;
596 uint64_t set:3;
597 uint64_t reserved_17_17:1;
598 uint64_t vabnum:3;
599 uint64_t sid:9;
600 uint64_t cmd:4;
601 uint64_t vld:1;
602 } cn50xx;
603 struct cvmx_l2c_lfb0_cn50xx cn52xx;
604 struct cvmx_l2c_lfb0_cn50xx cn52xxp1;
605 struct cvmx_l2c_lfb0_s cn56xx;
606 struct cvmx_l2c_lfb0_s cn56xxp1;
607 struct cvmx_l2c_lfb0_s cn58xx;
608 struct cvmx_l2c_lfb0_s cn58xxp1;
609};
610
611union cvmx_l2c_lfb1 {
612 uint64_t u64;
613 struct cvmx_l2c_lfb1_s {
614 uint64_t reserved_19_63:45;
615 uint64_t dsgoing:1;
616 uint64_t bid:2;
617 uint64_t wtrsp:1;
618 uint64_t wtdw:1;
619 uint64_t wtdq:1;
620 uint64_t wtwhp:1;
621 uint64_t wtwhf:1;
622 uint64_t wtwrm:1;
623 uint64_t wtstm:1;
624 uint64_t wtrda:1;
625 uint64_t wtstdt:1;
626 uint64_t wtstrsp:1;
627 uint64_t wtstrsc:1;
628 uint64_t wtvtm:1;
629 uint64_t wtmfl:1;
630 uint64_t prbrty:1;
631 uint64_t wtprb:1;
632 uint64_t vld:1;
633 } s;
634 struct cvmx_l2c_lfb1_s cn30xx;
635 struct cvmx_l2c_lfb1_s cn31xx;
636 struct cvmx_l2c_lfb1_s cn38xx;
637 struct cvmx_l2c_lfb1_s cn38xxp2;
638 struct cvmx_l2c_lfb1_s cn50xx;
639 struct cvmx_l2c_lfb1_s cn52xx;
640 struct cvmx_l2c_lfb1_s cn52xxp1;
641 struct cvmx_l2c_lfb1_s cn56xx;
642 struct cvmx_l2c_lfb1_s cn56xxp1;
643 struct cvmx_l2c_lfb1_s cn58xx;
644 struct cvmx_l2c_lfb1_s cn58xxp1;
645};
646
647union cvmx_l2c_lfb2 {
648 uint64_t u64;
649 struct cvmx_l2c_lfb2_s {
650 uint64_t reserved_0_63:64;
651 } s;
652 struct cvmx_l2c_lfb2_cn30xx {
653 uint64_t reserved_27_63:37;
654 uint64_t lfb_tag:19;
655 uint64_t lfb_idx:8;
656 } cn30xx;
657 struct cvmx_l2c_lfb2_cn31xx {
658 uint64_t reserved_27_63:37;
659 uint64_t lfb_tag:17;
660 uint64_t lfb_idx:10;
661 } cn31xx;
662 struct cvmx_l2c_lfb2_cn31xx cn38xx;
663 struct cvmx_l2c_lfb2_cn31xx cn38xxp2;
664 struct cvmx_l2c_lfb2_cn50xx {
665 uint64_t reserved_27_63:37;
666 uint64_t lfb_tag:20;
667 uint64_t lfb_idx:7;
668 } cn50xx;
669 struct cvmx_l2c_lfb2_cn52xx {
670 uint64_t reserved_27_63:37;
671 uint64_t lfb_tag:18;
672 uint64_t lfb_idx:9;
673 } cn52xx;
674 struct cvmx_l2c_lfb2_cn52xx cn52xxp1;
675 struct cvmx_l2c_lfb2_cn56xx {
676 uint64_t reserved_27_63:37;
677 uint64_t lfb_tag:16;
678 uint64_t lfb_idx:11;
679 } cn56xx;
680 struct cvmx_l2c_lfb2_cn56xx cn56xxp1;
681 struct cvmx_l2c_lfb2_cn56xx cn58xx;
682 struct cvmx_l2c_lfb2_cn56xx cn58xxp1;
683};
684
685union cvmx_l2c_lfb3 {
686 uint64_t u64;
687 struct cvmx_l2c_lfb3_s {
688 uint64_t reserved_5_63:59;
689 uint64_t stpartdis:1;
690 uint64_t lfb_hwm:4;
691 } s;
692 struct cvmx_l2c_lfb3_cn30xx {
693 uint64_t reserved_5_63:59;
694 uint64_t stpartdis:1;
695 uint64_t reserved_2_3:2;
696 uint64_t lfb_hwm:2;
697 } cn30xx;
698 struct cvmx_l2c_lfb3_cn31xx {
699 uint64_t reserved_5_63:59;
700 uint64_t stpartdis:1;
701 uint64_t reserved_3_3:1;
702 uint64_t lfb_hwm:3;
703 } cn31xx;
704 struct cvmx_l2c_lfb3_s cn38xx;
705 struct cvmx_l2c_lfb3_s cn38xxp2;
706 struct cvmx_l2c_lfb3_cn31xx cn50xx;
707 struct cvmx_l2c_lfb3_cn31xx cn52xx;
708 struct cvmx_l2c_lfb3_cn31xx cn52xxp1;
709 struct cvmx_l2c_lfb3_s cn56xx;
710 struct cvmx_l2c_lfb3_s cn56xxp1;
711 struct cvmx_l2c_lfb3_s cn58xx;
712 struct cvmx_l2c_lfb3_s cn58xxp1;
713};
714
715union cvmx_l2c_oob {
716 uint64_t u64;
717 struct cvmx_l2c_oob_s {
718 uint64_t reserved_2_63:62;
719 uint64_t dwbena:1;
720 uint64_t stena:1;
721 } s;
722 struct cvmx_l2c_oob_s cn52xx;
723 struct cvmx_l2c_oob_s cn52xxp1;
724 struct cvmx_l2c_oob_s cn56xx;
725 struct cvmx_l2c_oob_s cn56xxp1;
726};
727
728union cvmx_l2c_oob1 {
729 uint64_t u64;
730 struct cvmx_l2c_oob1_s {
731 uint64_t fadr:27;
732 uint64_t fsrc:1;
733 uint64_t reserved_34_35:2;
734 uint64_t sadr:14;
735 uint64_t reserved_14_19:6;
736 uint64_t size:14;
737 } s;
738 struct cvmx_l2c_oob1_s cn52xx;
739 struct cvmx_l2c_oob1_s cn52xxp1;
740 struct cvmx_l2c_oob1_s cn56xx;
741 struct cvmx_l2c_oob1_s cn56xxp1;
742};
743
744union cvmx_l2c_oob2 {
745 uint64_t u64;
746 struct cvmx_l2c_oob2_s {
747 uint64_t fadr:27;
748 uint64_t fsrc:1;
749 uint64_t reserved_34_35:2;
750 uint64_t sadr:14;
751 uint64_t reserved_14_19:6;
752 uint64_t size:14;
753 } s;
754 struct cvmx_l2c_oob2_s cn52xx;
755 struct cvmx_l2c_oob2_s cn52xxp1;
756 struct cvmx_l2c_oob2_s cn56xx;
757 struct cvmx_l2c_oob2_s cn56xxp1;
758};
759
760union cvmx_l2c_oob3 {
761 uint64_t u64;
762 struct cvmx_l2c_oob3_s {
763 uint64_t fadr:27;
764 uint64_t fsrc:1;
765 uint64_t reserved_34_35:2;
766 uint64_t sadr:14;
767 uint64_t reserved_14_19:6;
768 uint64_t size:14;
769 } s;
770 struct cvmx_l2c_oob3_s cn52xx;
771 struct cvmx_l2c_oob3_s cn52xxp1;
772 struct cvmx_l2c_oob3_s cn56xx;
773 struct cvmx_l2c_oob3_s cn56xxp1;
774};
775
776union cvmx_l2c_pfcx {
777 uint64_t u64;
778 struct cvmx_l2c_pfcx_s {
779 uint64_t reserved_36_63:28;
780 uint64_t pfcnt0:36;
781 } s;
782 struct cvmx_l2c_pfcx_s cn30xx;
783 struct cvmx_l2c_pfcx_s cn31xx;
784 struct cvmx_l2c_pfcx_s cn38xx;
785 struct cvmx_l2c_pfcx_s cn38xxp2;
786 struct cvmx_l2c_pfcx_s cn50xx;
787 struct cvmx_l2c_pfcx_s cn52xx;
788 struct cvmx_l2c_pfcx_s cn52xxp1;
789 struct cvmx_l2c_pfcx_s cn56xx;
790 struct cvmx_l2c_pfcx_s cn56xxp1;
791 struct cvmx_l2c_pfcx_s cn58xx;
792 struct cvmx_l2c_pfcx_s cn58xxp1;
793};
794
795union cvmx_l2c_pfctl {
796 uint64_t u64;
797 struct cvmx_l2c_pfctl_s {
798 uint64_t reserved_36_63:28;
799 uint64_t cnt3rdclr:1;
800 uint64_t cnt2rdclr:1;
801 uint64_t cnt1rdclr:1;
802 uint64_t cnt0rdclr:1;
803 uint64_t cnt3ena:1;
804 uint64_t cnt3clr:1;
805 uint64_t cnt3sel:6;
806 uint64_t cnt2ena:1;
807 uint64_t cnt2clr:1;
808 uint64_t cnt2sel:6;
809 uint64_t cnt1ena:1;
810 uint64_t cnt1clr:1;
811 uint64_t cnt1sel:6;
812 uint64_t cnt0ena:1;
813 uint64_t cnt0clr:1;
814 uint64_t cnt0sel:6;
815 } s;
816 struct cvmx_l2c_pfctl_s cn30xx;
817 struct cvmx_l2c_pfctl_s cn31xx;
818 struct cvmx_l2c_pfctl_s cn38xx;
819 struct cvmx_l2c_pfctl_s cn38xxp2;
820 struct cvmx_l2c_pfctl_s cn50xx;
821 struct cvmx_l2c_pfctl_s cn52xx;
822 struct cvmx_l2c_pfctl_s cn52xxp1;
823 struct cvmx_l2c_pfctl_s cn56xx;
824 struct cvmx_l2c_pfctl_s cn56xxp1;
825 struct cvmx_l2c_pfctl_s cn58xx;
826 struct cvmx_l2c_pfctl_s cn58xxp1;
827};
828
829union cvmx_l2c_ppgrp {
830 uint64_t u64;
831 struct cvmx_l2c_ppgrp_s {
832 uint64_t reserved_24_63:40;
833 uint64_t pp11grp:2;
834 uint64_t pp10grp:2;
835 uint64_t pp9grp:2;
836 uint64_t pp8grp:2;
837 uint64_t pp7grp:2;
838 uint64_t pp6grp:2;
839 uint64_t pp5grp:2;
840 uint64_t pp4grp:2;
841 uint64_t pp3grp:2;
842 uint64_t pp2grp:2;
843 uint64_t pp1grp:2;
844 uint64_t pp0grp:2;
845 } s;
846 struct cvmx_l2c_ppgrp_cn52xx {
847 uint64_t reserved_8_63:56;
848 uint64_t pp3grp:2;
849 uint64_t pp2grp:2;
850 uint64_t pp1grp:2;
851 uint64_t pp0grp:2;
852 } cn52xx;
853 struct cvmx_l2c_ppgrp_cn52xx cn52xxp1;
854 struct cvmx_l2c_ppgrp_s cn56xx;
855 struct cvmx_l2c_ppgrp_s cn56xxp1;
856};
857
858union cvmx_l2c_spar0 {
859 uint64_t u64;
860 struct cvmx_l2c_spar0_s {
861 uint64_t reserved_32_63:32;
862 uint64_t umsk3:8;
863 uint64_t umsk2:8;
864 uint64_t umsk1:8;
865 uint64_t umsk0:8;
866 } s;
867 struct cvmx_l2c_spar0_cn30xx {
868 uint64_t reserved_4_63:60;
869 uint64_t umsk0:4;
870 } cn30xx;
871 struct cvmx_l2c_spar0_cn31xx {
872 uint64_t reserved_12_63:52;
873 uint64_t umsk1:4;
874 uint64_t reserved_4_7:4;
875 uint64_t umsk0:4;
876 } cn31xx;
877 struct cvmx_l2c_spar0_s cn38xx;
878 struct cvmx_l2c_spar0_s cn38xxp2;
879 struct cvmx_l2c_spar0_cn50xx {
880 uint64_t reserved_16_63:48;
881 uint64_t umsk1:8;
882 uint64_t umsk0:8;
883 } cn50xx;
884 struct cvmx_l2c_spar0_s cn52xx;
885 struct cvmx_l2c_spar0_s cn52xxp1;
886 struct cvmx_l2c_spar0_s cn56xx;
887 struct cvmx_l2c_spar0_s cn56xxp1;
888 struct cvmx_l2c_spar0_s cn58xx;
889 struct cvmx_l2c_spar0_s cn58xxp1;
890};
891
892union cvmx_l2c_spar1 {
893 uint64_t u64;
894 struct cvmx_l2c_spar1_s {
895 uint64_t reserved_32_63:32;
896 uint64_t umsk7:8;
897 uint64_t umsk6:8;
898 uint64_t umsk5:8;
899 uint64_t umsk4:8;
900 } s;
901 struct cvmx_l2c_spar1_s cn38xx;
902 struct cvmx_l2c_spar1_s cn38xxp2;
903 struct cvmx_l2c_spar1_s cn56xx;
904 struct cvmx_l2c_spar1_s cn56xxp1;
905 struct cvmx_l2c_spar1_s cn58xx;
906 struct cvmx_l2c_spar1_s cn58xxp1;
907};
908
909union cvmx_l2c_spar2 {
910 uint64_t u64;
911 struct cvmx_l2c_spar2_s {
912 uint64_t reserved_32_63:32;
913 uint64_t umsk11:8;
914 uint64_t umsk10:8;
915 uint64_t umsk9:8;
916 uint64_t umsk8:8;
917 } s;
918 struct cvmx_l2c_spar2_s cn38xx;
919 struct cvmx_l2c_spar2_s cn38xxp2;
920 struct cvmx_l2c_spar2_s cn56xx;
921 struct cvmx_l2c_spar2_s cn56xxp1;
922 struct cvmx_l2c_spar2_s cn58xx;
923 struct cvmx_l2c_spar2_s cn58xxp1;
924};
925
926union cvmx_l2c_spar3 {
927 uint64_t u64;
928 struct cvmx_l2c_spar3_s {
929 uint64_t reserved_32_63:32;
930 uint64_t umsk15:8;
931 uint64_t umsk14:8;
932 uint64_t umsk13:8;
933 uint64_t umsk12:8;
934 } s;
935 struct cvmx_l2c_spar3_s cn38xx;
936 struct cvmx_l2c_spar3_s cn38xxp2;
937 struct cvmx_l2c_spar3_s cn58xx;
938 struct cvmx_l2c_spar3_s cn58xxp1;
939};
940
941union cvmx_l2c_spar4 {
942 uint64_t u64;
943 struct cvmx_l2c_spar4_s {
944 uint64_t reserved_8_63:56;
945 uint64_t umskiob:8;
946 } s;
947 struct cvmx_l2c_spar4_cn30xx {
948 uint64_t reserved_4_63:60;
949 uint64_t umskiob:4;
950 } cn30xx;
951 struct cvmx_l2c_spar4_cn30xx cn31xx;
952 struct cvmx_l2c_spar4_s cn38xx;
953 struct cvmx_l2c_spar4_s cn38xxp2;
954 struct cvmx_l2c_spar4_s cn50xx;
955 struct cvmx_l2c_spar4_s cn52xx;
956 struct cvmx_l2c_spar4_s cn52xxp1;
957 struct cvmx_l2c_spar4_s cn56xx;
958 struct cvmx_l2c_spar4_s cn56xxp1;
959 struct cvmx_l2c_spar4_s cn58xx;
960 struct cvmx_l2c_spar4_s cn58xxp1;
961};
962
963#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2c.h b/arch/mips/include/asm/octeon/cvmx-l2c.h
new file mode 100644
index 000000000000..2a8c0902ea50
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2c.h
@@ -0,0 +1,325 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * Interface to the Level 2 Cache (L2C) control, measurement, and debugging
31 * facilities.
32 */
33
34#ifndef __CVMX_L2C_H__
35#define __CVMX_L2C_H__
36
37/* Deprecated macro, use function */
38#define CVMX_L2_ASSOC cvmx_l2c_get_num_assoc()
39
40/* Deprecated macro, use function */
41#define CVMX_L2_SET_BITS cvmx_l2c_get_set_bits()
42
43/* Deprecated macro, use function */
44#define CVMX_L2_SETS cvmx_l2c_get_num_sets()
45
46#define CVMX_L2C_IDX_ADDR_SHIFT 7 /* based on 128 byte cache line size */
47#define CVMX_L2C_IDX_MASK (cvmx_l2c_get_num_sets() - 1)
48
49/* Defines for index aliasing computations */
50#define CVMX_L2C_TAG_ADDR_ALIAS_SHIFT \
51 (CVMX_L2C_IDX_ADDR_SHIFT + cvmx_l2c_get_set_bits())
52
53#define CVMX_L2C_ALIAS_MASK \
54 (CVMX_L2C_IDX_MASK << CVMX_L2C_TAG_ADDR_ALIAS_SHIFT)
55
56union cvmx_l2c_tag {
57 uint64_t u64;
58 struct {
59 uint64_t reserved:28;
60 uint64_t V:1; /* Line valid */
61 uint64_t D:1; /* Line dirty */
62 uint64_t L:1; /* Line locked */
63 uint64_t U:1; /* Use, LRU eviction */
64 uint64_t addr:32; /* Phys mem (not all bits valid) */
65 } s;
66};
67
68 /* L2C Performance Counter events. */
69enum cvmx_l2c_event {
70 CVMX_L2C_EVENT_CYCLES = 0,
71 CVMX_L2C_EVENT_INSTRUCTION_MISS = 1,
72 CVMX_L2C_EVENT_INSTRUCTION_HIT = 2,
73 CVMX_L2C_EVENT_DATA_MISS = 3,
74 CVMX_L2C_EVENT_DATA_HIT = 4,
75 CVMX_L2C_EVENT_MISS = 5,
76 CVMX_L2C_EVENT_HIT = 6,
77 CVMX_L2C_EVENT_VICTIM_HIT = 7,
78 CVMX_L2C_EVENT_INDEX_CONFLICT = 8,
79 CVMX_L2C_EVENT_TAG_PROBE = 9,
80 CVMX_L2C_EVENT_TAG_UPDATE = 10,
81 CVMX_L2C_EVENT_TAG_COMPLETE = 11,
82 CVMX_L2C_EVENT_TAG_DIRTY = 12,
83 CVMX_L2C_EVENT_DATA_STORE_NOP = 13,
84 CVMX_L2C_EVENT_DATA_STORE_READ = 14,
85 CVMX_L2C_EVENT_DATA_STORE_WRITE = 15,
86 CVMX_L2C_EVENT_FILL_DATA_VALID = 16,
87 CVMX_L2C_EVENT_WRITE_REQUEST = 17,
88 CVMX_L2C_EVENT_READ_REQUEST = 18,
89 CVMX_L2C_EVENT_WRITE_DATA_VALID = 19,
90 CVMX_L2C_EVENT_XMC_NOP = 20,
91 CVMX_L2C_EVENT_XMC_LDT = 21,
92 CVMX_L2C_EVENT_XMC_LDI = 22,
93 CVMX_L2C_EVENT_XMC_LDD = 23,
94 CVMX_L2C_EVENT_XMC_STF = 24,
95 CVMX_L2C_EVENT_XMC_STT = 25,
96 CVMX_L2C_EVENT_XMC_STP = 26,
97 CVMX_L2C_EVENT_XMC_STC = 27,
98 CVMX_L2C_EVENT_XMC_DWB = 28,
99 CVMX_L2C_EVENT_XMC_PL2 = 29,
100 CVMX_L2C_EVENT_XMC_PSL1 = 30,
101 CVMX_L2C_EVENT_XMC_IOBLD = 31,
102 CVMX_L2C_EVENT_XMC_IOBST = 32,
103 CVMX_L2C_EVENT_XMC_IOBDMA = 33,
104 CVMX_L2C_EVENT_XMC_IOBRSP = 34,
105 CVMX_L2C_EVENT_XMC_BUS_VALID = 35,
106 CVMX_L2C_EVENT_XMC_MEM_DATA = 36,
107 CVMX_L2C_EVENT_XMC_REFL_DATA = 37,
108 CVMX_L2C_EVENT_XMC_IOBRSP_DATA = 38,
109 CVMX_L2C_EVENT_RSC_NOP = 39,
110 CVMX_L2C_EVENT_RSC_STDN = 40,
111 CVMX_L2C_EVENT_RSC_FILL = 41,
112 CVMX_L2C_EVENT_RSC_REFL = 42,
113 CVMX_L2C_EVENT_RSC_STIN = 43,
114 CVMX_L2C_EVENT_RSC_SCIN = 44,
115 CVMX_L2C_EVENT_RSC_SCFL = 45,
116 CVMX_L2C_EVENT_RSC_SCDN = 46,
117 CVMX_L2C_EVENT_RSC_DATA_VALID = 47,
118 CVMX_L2C_EVENT_RSC_VALID_FILL = 48,
119 CVMX_L2C_EVENT_RSC_VALID_STRSP = 49,
120 CVMX_L2C_EVENT_RSC_VALID_REFL = 50,
121 CVMX_L2C_EVENT_LRF_REQ = 51,
122 CVMX_L2C_EVENT_DT_RD_ALLOC = 52,
123 CVMX_L2C_EVENT_DT_WR_INVAL = 53
124};
125
126/**
127 * Configure one of the four L2 Cache performance counters to capture event
128 * occurences.
129 *
130 * @counter: The counter to configure. Range 0..3.
131 * @event: The type of L2 Cache event occurrence to count.
132 * @clear_on_read: When asserted, any read of the performance counter
133 * clears the counter.
134 *
135 * The routine does not clear the counter.
136 */
137void cvmx_l2c_config_perf(uint32_t counter,
138 enum cvmx_l2c_event event, uint32_t clear_on_read);
139/**
140 * Read the given L2 Cache performance counter. The counter must be configured
141 * before reading, but this routine does not enforce this requirement.
142 *
143 * @counter: The counter to configure. Range 0..3.
144 *
145 * Returns The current counter value.
146 */
147uint64_t cvmx_l2c_read_perf(uint32_t counter);
148
149/**
150 * Return the L2 Cache way partitioning for a given core.
151 *
152 * @core: The core processor of interest.
153 *
154 * Returns The mask specifying the partitioning. 0 bits in mask indicates
155 * the cache 'ways' that a core can evict from.
156 * -1 on error
157 */
158int cvmx_l2c_get_core_way_partition(uint32_t core);
159
160/**
161 * Partitions the L2 cache for a core
162 *
163 * @core: The core that the partitioning applies to.
164 *
165 * @mask: The partitioning of the ways expressed as a binary mask. A 0
166 * bit allows the core to evict cache lines from a way, while a
167 * 1 bit blocks the core from evicting any lines from that
168 * way. There must be at least one allowed way (0 bit) in the
169 * mask.
170 *
171 * If any ways are blocked for all cores and the HW blocks, then those
172 * ways will never have any cache lines evicted from them. All cores
173 * and the hardware blocks are free to read from all ways regardless
174 * of the partitioning.
175 */
176int cvmx_l2c_set_core_way_partition(uint32_t core, uint32_t mask);
177
178/**
179 * Return the L2 Cache way partitioning for the hw blocks.
180 *
181 * Returns The mask specifying the reserved way. 0 bits in mask indicates
182 * the cache 'ways' that a core can evict from.
183 * -1 on error
184 */
185int cvmx_l2c_get_hw_way_partition(void);
186
187/**
188 * Partitions the L2 cache for the hardware blocks.
189 *
190 * @mask: The partitioning of the ways expressed as a binary mask. A 0
191 * bit allows the core to evict cache lines from a way, while a
192 * 1 bit blocks the core from evicting any lines from that
193 * way. There must be at least one allowed way (0 bit) in the
194 * mask.
195 *
196 * If any ways are blocked for all cores and the HW blocks, then those
197 * ways will never have any cache lines evicted from them. All cores
198 * and the hardware blocks are free to read from all ways regardless
199 * of the partitioning.
200 */
201int cvmx_l2c_set_hw_way_partition(uint32_t mask);
202
203/**
204 * Locks a line in the L2 cache at the specified physical address
205 *
206 * @addr: physical address of line to lock
207 *
208 * Returns 0 on success,
209 * 1 if line not locked.
210 */
211int cvmx_l2c_lock_line(uint64_t addr);
212
213/**
214 * Locks a specified memory region in the L2 cache.
215 *
216 * Note that if not all lines can be locked, that means that all
217 * but one of the ways (associations) available to the locking
218 * core are locked. Having only 1 association available for
219 * normal caching may have a significant adverse affect on performance.
220 * Care should be taken to ensure that enough of the L2 cache is left
221 * unlocked to allow for normal caching of DRAM.
222 *
223 * @start: Physical address of the start of the region to lock
224 * @len: Length (in bytes) of region to lock
225 *
226 * Returns Number of requested lines that where not locked.
227 * 0 on success (all locked)
228 */
229int cvmx_l2c_lock_mem_region(uint64_t start, uint64_t len);
230
231/**
232 * Unlock and flush a cache line from the L2 cache.
233 * IMPORTANT: Must only be run by one core at a time due to use
234 * of L2C debug features.
235 * Note that this function will flush a matching but unlocked cache line.
236 * (If address is not in L2, no lines are flushed.)
237 *
238 * @address: Physical address to unlock
239 *
240 * Returns 0: line not unlocked
241 * 1: line unlocked
242 */
243int cvmx_l2c_unlock_line(uint64_t address);
244
245/**
246 * Unlocks a region of memory that is locked in the L2 cache
247 *
248 * @start: start physical address
249 * @len: length (in bytes) to unlock
250 *
251 * Returns Number of locked lines that the call unlocked
252 */
253int cvmx_l2c_unlock_mem_region(uint64_t start, uint64_t len);
254
255/**
256 * Read the L2 controller tag for a given location in L2
257 *
258 * @association:
259 * Which association to read line from
260 * @index: Which way to read from.
261 *
262 * Returns l2c tag structure for line requested.
263 */
264union cvmx_l2c_tag cvmx_l2c_get_tag(uint32_t association, uint32_t index);
265
266/* Wrapper around deprecated old function name */
267static inline union cvmx_l2c_tag cvmx_get_l2c_tag(uint32_t association,
268 uint32_t index)
269{
270 return cvmx_l2c_get_tag(association, index);
271}
272
273/**
274 * Returns the cache index for a given physical address
275 *
276 * @addr: physical address
277 *
278 * Returns L2 cache index
279 */
280uint32_t cvmx_l2c_address_to_index(uint64_t addr);
281
282/**
283 * Flushes (and unlocks) the entire L2 cache.
284 * IMPORTANT: Must only be run by one core at a time due to use
285 * of L2C debug features.
286 */
287void cvmx_l2c_flush(void);
288
289/**
290 *
291 * Returns Returns the size of the L2 cache in bytes,
292 * -1 on error (unrecognized model)
293 */
294int cvmx_l2c_get_cache_size_bytes(void);
295
296/**
297 * Return the number of sets in the L2 Cache
298 *
299 * Returns
300 */
301int cvmx_l2c_get_num_sets(void);
302
303/**
304 * Return log base 2 of the number of sets in the L2 cache
305 * Returns
306 */
307int cvmx_l2c_get_set_bits(void);
308/**
309 * Return the number of associations in the L2 Cache
310 *
311 * Returns
312 */
313int cvmx_l2c_get_num_assoc(void);
314
315/**
316 * Flush a line from the L2 cache
317 * This should only be called from one core at a time, as this routine
318 * sets the core to the 'debug' core in order to flush the line.
319 *
320 * @assoc: Association (or way) to flush
321 * @index: Index to flush
322 */
323void cvmx_l2c_flush_line(uint32_t assoc, uint32_t index);
324
325#endif /* __CVMX_L2C_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
new file mode 100644
index 000000000000..d7102d455e1b
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
@@ -0,0 +1,369 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_L2D_DEFS_H__
29#define __CVMX_L2D_DEFS_H__
30
31#define CVMX_L2D_BST0 \
32 CVMX_ADD_IO_SEG(0x0001180080000780ull)
33#define CVMX_L2D_BST1 \
34 CVMX_ADD_IO_SEG(0x0001180080000788ull)
35#define CVMX_L2D_BST2 \
36 CVMX_ADD_IO_SEG(0x0001180080000790ull)
37#define CVMX_L2D_BST3 \
38 CVMX_ADD_IO_SEG(0x0001180080000798ull)
39#define CVMX_L2D_ERR \
40 CVMX_ADD_IO_SEG(0x0001180080000010ull)
41#define CVMX_L2D_FADR \
42 CVMX_ADD_IO_SEG(0x0001180080000018ull)
43#define CVMX_L2D_FSYN0 \
44 CVMX_ADD_IO_SEG(0x0001180080000020ull)
45#define CVMX_L2D_FSYN1 \
46 CVMX_ADD_IO_SEG(0x0001180080000028ull)
47#define CVMX_L2D_FUS0 \
48 CVMX_ADD_IO_SEG(0x00011800800007A0ull)
49#define CVMX_L2D_FUS1 \
50 CVMX_ADD_IO_SEG(0x00011800800007A8ull)
51#define CVMX_L2D_FUS2 \
52 CVMX_ADD_IO_SEG(0x00011800800007B0ull)
53#define CVMX_L2D_FUS3 \
54 CVMX_ADD_IO_SEG(0x00011800800007B8ull)
55
56union cvmx_l2d_bst0 {
57 uint64_t u64;
58 struct cvmx_l2d_bst0_s {
59 uint64_t reserved_35_63:29;
60 uint64_t ftl:1;
61 uint64_t q0stat:34;
62 } s;
63 struct cvmx_l2d_bst0_s cn30xx;
64 struct cvmx_l2d_bst0_s cn31xx;
65 struct cvmx_l2d_bst0_s cn38xx;
66 struct cvmx_l2d_bst0_s cn38xxp2;
67 struct cvmx_l2d_bst0_s cn50xx;
68 struct cvmx_l2d_bst0_s cn52xx;
69 struct cvmx_l2d_bst0_s cn52xxp1;
70 struct cvmx_l2d_bst0_s cn56xx;
71 struct cvmx_l2d_bst0_s cn56xxp1;
72 struct cvmx_l2d_bst0_s cn58xx;
73 struct cvmx_l2d_bst0_s cn58xxp1;
74};
75
76union cvmx_l2d_bst1 {
77 uint64_t u64;
78 struct cvmx_l2d_bst1_s {
79 uint64_t reserved_34_63:30;
80 uint64_t q1stat:34;
81 } s;
82 struct cvmx_l2d_bst1_s cn30xx;
83 struct cvmx_l2d_bst1_s cn31xx;
84 struct cvmx_l2d_bst1_s cn38xx;
85 struct cvmx_l2d_bst1_s cn38xxp2;
86 struct cvmx_l2d_bst1_s cn50xx;
87 struct cvmx_l2d_bst1_s cn52xx;
88 struct cvmx_l2d_bst1_s cn52xxp1;
89 struct cvmx_l2d_bst1_s cn56xx;
90 struct cvmx_l2d_bst1_s cn56xxp1;
91 struct cvmx_l2d_bst1_s cn58xx;
92 struct cvmx_l2d_bst1_s cn58xxp1;
93};
94
95union cvmx_l2d_bst2 {
96 uint64_t u64;
97 struct cvmx_l2d_bst2_s {
98 uint64_t reserved_34_63:30;
99 uint64_t q2stat:34;
100 } s;
101 struct cvmx_l2d_bst2_s cn30xx;
102 struct cvmx_l2d_bst2_s cn31xx;
103 struct cvmx_l2d_bst2_s cn38xx;
104 struct cvmx_l2d_bst2_s cn38xxp2;
105 struct cvmx_l2d_bst2_s cn50xx;
106 struct cvmx_l2d_bst2_s cn52xx;
107 struct cvmx_l2d_bst2_s cn52xxp1;
108 struct cvmx_l2d_bst2_s cn56xx;
109 struct cvmx_l2d_bst2_s cn56xxp1;
110 struct cvmx_l2d_bst2_s cn58xx;
111 struct cvmx_l2d_bst2_s cn58xxp1;
112};
113
114union cvmx_l2d_bst3 {
115 uint64_t u64;
116 struct cvmx_l2d_bst3_s {
117 uint64_t reserved_34_63:30;
118 uint64_t q3stat:34;
119 } s;
120 struct cvmx_l2d_bst3_s cn30xx;
121 struct cvmx_l2d_bst3_s cn31xx;
122 struct cvmx_l2d_bst3_s cn38xx;
123 struct cvmx_l2d_bst3_s cn38xxp2;
124 struct cvmx_l2d_bst3_s cn50xx;
125 struct cvmx_l2d_bst3_s cn52xx;
126 struct cvmx_l2d_bst3_s cn52xxp1;
127 struct cvmx_l2d_bst3_s cn56xx;
128 struct cvmx_l2d_bst3_s cn56xxp1;
129 struct cvmx_l2d_bst3_s cn58xx;
130 struct cvmx_l2d_bst3_s cn58xxp1;
131};
132
133union cvmx_l2d_err {
134 uint64_t u64;
135 struct cvmx_l2d_err_s {
136 uint64_t reserved_6_63:58;
137 uint64_t bmhclsel:1;
138 uint64_t ded_err:1;
139 uint64_t sec_err:1;
140 uint64_t ded_intena:1;
141 uint64_t sec_intena:1;
142 uint64_t ecc_ena:1;
143 } s;
144 struct cvmx_l2d_err_s cn30xx;
145 struct cvmx_l2d_err_s cn31xx;
146 struct cvmx_l2d_err_s cn38xx;
147 struct cvmx_l2d_err_s cn38xxp2;
148 struct cvmx_l2d_err_s cn50xx;
149 struct cvmx_l2d_err_s cn52xx;
150 struct cvmx_l2d_err_s cn52xxp1;
151 struct cvmx_l2d_err_s cn56xx;
152 struct cvmx_l2d_err_s cn56xxp1;
153 struct cvmx_l2d_err_s cn58xx;
154 struct cvmx_l2d_err_s cn58xxp1;
155};
156
157union cvmx_l2d_fadr {
158 uint64_t u64;
159 struct cvmx_l2d_fadr_s {
160 uint64_t reserved_19_63:45;
161 uint64_t fadru:1;
162 uint64_t fowmsk:4;
163 uint64_t fset:3;
164 uint64_t fadr:11;
165 } s;
166 struct cvmx_l2d_fadr_cn30xx {
167 uint64_t reserved_18_63:46;
168 uint64_t fowmsk:4;
169 uint64_t reserved_13_13:1;
170 uint64_t fset:2;
171 uint64_t reserved_9_10:2;
172 uint64_t fadr:9;
173 } cn30xx;
174 struct cvmx_l2d_fadr_cn31xx {
175 uint64_t reserved_18_63:46;
176 uint64_t fowmsk:4;
177 uint64_t reserved_13_13:1;
178 uint64_t fset:2;
179 uint64_t reserved_10_10:1;
180 uint64_t fadr:10;
181 } cn31xx;
182 struct cvmx_l2d_fadr_cn38xx {
183 uint64_t reserved_18_63:46;
184 uint64_t fowmsk:4;
185 uint64_t fset:3;
186 uint64_t fadr:11;
187 } cn38xx;
188 struct cvmx_l2d_fadr_cn38xx cn38xxp2;
189 struct cvmx_l2d_fadr_cn50xx {
190 uint64_t reserved_18_63:46;
191 uint64_t fowmsk:4;
192 uint64_t fset:3;
193 uint64_t reserved_8_10:3;
194 uint64_t fadr:8;
195 } cn50xx;
196 struct cvmx_l2d_fadr_cn52xx {
197 uint64_t reserved_18_63:46;
198 uint64_t fowmsk:4;
199 uint64_t fset:3;
200 uint64_t reserved_10_10:1;
201 uint64_t fadr:10;
202 } cn52xx;
203 struct cvmx_l2d_fadr_cn52xx cn52xxp1;
204 struct cvmx_l2d_fadr_s cn56xx;
205 struct cvmx_l2d_fadr_s cn56xxp1;
206 struct cvmx_l2d_fadr_s cn58xx;
207 struct cvmx_l2d_fadr_s cn58xxp1;
208};
209
210union cvmx_l2d_fsyn0 {
211 uint64_t u64;
212 struct cvmx_l2d_fsyn0_s {
213 uint64_t reserved_20_63:44;
214 uint64_t fsyn_ow1:10;
215 uint64_t fsyn_ow0:10;
216 } s;
217 struct cvmx_l2d_fsyn0_s cn30xx;
218 struct cvmx_l2d_fsyn0_s cn31xx;
219 struct cvmx_l2d_fsyn0_s cn38xx;
220 struct cvmx_l2d_fsyn0_s cn38xxp2;
221 struct cvmx_l2d_fsyn0_s cn50xx;
222 struct cvmx_l2d_fsyn0_s cn52xx;
223 struct cvmx_l2d_fsyn0_s cn52xxp1;
224 struct cvmx_l2d_fsyn0_s cn56xx;
225 struct cvmx_l2d_fsyn0_s cn56xxp1;
226 struct cvmx_l2d_fsyn0_s cn58xx;
227 struct cvmx_l2d_fsyn0_s cn58xxp1;
228};
229
230union cvmx_l2d_fsyn1 {
231 uint64_t u64;
232 struct cvmx_l2d_fsyn1_s {
233 uint64_t reserved_20_63:44;
234 uint64_t fsyn_ow3:10;
235 uint64_t fsyn_ow2:10;
236 } s;
237 struct cvmx_l2d_fsyn1_s cn30xx;
238 struct cvmx_l2d_fsyn1_s cn31xx;
239 struct cvmx_l2d_fsyn1_s cn38xx;
240 struct cvmx_l2d_fsyn1_s cn38xxp2;
241 struct cvmx_l2d_fsyn1_s cn50xx;
242 struct cvmx_l2d_fsyn1_s cn52xx;
243 struct cvmx_l2d_fsyn1_s cn52xxp1;
244 struct cvmx_l2d_fsyn1_s cn56xx;
245 struct cvmx_l2d_fsyn1_s cn56xxp1;
246 struct cvmx_l2d_fsyn1_s cn58xx;
247 struct cvmx_l2d_fsyn1_s cn58xxp1;
248};
249
250union cvmx_l2d_fus0 {
251 uint64_t u64;
252 struct cvmx_l2d_fus0_s {
253 uint64_t reserved_34_63:30;
254 uint64_t q0fus:34;
255 } s;
256 struct cvmx_l2d_fus0_s cn30xx;
257 struct cvmx_l2d_fus0_s cn31xx;
258 struct cvmx_l2d_fus0_s cn38xx;
259 struct cvmx_l2d_fus0_s cn38xxp2;
260 struct cvmx_l2d_fus0_s cn50xx;
261 struct cvmx_l2d_fus0_s cn52xx;
262 struct cvmx_l2d_fus0_s cn52xxp1;
263 struct cvmx_l2d_fus0_s cn56xx;
264 struct cvmx_l2d_fus0_s cn56xxp1;
265 struct cvmx_l2d_fus0_s cn58xx;
266 struct cvmx_l2d_fus0_s cn58xxp1;
267};
268
269union cvmx_l2d_fus1 {
270 uint64_t u64;
271 struct cvmx_l2d_fus1_s {
272 uint64_t reserved_34_63:30;
273 uint64_t q1fus:34;
274 } s;
275 struct cvmx_l2d_fus1_s cn30xx;
276 struct cvmx_l2d_fus1_s cn31xx;
277 struct cvmx_l2d_fus1_s cn38xx;
278 struct cvmx_l2d_fus1_s cn38xxp2;
279 struct cvmx_l2d_fus1_s cn50xx;
280 struct cvmx_l2d_fus1_s cn52xx;
281 struct cvmx_l2d_fus1_s cn52xxp1;
282 struct cvmx_l2d_fus1_s cn56xx;
283 struct cvmx_l2d_fus1_s cn56xxp1;
284 struct cvmx_l2d_fus1_s cn58xx;
285 struct cvmx_l2d_fus1_s cn58xxp1;
286};
287
288union cvmx_l2d_fus2 {
289 uint64_t u64;
290 struct cvmx_l2d_fus2_s {
291 uint64_t reserved_34_63:30;
292 uint64_t q2fus:34;
293 } s;
294 struct cvmx_l2d_fus2_s cn30xx;
295 struct cvmx_l2d_fus2_s cn31xx;
296 struct cvmx_l2d_fus2_s cn38xx;
297 struct cvmx_l2d_fus2_s cn38xxp2;
298 struct cvmx_l2d_fus2_s cn50xx;
299 struct cvmx_l2d_fus2_s cn52xx;
300 struct cvmx_l2d_fus2_s cn52xxp1;
301 struct cvmx_l2d_fus2_s cn56xx;
302 struct cvmx_l2d_fus2_s cn56xxp1;
303 struct cvmx_l2d_fus2_s cn58xx;
304 struct cvmx_l2d_fus2_s cn58xxp1;
305};
306
307union cvmx_l2d_fus3 {
308 uint64_t u64;
309 struct cvmx_l2d_fus3_s {
310 uint64_t reserved_40_63:24;
311 uint64_t ema_ctl:3;
312 uint64_t reserved_34_36:3;
313 uint64_t q3fus:34;
314 } s;
315 struct cvmx_l2d_fus3_cn30xx {
316 uint64_t reserved_35_63:29;
317 uint64_t crip_64k:1;
318 uint64_t q3fus:34;
319 } cn30xx;
320 struct cvmx_l2d_fus3_cn31xx {
321 uint64_t reserved_35_63:29;
322 uint64_t crip_128k:1;
323 uint64_t q3fus:34;
324 } cn31xx;
325 struct cvmx_l2d_fus3_cn38xx {
326 uint64_t reserved_36_63:28;
327 uint64_t crip_256k:1;
328 uint64_t crip_512k:1;
329 uint64_t q3fus:34;
330 } cn38xx;
331 struct cvmx_l2d_fus3_cn38xx cn38xxp2;
332 struct cvmx_l2d_fus3_cn50xx {
333 uint64_t reserved_40_63:24;
334 uint64_t ema_ctl:3;
335 uint64_t reserved_36_36:1;
336 uint64_t crip_32k:1;
337 uint64_t crip_64k:1;
338 uint64_t q3fus:34;
339 } cn50xx;
340 struct cvmx_l2d_fus3_cn52xx {
341 uint64_t reserved_40_63:24;
342 uint64_t ema_ctl:3;
343 uint64_t reserved_36_36:1;
344 uint64_t crip_128k:1;
345 uint64_t crip_256k:1;
346 uint64_t q3fus:34;
347 } cn52xx;
348 struct cvmx_l2d_fus3_cn52xx cn52xxp1;
349 struct cvmx_l2d_fus3_cn56xx {
350 uint64_t reserved_40_63:24;
351 uint64_t ema_ctl:3;
352 uint64_t reserved_36_36:1;
353 uint64_t crip_512k:1;
354 uint64_t crip_1024k:1;
355 uint64_t q3fus:34;
356 } cn56xx;
357 struct cvmx_l2d_fus3_cn56xx cn56xxp1;
358 struct cvmx_l2d_fus3_cn58xx {
359 uint64_t reserved_39_63:25;
360 uint64_t ema_ctl:2;
361 uint64_t reserved_36_36:1;
362 uint64_t crip_512k:1;
363 uint64_t crip_1024k:1;
364 uint64_t q3fus:34;
365 } cn58xx;
366 struct cvmx_l2d_fus3_cn58xx cn58xxp1;
367};
368
369#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
new file mode 100644
index 000000000000..2639a3f5ffc2
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h
@@ -0,0 +1,141 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_L2T_DEFS_H__
29#define __CVMX_L2T_DEFS_H__
30
31#define CVMX_L2T_ERR \
32 CVMX_ADD_IO_SEG(0x0001180080000008ull)
33
34union cvmx_l2t_err {
35 uint64_t u64;
36 struct cvmx_l2t_err_s {
37 uint64_t reserved_29_63:35;
38 uint64_t fadru:1;
39 uint64_t lck_intena2:1;
40 uint64_t lckerr2:1;
41 uint64_t lck_intena:1;
42 uint64_t lckerr:1;
43 uint64_t fset:3;
44 uint64_t fadr:10;
45 uint64_t fsyn:6;
46 uint64_t ded_err:1;
47 uint64_t sec_err:1;
48 uint64_t ded_intena:1;
49 uint64_t sec_intena:1;
50 uint64_t ecc_ena:1;
51 } s;
52 struct cvmx_l2t_err_cn30xx {
53 uint64_t reserved_28_63:36;
54 uint64_t lck_intena2:1;
55 uint64_t lckerr2:1;
56 uint64_t lck_intena:1;
57 uint64_t lckerr:1;
58 uint64_t reserved_23_23:1;
59 uint64_t fset:2;
60 uint64_t reserved_19_20:2;
61 uint64_t fadr:8;
62 uint64_t fsyn:6;
63 uint64_t ded_err:1;
64 uint64_t sec_err:1;
65 uint64_t ded_intena:1;
66 uint64_t sec_intena:1;
67 uint64_t ecc_ena:1;
68 } cn30xx;
69 struct cvmx_l2t_err_cn31xx {
70 uint64_t reserved_28_63:36;
71 uint64_t lck_intena2:1;
72 uint64_t lckerr2:1;
73 uint64_t lck_intena:1;
74 uint64_t lckerr:1;
75 uint64_t reserved_23_23:1;
76 uint64_t fset:2;
77 uint64_t reserved_20_20:1;
78 uint64_t fadr:9;
79 uint64_t fsyn:6;
80 uint64_t ded_err:1;
81 uint64_t sec_err:1;
82 uint64_t ded_intena:1;
83 uint64_t sec_intena:1;
84 uint64_t ecc_ena:1;
85 } cn31xx;
86 struct cvmx_l2t_err_cn38xx {
87 uint64_t reserved_28_63:36;
88 uint64_t lck_intena2:1;
89 uint64_t lckerr2:1;
90 uint64_t lck_intena:1;
91 uint64_t lckerr:1;
92 uint64_t fset:3;
93 uint64_t fadr:10;
94 uint64_t fsyn:6;
95 uint64_t ded_err:1;
96 uint64_t sec_err:1;
97 uint64_t ded_intena:1;
98 uint64_t sec_intena:1;
99 uint64_t ecc_ena:1;
100 } cn38xx;
101 struct cvmx_l2t_err_cn38xx cn38xxp2;
102 struct cvmx_l2t_err_cn50xx {
103 uint64_t reserved_28_63:36;
104 uint64_t lck_intena2:1;
105 uint64_t lckerr2:1;
106 uint64_t lck_intena:1;
107 uint64_t lckerr:1;
108 uint64_t fset:3;
109 uint64_t reserved_18_20:3;
110 uint64_t fadr:7;
111 uint64_t fsyn:6;
112 uint64_t ded_err:1;
113 uint64_t sec_err:1;
114 uint64_t ded_intena:1;
115 uint64_t sec_intena:1;
116 uint64_t ecc_ena:1;
117 } cn50xx;
118 struct cvmx_l2t_err_cn52xx {
119 uint64_t reserved_28_63:36;
120 uint64_t lck_intena2:1;
121 uint64_t lckerr2:1;
122 uint64_t lck_intena:1;
123 uint64_t lckerr:1;
124 uint64_t fset:3;
125 uint64_t reserved_20_20:1;
126 uint64_t fadr:9;
127 uint64_t fsyn:6;
128 uint64_t ded_err:1;
129 uint64_t sec_err:1;
130 uint64_t ded_intena:1;
131 uint64_t sec_intena:1;
132 uint64_t ecc_ena:1;
133 } cn52xx;
134 struct cvmx_l2t_err_cn52xx cn52xxp1;
135 struct cvmx_l2t_err_s cn56xx;
136 struct cvmx_l2t_err_s cn56xxp1;
137 struct cvmx_l2t_err_s cn58xx;
138 struct cvmx_l2t_err_s cn58xxp1;
139};
140
141#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-led-defs.h b/arch/mips/include/asm/octeon/cvmx-led-defs.h
new file mode 100644
index 000000000000..16f174a4dadf
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-led-defs.h
@@ -0,0 +1,240 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_LED_DEFS_H__
29#define __CVMX_LED_DEFS_H__
30
31#define CVMX_LED_BLINK \
32 CVMX_ADD_IO_SEG(0x0001180000001A48ull)
33#define CVMX_LED_CLK_PHASE \
34 CVMX_ADD_IO_SEG(0x0001180000001A08ull)
35#define CVMX_LED_CYLON \
36 CVMX_ADD_IO_SEG(0x0001180000001AF8ull)
37#define CVMX_LED_DBG \
38 CVMX_ADD_IO_SEG(0x0001180000001A18ull)
39#define CVMX_LED_EN \
40 CVMX_ADD_IO_SEG(0x0001180000001A00ull)
41#define CVMX_LED_POLARITY \
42 CVMX_ADD_IO_SEG(0x0001180000001A50ull)
43#define CVMX_LED_PRT \
44 CVMX_ADD_IO_SEG(0x0001180000001A10ull)
45#define CVMX_LED_PRT_FMT \
46 CVMX_ADD_IO_SEG(0x0001180000001A30ull)
47#define CVMX_LED_PRT_STATUSX(offset) \
48 CVMX_ADD_IO_SEG(0x0001180000001A80ull + (((offset) & 7) * 8))
49#define CVMX_LED_UDD_CNTX(offset) \
50 CVMX_ADD_IO_SEG(0x0001180000001A20ull + (((offset) & 1) * 8))
51#define CVMX_LED_UDD_DATX(offset) \
52 CVMX_ADD_IO_SEG(0x0001180000001A38ull + (((offset) & 1) * 8))
53#define CVMX_LED_UDD_DAT_CLRX(offset) \
54 CVMX_ADD_IO_SEG(0x0001180000001AC8ull + (((offset) & 1) * 16))
55#define CVMX_LED_UDD_DAT_SETX(offset) \
56 CVMX_ADD_IO_SEG(0x0001180000001AC0ull + (((offset) & 1) * 16))
57
58union cvmx_led_blink {
59 uint64_t u64;
60 struct cvmx_led_blink_s {
61 uint64_t reserved_8_63:56;
62 uint64_t rate:8;
63 } s;
64 struct cvmx_led_blink_s cn38xx;
65 struct cvmx_led_blink_s cn38xxp2;
66 struct cvmx_led_blink_s cn56xx;
67 struct cvmx_led_blink_s cn56xxp1;
68 struct cvmx_led_blink_s cn58xx;
69 struct cvmx_led_blink_s cn58xxp1;
70};
71
72union cvmx_led_clk_phase {
73 uint64_t u64;
74 struct cvmx_led_clk_phase_s {
75 uint64_t reserved_7_63:57;
76 uint64_t phase:7;
77 } s;
78 struct cvmx_led_clk_phase_s cn38xx;
79 struct cvmx_led_clk_phase_s cn38xxp2;
80 struct cvmx_led_clk_phase_s cn56xx;
81 struct cvmx_led_clk_phase_s cn56xxp1;
82 struct cvmx_led_clk_phase_s cn58xx;
83 struct cvmx_led_clk_phase_s cn58xxp1;
84};
85
86union cvmx_led_cylon {
87 uint64_t u64;
88 struct cvmx_led_cylon_s {
89 uint64_t reserved_16_63:48;
90 uint64_t rate:16;
91 } s;
92 struct cvmx_led_cylon_s cn38xx;
93 struct cvmx_led_cylon_s cn38xxp2;
94 struct cvmx_led_cylon_s cn56xx;
95 struct cvmx_led_cylon_s cn56xxp1;
96 struct cvmx_led_cylon_s cn58xx;
97 struct cvmx_led_cylon_s cn58xxp1;
98};
99
100union cvmx_led_dbg {
101 uint64_t u64;
102 struct cvmx_led_dbg_s {
103 uint64_t reserved_1_63:63;
104 uint64_t dbg_en:1;
105 } s;
106 struct cvmx_led_dbg_s cn38xx;
107 struct cvmx_led_dbg_s cn38xxp2;
108 struct cvmx_led_dbg_s cn56xx;
109 struct cvmx_led_dbg_s cn56xxp1;
110 struct cvmx_led_dbg_s cn58xx;
111 struct cvmx_led_dbg_s cn58xxp1;
112};
113
114union cvmx_led_en {
115 uint64_t u64;
116 struct cvmx_led_en_s {
117 uint64_t reserved_1_63:63;
118 uint64_t en:1;
119 } s;
120 struct cvmx_led_en_s cn38xx;
121 struct cvmx_led_en_s cn38xxp2;
122 struct cvmx_led_en_s cn56xx;
123 struct cvmx_led_en_s cn56xxp1;
124 struct cvmx_led_en_s cn58xx;
125 struct cvmx_led_en_s cn58xxp1;
126};
127
128union cvmx_led_polarity {
129 uint64_t u64;
130 struct cvmx_led_polarity_s {
131 uint64_t reserved_1_63:63;
132 uint64_t polarity:1;
133 } s;
134 struct cvmx_led_polarity_s cn38xx;
135 struct cvmx_led_polarity_s cn38xxp2;
136 struct cvmx_led_polarity_s cn56xx;
137 struct cvmx_led_polarity_s cn56xxp1;
138 struct cvmx_led_polarity_s cn58xx;
139 struct cvmx_led_polarity_s cn58xxp1;
140};
141
142union cvmx_led_prt {
143 uint64_t u64;
144 struct cvmx_led_prt_s {
145 uint64_t reserved_8_63:56;
146 uint64_t prt_en:8;
147 } s;
148 struct cvmx_led_prt_s cn38xx;
149 struct cvmx_led_prt_s cn38xxp2;
150 struct cvmx_led_prt_s cn56xx;
151 struct cvmx_led_prt_s cn56xxp1;
152 struct cvmx_led_prt_s cn58xx;
153 struct cvmx_led_prt_s cn58xxp1;
154};
155
156union cvmx_led_prt_fmt {
157 uint64_t u64;
158 struct cvmx_led_prt_fmt_s {
159 uint64_t reserved_4_63:60;
160 uint64_t format:4;
161 } s;
162 struct cvmx_led_prt_fmt_s cn38xx;
163 struct cvmx_led_prt_fmt_s cn38xxp2;
164 struct cvmx_led_prt_fmt_s cn56xx;
165 struct cvmx_led_prt_fmt_s cn56xxp1;
166 struct cvmx_led_prt_fmt_s cn58xx;
167 struct cvmx_led_prt_fmt_s cn58xxp1;
168};
169
170union cvmx_led_prt_statusx {
171 uint64_t u64;
172 struct cvmx_led_prt_statusx_s {
173 uint64_t reserved_6_63:58;
174 uint64_t status:6;
175 } s;
176 struct cvmx_led_prt_statusx_s cn38xx;
177 struct cvmx_led_prt_statusx_s cn38xxp2;
178 struct cvmx_led_prt_statusx_s cn56xx;
179 struct cvmx_led_prt_statusx_s cn56xxp1;
180 struct cvmx_led_prt_statusx_s cn58xx;
181 struct cvmx_led_prt_statusx_s cn58xxp1;
182};
183
184union cvmx_led_udd_cntx {
185 uint64_t u64;
186 struct cvmx_led_udd_cntx_s {
187 uint64_t reserved_6_63:58;
188 uint64_t cnt:6;
189 } s;
190 struct cvmx_led_udd_cntx_s cn38xx;
191 struct cvmx_led_udd_cntx_s cn38xxp2;
192 struct cvmx_led_udd_cntx_s cn56xx;
193 struct cvmx_led_udd_cntx_s cn56xxp1;
194 struct cvmx_led_udd_cntx_s cn58xx;
195 struct cvmx_led_udd_cntx_s cn58xxp1;
196};
197
198union cvmx_led_udd_datx {
199 uint64_t u64;
200 struct cvmx_led_udd_datx_s {
201 uint64_t reserved_32_63:32;
202 uint64_t dat:32;
203 } s;
204 struct cvmx_led_udd_datx_s cn38xx;
205 struct cvmx_led_udd_datx_s cn38xxp2;
206 struct cvmx_led_udd_datx_s cn56xx;
207 struct cvmx_led_udd_datx_s cn56xxp1;
208 struct cvmx_led_udd_datx_s cn58xx;
209 struct cvmx_led_udd_datx_s cn58xxp1;
210};
211
212union cvmx_led_udd_dat_clrx {
213 uint64_t u64;
214 struct cvmx_led_udd_dat_clrx_s {
215 uint64_t reserved_32_63:32;
216 uint64_t clr:32;
217 } s;
218 struct cvmx_led_udd_dat_clrx_s cn38xx;
219 struct cvmx_led_udd_dat_clrx_s cn38xxp2;
220 struct cvmx_led_udd_dat_clrx_s cn56xx;
221 struct cvmx_led_udd_dat_clrx_s cn56xxp1;
222 struct cvmx_led_udd_dat_clrx_s cn58xx;
223 struct cvmx_led_udd_dat_clrx_s cn58xxp1;
224};
225
226union cvmx_led_udd_dat_setx {
227 uint64_t u64;
228 struct cvmx_led_udd_dat_setx_s {
229 uint64_t reserved_32_63:32;
230 uint64_t set:32;
231 } s;
232 struct cvmx_led_udd_dat_setx_s cn38xx;
233 struct cvmx_led_udd_dat_setx_s cn38xxp2;
234 struct cvmx_led_udd_dat_setx_s cn56xx;
235 struct cvmx_led_udd_dat_setx_s cn56xxp1;
236 struct cvmx_led_udd_dat_setx_s cn58xx;
237 struct cvmx_led_udd_dat_setx_s cn58xxp1;
238};
239
240#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-mio-defs.h b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
new file mode 100644
index 000000000000..6555f0530988
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-mio-defs.h
@@ -0,0 +1,2004 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_MIO_DEFS_H__
29#define __CVMX_MIO_DEFS_H__
30
31#define CVMX_MIO_BOOT_BIST_STAT \
32 CVMX_ADD_IO_SEG(0x00011800000000F8ull)
33#define CVMX_MIO_BOOT_COMP \
34 CVMX_ADD_IO_SEG(0x00011800000000B8ull)
35#define CVMX_MIO_BOOT_DMA_CFGX(offset) \
36 CVMX_ADD_IO_SEG(0x0001180000000100ull + (((offset) & 3) * 8))
37#define CVMX_MIO_BOOT_DMA_INTX(offset) \
38 CVMX_ADD_IO_SEG(0x0001180000000138ull + (((offset) & 3) * 8))
39#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) \
40 CVMX_ADD_IO_SEG(0x0001180000000150ull + (((offset) & 3) * 8))
41#define CVMX_MIO_BOOT_DMA_TIMX(offset) \
42 CVMX_ADD_IO_SEG(0x0001180000000120ull + (((offset) & 3) * 8))
43#define CVMX_MIO_BOOT_ERR \
44 CVMX_ADD_IO_SEG(0x00011800000000A0ull)
45#define CVMX_MIO_BOOT_INT \
46 CVMX_ADD_IO_SEG(0x00011800000000A8ull)
47#define CVMX_MIO_BOOT_LOC_ADR \
48 CVMX_ADD_IO_SEG(0x0001180000000090ull)
49#define CVMX_MIO_BOOT_LOC_CFGX(offset) \
50 CVMX_ADD_IO_SEG(0x0001180000000080ull + (((offset) & 1) * 8))
51#define CVMX_MIO_BOOT_LOC_DAT \
52 CVMX_ADD_IO_SEG(0x0001180000000098ull)
53#define CVMX_MIO_BOOT_PIN_DEFS \
54 CVMX_ADD_IO_SEG(0x00011800000000C0ull)
55#define CVMX_MIO_BOOT_REG_CFGX(offset) \
56 CVMX_ADD_IO_SEG(0x0001180000000000ull + (((offset) & 7) * 8))
57#define CVMX_MIO_BOOT_REG_TIMX(offset) \
58 CVMX_ADD_IO_SEG(0x0001180000000040ull + (((offset) & 7) * 8))
59#define CVMX_MIO_BOOT_THR \
60 CVMX_ADD_IO_SEG(0x00011800000000B0ull)
61#define CVMX_MIO_FUS_BNK_DATX(offset) \
62 CVMX_ADD_IO_SEG(0x0001180000001520ull + (((offset) & 3) * 8))
63#define CVMX_MIO_FUS_DAT0 \
64 CVMX_ADD_IO_SEG(0x0001180000001400ull)
65#define CVMX_MIO_FUS_DAT1 \
66 CVMX_ADD_IO_SEG(0x0001180000001408ull)
67#define CVMX_MIO_FUS_DAT2 \
68 CVMX_ADD_IO_SEG(0x0001180000001410ull)
69#define CVMX_MIO_FUS_DAT3 \
70 CVMX_ADD_IO_SEG(0x0001180000001418ull)
71#define CVMX_MIO_FUS_EMA \
72 CVMX_ADD_IO_SEG(0x0001180000001550ull)
73#define CVMX_MIO_FUS_PDF \
74 CVMX_ADD_IO_SEG(0x0001180000001420ull)
75#define CVMX_MIO_FUS_PLL \
76 CVMX_ADD_IO_SEG(0x0001180000001580ull)
77#define CVMX_MIO_FUS_PROG \
78 CVMX_ADD_IO_SEG(0x0001180000001510ull)
79#define CVMX_MIO_FUS_PROG_TIMES \
80 CVMX_ADD_IO_SEG(0x0001180000001518ull)
81#define CVMX_MIO_FUS_RCMD \
82 CVMX_ADD_IO_SEG(0x0001180000001500ull)
83#define CVMX_MIO_FUS_SPR_REPAIR_RES \
84 CVMX_ADD_IO_SEG(0x0001180000001548ull)
85#define CVMX_MIO_FUS_SPR_REPAIR_SUM \
86 CVMX_ADD_IO_SEG(0x0001180000001540ull)
87#define CVMX_MIO_FUS_UNLOCK \
88 CVMX_ADD_IO_SEG(0x0001180000001578ull)
89#define CVMX_MIO_FUS_WADR \
90 CVMX_ADD_IO_SEG(0x0001180000001508ull)
91#define CVMX_MIO_NDF_DMA_CFG \
92 CVMX_ADD_IO_SEG(0x0001180000000168ull)
93#define CVMX_MIO_NDF_DMA_INT \
94 CVMX_ADD_IO_SEG(0x0001180000000170ull)
95#define CVMX_MIO_NDF_DMA_INT_EN \
96 CVMX_ADD_IO_SEG(0x0001180000000178ull)
97#define CVMX_MIO_PLL_CTL \
98 CVMX_ADD_IO_SEG(0x0001180000001448ull)
99#define CVMX_MIO_PLL_SETTING \
100 CVMX_ADD_IO_SEG(0x0001180000001440ull)
101#define CVMX_MIO_TWSX_INT(offset) \
102 CVMX_ADD_IO_SEG(0x0001180000001010ull + (((offset) & 1) * 512))
103#define CVMX_MIO_TWSX_SW_TWSI(offset) \
104 CVMX_ADD_IO_SEG(0x0001180000001000ull + (((offset) & 1) * 512))
105#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) \
106 CVMX_ADD_IO_SEG(0x0001180000001018ull + (((offset) & 1) * 512))
107#define CVMX_MIO_TWSX_TWSI_SW(offset) \
108 CVMX_ADD_IO_SEG(0x0001180000001008ull + (((offset) & 1) * 512))
109#define CVMX_MIO_UART2_DLH \
110 CVMX_ADD_IO_SEG(0x0001180000000488ull)
111#define CVMX_MIO_UART2_DLL \
112 CVMX_ADD_IO_SEG(0x0001180000000480ull)
113#define CVMX_MIO_UART2_FAR \
114 CVMX_ADD_IO_SEG(0x0001180000000520ull)
115#define CVMX_MIO_UART2_FCR \
116 CVMX_ADD_IO_SEG(0x0001180000000450ull)
117#define CVMX_MIO_UART2_HTX \
118 CVMX_ADD_IO_SEG(0x0001180000000708ull)
119#define CVMX_MIO_UART2_IER \
120 CVMX_ADD_IO_SEG(0x0001180000000408ull)
121#define CVMX_MIO_UART2_IIR \
122 CVMX_ADD_IO_SEG(0x0001180000000410ull)
123#define CVMX_MIO_UART2_LCR \
124 CVMX_ADD_IO_SEG(0x0001180000000418ull)
125#define CVMX_MIO_UART2_LSR \
126 CVMX_ADD_IO_SEG(0x0001180000000428ull)
127#define CVMX_MIO_UART2_MCR \
128 CVMX_ADD_IO_SEG(0x0001180000000420ull)
129#define CVMX_MIO_UART2_MSR \
130 CVMX_ADD_IO_SEG(0x0001180000000430ull)
131#define CVMX_MIO_UART2_RBR \
132 CVMX_ADD_IO_SEG(0x0001180000000400ull)
133#define CVMX_MIO_UART2_RFL \
134 CVMX_ADD_IO_SEG(0x0001180000000608ull)
135#define CVMX_MIO_UART2_RFW \
136 CVMX_ADD_IO_SEG(0x0001180000000530ull)
137#define CVMX_MIO_UART2_SBCR \
138 CVMX_ADD_IO_SEG(0x0001180000000620ull)
139#define CVMX_MIO_UART2_SCR \
140 CVMX_ADD_IO_SEG(0x0001180000000438ull)
141#define CVMX_MIO_UART2_SFE \
142 CVMX_ADD_IO_SEG(0x0001180000000630ull)
143#define CVMX_MIO_UART2_SRR \
144 CVMX_ADD_IO_SEG(0x0001180000000610ull)
145#define CVMX_MIO_UART2_SRT \
146 CVMX_ADD_IO_SEG(0x0001180000000638ull)
147#define CVMX_MIO_UART2_SRTS \
148 CVMX_ADD_IO_SEG(0x0001180000000618ull)
149#define CVMX_MIO_UART2_STT \
150 CVMX_ADD_IO_SEG(0x0001180000000700ull)
151#define CVMX_MIO_UART2_TFL \
152 CVMX_ADD_IO_SEG(0x0001180000000600ull)
153#define CVMX_MIO_UART2_TFR \
154 CVMX_ADD_IO_SEG(0x0001180000000528ull)
155#define CVMX_MIO_UART2_THR \
156 CVMX_ADD_IO_SEG(0x0001180000000440ull)
157#define CVMX_MIO_UART2_USR \
158 CVMX_ADD_IO_SEG(0x0001180000000538ull)
159#define CVMX_MIO_UARTX_DLH(offset) \
160 CVMX_ADD_IO_SEG(0x0001180000000888ull + (((offset) & 1) * 1024))
161#define CVMX_MIO_UARTX_DLL(offset) \
162 CVMX_ADD_IO_SEG(0x0001180000000880ull + (((offset) & 1) * 1024))
163#define CVMX_MIO_UARTX_FAR(offset) \
164 CVMX_ADD_IO_SEG(0x0001180000000920ull + (((offset) & 1) * 1024))
165#define CVMX_MIO_UARTX_FCR(offset) \
166 CVMX_ADD_IO_SEG(0x0001180000000850ull + (((offset) & 1) * 1024))
167#define CVMX_MIO_UARTX_HTX(offset) \
168 CVMX_ADD_IO_SEG(0x0001180000000B08ull + (((offset) & 1) * 1024))
169#define CVMX_MIO_UARTX_IER(offset) \
170 CVMX_ADD_IO_SEG(0x0001180000000808ull + (((offset) & 1) * 1024))
171#define CVMX_MIO_UARTX_IIR(offset) \
172 CVMX_ADD_IO_SEG(0x0001180000000810ull + (((offset) & 1) * 1024))
173#define CVMX_MIO_UARTX_LCR(offset) \
174 CVMX_ADD_IO_SEG(0x0001180000000818ull + (((offset) & 1) * 1024))
175#define CVMX_MIO_UARTX_LSR(offset) \
176 CVMX_ADD_IO_SEG(0x0001180000000828ull + (((offset) & 1) * 1024))
177#define CVMX_MIO_UARTX_MCR(offset) \
178 CVMX_ADD_IO_SEG(0x0001180000000820ull + (((offset) & 1) * 1024))
179#define CVMX_MIO_UARTX_MSR(offset) \
180 CVMX_ADD_IO_SEG(0x0001180000000830ull + (((offset) & 1) * 1024))
181#define CVMX_MIO_UARTX_RBR(offset) \
182 CVMX_ADD_IO_SEG(0x0001180000000800ull + (((offset) & 1) * 1024))
183#define CVMX_MIO_UARTX_RFL(offset) \
184 CVMX_ADD_IO_SEG(0x0001180000000A08ull + (((offset) & 1) * 1024))
185#define CVMX_MIO_UARTX_RFW(offset) \
186 CVMX_ADD_IO_SEG(0x0001180000000930ull + (((offset) & 1) * 1024))
187#define CVMX_MIO_UARTX_SBCR(offset) \
188 CVMX_ADD_IO_SEG(0x0001180000000A20ull + (((offset) & 1) * 1024))
189#define CVMX_MIO_UARTX_SCR(offset) \
190 CVMX_ADD_IO_SEG(0x0001180000000838ull + (((offset) & 1) * 1024))
191#define CVMX_MIO_UARTX_SFE(offset) \
192 CVMX_ADD_IO_SEG(0x0001180000000A30ull + (((offset) & 1) * 1024))
193#define CVMX_MIO_UARTX_SRR(offset) \
194 CVMX_ADD_IO_SEG(0x0001180000000A10ull + (((offset) & 1) * 1024))
195#define CVMX_MIO_UARTX_SRT(offset) \
196 CVMX_ADD_IO_SEG(0x0001180000000A38ull + (((offset) & 1) * 1024))
197#define CVMX_MIO_UARTX_SRTS(offset) \
198 CVMX_ADD_IO_SEG(0x0001180000000A18ull + (((offset) & 1) * 1024))
199#define CVMX_MIO_UARTX_STT(offset) \
200 CVMX_ADD_IO_SEG(0x0001180000000B00ull + (((offset) & 1) * 1024))
201#define CVMX_MIO_UARTX_TFL(offset) \
202 CVMX_ADD_IO_SEG(0x0001180000000A00ull + (((offset) & 1) * 1024))
203#define CVMX_MIO_UARTX_TFR(offset) \
204 CVMX_ADD_IO_SEG(0x0001180000000928ull + (((offset) & 1) * 1024))
205#define CVMX_MIO_UARTX_THR(offset) \
206 CVMX_ADD_IO_SEG(0x0001180000000840ull + (((offset) & 1) * 1024))
207#define CVMX_MIO_UARTX_USR(offset) \
208 CVMX_ADD_IO_SEG(0x0001180000000938ull + (((offset) & 1) * 1024))
209
210union cvmx_mio_boot_bist_stat {
211 uint64_t u64;
212 struct cvmx_mio_boot_bist_stat_s {
213 uint64_t reserved_2_63:62;
214 uint64_t loc:1;
215 uint64_t ncbi:1;
216 } s;
217 struct cvmx_mio_boot_bist_stat_cn30xx {
218 uint64_t reserved_4_63:60;
219 uint64_t ncbo_1:1;
220 uint64_t ncbo_0:1;
221 uint64_t loc:1;
222 uint64_t ncbi:1;
223 } cn30xx;
224 struct cvmx_mio_boot_bist_stat_cn30xx cn31xx;
225 struct cvmx_mio_boot_bist_stat_cn38xx {
226 uint64_t reserved_3_63:61;
227 uint64_t ncbo_0:1;
228 uint64_t loc:1;
229 uint64_t ncbi:1;
230 } cn38xx;
231 struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2;
232 struct cvmx_mio_boot_bist_stat_cn50xx {
233 uint64_t reserved_6_63:58;
234 uint64_t pcm_1:1;
235 uint64_t pcm_0:1;
236 uint64_t ncbo_1:1;
237 uint64_t ncbo_0:1;
238 uint64_t loc:1;
239 uint64_t ncbi:1;
240 } cn50xx;
241 struct cvmx_mio_boot_bist_stat_cn52xx {
242 uint64_t reserved_6_63:58;
243 uint64_t ndf:2;
244 uint64_t ncbo_0:1;
245 uint64_t dma:1;
246 uint64_t loc:1;
247 uint64_t ncbi:1;
248 } cn52xx;
249 struct cvmx_mio_boot_bist_stat_cn52xxp1 {
250 uint64_t reserved_4_63:60;
251 uint64_t ncbo_0:1;
252 uint64_t dma:1;
253 uint64_t loc:1;
254 uint64_t ncbi:1;
255 } cn52xxp1;
256 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx;
257 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1;
258 struct cvmx_mio_boot_bist_stat_cn38xx cn58xx;
259 struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1;
260};
261
262union cvmx_mio_boot_comp {
263 uint64_t u64;
264 struct cvmx_mio_boot_comp_s {
265 uint64_t reserved_10_63:54;
266 uint64_t pctl:5;
267 uint64_t nctl:5;
268 } s;
269 struct cvmx_mio_boot_comp_s cn50xx;
270 struct cvmx_mio_boot_comp_s cn52xx;
271 struct cvmx_mio_boot_comp_s cn52xxp1;
272 struct cvmx_mio_boot_comp_s cn56xx;
273 struct cvmx_mio_boot_comp_s cn56xxp1;
274};
275
276union cvmx_mio_boot_dma_cfgx {
277 uint64_t u64;
278 struct cvmx_mio_boot_dma_cfgx_s {
279 uint64_t en:1;
280 uint64_t rw:1;
281 uint64_t clr:1;
282 uint64_t reserved_60_60:1;
283 uint64_t swap32:1;
284 uint64_t swap16:1;
285 uint64_t swap8:1;
286 uint64_t endian:1;
287 uint64_t size:20;
288 uint64_t adr:36;
289 } s;
290 struct cvmx_mio_boot_dma_cfgx_s cn52xx;
291 struct cvmx_mio_boot_dma_cfgx_s cn52xxp1;
292 struct cvmx_mio_boot_dma_cfgx_s cn56xx;
293 struct cvmx_mio_boot_dma_cfgx_s cn56xxp1;
294};
295
296union cvmx_mio_boot_dma_intx {
297 uint64_t u64;
298 struct cvmx_mio_boot_dma_intx_s {
299 uint64_t reserved_2_63:62;
300 uint64_t dmarq:1;
301 uint64_t done:1;
302 } s;
303 struct cvmx_mio_boot_dma_intx_s cn52xx;
304 struct cvmx_mio_boot_dma_intx_s cn52xxp1;
305 struct cvmx_mio_boot_dma_intx_s cn56xx;
306 struct cvmx_mio_boot_dma_intx_s cn56xxp1;
307};
308
309union cvmx_mio_boot_dma_int_enx {
310 uint64_t u64;
311 struct cvmx_mio_boot_dma_int_enx_s {
312 uint64_t reserved_2_63:62;
313 uint64_t dmarq:1;
314 uint64_t done:1;
315 } s;
316 struct cvmx_mio_boot_dma_int_enx_s cn52xx;
317 struct cvmx_mio_boot_dma_int_enx_s cn52xxp1;
318 struct cvmx_mio_boot_dma_int_enx_s cn56xx;
319 struct cvmx_mio_boot_dma_int_enx_s cn56xxp1;
320};
321
322union cvmx_mio_boot_dma_timx {
323 uint64_t u64;
324 struct cvmx_mio_boot_dma_timx_s {
325 uint64_t dmack_pi:1;
326 uint64_t dmarq_pi:1;
327 uint64_t tim_mult:2;
328 uint64_t rd_dly:3;
329 uint64_t ddr:1;
330 uint64_t width:1;
331 uint64_t reserved_48_54:7;
332 uint64_t pause:6;
333 uint64_t dmack_h:6;
334 uint64_t we_n:6;
335 uint64_t we_a:6;
336 uint64_t oe_n:6;
337 uint64_t oe_a:6;
338 uint64_t dmack_s:6;
339 uint64_t dmarq:6;
340 } s;
341 struct cvmx_mio_boot_dma_timx_s cn52xx;
342 struct cvmx_mio_boot_dma_timx_s cn52xxp1;
343 struct cvmx_mio_boot_dma_timx_s cn56xx;
344 struct cvmx_mio_boot_dma_timx_s cn56xxp1;
345};
346
347union cvmx_mio_boot_err {
348 uint64_t u64;
349 struct cvmx_mio_boot_err_s {
350 uint64_t reserved_2_63:62;
351 uint64_t wait_err:1;
352 uint64_t adr_err:1;
353 } s;
354 struct cvmx_mio_boot_err_s cn30xx;
355 struct cvmx_mio_boot_err_s cn31xx;
356 struct cvmx_mio_boot_err_s cn38xx;
357 struct cvmx_mio_boot_err_s cn38xxp2;
358 struct cvmx_mio_boot_err_s cn50xx;
359 struct cvmx_mio_boot_err_s cn52xx;
360 struct cvmx_mio_boot_err_s cn52xxp1;
361 struct cvmx_mio_boot_err_s cn56xx;
362 struct cvmx_mio_boot_err_s cn56xxp1;
363 struct cvmx_mio_boot_err_s cn58xx;
364 struct cvmx_mio_boot_err_s cn58xxp1;
365};
366
367union cvmx_mio_boot_int {
368 uint64_t u64;
369 struct cvmx_mio_boot_int_s {
370 uint64_t reserved_2_63:62;
371 uint64_t wait_int:1;
372 uint64_t adr_int:1;
373 } s;
374 struct cvmx_mio_boot_int_s cn30xx;
375 struct cvmx_mio_boot_int_s cn31xx;
376 struct cvmx_mio_boot_int_s cn38xx;
377 struct cvmx_mio_boot_int_s cn38xxp2;
378 struct cvmx_mio_boot_int_s cn50xx;
379 struct cvmx_mio_boot_int_s cn52xx;
380 struct cvmx_mio_boot_int_s cn52xxp1;
381 struct cvmx_mio_boot_int_s cn56xx;
382 struct cvmx_mio_boot_int_s cn56xxp1;
383 struct cvmx_mio_boot_int_s cn58xx;
384 struct cvmx_mio_boot_int_s cn58xxp1;
385};
386
387union cvmx_mio_boot_loc_adr {
388 uint64_t u64;
389 struct cvmx_mio_boot_loc_adr_s {
390 uint64_t reserved_8_63:56;
391 uint64_t adr:5;
392 uint64_t reserved_0_2:3;
393 } s;
394 struct cvmx_mio_boot_loc_adr_s cn30xx;
395 struct cvmx_mio_boot_loc_adr_s cn31xx;
396 struct cvmx_mio_boot_loc_adr_s cn38xx;
397 struct cvmx_mio_boot_loc_adr_s cn38xxp2;
398 struct cvmx_mio_boot_loc_adr_s cn50xx;
399 struct cvmx_mio_boot_loc_adr_s cn52xx;
400 struct cvmx_mio_boot_loc_adr_s cn52xxp1;
401 struct cvmx_mio_boot_loc_adr_s cn56xx;
402 struct cvmx_mio_boot_loc_adr_s cn56xxp1;
403 struct cvmx_mio_boot_loc_adr_s cn58xx;
404 struct cvmx_mio_boot_loc_adr_s cn58xxp1;
405};
406
407union cvmx_mio_boot_loc_cfgx {
408 uint64_t u64;
409 struct cvmx_mio_boot_loc_cfgx_s {
410 uint64_t reserved_32_63:32;
411 uint64_t en:1;
412 uint64_t reserved_28_30:3;
413 uint64_t base:25;
414 uint64_t reserved_0_2:3;
415 } s;
416 struct cvmx_mio_boot_loc_cfgx_s cn30xx;
417 struct cvmx_mio_boot_loc_cfgx_s cn31xx;
418 struct cvmx_mio_boot_loc_cfgx_s cn38xx;
419 struct cvmx_mio_boot_loc_cfgx_s cn38xxp2;
420 struct cvmx_mio_boot_loc_cfgx_s cn50xx;
421 struct cvmx_mio_boot_loc_cfgx_s cn52xx;
422 struct cvmx_mio_boot_loc_cfgx_s cn52xxp1;
423 struct cvmx_mio_boot_loc_cfgx_s cn56xx;
424 struct cvmx_mio_boot_loc_cfgx_s cn56xxp1;
425 struct cvmx_mio_boot_loc_cfgx_s cn58xx;
426 struct cvmx_mio_boot_loc_cfgx_s cn58xxp1;
427};
428
429union cvmx_mio_boot_loc_dat {
430 uint64_t u64;
431 struct cvmx_mio_boot_loc_dat_s {
432 uint64_t data:64;
433 } s;
434 struct cvmx_mio_boot_loc_dat_s cn30xx;
435 struct cvmx_mio_boot_loc_dat_s cn31xx;
436 struct cvmx_mio_boot_loc_dat_s cn38xx;
437 struct cvmx_mio_boot_loc_dat_s cn38xxp2;
438 struct cvmx_mio_boot_loc_dat_s cn50xx;
439 struct cvmx_mio_boot_loc_dat_s cn52xx;
440 struct cvmx_mio_boot_loc_dat_s cn52xxp1;
441 struct cvmx_mio_boot_loc_dat_s cn56xx;
442 struct cvmx_mio_boot_loc_dat_s cn56xxp1;
443 struct cvmx_mio_boot_loc_dat_s cn58xx;
444 struct cvmx_mio_boot_loc_dat_s cn58xxp1;
445};
446
447union cvmx_mio_boot_pin_defs {
448 uint64_t u64;
449 struct cvmx_mio_boot_pin_defs_s {
450 uint64_t reserved_16_63:48;
451 uint64_t ale:1;
452 uint64_t width:1;
453 uint64_t dmack_p2:1;
454 uint64_t dmack_p1:1;
455 uint64_t dmack_p0:1;
456 uint64_t term:2;
457 uint64_t nand:1;
458 uint64_t reserved_0_7:8;
459 } s;
460 struct cvmx_mio_boot_pin_defs_cn52xx {
461 uint64_t reserved_16_63:48;
462 uint64_t ale:1;
463 uint64_t width:1;
464 uint64_t reserved_13_13:1;
465 uint64_t dmack_p1:1;
466 uint64_t dmack_p0:1;
467 uint64_t term:2;
468 uint64_t nand:1;
469 uint64_t reserved_0_7:8;
470 } cn52xx;
471 struct cvmx_mio_boot_pin_defs_cn56xx {
472 uint64_t reserved_16_63:48;
473 uint64_t ale:1;
474 uint64_t width:1;
475 uint64_t dmack_p2:1;
476 uint64_t dmack_p1:1;
477 uint64_t dmack_p0:1;
478 uint64_t term:2;
479 uint64_t reserved_0_8:9;
480 } cn56xx;
481};
482
483union cvmx_mio_boot_reg_cfgx {
484 uint64_t u64;
485 struct cvmx_mio_boot_reg_cfgx_s {
486 uint64_t reserved_44_63:20;
487 uint64_t dmack:2;
488 uint64_t tim_mult:2;
489 uint64_t rd_dly:3;
490 uint64_t sam:1;
491 uint64_t we_ext:2;
492 uint64_t oe_ext:2;
493 uint64_t en:1;
494 uint64_t orbit:1;
495 uint64_t ale:1;
496 uint64_t width:1;
497 uint64_t size:12;
498 uint64_t base:16;
499 } s;
500 struct cvmx_mio_boot_reg_cfgx_cn30xx {
501 uint64_t reserved_37_63:27;
502 uint64_t sam:1;
503 uint64_t we_ext:2;
504 uint64_t oe_ext:2;
505 uint64_t en:1;
506 uint64_t orbit:1;
507 uint64_t ale:1;
508 uint64_t width:1;
509 uint64_t size:12;
510 uint64_t base:16;
511 } cn30xx;
512 struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx;
513 struct cvmx_mio_boot_reg_cfgx_cn38xx {
514 uint64_t reserved_32_63:32;
515 uint64_t en:1;
516 uint64_t orbit:1;
517 uint64_t reserved_28_29:2;
518 uint64_t size:12;
519 uint64_t base:16;
520 } cn38xx;
521 struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2;
522 struct cvmx_mio_boot_reg_cfgx_cn50xx {
523 uint64_t reserved_42_63:22;
524 uint64_t tim_mult:2;
525 uint64_t rd_dly:3;
526 uint64_t sam:1;
527 uint64_t we_ext:2;
528 uint64_t oe_ext:2;
529 uint64_t en:1;
530 uint64_t orbit:1;
531 uint64_t ale:1;
532 uint64_t width:1;
533 uint64_t size:12;
534 uint64_t base:16;
535 } cn50xx;
536 struct cvmx_mio_boot_reg_cfgx_s cn52xx;
537 struct cvmx_mio_boot_reg_cfgx_s cn52xxp1;
538 struct cvmx_mio_boot_reg_cfgx_s cn56xx;
539 struct cvmx_mio_boot_reg_cfgx_s cn56xxp1;
540 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx;
541 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1;
542};
543
544union cvmx_mio_boot_reg_timx {
545 uint64_t u64;
546 struct cvmx_mio_boot_reg_timx_s {
547 uint64_t pagem:1;
548 uint64_t waitm:1;
549 uint64_t pages:2;
550 uint64_t ale:6;
551 uint64_t page:6;
552 uint64_t wait:6;
553 uint64_t pause:6;
554 uint64_t wr_hld:6;
555 uint64_t rd_hld:6;
556 uint64_t we:6;
557 uint64_t oe:6;
558 uint64_t ce:6;
559 uint64_t adr:6;
560 } s;
561 struct cvmx_mio_boot_reg_timx_s cn30xx;
562 struct cvmx_mio_boot_reg_timx_s cn31xx;
563 struct cvmx_mio_boot_reg_timx_cn38xx {
564 uint64_t pagem:1;
565 uint64_t waitm:1;
566 uint64_t pages:2;
567 uint64_t reserved_54_59:6;
568 uint64_t page:6;
569 uint64_t wait:6;
570 uint64_t pause:6;
571 uint64_t wr_hld:6;
572 uint64_t rd_hld:6;
573 uint64_t we:6;
574 uint64_t oe:6;
575 uint64_t ce:6;
576 uint64_t adr:6;
577 } cn38xx;
578 struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2;
579 struct cvmx_mio_boot_reg_timx_s cn50xx;
580 struct cvmx_mio_boot_reg_timx_s cn52xx;
581 struct cvmx_mio_boot_reg_timx_s cn52xxp1;
582 struct cvmx_mio_boot_reg_timx_s cn56xx;
583 struct cvmx_mio_boot_reg_timx_s cn56xxp1;
584 struct cvmx_mio_boot_reg_timx_s cn58xx;
585 struct cvmx_mio_boot_reg_timx_s cn58xxp1;
586};
587
588union cvmx_mio_boot_thr {
589 uint64_t u64;
590 struct cvmx_mio_boot_thr_s {
591 uint64_t reserved_22_63:42;
592 uint64_t dma_thr:6;
593 uint64_t reserved_14_15:2;
594 uint64_t fif_cnt:6;
595 uint64_t reserved_6_7:2;
596 uint64_t fif_thr:6;
597 } s;
598 struct cvmx_mio_boot_thr_cn30xx {
599 uint64_t reserved_14_63:50;
600 uint64_t fif_cnt:6;
601 uint64_t reserved_6_7:2;
602 uint64_t fif_thr:6;
603 } cn30xx;
604 struct cvmx_mio_boot_thr_cn30xx cn31xx;
605 struct cvmx_mio_boot_thr_cn30xx cn38xx;
606 struct cvmx_mio_boot_thr_cn30xx cn38xxp2;
607 struct cvmx_mio_boot_thr_cn30xx cn50xx;
608 struct cvmx_mio_boot_thr_s cn52xx;
609 struct cvmx_mio_boot_thr_s cn52xxp1;
610 struct cvmx_mio_boot_thr_s cn56xx;
611 struct cvmx_mio_boot_thr_s cn56xxp1;
612 struct cvmx_mio_boot_thr_cn30xx cn58xx;
613 struct cvmx_mio_boot_thr_cn30xx cn58xxp1;
614};
615
616union cvmx_mio_fus_bnk_datx {
617 uint64_t u64;
618 struct cvmx_mio_fus_bnk_datx_s {
619 uint64_t dat:64;
620 } s;
621 struct cvmx_mio_fus_bnk_datx_s cn50xx;
622 struct cvmx_mio_fus_bnk_datx_s cn52xx;
623 struct cvmx_mio_fus_bnk_datx_s cn52xxp1;
624 struct cvmx_mio_fus_bnk_datx_s cn56xx;
625 struct cvmx_mio_fus_bnk_datx_s cn56xxp1;
626 struct cvmx_mio_fus_bnk_datx_s cn58xx;
627 struct cvmx_mio_fus_bnk_datx_s cn58xxp1;
628};
629
630union cvmx_mio_fus_dat0 {
631 uint64_t u64;
632 struct cvmx_mio_fus_dat0_s {
633 uint64_t reserved_32_63:32;
634 uint64_t man_info:32;
635 } s;
636 struct cvmx_mio_fus_dat0_s cn30xx;
637 struct cvmx_mio_fus_dat0_s cn31xx;
638 struct cvmx_mio_fus_dat0_s cn38xx;
639 struct cvmx_mio_fus_dat0_s cn38xxp2;
640 struct cvmx_mio_fus_dat0_s cn50xx;
641 struct cvmx_mio_fus_dat0_s cn52xx;
642 struct cvmx_mio_fus_dat0_s cn52xxp1;
643 struct cvmx_mio_fus_dat0_s cn56xx;
644 struct cvmx_mio_fus_dat0_s cn56xxp1;
645 struct cvmx_mio_fus_dat0_s cn58xx;
646 struct cvmx_mio_fus_dat0_s cn58xxp1;
647};
648
649union cvmx_mio_fus_dat1 {
650 uint64_t u64;
651 struct cvmx_mio_fus_dat1_s {
652 uint64_t reserved_32_63:32;
653 uint64_t man_info:32;
654 } s;
655 struct cvmx_mio_fus_dat1_s cn30xx;
656 struct cvmx_mio_fus_dat1_s cn31xx;
657 struct cvmx_mio_fus_dat1_s cn38xx;
658 struct cvmx_mio_fus_dat1_s cn38xxp2;
659 struct cvmx_mio_fus_dat1_s cn50xx;
660 struct cvmx_mio_fus_dat1_s cn52xx;
661 struct cvmx_mio_fus_dat1_s cn52xxp1;
662 struct cvmx_mio_fus_dat1_s cn56xx;
663 struct cvmx_mio_fus_dat1_s cn56xxp1;
664 struct cvmx_mio_fus_dat1_s cn58xx;
665 struct cvmx_mio_fus_dat1_s cn58xxp1;
666};
667
668union cvmx_mio_fus_dat2 {
669 uint64_t u64;
670 struct cvmx_mio_fus_dat2_s {
671 uint64_t reserved_34_63:30;
672 uint64_t fus318:1;
673 uint64_t raid_en:1;
674 uint64_t reserved_30_31:2;
675 uint64_t nokasu:1;
676 uint64_t nodfa_cp2:1;
677 uint64_t nomul:1;
678 uint64_t nocrypto:1;
679 uint64_t rst_sht:1;
680 uint64_t bist_dis:1;
681 uint64_t chip_id:8;
682 uint64_t reserved_0_15:16;
683 } s;
684 struct cvmx_mio_fus_dat2_cn30xx {
685 uint64_t reserved_29_63:35;
686 uint64_t nodfa_cp2:1;
687 uint64_t nomul:1;
688 uint64_t nocrypto:1;
689 uint64_t rst_sht:1;
690 uint64_t bist_dis:1;
691 uint64_t chip_id:8;
692 uint64_t pll_off:4;
693 uint64_t reserved_1_11:11;
694 uint64_t pp_dis:1;
695 } cn30xx;
696 struct cvmx_mio_fus_dat2_cn31xx {
697 uint64_t reserved_29_63:35;
698 uint64_t nodfa_cp2:1;
699 uint64_t nomul:1;
700 uint64_t nocrypto:1;
701 uint64_t rst_sht:1;
702 uint64_t bist_dis:1;
703 uint64_t chip_id:8;
704 uint64_t pll_off:4;
705 uint64_t reserved_2_11:10;
706 uint64_t pp_dis:2;
707 } cn31xx;
708 struct cvmx_mio_fus_dat2_cn38xx {
709 uint64_t reserved_29_63:35;
710 uint64_t nodfa_cp2:1;
711 uint64_t nomul:1;
712 uint64_t nocrypto:1;
713 uint64_t rst_sht:1;
714 uint64_t bist_dis:1;
715 uint64_t chip_id:8;
716 uint64_t pp_dis:16;
717 } cn38xx;
718 struct cvmx_mio_fus_dat2_cn38xx cn38xxp2;
719 struct cvmx_mio_fus_dat2_cn50xx {
720 uint64_t reserved_34_63:30;
721 uint64_t fus318:1;
722 uint64_t raid_en:1;
723 uint64_t reserved_30_31:2;
724 uint64_t nokasu:1;
725 uint64_t nodfa_cp2:1;
726 uint64_t nomul:1;
727 uint64_t nocrypto:1;
728 uint64_t rst_sht:1;
729 uint64_t bist_dis:1;
730 uint64_t chip_id:8;
731 uint64_t reserved_2_15:14;
732 uint64_t pp_dis:2;
733 } cn50xx;
734 struct cvmx_mio_fus_dat2_cn52xx {
735 uint64_t reserved_34_63:30;
736 uint64_t fus318:1;
737 uint64_t raid_en:1;
738 uint64_t reserved_30_31:2;
739 uint64_t nokasu:1;
740 uint64_t nodfa_cp2:1;
741 uint64_t nomul:1;
742 uint64_t nocrypto:1;
743 uint64_t rst_sht:1;
744 uint64_t bist_dis:1;
745 uint64_t chip_id:8;
746 uint64_t reserved_4_15:12;
747 uint64_t pp_dis:4;
748 } cn52xx;
749 struct cvmx_mio_fus_dat2_cn52xx cn52xxp1;
750 struct cvmx_mio_fus_dat2_cn56xx {
751 uint64_t reserved_34_63:30;
752 uint64_t fus318:1;
753 uint64_t raid_en:1;
754 uint64_t reserved_30_31:2;
755 uint64_t nokasu:1;
756 uint64_t nodfa_cp2:1;
757 uint64_t nomul:1;
758 uint64_t nocrypto:1;
759 uint64_t rst_sht:1;
760 uint64_t bist_dis:1;
761 uint64_t chip_id:8;
762 uint64_t reserved_12_15:4;
763 uint64_t pp_dis:12;
764 } cn56xx;
765 struct cvmx_mio_fus_dat2_cn56xx cn56xxp1;
766 struct cvmx_mio_fus_dat2_cn58xx {
767 uint64_t reserved_30_63:34;
768 uint64_t nokasu:1;
769 uint64_t nodfa_cp2:1;
770 uint64_t nomul:1;
771 uint64_t nocrypto:1;
772 uint64_t rst_sht:1;
773 uint64_t bist_dis:1;
774 uint64_t chip_id:8;
775 uint64_t pp_dis:16;
776 } cn58xx;
777 struct cvmx_mio_fus_dat2_cn58xx cn58xxp1;
778};
779
780union cvmx_mio_fus_dat3 {
781 uint64_t u64;
782 struct cvmx_mio_fus_dat3_s {
783 uint64_t reserved_32_63:32;
784 uint64_t pll_div4:1;
785 uint64_t zip_crip:2;
786 uint64_t bar2_en:1;
787 uint64_t efus_lck:1;
788 uint64_t efus_ign:1;
789 uint64_t nozip:1;
790 uint64_t nodfa_dte:1;
791 uint64_t icache:24;
792 } s;
793 struct cvmx_mio_fus_dat3_cn30xx {
794 uint64_t reserved_32_63:32;
795 uint64_t pll_div4:1;
796 uint64_t reserved_29_30:2;
797 uint64_t bar2_en:1;
798 uint64_t efus_lck:1;
799 uint64_t efus_ign:1;
800 uint64_t nozip:1;
801 uint64_t nodfa_dte:1;
802 uint64_t icache:24;
803 } cn30xx;
804 struct cvmx_mio_fus_dat3_s cn31xx;
805 struct cvmx_mio_fus_dat3_cn38xx {
806 uint64_t reserved_31_63:33;
807 uint64_t zip_crip:2;
808 uint64_t bar2_en:1;
809 uint64_t efus_lck:1;
810 uint64_t efus_ign:1;
811 uint64_t nozip:1;
812 uint64_t nodfa_dte:1;
813 uint64_t icache:24;
814 } cn38xx;
815 struct cvmx_mio_fus_dat3_cn38xxp2 {
816 uint64_t reserved_29_63:35;
817 uint64_t bar2_en:1;
818 uint64_t efus_lck:1;
819 uint64_t efus_ign:1;
820 uint64_t nozip:1;
821 uint64_t nodfa_dte:1;
822 uint64_t icache:24;
823 } cn38xxp2;
824 struct cvmx_mio_fus_dat3_cn38xx cn50xx;
825 struct cvmx_mio_fus_dat3_cn38xx cn52xx;
826 struct cvmx_mio_fus_dat3_cn38xx cn52xxp1;
827 struct cvmx_mio_fus_dat3_cn38xx cn56xx;
828 struct cvmx_mio_fus_dat3_cn38xx cn56xxp1;
829 struct cvmx_mio_fus_dat3_cn38xx cn58xx;
830 struct cvmx_mio_fus_dat3_cn38xx cn58xxp1;
831};
832
833union cvmx_mio_fus_ema {
834 uint64_t u64;
835 struct cvmx_mio_fus_ema_s {
836 uint64_t reserved_7_63:57;
837 uint64_t eff_ema:3;
838 uint64_t reserved_3_3:1;
839 uint64_t ema:3;
840 } s;
841 struct cvmx_mio_fus_ema_s cn50xx;
842 struct cvmx_mio_fus_ema_s cn52xx;
843 struct cvmx_mio_fus_ema_s cn52xxp1;
844 struct cvmx_mio_fus_ema_s cn56xx;
845 struct cvmx_mio_fus_ema_s cn56xxp1;
846 struct cvmx_mio_fus_ema_cn58xx {
847 uint64_t reserved_2_63:62;
848 uint64_t ema:2;
849 } cn58xx;
850 struct cvmx_mio_fus_ema_cn58xx cn58xxp1;
851};
852
853union cvmx_mio_fus_pdf {
854 uint64_t u64;
855 struct cvmx_mio_fus_pdf_s {
856 uint64_t pdf:64;
857 } s;
858 struct cvmx_mio_fus_pdf_s cn50xx;
859 struct cvmx_mio_fus_pdf_s cn52xx;
860 struct cvmx_mio_fus_pdf_s cn52xxp1;
861 struct cvmx_mio_fus_pdf_s cn56xx;
862 struct cvmx_mio_fus_pdf_s cn56xxp1;
863 struct cvmx_mio_fus_pdf_s cn58xx;
864};
865
866union cvmx_mio_fus_pll {
867 uint64_t u64;
868 struct cvmx_mio_fus_pll_s {
869 uint64_t reserved_2_63:62;
870 uint64_t rfslip:1;
871 uint64_t fbslip:1;
872 } s;
873 struct cvmx_mio_fus_pll_s cn50xx;
874 struct cvmx_mio_fus_pll_s cn52xx;
875 struct cvmx_mio_fus_pll_s cn52xxp1;
876 struct cvmx_mio_fus_pll_s cn56xx;
877 struct cvmx_mio_fus_pll_s cn56xxp1;
878 struct cvmx_mio_fus_pll_s cn58xx;
879 struct cvmx_mio_fus_pll_s cn58xxp1;
880};
881
882union cvmx_mio_fus_prog {
883 uint64_t u64;
884 struct cvmx_mio_fus_prog_s {
885 uint64_t reserved_1_63:63;
886 uint64_t prog:1;
887 } s;
888 struct cvmx_mio_fus_prog_s cn30xx;
889 struct cvmx_mio_fus_prog_s cn31xx;
890 struct cvmx_mio_fus_prog_s cn38xx;
891 struct cvmx_mio_fus_prog_s cn38xxp2;
892 struct cvmx_mio_fus_prog_s cn50xx;
893 struct cvmx_mio_fus_prog_s cn52xx;
894 struct cvmx_mio_fus_prog_s cn52xxp1;
895 struct cvmx_mio_fus_prog_s cn56xx;
896 struct cvmx_mio_fus_prog_s cn56xxp1;
897 struct cvmx_mio_fus_prog_s cn58xx;
898 struct cvmx_mio_fus_prog_s cn58xxp1;
899};
900
901union cvmx_mio_fus_prog_times {
902 uint64_t u64;
903 struct cvmx_mio_fus_prog_times_s {
904 uint64_t reserved_33_63:31;
905 uint64_t prog_pin:1;
906 uint64_t out:8;
907 uint64_t sclk_lo:4;
908 uint64_t sclk_hi:12;
909 uint64_t setup:8;
910 } s;
911 struct cvmx_mio_fus_prog_times_s cn50xx;
912 struct cvmx_mio_fus_prog_times_s cn52xx;
913 struct cvmx_mio_fus_prog_times_s cn52xxp1;
914 struct cvmx_mio_fus_prog_times_s cn56xx;
915 struct cvmx_mio_fus_prog_times_s cn56xxp1;
916 struct cvmx_mio_fus_prog_times_s cn58xx;
917 struct cvmx_mio_fus_prog_times_s cn58xxp1;
918};
919
920union cvmx_mio_fus_rcmd {
921 uint64_t u64;
922 struct cvmx_mio_fus_rcmd_s {
923 uint64_t reserved_24_63:40;
924 uint64_t dat:8;
925 uint64_t reserved_13_15:3;
926 uint64_t pend:1;
927 uint64_t reserved_9_11:3;
928 uint64_t efuse:1;
929 uint64_t addr:8;
930 } s;
931 struct cvmx_mio_fus_rcmd_cn30xx {
932 uint64_t reserved_24_63:40;
933 uint64_t dat:8;
934 uint64_t reserved_13_15:3;
935 uint64_t pend:1;
936 uint64_t reserved_9_11:3;
937 uint64_t efuse:1;
938 uint64_t reserved_7_7:1;
939 uint64_t addr:7;
940 } cn30xx;
941 struct cvmx_mio_fus_rcmd_cn30xx cn31xx;
942 struct cvmx_mio_fus_rcmd_cn30xx cn38xx;
943 struct cvmx_mio_fus_rcmd_cn30xx cn38xxp2;
944 struct cvmx_mio_fus_rcmd_cn30xx cn50xx;
945 struct cvmx_mio_fus_rcmd_s cn52xx;
946 struct cvmx_mio_fus_rcmd_s cn52xxp1;
947 struct cvmx_mio_fus_rcmd_s cn56xx;
948 struct cvmx_mio_fus_rcmd_s cn56xxp1;
949 struct cvmx_mio_fus_rcmd_cn30xx cn58xx;
950 struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1;
951};
952
953union cvmx_mio_fus_spr_repair_res {
954 uint64_t u64;
955 struct cvmx_mio_fus_spr_repair_res_s {
956 uint64_t reserved_42_63:22;
957 uint64_t repair2:14;
958 uint64_t repair1:14;
959 uint64_t repair0:14;
960 } s;
961 struct cvmx_mio_fus_spr_repair_res_s cn30xx;
962 struct cvmx_mio_fus_spr_repair_res_s cn31xx;
963 struct cvmx_mio_fus_spr_repair_res_s cn38xx;
964 struct cvmx_mio_fus_spr_repair_res_s cn50xx;
965 struct cvmx_mio_fus_spr_repair_res_s cn52xx;
966 struct cvmx_mio_fus_spr_repair_res_s cn52xxp1;
967 struct cvmx_mio_fus_spr_repair_res_s cn56xx;
968 struct cvmx_mio_fus_spr_repair_res_s cn56xxp1;
969 struct cvmx_mio_fus_spr_repair_res_s cn58xx;
970 struct cvmx_mio_fus_spr_repair_res_s cn58xxp1;
971};
972
973union cvmx_mio_fus_spr_repair_sum {
974 uint64_t u64;
975 struct cvmx_mio_fus_spr_repair_sum_s {
976 uint64_t reserved_1_63:63;
977 uint64_t too_many:1;
978 } s;
979 struct cvmx_mio_fus_spr_repair_sum_s cn30xx;
980 struct cvmx_mio_fus_spr_repair_sum_s cn31xx;
981 struct cvmx_mio_fus_spr_repair_sum_s cn38xx;
982 struct cvmx_mio_fus_spr_repair_sum_s cn50xx;
983 struct cvmx_mio_fus_spr_repair_sum_s cn52xx;
984 struct cvmx_mio_fus_spr_repair_sum_s cn52xxp1;
985 struct cvmx_mio_fus_spr_repair_sum_s cn56xx;
986 struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1;
987 struct cvmx_mio_fus_spr_repair_sum_s cn58xx;
988 struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1;
989};
990
991union cvmx_mio_fus_unlock {
992 uint64_t u64;
993 struct cvmx_mio_fus_unlock_s {
994 uint64_t reserved_24_63:40;
995 uint64_t key:24;
996 } s;
997 struct cvmx_mio_fus_unlock_s cn30xx;
998 struct cvmx_mio_fus_unlock_s cn31xx;
999};
1000
1001union cvmx_mio_fus_wadr {
1002 uint64_t u64;
1003 struct cvmx_mio_fus_wadr_s {
1004 uint64_t reserved_10_63:54;
1005 uint64_t addr:10;
1006 } s;
1007 struct cvmx_mio_fus_wadr_s cn30xx;
1008 struct cvmx_mio_fus_wadr_s cn31xx;
1009 struct cvmx_mio_fus_wadr_s cn38xx;
1010 struct cvmx_mio_fus_wadr_s cn38xxp2;
1011 struct cvmx_mio_fus_wadr_cn50xx {
1012 uint64_t reserved_2_63:62;
1013 uint64_t addr:2;
1014 } cn50xx;
1015 struct cvmx_mio_fus_wadr_cn52xx {
1016 uint64_t reserved_3_63:61;
1017 uint64_t addr:3;
1018 } cn52xx;
1019 struct cvmx_mio_fus_wadr_cn52xx cn52xxp1;
1020 struct cvmx_mio_fus_wadr_cn52xx cn56xx;
1021 struct cvmx_mio_fus_wadr_cn52xx cn56xxp1;
1022 struct cvmx_mio_fus_wadr_cn50xx cn58xx;
1023 struct cvmx_mio_fus_wadr_cn50xx cn58xxp1;
1024};
1025
1026union cvmx_mio_ndf_dma_cfg {
1027 uint64_t u64;
1028 struct cvmx_mio_ndf_dma_cfg_s {
1029 uint64_t en:1;
1030 uint64_t rw:1;
1031 uint64_t clr:1;
1032 uint64_t reserved_60_60:1;
1033 uint64_t swap32:1;
1034 uint64_t swap16:1;
1035 uint64_t swap8:1;
1036 uint64_t endian:1;
1037 uint64_t size:20;
1038 uint64_t adr:36;
1039 } s;
1040 struct cvmx_mio_ndf_dma_cfg_s cn52xx;
1041};
1042
1043union cvmx_mio_ndf_dma_int {
1044 uint64_t u64;
1045 struct cvmx_mio_ndf_dma_int_s {
1046 uint64_t reserved_1_63:63;
1047 uint64_t done:1;
1048 } s;
1049 struct cvmx_mio_ndf_dma_int_s cn52xx;
1050};
1051
1052union cvmx_mio_ndf_dma_int_en {
1053 uint64_t u64;
1054 struct cvmx_mio_ndf_dma_int_en_s {
1055 uint64_t reserved_1_63:63;
1056 uint64_t done:1;
1057 } s;
1058 struct cvmx_mio_ndf_dma_int_en_s cn52xx;
1059};
1060
1061union cvmx_mio_pll_ctl {
1062 uint64_t u64;
1063 struct cvmx_mio_pll_ctl_s {
1064 uint64_t reserved_5_63:59;
1065 uint64_t bw_ctl:5;
1066 } s;
1067 struct cvmx_mio_pll_ctl_s cn30xx;
1068 struct cvmx_mio_pll_ctl_s cn31xx;
1069};
1070
1071union cvmx_mio_pll_setting {
1072 uint64_t u64;
1073 struct cvmx_mio_pll_setting_s {
1074 uint64_t reserved_17_63:47;
1075 uint64_t setting:17;
1076 } s;
1077 struct cvmx_mio_pll_setting_s cn30xx;
1078 struct cvmx_mio_pll_setting_s cn31xx;
1079};
1080
1081union cvmx_mio_twsx_int {
1082 uint64_t u64;
1083 struct cvmx_mio_twsx_int_s {
1084 uint64_t reserved_12_63:52;
1085 uint64_t scl:1;
1086 uint64_t sda:1;
1087 uint64_t scl_ovr:1;
1088 uint64_t sda_ovr:1;
1089 uint64_t reserved_7_7:1;
1090 uint64_t core_en:1;
1091 uint64_t ts_en:1;
1092 uint64_t st_en:1;
1093 uint64_t reserved_3_3:1;
1094 uint64_t core_int:1;
1095 uint64_t ts_int:1;
1096 uint64_t st_int:1;
1097 } s;
1098 struct cvmx_mio_twsx_int_s cn30xx;
1099 struct cvmx_mio_twsx_int_s cn31xx;
1100 struct cvmx_mio_twsx_int_s cn38xx;
1101 struct cvmx_mio_twsx_int_cn38xxp2 {
1102 uint64_t reserved_7_63:57;
1103 uint64_t core_en:1;
1104 uint64_t ts_en:1;
1105 uint64_t st_en:1;
1106 uint64_t reserved_3_3:1;
1107 uint64_t core_int:1;
1108 uint64_t ts_int:1;
1109 uint64_t st_int:1;
1110 } cn38xxp2;
1111 struct cvmx_mio_twsx_int_s cn50xx;
1112 struct cvmx_mio_twsx_int_s cn52xx;
1113 struct cvmx_mio_twsx_int_s cn52xxp1;
1114 struct cvmx_mio_twsx_int_s cn56xx;
1115 struct cvmx_mio_twsx_int_s cn56xxp1;
1116 struct cvmx_mio_twsx_int_s cn58xx;
1117 struct cvmx_mio_twsx_int_s cn58xxp1;
1118};
1119
1120union cvmx_mio_twsx_sw_twsi {
1121 uint64_t u64;
1122 struct cvmx_mio_twsx_sw_twsi_s {
1123 uint64_t v:1;
1124 uint64_t slonly:1;
1125 uint64_t eia:1;
1126 uint64_t op:4;
1127 uint64_t r:1;
1128 uint64_t sovr:1;
1129 uint64_t size:3;
1130 uint64_t scr:2;
1131 uint64_t a:10;
1132 uint64_t ia:5;
1133 uint64_t eop_ia:3;
1134 uint64_t d:32;
1135 } s;
1136 struct cvmx_mio_twsx_sw_twsi_s cn30xx;
1137 struct cvmx_mio_twsx_sw_twsi_s cn31xx;
1138 struct cvmx_mio_twsx_sw_twsi_s cn38xx;
1139 struct cvmx_mio_twsx_sw_twsi_s cn38xxp2;
1140 struct cvmx_mio_twsx_sw_twsi_s cn50xx;
1141 struct cvmx_mio_twsx_sw_twsi_s cn52xx;
1142 struct cvmx_mio_twsx_sw_twsi_s cn52xxp1;
1143 struct cvmx_mio_twsx_sw_twsi_s cn56xx;
1144 struct cvmx_mio_twsx_sw_twsi_s cn56xxp1;
1145 struct cvmx_mio_twsx_sw_twsi_s cn58xx;
1146 struct cvmx_mio_twsx_sw_twsi_s cn58xxp1;
1147};
1148
1149union cvmx_mio_twsx_sw_twsi_ext {
1150 uint64_t u64;
1151 struct cvmx_mio_twsx_sw_twsi_ext_s {
1152 uint64_t reserved_40_63:24;
1153 uint64_t ia:8;
1154 uint64_t d:32;
1155 } s;
1156 struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx;
1157 struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx;
1158 struct cvmx_mio_twsx_sw_twsi_ext_s cn38xx;
1159 struct cvmx_mio_twsx_sw_twsi_ext_s cn38xxp2;
1160 struct cvmx_mio_twsx_sw_twsi_ext_s cn50xx;
1161 struct cvmx_mio_twsx_sw_twsi_ext_s cn52xx;
1162 struct cvmx_mio_twsx_sw_twsi_ext_s cn52xxp1;
1163 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xx;
1164 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1;
1165 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx;
1166 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1;
1167};
1168
1169union cvmx_mio_twsx_twsi_sw {
1170 uint64_t u64;
1171 struct cvmx_mio_twsx_twsi_sw_s {
1172 uint64_t v:2;
1173 uint64_t reserved_32_61:30;
1174 uint64_t d:32;
1175 } s;
1176 struct cvmx_mio_twsx_twsi_sw_s cn30xx;
1177 struct cvmx_mio_twsx_twsi_sw_s cn31xx;
1178 struct cvmx_mio_twsx_twsi_sw_s cn38xx;
1179 struct cvmx_mio_twsx_twsi_sw_s cn38xxp2;
1180 struct cvmx_mio_twsx_twsi_sw_s cn50xx;
1181 struct cvmx_mio_twsx_twsi_sw_s cn52xx;
1182 struct cvmx_mio_twsx_twsi_sw_s cn52xxp1;
1183 struct cvmx_mio_twsx_twsi_sw_s cn56xx;
1184 struct cvmx_mio_twsx_twsi_sw_s cn56xxp1;
1185 struct cvmx_mio_twsx_twsi_sw_s cn58xx;
1186 struct cvmx_mio_twsx_twsi_sw_s cn58xxp1;
1187};
1188
1189union cvmx_mio_uartx_dlh {
1190 uint64_t u64;
1191 struct cvmx_mio_uartx_dlh_s {
1192 uint64_t reserved_8_63:56;
1193 uint64_t dlh:8;
1194 } s;
1195 struct cvmx_mio_uartx_dlh_s cn30xx;
1196 struct cvmx_mio_uartx_dlh_s cn31xx;
1197 struct cvmx_mio_uartx_dlh_s cn38xx;
1198 struct cvmx_mio_uartx_dlh_s cn38xxp2;
1199 struct cvmx_mio_uartx_dlh_s cn50xx;
1200 struct cvmx_mio_uartx_dlh_s cn52xx;
1201 struct cvmx_mio_uartx_dlh_s cn52xxp1;
1202 struct cvmx_mio_uartx_dlh_s cn56xx;
1203 struct cvmx_mio_uartx_dlh_s cn56xxp1;
1204 struct cvmx_mio_uartx_dlh_s cn58xx;
1205 struct cvmx_mio_uartx_dlh_s cn58xxp1;
1206};
1207
1208union cvmx_mio_uartx_dll {
1209 uint64_t u64;
1210 struct cvmx_mio_uartx_dll_s {
1211 uint64_t reserved_8_63:56;
1212 uint64_t dll:8;
1213 } s;
1214 struct cvmx_mio_uartx_dll_s cn30xx;
1215 struct cvmx_mio_uartx_dll_s cn31xx;
1216 struct cvmx_mio_uartx_dll_s cn38xx;
1217 struct cvmx_mio_uartx_dll_s cn38xxp2;
1218 struct cvmx_mio_uartx_dll_s cn50xx;
1219 struct cvmx_mio_uartx_dll_s cn52xx;
1220 struct cvmx_mio_uartx_dll_s cn52xxp1;
1221 struct cvmx_mio_uartx_dll_s cn56xx;
1222 struct cvmx_mio_uartx_dll_s cn56xxp1;
1223 struct cvmx_mio_uartx_dll_s cn58xx;
1224 struct cvmx_mio_uartx_dll_s cn58xxp1;
1225};
1226
1227union cvmx_mio_uartx_far {
1228 uint64_t u64;
1229 struct cvmx_mio_uartx_far_s {
1230 uint64_t reserved_1_63:63;
1231 uint64_t far:1;
1232 } s;
1233 struct cvmx_mio_uartx_far_s cn30xx;
1234 struct cvmx_mio_uartx_far_s cn31xx;
1235 struct cvmx_mio_uartx_far_s cn38xx;
1236 struct cvmx_mio_uartx_far_s cn38xxp2;
1237 struct cvmx_mio_uartx_far_s cn50xx;
1238 struct cvmx_mio_uartx_far_s cn52xx;
1239 struct cvmx_mio_uartx_far_s cn52xxp1;
1240 struct cvmx_mio_uartx_far_s cn56xx;
1241 struct cvmx_mio_uartx_far_s cn56xxp1;
1242 struct cvmx_mio_uartx_far_s cn58xx;
1243 struct cvmx_mio_uartx_far_s cn58xxp1;
1244};
1245
1246union cvmx_mio_uartx_fcr {
1247 uint64_t u64;
1248 struct cvmx_mio_uartx_fcr_s {
1249 uint64_t reserved_8_63:56;
1250 uint64_t rxtrig:2;
1251 uint64_t txtrig:2;
1252 uint64_t reserved_3_3:1;
1253 uint64_t txfr:1;
1254 uint64_t rxfr:1;
1255 uint64_t en:1;
1256 } s;
1257 struct cvmx_mio_uartx_fcr_s cn30xx;
1258 struct cvmx_mio_uartx_fcr_s cn31xx;
1259 struct cvmx_mio_uartx_fcr_s cn38xx;
1260 struct cvmx_mio_uartx_fcr_s cn38xxp2;
1261 struct cvmx_mio_uartx_fcr_s cn50xx;
1262 struct cvmx_mio_uartx_fcr_s cn52xx;
1263 struct cvmx_mio_uartx_fcr_s cn52xxp1;
1264 struct cvmx_mio_uartx_fcr_s cn56xx;
1265 struct cvmx_mio_uartx_fcr_s cn56xxp1;
1266 struct cvmx_mio_uartx_fcr_s cn58xx;
1267 struct cvmx_mio_uartx_fcr_s cn58xxp1;
1268};
1269
1270union cvmx_mio_uartx_htx {
1271 uint64_t u64;
1272 struct cvmx_mio_uartx_htx_s {
1273 uint64_t reserved_1_63:63;
1274 uint64_t htx:1;
1275 } s;
1276 struct cvmx_mio_uartx_htx_s cn30xx;
1277 struct cvmx_mio_uartx_htx_s cn31xx;
1278 struct cvmx_mio_uartx_htx_s cn38xx;
1279 struct cvmx_mio_uartx_htx_s cn38xxp2;
1280 struct cvmx_mio_uartx_htx_s cn50xx;
1281 struct cvmx_mio_uartx_htx_s cn52xx;
1282 struct cvmx_mio_uartx_htx_s cn52xxp1;
1283 struct cvmx_mio_uartx_htx_s cn56xx;
1284 struct cvmx_mio_uartx_htx_s cn56xxp1;
1285 struct cvmx_mio_uartx_htx_s cn58xx;
1286 struct cvmx_mio_uartx_htx_s cn58xxp1;
1287};
1288
1289union cvmx_mio_uartx_ier {
1290 uint64_t u64;
1291 struct cvmx_mio_uartx_ier_s {
1292 uint64_t reserved_8_63:56;
1293 uint64_t ptime:1;
1294 uint64_t reserved_4_6:3;
1295 uint64_t edssi:1;
1296 uint64_t elsi:1;
1297 uint64_t etbei:1;
1298 uint64_t erbfi:1;
1299 } s;
1300 struct cvmx_mio_uartx_ier_s cn30xx;
1301 struct cvmx_mio_uartx_ier_s cn31xx;
1302 struct cvmx_mio_uartx_ier_s cn38xx;
1303 struct cvmx_mio_uartx_ier_s cn38xxp2;
1304 struct cvmx_mio_uartx_ier_s cn50xx;
1305 struct cvmx_mio_uartx_ier_s cn52xx;
1306 struct cvmx_mio_uartx_ier_s cn52xxp1;
1307 struct cvmx_mio_uartx_ier_s cn56xx;
1308 struct cvmx_mio_uartx_ier_s cn56xxp1;
1309 struct cvmx_mio_uartx_ier_s cn58xx;
1310 struct cvmx_mio_uartx_ier_s cn58xxp1;
1311};
1312
1313union cvmx_mio_uartx_iir {
1314 uint64_t u64;
1315 struct cvmx_mio_uartx_iir_s {
1316 uint64_t reserved_8_63:56;
1317 uint64_t fen:2;
1318 uint64_t reserved_4_5:2;
1319 uint64_t iid:4;
1320 } s;
1321 struct cvmx_mio_uartx_iir_s cn30xx;
1322 struct cvmx_mio_uartx_iir_s cn31xx;
1323 struct cvmx_mio_uartx_iir_s cn38xx;
1324 struct cvmx_mio_uartx_iir_s cn38xxp2;
1325 struct cvmx_mio_uartx_iir_s cn50xx;
1326 struct cvmx_mio_uartx_iir_s cn52xx;
1327 struct cvmx_mio_uartx_iir_s cn52xxp1;
1328 struct cvmx_mio_uartx_iir_s cn56xx;
1329 struct cvmx_mio_uartx_iir_s cn56xxp1;
1330 struct cvmx_mio_uartx_iir_s cn58xx;
1331 struct cvmx_mio_uartx_iir_s cn58xxp1;
1332};
1333
1334union cvmx_mio_uartx_lcr {
1335 uint64_t u64;
1336 struct cvmx_mio_uartx_lcr_s {
1337 uint64_t reserved_8_63:56;
1338 uint64_t dlab:1;
1339 uint64_t brk:1;
1340 uint64_t reserved_5_5:1;
1341 uint64_t eps:1;
1342 uint64_t pen:1;
1343 uint64_t stop:1;
1344 uint64_t cls:2;
1345 } s;
1346 struct cvmx_mio_uartx_lcr_s cn30xx;
1347 struct cvmx_mio_uartx_lcr_s cn31xx;
1348 struct cvmx_mio_uartx_lcr_s cn38xx;
1349 struct cvmx_mio_uartx_lcr_s cn38xxp2;
1350 struct cvmx_mio_uartx_lcr_s cn50xx;
1351 struct cvmx_mio_uartx_lcr_s cn52xx;
1352 struct cvmx_mio_uartx_lcr_s cn52xxp1;
1353 struct cvmx_mio_uartx_lcr_s cn56xx;
1354 struct cvmx_mio_uartx_lcr_s cn56xxp1;
1355 struct cvmx_mio_uartx_lcr_s cn58xx;
1356 struct cvmx_mio_uartx_lcr_s cn58xxp1;
1357};
1358
1359union cvmx_mio_uartx_lsr {
1360 uint64_t u64;
1361 struct cvmx_mio_uartx_lsr_s {
1362 uint64_t reserved_8_63:56;
1363 uint64_t ferr:1;
1364 uint64_t temt:1;
1365 uint64_t thre:1;
1366 uint64_t bi:1;
1367 uint64_t fe:1;
1368 uint64_t pe:1;
1369 uint64_t oe:1;
1370 uint64_t dr:1;
1371 } s;
1372 struct cvmx_mio_uartx_lsr_s cn30xx;
1373 struct cvmx_mio_uartx_lsr_s cn31xx;
1374 struct cvmx_mio_uartx_lsr_s cn38xx;
1375 struct cvmx_mio_uartx_lsr_s cn38xxp2;
1376 struct cvmx_mio_uartx_lsr_s cn50xx;
1377 struct cvmx_mio_uartx_lsr_s cn52xx;
1378 struct cvmx_mio_uartx_lsr_s cn52xxp1;
1379 struct cvmx_mio_uartx_lsr_s cn56xx;
1380 struct cvmx_mio_uartx_lsr_s cn56xxp1;
1381 struct cvmx_mio_uartx_lsr_s cn58xx;
1382 struct cvmx_mio_uartx_lsr_s cn58xxp1;
1383};
1384
1385union cvmx_mio_uartx_mcr {
1386 uint64_t u64;
1387 struct cvmx_mio_uartx_mcr_s {
1388 uint64_t reserved_6_63:58;
1389 uint64_t afce:1;
1390 uint64_t loop:1;
1391 uint64_t out2:1;
1392 uint64_t out1:1;
1393 uint64_t rts:1;
1394 uint64_t dtr:1;
1395 } s;
1396 struct cvmx_mio_uartx_mcr_s cn30xx;
1397 struct cvmx_mio_uartx_mcr_s cn31xx;
1398 struct cvmx_mio_uartx_mcr_s cn38xx;
1399 struct cvmx_mio_uartx_mcr_s cn38xxp2;
1400 struct cvmx_mio_uartx_mcr_s cn50xx;
1401 struct cvmx_mio_uartx_mcr_s cn52xx;
1402 struct cvmx_mio_uartx_mcr_s cn52xxp1;
1403 struct cvmx_mio_uartx_mcr_s cn56xx;
1404 struct cvmx_mio_uartx_mcr_s cn56xxp1;
1405 struct cvmx_mio_uartx_mcr_s cn58xx;
1406 struct cvmx_mio_uartx_mcr_s cn58xxp1;
1407};
1408
1409union cvmx_mio_uartx_msr {
1410 uint64_t u64;
1411 struct cvmx_mio_uartx_msr_s {
1412 uint64_t reserved_8_63:56;
1413 uint64_t dcd:1;
1414 uint64_t ri:1;
1415 uint64_t dsr:1;
1416 uint64_t cts:1;
1417 uint64_t ddcd:1;
1418 uint64_t teri:1;
1419 uint64_t ddsr:1;
1420 uint64_t dcts:1;
1421 } s;
1422 struct cvmx_mio_uartx_msr_s cn30xx;
1423 struct cvmx_mio_uartx_msr_s cn31xx;
1424 struct cvmx_mio_uartx_msr_s cn38xx;
1425 struct cvmx_mio_uartx_msr_s cn38xxp2;
1426 struct cvmx_mio_uartx_msr_s cn50xx;
1427 struct cvmx_mio_uartx_msr_s cn52xx;
1428 struct cvmx_mio_uartx_msr_s cn52xxp1;
1429 struct cvmx_mio_uartx_msr_s cn56xx;
1430 struct cvmx_mio_uartx_msr_s cn56xxp1;
1431 struct cvmx_mio_uartx_msr_s cn58xx;
1432 struct cvmx_mio_uartx_msr_s cn58xxp1;
1433};
1434
1435union cvmx_mio_uartx_rbr {
1436 uint64_t u64;
1437 struct cvmx_mio_uartx_rbr_s {
1438 uint64_t reserved_8_63:56;
1439 uint64_t rbr:8;
1440 } s;
1441 struct cvmx_mio_uartx_rbr_s cn30xx;
1442 struct cvmx_mio_uartx_rbr_s cn31xx;
1443 struct cvmx_mio_uartx_rbr_s cn38xx;
1444 struct cvmx_mio_uartx_rbr_s cn38xxp2;
1445 struct cvmx_mio_uartx_rbr_s cn50xx;
1446 struct cvmx_mio_uartx_rbr_s cn52xx;
1447 struct cvmx_mio_uartx_rbr_s cn52xxp1;
1448 struct cvmx_mio_uartx_rbr_s cn56xx;
1449 struct cvmx_mio_uartx_rbr_s cn56xxp1;
1450 struct cvmx_mio_uartx_rbr_s cn58xx;
1451 struct cvmx_mio_uartx_rbr_s cn58xxp1;
1452};
1453
1454union cvmx_mio_uartx_rfl {
1455 uint64_t u64;
1456 struct cvmx_mio_uartx_rfl_s {
1457 uint64_t reserved_7_63:57;
1458 uint64_t rfl:7;
1459 } s;
1460 struct cvmx_mio_uartx_rfl_s cn30xx;
1461 struct cvmx_mio_uartx_rfl_s cn31xx;
1462 struct cvmx_mio_uartx_rfl_s cn38xx;
1463 struct cvmx_mio_uartx_rfl_s cn38xxp2;
1464 struct cvmx_mio_uartx_rfl_s cn50xx;
1465 struct cvmx_mio_uartx_rfl_s cn52xx;
1466 struct cvmx_mio_uartx_rfl_s cn52xxp1;
1467 struct cvmx_mio_uartx_rfl_s cn56xx;
1468 struct cvmx_mio_uartx_rfl_s cn56xxp1;
1469 struct cvmx_mio_uartx_rfl_s cn58xx;
1470 struct cvmx_mio_uartx_rfl_s cn58xxp1;
1471};
1472
1473union cvmx_mio_uartx_rfw {
1474 uint64_t u64;
1475 struct cvmx_mio_uartx_rfw_s {
1476 uint64_t reserved_10_63:54;
1477 uint64_t rffe:1;
1478 uint64_t rfpe:1;
1479 uint64_t rfwd:8;
1480 } s;
1481 struct cvmx_mio_uartx_rfw_s cn30xx;
1482 struct cvmx_mio_uartx_rfw_s cn31xx;
1483 struct cvmx_mio_uartx_rfw_s cn38xx;
1484 struct cvmx_mio_uartx_rfw_s cn38xxp2;
1485 struct cvmx_mio_uartx_rfw_s cn50xx;
1486 struct cvmx_mio_uartx_rfw_s cn52xx;
1487 struct cvmx_mio_uartx_rfw_s cn52xxp1;
1488 struct cvmx_mio_uartx_rfw_s cn56xx;
1489 struct cvmx_mio_uartx_rfw_s cn56xxp1;
1490 struct cvmx_mio_uartx_rfw_s cn58xx;
1491 struct cvmx_mio_uartx_rfw_s cn58xxp1;
1492};
1493
1494union cvmx_mio_uartx_sbcr {
1495 uint64_t u64;
1496 struct cvmx_mio_uartx_sbcr_s {
1497 uint64_t reserved_1_63:63;
1498 uint64_t sbcr:1;
1499 } s;
1500 struct cvmx_mio_uartx_sbcr_s cn30xx;
1501 struct cvmx_mio_uartx_sbcr_s cn31xx;
1502 struct cvmx_mio_uartx_sbcr_s cn38xx;
1503 struct cvmx_mio_uartx_sbcr_s cn38xxp2;
1504 struct cvmx_mio_uartx_sbcr_s cn50xx;
1505 struct cvmx_mio_uartx_sbcr_s cn52xx;
1506 struct cvmx_mio_uartx_sbcr_s cn52xxp1;
1507 struct cvmx_mio_uartx_sbcr_s cn56xx;
1508 struct cvmx_mio_uartx_sbcr_s cn56xxp1;
1509 struct cvmx_mio_uartx_sbcr_s cn58xx;
1510 struct cvmx_mio_uartx_sbcr_s cn58xxp1;
1511};
1512
1513union cvmx_mio_uartx_scr {
1514 uint64_t u64;
1515 struct cvmx_mio_uartx_scr_s {
1516 uint64_t reserved_8_63:56;
1517 uint64_t scr:8;
1518 } s;
1519 struct cvmx_mio_uartx_scr_s cn30xx;
1520 struct cvmx_mio_uartx_scr_s cn31xx;
1521 struct cvmx_mio_uartx_scr_s cn38xx;
1522 struct cvmx_mio_uartx_scr_s cn38xxp2;
1523 struct cvmx_mio_uartx_scr_s cn50xx;
1524 struct cvmx_mio_uartx_scr_s cn52xx;
1525 struct cvmx_mio_uartx_scr_s cn52xxp1;
1526 struct cvmx_mio_uartx_scr_s cn56xx;
1527 struct cvmx_mio_uartx_scr_s cn56xxp1;
1528 struct cvmx_mio_uartx_scr_s cn58xx;
1529 struct cvmx_mio_uartx_scr_s cn58xxp1;
1530};
1531
1532union cvmx_mio_uartx_sfe {
1533 uint64_t u64;
1534 struct cvmx_mio_uartx_sfe_s {
1535 uint64_t reserved_1_63:63;
1536 uint64_t sfe:1;
1537 } s;
1538 struct cvmx_mio_uartx_sfe_s cn30xx;
1539 struct cvmx_mio_uartx_sfe_s cn31xx;
1540 struct cvmx_mio_uartx_sfe_s cn38xx;
1541 struct cvmx_mio_uartx_sfe_s cn38xxp2;
1542 struct cvmx_mio_uartx_sfe_s cn50xx;
1543 struct cvmx_mio_uartx_sfe_s cn52xx;
1544 struct cvmx_mio_uartx_sfe_s cn52xxp1;
1545 struct cvmx_mio_uartx_sfe_s cn56xx;
1546 struct cvmx_mio_uartx_sfe_s cn56xxp1;
1547 struct cvmx_mio_uartx_sfe_s cn58xx;
1548 struct cvmx_mio_uartx_sfe_s cn58xxp1;
1549};
1550
1551union cvmx_mio_uartx_srr {
1552 uint64_t u64;
1553 struct cvmx_mio_uartx_srr_s {
1554 uint64_t reserved_3_63:61;
1555 uint64_t stfr:1;
1556 uint64_t srfr:1;
1557 uint64_t usr:1;
1558 } s;
1559 struct cvmx_mio_uartx_srr_s cn30xx;
1560 struct cvmx_mio_uartx_srr_s cn31xx;
1561 struct cvmx_mio_uartx_srr_s cn38xx;
1562 struct cvmx_mio_uartx_srr_s cn38xxp2;
1563 struct cvmx_mio_uartx_srr_s cn50xx;
1564 struct cvmx_mio_uartx_srr_s cn52xx;
1565 struct cvmx_mio_uartx_srr_s cn52xxp1;
1566 struct cvmx_mio_uartx_srr_s cn56xx;
1567 struct cvmx_mio_uartx_srr_s cn56xxp1;
1568 struct cvmx_mio_uartx_srr_s cn58xx;
1569 struct cvmx_mio_uartx_srr_s cn58xxp1;
1570};
1571
1572union cvmx_mio_uartx_srt {
1573 uint64_t u64;
1574 struct cvmx_mio_uartx_srt_s {
1575 uint64_t reserved_2_63:62;
1576 uint64_t srt:2;
1577 } s;
1578 struct cvmx_mio_uartx_srt_s cn30xx;
1579 struct cvmx_mio_uartx_srt_s cn31xx;
1580 struct cvmx_mio_uartx_srt_s cn38xx;
1581 struct cvmx_mio_uartx_srt_s cn38xxp2;
1582 struct cvmx_mio_uartx_srt_s cn50xx;
1583 struct cvmx_mio_uartx_srt_s cn52xx;
1584 struct cvmx_mio_uartx_srt_s cn52xxp1;
1585 struct cvmx_mio_uartx_srt_s cn56xx;
1586 struct cvmx_mio_uartx_srt_s cn56xxp1;
1587 struct cvmx_mio_uartx_srt_s cn58xx;
1588 struct cvmx_mio_uartx_srt_s cn58xxp1;
1589};
1590
1591union cvmx_mio_uartx_srts {
1592 uint64_t u64;
1593 struct cvmx_mio_uartx_srts_s {
1594 uint64_t reserved_1_63:63;
1595 uint64_t srts:1;
1596 } s;
1597 struct cvmx_mio_uartx_srts_s cn30xx;
1598 struct cvmx_mio_uartx_srts_s cn31xx;
1599 struct cvmx_mio_uartx_srts_s cn38xx;
1600 struct cvmx_mio_uartx_srts_s cn38xxp2;
1601 struct cvmx_mio_uartx_srts_s cn50xx;
1602 struct cvmx_mio_uartx_srts_s cn52xx;
1603 struct cvmx_mio_uartx_srts_s cn52xxp1;
1604 struct cvmx_mio_uartx_srts_s cn56xx;
1605 struct cvmx_mio_uartx_srts_s cn56xxp1;
1606 struct cvmx_mio_uartx_srts_s cn58xx;
1607 struct cvmx_mio_uartx_srts_s cn58xxp1;
1608};
1609
1610union cvmx_mio_uartx_stt {
1611 uint64_t u64;
1612 struct cvmx_mio_uartx_stt_s {
1613 uint64_t reserved_2_63:62;
1614 uint64_t stt:2;
1615 } s;
1616 struct cvmx_mio_uartx_stt_s cn30xx;
1617 struct cvmx_mio_uartx_stt_s cn31xx;
1618 struct cvmx_mio_uartx_stt_s cn38xx;
1619 struct cvmx_mio_uartx_stt_s cn38xxp2;
1620 struct cvmx_mio_uartx_stt_s cn50xx;
1621 struct cvmx_mio_uartx_stt_s cn52xx;
1622 struct cvmx_mio_uartx_stt_s cn52xxp1;
1623 struct cvmx_mio_uartx_stt_s cn56xx;
1624 struct cvmx_mio_uartx_stt_s cn56xxp1;
1625 struct cvmx_mio_uartx_stt_s cn58xx;
1626 struct cvmx_mio_uartx_stt_s cn58xxp1;
1627};
1628
1629union cvmx_mio_uartx_tfl {
1630 uint64_t u64;
1631 struct cvmx_mio_uartx_tfl_s {
1632 uint64_t reserved_7_63:57;
1633 uint64_t tfl:7;
1634 } s;
1635 struct cvmx_mio_uartx_tfl_s cn30xx;
1636 struct cvmx_mio_uartx_tfl_s cn31xx;
1637 struct cvmx_mio_uartx_tfl_s cn38xx;
1638 struct cvmx_mio_uartx_tfl_s cn38xxp2;
1639 struct cvmx_mio_uartx_tfl_s cn50xx;
1640 struct cvmx_mio_uartx_tfl_s cn52xx;
1641 struct cvmx_mio_uartx_tfl_s cn52xxp1;
1642 struct cvmx_mio_uartx_tfl_s cn56xx;
1643 struct cvmx_mio_uartx_tfl_s cn56xxp1;
1644 struct cvmx_mio_uartx_tfl_s cn58xx;
1645 struct cvmx_mio_uartx_tfl_s cn58xxp1;
1646};
1647
1648union cvmx_mio_uartx_tfr {
1649 uint64_t u64;
1650 struct cvmx_mio_uartx_tfr_s {
1651 uint64_t reserved_8_63:56;
1652 uint64_t tfr:8;
1653 } s;
1654 struct cvmx_mio_uartx_tfr_s cn30xx;
1655 struct cvmx_mio_uartx_tfr_s cn31xx;
1656 struct cvmx_mio_uartx_tfr_s cn38xx;
1657 struct cvmx_mio_uartx_tfr_s cn38xxp2;
1658 struct cvmx_mio_uartx_tfr_s cn50xx;
1659 struct cvmx_mio_uartx_tfr_s cn52xx;
1660 struct cvmx_mio_uartx_tfr_s cn52xxp1;
1661 struct cvmx_mio_uartx_tfr_s cn56xx;
1662 struct cvmx_mio_uartx_tfr_s cn56xxp1;
1663 struct cvmx_mio_uartx_tfr_s cn58xx;
1664 struct cvmx_mio_uartx_tfr_s cn58xxp1;
1665};
1666
1667union cvmx_mio_uartx_thr {
1668 uint64_t u64;
1669 struct cvmx_mio_uartx_thr_s {
1670 uint64_t reserved_8_63:56;
1671 uint64_t thr:8;
1672 } s;
1673 struct cvmx_mio_uartx_thr_s cn30xx;
1674 struct cvmx_mio_uartx_thr_s cn31xx;
1675 struct cvmx_mio_uartx_thr_s cn38xx;
1676 struct cvmx_mio_uartx_thr_s cn38xxp2;
1677 struct cvmx_mio_uartx_thr_s cn50xx;
1678 struct cvmx_mio_uartx_thr_s cn52xx;
1679 struct cvmx_mio_uartx_thr_s cn52xxp1;
1680 struct cvmx_mio_uartx_thr_s cn56xx;
1681 struct cvmx_mio_uartx_thr_s cn56xxp1;
1682 struct cvmx_mio_uartx_thr_s cn58xx;
1683 struct cvmx_mio_uartx_thr_s cn58xxp1;
1684};
1685
1686union cvmx_mio_uartx_usr {
1687 uint64_t u64;
1688 struct cvmx_mio_uartx_usr_s {
1689 uint64_t reserved_5_63:59;
1690 uint64_t rff:1;
1691 uint64_t rfne:1;
1692 uint64_t tfe:1;
1693 uint64_t tfnf:1;
1694 uint64_t busy:1;
1695 } s;
1696 struct cvmx_mio_uartx_usr_s cn30xx;
1697 struct cvmx_mio_uartx_usr_s cn31xx;
1698 struct cvmx_mio_uartx_usr_s cn38xx;
1699 struct cvmx_mio_uartx_usr_s cn38xxp2;
1700 struct cvmx_mio_uartx_usr_s cn50xx;
1701 struct cvmx_mio_uartx_usr_s cn52xx;
1702 struct cvmx_mio_uartx_usr_s cn52xxp1;
1703 struct cvmx_mio_uartx_usr_s cn56xx;
1704 struct cvmx_mio_uartx_usr_s cn56xxp1;
1705 struct cvmx_mio_uartx_usr_s cn58xx;
1706 struct cvmx_mio_uartx_usr_s cn58xxp1;
1707};
1708
1709union cvmx_mio_uart2_dlh {
1710 uint64_t u64;
1711 struct cvmx_mio_uart2_dlh_s {
1712 uint64_t reserved_8_63:56;
1713 uint64_t dlh:8;
1714 } s;
1715 struct cvmx_mio_uart2_dlh_s cn52xx;
1716 struct cvmx_mio_uart2_dlh_s cn52xxp1;
1717};
1718
1719union cvmx_mio_uart2_dll {
1720 uint64_t u64;
1721 struct cvmx_mio_uart2_dll_s {
1722 uint64_t reserved_8_63:56;
1723 uint64_t dll:8;
1724 } s;
1725 struct cvmx_mio_uart2_dll_s cn52xx;
1726 struct cvmx_mio_uart2_dll_s cn52xxp1;
1727};
1728
1729union cvmx_mio_uart2_far {
1730 uint64_t u64;
1731 struct cvmx_mio_uart2_far_s {
1732 uint64_t reserved_1_63:63;
1733 uint64_t far:1;
1734 } s;
1735 struct cvmx_mio_uart2_far_s cn52xx;
1736 struct cvmx_mio_uart2_far_s cn52xxp1;
1737};
1738
1739union cvmx_mio_uart2_fcr {
1740 uint64_t u64;
1741 struct cvmx_mio_uart2_fcr_s {
1742 uint64_t reserved_8_63:56;
1743 uint64_t rxtrig:2;
1744 uint64_t txtrig:2;
1745 uint64_t reserved_3_3:1;
1746 uint64_t txfr:1;
1747 uint64_t rxfr:1;
1748 uint64_t en:1;
1749 } s;
1750 struct cvmx_mio_uart2_fcr_s cn52xx;
1751 struct cvmx_mio_uart2_fcr_s cn52xxp1;
1752};
1753
1754union cvmx_mio_uart2_htx {
1755 uint64_t u64;
1756 struct cvmx_mio_uart2_htx_s {
1757 uint64_t reserved_1_63:63;
1758 uint64_t htx:1;
1759 } s;
1760 struct cvmx_mio_uart2_htx_s cn52xx;
1761 struct cvmx_mio_uart2_htx_s cn52xxp1;
1762};
1763
1764union cvmx_mio_uart2_ier {
1765 uint64_t u64;
1766 struct cvmx_mio_uart2_ier_s {
1767 uint64_t reserved_8_63:56;
1768 uint64_t ptime:1;
1769 uint64_t reserved_4_6:3;
1770 uint64_t edssi:1;
1771 uint64_t elsi:1;
1772 uint64_t etbei:1;
1773 uint64_t erbfi:1;
1774 } s;
1775 struct cvmx_mio_uart2_ier_s cn52xx;
1776 struct cvmx_mio_uart2_ier_s cn52xxp1;
1777};
1778
1779union cvmx_mio_uart2_iir {
1780 uint64_t u64;
1781 struct cvmx_mio_uart2_iir_s {
1782 uint64_t reserved_8_63:56;
1783 uint64_t fen:2;
1784 uint64_t reserved_4_5:2;
1785 uint64_t iid:4;
1786 } s;
1787 struct cvmx_mio_uart2_iir_s cn52xx;
1788 struct cvmx_mio_uart2_iir_s cn52xxp1;
1789};
1790
1791union cvmx_mio_uart2_lcr {
1792 uint64_t u64;
1793 struct cvmx_mio_uart2_lcr_s {
1794 uint64_t reserved_8_63:56;
1795 uint64_t dlab:1;
1796 uint64_t brk:1;
1797 uint64_t reserved_5_5:1;
1798 uint64_t eps:1;
1799 uint64_t pen:1;
1800 uint64_t stop:1;
1801 uint64_t cls:2;
1802 } s;
1803 struct cvmx_mio_uart2_lcr_s cn52xx;
1804 struct cvmx_mio_uart2_lcr_s cn52xxp1;
1805};
1806
1807union cvmx_mio_uart2_lsr {
1808 uint64_t u64;
1809 struct cvmx_mio_uart2_lsr_s {
1810 uint64_t reserved_8_63:56;
1811 uint64_t ferr:1;
1812 uint64_t temt:1;
1813 uint64_t thre:1;
1814 uint64_t bi:1;
1815 uint64_t fe:1;
1816 uint64_t pe:1;
1817 uint64_t oe:1;
1818 uint64_t dr:1;
1819 } s;
1820 struct cvmx_mio_uart2_lsr_s cn52xx;
1821 struct cvmx_mio_uart2_lsr_s cn52xxp1;
1822};
1823
1824union cvmx_mio_uart2_mcr {
1825 uint64_t u64;
1826 struct cvmx_mio_uart2_mcr_s {
1827 uint64_t reserved_6_63:58;
1828 uint64_t afce:1;
1829 uint64_t loop:1;
1830 uint64_t out2:1;
1831 uint64_t out1:1;
1832 uint64_t rts:1;
1833 uint64_t dtr:1;
1834 } s;
1835 struct cvmx_mio_uart2_mcr_s cn52xx;
1836 struct cvmx_mio_uart2_mcr_s cn52xxp1;
1837};
1838
1839union cvmx_mio_uart2_msr {
1840 uint64_t u64;
1841 struct cvmx_mio_uart2_msr_s {
1842 uint64_t reserved_8_63:56;
1843 uint64_t dcd:1;
1844 uint64_t ri:1;
1845 uint64_t dsr:1;
1846 uint64_t cts:1;
1847 uint64_t ddcd:1;
1848 uint64_t teri:1;
1849 uint64_t ddsr:1;
1850 uint64_t dcts:1;
1851 } s;
1852 struct cvmx_mio_uart2_msr_s cn52xx;
1853 struct cvmx_mio_uart2_msr_s cn52xxp1;
1854};
1855
1856union cvmx_mio_uart2_rbr {
1857 uint64_t u64;
1858 struct cvmx_mio_uart2_rbr_s {
1859 uint64_t reserved_8_63:56;
1860 uint64_t rbr:8;
1861 } s;
1862 struct cvmx_mio_uart2_rbr_s cn52xx;
1863 struct cvmx_mio_uart2_rbr_s cn52xxp1;
1864};
1865
1866union cvmx_mio_uart2_rfl {
1867 uint64_t u64;
1868 struct cvmx_mio_uart2_rfl_s {
1869 uint64_t reserved_7_63:57;
1870 uint64_t rfl:7;
1871 } s;
1872 struct cvmx_mio_uart2_rfl_s cn52xx;
1873 struct cvmx_mio_uart2_rfl_s cn52xxp1;
1874};
1875
1876union cvmx_mio_uart2_rfw {
1877 uint64_t u64;
1878 struct cvmx_mio_uart2_rfw_s {
1879 uint64_t reserved_10_63:54;
1880 uint64_t rffe:1;
1881 uint64_t rfpe:1;
1882 uint64_t rfwd:8;
1883 } s;
1884 struct cvmx_mio_uart2_rfw_s cn52xx;
1885 struct cvmx_mio_uart2_rfw_s cn52xxp1;
1886};
1887
1888union cvmx_mio_uart2_sbcr {
1889 uint64_t u64;
1890 struct cvmx_mio_uart2_sbcr_s {
1891 uint64_t reserved_1_63:63;
1892 uint64_t sbcr:1;
1893 } s;
1894 struct cvmx_mio_uart2_sbcr_s cn52xx;
1895 struct cvmx_mio_uart2_sbcr_s cn52xxp1;
1896};
1897
1898union cvmx_mio_uart2_scr {
1899 uint64_t u64;
1900 struct cvmx_mio_uart2_scr_s {
1901 uint64_t reserved_8_63:56;
1902 uint64_t scr:8;
1903 } s;
1904 struct cvmx_mio_uart2_scr_s cn52xx;
1905 struct cvmx_mio_uart2_scr_s cn52xxp1;
1906};
1907
1908union cvmx_mio_uart2_sfe {
1909 uint64_t u64;
1910 struct cvmx_mio_uart2_sfe_s {
1911 uint64_t reserved_1_63:63;
1912 uint64_t sfe:1;
1913 } s;
1914 struct cvmx_mio_uart2_sfe_s cn52xx;
1915 struct cvmx_mio_uart2_sfe_s cn52xxp1;
1916};
1917
1918union cvmx_mio_uart2_srr {
1919 uint64_t u64;
1920 struct cvmx_mio_uart2_srr_s {
1921 uint64_t reserved_3_63:61;
1922 uint64_t stfr:1;
1923 uint64_t srfr:1;
1924 uint64_t usr:1;
1925 } s;
1926 struct cvmx_mio_uart2_srr_s cn52xx;
1927 struct cvmx_mio_uart2_srr_s cn52xxp1;
1928};
1929
1930union cvmx_mio_uart2_srt {
1931 uint64_t u64;
1932 struct cvmx_mio_uart2_srt_s {
1933 uint64_t reserved_2_63:62;
1934 uint64_t srt:2;
1935 } s;
1936 struct cvmx_mio_uart2_srt_s cn52xx;
1937 struct cvmx_mio_uart2_srt_s cn52xxp1;
1938};
1939
1940union cvmx_mio_uart2_srts {
1941 uint64_t u64;
1942 struct cvmx_mio_uart2_srts_s {
1943 uint64_t reserved_1_63:63;
1944 uint64_t srts:1;
1945 } s;
1946 struct cvmx_mio_uart2_srts_s cn52xx;
1947 struct cvmx_mio_uart2_srts_s cn52xxp1;
1948};
1949
1950union cvmx_mio_uart2_stt {
1951 uint64_t u64;
1952 struct cvmx_mio_uart2_stt_s {
1953 uint64_t reserved_2_63:62;
1954 uint64_t stt:2;
1955 } s;
1956 struct cvmx_mio_uart2_stt_s cn52xx;
1957 struct cvmx_mio_uart2_stt_s cn52xxp1;
1958};
1959
1960union cvmx_mio_uart2_tfl {
1961 uint64_t u64;
1962 struct cvmx_mio_uart2_tfl_s {
1963 uint64_t reserved_7_63:57;
1964 uint64_t tfl:7;
1965 } s;
1966 struct cvmx_mio_uart2_tfl_s cn52xx;
1967 struct cvmx_mio_uart2_tfl_s cn52xxp1;
1968};
1969
1970union cvmx_mio_uart2_tfr {
1971 uint64_t u64;
1972 struct cvmx_mio_uart2_tfr_s {
1973 uint64_t reserved_8_63:56;
1974 uint64_t tfr:8;
1975 } s;
1976 struct cvmx_mio_uart2_tfr_s cn52xx;
1977 struct cvmx_mio_uart2_tfr_s cn52xxp1;
1978};
1979
1980union cvmx_mio_uart2_thr {
1981 uint64_t u64;
1982 struct cvmx_mio_uart2_thr_s {
1983 uint64_t reserved_8_63:56;
1984 uint64_t thr:8;
1985 } s;
1986 struct cvmx_mio_uart2_thr_s cn52xx;
1987 struct cvmx_mio_uart2_thr_s cn52xxp1;
1988};
1989
1990union cvmx_mio_uart2_usr {
1991 uint64_t u64;
1992 struct cvmx_mio_uart2_usr_s {
1993 uint64_t reserved_5_63:59;
1994 uint64_t rff:1;
1995 uint64_t rfne:1;
1996 uint64_t tfe:1;
1997 uint64_t tfnf:1;
1998 uint64_t busy:1;
1999 } s;
2000 struct cvmx_mio_uart2_usr_s cn52xx;
2001 struct cvmx_mio_uart2_usr_s cn52xxp1;
2002};
2003
2004#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-packet.h b/arch/mips/include/asm/octeon/cvmx-packet.h
new file mode 100644
index 000000000000..38aefa1bab9d
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-packet.h
@@ -0,0 +1,61 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * Packet buffer defines.
30 */
31
32#ifndef __CVMX_PACKET_H__
33#define __CVMX_PACKET_H__
34
35/**
36 * This structure defines a buffer pointer on Octeon
37 */
38union cvmx_buf_ptr {
39 void *ptr;
40 uint64_t u64;
41 struct {
42 /* if set, invert the "free" pick of the overall
43 * packet. HW always sets this bit to 0 on inbound
44 * packet */
45 uint64_t i:1;
46
47 /* Indicates the amount to back up to get to the
48 * buffer start in cache lines. In most cases this is
49 * less than one complete cache line, so the value is
50 * zero */
51 uint64_t back:4;
52 /* The pool that the buffer came from / goes to */
53 uint64_t pool:3;
54 /* The size of the segment pointed to by addr (in bytes) */
55 uint64_t size:16;
56 /* Pointer to the first byte of the data, NOT buffer */
57 uint64_t addr:40;
58 } s;
59};
60
61#endif /* __CVMX_PACKET_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-pow-defs.h b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
new file mode 100644
index 000000000000..2d82e24be51c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-pow-defs.h
@@ -0,0 +1,698 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_POW_DEFS_H__
29#define __CVMX_POW_DEFS_H__
30
31#define CVMX_POW_BIST_STAT \
32 CVMX_ADD_IO_SEG(0x00016700000003F8ull)
33#define CVMX_POW_DS_PC \
34 CVMX_ADD_IO_SEG(0x0001670000000398ull)
35#define CVMX_POW_ECC_ERR \
36 CVMX_ADD_IO_SEG(0x0001670000000218ull)
37#define CVMX_POW_INT_CTL \
38 CVMX_ADD_IO_SEG(0x0001670000000220ull)
39#define CVMX_POW_IQ_CNTX(offset) \
40 CVMX_ADD_IO_SEG(0x0001670000000340ull + (((offset) & 7) * 8))
41#define CVMX_POW_IQ_COM_CNT \
42 CVMX_ADD_IO_SEG(0x0001670000000388ull)
43#define CVMX_POW_IQ_INT \
44 CVMX_ADD_IO_SEG(0x0001670000000238ull)
45#define CVMX_POW_IQ_INT_EN \
46 CVMX_ADD_IO_SEG(0x0001670000000240ull)
47#define CVMX_POW_IQ_THRX(offset) \
48 CVMX_ADD_IO_SEG(0x00016700000003A0ull + (((offset) & 7) * 8))
49#define CVMX_POW_NOS_CNT \
50 CVMX_ADD_IO_SEG(0x0001670000000228ull)
51#define CVMX_POW_NW_TIM \
52 CVMX_ADD_IO_SEG(0x0001670000000210ull)
53#define CVMX_POW_PF_RST_MSK \
54 CVMX_ADD_IO_SEG(0x0001670000000230ull)
55#define CVMX_POW_PP_GRP_MSKX(offset) \
56 CVMX_ADD_IO_SEG(0x0001670000000000ull + (((offset) & 15) * 8))
57#define CVMX_POW_QOS_RNDX(offset) \
58 CVMX_ADD_IO_SEG(0x00016700000001C0ull + (((offset) & 7) * 8))
59#define CVMX_POW_QOS_THRX(offset) \
60 CVMX_ADD_IO_SEG(0x0001670000000180ull + (((offset) & 7) * 8))
61#define CVMX_POW_TS_PC \
62 CVMX_ADD_IO_SEG(0x0001670000000390ull)
63#define CVMX_POW_WA_COM_PC \
64 CVMX_ADD_IO_SEG(0x0001670000000380ull)
65#define CVMX_POW_WA_PCX(offset) \
66 CVMX_ADD_IO_SEG(0x0001670000000300ull + (((offset) & 7) * 8))
67#define CVMX_POW_WQ_INT \
68 CVMX_ADD_IO_SEG(0x0001670000000200ull)
69#define CVMX_POW_WQ_INT_CNTX(offset) \
70 CVMX_ADD_IO_SEG(0x0001670000000100ull + (((offset) & 15) * 8))
71#define CVMX_POW_WQ_INT_PC \
72 CVMX_ADD_IO_SEG(0x0001670000000208ull)
73#define CVMX_POW_WQ_INT_THRX(offset) \
74 CVMX_ADD_IO_SEG(0x0001670000000080ull + (((offset) & 15) * 8))
75#define CVMX_POW_WS_PCX(offset) \
76 CVMX_ADD_IO_SEG(0x0001670000000280ull + (((offset) & 15) * 8))
77
78union cvmx_pow_bist_stat {
79 uint64_t u64;
80 struct cvmx_pow_bist_stat_s {
81 uint64_t reserved_32_63:32;
82 uint64_t pp:16;
83 uint64_t reserved_0_15:16;
84 } s;
85 struct cvmx_pow_bist_stat_cn30xx {
86 uint64_t reserved_17_63:47;
87 uint64_t pp:1;
88 uint64_t reserved_9_15:7;
89 uint64_t cam:1;
90 uint64_t nbt1:1;
91 uint64_t nbt0:1;
92 uint64_t index:1;
93 uint64_t fidx:1;
94 uint64_t nbr1:1;
95 uint64_t nbr0:1;
96 uint64_t pend:1;
97 uint64_t adr:1;
98 } cn30xx;
99 struct cvmx_pow_bist_stat_cn31xx {
100 uint64_t reserved_18_63:46;
101 uint64_t pp:2;
102 uint64_t reserved_9_15:7;
103 uint64_t cam:1;
104 uint64_t nbt1:1;
105 uint64_t nbt0:1;
106 uint64_t index:1;
107 uint64_t fidx:1;
108 uint64_t nbr1:1;
109 uint64_t nbr0:1;
110 uint64_t pend:1;
111 uint64_t adr:1;
112 } cn31xx;
113 struct cvmx_pow_bist_stat_cn38xx {
114 uint64_t reserved_32_63:32;
115 uint64_t pp:16;
116 uint64_t reserved_10_15:6;
117 uint64_t cam:1;
118 uint64_t nbt:1;
119 uint64_t index:1;
120 uint64_t fidx:1;
121 uint64_t nbr1:1;
122 uint64_t nbr0:1;
123 uint64_t pend1:1;
124 uint64_t pend0:1;
125 uint64_t adr1:1;
126 uint64_t adr0:1;
127 } cn38xx;
128 struct cvmx_pow_bist_stat_cn38xx cn38xxp2;
129 struct cvmx_pow_bist_stat_cn31xx cn50xx;
130 struct cvmx_pow_bist_stat_cn52xx {
131 uint64_t reserved_20_63:44;
132 uint64_t pp:4;
133 uint64_t reserved_9_15:7;
134 uint64_t cam:1;
135 uint64_t nbt1:1;
136 uint64_t nbt0:1;
137 uint64_t index:1;
138 uint64_t fidx:1;
139 uint64_t nbr1:1;
140 uint64_t nbr0:1;
141 uint64_t pend:1;
142 uint64_t adr:1;
143 } cn52xx;
144 struct cvmx_pow_bist_stat_cn52xx cn52xxp1;
145 struct cvmx_pow_bist_stat_cn56xx {
146 uint64_t reserved_28_63:36;
147 uint64_t pp:12;
148 uint64_t reserved_10_15:6;
149 uint64_t cam:1;
150 uint64_t nbt:1;
151 uint64_t index:1;
152 uint64_t fidx:1;
153 uint64_t nbr1:1;
154 uint64_t nbr0:1;
155 uint64_t pend1:1;
156 uint64_t pend0:1;
157 uint64_t adr1:1;
158 uint64_t adr0:1;
159 } cn56xx;
160 struct cvmx_pow_bist_stat_cn56xx cn56xxp1;
161 struct cvmx_pow_bist_stat_cn38xx cn58xx;
162 struct cvmx_pow_bist_stat_cn38xx cn58xxp1;
163};
164
165union cvmx_pow_ds_pc {
166 uint64_t u64;
167 struct cvmx_pow_ds_pc_s {
168 uint64_t reserved_32_63:32;
169 uint64_t ds_pc:32;
170 } s;
171 struct cvmx_pow_ds_pc_s cn30xx;
172 struct cvmx_pow_ds_pc_s cn31xx;
173 struct cvmx_pow_ds_pc_s cn38xx;
174 struct cvmx_pow_ds_pc_s cn38xxp2;
175 struct cvmx_pow_ds_pc_s cn50xx;
176 struct cvmx_pow_ds_pc_s cn52xx;
177 struct cvmx_pow_ds_pc_s cn52xxp1;
178 struct cvmx_pow_ds_pc_s cn56xx;
179 struct cvmx_pow_ds_pc_s cn56xxp1;
180 struct cvmx_pow_ds_pc_s cn58xx;
181 struct cvmx_pow_ds_pc_s cn58xxp1;
182};
183
184union cvmx_pow_ecc_err {
185 uint64_t u64;
186 struct cvmx_pow_ecc_err_s {
187 uint64_t reserved_45_63:19;
188 uint64_t iop_ie:13;
189 uint64_t reserved_29_31:3;
190 uint64_t iop:13;
191 uint64_t reserved_14_15:2;
192 uint64_t rpe_ie:1;
193 uint64_t rpe:1;
194 uint64_t reserved_9_11:3;
195 uint64_t syn:5;
196 uint64_t dbe_ie:1;
197 uint64_t sbe_ie:1;
198 uint64_t dbe:1;
199 uint64_t sbe:1;
200 } s;
201 struct cvmx_pow_ecc_err_s cn30xx;
202 struct cvmx_pow_ecc_err_cn31xx {
203 uint64_t reserved_14_63:50;
204 uint64_t rpe_ie:1;
205 uint64_t rpe:1;
206 uint64_t reserved_9_11:3;
207 uint64_t syn:5;
208 uint64_t dbe_ie:1;
209 uint64_t sbe_ie:1;
210 uint64_t dbe:1;
211 uint64_t sbe:1;
212 } cn31xx;
213 struct cvmx_pow_ecc_err_s cn38xx;
214 struct cvmx_pow_ecc_err_cn31xx cn38xxp2;
215 struct cvmx_pow_ecc_err_s cn50xx;
216 struct cvmx_pow_ecc_err_s cn52xx;
217 struct cvmx_pow_ecc_err_s cn52xxp1;
218 struct cvmx_pow_ecc_err_s cn56xx;
219 struct cvmx_pow_ecc_err_s cn56xxp1;
220 struct cvmx_pow_ecc_err_s cn58xx;
221 struct cvmx_pow_ecc_err_s cn58xxp1;
222};
223
224union cvmx_pow_int_ctl {
225 uint64_t u64;
226 struct cvmx_pow_int_ctl_s {
227 uint64_t reserved_6_63:58;
228 uint64_t pfr_dis:1;
229 uint64_t nbr_thr:5;
230 } s;
231 struct cvmx_pow_int_ctl_s cn30xx;
232 struct cvmx_pow_int_ctl_s cn31xx;
233 struct cvmx_pow_int_ctl_s cn38xx;
234 struct cvmx_pow_int_ctl_s cn38xxp2;
235 struct cvmx_pow_int_ctl_s cn50xx;
236 struct cvmx_pow_int_ctl_s cn52xx;
237 struct cvmx_pow_int_ctl_s cn52xxp1;
238 struct cvmx_pow_int_ctl_s cn56xx;
239 struct cvmx_pow_int_ctl_s cn56xxp1;
240 struct cvmx_pow_int_ctl_s cn58xx;
241 struct cvmx_pow_int_ctl_s cn58xxp1;
242};
243
244union cvmx_pow_iq_cntx {
245 uint64_t u64;
246 struct cvmx_pow_iq_cntx_s {
247 uint64_t reserved_32_63:32;
248 uint64_t iq_cnt:32;
249 } s;
250 struct cvmx_pow_iq_cntx_s cn30xx;
251 struct cvmx_pow_iq_cntx_s cn31xx;
252 struct cvmx_pow_iq_cntx_s cn38xx;
253 struct cvmx_pow_iq_cntx_s cn38xxp2;
254 struct cvmx_pow_iq_cntx_s cn50xx;
255 struct cvmx_pow_iq_cntx_s cn52xx;
256 struct cvmx_pow_iq_cntx_s cn52xxp1;
257 struct cvmx_pow_iq_cntx_s cn56xx;
258 struct cvmx_pow_iq_cntx_s cn56xxp1;
259 struct cvmx_pow_iq_cntx_s cn58xx;
260 struct cvmx_pow_iq_cntx_s cn58xxp1;
261};
262
263union cvmx_pow_iq_com_cnt {
264 uint64_t u64;
265 struct cvmx_pow_iq_com_cnt_s {
266 uint64_t reserved_32_63:32;
267 uint64_t iq_cnt:32;
268 } s;
269 struct cvmx_pow_iq_com_cnt_s cn30xx;
270 struct cvmx_pow_iq_com_cnt_s cn31xx;
271 struct cvmx_pow_iq_com_cnt_s cn38xx;
272 struct cvmx_pow_iq_com_cnt_s cn38xxp2;
273 struct cvmx_pow_iq_com_cnt_s cn50xx;
274 struct cvmx_pow_iq_com_cnt_s cn52xx;
275 struct cvmx_pow_iq_com_cnt_s cn52xxp1;
276 struct cvmx_pow_iq_com_cnt_s cn56xx;
277 struct cvmx_pow_iq_com_cnt_s cn56xxp1;
278 struct cvmx_pow_iq_com_cnt_s cn58xx;
279 struct cvmx_pow_iq_com_cnt_s cn58xxp1;
280};
281
282union cvmx_pow_iq_int {
283 uint64_t u64;
284 struct cvmx_pow_iq_int_s {
285 uint64_t reserved_8_63:56;
286 uint64_t iq_int:8;
287 } s;
288 struct cvmx_pow_iq_int_s cn52xx;
289 struct cvmx_pow_iq_int_s cn52xxp1;
290 struct cvmx_pow_iq_int_s cn56xx;
291 struct cvmx_pow_iq_int_s cn56xxp1;
292};
293
294union cvmx_pow_iq_int_en {
295 uint64_t u64;
296 struct cvmx_pow_iq_int_en_s {
297 uint64_t reserved_8_63:56;
298 uint64_t int_en:8;
299 } s;
300 struct cvmx_pow_iq_int_en_s cn52xx;
301 struct cvmx_pow_iq_int_en_s cn52xxp1;
302 struct cvmx_pow_iq_int_en_s cn56xx;
303 struct cvmx_pow_iq_int_en_s cn56xxp1;
304};
305
306union cvmx_pow_iq_thrx {
307 uint64_t u64;
308 struct cvmx_pow_iq_thrx_s {
309 uint64_t reserved_32_63:32;
310 uint64_t iq_thr:32;
311 } s;
312 struct cvmx_pow_iq_thrx_s cn52xx;
313 struct cvmx_pow_iq_thrx_s cn52xxp1;
314 struct cvmx_pow_iq_thrx_s cn56xx;
315 struct cvmx_pow_iq_thrx_s cn56xxp1;
316};
317
318union cvmx_pow_nos_cnt {
319 uint64_t u64;
320 struct cvmx_pow_nos_cnt_s {
321 uint64_t reserved_12_63:52;
322 uint64_t nos_cnt:12;
323 } s;
324 struct cvmx_pow_nos_cnt_cn30xx {
325 uint64_t reserved_7_63:57;
326 uint64_t nos_cnt:7;
327 } cn30xx;
328 struct cvmx_pow_nos_cnt_cn31xx {
329 uint64_t reserved_9_63:55;
330 uint64_t nos_cnt:9;
331 } cn31xx;
332 struct cvmx_pow_nos_cnt_s cn38xx;
333 struct cvmx_pow_nos_cnt_s cn38xxp2;
334 struct cvmx_pow_nos_cnt_cn31xx cn50xx;
335 struct cvmx_pow_nos_cnt_cn52xx {
336 uint64_t reserved_10_63:54;
337 uint64_t nos_cnt:10;
338 } cn52xx;
339 struct cvmx_pow_nos_cnt_cn52xx cn52xxp1;
340 struct cvmx_pow_nos_cnt_s cn56xx;
341 struct cvmx_pow_nos_cnt_s cn56xxp1;
342 struct cvmx_pow_nos_cnt_s cn58xx;
343 struct cvmx_pow_nos_cnt_s cn58xxp1;
344};
345
346union cvmx_pow_nw_tim {
347 uint64_t u64;
348 struct cvmx_pow_nw_tim_s {
349 uint64_t reserved_10_63:54;
350 uint64_t nw_tim:10;
351 } s;
352 struct cvmx_pow_nw_tim_s cn30xx;
353 struct cvmx_pow_nw_tim_s cn31xx;
354 struct cvmx_pow_nw_tim_s cn38xx;
355 struct cvmx_pow_nw_tim_s cn38xxp2;
356 struct cvmx_pow_nw_tim_s cn50xx;
357 struct cvmx_pow_nw_tim_s cn52xx;
358 struct cvmx_pow_nw_tim_s cn52xxp1;
359 struct cvmx_pow_nw_tim_s cn56xx;
360 struct cvmx_pow_nw_tim_s cn56xxp1;
361 struct cvmx_pow_nw_tim_s cn58xx;
362 struct cvmx_pow_nw_tim_s cn58xxp1;
363};
364
365union cvmx_pow_pf_rst_msk {
366 uint64_t u64;
367 struct cvmx_pow_pf_rst_msk_s {
368 uint64_t reserved_8_63:56;
369 uint64_t rst_msk:8;
370 } s;
371 struct cvmx_pow_pf_rst_msk_s cn50xx;
372 struct cvmx_pow_pf_rst_msk_s cn52xx;
373 struct cvmx_pow_pf_rst_msk_s cn52xxp1;
374 struct cvmx_pow_pf_rst_msk_s cn56xx;
375 struct cvmx_pow_pf_rst_msk_s cn56xxp1;
376 struct cvmx_pow_pf_rst_msk_s cn58xx;
377 struct cvmx_pow_pf_rst_msk_s cn58xxp1;
378};
379
380union cvmx_pow_pp_grp_mskx {
381 uint64_t u64;
382 struct cvmx_pow_pp_grp_mskx_s {
383 uint64_t reserved_48_63:16;
384 uint64_t qos7_pri:4;
385 uint64_t qos6_pri:4;
386 uint64_t qos5_pri:4;
387 uint64_t qos4_pri:4;
388 uint64_t qos3_pri:4;
389 uint64_t qos2_pri:4;
390 uint64_t qos1_pri:4;
391 uint64_t qos0_pri:4;
392 uint64_t grp_msk:16;
393 } s;
394 struct cvmx_pow_pp_grp_mskx_cn30xx {
395 uint64_t reserved_16_63:48;
396 uint64_t grp_msk:16;
397 } cn30xx;
398 struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx;
399 struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx;
400 struct cvmx_pow_pp_grp_mskx_cn30xx cn38xxp2;
401 struct cvmx_pow_pp_grp_mskx_s cn50xx;
402 struct cvmx_pow_pp_grp_mskx_s cn52xx;
403 struct cvmx_pow_pp_grp_mskx_s cn52xxp1;
404 struct cvmx_pow_pp_grp_mskx_s cn56xx;
405 struct cvmx_pow_pp_grp_mskx_s cn56xxp1;
406 struct cvmx_pow_pp_grp_mskx_s cn58xx;
407 struct cvmx_pow_pp_grp_mskx_s cn58xxp1;
408};
409
410union cvmx_pow_qos_rndx {
411 uint64_t u64;
412 struct cvmx_pow_qos_rndx_s {
413 uint64_t reserved_32_63:32;
414 uint64_t rnd_p3:8;
415 uint64_t rnd_p2:8;
416 uint64_t rnd_p1:8;
417 uint64_t rnd:8;
418 } s;
419 struct cvmx_pow_qos_rndx_s cn30xx;
420 struct cvmx_pow_qos_rndx_s cn31xx;
421 struct cvmx_pow_qos_rndx_s cn38xx;
422 struct cvmx_pow_qos_rndx_s cn38xxp2;
423 struct cvmx_pow_qos_rndx_s cn50xx;
424 struct cvmx_pow_qos_rndx_s cn52xx;
425 struct cvmx_pow_qos_rndx_s cn52xxp1;
426 struct cvmx_pow_qos_rndx_s cn56xx;
427 struct cvmx_pow_qos_rndx_s cn56xxp1;
428 struct cvmx_pow_qos_rndx_s cn58xx;
429 struct cvmx_pow_qos_rndx_s cn58xxp1;
430};
431
432union cvmx_pow_qos_thrx {
433 uint64_t u64;
434 struct cvmx_pow_qos_thrx_s {
435 uint64_t reserved_60_63:4;
436 uint64_t des_cnt:12;
437 uint64_t buf_cnt:12;
438 uint64_t free_cnt:12;
439 uint64_t reserved_23_23:1;
440 uint64_t max_thr:11;
441 uint64_t reserved_11_11:1;
442 uint64_t min_thr:11;
443 } s;
444 struct cvmx_pow_qos_thrx_cn30xx {
445 uint64_t reserved_55_63:9;
446 uint64_t des_cnt:7;
447 uint64_t reserved_43_47:5;
448 uint64_t buf_cnt:7;
449 uint64_t reserved_31_35:5;
450 uint64_t free_cnt:7;
451 uint64_t reserved_18_23:6;
452 uint64_t max_thr:6;
453 uint64_t reserved_6_11:6;
454 uint64_t min_thr:6;
455 } cn30xx;
456 struct cvmx_pow_qos_thrx_cn31xx {
457 uint64_t reserved_57_63:7;
458 uint64_t des_cnt:9;
459 uint64_t reserved_45_47:3;
460 uint64_t buf_cnt:9;
461 uint64_t reserved_33_35:3;
462 uint64_t free_cnt:9;
463 uint64_t reserved_20_23:4;
464 uint64_t max_thr:8;
465 uint64_t reserved_8_11:4;
466 uint64_t min_thr:8;
467 } cn31xx;
468 struct cvmx_pow_qos_thrx_s cn38xx;
469 struct cvmx_pow_qos_thrx_s cn38xxp2;
470 struct cvmx_pow_qos_thrx_cn31xx cn50xx;
471 struct cvmx_pow_qos_thrx_cn52xx {
472 uint64_t reserved_58_63:6;
473 uint64_t des_cnt:10;
474 uint64_t reserved_46_47:2;
475 uint64_t buf_cnt:10;
476 uint64_t reserved_34_35:2;
477 uint64_t free_cnt:10;
478 uint64_t reserved_21_23:3;
479 uint64_t max_thr:9;
480 uint64_t reserved_9_11:3;
481 uint64_t min_thr:9;
482 } cn52xx;
483 struct cvmx_pow_qos_thrx_cn52xx cn52xxp1;
484 struct cvmx_pow_qos_thrx_s cn56xx;
485 struct cvmx_pow_qos_thrx_s cn56xxp1;
486 struct cvmx_pow_qos_thrx_s cn58xx;
487 struct cvmx_pow_qos_thrx_s cn58xxp1;
488};
489
490union cvmx_pow_ts_pc {
491 uint64_t u64;
492 struct cvmx_pow_ts_pc_s {
493 uint64_t reserved_32_63:32;
494 uint64_t ts_pc:32;
495 } s;
496 struct cvmx_pow_ts_pc_s cn30xx;
497 struct cvmx_pow_ts_pc_s cn31xx;
498 struct cvmx_pow_ts_pc_s cn38xx;
499 struct cvmx_pow_ts_pc_s cn38xxp2;
500 struct cvmx_pow_ts_pc_s cn50xx;
501 struct cvmx_pow_ts_pc_s cn52xx;
502 struct cvmx_pow_ts_pc_s cn52xxp1;
503 struct cvmx_pow_ts_pc_s cn56xx;
504 struct cvmx_pow_ts_pc_s cn56xxp1;
505 struct cvmx_pow_ts_pc_s cn58xx;
506 struct cvmx_pow_ts_pc_s cn58xxp1;
507};
508
509union cvmx_pow_wa_com_pc {
510 uint64_t u64;
511 struct cvmx_pow_wa_com_pc_s {
512 uint64_t reserved_32_63:32;
513 uint64_t wa_pc:32;
514 } s;
515 struct cvmx_pow_wa_com_pc_s cn30xx;
516 struct cvmx_pow_wa_com_pc_s cn31xx;
517 struct cvmx_pow_wa_com_pc_s cn38xx;
518 struct cvmx_pow_wa_com_pc_s cn38xxp2;
519 struct cvmx_pow_wa_com_pc_s cn50xx;
520 struct cvmx_pow_wa_com_pc_s cn52xx;
521 struct cvmx_pow_wa_com_pc_s cn52xxp1;
522 struct cvmx_pow_wa_com_pc_s cn56xx;
523 struct cvmx_pow_wa_com_pc_s cn56xxp1;
524 struct cvmx_pow_wa_com_pc_s cn58xx;
525 struct cvmx_pow_wa_com_pc_s cn58xxp1;
526};
527
528union cvmx_pow_wa_pcx {
529 uint64_t u64;
530 struct cvmx_pow_wa_pcx_s {
531 uint64_t reserved_32_63:32;
532 uint64_t wa_pc:32;
533 } s;
534 struct cvmx_pow_wa_pcx_s cn30xx;
535 struct cvmx_pow_wa_pcx_s cn31xx;
536 struct cvmx_pow_wa_pcx_s cn38xx;
537 struct cvmx_pow_wa_pcx_s cn38xxp2;
538 struct cvmx_pow_wa_pcx_s cn50xx;
539 struct cvmx_pow_wa_pcx_s cn52xx;
540 struct cvmx_pow_wa_pcx_s cn52xxp1;
541 struct cvmx_pow_wa_pcx_s cn56xx;
542 struct cvmx_pow_wa_pcx_s cn56xxp1;
543 struct cvmx_pow_wa_pcx_s cn58xx;
544 struct cvmx_pow_wa_pcx_s cn58xxp1;
545};
546
547union cvmx_pow_wq_int {
548 uint64_t u64;
549 struct cvmx_pow_wq_int_s {
550 uint64_t reserved_32_63:32;
551 uint64_t iq_dis:16;
552 uint64_t wq_int:16;
553 } s;
554 struct cvmx_pow_wq_int_s cn30xx;
555 struct cvmx_pow_wq_int_s cn31xx;
556 struct cvmx_pow_wq_int_s cn38xx;
557 struct cvmx_pow_wq_int_s cn38xxp2;
558 struct cvmx_pow_wq_int_s cn50xx;
559 struct cvmx_pow_wq_int_s cn52xx;
560 struct cvmx_pow_wq_int_s cn52xxp1;
561 struct cvmx_pow_wq_int_s cn56xx;
562 struct cvmx_pow_wq_int_s cn56xxp1;
563 struct cvmx_pow_wq_int_s cn58xx;
564 struct cvmx_pow_wq_int_s cn58xxp1;
565};
566
567union cvmx_pow_wq_int_cntx {
568 uint64_t u64;
569 struct cvmx_pow_wq_int_cntx_s {
570 uint64_t reserved_28_63:36;
571 uint64_t tc_cnt:4;
572 uint64_t ds_cnt:12;
573 uint64_t iq_cnt:12;
574 } s;
575 struct cvmx_pow_wq_int_cntx_cn30xx {
576 uint64_t reserved_28_63:36;
577 uint64_t tc_cnt:4;
578 uint64_t reserved_19_23:5;
579 uint64_t ds_cnt:7;
580 uint64_t reserved_7_11:5;
581 uint64_t iq_cnt:7;
582 } cn30xx;
583 struct cvmx_pow_wq_int_cntx_cn31xx {
584 uint64_t reserved_28_63:36;
585 uint64_t tc_cnt:4;
586 uint64_t reserved_21_23:3;
587 uint64_t ds_cnt:9;
588 uint64_t reserved_9_11:3;
589 uint64_t iq_cnt:9;
590 } cn31xx;
591 struct cvmx_pow_wq_int_cntx_s cn38xx;
592 struct cvmx_pow_wq_int_cntx_s cn38xxp2;
593 struct cvmx_pow_wq_int_cntx_cn31xx cn50xx;
594 struct cvmx_pow_wq_int_cntx_cn52xx {
595 uint64_t reserved_28_63:36;
596 uint64_t tc_cnt:4;
597 uint64_t reserved_22_23:2;
598 uint64_t ds_cnt:10;
599 uint64_t reserved_10_11:2;
600 uint64_t iq_cnt:10;
601 } cn52xx;
602 struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1;
603 struct cvmx_pow_wq_int_cntx_s cn56xx;
604 struct cvmx_pow_wq_int_cntx_s cn56xxp1;
605 struct cvmx_pow_wq_int_cntx_s cn58xx;
606 struct cvmx_pow_wq_int_cntx_s cn58xxp1;
607};
608
609union cvmx_pow_wq_int_pc {
610 uint64_t u64;
611 struct cvmx_pow_wq_int_pc_s {
612 uint64_t reserved_60_63:4;
613 uint64_t pc:28;
614 uint64_t reserved_28_31:4;
615 uint64_t pc_thr:20;
616 uint64_t reserved_0_7:8;
617 } s;
618 struct cvmx_pow_wq_int_pc_s cn30xx;
619 struct cvmx_pow_wq_int_pc_s cn31xx;
620 struct cvmx_pow_wq_int_pc_s cn38xx;
621 struct cvmx_pow_wq_int_pc_s cn38xxp2;
622 struct cvmx_pow_wq_int_pc_s cn50xx;
623 struct cvmx_pow_wq_int_pc_s cn52xx;
624 struct cvmx_pow_wq_int_pc_s cn52xxp1;
625 struct cvmx_pow_wq_int_pc_s cn56xx;
626 struct cvmx_pow_wq_int_pc_s cn56xxp1;
627 struct cvmx_pow_wq_int_pc_s cn58xx;
628 struct cvmx_pow_wq_int_pc_s cn58xxp1;
629};
630
631union cvmx_pow_wq_int_thrx {
632 uint64_t u64;
633 struct cvmx_pow_wq_int_thrx_s {
634 uint64_t reserved_29_63:35;
635 uint64_t tc_en:1;
636 uint64_t tc_thr:4;
637 uint64_t reserved_23_23:1;
638 uint64_t ds_thr:11;
639 uint64_t reserved_11_11:1;
640 uint64_t iq_thr:11;
641 } s;
642 struct cvmx_pow_wq_int_thrx_cn30xx {
643 uint64_t reserved_29_63:35;
644 uint64_t tc_en:1;
645 uint64_t tc_thr:4;
646 uint64_t reserved_18_23:6;
647 uint64_t ds_thr:6;
648 uint64_t reserved_6_11:6;
649 uint64_t iq_thr:6;
650 } cn30xx;
651 struct cvmx_pow_wq_int_thrx_cn31xx {
652 uint64_t reserved_29_63:35;
653 uint64_t tc_en:1;
654 uint64_t tc_thr:4;
655 uint64_t reserved_20_23:4;
656 uint64_t ds_thr:8;
657 uint64_t reserved_8_11:4;
658 uint64_t iq_thr:8;
659 } cn31xx;
660 struct cvmx_pow_wq_int_thrx_s cn38xx;
661 struct cvmx_pow_wq_int_thrx_s cn38xxp2;
662 struct cvmx_pow_wq_int_thrx_cn31xx cn50xx;
663 struct cvmx_pow_wq_int_thrx_cn52xx {
664 uint64_t reserved_29_63:35;
665 uint64_t tc_en:1;
666 uint64_t tc_thr:4;
667 uint64_t reserved_21_23:3;
668 uint64_t ds_thr:9;
669 uint64_t reserved_9_11:3;
670 uint64_t iq_thr:9;
671 } cn52xx;
672 struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1;
673 struct cvmx_pow_wq_int_thrx_s cn56xx;
674 struct cvmx_pow_wq_int_thrx_s cn56xxp1;
675 struct cvmx_pow_wq_int_thrx_s cn58xx;
676 struct cvmx_pow_wq_int_thrx_s cn58xxp1;
677};
678
679union cvmx_pow_ws_pcx {
680 uint64_t u64;
681 struct cvmx_pow_ws_pcx_s {
682 uint64_t reserved_32_63:32;
683 uint64_t ws_pc:32;
684 } s;
685 struct cvmx_pow_ws_pcx_s cn30xx;
686 struct cvmx_pow_ws_pcx_s cn31xx;
687 struct cvmx_pow_ws_pcx_s cn38xx;
688 struct cvmx_pow_ws_pcx_s cn38xxp2;
689 struct cvmx_pow_ws_pcx_s cn50xx;
690 struct cvmx_pow_ws_pcx_s cn52xx;
691 struct cvmx_pow_ws_pcx_s cn52xxp1;
692 struct cvmx_pow_ws_pcx_s cn56xx;
693 struct cvmx_pow_ws_pcx_s cn56xxp1;
694 struct cvmx_pow_ws_pcx_s cn58xx;
695 struct cvmx_pow_ws_pcx_s cn58xxp1;
696};
697
698#endif
diff --git a/arch/mips/include/asm/octeon/cvmx-spinlock.h b/arch/mips/include/asm/octeon/cvmx-spinlock.h
new file mode 100644
index 000000000000..2fbf0871df11
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-spinlock.h
@@ -0,0 +1,232 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 * Implementation of spinlocks for Octeon CVMX. Although similar in
30 * function to Linux kernel spinlocks, they are not compatible.
31 * Octeon CVMX spinlocks are only used to synchronize with the boot
32 * monitor and other non-Linux programs running in the system.
33 */
34
35#ifndef __CVMX_SPINLOCK_H__
36#define __CVMX_SPINLOCK_H__
37
38#include "cvmx-asm.h"
39
40/* Spinlocks for Octeon */
41
42/* define these to enable recursive spinlock debugging */
43/*#define CVMX_SPINLOCK_DEBUG */
44
45/**
46 * Spinlocks for Octeon CVMX
47 */
48typedef struct {
49 volatile uint32_t value;
50} cvmx_spinlock_t;
51
52/* note - macros not expanded in inline ASM, so values hardcoded */
53#define CVMX_SPINLOCK_UNLOCKED_VAL 0
54#define CVMX_SPINLOCK_LOCKED_VAL 1
55
56#define CVMX_SPINLOCK_UNLOCKED_INITIALIZER {CVMX_SPINLOCK_UNLOCKED_VAL}
57
58/**
59 * Initialize a spinlock
60 *
61 * @lock: Lock to initialize
62 */
63static inline void cvmx_spinlock_init(cvmx_spinlock_t *lock)
64{
65 lock->value = CVMX_SPINLOCK_UNLOCKED_VAL;
66}
67
68/**
69 * Return non-zero if the spinlock is currently locked
70 *
71 * @lock: Lock to check
72 * Returns Non-zero if locked
73 */
74static inline int cvmx_spinlock_locked(cvmx_spinlock_t *lock)
75{
76 return lock->value != CVMX_SPINLOCK_UNLOCKED_VAL;
77}
78
79/**
80 * Releases lock
81 *
82 * @lock: pointer to lock structure
83 */
84static inline void cvmx_spinlock_unlock(cvmx_spinlock_t *lock)
85{
86 CVMX_SYNCWS;
87 lock->value = 0;
88 CVMX_SYNCWS;
89}
90
91/**
92 * Attempts to take the lock, but does not spin if lock is not available.
93 * May take some time to acquire the lock even if it is available
94 * due to the ll/sc not succeeding.
95 *
96 * @lock: pointer to lock structure
97 *
98 * Returns 0: lock successfully taken
99 * 1: lock not taken, held by someone else
100 * These return values match the Linux semantics.
101 */
102
103static inline unsigned int cvmx_spinlock_trylock(cvmx_spinlock_t *lock)
104{
105 unsigned int tmp;
106
107 __asm__ __volatile__(".set noreorder \n"
108 "1: ll %[tmp], %[val] \n"
109 /* if lock held, fail immediately */
110 " bnez %[tmp], 2f \n"
111 " li %[tmp], 1 \n"
112 " sc %[tmp], %[val] \n"
113 " beqz %[tmp], 1b \n"
114 " li %[tmp], 0 \n"
115 "2: \n"
116 ".set reorder \n" :
117 [val] "+m"(lock->value), [tmp] "=&r"(tmp)
118 : : "memory");
119
120 return tmp != 0; /* normalize to 0 or 1 */
121}
122
123/**
124 * Gets lock, spins until lock is taken
125 *
126 * @lock: pointer to lock structure
127 */
128static inline void cvmx_spinlock_lock(cvmx_spinlock_t *lock)
129{
130 unsigned int tmp;
131
132 __asm__ __volatile__(".set noreorder \n"
133 "1: ll %[tmp], %[val] \n"
134 " bnez %[tmp], 1b \n"
135 " li %[tmp], 1 \n"
136 " sc %[tmp], %[val] \n"
137 " beqz %[tmp], 1b \n"
138 " nop \n"
139 ".set reorder \n" :
140 [val] "+m"(lock->value), [tmp] "=&r"(tmp)
141 : : "memory");
142
143}
144
145/** ********************************************************************
146 * Bit spinlocks
147 * These spinlocks use a single bit (bit 31) of a 32 bit word for locking.
148 * The rest of the bits in the word are left undisturbed. This enables more
149 * compact data structures as only 1 bit is consumed for the lock.
150 *
151 */
152
153/**
154 * Gets lock, spins until lock is taken
155 * Preserves the low 31 bits of the 32 bit
156 * word used for the lock.
157 *
158 *
159 * @word: word to lock bit 31 of
160 */
161static inline void cvmx_spinlock_bit_lock(uint32_t *word)
162{
163 unsigned int tmp;
164 unsigned int sav;
165
166 __asm__ __volatile__(".set noreorder \n"
167 ".set noat \n"
168 "1: ll %[tmp], %[val] \n"
169 " bbit1 %[tmp], 31, 1b \n"
170 " li $at, 1 \n"
171 " ins %[tmp], $at, 31, 1 \n"
172 " sc %[tmp], %[val] \n"
173 " beqz %[tmp], 1b \n"
174 " nop \n"
175 ".set at \n"
176 ".set reorder \n" :
177 [val] "+m"(*word), [tmp] "=&r"(tmp), [sav] "=&r"(sav)
178 : : "memory");
179
180}
181
182/**
183 * Attempts to get lock, returns immediately with success/failure
184 * Preserves the low 31 bits of the 32 bit
185 * word used for the lock.
186 *
187 *
188 * @word: word to lock bit 31 of
189 * Returns 0: lock successfully taken
190 * 1: lock not taken, held by someone else
191 * These return values match the Linux semantics.
192 */
193static inline unsigned int cvmx_spinlock_bit_trylock(uint32_t *word)
194{
195 unsigned int tmp;
196
197 __asm__ __volatile__(".set noreorder\n\t"
198 ".set noat\n"
199 "1: ll %[tmp], %[val] \n"
200 /* if lock held, fail immediately */
201 " bbit1 %[tmp], 31, 2f \n"
202 " li $at, 1 \n"
203 " ins %[tmp], $at, 31, 1 \n"
204 " sc %[tmp], %[val] \n"
205 " beqz %[tmp], 1b \n"
206 " li %[tmp], 0 \n"
207 "2: \n"
208 ".set at \n"
209 ".set reorder \n" :
210 [val] "+m"(*word), [tmp] "=&r"(tmp)
211 : : "memory");
212
213 return tmp != 0; /* normalize to 0 or 1 */
214}
215
216/**
217 * Releases bit lock
218 *
219 * Unconditionally clears bit 31 of the lock word. Note that this is
220 * done non-atomically, as this implementation assumes that the rest
221 * of the bits in the word are protected by the lock.
222 *
223 * @word: word to unlock bit 31 in
224 */
225static inline void cvmx_spinlock_bit_unlock(uint32_t *word)
226{
227 CVMX_SYNCWS;
228 *word &= ~(1UL << 31);
229 CVMX_SYNCWS;
230}
231
232#endif /* __CVMX_SPINLOCK_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx-sysinfo.h b/arch/mips/include/asm/octeon/cvmx-sysinfo.h
new file mode 100644
index 000000000000..61dd5741afe4
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx-sysinfo.h
@@ -0,0 +1,152 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * This module provides system/board information obtained by the bootloader.
30 */
31
32#ifndef __CVMX_SYSINFO_H__
33#define __CVMX_SYSINFO_H__
34
35#define OCTEON_SERIAL_LEN 20
36/**
37 * Structure describing application specific information.
38 * __cvmx_app_init() populates this from the cvmx boot descriptor.
39 * This structure is private to simple executive applications, so
40 * no versioning is required.
41 *
42 * This structure must be provided with some fields set in order to
43 * use simple executive functions in other applications (Linux kernel,
44 * u-boot, etc.) The cvmx_sysinfo_minimal_initialize() function is
45 * provided to set the required values in these cases.
46 */
47struct cvmx_sysinfo {
48 /* System wide variables */
49 /* installed DRAM in system, in bytes */
50 uint64_t system_dram_size;
51
52 /* ptr to memory descriptor block */
53 void *phy_mem_desc_ptr;
54
55
56 /* Application image specific variables */
57 /* stack top address (virtual) */
58 uint64_t stack_top;
59 /* heap base address (virtual) */
60 uint64_t heap_base;
61 /* stack size in bytes */
62 uint32_t stack_size;
63 /* heap size in bytes */
64 uint32_t heap_size;
65 /* coremask defining cores running application */
66 uint32_t core_mask;
67 /* Deprecated, use cvmx_coremask_first_core() to select init core */
68 uint32_t init_core;
69
70 /* exception base address, as set by bootloader */
71 uint64_t exception_base_addr;
72
73 /* cpu clock speed in hz */
74 uint32_t cpu_clock_hz;
75
76 /* dram data rate in hz (data rate = 2 * clock rate */
77 uint32_t dram_data_rate_hz;
78
79
80 uint16_t board_type;
81 uint8_t board_rev_major;
82 uint8_t board_rev_minor;
83 uint8_t mac_addr_base[6];
84 uint8_t mac_addr_count;
85 char board_serial_number[OCTEON_SERIAL_LEN];
86 /*
87 * Several boards support compact flash on the Octeon boot
88 * bus. The CF memory spaces may be mapped to different
89 * addresses on different boards. These values will be 0 if
90 * CF is not present. Note that these addresses are physical
91 * addresses, and it is up to the application to use the
92 * proper addressing mode (XKPHYS, KSEG0, etc.)
93 */
94 uint64_t compact_flash_common_base_addr;
95 uint64_t compact_flash_attribute_base_addr;
96 /*
97 * Base address of the LED display (as on EBT3000 board) This
98 * will be 0 if LED display not present. Note that this
99 * address is a physical address, and it is up to the
100 * application to use the proper addressing mode (XKPHYS,
101 * KSEG0, etc.)
102 */
103 uint64_t led_display_base_addr;
104 /* DFA reference clock in hz (if applicable)*/
105 uint32_t dfa_ref_clock_hz;
106 /* configuration flags from bootloader */
107 uint32_t bootloader_config_flags;
108
109 /* Uart number used for console */
110 uint8_t console_uart_num;
111};
112
113/**
114 * This function returns the system/board information as obtained
115 * by the bootloader.
116 *
117 *
118 * Returns Pointer to the boot information structure
119 *
120 */
121
122extern struct cvmx_sysinfo *cvmx_sysinfo_get(void);
123
124/**
125 * This function is used in non-simple executive environments (such as
126 * Linux kernel, u-boot, etc.) to configure the minimal fields that
127 * are required to use simple executive files directly.
128 *
129 * Locking (if required) must be handled outside of this
130 * function
131 *
132 * @phy_mem_desc_ptr: Pointer to global physical memory descriptor
133 * (bootmem descriptor) @board_type: Octeon board
134 * type enumeration
135 *
136 * @board_rev_major:
137 * Board major revision
138 * @board_rev_minor:
139 * Board minor revision
140 * @cpu_clock_hz:
141 * CPU clock freqency in hertz
142 *
143 * Returns 0: Failure
144 * 1: success
145 */
146extern int cvmx_sysinfo_minimal_initialize(void *phy_mem_desc_ptr,
147 uint16_t board_type,
148 uint8_t board_rev_major,
149 uint8_t board_rev_minor,
150 uint32_t cpu_clock_hz);
151
152#endif /* __CVMX_SYSINFO_H__ */
diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
new file mode 100644
index 000000000000..03fddfa3e928
--- /dev/null
+++ b/arch/mips/include/asm/octeon/cvmx.h
@@ -0,0 +1,505 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_H__
29#define __CVMX_H__
30
31#include <linux/kernel.h>
32#include <linux/string.h>
33
34#include "cvmx-asm.h"
35#include "cvmx-packet.h"
36#include "cvmx-sysinfo.h"
37
38#include "cvmx-ciu-defs.h"
39#include "cvmx-gpio-defs.h"
40#include "cvmx-iob-defs.h"
41#include "cvmx-ipd-defs.h"
42#include "cvmx-l2c-defs.h"
43#include "cvmx-l2d-defs.h"
44#include "cvmx-l2t-defs.h"
45#include "cvmx-led-defs.h"
46#include "cvmx-mio-defs.h"
47#include "cvmx-pow-defs.h"
48
49#include "cvmx-bootinfo.h"
50#include "cvmx-bootmem.h"
51#include "cvmx-l2c.h"
52
53#ifndef CVMX_ENABLE_DEBUG_PRINTS
54#define CVMX_ENABLE_DEBUG_PRINTS 1
55#endif
56
57#if CVMX_ENABLE_DEBUG_PRINTS
58#define cvmx_dprintf printk
59#else
60#define cvmx_dprintf(...) {}
61#endif
62
63#define CVMX_MAX_CORES (16)
64#define CVMX_CACHE_LINE_SIZE (128) /* In bytes */
65#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1) /* In bytes */
66#define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
67#define CAST64(v) ((long long)(long)(v))
68#define CASTPTR(type, v) ((type *)(long)(v))
69
70/*
71 * Returns processor ID, different Linux and simple exec versions
72 * provided in the cvmx-app-init*.c files.
73 */
74static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
75static inline uint32_t cvmx_get_proc_id(void)
76{
77 uint32_t id;
78 asm("mfc0 %0, $15,0" : "=r"(id));
79 return id;
80}
81
82/* turn the variable name into a string */
83#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
84#define CVMX_TMP_STR2(x) #x
85
86/**
87 * Builds a bit mask given the required size in bits.
88 *
89 * @bits: Number of bits in the mask
90 * Returns The mask
91 */ static inline uint64_t cvmx_build_mask(uint64_t bits)
92{
93 return ~((~0x0ull) << bits);
94}
95
96/**
97 * Builds a memory address for I/O based on the Major and Sub DID.
98 *
99 * @major_did: 5 bit major did
100 * @sub_did: 3 bit sub did
101 * Returns I/O base address
102 */
103static inline uint64_t cvmx_build_io_address(uint64_t major_did,
104 uint64_t sub_did)
105{
106 return (0x1ull << 48) | (major_did << 43) | (sub_did << 40);
107}
108
109/**
110 * Perform mask and shift to place the supplied value into
111 * the supplied bit rage.
112 *
113 * Example: cvmx_build_bits(39,24,value)
114 * <pre>
115 * 6 5 4 3 3 2 1
116 * 3 5 7 9 1 3 5 7 0
117 * +-------+-------+-------+-------+-------+-------+-------+------+
118 * 000000000000000000000000___________value000000000000000000000000
119 * </pre>
120 *
121 * @high_bit: Highest bit value can occupy (inclusive) 0-63
122 * @low_bit: Lowest bit value can occupy inclusive 0-high_bit
123 * @value: Value to use
124 * Returns Value masked and shifted
125 */
126static inline uint64_t cvmx_build_bits(uint64_t high_bit,
127 uint64_t low_bit, uint64_t value)
128{
129 return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
130}
131
132enum cvmx_mips_space {
133 CVMX_MIPS_SPACE_XKSEG = 3LL,
134 CVMX_MIPS_SPACE_XKPHYS = 2LL,
135 CVMX_MIPS_SPACE_XSSEG = 1LL,
136 CVMX_MIPS_SPACE_XUSEG = 0LL
137};
138
139/* These macros for use when using 32 bit pointers. */
140#define CVMX_MIPS32_SPACE_KSEG0 1l
141#define CVMX_ADD_SEG32(segment, add) \
142 (((int32_t)segment << 31) | (int32_t)(add))
143
144#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
145
146/* These macros simplify the process of creating common IO addresses */
147#define CVMX_ADD_SEG(segment, add) \
148 ((((uint64_t)segment) << 62) | (add))
149#ifndef CVMX_ADD_IO_SEG
150#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
151#endif
152
153/**
154 * Convert a memory pointer (void*) into a hardware compatable
155 * memory address (uint64_t). Octeon hardware widgets don't
156 * understand logical addresses.
157 *
158 * @ptr: C style memory pointer
159 * Returns Hardware physical address
160 */
161static inline uint64_t cvmx_ptr_to_phys(void *ptr)
162{
163 if (sizeof(void *) == 8) {
164 /*
165 * We're running in 64 bit mode. Normally this means
166 * that we can use 40 bits of address space (the
167 * hardware limit). Unfortunately there is one case
168 * were we need to limit this to 30 bits, sign
169 * extended 32 bit. Although these are 64 bits wide,
170 * only 30 bits can be used.
171 */
172 if ((CAST64(ptr) >> 62) == 3)
173 return CAST64(ptr) & cvmx_build_mask(30);
174 else
175 return CAST64(ptr) & cvmx_build_mask(40);
176 } else {
177 return (long)(ptr) & 0x1fffffff;
178 }
179}
180
181/**
182 * Convert a hardware physical address (uint64_t) into a
183 * memory pointer (void *).
184 *
185 * @physical_address:
186 * Hardware physical address to memory
187 * Returns Pointer to memory
188 */
189static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
190{
191 if (sizeof(void *) == 8) {
192 /* Just set the top bit, avoiding any TLB uglyness */
193 return CASTPTR(void,
194 CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
195 physical_address));
196 } else {
197 return CASTPTR(void,
198 CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,
199 physical_address));
200 }
201}
202
203/* The following #if controls the definition of the macro
204 CVMX_BUILD_WRITE64. This macro is used to build a store operation to
205 a full 64bit address. With a 64bit ABI, this can be done with a simple
206 pointer access. 32bit ABIs require more complicated assembly */
207
208/* We have a full 64bit ABI. Writing to a 64bit address can be done with
209 a simple volatile pointer */
210#define CVMX_BUILD_WRITE64(TYPE, ST) \
211static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
212{ \
213 *CASTPTR(volatile TYPE##_t, addr) = val; \
214}
215
216
217/* The following #if controls the definition of the macro
218 CVMX_BUILD_READ64. This macro is used to build a load operation from
219 a full 64bit address. With a 64bit ABI, this can be done with a simple
220 pointer access. 32bit ABIs require more complicated assembly */
221
222/* We have a full 64bit ABI. Writing to a 64bit address can be done with
223 a simple volatile pointer */
224#define CVMX_BUILD_READ64(TYPE, LT) \
225static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
226{ \
227 return *CASTPTR(volatile TYPE##_t, addr); \
228}
229
230
231/* The following defines 8 functions for writing to a 64bit address. Each
232 takes two arguments, the address and the value to write.
233 cvmx_write64_int64 cvmx_write64_uint64
234 cvmx_write64_int32 cvmx_write64_uint32
235 cvmx_write64_int16 cvmx_write64_uint16
236 cvmx_write64_int8 cvmx_write64_uint8 */
237CVMX_BUILD_WRITE64(int64, "sd");
238CVMX_BUILD_WRITE64(int32, "sw");
239CVMX_BUILD_WRITE64(int16, "sh");
240CVMX_BUILD_WRITE64(int8, "sb");
241CVMX_BUILD_WRITE64(uint64, "sd");
242CVMX_BUILD_WRITE64(uint32, "sw");
243CVMX_BUILD_WRITE64(uint16, "sh");
244CVMX_BUILD_WRITE64(uint8, "sb");
245#define cvmx_write64 cvmx_write64_uint64
246
247/* The following defines 8 functions for reading from a 64bit address. Each
248 takes the address as the only argument
249 cvmx_read64_int64 cvmx_read64_uint64
250 cvmx_read64_int32 cvmx_read64_uint32
251 cvmx_read64_int16 cvmx_read64_uint16
252 cvmx_read64_int8 cvmx_read64_uint8 */
253CVMX_BUILD_READ64(int64, "ld");
254CVMX_BUILD_READ64(int32, "lw");
255CVMX_BUILD_READ64(int16, "lh");
256CVMX_BUILD_READ64(int8, "lb");
257CVMX_BUILD_READ64(uint64, "ld");
258CVMX_BUILD_READ64(uint32, "lw");
259CVMX_BUILD_READ64(uint16, "lhu");
260CVMX_BUILD_READ64(uint8, "lbu");
261#define cvmx_read64 cvmx_read64_uint64
262
263
264static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
265{
266 cvmx_write64(csr_addr, val);
267
268 /*
269 * Perform an immediate read after every write to an RSL
270 * register to force the write to complete. It doesn't matter
271 * what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT
272 * because it is fast and harmless.
273 */
274 if ((csr_addr >> 40) == (0x800118))
275 cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);
276}
277
278static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
279{
280 cvmx_write64(io_addr, val);
281
282}
283
284static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
285{
286 uint64_t val = cvmx_read64(csr_addr);
287 return val;
288}
289
290
291static inline void cvmx_send_single(uint64_t data)
292{
293 const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull;
294 cvmx_write64(CVMX_IOBDMA_SENDSINGLE, data);
295}
296
297static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr)
298{
299 union {
300 uint64_t u64;
301 struct {
302 uint64_t scraddr:8;
303 uint64_t len:8;
304 uint64_t addr:48;
305 } s;
306 } addr;
307 addr.u64 = csr_addr;
308 addr.s.scraddr = scraddr >> 3;
309 addr.s.len = 1;
310 cvmx_send_single(addr.u64);
311}
312
313/* Return true if Octeon is CN38XX pass 1 */
314static inline int cvmx_octeon_is_pass1(void)
315{
316#if OCTEON_IS_COMMON_BINARY()
317 return 0; /* Pass 1 isn't supported for common binaries */
318#else
319/* Now that we know we're built for a specific model, only check CN38XX */
320#if OCTEON_IS_MODEL(OCTEON_CN38XX)
321 return cvmx_get_proc_id() == OCTEON_CN38XX_PASS1;
322#else
323 return 0; /* Built for non CN38XX chip, we're not CN38XX pass1 */
324#endif
325#endif
326}
327
328static inline unsigned int cvmx_get_core_num(void)
329{
330 unsigned int core_num;
331 CVMX_RDHWRNV(core_num, 0);
332 return core_num;
333}
334
335/**
336 * Returns the number of bits set in the provided value.
337 * Simple wrapper for POP instruction.
338 *
339 * @val: 32 bit value to count set bits in
340 *
341 * Returns Number of bits set
342 */
343static inline uint32_t cvmx_pop(uint32_t val)
344{
345 uint32_t pop;
346 CVMX_POP(pop, val);
347 return pop;
348}
349
350/**
351 * Returns the number of bits set in the provided value.
352 * Simple wrapper for DPOP instruction.
353 *
354 * @val: 64 bit value to count set bits in
355 *
356 * Returns Number of bits set
357 */
358static inline int cvmx_dpop(uint64_t val)
359{
360 int pop;
361 CVMX_DPOP(pop, val);
362 return pop;
363}
364
365/**
366 * Provide current cycle counter as a return value
367 *
368 * Returns current cycle counter
369 */
370
371static inline uint64_t cvmx_get_cycle(void)
372{
373 uint64_t cycle;
374 CVMX_RDHWR(cycle, 31);
375 return cycle;
376}
377
378/**
379 * Reads a chip global cycle counter. This counts CPU cycles since
380 * chip reset. The counter is 64 bit.
381 * This register does not exist on CN38XX pass 1 silicion
382 *
383 * Returns Global chip cycle count since chip reset.
384 */
385static inline uint64_t cvmx_get_cycle_global(void)
386{
387 if (cvmx_octeon_is_pass1())
388 return 0;
389 else
390 return cvmx_read64(CVMX_IPD_CLK_COUNT);
391}
392
393/**
394 * This macro spins on a field waiting for it to reach a value. It
395 * is common in code to need to wait for a specific field in a CSR
396 * to match a specific value. Conceptually this macro expands to:
397 *
398 * 1) read csr at "address" with a csr typedef of "type"
399 * 2) Check if ("type".s."field" "op" "value")
400 * 3) If #2 isn't true loop to #1 unless too much time has passed.
401 */
402#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\
403 ( \
404{ \
405 int result; \
406 do { \
407 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
408 cvmx_sysinfo_get()->cpu_clock_hz / 1000000; \
409 type c; \
410 while (1) { \
411 c.u64 = cvmx_read_csr(address); \
412 if ((c.s.field) op(value)) { \
413 result = 0; \
414 break; \
415 } else if (cvmx_get_cycle() > done) { \
416 result = -1; \
417 break; \
418 } else \
419 cvmx_wait(100); \
420 } \
421 } while (0); \
422 result; \
423})
424
425/***************************************************************************/
426
427static inline void cvmx_reset_octeon(void)
428{
429 union cvmx_ciu_soft_rst ciu_soft_rst;
430 ciu_soft_rst.u64 = 0;
431 ciu_soft_rst.s.soft_rst = 1;
432 cvmx_write_csr(CVMX_CIU_SOFT_RST, ciu_soft_rst.u64);
433}
434
435/* Return the number of cores available in the chip */
436static inline uint32_t cvmx_octeon_num_cores(void)
437{
438 uint32_t ciu_fuse = (uint32_t) cvmx_read_csr(CVMX_CIU_FUSE) & 0xffff;
439 return cvmx_pop(ciu_fuse);
440}
441
442/**
443 * Read a byte of fuse data
444 * @byte_addr: address to read
445 *
446 * Returns fuse value: 0 or 1
447 */
448static uint8_t cvmx_fuse_read_byte(int byte_addr)
449{
450 union cvmx_mio_fus_rcmd read_cmd;
451
452 read_cmd.u64 = 0;
453 read_cmd.s.addr = byte_addr;
454 read_cmd.s.pend = 1;
455 cvmx_write_csr(CVMX_MIO_FUS_RCMD, read_cmd.u64);
456 while ((read_cmd.u64 = cvmx_read_csr(CVMX_MIO_FUS_RCMD))
457 && read_cmd.s.pend)
458 ;
459 return read_cmd.s.dat;
460}
461
462/**
463 * Read a single fuse bit
464 *
465 * @fuse: Fuse number (0-1024)
466 *
467 * Returns fuse value: 0 or 1
468 */
469static inline int cvmx_fuse_read(int fuse)
470{
471 return (cvmx_fuse_read_byte(fuse >> 3) >> (fuse & 0x7)) & 1;
472}
473
474static inline int cvmx_octeon_model_CN36XX(void)
475{
476 return OCTEON_IS_MODEL(OCTEON_CN38XX)
477 && !cvmx_octeon_is_pass1()
478 && cvmx_fuse_read(264);
479}
480
481static inline int cvmx_octeon_zip_present(void)
482{
483 return octeon_has_feature(OCTEON_FEATURE_ZIP);
484}
485
486static inline int cvmx_octeon_dfa_present(void)
487{
488 if (!OCTEON_IS_MODEL(OCTEON_CN38XX)
489 && !OCTEON_IS_MODEL(OCTEON_CN31XX)
490 && !OCTEON_IS_MODEL(OCTEON_CN58XX))
491 return 0;
492 else if (OCTEON_IS_MODEL(OCTEON_CN3020))
493 return 0;
494 else if (cvmx_octeon_is_pass1())
495 return 1;
496 else
497 return !cvmx_fuse_read(120);
498}
499
500static inline int cvmx_octeon_crypto_present(void)
501{
502 return octeon_has_feature(OCTEON_FEATURE_CRYPTO);
503}
504
505#endif /* __CVMX_H__ */
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h
new file mode 100644
index 000000000000..04fac684069c
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -0,0 +1,119 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 * File defining checks for different Octeon features.
30 */
31
32#ifndef __OCTEON_FEATURE_H__
33#define __OCTEON_FEATURE_H__
34
35enum octeon_feature {
36 /*
37 * Octeon models in the CN5XXX family and higher support
38 * atomic add instructions to memory (saa/saad).
39 */
40 OCTEON_FEATURE_SAAD,
41 /* Does this Octeon support the ZIP offload engine? */
42 OCTEON_FEATURE_ZIP,
43 /* Does this Octeon support crypto acceleration using COP2? */
44 OCTEON_FEATURE_CRYPTO,
45 /* Does this Octeon support PCI express? */
46 OCTEON_FEATURE_PCIE,
47 /* Some Octeon models support internal memory for storing
48 * cryptographic keys */
49 OCTEON_FEATURE_KEY_MEMORY,
50 /* Octeon has a LED controller for banks of external LEDs */
51 OCTEON_FEATURE_LED_CONTROLLER,
52 /* Octeon has a trace buffer */
53 OCTEON_FEATURE_TRA,
54 /* Octeon has a management port */
55 OCTEON_FEATURE_MGMT_PORT,
56 /* Octeon has a raid unit */
57 OCTEON_FEATURE_RAID,
58 /* Octeon has a builtin USB */
59 OCTEON_FEATURE_USB,
60};
61
62static inline int cvmx_fuse_read(int fuse);
63
64/**
65 * Determine if the current Octeon supports a specific feature. These
66 * checks have been optimized to be fairly quick, but they should still
67 * be kept out of fast path code.
68 *
69 * @feature: Feature to check for. This should always be a constant so the
70 * compiler can remove the switch statement through optimization.
71 *
72 * Returns Non zero if the feature exists. Zero if the feature does not
73 * exist.
74 */
75static inline int octeon_has_feature(enum octeon_feature feature)
76{
77 switch (feature) {
78 case OCTEON_FEATURE_SAAD:
79 return !OCTEON_IS_MODEL(OCTEON_CN3XXX);
80
81 case OCTEON_FEATURE_ZIP:
82 if (OCTEON_IS_MODEL(OCTEON_CN30XX)
83 || OCTEON_IS_MODEL(OCTEON_CN50XX)
84 || OCTEON_IS_MODEL(OCTEON_CN52XX))
85 return 0;
86 else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
87 return 1;
88 else
89 return !cvmx_fuse_read(121);
90
91 case OCTEON_FEATURE_CRYPTO:
92 return !cvmx_fuse_read(90);
93
94 case OCTEON_FEATURE_PCIE:
95 return OCTEON_IS_MODEL(OCTEON_CN56XX)
96 || OCTEON_IS_MODEL(OCTEON_CN52XX);
97
98 case OCTEON_FEATURE_KEY_MEMORY:
99 case OCTEON_FEATURE_LED_CONTROLLER:
100 return OCTEON_IS_MODEL(OCTEON_CN38XX)
101 || OCTEON_IS_MODEL(OCTEON_CN58XX)
102 || OCTEON_IS_MODEL(OCTEON_CN56XX);
103 case OCTEON_FEATURE_TRA:
104 return !(OCTEON_IS_MODEL(OCTEON_CN30XX)
105 || OCTEON_IS_MODEL(OCTEON_CN50XX));
106 case OCTEON_FEATURE_MGMT_PORT:
107 return OCTEON_IS_MODEL(OCTEON_CN56XX)
108 || OCTEON_IS_MODEL(OCTEON_CN52XX);
109 case OCTEON_FEATURE_RAID:
110 return OCTEON_IS_MODEL(OCTEON_CN56XX)
111 || OCTEON_IS_MODEL(OCTEON_CN52XX);
112 case OCTEON_FEATURE_USB:
113 return !(OCTEON_IS_MODEL(OCTEON_CN38XX)
114 || OCTEON_IS_MODEL(OCTEON_CN58XX));
115 }
116 return 0;
117}
118
119#endif /* __OCTEON_FEATURE_H__ */
diff --git a/arch/mips/include/asm/octeon/octeon-model.h b/arch/mips/include/asm/octeon/octeon-model.h
new file mode 100644
index 000000000000..cf50336eca2e
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon-model.h
@@ -0,0 +1,321 @@
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/*
29 *
30 * File defining different Octeon model IDs and macros to
31 * compare them.
32 *
33 */
34
35#ifndef __OCTEON_MODEL_H__
36#define __OCTEON_MODEL_H__
37
38/* NOTE: These must match what is checked in common-config.mk */
39/* Defines to represent the different versions of Octeon. */
40
41/*
42 * IMPORTANT: When the default pass is updated for an Octeon Model,
43 * the corresponding change must also be made in the oct-sim script.
44 */
45
46/*
47 * The defines below should be used with the OCTEON_IS_MODEL() macro
48 * to determine what model of chip the software is running on. Models
49 * ending in 'XX' match multiple models (families), while specific
50 * models match only that model. If a pass (revision) is specified,
51 * then only that revision will be matched. Care should be taken when
52 * checking for both specific models and families that the specific
53 * models are checked for first. While these defines are similar to
54 * the processor ID, they are not intended to be used by anything
55 * other that the OCTEON_IS_MODEL framework, and the values are
56 * subject to change at anytime without notice.
57 *
58 * NOTE: only the OCTEON_IS_MODEL() macro/function and the OCTEON_CN*
59 * macros should be used outside of this file. All other macros are
60 * for internal use only, and may change without notice.
61 */
62
63/* Flag bits in top byte */
64/* Ignores revision in model checks */
65#define OM_IGNORE_REVISION 0x01000000
66/* Check submodels */
67#define OM_CHECK_SUBMODEL 0x02000000
68/* Match all models previous than the one specified */
69#define OM_MATCH_PREVIOUS_MODELS 0x04000000
70/* Ignores the minor revison on newer parts */
71#define OM_IGNORE_MINOR_REVISION 0x08000000
72#define OM_FLAG_MASK 0xff000000
73
74/*
75 * CN5XXX models with new revision encoding
76 */
77#define OCTEON_CN58XX_PASS1_0 0x000d0300
78#define OCTEON_CN58XX_PASS1_1 0x000d0301
79#define OCTEON_CN58XX_PASS1_2 0x000d0303
80#define OCTEON_CN58XX_PASS2_0 0x000d0308
81#define OCTEON_CN58XX_PASS2_1 0x000d0309
82#define OCTEON_CN58XX_PASS2_2 0x000d030a
83#define OCTEON_CN58XX_PASS2_3 0x000d030b
84
85#define OCTEON_CN58XX (OCTEON_CN58XX_PASS1_0 | OM_IGNORE_REVISION)
86#define OCTEON_CN58XX_PASS1_X (OCTEON_CN58XX_PASS1_0 \
87 | OM_IGNORE_MINOR_REVISION)
88#define OCTEON_CN58XX_PASS2_X (OCTEON_CN58XX_PASS2_0 \
89 | OM_IGNORE_MINOR_REVISION)
90#define OCTEON_CN58XX_PASS1 OCTEON_CN58XX_PASS1_X
91#define OCTEON_CN58XX_PASS2 OCTEON_CN58XX_PASS2_X
92
93#define OCTEON_CN56XX_PASS1_0 0x000d0400
94#define OCTEON_CN56XX_PASS1_1 0x000d0401
95#define OCTEON_CN56XX_PASS2_0 0x000d0408
96#define OCTEON_CN56XX_PASS2_1 0x000d0409
97
98#define OCTEON_CN56XX (OCTEON_CN56XX_PASS2_0 | OM_IGNORE_REVISION)
99#define OCTEON_CN56XX_PASS1_X (OCTEON_CN56XX_PASS1_0 \
100 | OM_IGNORE_MINOR_REVISION)
101#define OCTEON_CN56XX_PASS2_X (OCTEON_CN56XX_PASS2_0 \
102 | OM_IGNORE_MINOR_REVISION)
103#define OCTEON_CN56XX_PASS1 OCTEON_CN56XX_PASS1_X
104#define OCTEON_CN56XX_PASS2 OCTEON_CN56XX_PASS2_X
105
106#define OCTEON_CN57XX OCTEON_CN56XX
107#define OCTEON_CN57XX_PASS1 OCTEON_CN56XX_PASS1
108#define OCTEON_CN57XX_PASS2 OCTEON_CN56XX_PASS2
109
110#define OCTEON_CN55XX OCTEON_CN56XX
111#define OCTEON_CN55XX_PASS1 OCTEON_CN56XX_PASS1
112#define OCTEON_CN55XX_PASS2 OCTEON_CN56XX_PASS2
113
114#define OCTEON_CN54XX OCTEON_CN56XX
115#define OCTEON_CN54XX_PASS1 OCTEON_CN56XX_PASS1
116#define OCTEON_CN54XX_PASS2 OCTEON_CN56XX_PASS2
117
118#define OCTEON_CN50XX_PASS1_0 0x000d0600
119
120#define OCTEON_CN50XX (OCTEON_CN50XX_PASS1_0 | OM_IGNORE_REVISION)
121#define OCTEON_CN50XX_PASS1_X (OCTEON_CN50XX_PASS1_0 \
122 | OM_IGNORE_MINOR_REVISION)
123#define OCTEON_CN50XX_PASS1 OCTEON_CN50XX_PASS1_X
124
125/*
126 * NOTE: Octeon CN5000F model is not identifiable using the
127 * OCTEON_IS_MODEL() functions, but are treated as CN50XX.
128 */
129
130#define OCTEON_CN52XX_PASS1_0 0x000d0700
131#define OCTEON_CN52XX_PASS2_0 0x000d0708
132
133#define OCTEON_CN52XX (OCTEON_CN52XX_PASS2_0 | OM_IGNORE_REVISION)
134#define OCTEON_CN52XX_PASS1_X (OCTEON_CN52XX_PASS1_0 \
135 | OM_IGNORE_MINOR_REVISION)
136#define OCTEON_CN52XX_PASS2_X (OCTEON_CN52XX_PASS2_0 \
137 | OM_IGNORE_MINOR_REVISION)
138#define OCTEON_CN52XX_PASS1 OCTEON_CN52XX_PASS1_X
139#define OCTEON_CN52XX_PASS2 OCTEON_CN52XX_PASS2_X
140
141/*
142 * CN3XXX models with old revision enconding
143 */
144#define OCTEON_CN38XX_PASS1 0x000d0000
145#define OCTEON_CN38XX_PASS2 0x000d0001
146#define OCTEON_CN38XX_PASS3 0x000d0003
147#define OCTEON_CN38XX (OCTEON_CN38XX_PASS3 | OM_IGNORE_REVISION)
148
149#define OCTEON_CN36XX OCTEON_CN38XX
150#define OCTEON_CN36XX_PASS2 OCTEON_CN38XX_PASS2
151#define OCTEON_CN36XX_PASS3 OCTEON_CN38XX_PASS3
152
153/* The OCTEON_CN31XX matches CN31XX models and the CN3020 */
154#define OCTEON_CN31XX_PASS1 0x000d0100
155#define OCTEON_CN31XX_PASS1_1 0x000d0102
156#define OCTEON_CN31XX (OCTEON_CN31XX_PASS1 | OM_IGNORE_REVISION)
157
158/*
159 * This model is only used for internal checks, it is not a valid
160 * model for the OCTEON_MODEL environment variable. This matches the
161 * CN3010 and CN3005 but NOT the CN3020.
162 */
163#define OCTEON_CN30XX_PASS1 0x000d0200
164#define OCTEON_CN30XX_PASS1_1 0x000d0202
165#define OCTEON_CN30XX (OCTEON_CN30XX_PASS1 | OM_IGNORE_REVISION)
166
167#define OCTEON_CN3005_PASS1 (0x000d0210 | OM_CHECK_SUBMODEL)
168#define OCTEON_CN3005_PASS1_0 (0x000d0210 | OM_CHECK_SUBMODEL)
169#define OCTEON_CN3005_PASS1_1 (0x000d0212 | OM_CHECK_SUBMODEL)
170#define OCTEON_CN3005 (OCTEON_CN3005_PASS1 | OM_IGNORE_REVISION \
171 | OM_CHECK_SUBMODEL)
172
173#define OCTEON_CN3010_PASS1 (0x000d0200 | OM_CHECK_SUBMODEL)
174#define OCTEON_CN3010_PASS1_0 (0x000d0200 | OM_CHECK_SUBMODEL)
175#define OCTEON_CN3010_PASS1_1 (0x000d0202 | OM_CHECK_SUBMODEL)
176#define OCTEON_CN3010 (OCTEON_CN3010_PASS1 | OM_IGNORE_REVISION \
177 | OM_CHECK_SUBMODEL)
178
179#define OCTEON_CN3020_PASS1 (0x000d0110 | OM_CHECK_SUBMODEL)
180#define OCTEON_CN3020_PASS1_0 (0x000d0110 | OM_CHECK_SUBMODEL)
181#define OCTEON_CN3020_PASS1_1 (0x000d0112 | OM_CHECK_SUBMODEL)
182#define OCTEON_CN3020 (OCTEON_CN3020_PASS1 | OM_IGNORE_REVISION \
183 | OM_CHECK_SUBMODEL)
184
185
186
187/* This matches the complete family of CN3xxx CPUs, and not subsequent models */
188#define OCTEON_CN3XXX (OCTEON_CN58XX_PASS1_0 \
189 | OM_MATCH_PREVIOUS_MODELS \
190 | OM_IGNORE_REVISION)
191
192/* The revision byte (low byte) has two different encodings.
193 * CN3XXX:
194 *
195 * bits
196 * <7:5>: reserved (0)
197 * <4>: alternate package
198 * <3:0>: revision
199 *
200 * CN5XXX:
201 *
202 * bits
203 * <7>: reserved (0)
204 * <6>: alternate package
205 * <5:3>: major revision
206 * <2:0>: minor revision
207 *
208 */
209
210/* Masks used for the various types of model/family/revision matching */
211#define OCTEON_38XX_FAMILY_MASK 0x00ffff00
212#define OCTEON_38XX_FAMILY_REV_MASK 0x00ffff0f
213#define OCTEON_38XX_MODEL_MASK 0x00ffff10
214#define OCTEON_38XX_MODEL_REV_MASK (OCTEON_38XX_FAMILY_REV_MASK \
215 | OCTEON_38XX_MODEL_MASK)
216
217/* CN5XXX and later use different layout of bits in the revision ID field */
218#define OCTEON_58XX_FAMILY_MASK OCTEON_38XX_FAMILY_MASK
219#define OCTEON_58XX_FAMILY_REV_MASK 0x00ffff3f
220#define OCTEON_58XX_MODEL_MASK 0x00ffffc0
221#define OCTEON_58XX_MODEL_REV_MASK (OCTEON_58XX_FAMILY_REV_MASK \
222 | OCTEON_58XX_MODEL_MASK)
223#define OCTEON_58XX_MODEL_MINOR_REV_MASK (OCTEON_58XX_MODEL_REV_MASK \
224 & 0x00fffff8)
225
226#define __OCTEON_MATCH_MASK__(x, y, z) (((x) & (z)) == ((y) & (z)))
227
228/* NOTE: This is for internal (to this file) use only. */
229static inline int __OCTEON_IS_MODEL_COMPILE__(uint32_t arg_model,
230 uint32_t chip_model)
231{
232 uint32_t rev_and_sub = OM_IGNORE_REVISION | OM_CHECK_SUBMODEL;
233
234 if ((arg_model & OCTEON_38XX_FAMILY_MASK) < OCTEON_CN58XX_PASS1_0) {
235 if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
236 __OCTEON_MATCH_MASK__(chip_model, arg_model,
237 OCTEON_38XX_MODEL_MASK))
238 return 1;
239 if (((arg_model & OM_FLAG_MASK) == 0) &&
240 __OCTEON_MATCH_MASK__(chip_model, arg_model,
241 OCTEON_38XX_FAMILY_REV_MASK))
242 return 1;
243 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
244 __OCTEON_MATCH_MASK__(chip_model, arg_model,
245 OCTEON_38XX_FAMILY_MASK))
246 return 1;
247 if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
248 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
249 OCTEON_38XX_MODEL_REV_MASK))
250 return 1;
251 if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
252 ((chip_model & OCTEON_38XX_MODEL_MASK) <
253 (arg_model & OCTEON_38XX_MODEL_MASK)))
254 return 1;
255 } else {
256 if (((arg_model & OM_FLAG_MASK) == rev_and_sub) &&
257 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
258 OCTEON_58XX_MODEL_MASK))
259 return 1;
260 if (((arg_model & OM_FLAG_MASK) == 0) &&
261 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
262 OCTEON_58XX_FAMILY_REV_MASK))
263 return 1;
264 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_MINOR_REVISION) &&
265 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
266 OCTEON_58XX_MODEL_MINOR_REV_MASK))
267 return 1;
268 if (((arg_model & OM_FLAG_MASK) == OM_IGNORE_REVISION) &&
269 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
270 OCTEON_58XX_FAMILY_MASK))
271 return 1;
272 if (((arg_model & OM_FLAG_MASK) == OM_CHECK_SUBMODEL) &&
273 __OCTEON_MATCH_MASK__((chip_model), (arg_model),
274 OCTEON_58XX_MODEL_REV_MASK))
275 return 1;
276 if ((arg_model & OM_MATCH_PREVIOUS_MODELS) &&
277 ((chip_model & OCTEON_58XX_MODEL_MASK) <
278 (arg_model & OCTEON_58XX_MODEL_MASK)))
279 return 1;
280 }
281 return 0;
282}
283
284/* forward declarations */
285static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
286static inline uint64_t cvmx_read_csr(uint64_t csr_addr);
287
288/* NOTE: This for internal use only!!!!! */
289static inline int __octeon_is_model_runtime__(uint32_t model)
290{
291 uint32_t cpuid = cvmx_get_proc_id();
292
293 /*
294 * Check for special case of mismarked 3005 samples. We only
295 * need to check if the sub model isn't being ignored.
296 */
297 if ((model & OM_CHECK_SUBMODEL) == OM_CHECK_SUBMODEL) {
298 if (cpuid == OCTEON_CN3010_PASS1 \
299 && (cvmx_read_csr(0x80011800800007B8ull) & (1ull << 34)))
300 cpuid |= 0x10;
301 }
302 return __OCTEON_IS_MODEL_COMPILE__(model, cpuid);
303}
304
305/*
306 * The OCTEON_IS_MODEL macro should be used for all Octeon model
307 * checking done in a program. This should be kept runtime if at all
308 * possible. Any compile time (#if OCTEON_IS_MODEL) usage must be
309 * condtionalized with OCTEON_IS_COMMON_BINARY() if runtime checking
310 * support is required.
311 */
312#define OCTEON_IS_MODEL(x) __octeon_is_model_runtime__(x)
313#define OCTEON_IS_COMMON_BINARY() 1
314#undef OCTEON_MODEL
315
316const char *octeon_model_get_string(uint32_t chip_id);
317const char *octeon_model_get_string_buffer(uint32_t chip_id, char *buffer);
318
319#include "octeon-feature.h"
320
321#endif /* __OCTEON_MODEL_H__ */
diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
new file mode 100644
index 000000000000..edc676084cda
--- /dev/null
+++ b/arch/mips/include/asm/octeon/octeon.h
@@ -0,0 +1,248 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2004-2008 Cavium Networks
7 */
8#ifndef __ASM_OCTEON_OCTEON_H
9#define __ASM_OCTEON_OCTEON_H
10
11#include "cvmx.h"
12
13extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
14 uint64_t alignment,
15 uint64_t min_addr,
16 uint64_t max_addr,
17 int do_locking);
18extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment,
19 int do_locking);
20extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment,
21 uint64_t min_addr, uint64_t max_addr,
22 int do_locking);
23extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment,
24 char *name);
25extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
26 uint64_t max_addr, uint64_t align,
27 char *name);
28extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address,
29 char *name);
30extern int octeon_bootmem_free_named(char *name);
31extern void octeon_bootmem_lock(void);
32extern void octeon_bootmem_unlock(void);
33
34extern int octeon_is_simulation(void);
35extern int octeon_is_pci_host(void);
36extern int octeon_usb_is_ref_clk(void);
37extern uint64_t octeon_get_clock_rate(void);
38extern const char *octeon_board_type_string(void);
39extern const char *octeon_get_pci_interrupts(void);
40extern int octeon_get_southbridge_interrupt(void);
41extern int octeon_get_boot_coremask(void);
42extern int octeon_get_boot_num_arguments(void);
43extern const char *octeon_get_boot_argument(int arg);
44extern void octeon_hal_setup_reserved32(void);
45extern void octeon_user_io_init(void);
46struct octeon_cop2_state;
47extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
48extern void octeon_crypto_disable(struct octeon_cop2_state *state,
49 unsigned long flags);
50
51extern void octeon_init_cvmcount(void);
52
53#define OCTEON_ARGV_MAX_ARGS 64
54#define OCTOEN_SERIAL_LEN 20
55
56struct octeon_boot_descriptor {
57 /* Start of block referenced by assembly code - do not change! */
58 uint32_t desc_version;
59 uint32_t desc_size;
60 uint64_t stack_top;
61 uint64_t heap_base;
62 uint64_t heap_end;
63 /* Only used by bootloader */
64 uint64_t entry_point;
65 uint64_t desc_vaddr;
66 /* End of This block referenced by assembly code - do not change! */
67 uint32_t exception_base_addr;
68 uint32_t stack_size;
69 uint32_t heap_size;
70 /* Argc count for application. */
71 uint32_t argc;
72 uint32_t argv[OCTEON_ARGV_MAX_ARGS];
73
74#define BOOT_FLAG_INIT_CORE (1 << 0)
75#define OCTEON_BL_FLAG_DEBUG (1 << 1)
76#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2)
77 /* If set, use uart1 for console */
78#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3)
79 /* If set, use PCI console */
80#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4)
81 /* Call exit on break on serial port */
82#define OCTEON_BL_FLAG_BREAK (1 << 5)
83
84 uint32_t flags;
85 uint32_t core_mask;
86 /* DRAM size in megabyes. */
87 uint32_t dram_size;
88 /* physical address of free memory descriptor block. */
89 uint32_t phy_mem_desc_addr;
90 /* used to pass flags from app to debugger. */
91 uint32_t debugger_flags_base_addr;
92 /* CPU clock speed, in hz. */
93 uint32_t eclock_hz;
94 /* DRAM clock speed, in hz. */
95 uint32_t dclock_hz;
96 /* SPI4 clock in hz. */
97 uint32_t spi_clock_hz;
98 uint16_t board_type;
99 uint8_t board_rev_major;
100 uint8_t board_rev_minor;
101 uint16_t chip_type;
102 uint8_t chip_rev_major;
103 uint8_t chip_rev_minor;
104 char board_serial_number[OCTOEN_SERIAL_LEN];
105 uint8_t mac_addr_base[6];
106 uint8_t mac_addr_count;
107 uint64_t cvmx_desc_vaddr;
108};
109
110union octeon_cvmemctl {
111 uint64_t u64;
112 struct {
113 /* RO 1 = BIST fail, 0 = BIST pass */
114 uint64_t tlbbist:1;
115 /* RO 1 = BIST fail, 0 = BIST pass */
116 uint64_t l1cbist:1;
117 /* RO 1 = BIST fail, 0 = BIST pass */
118 uint64_t l1dbist:1;
119 /* RO 1 = BIST fail, 0 = BIST pass */
120 uint64_t dcmbist:1;
121 /* RO 1 = BIST fail, 0 = BIST pass */
122 uint64_t ptgbist:1;
123 /* RO 1 = BIST fail, 0 = BIST pass */
124 uint64_t wbfbist:1;
125 /* Reserved */
126 uint64_t reserved:22;
127 /* R/W If set, marked write-buffer entries time out
128 * the same as as other entries; if clear, marked
129 * write-buffer entries use the maximum timeout. */
130 uint64_t dismarkwblongto:1;
131 /* R/W If set, a merged store does not clear the
132 * write-buffer entry timeout state. */
133 uint64_t dismrgclrwbto:1;
134 /* R/W Two bits that are the MSBs of the resultant
135 * CVMSEG LM word location for an IOBDMA. The other 8
136 * bits come from the SCRADDR field of the IOBDMA. */
137 uint64_t iobdmascrmsb:2;
138 /* R/W If set, SYNCWS and SYNCS only order marked
139 * stores; if clear, SYNCWS and SYNCS only order
140 * unmarked stores. SYNCWSMARKED has no effect when
141 * DISSYNCWS is set. */
142 uint64_t syncwsmarked:1;
143 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
144 * SYNC. */
145 uint64_t dissyncws:1;
146 /* R/W If set, no stall happens on write buffer
147 * full. */
148 uint64_t diswbfst:1;
149 /* R/W If set (and SX set), supervisor-level
150 * loads/stores can use XKPHYS addresses with
151 * VA<48>==0 */
152 uint64_t xkmemenas:1;
153 /* R/W If set (and UX set), user-level loads/stores
154 * can use XKPHYS addresses with VA<48>==0 */
155 uint64_t xkmemenau:1;
156 /* R/W If set (and SX set), supervisor-level
157 * loads/stores can use XKPHYS addresses with
158 * VA<48>==1 */
159 uint64_t xkioenas:1;
160 /* R/W If set (and UX set), user-level loads/stores
161 * can use XKPHYS addresses with VA<48>==1 */
162 uint64_t xkioenau:1;
163 /* R/W If set, all stores act as SYNCW (NOMERGE must
164 * be set when this is set) RW, reset to 0. */
165 uint64_t allsyncw:1;
166 /* R/W If set, no stores merge, and all stores reach
167 * the coherent bus in order. */
168 uint64_t nomerge:1;
169 /* R/W Selects the bit in the counter used for DID
170 * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
171 * 214. Actual time-out is between 1x and 2x this
172 * interval. For example, with DIDTTO=3, expiration
173 * interval is between 16K and 32K. */
174 uint64_t didtto:2;
175 /* R/W If set, the (mem) CSR clock never turns off. */
176 uint64_t csrckalwys:1;
177 /* R/W If set, mclk never turns off. */
178 uint64_t mclkalwys:1;
179 /* R/W Selects the bit in the counter used for write
180 * buffer flush time-outs (WBFLT+11) is the bit
181 * position in an internal counter used to determine
182 * expiration. The write buffer expires between 1x and
183 * 2x this interval. For example, with WBFLT = 0, a
184 * write buffer expires between 2K and 4K cycles after
185 * the write buffer entry is allocated. */
186 uint64_t wbfltime:3;
187 /* R/W If set, do not put Istream in the L2 cache. */
188 uint64_t istrnol2:1;
189 /* R/W The write buffer threshold. */
190 uint64_t wbthresh:4;
191 /* Reserved */
192 uint64_t reserved2:2;
193 /* R/W If set, CVMSEG is available for loads/stores in
194 * kernel/debug mode. */
195 uint64_t cvmsegenak:1;
196 /* R/W If set, CVMSEG is available for loads/stores in
197 * supervisor mode. */
198 uint64_t cvmsegenas:1;
199 /* R/W If set, CVMSEG is available for loads/stores in
200 * user mode. */
201 uint64_t cvmsegenau:1;
202 /* R/W Size of local memory in cache blocks, 54 (6912
203 * bytes) is max legal value. */
204 uint64_t lmemsz:6;
205 } s;
206};
207
208struct octeon_cf_data {
209 unsigned long base_region_bias;
210 unsigned int base_region; /* The chip select region used by CF */
211 int is16bit; /* 0 - 8bit, !0 - 16bit */
212 int dma_engine; /* -1 for no DMA */
213};
214
215extern void octeon_write_lcd(const char *s);
216extern void octeon_check_cpu_bist(void);
217extern int octeon_get_boot_debug_flag(void);
218extern int octeon_get_boot_uart(void);
219
220struct uart_port;
221extern unsigned int octeon_serial_in(struct uart_port *, int);
222extern void octeon_serial_out(struct uart_port *, int, int);
223
224/**
225 * Write a 32bit value to the Octeon NPI register space
226 *
227 * @address: Address to write to
228 * @val: Value to write
229 */
230static inline void octeon_npi_write32(uint64_t address, uint32_t val)
231{
232 cvmx_write64_uint32(address ^ 4, val);
233 cvmx_read64_uint32(address ^ 4);
234}
235
236
237/**
238 * Read a 32bit value from the Octeon NPI register space
239 *
240 * @address: Address to read
241 * Returns The result
242 */
243static inline uint32_t octeon_npi_read32(uint64_t address)
244{
245 return cvmx_read64_uint32(address ^ 4);
246}
247
248#endif /* __ASM_OCTEON_OCTEON_H */
diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h
index 18ee58e39445..0f926aa0cb47 100644
--- a/arch/mips/include/asm/processor.h
+++ b/arch/mips/include/asm/processor.h
@@ -118,6 +118,60 @@ union mips_watch_reg_state {
118 struct mips3264_watch_reg_state mips3264; 118 struct mips3264_watch_reg_state mips3264;
119}; 119};
120 120
121#ifdef CONFIG_CPU_CAVIUM_OCTEON
122
123struct octeon_cop2_state {
124 /* DMFC2 rt, 0x0201 */
125 unsigned long cop2_crc_iv;
126 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
127 unsigned long cop2_crc_length;
128 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
129 unsigned long cop2_crc_poly;
130 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
131 unsigned long cop2_llm_dat[2];
132 /* DMFC2 rt, 0x0084 */
133 unsigned long cop2_3des_iv;
134 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
135 unsigned long cop2_3des_key[3];
136 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
137 unsigned long cop2_3des_result;
138 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
139 unsigned long cop2_aes_inp0;
140 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
141 unsigned long cop2_aes_iv[2];
142 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
143 * rt, 0x0107 */
144 unsigned long cop2_aes_key[4];
145 /* DMFC2 rt, 0x0110 */
146 unsigned long cop2_aes_keylen;
147 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
148 unsigned long cop2_aes_result[2];
149 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
150 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
151 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
152 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
153 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
154 unsigned long cop2_hsh_datw[15];
155 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
156 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
157 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
158 unsigned long cop2_hsh_ivw[8];
159 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
160 unsigned long cop2_gfm_mult[2];
161 /* DMFC2 rt, 0x025E - Pass2 */
162 unsigned long cop2_gfm_poly;
163 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
164 unsigned long cop2_gfm_result[2];
165};
166#define INIT_OCTEON_COP2 {0,}
167
168struct octeon_cvmseg_state {
169 unsigned long cvmseg[CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE]
170 [cpu_dcache_line_size() / sizeof(unsigned long)];
171};
172
173#endif
174
121typedef struct { 175typedef struct {
122 unsigned long seg; 176 unsigned long seg;
123} mm_segment_t; 177} mm_segment_t;
@@ -160,6 +214,10 @@ struct thread_struct {
160 unsigned long trap_no; 214 unsigned long trap_no;
161 unsigned long irix_trampoline; /* Wheee... */ 215 unsigned long irix_trampoline; /* Wheee... */
162 unsigned long irix_oldctx; 216 unsigned long irix_oldctx;
217#ifdef CONFIG_CPU_CAVIUM_OCTEON
218 struct octeon_cop2_state cp2 __attribute__ ((__aligned__(128)));
219 struct octeon_cvmseg_state cvmseg __attribute__ ((__aligned__(128)));
220#endif
163 struct mips_abi *abi; 221 struct mips_abi *abi;
164}; 222};
165 223
@@ -171,6 +229,13 @@ struct thread_struct {
171#define FPAFF_INIT 229#define FPAFF_INIT
172#endif /* CONFIG_MIPS_MT_FPAFF */ 230#endif /* CONFIG_MIPS_MT_FPAFF */
173 231
232#ifdef CONFIG_CPU_CAVIUM_OCTEON
233#define OCTEON_INIT \
234 .cp2 = INIT_OCTEON_COP2,
235#else
236#define OCTEON_INIT
237#endif /* CONFIG_CPU_CAVIUM_OCTEON */
238
174#define INIT_THREAD { \ 239#define INIT_THREAD { \
175 /* \ 240 /* \
176 * Saved main processor registers \ 241 * Saved main processor registers \
@@ -221,6 +286,10 @@ struct thread_struct {
221 .trap_no = 0, \ 286 .trap_no = 0, \
222 .irix_trampoline = 0, \ 287 .irix_trampoline = 0, \
223 .irix_oldctx = 0, \ 288 .irix_oldctx = 0, \
289 /* \
290 * Cavium Octeon specifics (null if not Octeon) \
291 */ \
292 OCTEON_INIT \
224} 293}
225 294
226struct task_struct; 295struct task_struct;
diff --git a/arch/mips/include/asm/ptrace.h b/arch/mips/include/asm/ptrace.h
index c2c8bac43307..1f30d16d4669 100644
--- a/arch/mips/include/asm/ptrace.h
+++ b/arch/mips/include/asm/ptrace.h
@@ -48,6 +48,10 @@ struct pt_regs {
48#ifdef CONFIG_MIPS_MT_SMTC 48#ifdef CONFIG_MIPS_MT_SMTC
49 unsigned long cp0_tcstatus; 49 unsigned long cp0_tcstatus;
50#endif /* CONFIG_MIPS_MT_SMTC */ 50#endif /* CONFIG_MIPS_MT_SMTC */
51#ifdef CONFIG_CPU_CAVIUM_OCTEON
52 unsigned long long mpl[3]; /* MTM{0,1,2} */
53 unsigned long long mtp[3]; /* MTP{0,1,2} */
54#endif
51} __attribute__ ((aligned (8))); 55} __attribute__ ((aligned (8)));
52 56
53/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */ 57/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 86557b5d1b3f..40e5ef1d4d26 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -37,6 +37,9 @@ extern int __cpu_logical_map[NR_CPUS];
37 37
38#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */ 38#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */
39#define SMP_CALL_FUNCTION 0x2 39#define SMP_CALL_FUNCTION 0x2
40/* Octeon - Tell another core to flush its icache */
41#define SMP_ICACHE_FLUSH 0x4
42
40 43
41extern void asmlinkage smp_bootstrap(void); 44extern void asmlinkage smp_bootstrap(void);
42 45
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 4c37c4e5f72e..db0fa7b5aeaf 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -194,6 +194,19 @@
194 LONG_S $31, PT_R31(sp) 194 LONG_S $31, PT_R31(sp)
195 ori $28, sp, _THREAD_MASK 195 ori $28, sp, _THREAD_MASK
196 xori $28, _THREAD_MASK 196 xori $28, _THREAD_MASK
197#ifdef CONFIG_CPU_CAVIUM_OCTEON
198 .set mips64
199 pref 0, 0($28) /* Prefetch the current pointer */
200 pref 0, PT_R31(sp) /* Prefetch the $31(ra) */
201 /* The Octeon multiplier state is affected by general multiply
202 instructions. It must be saved before and kernel code might
203 corrupt it */
204 jal octeon_mult_save
205 LONG_L v1, 0($28) /* Load the current pointer */
206 /* Restore $31(ra) that was changed by the jal */
207 LONG_L ra, PT_R31(sp)
208 pref 0, 0(v1) /* Prefetch the current thread */
209#endif
197 .set pop 210 .set pop
198 .endm 211 .endm
199 212
@@ -324,6 +337,10 @@
324 DVPE 5 # dvpe a1 337 DVPE 5 # dvpe a1
325 jal mips_ihb 338 jal mips_ihb
326#endif /* CONFIG_MIPS_MT_SMTC */ 339#endif /* CONFIG_MIPS_MT_SMTC */
340#ifdef CONFIG_CPU_CAVIUM_OCTEON
341 /* Restore the Octeon multiplier state */
342 jal octeon_mult_restore
343#endif
327 mfc0 a0, CP0_STATUS 344 mfc0 a0, CP0_STATUS
328 ori a0, STATMASK 345 ori a0, STATMASK
329 xori a0, STATMASK 346 xori a0, STATMASK
diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h
index 9601ea950542..38a30d2ee959 100644
--- a/arch/mips/include/asm/time.h
+++ b/arch/mips/include/asm/time.h
@@ -50,27 +50,35 @@ extern int (*perf_irq)(void);
50/* 50/*
51 * Initialize the calling CPU's compare interrupt as clockevent device 51 * Initialize the calling CPU's compare interrupt as clockevent device
52 */ 52 */
53#ifdef CONFIG_CEVT_R4K 53#ifdef CONFIG_CEVT_R4K_LIB
54extern int mips_clockevent_init(void);
55extern unsigned int __weak get_c0_compare_int(void); 54extern unsigned int __weak get_c0_compare_int(void);
56#else 55extern int r4k_clockevent_init(void);
56#endif
57
57static inline int mips_clockevent_init(void) 58static inline int mips_clockevent_init(void)
58{ 59{
60#ifdef CONFIG_CEVT_R4K
61 return r4k_clockevent_init();
62#else
59 return -ENXIO; 63 return -ENXIO;
60}
61#endif 64#endif
65}
62 66
63/* 67/*
64 * Initialize the count register as a clocksource 68 * Initialize the count register as a clocksource
65 */ 69 */
66#ifdef CONFIG_CSRC_R4K 70#ifdef CONFIG_CSRC_R4K_LIB
67extern int init_mips_clocksource(void); 71extern int init_r4k_clocksource(void);
68#else 72#endif
73
69static inline int init_mips_clocksource(void) 74static inline int init_mips_clocksource(void)
70{ 75{
76#ifdef CONFIG_CSRC_R4K
77 return init_r4k_clocksource();
78#else
71 return 0; 79 return 0;
72}
73#endif 80#endif
81}
74 82
75extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock); 83extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock);
76extern void clockevent_set_clock(struct clock_event_device *cd, 84extern void clockevent_set_clock(struct clock_event_device *cd,
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index b1372c27f136..e96122159928 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -9,7 +9,7 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
9 time.o topology.o traps.o unaligned.o watch.o 9 time.o topology.o traps.o unaligned.o watch.o
10 10
11obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o 11obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
12obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o 12obj-$(CONFIG_CEVT_R4K_LIB) += cevt-r4k.o
13obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o 13obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o
14obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o 14obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o
15obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o 15obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
@@ -17,7 +17,7 @@ obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
17obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o 17obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
18obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o 18obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
19obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o 19obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
20obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o 20obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o
21obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o 21obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
22obj-$(CONFIG_SYNC_R4K) += sync-r4k.o 22obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
23 23
@@ -43,6 +43,7 @@ obj-$(CONFIG_CPU_SB1) += r4k_fpu.o r4k_switch.o
43obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o 43obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
44obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o 44obj-$(CONFIG_CPU_TX49XX) += r4k_fpu.o r4k_switch.o
45obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o 45obj-$(CONFIG_CPU_VR41XX) += r4k_fpu.o r4k_switch.o
46obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
46 47
47obj-$(CONFIG_SMP) += smp.o 48obj-$(CONFIG_SMP) += smp.o
48obj-$(CONFIG_SMP_UP) += smp-up.o 49obj-$(CONFIG_SMP_UP) += smp-up.o
diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c
index 72942226fcdd..c901c22d7ad0 100644
--- a/arch/mips/kernel/asm-offsets.c
+++ b/arch/mips/kernel/asm-offsets.c
@@ -64,6 +64,10 @@ void output_ptreg_defines(void)
64#ifdef CONFIG_MIPS_MT_SMTC 64#ifdef CONFIG_MIPS_MT_SMTC
65 OFFSET(PT_TCSTATUS, pt_regs, cp0_tcstatus); 65 OFFSET(PT_TCSTATUS, pt_regs, cp0_tcstatus);
66#endif /* CONFIG_MIPS_MT_SMTC */ 66#endif /* CONFIG_MIPS_MT_SMTC */
67#ifdef CONFIG_CPU_CAVIUM_OCTEON
68 OFFSET(PT_MPL, pt_regs, mpl);
69 OFFSET(PT_MTP, pt_regs, mtp);
70#endif /* CONFIG_CPU_CAVIUM_OCTEON */
67 DEFINE(PT_SIZE, sizeof(struct pt_regs)); 71 DEFINE(PT_SIZE, sizeof(struct pt_regs));
68 BLANK(); 72 BLANK();
69} 73}
@@ -295,3 +299,30 @@ void output_irq_cpustat_t_defines(void)
295 DEFINE(IC_IRQ_CPUSTAT_T, sizeof(irq_cpustat_t)); 299 DEFINE(IC_IRQ_CPUSTAT_T, sizeof(irq_cpustat_t));
296 BLANK(); 300 BLANK();
297} 301}
302
303#ifdef CONFIG_CPU_CAVIUM_OCTEON
304void output_octeon_cop2_state_defines(void)
305{
306 COMMENT("Octeon specific octeon_cop2_state offsets.");
307 OFFSET(OCTEON_CP2_CRC_IV, octeon_cop2_state, cop2_crc_iv);
308 OFFSET(OCTEON_CP2_CRC_LENGTH, octeon_cop2_state, cop2_crc_length);
309 OFFSET(OCTEON_CP2_CRC_POLY, octeon_cop2_state, cop2_crc_poly);
310 OFFSET(OCTEON_CP2_LLM_DAT, octeon_cop2_state, cop2_llm_dat);
311 OFFSET(OCTEON_CP2_3DES_IV, octeon_cop2_state, cop2_3des_iv);
312 OFFSET(OCTEON_CP2_3DES_KEY, octeon_cop2_state, cop2_3des_key);
313 OFFSET(OCTEON_CP2_3DES_RESULT, octeon_cop2_state, cop2_3des_result);
314 OFFSET(OCTEON_CP2_AES_INP0, octeon_cop2_state, cop2_aes_inp0);
315 OFFSET(OCTEON_CP2_AES_IV, octeon_cop2_state, cop2_aes_iv);
316 OFFSET(OCTEON_CP2_AES_KEY, octeon_cop2_state, cop2_aes_key);
317 OFFSET(OCTEON_CP2_AES_KEYLEN, octeon_cop2_state, cop2_aes_keylen);
318 OFFSET(OCTEON_CP2_AES_RESULT, octeon_cop2_state, cop2_aes_result);
319 OFFSET(OCTEON_CP2_GFM_MULT, octeon_cop2_state, cop2_gfm_mult);
320 OFFSET(OCTEON_CP2_GFM_POLY, octeon_cop2_state, cop2_gfm_poly);
321 OFFSET(OCTEON_CP2_GFM_RESULT, octeon_cop2_state, cop2_gfm_result);
322 OFFSET(OCTEON_CP2_HSH_DATW, octeon_cop2_state, cop2_hsh_datw);
323 OFFSET(OCTEON_CP2_HSH_IVW, octeon_cop2_state, cop2_hsh_ivw);
324 OFFSET(THREAD_CP2, task_struct, thread.cp2);
325 OFFSET(THREAD_CVMSEG, task_struct, thread.cvmseg.cvmseg);
326 BLANK();
327}
328#endif
diff --git a/arch/mips/kernel/branch.c b/arch/mips/kernel/branch.c
index 6b5df8bfab85..0176ed015c89 100644
--- a/arch/mips/kernel/branch.c
+++ b/arch/mips/kernel/branch.c
@@ -205,6 +205,39 @@ int __compute_return_epc(struct pt_regs *regs)
205 break; 205 break;
206 } 206 }
207 break; 207 break;
208#ifdef CONFIG_CPU_CAVIUM_OCTEON
209 case lwc2_op: /* This is bbit0 on Octeon */
210 if ((regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
211 == 0)
212 epc = epc + 4 + (insn.i_format.simmediate << 2);
213 else
214 epc += 8;
215 regs->cp0_epc = epc;
216 break;
217 case ldc2_op: /* This is bbit032 on Octeon */
218 if ((regs->regs[insn.i_format.rs] &
219 (1ull<<(insn.i_format.rt+32))) == 0)
220 epc = epc + 4 + (insn.i_format.simmediate << 2);
221 else
222 epc += 8;
223 regs->cp0_epc = epc;
224 break;
225 case swc2_op: /* This is bbit1 on Octeon */
226 if (regs->regs[insn.i_format.rs] & (1ull<<insn.i_format.rt))
227 epc = epc + 4 + (insn.i_format.simmediate << 2);
228 else
229 epc += 8;
230 regs->cp0_epc = epc;
231 break;
232 case sdc2_op: /* This is bbit132 on Octeon */
233 if (regs->regs[insn.i_format.rs] &
234 (1ull<<(insn.i_format.rt+32)))
235 epc = epc + 4 + (insn.i_format.simmediate << 2);
236 else
237 epc += 8;
238 regs->cp0_epc = epc;
239 break;
240#endif
208 } 241 }
209 242
210 return 0; 243 return 0;
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index e1ec83b68031..0015e442572b 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -160,7 +160,7 @@ int c0_compare_int_usable(void)
160 160
161#ifndef CONFIG_MIPS_MT_SMTC 161#ifndef CONFIG_MIPS_MT_SMTC
162 162
163int __cpuinit mips_clockevent_init(void) 163int __cpuinit r4k_clockevent_init(void)
164{ 164{
165 uint64_t mips_freq = mips_hpt_frequency; 165 uint64_t mips_freq = mips_hpt_frequency;
166 unsigned int cpu = smp_processor_id(); 166 unsigned int cpu = smp_processor_id();
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index c9207b5fd923..a7162a4484cf 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -96,6 +96,9 @@ int allow_au1k_wait;
96 96
97static void au1k_wait(void) 97static void au1k_wait(void)
98{ 98{
99 if (!allow_au1k_wait)
100 return;
101
99 /* using the wait instruction makes CP0 counter unusable */ 102 /* using the wait instruction makes CP0 counter unusable */
100 __asm__(" .set mips3 \n" 103 __asm__(" .set mips3 \n"
101 " cache 0x14, 0(%0) \n" 104 " cache 0x14, 0(%0) \n"
@@ -154,6 +157,7 @@ void __init check_wait(void)
154 case CPU_25KF: 157 case CPU_25KF:
155 case CPU_PR4450: 158 case CPU_PR4450:
156 case CPU_BCM3302: 159 case CPU_BCM3302:
160 case CPU_CAVIUM_OCTEON:
157 cpu_wait = r4k_wait; 161 cpu_wait = r4k_wait;
158 break; 162 break;
159 163
@@ -185,8 +189,7 @@ void __init check_wait(void)
185 case CPU_AU1200: 189 case CPU_AU1200:
186 case CPU_AU1210: 190 case CPU_AU1210:
187 case CPU_AU1250: 191 case CPU_AU1250:
188 if (allow_au1k_wait) 192 cpu_wait = au1k_wait;
189 cpu_wait = au1k_wait;
190 break; 193 break;
191 case CPU_20KC: 194 case CPU_20KC:
192 /* 195 /*
@@ -875,6 +878,27 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
875 } 878 }
876} 879}
877 880
881static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
882{
883 decode_configs(c);
884 switch (c->processor_id & 0xff00) {
885 case PRID_IMP_CAVIUM_CN38XX:
886 case PRID_IMP_CAVIUM_CN31XX:
887 case PRID_IMP_CAVIUM_CN30XX:
888 case PRID_IMP_CAVIUM_CN58XX:
889 case PRID_IMP_CAVIUM_CN56XX:
890 case PRID_IMP_CAVIUM_CN50XX:
891 case PRID_IMP_CAVIUM_CN52XX:
892 c->cputype = CPU_CAVIUM_OCTEON;
893 __cpu_name[cpu] = "Cavium Octeon";
894 break;
895 default:
896 printk(KERN_INFO "Unknown Octeon chip!\n");
897 c->cputype = CPU_UNKNOWN;
898 break;
899 }
900}
901
878const char *__cpu_name[NR_CPUS]; 902const char *__cpu_name[NR_CPUS];
879 903
880__cpuinit void cpu_probe(void) 904__cpuinit void cpu_probe(void)
@@ -909,6 +933,9 @@ __cpuinit void cpu_probe(void)
909 case PRID_COMP_NXP: 933 case PRID_COMP_NXP:
910 cpu_probe_nxp(c, cpu); 934 cpu_probe_nxp(c, cpu);
911 break; 935 break;
936 case PRID_COMP_CAVIUM:
937 cpu_probe_cavium(c, cpu);
938 break;
912 } 939 }
913 940
914 BUG_ON(!__cpu_name[cpu]); 941 BUG_ON(!__cpu_name[cpu]);
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
index 74fb74583b4e..f1a2893931ed 100644
--- a/arch/mips/kernel/csrc-r4k.c
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -22,7 +22,7 @@ static struct clocksource clocksource_mips = {
22 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 22 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
23}; 23};
24 24
25int __init init_mips_clocksource(void) 25int __init init_r4k_clocksource(void)
26{ 26{
27 if (!cpu_has_counter || !mips_hpt_frequency) 27 if (!cpu_has_counter || !mips_hpt_frequency)
28 return -ENXIO; 28 return -ENXIO;
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index 757d48f0d80f..fb6f73148df2 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -385,10 +385,14 @@ NESTED(nmi_handler, PT_SIZE, sp)
385 .endm 385 .endm
386 386
387 .macro __build_clear_fpe 387 .macro __build_clear_fpe
388 .set push
389 /* gas fails to assemble cfc1 for some archs (octeon).*/ \
390 .set mips1
388 cfc1 a1, fcr31 391 cfc1 a1, fcr31
389 li a2, ~(0x3f << 12) 392 li a2, ~(0x3f << 12)
390 and a2, a1 393 and a2, a1
391 ctc1 a2, fcr31 394 ctc1 a2, fcr31
395 .set pop
392 TRACE_IRQS_ON 396 TRACE_IRQS_ON
393 STI 397 STI
394 .endm 398 .endm
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 4b4007b3083a..a0ff2b66e22b 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -111,6 +111,7 @@ int show_interrupts(struct seq_file *p, void *v)
111 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); 111 seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]);
112#endif 112#endif
113 seq_printf(p, " %14s", irq_desc[i].chip->name); 113 seq_printf(p, " %14s", irq_desc[i].chip->name);
114 seq_printf(p, "-%-8s", irq_desc[i].name);
114 seq_printf(p, " %s", action->name); 115 seq_printf(p, " %s", action->name);
115 116
116 for (action=action->next; action; action = action->next) 117 for (action=action->next; action; action = action->next)
diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S
new file mode 100644
index 000000000000..d52389672b06
--- /dev/null
+++ b/arch/mips/kernel/octeon_switch.S
@@ -0,0 +1,506 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
7 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
8 * Copyright (C) 1994, 1995, 1996, by Andreas Busse
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Copyright (C) 2000 MIPS Technologies, Inc.
11 * written by Carsten Langgaard, carstenl@mips.com
12 */
13#include <asm/asm.h>
14#include <asm/cachectl.h>
15#include <asm/fpregdef.h>
16#include <asm/mipsregs.h>
17#include <asm/asm-offsets.h>
18#include <asm/page.h>
19#include <asm/pgtable-bits.h>
20#include <asm/regdef.h>
21#include <asm/stackframe.h>
22#include <asm/thread_info.h>
23
24#include <asm/asmmacro.h>
25
26/*
27 * Offset to the current process status flags, the first 32 bytes of the
28 * stack are not used.
29 */
30#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
31
32/*
33 * task_struct *resume(task_struct *prev, task_struct *next,
34 * struct thread_info *next_ti)
35 */
36 .align 7
37 LEAF(resume)
38 .set arch=octeon
39#ifndef CONFIG_CPU_HAS_LLSC
40 sw zero, ll_bit
41#endif
42 mfc0 t1, CP0_STATUS
43 LONG_S t1, THREAD_STATUS(a0)
44 cpu_save_nonscratch a0
45 LONG_S ra, THREAD_REG31(a0)
46
47 /* check if we need to save COP2 registers */
48 PTR_L t2, TASK_THREAD_INFO(a0)
49 LONG_L t0, ST_OFF(t2)
50 bbit0 t0, 30, 1f
51
52 /* Disable COP2 in the stored process state */
53 li t1, ST0_CU2
54 xor t0, t1
55 LONG_S t0, ST_OFF(t2)
56
57 /* Enable COP2 so we can save it */
58 mfc0 t0, CP0_STATUS
59 or t0, t1
60 mtc0 t0, CP0_STATUS
61
62 /* Save COP2 */
63 daddu a0, THREAD_CP2
64 jal octeon_cop2_save
65 dsubu a0, THREAD_CP2
66
67 /* Disable COP2 now that we are done */
68 mfc0 t0, CP0_STATUS
69 li t1, ST0_CU2
70 xor t0, t1
71 mtc0 t0, CP0_STATUS
72
731:
74#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
75 /* Check if we need to store CVMSEG state */
76 mfc0 t0, $11,7 /* CvmMemCtl */
77 bbit0 t0, 6, 3f /* Is user access enabled? */
78
79 /* Store the CVMSEG state */
80 /* Extract the size of CVMSEG */
81 andi t0, 0x3f
82 /* Multiply * (cache line size/sizeof(long)/2) */
83 sll t0, 7-LONGLOG-1
84 li t1, -32768 /* Base address of CVMSEG */
85 LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
86 synciobdma
872:
88 .set noreorder
89 LONG_L t8, 0(t1) /* Load from CVMSEG */
90 subu t0, 1 /* Decrement loop var */
91 LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
92 LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
93 LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */
94 LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */
95 bnez t0, 2b /* Loop until we've copied it all */
96 LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
97 .set reorder
98
99 /* Disable access to CVMSEG */
100 mfc0 t0, $11,7 /* CvmMemCtl */
101 xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
102 mtc0 t0, $11,7 /* CvmMemCtl */
103#endif
1043:
105 /*
106 * The order of restoring the registers takes care of the race
107 * updating $28, $29 and kernelsp without disabling ints.
108 */
109 move $28, a2
110 cpu_restore_nonscratch a1
111
112#if (_THREAD_SIZE - 32) < 0x8000
113 PTR_ADDIU t0, $28, _THREAD_SIZE - 32
114#else
115 PTR_LI t0, _THREAD_SIZE - 32
116 PTR_ADDU t0, $28
117#endif
118 set_saved_sp t0, t1, t2
119
120 mfc0 t1, CP0_STATUS /* Do we really need this? */
121 li a3, 0xff01
122 and t1, a3
123 LONG_L a2, THREAD_STATUS(a1)
124 nor a3, $0, a3
125 and a2, a3
126 or a2, t1
127 mtc0 a2, CP0_STATUS
128 move v0, a0
129 jr ra
130 END(resume)
131
132/*
133 * void octeon_cop2_save(struct octeon_cop2_state *a0)
134 */
135 .align 7
136 LEAF(octeon_cop2_save)
137
138 dmfc0 t9, $9,7 /* CvmCtl register. */
139
140 /* Save the COP2 CRC state */
141 dmfc2 t0, 0x0201
142 dmfc2 t1, 0x0202
143 dmfc2 t2, 0x0200
144 sd t0, OCTEON_CP2_CRC_IV(a0)
145 sd t1, OCTEON_CP2_CRC_LENGTH(a0)
146 sd t2, OCTEON_CP2_CRC_POLY(a0)
147 /* Skip next instructions if CvmCtl[NODFA_CP2] set */
148 bbit1 t9, 28, 1f
149
150 /* Save the LLM state */
151 dmfc2 t0, 0x0402
152 dmfc2 t1, 0x040A
153 sd t0, OCTEON_CP2_LLM_DAT(a0)
154 sd t1, OCTEON_CP2_LLM_DAT+8(a0)
155
1561: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
157
158 /* Save the COP2 crypto state */
159 /* this part is mostly common to both pass 1 and later revisions */
160 dmfc2 t0, 0x0084
161 dmfc2 t1, 0x0080
162 dmfc2 t2, 0x0081
163 dmfc2 t3, 0x0082
164 sd t0, OCTEON_CP2_3DES_IV(a0)
165 dmfc2 t0, 0x0088
166 sd t1, OCTEON_CP2_3DES_KEY(a0)
167 dmfc2 t1, 0x0111 /* only necessary for pass 1 */
168 sd t2, OCTEON_CP2_3DES_KEY+8(a0)
169 dmfc2 t2, 0x0102
170 sd t3, OCTEON_CP2_3DES_KEY+16(a0)
171 dmfc2 t3, 0x0103
172 sd t0, OCTEON_CP2_3DES_RESULT(a0)
173 dmfc2 t0, 0x0104
174 sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */
175 dmfc2 t1, 0x0105
176 sd t2, OCTEON_CP2_AES_IV(a0)
177 dmfc2 t2, 0x0106
178 sd t3, OCTEON_CP2_AES_IV+8(a0)
179 dmfc2 t3, 0x0107
180 sd t0, OCTEON_CP2_AES_KEY(a0)
181 dmfc2 t0, 0x0110
182 sd t1, OCTEON_CP2_AES_KEY+8(a0)
183 dmfc2 t1, 0x0100
184 sd t2, OCTEON_CP2_AES_KEY+16(a0)
185 dmfc2 t2, 0x0101
186 sd t3, OCTEON_CP2_AES_KEY+24(a0)
187 mfc0 t3, $15,0 /* Get the processor ID register */
188 sd t0, OCTEON_CP2_AES_KEYLEN(a0)
189 li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
190 sd t1, OCTEON_CP2_AES_RESULT(a0)
191 sd t2, OCTEON_CP2_AES_RESULT+8(a0)
192 /* Skip to the Pass1 version of the remainder of the COP2 state */
193 beq t3, t0, 2f
194
195 /* the non-pass1 state when !CvmCtl[NOCRYPTO] */
196 dmfc2 t1, 0x0240
197 dmfc2 t2, 0x0241
198 dmfc2 t3, 0x0242
199 dmfc2 t0, 0x0243
200 sd t1, OCTEON_CP2_HSH_DATW(a0)
201 dmfc2 t1, 0x0244
202 sd t2, OCTEON_CP2_HSH_DATW+8(a0)
203 dmfc2 t2, 0x0245
204 sd t3, OCTEON_CP2_HSH_DATW+16(a0)
205 dmfc2 t3, 0x0246
206 sd t0, OCTEON_CP2_HSH_DATW+24(a0)
207 dmfc2 t0, 0x0247
208 sd t1, OCTEON_CP2_HSH_DATW+32(a0)
209 dmfc2 t1, 0x0248
210 sd t2, OCTEON_CP2_HSH_DATW+40(a0)
211 dmfc2 t2, 0x0249
212 sd t3, OCTEON_CP2_HSH_DATW+48(a0)
213 dmfc2 t3, 0x024A
214 sd t0, OCTEON_CP2_HSH_DATW+56(a0)
215 dmfc2 t0, 0x024B
216 sd t1, OCTEON_CP2_HSH_DATW+64(a0)
217 dmfc2 t1, 0x024C
218 sd t2, OCTEON_CP2_HSH_DATW+72(a0)
219 dmfc2 t2, 0x024D
220 sd t3, OCTEON_CP2_HSH_DATW+80(a0)
221 dmfc2 t3, 0x024E
222 sd t0, OCTEON_CP2_HSH_DATW+88(a0)
223 dmfc2 t0, 0x0250
224 sd t1, OCTEON_CP2_HSH_DATW+96(a0)
225 dmfc2 t1, 0x0251
226 sd t2, OCTEON_CP2_HSH_DATW+104(a0)
227 dmfc2 t2, 0x0252
228 sd t3, OCTEON_CP2_HSH_DATW+112(a0)
229 dmfc2 t3, 0x0253
230 sd t0, OCTEON_CP2_HSH_IVW(a0)
231 dmfc2 t0, 0x0254
232 sd t1, OCTEON_CP2_HSH_IVW+8(a0)
233 dmfc2 t1, 0x0255
234 sd t2, OCTEON_CP2_HSH_IVW+16(a0)
235 dmfc2 t2, 0x0256
236 sd t3, OCTEON_CP2_HSH_IVW+24(a0)
237 dmfc2 t3, 0x0257
238 sd t0, OCTEON_CP2_HSH_IVW+32(a0)
239 dmfc2 t0, 0x0258
240 sd t1, OCTEON_CP2_HSH_IVW+40(a0)
241 dmfc2 t1, 0x0259
242 sd t2, OCTEON_CP2_HSH_IVW+48(a0)
243 dmfc2 t2, 0x025E
244 sd t3, OCTEON_CP2_HSH_IVW+56(a0)
245 dmfc2 t3, 0x025A
246 sd t0, OCTEON_CP2_GFM_MULT(a0)
247 dmfc2 t0, 0x025B
248 sd t1, OCTEON_CP2_GFM_MULT+8(a0)
249 sd t2, OCTEON_CP2_GFM_POLY(a0)
250 sd t3, OCTEON_CP2_GFM_RESULT(a0)
251 sd t0, OCTEON_CP2_GFM_RESULT+8(a0)
252 jr ra
253
2542: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
255 dmfc2 t3, 0x0040
256 dmfc2 t0, 0x0041
257 dmfc2 t1, 0x0042
258 dmfc2 t2, 0x0043
259 sd t3, OCTEON_CP2_HSH_DATW(a0)
260 dmfc2 t3, 0x0044
261 sd t0, OCTEON_CP2_HSH_DATW+8(a0)
262 dmfc2 t0, 0x0045
263 sd t1, OCTEON_CP2_HSH_DATW+16(a0)
264 dmfc2 t1, 0x0046
265 sd t2, OCTEON_CP2_HSH_DATW+24(a0)
266 dmfc2 t2, 0x0048
267 sd t3, OCTEON_CP2_HSH_DATW+32(a0)
268 dmfc2 t3, 0x0049
269 sd t0, OCTEON_CP2_HSH_DATW+40(a0)
270 dmfc2 t0, 0x004A
271 sd t1, OCTEON_CP2_HSH_DATW+48(a0)
272 sd t2, OCTEON_CP2_HSH_IVW(a0)
273 sd t3, OCTEON_CP2_HSH_IVW+8(a0)
274 sd t0, OCTEON_CP2_HSH_IVW+16(a0)
275
2763: /* pass 1 or CvmCtl[NOCRYPTO] set */
277 jr ra
278 END(octeon_cop2_save)
279
280/*
281 * void octeon_cop2_restore(struct octeon_cop2_state *a0)
282 */
283 .align 7
284 .set push
285 .set noreorder
286 LEAF(octeon_cop2_restore)
287 /* First cache line was prefetched before the call */
288 pref 4, 128(a0)
289 dmfc0 t9, $9,7 /* CvmCtl register. */
290
291 pref 4, 256(a0)
292 ld t0, OCTEON_CP2_CRC_IV(a0)
293 pref 4, 384(a0)
294 ld t1, OCTEON_CP2_CRC_LENGTH(a0)
295 ld t2, OCTEON_CP2_CRC_POLY(a0)
296
297 /* Restore the COP2 CRC state */
298 dmtc2 t0, 0x0201
299 dmtc2 t1, 0x1202
300 bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
301 dmtc2 t2, 0x4200
302
303 /* Restore the LLM state */
304 ld t0, OCTEON_CP2_LLM_DAT(a0)
305 ld t1, OCTEON_CP2_LLM_DAT+8(a0)
306 dmtc2 t0, 0x0402
307 dmtc2 t1, 0x040A
308
3092:
310 bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
311 nop
312
313 /* Restore the COP2 crypto state common to pass 1 and pass 2 */
314 ld t0, OCTEON_CP2_3DES_IV(a0)
315 ld t1, OCTEON_CP2_3DES_KEY(a0)
316 ld t2, OCTEON_CP2_3DES_KEY+8(a0)
317 dmtc2 t0, 0x0084
318 ld t0, OCTEON_CP2_3DES_KEY+16(a0)
319 dmtc2 t1, 0x0080
320 ld t1, OCTEON_CP2_3DES_RESULT(a0)
321 dmtc2 t2, 0x0081
322 ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
323 dmtc2 t0, 0x0082
324 ld t0, OCTEON_CP2_AES_IV(a0)
325 dmtc2 t1, 0x0098
326 ld t1, OCTEON_CP2_AES_IV+8(a0)
327 dmtc2 t2, 0x010A /* only really needed for pass 1 */
328 ld t2, OCTEON_CP2_AES_KEY(a0)
329 dmtc2 t0, 0x0102
330 ld t0, OCTEON_CP2_AES_KEY+8(a0)
331 dmtc2 t1, 0x0103
332 ld t1, OCTEON_CP2_AES_KEY+16(a0)
333 dmtc2 t2, 0x0104
334 ld t2, OCTEON_CP2_AES_KEY+24(a0)
335 dmtc2 t0, 0x0105
336 ld t0, OCTEON_CP2_AES_KEYLEN(a0)
337 dmtc2 t1, 0x0106
338 ld t1, OCTEON_CP2_AES_RESULT(a0)
339 dmtc2 t2, 0x0107
340 ld t2, OCTEON_CP2_AES_RESULT+8(a0)
341 mfc0 t3, $15,0 /* Get the processor ID register */
342 dmtc2 t0, 0x0110
343 li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
344 dmtc2 t1, 0x0100
345 bne t0, t3, 3f /* Skip the next stuff for non-pass1 */
346 dmtc2 t2, 0x0101
347
348 /* this code is specific for pass 1 */
349 ld t0, OCTEON_CP2_HSH_DATW(a0)
350 ld t1, OCTEON_CP2_HSH_DATW+8(a0)
351 ld t2, OCTEON_CP2_HSH_DATW+16(a0)
352 dmtc2 t0, 0x0040
353 ld t0, OCTEON_CP2_HSH_DATW+24(a0)
354 dmtc2 t1, 0x0041
355 ld t1, OCTEON_CP2_HSH_DATW+32(a0)
356 dmtc2 t2, 0x0042
357 ld t2, OCTEON_CP2_HSH_DATW+40(a0)
358 dmtc2 t0, 0x0043
359 ld t0, OCTEON_CP2_HSH_DATW+48(a0)
360 dmtc2 t1, 0x0044
361 ld t1, OCTEON_CP2_HSH_IVW(a0)
362 dmtc2 t2, 0x0045
363 ld t2, OCTEON_CP2_HSH_IVW+8(a0)
364 dmtc2 t0, 0x0046
365 ld t0, OCTEON_CP2_HSH_IVW+16(a0)
366 dmtc2 t1, 0x0048
367 dmtc2 t2, 0x0049
368 b done_restore /* unconditional branch */
369 dmtc2 t0, 0x004A
370
3713: /* this is post-pass1 code */
372 ld t2, OCTEON_CP2_HSH_DATW(a0)
373 ld t0, OCTEON_CP2_HSH_DATW+8(a0)
374 ld t1, OCTEON_CP2_HSH_DATW+16(a0)
375 dmtc2 t2, 0x0240
376 ld t2, OCTEON_CP2_HSH_DATW+24(a0)
377 dmtc2 t0, 0x0241
378 ld t0, OCTEON_CP2_HSH_DATW+32(a0)
379 dmtc2 t1, 0x0242
380 ld t1, OCTEON_CP2_HSH_DATW+40(a0)
381 dmtc2 t2, 0x0243
382 ld t2, OCTEON_CP2_HSH_DATW+48(a0)
383 dmtc2 t0, 0x0244
384 ld t0, OCTEON_CP2_HSH_DATW+56(a0)
385 dmtc2 t1, 0x0245
386 ld t1, OCTEON_CP2_HSH_DATW+64(a0)
387 dmtc2 t2, 0x0246
388 ld t2, OCTEON_CP2_HSH_DATW+72(a0)
389 dmtc2 t0, 0x0247
390 ld t0, OCTEON_CP2_HSH_DATW+80(a0)
391 dmtc2 t1, 0x0248
392 ld t1, OCTEON_CP2_HSH_DATW+88(a0)
393 dmtc2 t2, 0x0249
394 ld t2, OCTEON_CP2_HSH_DATW+96(a0)
395 dmtc2 t0, 0x024A
396 ld t0, OCTEON_CP2_HSH_DATW+104(a0)
397 dmtc2 t1, 0x024B
398 ld t1, OCTEON_CP2_HSH_DATW+112(a0)
399 dmtc2 t2, 0x024C
400 ld t2, OCTEON_CP2_HSH_IVW(a0)
401 dmtc2 t0, 0x024D
402 ld t0, OCTEON_CP2_HSH_IVW+8(a0)
403 dmtc2 t1, 0x024E
404 ld t1, OCTEON_CP2_HSH_IVW+16(a0)
405 dmtc2 t2, 0x0250
406 ld t2, OCTEON_CP2_HSH_IVW+24(a0)
407 dmtc2 t0, 0x0251
408 ld t0, OCTEON_CP2_HSH_IVW+32(a0)
409 dmtc2 t1, 0x0252
410 ld t1, OCTEON_CP2_HSH_IVW+40(a0)
411 dmtc2 t2, 0x0253
412 ld t2, OCTEON_CP2_HSH_IVW+48(a0)
413 dmtc2 t0, 0x0254
414 ld t0, OCTEON_CP2_HSH_IVW+56(a0)
415 dmtc2 t1, 0x0255
416 ld t1, OCTEON_CP2_GFM_MULT(a0)
417 dmtc2 t2, 0x0256
418 ld t2, OCTEON_CP2_GFM_MULT+8(a0)
419 dmtc2 t0, 0x0257
420 ld t0, OCTEON_CP2_GFM_POLY(a0)
421 dmtc2 t1, 0x0258
422 ld t1, OCTEON_CP2_GFM_RESULT(a0)
423 dmtc2 t2, 0x0259
424 ld t2, OCTEON_CP2_GFM_RESULT+8(a0)
425 dmtc2 t0, 0x025E
426 dmtc2 t1, 0x025A
427 dmtc2 t2, 0x025B
428
429done_restore:
430 jr ra
431 nop
432 END(octeon_cop2_restore)
433 .set pop
434
435/*
436 * void octeon_mult_save()
437 * sp is assumed to point to a struct pt_regs
438 *
439 * NOTE: This is called in SAVE_SOME in stackframe.h. It can only
440 * safely modify k0 and k1.
441 */
442 .align 7
443 .set push
444 .set noreorder
445 LEAF(octeon_mult_save)
446 dmfc0 k0, $9,7 /* CvmCtl register. */
447 bbit1 k0, 27, 1f /* Skip CvmCtl[NOMUL] */
448 nop
449
450 /* Save the multiplier state */
451 v3mulu k0, $0, $0
452 v3mulu k1, $0, $0
453 sd k0, PT_MTP(sp) /* PT_MTP has P0 */
454 v3mulu k0, $0, $0
455 sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */
456 ori k1, $0, 1
457 v3mulu k1, k1, $0
458 sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */
459 v3mulu k0, $0, $0
460 sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */
461 v3mulu k1, $0, $0
462 sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */
463 jr ra
464 sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */
465
4661: /* Resume here if CvmCtl[NOMUL] */
467 jr ra
468 END(octeon_mult_save)
469 .set pop
470
471/*
472 * void octeon_mult_restore()
473 * sp is assumed to point to a struct pt_regs
474 *
475 * NOTE: This is called in RESTORE_SOME in stackframe.h.
476 */
477 .align 7
478 .set push
479 .set noreorder
480 LEAF(octeon_mult_restore)
481 dmfc0 k1, $9,7 /* CvmCtl register. */
482 ld v0, PT_MPL(sp) /* MPL0 */
483 ld v1, PT_MPL+8(sp) /* MPL1 */
484 ld k0, PT_MPL+16(sp) /* MPL2 */
485 bbit1 k1, 27, 1f /* Skip CvmCtl[NOMUL] */
486 /* Normally falls through, so no time wasted here */
487 nop
488
489 /* Restore the multiplier state */
490 ld k1, PT_MTP+16(sp) /* P2 */
491 MTM0 v0 /* MPL0 */
492 ld v0, PT_MTP+8(sp) /* P1 */
493 MTM1 v1 /* MPL1 */
494 ld v1, PT_MTP(sp) /* P0 */
495 MTM2 k0 /* MPL2 */
496 MTP2 k1 /* P2 */
497 MTP1 v0 /* P1 */
498 jr ra
499 MTP0 v1 /* P0 */
500
5011: /* Resume here if CvmCtl[NOMUL] */
502 jr ra
503 nop
504 END(octeon_mult_restore)
505 .set pop
506
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index 1ca34104e593..c4f9ac17474a 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -49,19 +49,6 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
49 int ret; 49 int ret;
50 50
51 switch (request) { 51 switch (request) {
52 /* when I and D space are separate, these will need to be fixed. */
53 case PTRACE_PEEKTEXT: /* read word at location addr. */
54 case PTRACE_PEEKDATA: {
55 unsigned int tmp;
56 int copied;
57
58 copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0);
59 ret = -EIO;
60 if (copied != sizeof(tmp))
61 break;
62 ret = put_user(tmp, (unsigned int __user *) (unsigned long) data);
63 break;
64 }
65 52
66 /* 53 /*
67 * Read 4 bytes of the other process' storage 54 * Read 4 bytes of the other process' storage
@@ -208,16 +195,6 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
208 break; 195 break;
209 } 196 }
210 197
211 /* when I and D space are separate, this will have to be fixed. */
212 case PTRACE_POKETEXT: /* write the word at location addr. */
213 case PTRACE_POKEDATA:
214 ret = 0;
215 if (access_process_vm(child, addr, &data, sizeof(data), 1)
216 == sizeof(data))
217 break;
218 ret = -EIO;
219 break;
220
221 /* 198 /*
222 * Write 4 bytes into the other process' storage 199 * Write 4 bytes into the other process' storage
223 * data is the 4 bytes that the user wants written 200 * data is the 4 bytes that the user wants written
@@ -332,50 +309,11 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
332 ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data); 309 ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data);
333 break; 310 break;
334 311
335 case PTRACE_SYSCALL: /* continue and stop at next (return from) syscall */
336 case PTRACE_CONT: { /* restart after signal. */
337 ret = -EIO;
338 if (!valid_signal(data))
339 break;
340 if (request == PTRACE_SYSCALL) {
341 set_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
342 }
343 else {
344 clear_tsk_thread_flag(child, TIF_SYSCALL_TRACE);
345 }
346 child->exit_code = data;
347 wake_up_process(child);
348 ret = 0;
349 break;
350 }
351
352 /*
353 * make the child exit. Best I can do is send it a sigkill.
354 * perhaps it should be put in the status that it wants to
355 * exit.
356 */
357 case PTRACE_KILL:
358 ret = 0;
359 if (child->exit_state == EXIT_ZOMBIE) /* already dead */
360 break;
361 child->exit_code = SIGKILL;
362 wake_up_process(child);
363 break;
364
365 case PTRACE_GET_THREAD_AREA: 312 case PTRACE_GET_THREAD_AREA:
366 ret = put_user(task_thread_info(child)->tp_value, 313 ret = put_user(task_thread_info(child)->tp_value,
367 (unsigned int __user *) (unsigned long) data); 314 (unsigned int __user *) (unsigned long) data);
368 break; 315 break;
369 316
370 case PTRACE_DETACH: /* detach a process that was attached. */
371 ret = ptrace_detach(child, data);
372 break;
373
374 case PTRACE_GETEVENTMSG:
375 ret = put_user(child->ptrace_message,
376 (unsigned int __user *) (unsigned long) data);
377 break;
378
379 case PTRACE_GET_THREAD_AREA_3264: 317 case PTRACE_GET_THREAD_AREA_3264:
380 ret = put_user(task_thread_info(child)->tp_value, 318 ret = put_user(task_thread_info(child)->tp_value,
381 (unsigned long __user *) (unsigned long) data); 319 (unsigned long __user *) (unsigned long) data);
@@ -392,7 +330,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
392 break; 330 break;
393 331
394 default: 332 default:
395 ret = ptrace_request(child, request, addr, data); 333 ret = compat_ptrace_request(child, request, addr, data);
396 break; 334 break;
397 } 335 }
398out: 336out:
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 353056110f2b..f6083c6bfaa4 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -47,6 +47,7 @@
47#include <asm/mmu_context.h> 47#include <asm/mmu_context.h>
48#include <asm/types.h> 48#include <asm/types.h>
49#include <asm/stacktrace.h> 49#include <asm/stacktrace.h>
50#include <asm/irq.h>
50 51
51extern void check_wait(void); 52extern void check_wait(void);
52extern asmlinkage void r4k_wait(void); 53extern asmlinkage void r4k_wait(void);
@@ -78,6 +79,10 @@ extern asmlinkage void handle_reserved(void);
78extern int fpu_emulator_cop1Handler(struct pt_regs *xcp, 79extern int fpu_emulator_cop1Handler(struct pt_regs *xcp,
79 struct mips_fpu_struct *ctx, int has_fpu); 80 struct mips_fpu_struct *ctx, int has_fpu);
80 81
82#ifdef CONFIG_CPU_CAVIUM_OCTEON
83extern asmlinkage void octeon_cop2_restore(struct octeon_cop2_state *task);
84#endif
85
81void (*board_be_init)(void); 86void (*board_be_init)(void);
82int (*board_be_handler)(struct pt_regs *regs, int is_fixup); 87int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
83void (*board_nmi_handler_setup)(void); 88void (*board_nmi_handler_setup)(void);
@@ -860,6 +865,7 @@ asmlinkage void do_cpu(struct pt_regs *regs)
860 unsigned int opcode; 865 unsigned int opcode;
861 unsigned int cpid; 866 unsigned int cpid;
862 int status; 867 int status;
868 unsigned long __maybe_unused flags;
863 869
864 die_if_kernel("do_cpu invoked from kernel context!", regs); 870 die_if_kernel("do_cpu invoked from kernel context!", regs);
865 871
@@ -915,6 +921,17 @@ asmlinkage void do_cpu(struct pt_regs *regs)
915 return; 921 return;
916 922
917 case 2: 923 case 2:
924#ifdef CONFIG_CPU_CAVIUM_OCTEON
925 prefetch(&current->thread.cp2);
926 local_irq_save(flags);
927 KSTK_STATUS(current) |= ST0_CU2;
928 status = read_c0_status();
929 write_c0_status(status | ST0_CU2);
930 octeon_cop2_restore(&(current->thread.cp2));
931 write_c0_status(status & ~ST0_CU2);
932 local_irq_restore(flags);
933 return;
934#endif
918 case 3: 935 case 3:
919 break; 936 break;
920 } 937 }
@@ -1488,6 +1505,10 @@ void __cpuinit per_cpu_trap_init(void)
1488 write_c0_hwrena(enable); 1505 write_c0_hwrena(enable);
1489 } 1506 }
1490 1507
1508#ifdef CONFIG_CPU_CAVIUM_OCTEON
1509 write_c0_hwrena(0xc000000f); /* Octeon has register 30 and 31 */
1510#endif
1511
1491#ifdef CONFIG_MIPS_MT_SMTC 1512#ifdef CONFIG_MIPS_MT_SMTC
1492 if (!secondaryTC) { 1513 if (!secondaryTC) {
1493#endif /* CONFIG_MIPS_MT_SMTC */ 1514#endif /* CONFIG_MIPS_MT_SMTC */
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index dbcf6511b74e..c13c7ad2cdae 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CPU_SB1) += dump_tlb.o
27obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o 27obj-$(CONFIG_CPU_TX39XX) += r3k_dump_tlb.o
28obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o 28obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o
29obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o 29obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o
30obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o
30 31
31# libgcc-style stuff needed in the kernel 32# libgcc-style stuff needed in the kernel
32obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o 33obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index 95ba32b5b720..d7ec95522292 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -27,6 +27,7 @@ obj-$(CONFIG_CPU_SB1) += c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
27obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o 27obj-$(CONFIG_CPU_TX39XX) += c-tx39.o tlb-r3k.o
28obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o 28obj-$(CONFIG_CPU_TX49XX) += c-r4k.o cex-gen.o tlb-r4k.o
29obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o 29obj-$(CONFIG_CPU_VR41XX) += c-r4k.o cex-gen.o tlb-r4k.o
30obj-$(CONFIG_CPU_CAVIUM_OCTEON) += c-octeon.o cex-oct.o tlb-r4k.o
30 31
31obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o 32obj-$(CONFIG_IP22_CPU_SCACHE) += sc-ip22.o
32obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o 33obj-$(CONFIG_R5000_CPU_SCACHE) += sc-r5k.o
diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c
new file mode 100644
index 000000000000..44d01a0a8490
--- /dev/null
+++ b/arch/mips/mm/c-octeon.c
@@ -0,0 +1,307 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2005-2007 Cavium Networks
7 */
8#include <linux/init.h>
9#include <linux/kernel.h>
10#include <linux/sched.h>
11#include <linux/mm.h>
12#include <linux/bitops.h>
13#include <linux/cpu.h>
14#include <linux/io.h>
15
16#include <asm/bcache.h>
17#include <asm/bootinfo.h>
18#include <asm/cacheops.h>
19#include <asm/cpu-features.h>
20#include <asm/page.h>
21#include <asm/pgtable.h>
22#include <asm/r4kcache.h>
23#include <asm/system.h>
24#include <asm/mmu_context.h>
25#include <asm/war.h>
26
27#include <asm/octeon/octeon.h>
28
29unsigned long long cache_err_dcache[NR_CPUS];
30
31/**
32 * Octeon automatically flushes the dcache on tlb changes, so
33 * from Linux's viewpoint it acts much like a physically
34 * tagged cache. No flushing is needed
35 *
36 */
37static void octeon_flush_data_cache_page(unsigned long addr)
38{
39 /* Nothing to do */
40}
41
42static inline void octeon_local_flush_icache(void)
43{
44 asm volatile ("synci 0($0)");
45}
46
47/*
48 * Flush local I-cache for the specified range.
49 */
50static void local_octeon_flush_icache_range(unsigned long start,
51 unsigned long end)
52{
53 octeon_local_flush_icache();
54}
55
56/**
57 * Flush caches as necessary for all cores affected by a
58 * vma. If no vma is supplied, all cores are flushed.
59 *
60 * @vma: VMA to flush or NULL to flush all icaches.
61 */
62static void octeon_flush_icache_all_cores(struct vm_area_struct *vma)
63{
64 extern void octeon_send_ipi_single(int cpu, unsigned int action);
65#ifdef CONFIG_SMP
66 int cpu;
67 cpumask_t mask;
68#endif
69
70 mb();
71 octeon_local_flush_icache();
72#ifdef CONFIG_SMP
73 preempt_disable();
74 cpu = smp_processor_id();
75
76 /*
77 * If we have a vma structure, we only need to worry about
78 * cores it has been used on
79 */
80 if (vma)
81 mask = vma->vm_mm->cpu_vm_mask;
82 else
83 mask = cpu_online_map;
84 cpu_clear(cpu, mask);
85 for_each_cpu_mask(cpu, mask)
86 octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH);
87
88 preempt_enable();
89#endif
90}
91
92
93/**
94 * Called to flush the icache on all cores
95 */
96static void octeon_flush_icache_all(void)
97{
98 octeon_flush_icache_all_cores(NULL);
99}
100
101
102/**
103 * Called to flush all memory associated with a memory
104 * context.
105 *
106 * @mm: Memory context to flush
107 */
108static void octeon_flush_cache_mm(struct mm_struct *mm)
109{
110 /*
111 * According to the R4K version of this file, CPUs without
112 * dcache aliases don't need to do anything here
113 */
114}
115
116
117/**
118 * Flush a range of kernel addresses out of the icache
119 *
120 */
121static void octeon_flush_icache_range(unsigned long start, unsigned long end)
122{
123 octeon_flush_icache_all_cores(NULL);
124}
125
126
127/**
128 * Flush the icache for a trampoline. These are used for interrupt
129 * and exception hooking.
130 *
131 * @addr: Address to flush
132 */
133static void octeon_flush_cache_sigtramp(unsigned long addr)
134{
135 struct vm_area_struct *vma;
136
137 vma = find_vma(current->mm, addr);
138 octeon_flush_icache_all_cores(vma);
139}
140
141
142/**
143 * Flush a range out of a vma
144 *
145 * @vma: VMA to flush
146 * @start:
147 * @end:
148 */
149static void octeon_flush_cache_range(struct vm_area_struct *vma,
150 unsigned long start, unsigned long end)
151{
152 if (vma->vm_flags & VM_EXEC)
153 octeon_flush_icache_all_cores(vma);
154}
155
156
157/**
158 * Flush a specific page of a vma
159 *
160 * @vma: VMA to flush page for
161 * @page: Page to flush
162 * @pfn:
163 */
164static void octeon_flush_cache_page(struct vm_area_struct *vma,
165 unsigned long page, unsigned long pfn)
166{
167 if (vma->vm_flags & VM_EXEC)
168 octeon_flush_icache_all_cores(vma);
169}
170
171
172/**
173 * Probe Octeon's caches
174 *
175 */
176static void __devinit probe_octeon(void)
177{
178 unsigned long icache_size;
179 unsigned long dcache_size;
180 unsigned int config1;
181 struct cpuinfo_mips *c = &current_cpu_data;
182
183 switch (c->cputype) {
184 case CPU_CAVIUM_OCTEON:
185 config1 = read_c0_config1();
186 c->icache.linesz = 2 << ((config1 >> 19) & 7);
187 c->icache.sets = 64 << ((config1 >> 22) & 7);
188 c->icache.ways = 1 + ((config1 >> 16) & 7);
189 c->icache.flags |= MIPS_CACHE_VTAG;
190 icache_size =
191 c->icache.sets * c->icache.ways * c->icache.linesz;
192 c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
193 c->dcache.linesz = 128;
194 if (OCTEON_IS_MODEL(OCTEON_CN3XXX))
195 c->dcache.sets = 1; /* CN3XXX has one Dcache set */
196 else
197 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
198 c->dcache.ways = 64;
199 dcache_size =
200 c->dcache.sets * c->dcache.ways * c->dcache.linesz;
201 c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1;
202 c->options |= MIPS_CPU_PREFETCH;
203 break;
204
205 default:
206 panic("Unsupported Cavium Networks CPU type\n");
207 break;
208 }
209
210 /* compute a couple of other cache variables */
211 c->icache.waysize = icache_size / c->icache.ways;
212 c->dcache.waysize = dcache_size / c->dcache.ways;
213
214 c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways);
215 c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways);
216
217 if (smp_processor_id() == 0) {
218 pr_notice("Primary instruction cache %ldkB, %s, %d way, "
219 "%d sets, linesize %d bytes.\n",
220 icache_size >> 10,
221 cpu_has_vtag_icache ?
222 "virtually tagged" : "physically tagged",
223 c->icache.ways, c->icache.sets, c->icache.linesz);
224
225 pr_notice("Primary data cache %ldkB, %d-way, %d sets, "
226 "linesize %d bytes.\n",
227 dcache_size >> 10, c->dcache.ways,
228 c->dcache.sets, c->dcache.linesz);
229 }
230}
231
232
233/**
234 * Setup the Octeon cache flush routines
235 *
236 */
237void __devinit octeon_cache_init(void)
238{
239 extern unsigned long ebase;
240 extern char except_vec2_octeon;
241
242 memcpy((void *)(ebase + 0x100), &except_vec2_octeon, 0x80);
243 octeon_flush_cache_sigtramp(ebase + 0x100);
244
245 probe_octeon();
246
247 shm_align_mask = PAGE_SIZE - 1;
248
249 flush_cache_all = octeon_flush_icache_all;
250 __flush_cache_all = octeon_flush_icache_all;
251 flush_cache_mm = octeon_flush_cache_mm;
252 flush_cache_page = octeon_flush_cache_page;
253 flush_cache_range = octeon_flush_cache_range;
254 flush_cache_sigtramp = octeon_flush_cache_sigtramp;
255 flush_icache_all = octeon_flush_icache_all;
256 flush_data_cache_page = octeon_flush_data_cache_page;
257 flush_icache_range = octeon_flush_icache_range;
258 local_flush_icache_range = local_octeon_flush_icache_range;
259
260 build_clear_page();
261 build_copy_page();
262}
263
264/**
265 * Handle a cache error exception
266 */
267
268static void cache_parity_error_octeon(int non_recoverable)
269{
270 unsigned long coreid = cvmx_get_core_num();
271 uint64_t icache_err = read_octeon_c0_icacheerr();
272
273 pr_err("Cache error exception:\n");
274 pr_err("cp0_errorepc == %lx\n", read_c0_errorepc());
275 if (icache_err & 1) {
276 pr_err("CacheErr (Icache) == %llx\n",
277 (unsigned long long)icache_err);
278 write_octeon_c0_icacheerr(0);
279 }
280 if (cache_err_dcache[coreid] & 1) {
281 pr_err("CacheErr (Dcache) == %llx\n",
282 (unsigned long long)cache_err_dcache[coreid]);
283 cache_err_dcache[coreid] = 0;
284 }
285
286 if (non_recoverable)
287 panic("Can't handle cache error: nested exception");
288}
289
290/**
291 * Called when the the exception is not recoverable
292 */
293
294asmlinkage void cache_parity_error_octeon_recoverable(void)
295{
296 cache_parity_error_octeon(0);
297}
298
299/**
300 * Called when the the exception is recoverable
301 */
302
303asmlinkage void cache_parity_error_octeon_non_recoverable(void)
304{
305 cache_parity_error_octeon(1);
306}
307
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index 1eb7c71e3d6a..98ad0a82c29e 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -182,6 +182,12 @@ void __devinit cpu_cache_init(void)
182 tx39_cache_init(); 182 tx39_cache_init();
183 } 183 }
184 184
185 if (cpu_has_octeon_cache) {
186 extern void __weak octeon_cache_init(void);
187
188 octeon_cache_init();
189 }
190
185 setup_protection_map(); 191 setup_protection_map();
186} 192}
187 193
diff --git a/arch/mips/mm/cex-oct.S b/arch/mips/mm/cex-oct.S
new file mode 100644
index 000000000000..3db8553fcd34
--- /dev/null
+++ b/arch/mips/mm/cex-oct.S
@@ -0,0 +1,70 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2006 Cavium Networks
7 * Cache error handler
8 */
9
10#include <asm/asm.h>
11#include <asm/regdef.h>
12#include <asm/mipsregs.h>
13#include <asm/stackframe.h>
14
15/*
16 * Handle cache error. Indicate to the second level handler whether
17 * the exception is recoverable.
18 */
19 LEAF(except_vec2_octeon)
20
21 .set push
22 .set mips64r2
23 .set noreorder
24 .set noat
25
26
27 /* due to an errata we need to read the COP0 CacheErr (Dcache)
28 * before any cache/DRAM access */
29
30 rdhwr k0, $0 /* get core_id */
31 PTR_LA k1, cache_err_dcache
32 sll k0, k0, 3
33 PTR_ADDU k1, k0, k1 /* k1 = &cache_err_dcache[core_id] */
34
35 dmfc0 k0, CP0_CACHEERR, 1
36 sd k0, (k1)
37 dmtc0 $0, CP0_CACHEERR, 1
38
39 /* check whether this is a nested exception */
40 mfc0 k1, CP0_STATUS
41 andi k1, k1, ST0_EXL
42 beqz k1, 1f
43 nop
44 j cache_parity_error_octeon_non_recoverable
45 nop
46
47 /* exception is recoverable */
481: j handle_cache_err
49 nop
50
51 .set pop
52 END(except_vec2_octeon)
53
54 /* We need to jump to handle_cache_err so that the previous handler
55 * can fit within 0x80 bytes. We also move from 0xFFFFFFFFAXXXXXXX
56 * space (uncached) to the 0xFFFFFFFF8XXXXXXX space (cached). */
57 LEAF(handle_cache_err)
58 .set push
59 .set noreorder
60 .set noat
61
62 SAVE_ALL
63 KMODE
64 jal cache_parity_error_octeon_recoverable
65 nop
66 j ret_from_exception
67 nop
68
69 .set pop
70 END(handle_cache_err)
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index e6708b3ad343..546e6977d4ff 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -111,7 +111,7 @@ EXPORT_SYMBOL(dma_alloc_coherent);
111void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr, 111void dma_free_noncoherent(struct device *dev, size_t size, void *vaddr,
112 dma_addr_t dma_handle) 112 dma_addr_t dma_handle)
113{ 113{
114 plat_unmap_dma_mem(dma_handle); 114 plat_unmap_dma_mem(dev, dma_handle);
115 free_pages((unsigned long) vaddr, get_order(size)); 115 free_pages((unsigned long) vaddr, get_order(size));
116} 116}
117 117
@@ -122,7 +122,7 @@ void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
122{ 122{
123 unsigned long addr = (unsigned long) vaddr; 123 unsigned long addr = (unsigned long) vaddr;
124 124
125 plat_unmap_dma_mem(dma_handle); 125 plat_unmap_dma_mem(dev, dma_handle);
126 126
127 if (!plat_device_is_coherent(dev)) 127 if (!plat_device_is_coherent(dev))
128 addr = CAC_ADDR(addr); 128 addr = CAC_ADDR(addr);
@@ -173,7 +173,7 @@ void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
173 __dma_sync(dma_addr_to_virt(dma_addr), size, 173 __dma_sync(dma_addr_to_virt(dma_addr), size,
174 direction); 174 direction);
175 175
176 plat_unmap_dma_mem(dma_addr); 176 plat_unmap_dma_mem(dev, dma_addr);
177} 177}
178 178
179EXPORT_SYMBOL(dma_unmap_single); 179EXPORT_SYMBOL(dma_unmap_single);
@@ -229,7 +229,7 @@ void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
229 dma_cache_wback_inv(addr, size); 229 dma_cache_wback_inv(addr, size);
230 } 230 }
231 231
232 plat_unmap_dma_mem(dma_address); 232 plat_unmap_dma_mem(dev, dma_address);
233} 233}
234 234
235EXPORT_SYMBOL(dma_unmap_page); 235EXPORT_SYMBOL(dma_unmap_page);
@@ -249,7 +249,7 @@ void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
249 if (addr) 249 if (addr)
250 __dma_sync(addr, sg->length, direction); 250 __dma_sync(addr, sg->length, direction);
251 } 251 }
252 plat_unmap_dma_mem(sg->dma_address); 252 plat_unmap_dma_mem(dev, sg->dma_address);
253 } 253 }
254} 254}
255 255
@@ -275,6 +275,7 @@ void dma_sync_single_for_device(struct device *dev, dma_addr_t dma_handle,
275{ 275{
276 BUG_ON(direction == DMA_NONE); 276 BUG_ON(direction == DMA_NONE);
277 277
278 plat_extra_sync_for_device(dev);
278 if (!plat_device_is_coherent(dev)) { 279 if (!plat_device_is_coherent(dev)) {
279 unsigned long addr; 280 unsigned long addr;
280 281
@@ -305,6 +306,7 @@ void dma_sync_single_range_for_device(struct device *dev, dma_addr_t dma_handle,
305{ 306{
306 BUG_ON(direction == DMA_NONE); 307 BUG_ON(direction == DMA_NONE);
307 308
309 plat_extra_sync_for_device(dev);
308 if (!plat_device_is_coherent(dev)) { 310 if (!plat_device_is_coherent(dev)) {
309 unsigned long addr; 311 unsigned long addr;
310 312
@@ -351,22 +353,14 @@ EXPORT_SYMBOL(dma_sync_sg_for_device);
351 353
352int dma_mapping_error(struct device *dev, dma_addr_t dma_addr) 354int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
353{ 355{
354 return 0; 356 return plat_dma_mapping_error(dev, dma_addr);
355} 357}
356 358
357EXPORT_SYMBOL(dma_mapping_error); 359EXPORT_SYMBOL(dma_mapping_error);
358 360
359int dma_supported(struct device *dev, u64 mask) 361int dma_supported(struct device *dev, u64 mask)
360{ 362{
361 /* 363 return plat_dma_supported(dev, mask);
362 * we fall back to GFP_DMA when the mask isn't all 1s,
363 * so we can't guarantee allocations that must be
364 * within a tighter range than GFP_DMA..
365 */
366 if (mask < DMA_BIT_MASK(24))
367 return 0;
368
369 return 1;
370} 364}
371 365
372EXPORT_SYMBOL(dma_supported); 366EXPORT_SYMBOL(dma_supported);
@@ -383,6 +377,7 @@ void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
383{ 377{
384 BUG_ON(direction == DMA_NONE); 378 BUG_ON(direction == DMA_NONE);
385 379
380 plat_extra_sync_for_device(dev);
386 if (!plat_device_is_coherent(dev)) 381 if (!plat_device_is_coherent(dev))
387 __dma_sync((unsigned long)vaddr, size, direction); 382 __dma_sync((unsigned long)vaddr, size, direction);
388} 383}
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c
index 5ce2fa745626..9619f66e531e 100644
--- a/arch/mips/mm/tlb-r4k.c
+++ b/arch/mips/mm/tlb-r4k.c
@@ -478,7 +478,10 @@ void __cpuinit tlb_init(void)
478 probe_tlb(config); 478 probe_tlb(config);
479 write_c0_pagemask(PM_DEFAULT_MASK); 479 write_c0_pagemask(PM_DEFAULT_MASK);
480 write_c0_wired(0); 480 write_c0_wired(0);
481 write_c0_framemask(0); 481 if (current_cpu_type() == CPU_R10000 ||
482 current_cpu_type() == CPU_R12000 ||
483 current_cpu_type() == CPU_R14000)
484 write_c0_framemask(0);
482 temp_tlb_entry = current_cpu_data.tlbsize - 1; 485 temp_tlb_entry = current_cpu_data.tlbsize - 1;
483 486
484 /* From this point on the ARC firmware is dead. */ 487 /* From this point on the ARC firmware is dead. */
diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 979cf9197282..42942038d0fd 100644
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -317,6 +317,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l,
317 case CPU_BCM3302: 317 case CPU_BCM3302:
318 case CPU_BCM4710: 318 case CPU_BCM4710:
319 case CPU_LOONGSON2: 319 case CPU_LOONGSON2:
320 case CPU_CAVIUM_OCTEON:
320 if (m4kc_tlbp_war()) 321 if (m4kc_tlbp_war())
321 uasm_i_nop(p); 322 uasm_i_nop(p);
322 tlbw(p); 323 tlbw(p);
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-23 23:57:59 -0500