diff options
author | Brice Goglin <brice@myri.com> | 2008-08-06 10:14:43 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@redhat.com> | 2008-08-07 01:54:44 -0400 |
commit | 6a4c4ad2f0aa331324649579649c5d9064893079 (patch) | |
tree | b43bbb0f4cb31831a6087c2fbb0f9c066d44f6ba | |
parent | 0967d61ea0d8e8a7826bd8949cd93dd1e829ac55 (diff) |
myri10ge: update firmware headers
Update myri10ge firmware headers.
Signed-off-by: Brice Goglin <brice@myri.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
-rw-r--r-- | drivers/net/myri10ge/myri10ge_mcp.h | 52 | ||||
-rw-r--r-- | drivers/net/myri10ge/myri10ge_mcp_gen_header.h | 2 |
2 files changed, 48 insertions, 6 deletions
diff --git a/drivers/net/myri10ge/myri10ge_mcp.h b/drivers/net/myri10ge/myri10ge_mcp.h index fdbeeee07372..993721090777 100644 --- a/drivers/net/myri10ge/myri10ge_mcp.h +++ b/drivers/net/myri10ge/myri10ge_mcp.h | |||
@@ -101,6 +101,8 @@ struct mcp_kreq_ether_recv { | |||
101 | #define MXGEFW_ETH_SEND_3 0x2c0000 | 101 | #define MXGEFW_ETH_SEND_3 0x2c0000 |
102 | #define MXGEFW_ETH_RECV_SMALL 0x300000 | 102 | #define MXGEFW_ETH_RECV_SMALL 0x300000 |
103 | #define MXGEFW_ETH_RECV_BIG 0x340000 | 103 | #define MXGEFW_ETH_RECV_BIG 0x340000 |
104 | #define MXGEFW_ETH_SEND_GO 0x380000 | ||
105 | #define MXGEFW_ETH_SEND_STOP 0x3C0000 | ||
104 | 106 | ||
105 | #define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) | 107 | #define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) |
106 | #define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) | 108 | #define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) |
@@ -120,6 +122,11 @@ enum myri10ge_mcp_cmd_type { | |||
120 | * MXGEFW_CMD_RESET is issued */ | 122 | * MXGEFW_CMD_RESET is issued */ |
121 | 123 | ||
122 | MXGEFW_CMD_SET_INTRQ_DMA, | 124 | MXGEFW_CMD_SET_INTRQ_DMA, |
125 | /* data0 = LSW of the host address | ||
126 | * data1 = MSW of the host address | ||
127 | * data2 = slice number if multiple slices are used | ||
128 | */ | ||
129 | |||
123 | MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */ | 130 | MXGEFW_CMD_SET_BIG_BUFFER_SIZE, /* in bytes, power of 2 */ |
124 | MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */ | 131 | MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, /* in bytes */ |
125 | 132 | ||
@@ -129,6 +136,8 @@ enum myri10ge_mcp_cmd_type { | |||
129 | MXGEFW_CMD_GET_SEND_OFFSET, | 136 | MXGEFW_CMD_GET_SEND_OFFSET, |
130 | MXGEFW_CMD_GET_SMALL_RX_OFFSET, | 137 | MXGEFW_CMD_GET_SMALL_RX_OFFSET, |
131 | MXGEFW_CMD_GET_BIG_RX_OFFSET, | 138 | MXGEFW_CMD_GET_BIG_RX_OFFSET, |
139 | /* data0 = slice number if multiple slices are used */ | ||
140 | |||
132 | MXGEFW_CMD_GET_IRQ_ACK_OFFSET, | 141 | MXGEFW_CMD_GET_IRQ_ACK_OFFSET, |
133 | MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, | 142 | MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET, |
134 | 143 | ||
@@ -200,7 +209,12 @@ enum myri10ge_mcp_cmd_type { | |||
200 | MXGEFW_CMD_SET_STATS_DMA_V2, | 209 | MXGEFW_CMD_SET_STATS_DMA_V2, |
201 | /* data0, data1 = bus addr, | 210 | /* data0, data1 = bus addr, |
202 | * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows | 211 | * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows |
203 | * adding new stuff to mcp_irq_data without changing the ABI */ | 212 | * adding new stuff to mcp_irq_data without changing the ABI |
213 | * | ||
214 | * If multiple slices are used, data2 contains both the size of the | ||
215 | * structure (in the lower 16 bits) and the slice number | ||
216 | * (in the upper 16 bits). | ||
217 | */ | ||
204 | 218 | ||
205 | MXGEFW_CMD_UNALIGNED_TEST, | 219 | MXGEFW_CMD_UNALIGNED_TEST, |
206 | /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned | 220 | /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned |
@@ -222,13 +236,18 @@ enum myri10ge_mcp_cmd_type { | |||
222 | MXGEFW_CMD_GET_MAX_RSS_QUEUES, | 236 | MXGEFW_CMD_GET_MAX_RSS_QUEUES, |
223 | MXGEFW_CMD_ENABLE_RSS_QUEUES, | 237 | MXGEFW_CMD_ENABLE_RSS_QUEUES, |
224 | /* data0 = number of slices n (0, 1, ..., n-1) to enable | 238 | /* data0 = number of slices n (0, 1, ..., n-1) to enable |
225 | * data1 = interrupt mode. | 239 | * data1 = interrupt mode | use of multiple transmit queues. |
226 | * 0=share one INTx/MSI, 1=use one MSI-X per queue. | 240 | * 0=share one INTx/MSI. |
241 | * 1=use one MSI-X per queue. | ||
227 | * If all queues share one interrupt, the driver must have set | 242 | * If all queues share one interrupt, the driver must have set |
228 | * RSS_SHARED_INTERRUPT_DMA before enabling queues. | 243 | * RSS_SHARED_INTERRUPT_DMA before enabling queues. |
244 | * 2=enable both receive and send queues. | ||
245 | * Without this bit set, only one send queue (slice 0's send queue) | ||
246 | * is enabled. The receive queues are always enabled. | ||
229 | */ | 247 | */ |
230 | #define MXGEFW_SLICE_INTR_MODE_SHARED 0 | 248 | #define MXGEFW_SLICE_INTR_MODE_SHARED 0x0 |
231 | #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 1 | 249 | #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1 |
250 | #define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2 | ||
232 | 251 | ||
233 | MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET, | 252 | MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET, |
234 | MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA, | 253 | MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA, |
@@ -250,10 +269,13 @@ enum myri10ge_mcp_cmd_type { | |||
250 | * 2: TCP_IPV4 (required by RSS) | 269 | * 2: TCP_IPV4 (required by RSS) |
251 | * 3: IPV4 | TCP_IPV4 (required by RSS) | 270 | * 3: IPV4 | TCP_IPV4 (required by RSS) |
252 | * 4: source port | 271 | * 4: source port |
272 | * 5: source port + destination port | ||
253 | */ | 273 | */ |
254 | #define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 | 274 | #define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 |
255 | #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 | 275 | #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 |
256 | #define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 | 276 | #define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 |
277 | #define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5 | ||
278 | #define MXGEFW_RSS_HASH_TYPE_MAX 0x5 | ||
257 | 279 | ||
258 | MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE, | 280 | MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE, |
259 | /* Return data = the max. size of the entire headers of a IPv6 TSO packet. | 281 | /* Return data = the max. size of the entire headers of a IPv6 TSO packet. |
@@ -329,6 +351,20 @@ enum myri10ge_mcp_cmd_type { | |||
329 | 351 | ||
330 | MXGEFW_CMD_GET_DCA_OFFSET, | 352 | MXGEFW_CMD_GET_DCA_OFFSET, |
331 | /* offset of dca control for WDMAs */ | 353 | /* offset of dca control for WDMAs */ |
354 | |||
355 | /* VMWare NetQueue commands */ | ||
356 | MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE, | ||
357 | MXGEFW_CMD_NETQ_ADD_FILTER, | ||
358 | /* data0 = filter_id << 16 | queue << 8 | type */ | ||
359 | /* data1 = MS4 of MAC Addr */ | ||
360 | /* data2 = LS2_MAC << 16 | VLAN_tag */ | ||
361 | MXGEFW_CMD_NETQ_DEL_FILTER, | ||
362 | /* data0 = filter_id */ | ||
363 | MXGEFW_CMD_NETQ_QUERY1, | ||
364 | MXGEFW_CMD_NETQ_QUERY2, | ||
365 | MXGEFW_CMD_NETQ_QUERY3, | ||
366 | MXGEFW_CMD_NETQ_QUERY4, | ||
367 | |||
332 | }; | 368 | }; |
333 | 369 | ||
334 | enum myri10ge_mcp_cmd_status { | 370 | enum myri10ge_mcp_cmd_status { |
@@ -381,4 +417,10 @@ struct mcp_irq_data { | |||
381 | u8 valid; | 417 | u8 valid; |
382 | }; | 418 | }; |
383 | 419 | ||
420 | /* definitions for NETQ filter type */ | ||
421 | #define MXGEFW_NETQ_FILTERTYPE_NONE 0 | ||
422 | #define MXGEFW_NETQ_FILTERTYPE_MACADDR 1 | ||
423 | #define MXGEFW_NETQ_FILTERTYPE_VLAN 2 | ||
424 | #define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3 | ||
425 | |||
384 | #endif /* __MYRI10GE_MCP_H__ */ | 426 | #endif /* __MYRI10GE_MCP_H__ */ |
diff --git a/drivers/net/myri10ge/myri10ge_mcp_gen_header.h b/drivers/net/myri10ge/myri10ge_mcp_gen_header.h index 07d65c2cbb24..a8662ea8079a 100644 --- a/drivers/net/myri10ge/myri10ge_mcp_gen_header.h +++ b/drivers/net/myri10ge/myri10ge_mcp_gen_header.h | |||
@@ -35,7 +35,7 @@ struct mcp_gen_header { | |||
35 | unsigned char mcp_index; | 35 | unsigned char mcp_index; |
36 | unsigned char disable_rabbit; | 36 | unsigned char disable_rabbit; |
37 | unsigned char unaligned_tlp; | 37 | unsigned char unaligned_tlp; |
38 | unsigned char pad1; | 38 | unsigned char pcie_link_algo; |
39 | unsigned counters_addr; | 39 | unsigned counters_addr; |
40 | unsigned copy_block_info; /* for small mcps loaded with "lload -d" */ | 40 | unsigned copy_block_info; /* for small mcps loaded with "lload -d" */ |
41 | unsigned short handoff_id_major; /* must be equal */ | 41 | unsigned short handoff_id_major; /* must be equal */ |