diff options
author | Nicolas Ferre <nicolas.ferre@atmel.com> | 2009-11-11 17:26:35 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-11-12 10:25:57 -0500 |
commit | 431861cfab0c8613f83bac0f41dae22ff74f9bc1 (patch) | |
tree | 3bbcc466f1f21fc5becca1feb081bd46716a0540 | |
parent | 7779d7bed950a7fb1af4f540c2f82a6b81b65901 (diff) |
atmel_lcdfb: new alternate pixel clock formula
at91sam9g45 non ES lots have an alternate pixel clock calculation formula.
Introduce this one with condition on the cpu_is_xxxxx() macros.
Newer 9g45 SOC will not have good pixel clock calculation without this
fix.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: Krzysztof Helt <krzysztof.h1@wp.pl>
Cc: Haavard Skinnemoen <hskinnemoen@atmel.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
-rw-r--r-- | drivers/video/atmel_lcdfb.c | 11 |
1 files changed, 8 insertions, 3 deletions
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c index 2830ffd72976..d5e801076d33 100644 --- a/drivers/video/atmel_lcdfb.c +++ b/drivers/video/atmel_lcdfb.c | |||
@@ -484,6 +484,7 @@ static int atmel_lcdfb_set_par(struct fb_info *info) | |||
484 | unsigned long value; | 484 | unsigned long value; |
485 | unsigned long clk_value_khz; | 485 | unsigned long clk_value_khz; |
486 | unsigned long bits_per_line; | 486 | unsigned long bits_per_line; |
487 | unsigned long pix_factor = 2; | ||
487 | 488 | ||
488 | might_sleep(); | 489 | might_sleep(); |
489 | 490 | ||
@@ -516,20 +517,24 @@ static int atmel_lcdfb_set_par(struct fb_info *info) | |||
516 | /* Now, the LCDC core... */ | 517 | /* Now, the LCDC core... */ |
517 | 518 | ||
518 | /* Set pixel clock */ | 519 | /* Set pixel clock */ |
520 | if (cpu_is_at91sam9g45() && !cpu_is_at91sam9g45es()) | ||
521 | pix_factor = 1; | ||
522 | |||
519 | clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000; | 523 | clk_value_khz = clk_get_rate(sinfo->lcdc_clk) / 1000; |
520 | 524 | ||
521 | value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock)); | 525 | value = DIV_ROUND_UP(clk_value_khz, PICOS2KHZ(info->var.pixclock)); |
522 | 526 | ||
523 | if (value < 2) { | 527 | if (value < pix_factor) { |
524 | dev_notice(info->device, "Bypassing pixel clock divider\n"); | 528 | dev_notice(info->device, "Bypassing pixel clock divider\n"); |
525 | lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS); | 529 | lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, ATMEL_LCDC_BYPASS); |
526 | } else { | 530 | } else { |
527 | value = (value / 2) - 1; | 531 | value = (value / pix_factor) - 1; |
528 | dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n", | 532 | dev_dbg(info->device, " * programming CLKVAL = 0x%08lx\n", |
529 | value); | 533 | value); |
530 | lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, | 534 | lcdc_writel(sinfo, ATMEL_LCDC_LCDCON1, |
531 | value << ATMEL_LCDC_CLKVAL_OFFSET); | 535 | value << ATMEL_LCDC_CLKVAL_OFFSET); |
532 | info->var.pixclock = KHZ2PICOS(clk_value_khz / (2 * (value + 1))); | 536 | info->var.pixclock = |
537 | KHZ2PICOS(clk_value_khz / (pix_factor * (value + 1))); | ||
533 | dev_dbg(info->device, " updated pixclk: %lu KHz\n", | 538 | dev_dbg(info->device, " updated pixclk: %lu KHz\n", |
534 | PICOS2KHZ(info->var.pixclock)); | 539 | PICOS2KHZ(info->var.pixclock)); |
535 | } | 540 | } |