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authorTakashi Iwai <tiwai@suse.de>2009-12-03 00:12:02 -0500
committerDavid S. Miller <davem@davemloft.net>2009-12-11 17:54:31 -0500
commitd66f0b20b2f8eac365fadf5ca492efe4ba539446 (patch)
tree64f923924269ee0faf38ed194e5b955045d4ce2b
parentb338682dc5c20e8ff986e58407bdb6e3a3e3f0a3 (diff)
net: Add missing TST_CFG_WRITE bits around sky2_pci_write
Add missing TST_CFG_WRITE bits around sky2_pci_write*() in Optima setup routines. Without the cfg-write bits, the driver may spew endless link-up messages through qlink irq. Signed-off-by: Takashi Iwai <tiwai@suse.de> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/sky2.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 050e6b58d4f9..013c9f52ceaa 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -2152,7 +2152,9 @@ static void sky2_qlink_intr(struct sky2_hw *hw)
2152 2152
2153 /* reset PHY Link Detect */ 2153 /* reset PHY Link Detect */
2154 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4); 2154 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2155 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2155 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1); 2156 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2157 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2156 2158
2157 sky2_link_up(sky2); 2159 sky2_link_up(sky2);
2158} 2160}
@@ -3082,6 +3084,7 @@ static void sky2_reset(struct sky2_hw *hw)
3082 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE; 3084 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3083 3085
3084 /* reset PHY Link Detect */ 3086 /* reset PHY Link Detect */
3087 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3085 sky2_pci_write16(hw, PSM_CONFIG_REG4, 3088 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3086 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT); 3089 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3087 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg); 3090 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
@@ -3099,6 +3102,7 @@ static void sky2_reset(struct sky2_hw *hw)
3099 /* restore the PCIe Link Control register */ 3102 /* restore the PCIe Link Control register */
3100 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg); 3103 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3101 } 3104 }
3105 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3102 3106
3103 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */ 3107 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3104 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16)); 3108 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));