diff options
author | Luotao Fu <l.fu@pengutronix.de> | 2008-09-09 04:19:43 -0400 |
---|---|---|
committer | Sascha Hauer <s.hauer@pengutronix.de> | 2008-09-09 06:13:53 -0400 |
commit | defa8c309d280915a2e7f4451f70bcbb087088a3 (patch) | |
tree | e7c6e63db7a8e4816f5b91289aaf9741033e60e8 | |
parent | 8b0171fad1db5c9a5b315f4a11e65da45fbd6f21 (diff) |
i.MX3: Fix compiler warnings
Fix some base address declaration by adding a cast.
Signed-off-by: Luotao Fu <l.fu@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r-- | arch/arm/mach-mx3/iomux.c | 6 | ||||
-rw-r--r-- | arch/arm/plat-mxc/include/mach/clock.h | 2 | ||||
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx27.h | 1 | ||||
-rw-r--r-- | arch/arm/plat-mxc/include/mach/mx31.h | 1 |
4 files changed, 7 insertions, 3 deletions
diff --git a/arch/arm/mach-mx3/iomux.c b/arch/arm/mach-mx3/iomux.c index 3dda1fe23cbf..6e664be8cc13 100644 --- a/arch/arm/mach-mx3/iomux.c +++ b/arch/arm/mach-mx3/iomux.c | |||
@@ -43,7 +43,8 @@ static DEFINE_SPINLOCK(gpio_mux_lock); | |||
43 | */ | 43 | */ |
44 | int mxc_iomux_mode(unsigned int pin_mode) | 44 | int mxc_iomux_mode(unsigned int pin_mode) |
45 | { | 45 | { |
46 | u32 reg, field, l, mode, ret = 0; | 46 | u32 field, l, mode, ret = 0; |
47 | void __iomem *reg; | ||
47 | 48 | ||
48 | reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK); | 49 | reg = IOMUXSW_MUX_CTL + (pin_mode & IOMUX_REG_MASK); |
49 | field = pin_mode & 0x3; | 50 | field = pin_mode & 0x3; |
@@ -70,7 +71,8 @@ EXPORT_SYMBOL(mxc_iomux_mode); | |||
70 | */ | 71 | */ |
71 | void mxc_iomux_set_pad(enum iomux_pins pin, u32 config) | 72 | void mxc_iomux_set_pad(enum iomux_pins pin, u32 config) |
72 | { | 73 | { |
73 | u32 reg, field, l; | 74 | u32 field, l; |
75 | void __iomem *reg; | ||
74 | 76 | ||
75 | reg = IOMUXSW_PAD_CTL + (pin + 2) / 3; | 77 | reg = IOMUXSW_PAD_CTL + (pin + 2) / 3; |
76 | field = (pin + 2) % 3; | 78 | field = (pin + 2) % 3; |
diff --git a/arch/arm/plat-mxc/include/mach/clock.h b/arch/arm/plat-mxc/include/mach/clock.h index 24caa2b7c91d..d21f78e78819 100644 --- a/arch/arm/plat-mxc/include/mach/clock.h +++ b/arch/arm/plat-mxc/include/mach/clock.h | |||
@@ -39,7 +39,7 @@ struct clk { | |||
39 | /* Register bit position for clock's enable/disable control. */ | 39 | /* Register bit position for clock's enable/disable control. */ |
40 | u8 enable_shift; | 40 | u8 enable_shift; |
41 | /* Register address for clock's enable/disable control. */ | 41 | /* Register address for clock's enable/disable control. */ |
42 | u32 enable_reg; | 42 | void __iomem *enable_reg; |
43 | u32 flags; | 43 | u32 flags; |
44 | /* get the current clock rate (always a fresh value) */ | 44 | /* get the current clock rate (always a fresh value) */ |
45 | unsigned long (*get_rate) (struct clk *); | 45 | unsigned long (*get_rate) (struct clk *); |
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h index 212ecc246626..a86db64744a1 100644 --- a/arch/arm/plat-mxc/include/mach/mx27.h +++ b/arch/arm/plat-mxc/include/mach/mx27.h | |||
@@ -128,6 +128,7 @@ | |||
128 | * it returns 0xDEADBEEF | 128 | * it returns 0xDEADBEEF |
129 | */ | 129 | */ |
130 | #define IO_ADDRESS(x) \ | 130 | #define IO_ADDRESS(x) \ |
131 | (void __iomem *) \ | ||
131 | (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \ | 132 | (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \ |
132 | AIPI_IO_ADDRESS(x) : \ | 133 | AIPI_IO_ADDRESS(x) : \ |
133 | ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \ | 134 | ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \ |
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h index a7373e4a56cb..0536f8917bc0 100644 --- a/arch/arm/plat-mxc/include/mach/mx31.h +++ b/arch/arm/plat-mxc/include/mach/mx31.h | |||
@@ -198,6 +198,7 @@ | |||
198 | * it returns 0xDEADBEEF | 198 | * it returns 0xDEADBEEF |
199 | */ | 199 | */ |
200 | #define IO_ADDRESS(x) \ | 200 | #define IO_ADDRESS(x) \ |
201 | (void __iomem *) \ | ||
201 | (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\ | 202 | (((x >= IRAM_BASE_ADDR) && (x < (IRAM_BASE_ADDR + IRAM_SIZE))) ? IRAM_IO_ADDRESS(x):\ |
202 | ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\ | 203 | ((x >= L2CC_BASE_ADDR) && (x < (L2CC_BASE_ADDR + L2CC_SIZE))) ? L2CC_IO_ADDRESS(x):\ |
203 | ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ | 204 | ((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\ |