Merge remote branch 'nouveau/drm-nouveau-fixes' of /ssd/git/drm-nouveau-next into drm-fixes

* 'nouveau/drm-nouveau-fixes' of /ssd/git/drm-nouveau-next:
  drm/nv40: fall back to paged dma object for the moment
  drm/nouveau: fix leak of gart mm node
  drm/nouveau: fix vram page mapping when crossing page table boundaries
  drm/nv17-nv40: Fix modesetting failure when pitch == 4096px (fdo bug 35901).
  drm/nouveau: don't create accel engine objects when noaccel=1
  drm/nvc0: recognise 0xdX chipsets as NV_C0

7 files changed, 74 insertions, 59 deletions

diff --git a/drivers/gpu/drm/nouveau/nouveau_hw.c b/drivers/gpu/drm/nouveau/nouveau_hw.c
index 053edf9d2f67..ba896e54b799 100644
--- a/drivers/gpu/drm/nouveau/nouveau_hw.c
+++ b/drivers/gpu/drm/nouveau/nouveau_hw.c
@@ -900,6 +900,7 @@ nv_save_state_ext(struct drm_device *dev, int head,
         }
         /* NV11 and NV20 don't have this, they stop at 0x52. */
         if (nv_gf4_disp_arch(dev)) {
+                rd_cio_state(dev, head, regp, NV_CIO_CRE_42);
                 rd_cio_state(dev, head, regp, NV_CIO_CRE_53);
                 rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
 
@@ -1003,6 +1004,7 @@ nv_load_state_ext(struct drm_device *dev, int head,
                         nouveau_wait_eq(dev, 650000000, NV_PRMCIO_INP0__COLOR, 0x8, 0x0);
                 }
 
+                wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
                 wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
                 wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index 2960f583dc38..5ee14d216ce8 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -397,7 +397,7 @@ nouveau_mem_vram_init(struct drm_device *dev)
                 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
                         dma_bits = 40;
         } else
-        if (drm_pci_device_is_pcie(dev) &&
+        if (0 && drm_pci_device_is_pcie(dev) &&
             dev_priv->chipset  > 0x40 &&
             dev_priv->chipset != 0x45) {
                 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39)))
@@ -868,7 +868,9 @@ nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
                 nouveau_vm_unmap(&node->tmp_vma);
                 nouveau_vm_put(&node->tmp_vma);
         }
+
         mem->mm_node = NULL;
+        kfree(node);
 }
 
 static int
diff --git a/drivers/gpu/drm/nouveau/nouveau_sgdma.c b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
index c77111eca6ac..82fad914e648 100644
--- a/drivers/gpu/drm/nouveau/nouveau_sgdma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_sgdma.c
@@ -458,7 +458,7 @@ nouveau_sgdma_init(struct drm_device *dev)
                 dev_priv->gart_info.type = NOUVEAU_GART_HW;
                 dev_priv->gart_info.func = &nv50_sgdma_backend;
         } else
-        if (drm_pci_device_is_pcie(dev) &&
+        if (0 && drm_pci_device_is_pcie(dev) &&
             dev_priv->chipset > 0x40 && dev_priv->chipset != 0x45) {
                 if (nv44_graph_class(dev)) {
                         dev_priv->gart_info.func = &nv44_sgdma_backend;
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 38ea662568c1..80218887e0a0 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -371,6 +371,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
                 engine->vram.flags_valid        = nv50_vram_flags_valid;
                 break;
         case 0xC0:
+        case 0xD0:
                 engine->instmem.init            = nvc0_instmem_init;
                 engine->instmem.takedown        = nvc0_instmem_takedown;
                 engine->instmem.suspend         = nvc0_instmem_suspend;
@@ -563,68 +564,68 @@ nouveau_card_init(struct drm_device *dev)
         if (ret)
                 goto out_timer;
 
-        switch (dev_priv->card_type) {
-        case NV_04:
-                nv04_graph_create(dev);
-                break;
-        case NV_10:
-                nv10_graph_create(dev);
-                break;
-        case NV_20:
-        case NV_30:
-                nv20_graph_create(dev);
-                break;
-        case NV_40:
-                nv40_graph_create(dev);
-                break;
-        case NV_50:
-                nv50_graph_create(dev);
-                break;
-        case NV_C0:
-                nvc0_graph_create(dev);
-                break;
-        default:
-                break;
-        }
-
-        switch (dev_priv->chipset) {
-        case 0x84:
-        case 0x86:
-        case 0x92:
-        case 0x94:
-        case 0x96:
-        case 0xa0:
-                nv84_crypt_create(dev);
-                break;
-        }
+        if (!nouveau_noaccel) {
+                switch (dev_priv->card_type) {
+                case NV_04:
+                        nv04_graph_create(dev);
+                        break;
+                case NV_10:
+                        nv10_graph_create(dev);
+                        break;
+                case NV_20:
+                case NV_30:
+                        nv20_graph_create(dev);
+                        break;
+                case NV_40:
+                        nv40_graph_create(dev);
+                        break;
+                case NV_50:
+                        nv50_graph_create(dev);
+                        break;
+                case NV_C0:
+                        nvc0_graph_create(dev);
+                        break;
+                default:
+                        break;
+                }
 
-        switch (dev_priv->card_type) {
-        case NV_50:
                 switch (dev_priv->chipset) {
-                case 0xa3:
-                case 0xa5:
-                case 0xa8:
-                case 0xaf:
-                        nva3_copy_create(dev);
+                case 0x84:
+                case 0x86:
+                case 0x92:
+                case 0x94:
+                case 0x96:
+                case 0xa0:
+                        nv84_crypt_create(dev);
                         break;
                 }
-                break;
-        case NV_C0:
-                nvc0_copy_create(dev, 0);
-                nvc0_copy_create(dev, 1);
-                break;
-        default:
-                break;
-        }
 
-        if (dev_priv->card_type == NV_40)
-                nv40_mpeg_create(dev);
-        else
-        if (dev_priv->card_type == NV_50 &&
-            (dev_priv->chipset < 0x98 || dev_priv->chipset == 0xa0))
-                nv50_mpeg_create(dev);
+                switch (dev_priv->card_type) {
+                case NV_50:
+                        switch (dev_priv->chipset) {
+                        case 0xa3:
+                        case 0xa5:
+                        case 0xa8:
+                        case 0xaf:
+                                nva3_copy_create(dev);
+                                break;
+                        }
+                        break;
+                case NV_C0:
+                        nvc0_copy_create(dev, 0);
+                        nvc0_copy_create(dev, 1);
+                        break;
+                default:
+                        break;
+                }
+
+                if (dev_priv->card_type == NV_40)
+                        nv40_mpeg_create(dev);
+                else
+                if (dev_priv->card_type == NV_50 &&
+                    (dev_priv->chipset < 0x98 || dev_priv->chipset == 0xa0))
+                        nv50_mpeg_create(dev);
 
-        if (!nouveau_noaccel) {
                 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
                         if (dev_priv->eng[e]) {
                                 ret = dev_priv->eng[e]->init(dev, e);
@@ -922,6 +923,7 @@ int nouveau_load(struct drm_device *dev, unsigned long flags)
                 dev_priv->card_type = NV_50;
                 break;
         case 0xc0:
+        case 0xd0:
                 dev_priv->card_type = NV_C0;
                 break;
         default:
diff --git a/drivers/gpu/drm/nouveau/nouveau_vm.c b/drivers/gpu/drm/nouveau/nouveau_vm.c
index 0059e6f58a8b..519a6b4bba46 100644
--- a/drivers/gpu/drm/nouveau/nouveau_vm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_vm.c
@@ -58,6 +58,7 @@ nouveau_vm_map_at(struct nouveau_vma *vma, u64 delta, struct nouveau_mem *node)
                         num -= len;
                         pte += len;
                         if (unlikely(end >= max)) {
+                                phys += len << (bits + 12);
                                 pde++;
                                 pte = 0;
                         }
diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
index 3c78bc81357e..f1a3ae491995 100644
--- a/drivers/gpu/drm/nouveau/nv04_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
@@ -376,7 +376,10 @@ nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode)
          */
 
         /* framebuffer can be larger than crtc scanout area. */
-        regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = XLATE(fb->pitch / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
+        regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
+                XLATE(fb->pitch / 8, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
+        regp->CRTC[NV_CIO_CRE_42] =
+                XLATE(fb->pitch / 8, 11, NV_CIO_CRE_42_OFFSET_11);
         regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ?
                                             MASK(NV_CIO_CRE_RPC1_LARGE) : 0x00;
         regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) |
@@ -824,8 +827,11 @@ nv04_crtc_do_mode_set_base(struct drm_crtc *crtc,
         regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitch >> 3;
         regp->CRTC[NV_CIO_CRE_RPC0_INDEX] =
                 XLATE(drm_fb->pitch >> 3, 8, NV_CIO_CRE_RPC0_OFFSET_10_8);
+        regp->CRTC[NV_CIO_CRE_42] =
+                XLATE(drm_fb->pitch / 8, 11, NV_CIO_CRE_42_OFFSET_11);
         crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX);
         crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX);
+        crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42);
 
         /* Update the framebuffer location. */
         regp->fb_start = nv_crtc->fb.offset & ~3;
diff --git a/drivers/gpu/drm/nouveau/nvreg.h b/drivers/gpu/drm/nouveau/nvreg.h
index fe0f253089ac..bbfb1a68fb11 100644
--- a/drivers/gpu/drm/nouveau/nvreg.h
+++ b/drivers/gpu/drm/nouveau/nvreg.h
@@ -277,6 +277,8 @@
 #               define NV_CIO_CRE_EBR_VDE_11            2:2
 #               define NV_CIO_CRE_EBR_VRS_11            4:4
 #               define NV_CIO_CRE_EBR_VBS_11            6:6
+#       define NV_CIO_CRE_42                    0x42
+#               define NV_CIO_CRE_42_OFFSET_11          6:6
 #       define NV_CIO_CRE_43                    0x43
 #       define NV_CIO_CRE_44                    0x44    /* head control */
 #       define NV_CIO_CRE_CSB                   0x45    /* colour saturation boost */