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authorJohn Adamson <jadamson@allen-organ.com>2008-08-22 02:43:49 -0400
committerGreg Ungerer <gerg@uclinux.org>2009-01-27 01:42:00 -0500
commit26a4bc66a6f57299027e04d90b14fe56a44c6d2b (patch)
tree78465b6c8de7c1309f59667455287df9f88f2c76
parentc7bcd0df1f2879fcedc3f55323c3afa7bb1f4295 (diff)
m68knommu: fix ColdFire 5272 serial baud rates in mcf.c
I noticed (the hard way) that the mcf.c driver doesn't support the fractional precision register on the MCF5272. This makes the console dicey at 115200 baud and a system clock of 66.0 MHz. On the other hand, if your hardware is running at 66.666 MHz, it probably isn't a problem. Patch submitted by John Adamson <jadamson@allen-organ.com> Signed-off-by: Greg Ungerer <gerg@uclinux.org>
-rw-r--r--drivers/serial/mcf.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/serial/mcf.c b/drivers/serial/mcf.c
index b2001c5b145c..56841fe5f483 100644
--- a/drivers/serial/mcf.c
+++ b/drivers/serial/mcf.c
@@ -212,10 +212,18 @@ static void mcf_set_termios(struct uart_port *port, struct ktermios *termios,
212{ 212{
213 unsigned long flags; 213 unsigned long flags;
214 unsigned int baud, baudclk; 214 unsigned int baud, baudclk;
215#if defined(CONFIG_M5272)
216 unsigned int baudfr;
217#endif
215 unsigned char mr1, mr2; 218 unsigned char mr1, mr2;
216 219
217 baud = uart_get_baud_rate(port, termios, old, 0, 230400); 220 baud = uart_get_baud_rate(port, termios, old, 0, 230400);
221#if defined(CONFIG_M5272)
222 baudclk = (MCF_BUSCLK / baud) / 32;
223 baudfr = (((MCF_BUSCLK / baud) + 1) / 2) % 16;
224#else
218 baudclk = ((MCF_BUSCLK / baud) + 16) / 32; 225 baudclk = ((MCF_BUSCLK / baud) + 16) / 32;
226#endif
219 227
220 mr1 = MCFUART_MR1_RXIRQRDY | MCFUART_MR1_RXERRCHAR; 228 mr1 = MCFUART_MR1_RXIRQRDY | MCFUART_MR1_RXERRCHAR;
221 mr2 = 0; 229 mr2 = 0;
@@ -262,6 +270,9 @@ static void mcf_set_termios(struct uart_port *port, struct ktermios *termios,
262 writeb(mr2, port->membase + MCFUART_UMR); 270 writeb(mr2, port->membase + MCFUART_UMR);
263 writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1); 271 writeb((baudclk & 0xff00) >> 8, port->membase + MCFUART_UBG1);
264 writeb((baudclk & 0xff), port->membase + MCFUART_UBG2); 272 writeb((baudclk & 0xff), port->membase + MCFUART_UBG2);
273#if defined(CONFIG_M5272)
274 writeb((baudfr & 0x0f), port->membase + MCFUART_UFPD);
275#endif
265 writeb(MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER, 276 writeb(MCFUART_UCSR_RXCLKTIMER | MCFUART_UCSR_TXCLKTIMER,
266 port->membase + MCFUART_UCSR); 277 port->membase + MCFUART_UCSR);
267 writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE, 278 writeb(MCFUART_UCR_RXENABLE | MCFUART_UCR_TXENABLE,