diff options
author | Victor Kamensky <victor.kamensky@linaro.org> | 2014-04-15 13:37:48 -0400 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2014-05-08 10:09:55 -0400 |
commit | f6f3b50f996b938b034b14b5084108b2acfcae7d (patch) | |
tree | dc7006a6b24ba55efbc9d085141f6f1b7618b5f8 | |
parent | 834cacfbef09afc5566eae4dbdc08a422e90451b (diff) |
ARM: OMAP: counter-32k: raw read and write endian fix
All OMAP IP blocks expect LE data, but CPU may operate in BE mode.
Need to use endian neutral functions to read/write h/w registers.
I.e instead of __raw_read[lw] and __raw_write[lw] functions code
need to use read[lw]_relaxed and write[lw]_relaxed functions.
If the first simply reads/writes register, the second will byteswap
it if host operates in BE mode.
Changes are trivial sed like replacement of __raw_xxx functions
with xxx_relaxed variant.
Signed-off-by: Victor Kamensky <victor.kamensky@linaro.org>
Signed-off-by: Taras Kondratiuk <taras.kondratiuk@linaro.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r-- | arch/arm/plat-omap/counter_32k.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/plat-omap/counter_32k.c b/arch/arm/plat-omap/counter_32k.c index 384a776d8eb2..61b4d705c267 100644 --- a/arch/arm/plat-omap/counter_32k.c +++ b/arch/arm/plat-omap/counter_32k.c | |||
@@ -40,7 +40,7 @@ static void __iomem *sync32k_cnt_reg; | |||
40 | 40 | ||
41 | static u64 notrace omap_32k_read_sched_clock(void) | 41 | static u64 notrace omap_32k_read_sched_clock(void) |
42 | { | 42 | { |
43 | return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0; | 43 | return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; |
44 | } | 44 | } |
45 | 45 | ||
46 | /** | 46 | /** |
@@ -64,7 +64,7 @@ static void omap_read_persistent_clock(struct timespec *ts) | |||
64 | spin_lock_irqsave(&read_persistent_clock_lock, flags); | 64 | spin_lock_irqsave(&read_persistent_clock_lock, flags); |
65 | 65 | ||
66 | last_cycles = cycles; | 66 | last_cycles = cycles; |
67 | cycles = sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0; | 67 | cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; |
68 | 68 | ||
69 | nsecs = clocksource_cyc2ns(cycles - last_cycles, | 69 | nsecs = clocksource_cyc2ns(cycles - last_cycles, |
70 | persistent_mult, persistent_shift); | 70 | persistent_mult, persistent_shift); |
@@ -95,7 +95,7 @@ int __init omap_init_clocksource_32k(void __iomem *vbase) | |||
95 | * The 'SCHEME' bits(30-31) of the revision register is used | 95 | * The 'SCHEME' bits(30-31) of the revision register is used |
96 | * to identify the version. | 96 | * to identify the version. |
97 | */ | 97 | */ |
98 | if (__raw_readl(vbase + OMAP2_32KSYNCNT_REV_OFF) & | 98 | if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) & |
99 | OMAP2_32KSYNCNT_REV_SCHEME) | 99 | OMAP2_32KSYNCNT_REV_SCHEME) |
100 | sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH; | 100 | sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH; |
101 | else | 101 | else |