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authorLinus Torvalds <torvalds@g5.osdl.org>2006-06-20 17:49:00 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2006-06-20 17:49:00 -0400
commitff9144530e9cfe8923e00172e3f8ff83c3b8ff8b (patch)
treec64a9528dde590b9f3174125ad361f46ee30bba8
parent25f42b6af09e34c3f92107b36b5aa6edc2fdba2f (diff)
parent96ce2385dd2817da549910001a69ac0a2762a1b9 (diff)
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (22 commits) [ARM] 3559/1: S3C2442: core and serial port [ARM] 3557/1: S3C24XX: centralise and cleanup uart registration [ARM] 3558/1: SMDK24XX: LED platform devices [ARM] 3534/1: add spi support to lubbock platform [ARM] 3554/1: ARM: Fix dyntick locking [ARM] 3553/1: S3C24XX: earlier print of cpu idcode info [ARM] 3552/1: S3C24XX: Move VA of GPIO for low-level debug [ARM] 3551/1: S3C24XX: PM code failes to compile with CONFIG_DCACHE_WRITETHROUGH [ARM] 3550/1: OSIRIS: fix serial port map for 1:1 [ARM] 3548/1: Fix the ARMv6 CPU id in compressed/head.S [ARM] 3335/1: Old-abi Thumb sys_syscall broken [ARM] 3467/1: [3/3] Support for Philips PNX4008 platform: defconfig [ARM] 3466/1: [2/3] Support for Philips PNX4008 platform: chip support [ARM] 3465/1: [1/3] Support for Philips PNX4008 platform: headers [ARM] 3407/1: lpd7x: documetation update [ARM] 3406/1: lpd7x: compilation fix for smc91x [ARM] 3405/1: lpd7a40x: CPLD ssp driver [ARM] 3404/1: lpd7a40x: AMBA CLCD support [ARM] 3403/1: lpd7a40x: updated default configurations [ARM] 3402/1: lpd7a40x: serial driver bug fix ...
Diffstat
-rw-r--r--Documentation/arm/Sharp-LH/ADC-LH7-Touchscreen61
-rw-r--r--Documentation/arm/Sharp-LH/LCDPanels59
-rw-r--r--arch/arm/Kconfig5
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/compressed/head.S4
-rw-r--r--arch/arm/configs/lpd7a400_defconfig135
-rw-r--r--arch/arm/configs/lpd7a404_defconfig430
-rw-r--r--arch/arm/configs/pnx4008_defconfig2072
-rw-r--r--arch/arm/kernel/entry-common.S2
-rw-r--r--arch/arm/kernel/irq.c4
-rw-r--r--arch/arm/kernel/time.c24
-rw-r--r--arch/arm/mach-lh7a40x/Kconfig5
-rw-r--r--arch/arm/mach-lh7a40x/Makefile19
-rw-r--r--arch/arm/mach-lh7a40x/arch-lpd7a40x.c200
-rw-r--r--arch/arm/mach-lh7a40x/clcd.c241
-rw-r--r--arch/arm/mach-lh7a40x/clocks.c199
-rw-r--r--arch/arm/mach-lh7a40x/common.h1
-rw-r--r--arch/arm/mach-lh7a40x/irq-lh7a404.c17
-rw-r--r--arch/arm/mach-lh7a40x/lcd-panel.h346
-rw-r--r--arch/arm/mach-lh7a40x/ssp-cpld.c343
-rw-r--r--arch/arm/mach-lh7a40x/time.c4
-rw-r--r--arch/arm/mach-pnx4008/Makefile12
-rw-r--r--arch/arm/mach-pnx4008/Makefile.boot4
-rw-r--r--arch/arm/mach-pnx4008/clock.c1010
-rw-r--r--arch/arm/mach-pnx4008/clock.h43
-rw-r--r--arch/arm/mach-pnx4008/core.c207
-rw-r--r--arch/arm/mach-pnx4008/dma.c1109
-rw-r--r--arch/arm/mach-pnx4008/gpio.c330
-rw-r--r--arch/arm/mach-pnx4008/irq.c121
-rw-r--r--arch/arm/mach-pnx4008/pm.c184
-rw-r--r--arch/arm/mach-pnx4008/serial.c69
-rw-r--r--arch/arm/mach-pnx4008/sleep.S196
-rw-r--r--arch/arm/mach-pnx4008/time.c141
-rw-r--r--arch/arm/mach-pxa/lubbock.c84
-rw-r--r--arch/arm/mach-s3c2410/Kconfig26
-rw-r--r--arch/arm/mach-s3c2410/Makefile10
-rw-r--r--arch/arm/mach-s3c2410/clock.c2
-rw-r--r--arch/arm/mach-s3c2410/common-smdk.c65
-rw-r--r--arch/arm/mach-s3c2410/cpu.c77
-rw-r--r--arch/arm/mach-s3c2410/cpu.h7
-rw-r--r--arch/arm/mach-s3c2410/devs.c78
-rw-r--r--arch/arm/mach-s3c2410/devs.h8
-rw-r--r--arch/arm/mach-s3c2410/mach-anubis.c2
-rw-r--r--arch/arm/mach-s3c2410/mach-bast.c2
-rw-r--r--arch/arm/mach-s3c2410/mach-h1940.c2
-rw-r--r--arch/arm/mach-s3c2410/mach-nexcoder.c2
-rw-r--r--arch/arm/mach-s3c2410/mach-osiris.c5
-rw-r--r--arch/arm/mach-s3c2410/mach-otom.c2
-rw-r--r--arch/arm/mach-s3c2410/mach-smdk2410.c2
-rw-r--r--arch/arm/mach-s3c2410/mach-smdk2440.c2
-rw-r--r--arch/arm/mach-s3c2410/mach-vr1000.c2
-rw-r--r--arch/arm/mach-s3c2410/pm.c4
-rw-r--r--arch/arm/mach-s3c2410/s3c2410.c85
-rw-r--r--arch/arm/mach-s3c2410/s3c2440-irq.c77
-rw-r--r--arch/arm/mach-s3c2410/s3c2440.c234
-rw-r--r--arch/arm/mach-s3c2410/s3c2442-clock.c171
-rw-r--r--arch/arm/mach-s3c2410/s3c2442.c52
-rw-r--r--arch/arm/mach-s3c2410/s3c2442.h17
-rw-r--r--arch/arm/mach-s3c2410/s3c244x-irq.c142
-rw-r--r--arch/arm/mach-s3c2410/s3c244x.c182
-rw-r--r--arch/arm/mach-s3c2410/s3c244x.h25
-rw-r--r--arch/arm/mach-s3c2410/sleep.S2
-rw-r--r--arch/arm/mm/Kconfig4
-rw-r--r--drivers/net/smc91x.h44
-rw-r--r--drivers/serial/s3c2410.c2
-rw-r--r--drivers/serial/serial_lh7a40x.c13
-rw-r--r--drivers/video/Kconfig63
-rw-r--r--include/asm-arm/arch-lh7a40x/clocks.h20
-rw-r--r--include/asm-arm/arch-lh7a40x/constants.h8
-rw-r--r--include/asm-arm/arch-lh7a40x/dma.h79
-rw-r--r--include/asm-arm/arch-lh7a40x/entry-macro.S70
-rw-r--r--include/asm-arm/arch-lh7a40x/hardware.h4
-rw-r--r--include/asm-arm/arch-lh7a40x/irqs.h7
-rw-r--r--include/asm-arm/arch-lh7a40x/registers.h64
-rw-r--r--include/asm-arm/arch-lh7a40x/ssp.h71
-rw-r--r--include/asm-arm/arch-lh7a40x/uncompress.h2
-rw-r--r--include/asm-arm/arch-pnx4008/clock.h61
-rw-r--r--include/asm-arm/arch-pnx4008/debug-macro.S27
-rw-r--r--include/asm-arm/arch-pnx4008/dma.h162
-rw-r--r--include/asm-arm/arch-pnx4008/entry-macro.S121
-rw-r--r--include/asm-arm/arch-pnx4008/gpio.h139
-rw-r--r--include/asm-arm/arch-pnx4008/hardware.h32
-rw-r--r--include/asm-arm/arch-pnx4008/io.h21
-rw-r--r--include/asm-arm/arch-pnx4008/irq.h42
-rw-r--r--include/asm-arm/arch-pnx4008/irqs.h215
-rw-r--r--include/asm-arm/arch-pnx4008/memory.h24
-rw-r--r--include/asm-arm/arch-pnx4008/param.h21
-rw-r--r--include/asm-arm/arch-pnx4008/platform.h69
-rw-r--r--include/asm-arm/arch-pnx4008/pm.h62
-rw-r--r--include/asm-arm/arch-pnx4008/system.h38
-rw-r--r--include/asm-arm/arch-pnx4008/timex.h73
-rw-r--r--include/asm-arm/arch-pnx4008/uncompress.h46
-rw-r--r--include/asm-arm/arch-pnx4008/vmalloc.h20
-rw-r--r--include/asm-arm/arch-s3c2410/map.h11
-rw-r--r--include/asm-arm/arch-s3c2410/regs-clock.h6
-rw-r--r--include/asm-arm/arch-s3c2410/regs-gpio.h5
-rw-r--r--include/asm-arm/arch-s3c2410/uncompress.h5
-rw-r--r--include/asm-arm/mach/time.h1
98 files changed, 9948 insertions, 671 deletions
diff --git a/Documentation/arm/Sharp-LH/ADC-LH7-Touchscreen b/Documentation/arm/Sharp-LH/ADC-LH7-Touchscreen
new file mode 100644
index 000000000000..1e6a23fdf2fc
--- /dev/null
+++ b/Documentation/arm/Sharp-LH/ADC-LH7-Touchscreen
@@ -0,0 +1,61 @@
1README on the ADC/Touchscreen Controller
2========================================
3
4The LH79524 and LH7A404 include a built-in Analog to Digital
5controller (ADC) that is used to process input from a touchscreen.
6The driver only implements a four-wire touch panel protocol.
7
8The touchscreen driver is maintenance free except for the pen-down or
9touch threshold. Some resistive displays and board combinations may
10require tuning of this threshold. The driver exposes some of it's
11internal state in the sys filesystem. If the kernel is configured
12with it, CONFIG_SYSFS, and sysfs is mounted at /sys, there will be a
13directory
14
15 /sys/devices/platform/adc-lh7.0
16
17containing these files.
18
19 -r--r--r-- 1 root root 4096 Jan 1 00:00 samples
20 -rw-r--r-- 1 root root 4096 Jan 1 00:00 threshold
21 -r--r--r-- 1 root root 4096 Jan 1 00:00 threshold_range
22
23The threshold is the current touch threshold. It defaults to 750 on
24most targets.
25
26 # cat threshold
27 750
28
29The threshold_range contains the range of valid values for the
30threshold. Values outside of this range will be silently ignored.
31
32 # cat threshold_range
33 0 1023
34
35To change the threshold, write a value to the threshold file.
36
37 # echo 500 > threshold
38 # cat threshold
39 500
40
41The samples file contains the most recently sampled values from the
42ADC. There are 12. Below are typical of the last sampled values when
43the pen has been released. The first two and last two samples are for
44detecting whether or not the pen is down. The third through sixth are
45X coordinate samples. The seventh through tenth are Y coordinate
46samples.
47
48 # cat samples
49 1023 1023 0 0 0 0 530 529 530 529 1023 1023
50
51To determine a reasonable threshold, press on the touch panel with an
52appropriate stylus and read the values from samples.
53
54 # cat samples
55 1023 676 92 103 101 102 855 919 922 922 1023 679
56
57The first and eleventh samples are discarded. Thus, the important
58values are the second and twelfth which are used to determine if the
59pen is down. When both are below the threshold, the driver registers
60that the pen is down. When either is above the threshold, it
61registers then pen is up.
diff --git a/Documentation/arm/Sharp-LH/LCDPanels b/Documentation/arm/Sharp-LH/LCDPanels
new file mode 100644
index 000000000000..fb1b21c2f2f4
--- /dev/null
+++ b/Documentation/arm/Sharp-LH/LCDPanels
@@ -0,0 +1,59 @@
1README on the LCD Panels
2========================
3
4Configuration options for several LCD panels, available from Logic PD,
5are included in the kernel source. This README will help you
6understand the configuration data and give you some guidance for
7adding support for other panels if you wish.
8
9
10lcd-panels.h
11------------
12
13There is no way, at present, to detect which panel is attached to the
14system at runtime. Thus the kernel configuration is static. The file
15arch/arm/mach-ld7a40x/lcd-panels.h (or similar) defines all of the
16panel specific parameters.
17
18It should be possible for this data to be shared among several device
19families. The current layout may be insufficiently general, but it is
20amenable to improvement.
21
22
23PIXEL_CLOCK
24-----------
25
26The panel data sheets will give a range of acceptable pixel clocks.
27The fundamental LCDCLK input frequency is divided down by a PCD
28constant in field '.tim2'. It may happen that it is impossible to set
29the pixel clock within this range. A clock which is too slow will
30tend to flicker. For the highest quality image, set the clock as high
31as possible.
32
33
34MARGINS
35-------
36
37These values may be difficult to glean from the panel data sheet. In
38the case of the Sharp panels, the upper margin is explicitly called
39out as a specific number of lines from the top of the frame. The
40other values may not matter as much as the panels tend to
41automatically center the image.
42
43
44Sync Sense
45----------
46
47The sense of the hsync and vsync pulses may be called out in the data
48sheet. On one panel, the sense of these pulses determine the height
49of the visible region on the panel. Most of the Sharp panels use
50negative sense sync pulses set by the TIM2_IHS and TIM2_IVS bits in
51'.tim2'.
52
53
54Pel Layout
55----------
56
57The Sharp color TFT panels are all configured for 16 bit direct color
58modes. The amba-lcd driver sets the pel mode to 565 for 5 bits of
59each red and blue and 6 bits of green.
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 08b7cc900cae..f47cf9af3bc8 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -270,6 +270,11 @@ config ARCH_AT91RM9200
270 Say Y here if you intend to run this kernel on an Atmel 270 Say Y here if you intend to run this kernel on an Atmel
271 AT91RM9200-based board. 271 AT91RM9200-based board.
272 272
273config ARCH_PNX4008
274 bool "Philips Nexperia PNX4008 Mobile"
275 help
276 This enables support for Philips PNX4008 mobile platform.
277
273endchoice 278endchoice
274 279
275source "arch/arm/mach-clps711x/Kconfig" 280source "arch/arm/mach-clps711x/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6f8e84c1c1f2..6c97aa70d3bc 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -116,6 +116,7 @@ endif
116 machine-$(CONFIG_ARCH_REALVIEW) := realview 116 machine-$(CONFIG_ARCH_REALVIEW) := realview
117 machine-$(CONFIG_ARCH_AT91RM9200) := at91rm9200 117 machine-$(CONFIG_ARCH_AT91RM9200) := at91rm9200
118 machine-$(CONFIG_ARCH_EP93XX) := ep93xx 118 machine-$(CONFIG_ARCH_EP93XX) := ep93xx
119 machine-$(CONFIG_ARCH_PNX4008) := pnx4008
119 120
120ifeq ($(CONFIG_ARCH_EBSA110),y) 121ifeq ($(CONFIG_ARCH_EBSA110),y)
121# This is what happens if you forget the IOCS16 line. 122# This is what happens if you forget the IOCS16 line.
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index b56f5e691d65..23016f6aa645 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -605,8 +605,8 @@ proc_types:
605 b __armv4_mmu_cache_off 605 b __armv4_mmu_cache_off
606 b __armv4_mmu_cache_flush 606 b __armv4_mmu_cache_flush
607 607
608 .word 0x00070000 @ ARMv6 608 .word 0x0007b000 @ ARMv6
609 .word 0x000f0000 609 .word 0x0007f000
610 b __armv4_mmu_cache_on 610 b __armv4_mmu_cache_on
611 b __armv4_mmu_cache_off 611 b __armv4_mmu_cache_off
612 b __armv6_mmu_cache_flush 612 b __armv6_mmu_cache_flush
diff --git a/arch/arm/configs/lpd7a400_defconfig b/arch/arm/configs/lpd7a400_defconfig
index 67eaa26c2647..bf9cf9c6d2df 100644
--- a/arch/arm/configs/lpd7a400_defconfig
+++ b/arch/arm/configs/lpd7a400_defconfig
@@ -1,7 +1,7 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc1-bk2 3# Linux kernel version: 2.6.12
4# Mon Mar 28 00:06:33 2005 4# Thu Nov 3 14:15:32 2005
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_MMU=y 7CONFIG_MMU=y
@@ -17,6 +17,7 @@ CONFIG_EXPERIMENTAL=y
17CONFIG_CLEAN_COMPILE=y 17CONFIG_CLEAN_COMPILE=y
18CONFIG_BROKEN_ON_SMP=y 18CONFIG_BROKEN_ON_SMP=y
19CONFIG_LOCK_KERNEL=y 19CONFIG_LOCK_KERNEL=y
20CONFIG_INIT_ENV_ARG_LIMIT=32
20 21
21# 22#
22# General setup 23# General setup
@@ -36,6 +37,8 @@ CONFIG_EMBEDDED=y
36CONFIG_KALLSYMS=y 37CONFIG_KALLSYMS=y
37# CONFIG_KALLSYMS_ALL is not set 38# CONFIG_KALLSYMS_ALL is not set
38# CONFIG_KALLSYMS_EXTRA_PASS is not set 39# CONFIG_KALLSYMS_EXTRA_PASS is not set
40CONFIG_PRINTK=y
41CONFIG_BUG=y
39CONFIG_BASE_FULL=y 42CONFIG_BASE_FULL=y
40CONFIG_FUTEX=y 43CONFIG_FUTEX=y
41# CONFIG_EPOLL is not set 44# CONFIG_EPOLL is not set
@@ -71,6 +74,7 @@ CONFIG_BASE_SMALL=0
71# CONFIG_ARCH_SA1100 is not set 74# CONFIG_ARCH_SA1100 is not set
72# CONFIG_ARCH_S3C2410 is not set 75# CONFIG_ARCH_S3C2410 is not set
73# CONFIG_ARCH_SHARK is not set 76# CONFIG_ARCH_SHARK is not set
77# CONFIG_ARCH_LH7952X is not set
74CONFIG_ARCH_LH7A40X=y 78CONFIG_ARCH_LH7A40X=y
75# CONFIG_ARCH_OMAP is not set 79# CONFIG_ARCH_OMAP is not set
76# CONFIG_ARCH_VERSATILE is not set 80# CONFIG_ARCH_VERSATILE is not set
@@ -84,6 +88,7 @@ CONFIG_ARCH_LH7A40X=y
84CONFIG_MACH_LPD7A400=y 88CONFIG_MACH_LPD7A400=y
85# CONFIG_MACH_LPD7A404 is not set 89# CONFIG_MACH_LPD7A404 is not set
86CONFIG_ARCH_LH7A400=y 90CONFIG_ARCH_LH7A400=y
91CONFIG_LPD7A40X_CPLD_SSP=y
87# CONFIG_LH7A40X_CONTIGMEM is not set 92# CONFIG_LH7A40X_CONTIGMEM is not set
88# CONFIG_LH7A40X_ONE_BANK_PER_NODE is not set 93# CONFIG_LH7A40X_ONE_BANK_PER_NODE is not set
89 94
@@ -110,6 +115,8 @@ CONFIG_ARM_THUMB=y
110# 115#
111# Bus support 116# Bus support
112# 117#
118CONFIG_ARM_AMBA=y
119CONFIG_ISA_DMA_API=y
113 120
114# 121#
115# PCCARD (PCMCIA/CardBus) support 122# PCCARD (PCMCIA/CardBus) support
@@ -119,6 +126,7 @@ CONFIG_ARM_THUMB=y
119# 126#
120# Kernel Features 127# Kernel Features
121# 128#
129# CONFIG_SMP is not set
122CONFIG_PREEMPT=y 130CONFIG_PREEMPT=y
123CONFIG_DISCONTIGMEM=y 131CONFIG_DISCONTIGMEM=y
124CONFIG_ALIGNMENT_TRAP=y 132CONFIG_ALIGNMENT_TRAP=y
@@ -175,7 +183,7 @@ CONFIG_MTD=y
175# CONFIG_MTD_CONCAT is not set 183# CONFIG_MTD_CONCAT is not set
176CONFIG_MTD_PARTITIONS=y 184CONFIG_MTD_PARTITIONS=y
177# CONFIG_MTD_REDBOOT_PARTS is not set 185# CONFIG_MTD_REDBOOT_PARTS is not set
178# CONFIG_MTD_CMDLINE_PARTS is not set 186CONFIG_MTD_CMDLINE_PARTS=y
179# CONFIG_MTD_AFS_PARTS is not set 187# CONFIG_MTD_AFS_PARTS is not set
180 188
181# 189#
@@ -217,7 +225,10 @@ CONFIG_MTD_CFI_UTIL=y
217# Mapping drivers for chip access 225# Mapping drivers for chip access
218# 226#
219# CONFIG_MTD_COMPLEX_MAPPINGS is not set 227# CONFIG_MTD_COMPLEX_MAPPINGS is not set
220# CONFIG_MTD_PHYSMAP is not set 228CONFIG_MTD_PHYSMAP=y
229CONFIG_MTD_PHYSMAP_START=0x00000000
230CONFIG_MTD_PHYSMAP_LEN=0x04000000
231CONFIG_MTD_PHYSMAP_BANKWIDTH=4
221# CONFIG_MTD_ARM_INTEGRATOR is not set 232# CONFIG_MTD_ARM_INTEGRATOR is not set
222# CONFIG_MTD_EDB7312 is not set 233# CONFIG_MTD_EDB7312 is not set
223 234
@@ -254,7 +265,6 @@ CONFIG_MTD_CFI_UTIL=y
254# 265#
255# Block devices 266# Block devices
256# 267#
257# CONFIG_BLK_DEV_FD is not set
258# CONFIG_BLK_DEV_COW_COMMON is not set 268# CONFIG_BLK_DEV_COW_COMMON is not set
259CONFIG_BLK_DEV_LOOP=y 269CONFIG_BLK_DEV_LOOP=y
260# CONFIG_BLK_DEV_CRYPTOLOOP is not set 270# CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -288,13 +298,15 @@ CONFIG_BLK_DEV_IDEDISK=y
288# CONFIG_BLK_DEV_IDECD is not set 298# CONFIG_BLK_DEV_IDECD is not set
289# CONFIG_BLK_DEV_IDETAPE is not set 299# CONFIG_BLK_DEV_IDETAPE is not set
290# CONFIG_BLK_DEV_IDEFLOPPY is not set 300# CONFIG_BLK_DEV_IDEFLOPPY is not set
301# CONFIG_BLK_DEV_IDESCSI is not set
291# CONFIG_IDE_TASK_IOCTL is not set 302# CONFIG_IDE_TASK_IOCTL is not set
303CONFIG_IDE_POLL=y
292 304
293# 305#
294# IDE chipset support/bugfixes 306# IDE chipset support/bugfixes
295# 307#
296CONFIG_IDE_GENERIC=y 308CONFIG_IDE_GENERIC=y
297# CONFIG_IDE_ARM is not set 309CONFIG_IDE_ARM=y
298# CONFIG_BLK_DEV_IDEDMA is not set 310# CONFIG_BLK_DEV_IDEDMA is not set
299# CONFIG_IDEDMA_AUTO is not set 311# CONFIG_IDEDMA_AUTO is not set
300# CONFIG_BLK_DEV_HD is not set 312# CONFIG_BLK_DEV_HD is not set
@@ -302,7 +314,37 @@ CONFIG_IDE_GENERIC=y
302# 314#
303# SCSI device support 315# SCSI device support
304# 316#
305# CONFIG_SCSI is not set 317CONFIG_SCSI=y
318# CONFIG_SCSI_PROC_FS is not set
319
320#
321# SCSI support type (disk, tape, CD-ROM)
322#
323# CONFIG_BLK_DEV_SD is not set
324# CONFIG_CHR_DEV_ST is not set
325# CONFIG_CHR_DEV_OSST is not set
326# CONFIG_BLK_DEV_SR is not set
327# CONFIG_CHR_DEV_SG is not set
328
329#
330# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
331#
332# CONFIG_SCSI_MULTI_LUN is not set
333# CONFIG_SCSI_CONSTANTS is not set
334# CONFIG_SCSI_LOGGING is not set
335
336#
337# SCSI Transport Attributes
338#
339# CONFIG_SCSI_SPI_ATTRS is not set
340# CONFIG_SCSI_FC_ATTRS is not set
341# CONFIG_SCSI_ISCSI_ATTRS is not set
342
343#
344# SCSI low-level drivers
345#
346# CONFIG_SCSI_SATA is not set
347# CONFIG_SCSI_DEBUG is not set
306 348
307# 349#
308# Multi-device support (RAID and LVM) 350# Multi-device support (RAID and LVM)
@@ -331,7 +373,6 @@ CONFIG_NET=y
331# 373#
332CONFIG_PACKET=y 374CONFIG_PACKET=y
333# CONFIG_PACKET_MMAP is not set 375# CONFIG_PACKET_MMAP is not set
334# CONFIG_NETLINK_DEV is not set
335CONFIG_UNIX=y 376CONFIG_UNIX=y
336# CONFIG_NET_KEY is not set 377# CONFIG_NET_KEY is not set
337CONFIG_INET=y 378CONFIG_INET=y
@@ -438,13 +479,10 @@ CONFIG_INPUT=y
438# 479#
439# Userland interfaces 480# Userland interfaces
440# 481#
441CONFIG_INPUT_MOUSEDEV=y 482# CONFIG_INPUT_MOUSEDEV is not set
442CONFIG_INPUT_MOUSEDEV_PSAUX=y
443CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
444CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
445# CONFIG_INPUT_JOYDEV is not set 483# CONFIG_INPUT_JOYDEV is not set
446# CONFIG_INPUT_TSDEV is not set 484# CONFIG_INPUT_TSDEV is not set
447# CONFIG_INPUT_EVDEV is not set 485CONFIG_INPUT_EVDEV=y
448# CONFIG_INPUT_EVBUG is not set 486# CONFIG_INPUT_EVBUG is not set
449 487
450# 488#
@@ -453,7 +491,13 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
453# CONFIG_INPUT_KEYBOARD is not set 491# CONFIG_INPUT_KEYBOARD is not set
454# CONFIG_INPUT_MOUSE is not set 492# CONFIG_INPUT_MOUSE is not set
455# CONFIG_INPUT_JOYSTICK is not set 493# CONFIG_INPUT_JOYSTICK is not set
456# CONFIG_INPUT_TOUCHSCREEN is not set 494CONFIG_INPUT_TOUCHSCREEN=y
495# CONFIG_TOUCHSCREEN_GUNZE is not set
496# CONFIG_TOUCHSCREEN_ELO is not set
497# CONFIG_TOUCHSCREEN_MTOUCH is not set
498# CONFIG_TOUCHSCREEN_MK712 is not set
499CONFIG_TOUCHSCREEN_ADS7843_LH7=y
500CONFIG_HAS_TOUCHSCREEN_ADS7843_LH7=y
457# CONFIG_INPUT_MISC is not set 501# CONFIG_INPUT_MISC is not set
458 502
459# 503#
@@ -461,7 +505,6 @@ CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
461# 505#
462# CONFIG_SERIO is not set 506# CONFIG_SERIO is not set
463# CONFIG_GAMEPORT is not set 507# CONFIG_GAMEPORT is not set
464CONFIG_SOUND_GAMEPORT=y
465 508
466# 509#
467# Character devices 510# Character devices
@@ -479,6 +522,8 @@ CONFIG_HW_CONSOLE=y
479# 522#
480# Non-8250 serial port support 523# Non-8250 serial port support
481# 524#
525# CONFIG_SERIAL_AMBA_PL010 is not set
526# CONFIG_SERIAL_AMBA_PL011 is not set
482CONFIG_SERIAL_CORE=y 527CONFIG_SERIAL_CORE=y
483CONFIG_SERIAL_CORE_CONSOLE=y 528CONFIG_SERIAL_CORE_CONSOLE=y
484CONFIG_SERIAL_LH7A40X=y 529CONFIG_SERIAL_LH7A40X=y
@@ -510,7 +555,6 @@ CONFIG_RTC=y
510# 555#
511# TPM devices 556# TPM devices
512# 557#
513# CONFIG_TCG_TPM is not set
514 558
515# 559#
516# I2C support 560# I2C support
@@ -534,18 +578,73 @@ CONFIG_RTC=y
534# 578#
535# Graphics support 579# Graphics support
536# 580#
537# CONFIG_FB is not set 581CONFIG_FB=y
582CONFIG_FB_CFB_FILLRECT=y
583CONFIG_FB_CFB_COPYAREA=y
584CONFIG_FB_CFB_IMAGEBLIT=y
585CONFIG_FB_SOFT_CURSOR=y
586# CONFIG_FB_MACMODES is not set
587# CONFIG_FB_MODE_HELPERS is not set
588# CONFIG_FB_TILEBLITTING is not set
589CONFIG_FB_ARMCLCD=y
590CONFIG_FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT=y
591# CONFIG_FB_ARMCLCD_SHARP_LQ057Q3DC02 is not set
592# CONFIG_FB_ARMCLCD_SHARP_LQ64D343 is not set
593# CONFIG_FB_ARMCLCD_SHARP_LQ10D368 is not set
594# CONFIG_FB_ARMCLCD_SHARP_LQ121S1DG41 is not set
595# CONFIG_FB_S1D13XXX is not set
596# CONFIG_FB_VIRTUAL is not set
538 597
539# 598#
540# Console display driver support 599# Console display driver support
541# 600#
542# CONFIG_VGA_CONSOLE is not set 601# CONFIG_VGA_CONSOLE is not set
543CONFIG_DUMMY_CONSOLE=y 602CONFIG_DUMMY_CONSOLE=y
603# CONFIG_FRAMEBUFFER_CONSOLE is not set
604
605#
606# Logo configuration
607#
608# CONFIG_LOGO is not set
609# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
544 610
545# 611#
546# Sound 612# Sound
547# 613#
548# CONFIG_SOUND is not set 614CONFIG_SOUND=y
615
616#
617# Advanced Linux Sound Architecture
618#
619CONFIG_SND=y
620CONFIG_SND_TIMER=y
621CONFIG_SND_PCM=y
622# CONFIG_SND_SEQUENCER is not set
623CONFIG_SND_OSSEMUL=y
624CONFIG_SND_MIXER_OSS=y
625CONFIG_SND_PCM_OSS=y
626# CONFIG_SND_RTCTIMER is not set
627# CONFIG_SND_VERBOSE_PRINTK is not set
628# CONFIG_SND_DEBUG is not set
629
630#
631# Generic devices
632#
633# CONFIG_SND_DUMMY is not set
634# CONFIG_SND_MTPAV is not set
635# CONFIG_SND_SERIAL_U16550 is not set
636# CONFIG_SND_MPU401 is not set
637CONFIG_SND_AC97_CODEC=y
638
639#
640# ALSA ARM devices
641#
642CONFIG_SND_LH7A40X_AC97=y
643
644#
645# Open Sound System
646#
647# CONFIG_SOUND_PRIME is not set
549 648
550# 649#
551# USB support 650# USB support
diff --git a/arch/arm/configs/lpd7a404_defconfig b/arch/arm/configs/lpd7a404_defconfig
index 208d591ebfce..3a57be32e849 100644
--- a/arch/arm/configs/lpd7a404_defconfig
+++ b/arch/arm/configs/lpd7a404_defconfig
@@ -1,52 +1,58 @@
1# 1#
2# Automatically generated make config: don't edit 2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.12-rc1-bk2 3# Linux kernel version: 2.6.16
4# Mon Mar 28 00:14:08 2005 4# Thu Mar 23 17:50:31 2006
5# 5#
6CONFIG_ARM=y 6CONFIG_ARM=y
7CONFIG_MMU=y 7CONFIG_MMU=y
8CONFIG_UID16=y
9CONFIG_RWSEM_GENERIC_SPINLOCK=y 8CONFIG_RWSEM_GENERIC_SPINLOCK=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y 9CONFIG_GENERIC_CALIBRATE_DELAY=y
11CONFIG_GENERIC_IOMAP=y
12 10
13# 11#
14# Code maturity level options 12# Code maturity level options
15# 13#
16CONFIG_EXPERIMENTAL=y 14CONFIG_EXPERIMENTAL=y
17CONFIG_CLEAN_COMPILE=y
18CONFIG_BROKEN_ON_SMP=y 15CONFIG_BROKEN_ON_SMP=y
19CONFIG_LOCK_KERNEL=y 16CONFIG_LOCK_KERNEL=y
17CONFIG_INIT_ENV_ARG_LIMIT=32
20 18
21# 19#
22# General setup 20# General setup
23# 21#
24CONFIG_LOCALVERSION="" 22CONFIG_LOCALVERSION=""
23CONFIG_LOCALVERSION_AUTO=y
25# CONFIG_SWAP is not set 24# CONFIG_SWAP is not set
26CONFIG_SYSVIPC=y 25CONFIG_SYSVIPC=y
27# CONFIG_POSIX_MQUEUE is not set 26# CONFIG_POSIX_MQUEUE is not set
28# CONFIG_BSD_PROCESS_ACCT is not set 27# CONFIG_BSD_PROCESS_ACCT is not set
29CONFIG_SYSCTL=y 28CONFIG_SYSCTL=y
30# CONFIG_AUDIT is not set 29# CONFIG_AUDIT is not set
31# CONFIG_HOTPLUG is not set
32CONFIG_KOBJECT_UEVENT=y
33CONFIG_IKCONFIG=y 30CONFIG_IKCONFIG=y
34# CONFIG_IKCONFIG_PROC is not set 31# CONFIG_IKCONFIG_PROC is not set
32CONFIG_INITRAMFS_SOURCE=""
33CONFIG_UID16=y
34CONFIG_CC_OPTIMIZE_FOR_SIZE=y
35CONFIG_EMBEDDED=y 35CONFIG_EMBEDDED=y
36CONFIG_KALLSYMS=y 36CONFIG_KALLSYMS=y
37# CONFIG_KALLSYMS_ALL is not set 37# CONFIG_KALLSYMS_ALL is not set
38# CONFIG_KALLSYMS_EXTRA_PASS is not set 38# CONFIG_KALLSYMS_EXTRA_PASS is not set
39# CONFIG_HOTPLUG is not set
40CONFIG_PRINTK=y
41CONFIG_BUG=y
42CONFIG_ELF_CORE=y
39CONFIG_BASE_FULL=y 43CONFIG_BASE_FULL=y
40CONFIG_FUTEX=y 44CONFIG_FUTEX=y
41# CONFIG_EPOLL is not set 45# CONFIG_EPOLL is not set
42CONFIG_CC_OPTIMIZE_FOR_SIZE=y
43CONFIG_SHMEM=y 46CONFIG_SHMEM=y
44CONFIG_CC_ALIGN_FUNCTIONS=0 47CONFIG_CC_ALIGN_FUNCTIONS=0
45CONFIG_CC_ALIGN_LABELS=0 48CONFIG_CC_ALIGN_LABELS=0
46CONFIG_CC_ALIGN_LOOPS=0 49CONFIG_CC_ALIGN_LOOPS=0
47CONFIG_CC_ALIGN_JUMPS=0 50CONFIG_CC_ALIGN_JUMPS=0
51CONFIG_SLAB=y
48# CONFIG_TINY_SHMEM is not set 52# CONFIG_TINY_SHMEM is not set
49CONFIG_BASE_SMALL=0 53CONFIG_BASE_SMALL=0
54# CONFIG_SLOB is not set
55CONFIG_OBSOLETE_INTERMODULE=y
50 56
51# 57#
52# Loadable module support 58# Loadable module support
@@ -54,6 +60,23 @@ CONFIG_BASE_SMALL=0
54# CONFIG_MODULES is not set 60# CONFIG_MODULES is not set
55 61
56# 62#
63# Block layer
64#
65
66#
67# IO Schedulers
68#
69CONFIG_IOSCHED_NOOP=y
70# CONFIG_IOSCHED_AS is not set
71# CONFIG_IOSCHED_DEADLINE is not set
72CONFIG_IOSCHED_CFQ=y
73# CONFIG_DEFAULT_AS is not set
74# CONFIG_DEFAULT_DEADLINE is not set
75CONFIG_DEFAULT_CFQ=y
76# CONFIG_DEFAULT_NOOP is not set
77CONFIG_DEFAULT_IOSCHED="cfq"
78
79#
57# System Type 80# System Type
58# 81#
59# CONFIG_ARCH_CLPS7500 is not set 82# CONFIG_ARCH_CLPS7500 is not set
@@ -71,11 +94,15 @@ CONFIG_BASE_SMALL=0
71# CONFIG_ARCH_SA1100 is not set 94# CONFIG_ARCH_SA1100 is not set
72# CONFIG_ARCH_S3C2410 is not set 95# CONFIG_ARCH_S3C2410 is not set
73# CONFIG_ARCH_SHARK is not set 96# CONFIG_ARCH_SHARK is not set
97# CONFIG_ARCH_LH7952X is not set
74CONFIG_ARCH_LH7A40X=y 98CONFIG_ARCH_LH7A40X=y
75# CONFIG_ARCH_OMAP is not set 99# CONFIG_ARCH_OMAP is not set
76# CONFIG_ARCH_VERSATILE is not set 100# CONFIG_ARCH_VERSATILE is not set
101# CONFIG_ARCH_REALVIEW is not set
77# CONFIG_ARCH_IMX is not set 102# CONFIG_ARCH_IMX is not set
78# CONFIG_ARCH_H720X is not set 103# CONFIG_ARCH_H720X is not set
104# CONFIG_ARCH_AAEC2000 is not set
105# CONFIG_ARCH_AT91RM9200 is not set
79 106
80# 107#
81# LH7A40X Implementations 108# LH7A40X Implementations
@@ -110,6 +137,7 @@ CONFIG_ARM_THUMB=y
110# 137#
111# Bus support 138# Bus support
112# 139#
140CONFIG_ARM_AMBA=y
113 141
114# 142#
115# PCCARD (PCMCIA/CardBus) support 143# PCCARD (PCMCIA/CardBus) support
@@ -120,7 +148,18 @@ CONFIG_ARM_THUMB=y
120# Kernel Features 148# Kernel Features
121# 149#
122CONFIG_PREEMPT=y 150CONFIG_PREEMPT=y
151# CONFIG_NO_IDLE_HZ is not set
152# CONFIG_AEABI is not set
153CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
154CONFIG_SELECT_MEMORY_MODEL=y
155# CONFIG_FLATMEM_MANUAL is not set
156CONFIG_DISCONTIGMEM_MANUAL=y
157# CONFIG_SPARSEMEM_MANUAL is not set
123CONFIG_DISCONTIGMEM=y 158CONFIG_DISCONTIGMEM=y
159CONFIG_FLAT_NODE_MEM_MAP=y
160CONFIG_NEED_MULTIPLE_NODES=y
161# CONFIG_SPARSEMEM_STATIC is not set
162CONFIG_SPLIT_PTLOCK_CPUS=4096
124CONFIG_ALIGNMENT_TRAP=y 163CONFIG_ALIGNMENT_TRAP=y
125 164
126# 165#
@@ -154,6 +193,84 @@ CONFIG_BINFMT_ELF=y
154# Power management options 193# Power management options
155# 194#
156# CONFIG_PM is not set 195# CONFIG_PM is not set
196# CONFIG_APM is not set
197
198#
199# Networking
200#
201CONFIG_NET=y
202
203#
204# Networking options
205#
206# CONFIG_NETDEBUG is not set
207CONFIG_PACKET=y
208# CONFIG_PACKET_MMAP is not set
209CONFIG_UNIX=y
210# CONFIG_NET_KEY is not set
211CONFIG_INET=y
212# CONFIG_IP_MULTICAST is not set
213# CONFIG_IP_ADVANCED_ROUTER is not set
214CONFIG_IP_FIB_HASH=y
215CONFIG_IP_PNP=y
216CONFIG_IP_PNP_DHCP=y
217CONFIG_IP_PNP_BOOTP=y
218CONFIG_IP_PNP_RARP=y
219# CONFIG_NET_IPIP is not set
220# CONFIG_NET_IPGRE is not set
221# CONFIG_ARPD is not set
222# CONFIG_SYN_COOKIES is not set
223# CONFIG_INET_AH is not set
224# CONFIG_INET_ESP is not set
225# CONFIG_INET_IPCOMP is not set
226# CONFIG_INET_TUNNEL is not set
227CONFIG_INET_DIAG=y
228CONFIG_INET_TCP_DIAG=y
229# CONFIG_TCP_CONG_ADVANCED is not set
230CONFIG_TCP_CONG_BIC=y
231# CONFIG_IPV6 is not set
232# CONFIG_NETFILTER is not set
233
234#
235# DCCP Configuration (EXPERIMENTAL)
236#
237# CONFIG_IP_DCCP is not set
238
239#
240# SCTP Configuration (EXPERIMENTAL)
241#
242# CONFIG_IP_SCTP is not set
243
244#
245# TIPC Configuration (EXPERIMENTAL)
246#
247# CONFIG_TIPC is not set
248# CONFIG_ATM is not set
249# CONFIG_BRIDGE is not set
250# CONFIG_VLAN_8021Q is not set
251# CONFIG_DECNET is not set
252# CONFIG_LLC2 is not set
253# CONFIG_IPX is not set
254# CONFIG_ATALK is not set
255# CONFIG_X25 is not set
256# CONFIG_LAPB is not set
257# CONFIG_NET_DIVERT is not set
258# CONFIG_ECONET is not set
259# CONFIG_WAN_ROUTER is not set
260
261#
262# QoS and/or fair queueing
263#
264# CONFIG_NET_SCHED is not set
265
266#
267# Network testing
268#
269# CONFIG_NET_PKTGEN is not set
270# CONFIG_HAMRADIO is not set
271# CONFIG_IRDA is not set
272# CONFIG_BT is not set
273# CONFIG_IEEE80211 is not set
157 274
158# 275#
159# Device Drivers 276# Device Drivers
@@ -168,6 +285,11 @@ CONFIG_PREVENT_FIRMWARE_BUILD=y
168# CONFIG_DEBUG_DRIVER is not set 285# CONFIG_DEBUG_DRIVER is not set
169 286
170# 287#
288# Connector - unified userspace <-> kernelspace linker
289#
290# CONFIG_CONNECTOR is not set
291
292#
171# Memory Technology Devices (MTD) 293# Memory Technology Devices (MTD)
172# 294#
173CONFIG_MTD=y 295CONFIG_MTD=y
@@ -175,7 +297,7 @@ CONFIG_MTD=y
175# CONFIG_MTD_CONCAT is not set 297# CONFIG_MTD_CONCAT is not set
176CONFIG_MTD_PARTITIONS=y 298CONFIG_MTD_PARTITIONS=y
177# CONFIG_MTD_REDBOOT_PARTS is not set 299# CONFIG_MTD_REDBOOT_PARTS is not set
178# CONFIG_MTD_CMDLINE_PARTS is not set 300CONFIG_MTD_CMDLINE_PARTS=y
179# CONFIG_MTD_AFS_PARTS is not set 301# CONFIG_MTD_AFS_PARTS is not set
180 302
181# 303#
@@ -186,6 +308,7 @@ CONFIG_MTD_BLOCK=y
186# CONFIG_FTL is not set 308# CONFIG_FTL is not set
187# CONFIG_NFTL is not set 309# CONFIG_NFTL is not set
188# CONFIG_INFTL is not set 310# CONFIG_INFTL is not set
311# CONFIG_RFD_FTL is not set
189 312
190# 313#
191# RAM/ROM/Flash chip drivers 314# RAM/ROM/Flash chip drivers
@@ -211,15 +334,18 @@ CONFIG_MTD_CFI_UTIL=y
211# CONFIG_MTD_RAM is not set 334# CONFIG_MTD_RAM is not set
212# CONFIG_MTD_ROM is not set 335# CONFIG_MTD_ROM is not set
213# CONFIG_MTD_ABSENT is not set 336# CONFIG_MTD_ABSENT is not set
214# CONFIG_MTD_XIP is not set 337# CONFIG_MTD_OBSOLETE_CHIPS is not set
215 338
216# 339#
217# Mapping drivers for chip access 340# Mapping drivers for chip access
218# 341#
219# CONFIG_MTD_COMPLEX_MAPPINGS is not set 342# CONFIG_MTD_COMPLEX_MAPPINGS is not set
220# CONFIG_MTD_PHYSMAP is not set 343CONFIG_MTD_PHYSMAP=y
344CONFIG_MTD_PHYSMAP_START=0x00000000
345CONFIG_MTD_PHYSMAP_LEN=0x04000000
346CONFIG_MTD_PHYSMAP_BANKWIDTH=4
221# CONFIG_MTD_ARM_INTEGRATOR is not set 347# CONFIG_MTD_ARM_INTEGRATOR is not set
222# CONFIG_MTD_EDB7312 is not set 348# CONFIG_MTD_PLATRAM is not set
223 349
224# 350#
225# Self-contained MTD device drivers 351# Self-contained MTD device drivers
@@ -243,6 +369,11 @@ CONFIG_MTD_CFI_UTIL=y
243# CONFIG_MTD_NAND is not set 369# CONFIG_MTD_NAND is not set
244 370
245# 371#
372# OneNAND Flash Device Drivers
373#
374# CONFIG_MTD_ONENAND is not set
375
376#
246# Parallel port support 377# Parallel port support
247# 378#
248# CONFIG_PARPORT is not set 379# CONFIG_PARPORT is not set
@@ -254,7 +385,6 @@ CONFIG_MTD_CFI_UTIL=y
254# 385#
255# Block devices 386# Block devices
256# 387#
257# CONFIG_BLK_DEV_FD is not set
258# CONFIG_BLK_DEV_COW_COMMON is not set 388# CONFIG_BLK_DEV_COW_COMMON is not set
259CONFIG_BLK_DEV_LOOP=y 389CONFIG_BLK_DEV_LOOP=y
260# CONFIG_BLK_DEV_CRYPTOLOOP is not set 390# CONFIG_BLK_DEV_CRYPTOLOOP is not set
@@ -262,16 +392,7 @@ CONFIG_BLK_DEV_LOOP=y
262# CONFIG_BLK_DEV_UB is not set 392# CONFIG_BLK_DEV_UB is not set
263# CONFIG_BLK_DEV_RAM is not set 393# CONFIG_BLK_DEV_RAM is not set
264CONFIG_BLK_DEV_RAM_COUNT=16 394CONFIG_BLK_DEV_RAM_COUNT=16
265CONFIG_INITRAMFS_SOURCE=""
266# CONFIG_CDROM_PKTCDVD is not set 395# CONFIG_CDROM_PKTCDVD is not set
267
268#
269# IO Schedulers
270#
271CONFIG_IOSCHED_NOOP=y
272# CONFIG_IOSCHED_AS is not set
273# CONFIG_IOSCHED_DEADLINE is not set
274CONFIG_IOSCHED_CFQ=y
275# CONFIG_ATA_OVER_ETH is not set 396# CONFIG_ATA_OVER_ETH is not set
276 397
277# 398#
@@ -291,12 +412,13 @@ CONFIG_BLK_DEV_IDEDISK=y
291# CONFIG_BLK_DEV_IDEFLOPPY is not set 412# CONFIG_BLK_DEV_IDEFLOPPY is not set
292# CONFIG_BLK_DEV_IDESCSI is not set 413# CONFIG_BLK_DEV_IDESCSI is not set
293# CONFIG_IDE_TASK_IOCTL is not set 414# CONFIG_IDE_TASK_IOCTL is not set
415CONFIG_IDE_POLL=y
294 416
295# 417#
296# IDE chipset support/bugfixes 418# IDE chipset support/bugfixes
297# 419#
298CONFIG_IDE_GENERIC=y 420CONFIG_IDE_GENERIC=y
299# CONFIG_IDE_ARM is not set 421CONFIG_IDE_ARM=y
300# CONFIG_BLK_DEV_IDEDMA is not set 422# CONFIG_BLK_DEV_IDEDMA is not set
301# CONFIG_IDEDMA_AUTO is not set 423# CONFIG_IDEDMA_AUTO is not set
302# CONFIG_BLK_DEV_HD is not set 424# CONFIG_BLK_DEV_HD is not set
@@ -304,6 +426,7 @@ CONFIG_IDE_GENERIC=y
304# 426#
305# SCSI device support 427# SCSI device support
306# 428#
429# CONFIG_RAID_ATTRS is not set
307CONFIG_SCSI=y 430CONFIG_SCSI=y
308# CONFIG_SCSI_PROC_FS is not set 431# CONFIG_SCSI_PROC_FS is not set
309 432
@@ -315,6 +438,7 @@ CONFIG_SCSI=y
315# CONFIG_CHR_DEV_OSST is not set 438# CONFIG_CHR_DEV_OSST is not set
316# CONFIG_BLK_DEV_SR is not set 439# CONFIG_BLK_DEV_SR is not set
317# CONFIG_CHR_DEV_SG is not set 440# CONFIG_CHR_DEV_SG is not set
441# CONFIG_CHR_DEV_SCH is not set
318 442
319# 443#
320# Some SCSI devices (e.g. CD jukebox) support multiple LUNs 444# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
@@ -329,10 +453,12 @@ CONFIG_SCSI=y
329# CONFIG_SCSI_SPI_ATTRS is not set 453# CONFIG_SCSI_SPI_ATTRS is not set
330# CONFIG_SCSI_FC_ATTRS is not set 454# CONFIG_SCSI_FC_ATTRS is not set
331# CONFIG_SCSI_ISCSI_ATTRS is not set 455# CONFIG_SCSI_ISCSI_ATTRS is not set
456# CONFIG_SCSI_SAS_ATTRS is not set
332 457
333# 458#
334# SCSI low-level drivers 459# SCSI low-level drivers
335# 460#
461# CONFIG_ISCSI_TCP is not set
336# CONFIG_SCSI_SATA is not set 462# CONFIG_SCSI_SATA is not set
337# CONFIG_SCSI_DEBUG is not set 463# CONFIG_SCSI_DEBUG is not set
338 464
@@ -344,6 +470,7 @@ CONFIG_SCSI=y
344# 470#
345# Fusion MPT device support 471# Fusion MPT device support
346# 472#
473# CONFIG_FUSION is not set
347 474
348# 475#
349# IEEE 1394 (FireWire) support 476# IEEE 1394 (FireWire) support
@@ -354,70 +481,8 @@ CONFIG_SCSI=y
354# 481#
355 482
356# 483#
357# Networking support 484# Network device support
358# 485#
359CONFIG_NET=y
360
361#
362# Networking options
363#
364CONFIG_PACKET=y
365# CONFIG_PACKET_MMAP is not set
366# CONFIG_NETLINK_DEV is not set
367CONFIG_UNIX=y
368# CONFIG_NET_KEY is not set
369CONFIG_INET=y
370# CONFIG_IP_MULTICAST is not set
371# CONFIG_IP_ADVANCED_ROUTER is not set
372CONFIG_IP_PNP=y
373CONFIG_IP_PNP_DHCP=y
374CONFIG_IP_PNP_BOOTP=y
375CONFIG_IP_PNP_RARP=y
376# CONFIG_NET_IPIP is not set
377# CONFIG_NET_IPGRE is not set
378# CONFIG_ARPD is not set
379# CONFIG_SYN_COOKIES is not set
380# CONFIG_INET_AH is not set
381# CONFIG_INET_ESP is not set
382# CONFIG_INET_IPCOMP is not set
383# CONFIG_INET_TUNNEL is not set
384# CONFIG_IP_TCPDIAG is not set
385# CONFIG_IP_TCPDIAG_IPV6 is not set
386# CONFIG_IPV6 is not set
387# CONFIG_NETFILTER is not set
388
389#
390# SCTP Configuration (EXPERIMENTAL)
391#
392# CONFIG_IP_SCTP is not set
393# CONFIG_ATM is not set
394# CONFIG_BRIDGE is not set
395# CONFIG_VLAN_8021Q is not set
396# CONFIG_DECNET is not set
397# CONFIG_LLC2 is not set
398# CONFIG_IPX is not set
399# CONFIG_ATALK is not set
400# CONFIG_X25 is not set
401# CONFIG_LAPB is not set
402# CONFIG_NET_DIVERT is not set
403# CONFIG_ECONET is not set
404# CONFIG_WAN_ROUTER is not set
405
406#
407# QoS and/or fair queueing
408#
409# CONFIG_NET_SCHED is not set
410# CONFIG_NET_CLS_ROUTE is not set
411
412#
413# Network testing
414#
415# CONFIG_NET_PKTGEN is not set
416# CONFIG_NETPOLL is not set
417# CONFIG_NET_POLL_CONTROLLER is not set
418# CONFIG_HAMRADIO is not set
419# CONFIG_IRDA is not set
420# CONFIG_BT is not set
421CONFIG_NETDEVICES=y 486CONFIG_NETDEVICES=y
422# CONFIG_DUMMY is not set 487# CONFIG_DUMMY is not set
423# CONFIG_BONDING is not set 488# CONFIG_BONDING is not set
@@ -425,11 +490,17 @@ CONFIG_NETDEVICES=y
425# CONFIG_TUN is not set 490# CONFIG_TUN is not set
426 491
427# 492#
493# PHY device support
494#
495# CONFIG_PHYLIB is not set
496
497#
428# Ethernet (10 or 100Mbit) 498# Ethernet (10 or 100Mbit)
429# 499#
430CONFIG_NET_ETHERNET=y 500CONFIG_NET_ETHERNET=y
431CONFIG_MII=y 501CONFIG_MII=y
432CONFIG_SMC91X=y 502CONFIG_SMC91X=y
503# CONFIG_DM9000 is not set
433 504
434# 505#
435# Ethernet (1000 Mbit) 506# Ethernet (1000 Mbit)
@@ -456,6 +527,8 @@ CONFIG_SMC91X=y
456# CONFIG_SLIP is not set 527# CONFIG_SLIP is not set
457# CONFIG_SHAPER is not set 528# CONFIG_SHAPER is not set
458# CONFIG_NETCONSOLE is not set 529# CONFIG_NETCONSOLE is not set
530# CONFIG_NETPOLL is not set
531# CONFIG_NET_POLL_CONTROLLER is not set
459 532
460# 533#
461# ISDN subsystem 534# ISDN subsystem
@@ -470,10 +543,13 @@ CONFIG_INPUT=y
470# 543#
471# Userland interfaces 544# Userland interfaces
472# 545#
473# CONFIG_INPUT_MOUSEDEV is not set 546CONFIG_INPUT_MOUSEDEV=y
547# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
548CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
549CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
474# CONFIG_INPUT_JOYDEV is not set 550# CONFIG_INPUT_JOYDEV is not set
475# CONFIG_INPUT_TSDEV is not set 551# CONFIG_INPUT_TSDEV is not set
476# CONFIG_INPUT_EVDEV is not set 552CONFIG_INPUT_EVDEV=y
477# CONFIG_INPUT_EVBUG is not set 553# CONFIG_INPUT_EVBUG is not set
478 554
479# 555#
@@ -482,7 +558,13 @@ CONFIG_INPUT=y
482# CONFIG_INPUT_KEYBOARD is not set 558# CONFIG_INPUT_KEYBOARD is not set
483# CONFIG_INPUT_MOUSE is not set 559# CONFIG_INPUT_MOUSE is not set
484# CONFIG_INPUT_JOYSTICK is not set 560# CONFIG_INPUT_JOYSTICK is not set
485# CONFIG_INPUT_TOUCHSCREEN is not set 561CONFIG_INPUT_TOUCHSCREEN=y
562# CONFIG_TOUCHSCREEN_GUNZE is not set
563# CONFIG_TOUCHSCREEN_ELO is not set
564# CONFIG_TOUCHSCREEN_MTOUCH is not set
565# CONFIG_TOUCHSCREEN_MK712 is not set
566CONFIG_TOUCHSCREEN_ADC_LH7=y
567CONFIG_HAS_TOUCHSCREEN_ADC_LH7=y
486# CONFIG_INPUT_MISC is not set 568# CONFIG_INPUT_MISC is not set
487 569
488# 570#
@@ -490,7 +572,6 @@ CONFIG_INPUT=y
490# 572#
491# CONFIG_SERIO is not set 573# CONFIG_SERIO is not set
492# CONFIG_GAMEPORT is not set 574# CONFIG_GAMEPORT is not set
493CONFIG_SOUND_GAMEPORT=y
494 575
495# 576#
496# Character devices 577# Character devices
@@ -508,6 +589,8 @@ CONFIG_HW_CONSOLE=y
508# 589#
509# Non-8250 serial port support 590# Non-8250 serial port support
510# 591#
592# CONFIG_SERIAL_AMBA_PL010 is not set
593# CONFIG_SERIAL_AMBA_PL011 is not set
511CONFIG_SERIAL_CORE=y 594CONFIG_SERIAL_CORE=y
512CONFIG_SERIAL_CORE_CONSOLE=y 595CONFIG_SERIAL_CORE_CONSOLE=y
513CONFIG_SERIAL_LH7A40X=y 596CONFIG_SERIAL_LH7A40X=y
@@ -533,13 +616,13 @@ CONFIG_RTC=y
533# 616#
534# Ftape, the floppy tape device driver 617# Ftape, the floppy tape device driver
535# 618#
536# CONFIG_DRM is not set
537# CONFIG_RAW_DRIVER is not set 619# CONFIG_RAW_DRIVER is not set
538 620
539# 621#
540# TPM devices 622# TPM devices
541# 623#
542# CONFIG_TCG_TPM is not set 624# CONFIG_TCG_TPM is not set
625# CONFIG_TELCLOCK is not set
543 626
544# 627#
545# I2C support 628# I2C support
@@ -547,10 +630,33 @@ CONFIG_RTC=y
547# CONFIG_I2C is not set 630# CONFIG_I2C is not set
548 631
549# 632#
633# SPI support
634#
635# CONFIG_SPI is not set
636# CONFIG_SPI_MASTER is not set
637
638#
639# Dallas's 1-wire bus
640#
641# CONFIG_W1 is not set
642
643#
644# Hardware Monitoring support
645#
646CONFIG_HWMON=y
647# CONFIG_HWMON_VID is not set
648# CONFIG_SENSORS_F71805F is not set
649# CONFIG_HWMON_DEBUG_CHIP is not set
650
651#
550# Misc devices 652# Misc devices
551# 653#
552 654
553# 655#
656# Multimedia Capabilities Port drivers
657#
658
659#
554# Multimedia devices 660# Multimedia devices
555# 661#
556# CONFIG_VIDEO_DEV is not set 662# CONFIG_VIDEO_DEV is not set
@@ -563,18 +669,83 @@ CONFIG_RTC=y
563# 669#
564# Graphics support 670# Graphics support
565# 671#
566# CONFIG_FB is not set 672CONFIG_FB=y
673CONFIG_FB_CFB_FILLRECT=y
674CONFIG_FB_CFB_COPYAREA=y
675CONFIG_FB_CFB_IMAGEBLIT=y
676# CONFIG_FB_MACMODES is not set
677# CONFIG_FB_MODE_HELPERS is not set
678# CONFIG_FB_TILEBLITTING is not set
679CONFIG_FB_ARMCLCD=y
680CONFIG_FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT=y
681# CONFIG_FB_ARMCLCD_SHARP_LQ057Q3DC02 is not set
682# CONFIG_FB_ARMCLCD_SHARP_LQ64D343 is not set
683# CONFIG_FB_ARMCLCD_SHARP_LQ10D368 is not set
684# CONFIG_FB_ARMCLCD_SHARP_LQ121S1DG41 is not set
685# CONFIG_FB_ARMCLCD_AUO_A070VW01_WIDE is not set
686# CONFIG_FB_ARMCLCD_HITACHI is not set
687# CONFIG_FB_S1D13XXX is not set
688# CONFIG_FB_VIRTUAL is not set
567 689
568# 690#
569# Console display driver support 691# Console display driver support
570# 692#
571# CONFIG_VGA_CONSOLE is not set 693# CONFIG_VGA_CONSOLE is not set
572CONFIG_DUMMY_CONSOLE=y 694CONFIG_DUMMY_CONSOLE=y
695# CONFIG_FRAMEBUFFER_CONSOLE is not set
696
697#
698# Logo configuration
699#
700# CONFIG_LOGO is not set
701# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
573 702
574# 703#
575# Sound 704# Sound
576# 705#
577# CONFIG_SOUND is not set 706CONFIG_SOUND=y
707
708#
709# Advanced Linux Sound Architecture
710#
711CONFIG_SND=y
712CONFIG_SND_TIMER=y
713CONFIG_SND_PCM=y
714# CONFIG_SND_SEQUENCER is not set
715CONFIG_SND_OSSEMUL=y
716CONFIG_SND_MIXER_OSS=y
717CONFIG_SND_PCM_OSS=y
718# CONFIG_SND_RTCTIMER is not set
719# CONFIG_SND_DYNAMIC_MINORS is not set
720CONFIG_SND_SUPPORT_OLD_API=y
721# CONFIG_SND_VERBOSE_PRINTK is not set
722# CONFIG_SND_DEBUG is not set
723
724#
725# Generic devices
726#
727CONFIG_SND_AC97_CODEC=y
728CONFIG_SND_AC97_BUS=y
729# CONFIG_SND_DUMMY is not set
730# CONFIG_SND_MTPAV is not set
731# CONFIG_SND_SERIAL_U16550 is not set
732# CONFIG_SND_MPU401 is not set
733
734#
735# ALSA ARM devices
736#
737# CONFIG_SND_ARMAACI is not set
738CONFIG_SND_LH7A40X_AC97=y
739
740#
741# USB devices
742#
743# CONFIG_SND_USB_AUDIO is not set
744
745#
746# Open Sound System
747#
748# CONFIG_SOUND_PRIME is not set
578 749
579# 750#
580# USB support 751# USB support
@@ -595,6 +766,7 @@ CONFIG_USB_DEVICEFS=y
595# 766#
596# USB Host Controller Drivers 767# USB Host Controller Drivers
597# 768#
769# CONFIG_USB_ISP116X_HCD is not set
598CONFIG_USB_OHCI_HCD=y 770CONFIG_USB_OHCI_HCD=y
599# CONFIG_USB_OHCI_BIG_ENDIAN is not set 771# CONFIG_USB_OHCI_BIG_ENDIAN is not set
600CONFIG_USB_OHCI_LITTLE_ENDIAN=y 772CONFIG_USB_OHCI_LITTLE_ENDIAN=y
@@ -603,16 +775,19 @@ CONFIG_USB_OHCI_LITTLE_ENDIAN=y
603# 775#
604# USB Device Class drivers 776# USB Device Class drivers
605# 777#
606# CONFIG_USB_BLUETOOTH_TTY is not set 778# CONFIG_OBSOLETE_OSS_USB_DRIVER is not set
607# CONFIG_USB_ACM is not set 779# CONFIG_USB_ACM is not set
608# CONFIG_USB_PRINTER is not set 780# CONFIG_USB_PRINTER is not set
609 781
610# 782#
611# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' may also be needed; see USB_STORAGE Help for more information 783# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
784#
785
786#
787# may also be needed; see USB_STORAGE Help for more information
612# 788#
613CONFIG_USB_STORAGE=y 789CONFIG_USB_STORAGE=y
614CONFIG_USB_STORAGE_DEBUG=y 790CONFIG_USB_STORAGE_DEBUG=y
615# CONFIG_USB_STORAGE_RW_DETECT is not set
616CONFIG_USB_STORAGE_DATAFAB=y 791CONFIG_USB_STORAGE_DATAFAB=y
617# CONFIG_USB_STORAGE_FREECOM is not set 792# CONFIG_USB_STORAGE_FREECOM is not set
618# CONFIG_USB_STORAGE_ISD200 is not set 793# CONFIG_USB_STORAGE_ISD200 is not set
@@ -621,22 +796,32 @@ CONFIG_USB_STORAGE_DATAFAB=y
621# CONFIG_USB_STORAGE_SDDR09 is not set 796# CONFIG_USB_STORAGE_SDDR09 is not set
622# CONFIG_USB_STORAGE_SDDR55 is not set 797# CONFIG_USB_STORAGE_SDDR55 is not set
623# CONFIG_USB_STORAGE_JUMPSHOT is not set 798# CONFIG_USB_STORAGE_JUMPSHOT is not set
799# CONFIG_USB_STORAGE_ALAUDA is not set
800# CONFIG_USB_STORAGE_ONETOUCH is not set
801# CONFIG_USB_LIBUSUAL is not set
624 802
625# 803#
626# USB Input Devices 804# USB Input Devices
627# 805#
628CONFIG_USB_HID=y 806CONFIG_USB_HID=y
629CONFIG_USB_HIDINPUT=y 807CONFIG_USB_HIDINPUT=y
808# CONFIG_USB_HIDINPUT_POWERBOOK is not set
630# CONFIG_HID_FF is not set 809# CONFIG_HID_FF is not set
631# CONFIG_USB_HIDDEV is not set 810# CONFIG_USB_HIDDEV is not set
632# CONFIG_USB_AIPTEK is not set 811# CONFIG_USB_AIPTEK is not set
633# CONFIG_USB_WACOM is not set 812# CONFIG_USB_WACOM is not set
813# CONFIG_USB_ACECAD is not set
634# CONFIG_USB_KBTAB is not set 814# CONFIG_USB_KBTAB is not set
635# CONFIG_USB_POWERMATE is not set 815# CONFIG_USB_POWERMATE is not set
636# CONFIG_USB_MTOUCH is not set 816# CONFIG_USB_MTOUCH is not set
817# CONFIG_USB_ITMTOUCH is not set
637# CONFIG_USB_EGALAX is not set 818# CONFIG_USB_EGALAX is not set
819# CONFIG_USB_YEALINK is not set
638# CONFIG_USB_XPAD is not set 820# CONFIG_USB_XPAD is not set
639# CONFIG_USB_ATI_REMOTE is not set 821# CONFIG_USB_ATI_REMOTE is not set
822# CONFIG_USB_ATI_REMOTE2 is not set
823# CONFIG_USB_KEYSPAN_REMOTE is not set
824# CONFIG_USB_APPLETOUCH is not set
640 825
641# 826#
642# USB Imaging devices 827# USB Imaging devices
@@ -686,16 +871,33 @@ CONFIG_USB_MON=y
686# CONFIG_USB_PHIDGETKIT is not set 871# CONFIG_USB_PHIDGETKIT is not set
687# CONFIG_USB_PHIDGETSERVO is not set 872# CONFIG_USB_PHIDGETSERVO is not set
688# CONFIG_USB_IDMOUSE is not set 873# CONFIG_USB_IDMOUSE is not set
874# CONFIG_USB_LD is not set
689# CONFIG_USB_TEST is not set 875# CONFIG_USB_TEST is not set
690 876
691# 877#
692# USB ATM/DSL drivers 878# USB DSL modem support
693# 879#
694 880
695# 881#
696# USB Gadget Support 882# USB Gadget Support
697# 883#
698# CONFIG_USB_GADGET is not set 884CONFIG_USB_GADGET=y
885# CONFIG_USB_GADGET_DEBUG_FILES is not set
886CONFIG_USB_GADGET_SELECTED=y
887# CONFIG_USB_GADGET_NET2280 is not set
888# CONFIG_USB_GADGET_PXA2XX is not set
889# CONFIG_USB_GADGET_GOKU is not set
890# CONFIG_USB_GADGET_LH7A40X is not set
891CONFIG_USB_GADGET_LH7=y
892CONFIG_USB_LH7=y
893# CONFIG_USB_GADGET_OMAP is not set
894# CONFIG_USB_GADGET_DUMMY_HCD is not set
895# CONFIG_USB_GADGET_DUALSPEED is not set
896CONFIG_USB_ZERO=y
897# CONFIG_USB_ETH is not set
898# CONFIG_USB_GADGETFS is not set
899# CONFIG_USB_FILE_STORAGE is not set
900# CONFIG_USB_G_SERIAL is not set
699 901
700# 902#
701# MMC/SD Card support 903# MMC/SD Card support
@@ -707,6 +909,7 @@ CONFIG_USB_MON=y
707# 909#
708CONFIG_EXT2_FS=y 910CONFIG_EXT2_FS=y
709# CONFIG_EXT2_FS_XATTR is not set 911# CONFIG_EXT2_FS_XATTR is not set
912# CONFIG_EXT2_FS_XIP is not set
710CONFIG_EXT3_FS=y 913CONFIG_EXT3_FS=y
711CONFIG_EXT3_FS_XATTR=y 914CONFIG_EXT3_FS_XATTR=y
712# CONFIG_EXT3_FS_POSIX_ACL is not set 915# CONFIG_EXT3_FS_POSIX_ACL is not set
@@ -716,17 +919,17 @@ CONFIG_JBD=y
716CONFIG_FS_MBCACHE=y 919CONFIG_FS_MBCACHE=y
717# CONFIG_REISERFS_FS is not set 920# CONFIG_REISERFS_FS is not set
718# CONFIG_JFS_FS is not set 921# CONFIG_JFS_FS is not set
719 922# CONFIG_FS_POSIX_ACL is not set
720#
721# XFS support
722#
723# CONFIG_XFS_FS is not set 923# CONFIG_XFS_FS is not set
924# CONFIG_OCFS2_FS is not set
724# CONFIG_MINIX_FS is not set 925# CONFIG_MINIX_FS is not set
725# CONFIG_ROMFS_FS is not set 926# CONFIG_ROMFS_FS is not set
927CONFIG_INOTIFY=y
726# CONFIG_QUOTA is not set 928# CONFIG_QUOTA is not set
727CONFIG_DNOTIFY=y 929CONFIG_DNOTIFY=y
728# CONFIG_AUTOFS_FS is not set 930# CONFIG_AUTOFS_FS is not set
729# CONFIG_AUTOFS4_FS is not set 931# CONFIG_AUTOFS4_FS is not set
932# CONFIG_FUSE_FS is not set
730 933
731# 934#
732# CD-ROM/DVD Filesystems 935# CD-ROM/DVD Filesystems
@@ -749,12 +952,11 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
749# 952#
750CONFIG_PROC_FS=y 953CONFIG_PROC_FS=y
751CONFIG_SYSFS=y 954CONFIG_SYSFS=y
752# CONFIG_DEVFS_FS is not set
753# CONFIG_DEVPTS_FS_XATTR is not set
754CONFIG_TMPFS=y 955CONFIG_TMPFS=y
755# CONFIG_TMPFS_XATTR is not set
756# CONFIG_HUGETLB_PAGE is not set 956# CONFIG_HUGETLB_PAGE is not set
757CONFIG_RAMFS=y 957CONFIG_RAMFS=y
958# CONFIG_RELAYFS_FS is not set
959# CONFIG_CONFIGFS_FS is not set
758 960
759# 961#
760# Miscellaneous filesystems 962# Miscellaneous filesystems
@@ -769,8 +971,8 @@ CONFIG_RAMFS=y
769# CONFIG_JFFS_FS is not set 971# CONFIG_JFFS_FS is not set
770CONFIG_JFFS2_FS=y 972CONFIG_JFFS2_FS=y
771CONFIG_JFFS2_FS_DEBUG=0 973CONFIG_JFFS2_FS_DEBUG=0
772# CONFIG_JFFS2_FS_NAND is not set 974CONFIG_JFFS2_FS_WRITEBUFFER=y
773# CONFIG_JFFS2_FS_NOR_ECC is not set 975# CONFIG_JFFS2_SUMMARY is not set
774# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set 976# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
775CONFIG_JFFS2_ZLIB=y 977CONFIG_JFFS2_ZLIB=y
776CONFIG_JFFS2_RTIME=y 978CONFIG_JFFS2_RTIME=y
@@ -787,12 +989,14 @@ CONFIG_CRAMFS=y
787# 989#
788CONFIG_NFS_FS=y 990CONFIG_NFS_FS=y
789CONFIG_NFS_V3=y 991CONFIG_NFS_V3=y
992# CONFIG_NFS_V3_ACL is not set
790# CONFIG_NFS_V4 is not set 993# CONFIG_NFS_V4 is not set
791# CONFIG_NFS_DIRECTIO is not set 994# CONFIG_NFS_DIRECTIO is not set
792# CONFIG_NFSD is not set 995# CONFIG_NFSD is not set
793CONFIG_ROOT_NFS=y 996CONFIG_ROOT_NFS=y
794CONFIG_LOCKD=y 997CONFIG_LOCKD=y
795CONFIG_LOCKD_V4=y 998CONFIG_LOCKD_V4=y
999CONFIG_NFS_COMMON=y
796CONFIG_SUNRPC=y 1000CONFIG_SUNRPC=y
797# CONFIG_RPCSEC_GSS_KRB5 is not set 1001# CONFIG_RPCSEC_GSS_KRB5 is not set
798# CONFIG_RPCSEC_GSS_SPKM3 is not set 1002# CONFIG_RPCSEC_GSS_SPKM3 is not set
@@ -801,6 +1005,7 @@ CONFIG_SUNRPC=y
801# CONFIG_NCP_FS is not set 1005# CONFIG_NCP_FS is not set
802# CONFIG_CODA_FS is not set 1006# CONFIG_CODA_FS is not set
803# CONFIG_AFS_FS is not set 1007# CONFIG_AFS_FS is not set
1008# CONFIG_9P_FS is not set
804 1009
805# 1010#
806# Partition Types 1011# Partition Types
@@ -820,6 +1025,7 @@ CONFIG_MSDOS_PARTITION=y
820# CONFIG_SGI_PARTITION is not set 1025# CONFIG_SGI_PARTITION is not set
821# CONFIG_ULTRIX_PARTITION is not set 1026# CONFIG_ULTRIX_PARTITION is not set
822# CONFIG_SUN_PARTITION is not set 1027# CONFIG_SUN_PARTITION is not set
1028# CONFIG_KARMA_PARTITION is not set
823# CONFIG_EFI_PARTITION is not set 1029# CONFIG_EFI_PARTITION is not set
824 1030
825# 1031#
@@ -875,19 +1081,24 @@ CONFIG_NLS_DEFAULT="iso8859-1"
875# Kernel hacking 1081# Kernel hacking
876# 1082#
877# CONFIG_PRINTK_TIME is not set 1083# CONFIG_PRINTK_TIME is not set
878CONFIG_DEBUG_KERNEL=y
879CONFIG_MAGIC_SYSRQ=y 1084CONFIG_MAGIC_SYSRQ=y
880CONFIG_LOG_BUF_SHIFT=14 1085CONFIG_DEBUG_KERNEL=y
1086CONFIG_LOG_BUF_SHIFT=16
1087CONFIG_DETECT_SOFTLOCKUP=y
881# CONFIG_SCHEDSTATS is not set 1088# CONFIG_SCHEDSTATS is not set
882# CONFIG_DEBUG_SLAB is not set 1089# CONFIG_DEBUG_SLAB is not set
883CONFIG_DEBUG_PREEMPT=y 1090CONFIG_DEBUG_PREEMPT=y
1091CONFIG_DEBUG_MUTEXES=y
884# CONFIG_DEBUG_SPINLOCK is not set 1092# CONFIG_DEBUG_SPINLOCK is not set
885# CONFIG_DEBUG_SPINLOCK_SLEEP is not set 1093# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
886# CONFIG_DEBUG_KOBJECT is not set 1094# CONFIG_DEBUG_KOBJECT is not set
887CONFIG_DEBUG_BUGVERBOSE=y 1095CONFIG_DEBUG_BUGVERBOSE=y
888CONFIG_DEBUG_INFO=y 1096CONFIG_DEBUG_INFO=y
889# CONFIG_DEBUG_FS is not set 1097# CONFIG_DEBUG_FS is not set
1098# CONFIG_DEBUG_VM is not set
890CONFIG_FRAME_POINTER=y 1099CONFIG_FRAME_POINTER=y
1100CONFIG_FORCED_INLINING=y
1101# CONFIG_RCU_TORTURE_TEST is not set
891CONFIG_DEBUG_USER=y 1102CONFIG_DEBUG_USER=y
892# CONFIG_DEBUG_WAITQ is not set 1103# CONFIG_DEBUG_WAITQ is not set
893CONFIG_DEBUG_ERRORS=y 1104CONFIG_DEBUG_ERRORS=y
@@ -912,6 +1123,7 @@ CONFIG_DEBUG_ERRORS=y
912# Library routines 1123# Library routines
913# 1124#
914# CONFIG_CRC_CCITT is not set 1125# CONFIG_CRC_CCITT is not set
1126# CONFIG_CRC16 is not set
915CONFIG_CRC32=y 1127CONFIG_CRC32=y
916# CONFIG_LIBCRC32C is not set 1128# CONFIG_LIBCRC32C is not set
917CONFIG_ZLIB_INFLATE=y 1129CONFIG_ZLIB_INFLATE=y
diff --git a/arch/arm/configs/pnx4008_defconfig b/arch/arm/configs/pnx4008_defconfig
new file mode 100644
index 000000000000..8a078d479d57
--- /dev/null
+++ b/arch/arm/configs/pnx4008_defconfig
@@ -0,0 +1,2072 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.17-rc1
4# Thu Apr 6 17:05:58 2006
5#
6CONFIG_ARM=y
7CONFIG_MMU=y
8CONFIG_RWSEM_GENERIC_SPINLOCK=y
9CONFIG_GENERIC_HWEIGHT=y
10CONFIG_GENERIC_CALIBRATE_DELAY=y
11CONFIG_VECTORS_BASE=0xffff0000
12
13#
14# Code maturity level options
15#
16CONFIG_EXPERIMENTAL=y
17CONFIG_BROKEN_ON_SMP=y
18CONFIG_LOCK_KERNEL=y
19CONFIG_INIT_ENV_ARG_LIMIT=32
20
21#
22# General setup
23#
24CONFIG_LOCALVERSION=""
25CONFIG_LOCALVERSION_AUTO=y
26CONFIG_SWAP=y
27CONFIG_SYSVIPC=y
28CONFIG_POSIX_MQUEUE=y
29CONFIG_BSD_PROCESS_ACCT=y
30# CONFIG_BSD_PROCESS_ACCT_V3 is not set
31CONFIG_SYSCTL=y
32CONFIG_AUDIT=y
33# CONFIG_IKCONFIG is not set
34# CONFIG_RELAY is not set
35CONFIG_INITRAMFS_SOURCE=""
36CONFIG_UID16=y
37CONFIG_CC_OPTIMIZE_FOR_SIZE=y
38CONFIG_EMBEDDED=y
39CONFIG_KALLSYMS=y
40# CONFIG_KALLSYMS_ALL is not set
41# CONFIG_KALLSYMS_EXTRA_PASS is not set
42CONFIG_HOTPLUG=y
43CONFIG_PRINTK=y
44CONFIG_BUG=y
45CONFIG_ELF_CORE=y
46CONFIG_BASE_FULL=y
47CONFIG_FUTEX=y
48CONFIG_EPOLL=y
49CONFIG_SHMEM=y
50CONFIG_SLAB=y
51# CONFIG_TINY_SHMEM is not set
52CONFIG_BASE_SMALL=0
53# CONFIG_SLOB is not set
54CONFIG_OBSOLETE_INTERMODULE=m
55
56#
57# Loadable module support
58#
59CONFIG_MODULES=y
60CONFIG_MODULE_UNLOAD=y
61CONFIG_MODULE_FORCE_UNLOAD=y
62CONFIG_MODVERSIONS=y
63CONFIG_MODULE_SRCVERSION_ALL=y
64CONFIG_KMOD=y
65
66#
67# Block layer
68#
69# CONFIG_BLK_DEV_IO_TRACE is not set
70
71#
72# IO Schedulers
73#
74CONFIG_IOSCHED_NOOP=y
75CONFIG_IOSCHED_AS=y
76CONFIG_IOSCHED_DEADLINE=y
77CONFIG_IOSCHED_CFQ=y
78CONFIG_DEFAULT_AS=y
79# CONFIG_DEFAULT_DEADLINE is not set
80# CONFIG_DEFAULT_CFQ is not set
81# CONFIG_DEFAULT_NOOP is not set
82CONFIG_DEFAULT_IOSCHED="anticipatory"
83
84#
85# System Type
86#
87# CONFIG_ARCH_CLPS7500 is not set
88# CONFIG_ARCH_CLPS711X is not set
89# CONFIG_ARCH_CO285 is not set
90# CONFIG_ARCH_EBSA110 is not set
91# CONFIG_ARCH_EP93XX is not set
92# CONFIG_ARCH_FOOTBRIDGE is not set
93# CONFIG_ARCH_INTEGRATOR is not set
94# CONFIG_ARCH_IOP3XX is not set
95# CONFIG_ARCH_IXP4XX is not set
96# CONFIG_ARCH_IXP2000 is not set
97# CONFIG_ARCH_IXP23XX is not set
98# CONFIG_ARCH_L7200 is not set
99# CONFIG_ARCH_PXA is not set
100# CONFIG_ARCH_RPC is not set
101# CONFIG_ARCH_SA1100 is not set
102# CONFIG_ARCH_S3C2410 is not set
103# CONFIG_ARCH_SHARK is not set
104# CONFIG_ARCH_LH7A40X is not set
105# CONFIG_ARCH_OMAP is not set
106# CONFIG_ARCH_VERSATILE is not set
107# CONFIG_ARCH_REALVIEW is not set
108# CONFIG_ARCH_IMX is not set
109# CONFIG_ARCH_H720X is not set
110# CONFIG_ARCH_AAEC2000 is not set
111# CONFIG_ARCH_AT91RM9200 is not set
112CONFIG_ARCH_PNX4008=y
113
114#
115# Processor Type
116#
117CONFIG_CPU_32=y
118CONFIG_CPU_ARM926T=y
119CONFIG_CPU_32v5=y
120CONFIG_CPU_ABRT_EV5TJ=y
121CONFIG_CPU_CACHE_VIVT=y
122CONFIG_CPU_COPY_V4WB=y
123CONFIG_CPU_TLB_V4WBI=y
124
125#
126# Processor Features
127#
128CONFIG_ARM_THUMB=y
129# CONFIG_CPU_ICACHE_DISABLE is not set
130# CONFIG_CPU_DCACHE_DISABLE is not set
131# CONFIG_CPU_DCACHE_WRITETHROUGH is not set
132# CONFIG_CPU_CACHE_ROUND_ROBIN is not set
133
134#
135# Bus support
136#
137
138#
139# PCCARD (PCMCIA/CardBus) support
140#
141CONFIG_PCCARD=m
142# CONFIG_PCMCIA_DEBUG is not set
143CONFIG_PCMCIA=m
144CONFIG_PCMCIA_LOAD_CIS=y
145CONFIG_PCMCIA_IOCTL=y
146
147#
148# PC-card bridges
149#
150
151#
152# Kernel Features
153#
154CONFIG_PREEMPT=y
155# CONFIG_NO_IDLE_HZ is not set
156CONFIG_HZ=100
157# CONFIG_AEABI is not set
158# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
159CONFIG_SELECT_MEMORY_MODEL=y
160CONFIG_FLATMEM_MANUAL=y
161# CONFIG_DISCONTIGMEM_MANUAL is not set
162# CONFIG_SPARSEMEM_MANUAL is not set
163CONFIG_FLATMEM=y
164CONFIG_FLAT_NODE_MEM_MAP=y
165# CONFIG_SPARSEMEM_STATIC is not set
166CONFIG_SPLIT_PTLOCK_CPUS=4096
167CONFIG_ALIGNMENT_TRAP=y
168
169#
170# Boot options
171#
172CONFIG_ZBOOT_ROM_TEXT=0
173CONFIG_ZBOOT_ROM_BSS=0
174CONFIG_CMDLINE="mem=64M console=ttyS0,115200"
175# CONFIG_XIP_KERNEL is not set
176
177#
178# Floating point emulation
179#
180
181#
182# At least one emulation must be selected
183#
184# CONFIG_FPE_NWFPE is not set
185# CONFIG_FPE_FASTFPE is not set
186# CONFIG_VFP is not set
187
188#
189# Userspace binary formats
190#
191CONFIG_BINFMT_ELF=y
192CONFIG_BINFMT_AOUT=m
193CONFIG_BINFMT_MISC=m
194# CONFIG_ARTHUR is not set
195
196#
197# Power management options
198#
199CONFIG_PM=y
200CONFIG_PM_LEGACY=y
201# CONFIG_PM_DEBUG is not set
202CONFIG_APM=m
203
204#
205# Networking
206#
207CONFIG_NET=y
208
209#
210# Networking options
211#
212# CONFIG_NETDEBUG is not set
213CONFIG_PACKET=m
214CONFIG_PACKET_MMAP=y
215CONFIG_UNIX=m
216CONFIG_XFRM=y
217CONFIG_XFRM_USER=m
218CONFIG_NET_KEY=m
219CONFIG_INET=y
220CONFIG_IP_MULTICAST=y
221CONFIG_IP_ADVANCED_ROUTER=y
222CONFIG_ASK_IP_FIB_HASH=y
223# CONFIG_IP_FIB_TRIE is not set
224CONFIG_IP_FIB_HASH=y
225CONFIG_IP_MULTIPLE_TABLES=y
226CONFIG_IP_ROUTE_FWMARK=y
227CONFIG_IP_ROUTE_MULTIPATH=y
228# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
229CONFIG_IP_ROUTE_VERBOSE=y
230# CONFIG_IP_PNP is not set
231CONFIG_NET_IPIP=m
232CONFIG_NET_IPGRE=m
233CONFIG_NET_IPGRE_BROADCAST=y
234CONFIG_IP_MROUTE=y
235CONFIG_IP_PIMSM_V1=y
236CONFIG_IP_PIMSM_V2=y
237# CONFIG_ARPD is not set
238CONFIG_SYN_COOKIES=y
239CONFIG_INET_AH=m
240CONFIG_INET_ESP=m
241CONFIG_INET_IPCOMP=m
242CONFIG_INET_XFRM_TUNNEL=m
243CONFIG_INET_TUNNEL=m
244CONFIG_INET_DIAG=y
245CONFIG_INET_TCP_DIAG=y
246# CONFIG_TCP_CONG_ADVANCED is not set
247CONFIG_TCP_CONG_BIC=y
248
249#
250# IP: Virtual Server Configuration
251#
252CONFIG_IP_VS=m
253# CONFIG_IP_VS_DEBUG is not set
254CONFIG_IP_VS_TAB_BITS=12
255
256#
257# IPVS transport protocol load balancing support
258#
259CONFIG_IP_VS_PROTO_TCP=y
260CONFIG_IP_VS_PROTO_UDP=y
261CONFIG_IP_VS_PROTO_ESP=y
262CONFIG_IP_VS_PROTO_AH=y
263
264#
265# IPVS scheduler
266#
267CONFIG_IP_VS_RR=m
268CONFIG_IP_VS_WRR=m
269CONFIG_IP_VS_LC=m
270CONFIG_IP_VS_WLC=m
271CONFIG_IP_VS_LBLC=m
272CONFIG_IP_VS_LBLCR=m
273CONFIG_IP_VS_DH=m
274CONFIG_IP_VS_SH=m
275CONFIG_IP_VS_SED=m
276CONFIG_IP_VS_NQ=m
277
278#
279# IPVS application helper
280#
281CONFIG_IP_VS_FTP=m
282CONFIG_IPV6=m
283CONFIG_IPV6_PRIVACY=y
284# CONFIG_IPV6_ROUTER_PREF is not set
285CONFIG_INET6_AH=m
286CONFIG_INET6_ESP=m
287CONFIG_INET6_IPCOMP=m
288CONFIG_INET6_XFRM_TUNNEL=m
289CONFIG_INET6_TUNNEL=m
290CONFIG_IPV6_TUNNEL=m
291CONFIG_NETFILTER=y
292# CONFIG_NETFILTER_DEBUG is not set
293CONFIG_BRIDGE_NETFILTER=y
294
295#
296# Core Netfilter Configuration
297#
298# CONFIG_NETFILTER_NETLINK is not set
299# CONFIG_NETFILTER_XTABLES is not set
300
301#
302# IP: Netfilter Configuration
303#
304CONFIG_IP_NF_CONNTRACK=m
305CONFIG_IP_NF_CT_ACCT=y
306CONFIG_IP_NF_CONNTRACK_MARK=y
307# CONFIG_IP_NF_CONNTRACK_EVENTS is not set
308CONFIG_IP_NF_CT_PROTO_SCTP=m
309CONFIG_IP_NF_FTP=m
310CONFIG_IP_NF_IRC=m
311# CONFIG_IP_NF_NETBIOS_NS is not set
312CONFIG_IP_NF_TFTP=m
313CONFIG_IP_NF_AMANDA=m
314# CONFIG_IP_NF_PPTP is not set
315# CONFIG_IP_NF_H323 is not set
316CONFIG_IP_NF_QUEUE=m
317
318#
319# IPv6: Netfilter Configuration (EXPERIMENTAL)
320#
321CONFIG_IP6_NF_QUEUE=m
322
323#
324# DECnet: Netfilter Configuration
325#
326CONFIG_DECNET_NF_GRABULATOR=m
327
328#
329# Bridge: Netfilter Configuration
330#
331CONFIG_BRIDGE_NF_EBTABLES=m
332CONFIG_BRIDGE_EBT_BROUTE=m
333CONFIG_BRIDGE_EBT_T_FILTER=m
334CONFIG_BRIDGE_EBT_T_NAT=m
335CONFIG_BRIDGE_EBT_802_3=m
336CONFIG_BRIDGE_EBT_AMONG=m
337CONFIG_BRIDGE_EBT_ARP=m
338CONFIG_BRIDGE_EBT_IP=m
339CONFIG_BRIDGE_EBT_LIMIT=m
340CONFIG_BRIDGE_EBT_MARK=m
341CONFIG_BRIDGE_EBT_PKTTYPE=m
342CONFIG_BRIDGE_EBT_STP=m
343CONFIG_BRIDGE_EBT_VLAN=m
344CONFIG_BRIDGE_EBT_ARPREPLY=m
345CONFIG_BRIDGE_EBT_DNAT=m
346CONFIG_BRIDGE_EBT_MARK_T=m
347CONFIG_BRIDGE_EBT_REDIRECT=m
348CONFIG_BRIDGE_EBT_SNAT=m
349CONFIG_BRIDGE_EBT_LOG=m
350# CONFIG_BRIDGE_EBT_ULOG is not set
351
352#
353# DCCP Configuration (EXPERIMENTAL)
354#
355# CONFIG_IP_DCCP is not set
356
357#
358# SCTP Configuration (EXPERIMENTAL)
359#
360CONFIG_IP_SCTP=m
361# CONFIG_SCTP_DBG_MSG is not set
362# CONFIG_SCTP_DBG_OBJCNT is not set
363# CONFIG_SCTP_HMAC_NONE is not set
364# CONFIG_SCTP_HMAC_SHA1 is not set
365CONFIG_SCTP_HMAC_MD5=y
366
367#
368# TIPC Configuration (EXPERIMENTAL)
369#
370# CONFIG_TIPC is not set
371CONFIG_ATM=y
372CONFIG_ATM_CLIP=y
373# CONFIG_ATM_CLIP_NO_ICMP is not set
374CONFIG_ATM_LANE=m
375CONFIG_ATM_MPOA=m
376CONFIG_ATM_BR2684=m
377# CONFIG_ATM_BR2684_IPFILTER is not set
378CONFIG_BRIDGE=m
379CONFIG_VLAN_8021Q=m
380CONFIG_DECNET=m
381# CONFIG_DECNET_ROUTER is not set
382CONFIG_LLC=m
383CONFIG_LLC2=m
384CONFIG_IPX=m
385# CONFIG_IPX_INTERN is not set
386CONFIG_ATALK=m
387CONFIG_DEV_APPLETALK=y
388CONFIG_IPDDP=m
389CONFIG_IPDDP_ENCAP=y
390CONFIG_IPDDP_DECAP=y
391CONFIG_X25=m
392CONFIG_LAPB=m
393# CONFIG_NET_DIVERT is not set
394CONFIG_ECONET=m
395CONFIG_ECONET_AUNUDP=y
396CONFIG_ECONET_NATIVE=y
397CONFIG_WAN_ROUTER=m
398
399#
400# QoS and/or fair queueing
401#
402CONFIG_NET_SCHED=y
403CONFIG_NET_SCH_CLK_JIFFIES=y
404# CONFIG_NET_SCH_CLK_GETTIMEOFDAY is not set
405# CONFIG_NET_SCH_CLK_CPU is not set
406
407#
408# Queueing/Scheduling
409#
410CONFIG_NET_SCH_CBQ=m
411CONFIG_NET_SCH_HTB=m
412CONFIG_NET_SCH_HFSC=m
413CONFIG_NET_SCH_ATM=m
414CONFIG_NET_SCH_PRIO=m
415CONFIG_NET_SCH_RED=m
416CONFIG_NET_SCH_SFQ=m
417CONFIG_NET_SCH_TEQL=m
418CONFIG_NET_SCH_TBF=m
419CONFIG_NET_SCH_GRED=m
420CONFIG_NET_SCH_DSMARK=m
421CONFIG_NET_SCH_NETEM=m
422CONFIG_NET_SCH_INGRESS=m
423
424#
425# Classification
426#
427CONFIG_NET_CLS=y
428# CONFIG_NET_CLS_BASIC is not set
429CONFIG_NET_CLS_TCINDEX=m
430CONFIG_NET_CLS_ROUTE4=m
431CONFIG_NET_CLS_ROUTE=y
432CONFIG_NET_CLS_FW=m
433CONFIG_NET_CLS_U32=m
434# CONFIG_CLS_U32_PERF is not set
435# CONFIG_CLS_U32_MARK is not set
436CONFIG_NET_CLS_RSVP=m
437CONFIG_NET_CLS_RSVP6=m
438# CONFIG_NET_EMATCH is not set
439# CONFIG_NET_CLS_ACT is not set
440CONFIG_NET_CLS_POLICE=y
441# CONFIG_NET_CLS_IND is not set
442CONFIG_NET_ESTIMATOR=y
443
444#
445# Network testing
446#
447CONFIG_NET_PKTGEN=m
448CONFIG_HAMRADIO=y
449
450#
451# Packet Radio protocols
452#
453CONFIG_AX25=m
454# CONFIG_AX25_DAMA_SLAVE is not set
455CONFIG_NETROM=m
456CONFIG_ROSE=m
457
458#
459# AX.25 network device drivers
460#
461CONFIG_MKISS=m
462CONFIG_6PACK=m
463CONFIG_BPQETHER=m
464CONFIG_BAYCOM_SER_FDX=m
465CONFIG_BAYCOM_SER_HDX=m
466CONFIG_BAYCOM_PAR=m
467CONFIG_BAYCOM_EPP=m
468CONFIG_YAM=m
469CONFIG_IRDA=m
470
471#
472# IrDA protocols
473#
474CONFIG_IRLAN=m
475CONFIG_IRNET=m
476CONFIG_IRCOMM=m
477# CONFIG_IRDA_ULTRA is not set
478
479#
480# IrDA options
481#
482CONFIG_IRDA_CACHE_LAST_LSAP=y
483CONFIG_IRDA_FAST_RR=y
484CONFIG_IRDA_DEBUG=y
485
486#
487# Infrared-port device drivers
488#
489
490#
491# SIR device drivers
492#
493CONFIG_IRTTY_SIR=m
494
495#
496# Dongle support
497#
498CONFIG_DONGLE=y
499CONFIG_ESI_DONGLE=m
500CONFIG_ACTISYS_DONGLE=m
501CONFIG_TEKRAM_DONGLE=m
502# CONFIG_TOIM3232_DONGLE is not set
503CONFIG_LITELINK_DONGLE=m
504CONFIG_MA600_DONGLE=m
505CONFIG_GIRBIL_DONGLE=m
506CONFIG_MCP2120_DONGLE=m
507CONFIG_OLD_BELKIN_DONGLE=m
508CONFIG_ACT200L_DONGLE=m
509
510#
511# Old SIR device drivers
512#
513CONFIG_IRPORT_SIR=m
514
515#
516# Old Serial dongle support
517#
518# CONFIG_DONGLE_OLD is not set
519
520#
521# FIR device drivers
522#
523CONFIG_USB_IRDA=m
524CONFIG_SIGMATEL_FIR=m
525CONFIG_BT=m
526CONFIG_BT_L2CAP=m
527CONFIG_BT_SCO=m
528CONFIG_BT_RFCOMM=m
529CONFIG_BT_RFCOMM_TTY=y
530CONFIG_BT_BNEP=m
531CONFIG_BT_BNEP_MC_FILTER=y
532CONFIG_BT_BNEP_PROTO_FILTER=y
533CONFIG_BT_CMTP=m
534CONFIG_BT_HIDP=m
535
536#
537# Bluetooth device drivers
538#
539CONFIG_BT_HCIUSB=m
540CONFIG_BT_HCIUSB_SCO=y
541CONFIG_BT_HCIUART=m
542CONFIG_BT_HCIUART_H4=y
543CONFIG_BT_HCIUART_BCSP=y
544CONFIG_BT_HCIBCM203X=m
545# CONFIG_BT_HCIBPA10X is not set
546CONFIG_BT_HCIBFUSB=m
547CONFIG_BT_HCIDTL1=m
548CONFIG_BT_HCIBT3C=m
549CONFIG_BT_HCIBLUECARD=m
550CONFIG_BT_HCIBTUART=m
551CONFIG_BT_HCIVHCI=m
552CONFIG_IEEE80211=m
553# CONFIG_IEEE80211_DEBUG is not set
554# CONFIG_IEEE80211_CRYPT_WEP is not set
555CONFIG_IEEE80211_CRYPT_CCMP=m
556CONFIG_IEEE80211_CRYPT_TKIP=m
557# CONFIG_IEEE80211_SOFTMAC is not set
558CONFIG_WIRELESS_EXT=y
559
560#
561# Device Drivers
562#
563
564#
565# Generic Driver Options
566#
567CONFIG_STANDALONE=y
568CONFIG_PREVENT_FIRMWARE_BUILD=y
569CONFIG_FW_LOADER=m
570# CONFIG_DEBUG_DRIVER is not set
571
572#
573# Connector - unified userspace <-> kernelspace linker
574#
575# CONFIG_CONNECTOR is not set
576
577#
578# Memory Technology Devices (MTD)
579#
580CONFIG_MTD=m
581# CONFIG_MTD_DEBUG is not set
582CONFIG_MTD_CONCAT=m
583CONFIG_MTD_PARTITIONS=y
584CONFIG_MTD_REDBOOT_PARTS=m
585CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
586# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
587# CONFIG_MTD_REDBOOT_PARTS_READONLY is not set
588# CONFIG_MTD_CMDLINE_PARTS is not set
589# CONFIG_MTD_AFS_PARTS is not set
590
591#
592# User Modules And Translation Layers
593#
594CONFIG_MTD_CHAR=m
595CONFIG_MTD_BLOCK=m
596CONFIG_MTD_BLOCK_RO=m
597CONFIG_FTL=m
598CONFIG_NFTL=m
599CONFIG_NFTL_RW=y
600CONFIG_INFTL=m
601# CONFIG_RFD_FTL is not set
602
603#
604# RAM/ROM/Flash chip drivers
605#
606CONFIG_MTD_CFI=m
607CONFIG_MTD_JEDECPROBE=m
608CONFIG_MTD_GEN_PROBE=m
609# CONFIG_MTD_CFI_ADV_OPTIONS is not set
610CONFIG_MTD_MAP_BANK_WIDTH_1=y
611CONFIG_MTD_MAP_BANK_WIDTH_2=y
612CONFIG_MTD_MAP_BANK_WIDTH_4=y
613# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
614# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
615# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
616CONFIG_MTD_CFI_I1=y
617CONFIG_MTD_CFI_I2=y
618# CONFIG_MTD_CFI_I4 is not set
619# CONFIG_MTD_CFI_I8 is not set
620CONFIG_MTD_CFI_INTELEXT=m
621CONFIG_MTD_CFI_AMDSTD=m
622CONFIG_MTD_CFI_STAA=m
623CONFIG_MTD_CFI_UTIL=m
624CONFIG_MTD_RAM=m
625CONFIG_MTD_ROM=m
626CONFIG_MTD_ABSENT=m
627# CONFIG_MTD_OBSOLETE_CHIPS is not set
628
629#
630# Mapping drivers for chip access
631#
632CONFIG_MTD_COMPLEX_MAPPINGS=y
633CONFIG_MTD_PHYSMAP=m
634CONFIG_MTD_PHYSMAP_START=0x8000000
635CONFIG_MTD_PHYSMAP_LEN=0x4000000
636CONFIG_MTD_PHYSMAP_BANKWIDTH=2
637# CONFIG_MTD_ARM_INTEGRATOR is not set
638# CONFIG_MTD_IMPA7 is not set
639# CONFIG_MTD_PLATRAM is not set
640
641#
642# Self-contained MTD device drivers
643#
644CONFIG_MTD_SLRAM=m
645CONFIG_MTD_PHRAM=m
646CONFIG_MTD_MTDRAM=m
647CONFIG_MTDRAM_TOTAL_SIZE=4096
648CONFIG_MTDRAM_ERASE_SIZE=128
649CONFIG_MTD_BLKMTD=m
650# CONFIG_MTD_BLOCK2MTD is not set
651
652#
653# Disk-On-Chip Device Drivers
654#
655CONFIG_MTD_DOC2000=m
656CONFIG_MTD_DOC2001=m
657CONFIG_MTD_DOC2001PLUS=m
658CONFIG_MTD_DOCPROBE=m
659CONFIG_MTD_DOCECC=m
660# CONFIG_MTD_DOCPROBE_ADVANCED is not set
661CONFIG_MTD_DOCPROBE_ADDRESS=0
662
663#
664# NAND Flash Device Drivers
665#
666CONFIG_MTD_NAND=m
667# CONFIG_MTD_NAND_VERIFY_WRITE is not set
668CONFIG_MTD_NAND_IDS=m
669CONFIG_MTD_NAND_DISKONCHIP=m
670# CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED is not set
671CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0
672# CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE is not set
673# CONFIG_MTD_NAND_NANDSIM is not set
674
675#
676# OneNAND Flash Device Drivers
677#
678# CONFIG_MTD_ONENAND is not set
679
680#
681# Parallel port support
682#
683CONFIG_PARPORT=m
684CONFIG_PARPORT_PC=m
685CONFIG_PARPORT_PC_FIFO=y
686# CONFIG_PARPORT_PC_SUPERIO is not set
687CONFIG_PARPORT_PC_PCMCIA=m
688CONFIG_PARPORT_NOT_PC=y
689# CONFIG_PARPORT_ARC is not set
690# CONFIG_PARPORT_GSC is not set
691CONFIG_PARPORT_1284=y
692
693#
694# Plug and Play support
695#
696
697#
698# Block devices
699#
700CONFIG_PARIDE=m
701CONFIG_PARIDE_PARPORT=m
702
703#
704# Parallel IDE high-level drivers
705#
706CONFIG_PARIDE_PD=m
707CONFIG_PARIDE_PCD=m
708CONFIG_PARIDE_PF=m
709CONFIG_PARIDE_PT=m
710CONFIG_PARIDE_PG=m
711
712#
713# Parallel IDE protocol modules
714#
715CONFIG_PARIDE_ATEN=m
716CONFIG_PARIDE_BPCK=m
717CONFIG_PARIDE_BPCK6=m
718CONFIG_PARIDE_COMM=m
719CONFIG_PARIDE_DSTR=m
720CONFIG_PARIDE_FIT2=m
721CONFIG_PARIDE_FIT3=m
722CONFIG_PARIDE_EPAT=m
723# CONFIG_PARIDE_EPATC8 is not set
724CONFIG_PARIDE_EPIA=m
725CONFIG_PARIDE_FRIQ=m
726CONFIG_PARIDE_FRPW=m
727CONFIG_PARIDE_KBIC=m
728CONFIG_PARIDE_KTTI=m
729CONFIG_PARIDE_ON20=m
730CONFIG_PARIDE_ON26=m
731# CONFIG_BLK_DEV_COW_COMMON is not set
732CONFIG_BLK_DEV_LOOP=m
733CONFIG_BLK_DEV_CRYPTOLOOP=m
734CONFIG_BLK_DEV_NBD=m
735# CONFIG_BLK_DEV_UB is not set
736CONFIG_BLK_DEV_RAM=y
737CONFIG_BLK_DEV_RAM_COUNT=16
738CONFIG_BLK_DEV_RAM_SIZE=8192
739CONFIG_BLK_DEV_INITRD=y
740CONFIG_CDROM_PKTCDVD=m
741CONFIG_CDROM_PKTCDVD_BUFFERS=8
742# CONFIG_CDROM_PKTCDVD_WCACHE is not set
743# CONFIG_ATA_OVER_ETH is not set
744
745#
746# ATA/ATAPI/MFM/RLL support
747#
748CONFIG_IDE=m
749CONFIG_BLK_DEV_IDE=m
750
751#
752# Please see Documentation/ide.txt for help/info on IDE drives
753#
754# CONFIG_BLK_DEV_IDE_SATA is not set
755CONFIG_BLK_DEV_IDEDISK=m
756# CONFIG_IDEDISK_MULTI_MODE is not set
757CONFIG_BLK_DEV_IDECS=m
758CONFIG_BLK_DEV_IDECD=m
759CONFIG_BLK_DEV_IDETAPE=m
760CONFIG_BLK_DEV_IDEFLOPPY=m
761CONFIG_BLK_DEV_IDESCSI=m
762# CONFIG_IDE_TASK_IOCTL is not set
763
764#
765# IDE chipset support/bugfixes
766#
767CONFIG_IDE_GENERIC=m
768# CONFIG_IDE_ARM is not set
769# CONFIG_BLK_DEV_IDEDMA is not set
770# CONFIG_IDEDMA_AUTO is not set
771# CONFIG_BLK_DEV_HD is not set
772
773#
774# SCSI device support
775#
776# CONFIG_RAID_ATTRS is not set
777CONFIG_SCSI=m
778CONFIG_SCSI_PROC_FS=y
779
780#
781# SCSI support type (disk, tape, CD-ROM)
782#
783CONFIG_BLK_DEV_SD=m
784CONFIG_CHR_DEV_ST=m
785CONFIG_CHR_DEV_OSST=m
786CONFIG_BLK_DEV_SR=m
787# CONFIG_BLK_DEV_SR_VENDOR is not set
788CONFIG_CHR_DEV_SG=m
789CONFIG_CHR_DEV_SCH=m
790
791#
792# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
793#
794CONFIG_SCSI_MULTI_LUN=y
795CONFIG_SCSI_CONSTANTS=y
796CONFIG_SCSI_LOGGING=y
797
798#
799# SCSI Transport Attributes
800#
801CONFIG_SCSI_SPI_ATTRS=m
802CONFIG_SCSI_FC_ATTRS=m
803# CONFIG_SCSI_ISCSI_ATTRS is not set
804# CONFIG_SCSI_SAS_ATTRS is not set
805
806#
807# SCSI low-level drivers
808#
809# CONFIG_ISCSI_TCP is not set
810CONFIG_SCSI_SATA=m
811CONFIG_SCSI_PPA=m
812CONFIG_SCSI_IMM=m
813# CONFIG_SCSI_IZIP_EPP16 is not set
814# CONFIG_SCSI_IZIP_SLOW_CTR is not set
815CONFIG_SCSI_DEBUG=m
816
817#
818# PCMCIA SCSI adapter support
819#
820CONFIG_PCMCIA_AHA152X=m
821CONFIG_PCMCIA_FDOMAIN=m
822CONFIG_PCMCIA_NINJA_SCSI=m
823CONFIG_PCMCIA_QLOGIC=m
824CONFIG_PCMCIA_SYM53C500=m
825
826#
827# Multi-device support (RAID and LVM)
828#
829CONFIG_MD=y
830CONFIG_BLK_DEV_MD=m
831CONFIG_MD_LINEAR=m
832CONFIG_MD_RAID0=m
833CONFIG_MD_RAID1=m
834CONFIG_MD_RAID10=m
835CONFIG_MD_RAID5=m
836# CONFIG_MD_RAID5_RESHAPE is not set
837CONFIG_MD_RAID6=m
838CONFIG_MD_MULTIPATH=m
839CONFIG_MD_FAULTY=m
840CONFIG_BLK_DEV_DM=m
841CONFIG_DM_CRYPT=m
842CONFIG_DM_SNAPSHOT=m
843CONFIG_DM_MIRROR=m
844CONFIG_DM_ZERO=m
845# CONFIG_DM_MULTIPATH is not set
846
847#
848# Fusion MPT device support
849#
850# CONFIG_FUSION is not set
851
852#
853# IEEE 1394 (FireWire) support
854#
855
856#
857# I2O device support
858#
859
860#
861# Network device support
862#
863CONFIG_NETDEVICES=y
864CONFIG_DUMMY=m
865CONFIG_BONDING=m
866CONFIG_EQUALIZER=m
867CONFIG_TUN=m
868
869#
870# PHY device support
871#
872# CONFIG_PHYLIB is not set
873
874#
875# Ethernet (10 or 100Mbit)
876#
877CONFIG_NET_ETHERNET=y
878CONFIG_MII=m
879# CONFIG_SMC91X is not set
880# CONFIG_DM9000 is not set
881CONFIG_NET_POCKET=y
882CONFIG_DE600=m
883CONFIG_DE620=m
884
885#
886# Ethernet (1000 Mbit)
887#
888
889#
890# Ethernet (10000 Mbit)
891#
892
893#
894# Token Ring devices
895#
896
897#
898# Wireless LAN (non-hamradio)
899#
900CONFIG_NET_RADIO=y
901# CONFIG_NET_WIRELESS_RTNETLINK is not set
902
903#
904# Obsolete Wireless cards support (pre-802.11)
905#
906CONFIG_STRIP=m
907CONFIG_PCMCIA_WAVELAN=m
908CONFIG_PCMCIA_NETWAVE=m
909
910#
911# Wireless 802.11 Frequency Hopping cards support
912#
913CONFIG_PCMCIA_RAYCS=m
914
915#
916# Wireless 802.11b ISA/PCI cards support
917#
918CONFIG_HERMES=m
919CONFIG_ATMEL=m
920
921#
922# Wireless 802.11b Pcmcia/Cardbus cards support
923#
924CONFIG_PCMCIA_HERMES=m
925# CONFIG_PCMCIA_SPECTRUM is not set
926CONFIG_AIRO_CS=m
927CONFIG_PCMCIA_ATMEL=m
928CONFIG_PCMCIA_WL3501=m
929# CONFIG_HOSTAP is not set
930CONFIG_NET_WIRELESS=y
931
932#
933# PCMCIA network device support
934#
935CONFIG_NET_PCMCIA=y
936CONFIG_PCMCIA_3C589=m
937CONFIG_PCMCIA_3C574=m
938CONFIG_PCMCIA_FMVJ18X=m
939CONFIG_PCMCIA_PCNET=m
940CONFIG_PCMCIA_NMCLAN=m
941CONFIG_PCMCIA_SMC91C92=m
942CONFIG_PCMCIA_XIRC2PS=m
943CONFIG_PCMCIA_AXNET=m
944
945#
946# Wan interfaces
947#
948CONFIG_WAN=y
949CONFIG_SYNCLINK_SYNCPPP=m
950CONFIG_HDLC=m
951CONFIG_HDLC_RAW=y
952CONFIG_HDLC_RAW_ETH=y
953CONFIG_HDLC_CISCO=y
954CONFIG_HDLC_FR=y
955CONFIG_HDLC_PPP=y
956CONFIG_HDLC_X25=y
957CONFIG_DLCI=m
958CONFIG_DLCI_COUNT=24
959CONFIG_DLCI_MAX=8
960CONFIG_WAN_ROUTER_DRIVERS=y
961CONFIG_LAPBETHER=m
962CONFIG_X25_ASY=m
963
964#
965# ATM drivers
966#
967# CONFIG_ATM_DUMMY is not set
968CONFIG_ATM_TCP=m
969CONFIG_PLIP=m
970CONFIG_PPP=m
971CONFIG_PPP_MULTILINK=y
972CONFIG_PPP_FILTER=y
973CONFIG_PPP_ASYNC=m
974CONFIG_PPP_SYNC_TTY=m
975CONFIG_PPP_DEFLATE=m
976CONFIG_PPP_BSDCOMP=m
977CONFIG_PPP_MPPE=m
978CONFIG_PPPOE=m
979CONFIG_PPPOATM=m
980CONFIG_SLIP=m
981CONFIG_SLIP_COMPRESSED=y
982CONFIG_SLIP_SMART=y
983CONFIG_SLIP_MODE_SLIP6=y
984CONFIG_SHAPER=m
985CONFIG_NETCONSOLE=m
986CONFIG_NETPOLL=y
987# CONFIG_NETPOLL_RX is not set
988# CONFIG_NETPOLL_TRAP is not set
989CONFIG_NET_POLL_CONTROLLER=y
990
991#
992# ISDN subsystem
993#
994CONFIG_ISDN=m
995
996#
997# Old ISDN4Linux
998#
999CONFIG_ISDN_I4L=m
1000CONFIG_ISDN_PPP=y
1001CONFIG_ISDN_PPP_VJ=y
1002CONFIG_ISDN_MPP=y
1003CONFIG_IPPP_FILTER=y
1004CONFIG_ISDN_PPP_BSDCOMP=m
1005CONFIG_ISDN_AUDIO=y
1006CONFIG_ISDN_TTY_FAX=y
1007CONFIG_ISDN_X25=y
1008
1009#
1010# ISDN feature submodules
1011#
1012CONFIG_ISDN_DRV_LOOP=m
1013CONFIG_ISDN_DIVERSION=m
1014
1015#
1016# ISDN4Linux hardware drivers
1017#
1018
1019#
1020# Passive cards
1021#
1022CONFIG_ISDN_DRV_HISAX=m
1023
1024#
1025# D-channel protocol features
1026#
1027CONFIG_HISAX_EURO=y
1028CONFIG_DE_AOC=y
1029# CONFIG_HISAX_NO_SENDCOMPLETE is not set
1030# CONFIG_HISAX_NO_LLC is not set
1031# CONFIG_HISAX_NO_KEYPAD is not set
1032CONFIG_HISAX_1TR6=y
1033CONFIG_HISAX_NI1=y
1034CONFIG_HISAX_MAX_CARDS=8
1035
1036#
1037# HiSax supported cards
1038#
1039CONFIG_HISAX_16_3=y
1040CONFIG_HISAX_S0BOX=y
1041CONFIG_HISAX_FRITZPCI=y
1042CONFIG_HISAX_AVM_A1_PCMCIA=y
1043CONFIG_HISAX_ELSA=y
1044CONFIG_HISAX_DIEHLDIVA=y
1045CONFIG_HISAX_SEDLBAUER=y
1046CONFIG_HISAX_NICCY=y
1047CONFIG_HISAX_GAZEL=y
1048CONFIG_HISAX_HFC_SX=y
1049# CONFIG_HISAX_DEBUG is not set
1050
1051#
1052# HiSax PCMCIA card service modules
1053#
1054CONFIG_HISAX_SEDLBAUER_CS=m
1055CONFIG_HISAX_ELSA_CS=m
1056CONFIG_HISAX_AVM_A1_CS=m
1057CONFIG_HISAX_TELES_CS=m
1058
1059#
1060# HiSax sub driver modules
1061#
1062CONFIG_HISAX_ST5481=m
1063CONFIG_HISAX_HFCUSB=m
1064# CONFIG_HISAX_HFC4S8S is not set
1065CONFIG_HISAX_HDLC=y
1066
1067#
1068# Active cards
1069#
1070
1071#
1072# Siemens Gigaset
1073#
1074# CONFIG_ISDN_DRV_GIGASET is not set
1075
1076#
1077# CAPI subsystem
1078#
1079CONFIG_ISDN_CAPI=m
1080CONFIG_ISDN_DRV_AVMB1_VERBOSE_REASON=y
1081CONFIG_ISDN_CAPI_MIDDLEWARE=y
1082CONFIG_ISDN_CAPI_CAPI20=m
1083CONFIG_ISDN_CAPI_CAPIFS_BOOL=y
1084CONFIG_ISDN_CAPI_CAPIFS=m
1085CONFIG_ISDN_CAPI_CAPIDRV=m
1086
1087#
1088# CAPI hardware drivers
1089#
1090
1091#
1092# Active AVM cards
1093#
1094CONFIG_CAPI_AVM=y
1095CONFIG_ISDN_DRV_AVMB1_B1PCMCIA=m
1096CONFIG_ISDN_DRV_AVMB1_AVM_CS=m
1097
1098#
1099# Active Eicon DIVA Server cards
1100#
1101CONFIG_CAPI_EICON=y
1102
1103#
1104# Input device support
1105#
1106CONFIG_INPUT=y
1107
1108#
1109# Userland interfaces
1110#
1111CONFIG_INPUT_MOUSEDEV=m
1112CONFIG_INPUT_MOUSEDEV_PSAUX=y
1113CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
1114CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
1115CONFIG_INPUT_JOYDEV=m
1116CONFIG_INPUT_TSDEV=m
1117CONFIG_INPUT_TSDEV_SCREEN_X=240
1118CONFIG_INPUT_TSDEV_SCREEN_Y=320
1119CONFIG_INPUT_EVDEV=m
1120CONFIG_INPUT_EVBUG=m
1121
1122#
1123# Input Device Drivers
1124#
1125CONFIG_INPUT_KEYBOARD=y
1126CONFIG_KEYBOARD_ATKBD=y
1127CONFIG_KEYBOARD_SUNKBD=m
1128CONFIG_KEYBOARD_LKKBD=m
1129CONFIG_KEYBOARD_XTKBD=m
1130CONFIG_KEYBOARD_NEWTON=m
1131CONFIG_INPUT_MOUSE=y
1132CONFIG_MOUSE_PS2=m
1133CONFIG_MOUSE_SERIAL=m
1134CONFIG_MOUSE_VSXXXAA=m
1135CONFIG_INPUT_JOYSTICK=y
1136CONFIG_JOYSTICK_ANALOG=m
1137CONFIG_JOYSTICK_A3D=m
1138CONFIG_JOYSTICK_ADI=m
1139CONFIG_JOYSTICK_COBRA=m
1140CONFIG_JOYSTICK_GF2K=m
1141CONFIG_JOYSTICK_GRIP=m
1142CONFIG_JOYSTICK_GRIP_MP=m
1143CONFIG_JOYSTICK_GUILLEMOT=m
1144CONFIG_JOYSTICK_INTERACT=m
1145CONFIG_JOYSTICK_SIDEWINDER=m
1146CONFIG_JOYSTICK_TMDC=m
1147CONFIG_JOYSTICK_IFORCE=m
1148CONFIG_JOYSTICK_IFORCE_USB=y
1149CONFIG_JOYSTICK_IFORCE_232=y
1150CONFIG_JOYSTICK_WARRIOR=m
1151CONFIG_JOYSTICK_MAGELLAN=m
1152CONFIG_JOYSTICK_SPACEORB=m
1153CONFIG_JOYSTICK_SPACEBALL=m
1154CONFIG_JOYSTICK_STINGER=m
1155# CONFIG_JOYSTICK_TWIDJOY is not set
1156CONFIG_JOYSTICK_DB9=m
1157CONFIG_JOYSTICK_GAMECON=m
1158CONFIG_JOYSTICK_TURBOGRAFX=m
1159CONFIG_JOYSTICK_JOYDUMP=m
1160CONFIG_INPUT_TOUCHSCREEN=y
1161CONFIG_TOUCHSCREEN_GUNZE=m
1162# CONFIG_TOUCHSCREEN_ELO is not set
1163# CONFIG_TOUCHSCREEN_MTOUCH is not set
1164# CONFIG_TOUCHSCREEN_MK712 is not set
1165CONFIG_INPUT_MISC=y
1166CONFIG_INPUT_UINPUT=m
1167
1168#
1169# Hardware I/O ports
1170#
1171CONFIG_SERIO=y
1172CONFIG_SERIO_SERPORT=m
1173CONFIG_SERIO_PARKBD=m
1174CONFIG_SERIO_LIBPS2=y
1175CONFIG_SERIO_RAW=m
1176CONFIG_GAMEPORT=m
1177CONFIG_GAMEPORT_NS558=m
1178CONFIG_GAMEPORT_L4=m
1179
1180#
1181# Character devices
1182#
1183CONFIG_VT=y
1184CONFIG_VT_CONSOLE=y
1185CONFIG_HW_CONSOLE=y
1186CONFIG_SERIAL_NONSTANDARD=y
1187CONFIG_COMPUTONE=m
1188CONFIG_ROCKETPORT=m
1189CONFIG_CYCLADES=m
1190# CONFIG_CYZ_INTR is not set
1191CONFIG_DIGIEPCA=m
1192CONFIG_MOXA_INTELLIO=m
1193CONFIG_MOXA_SMARTIO=m
1194# CONFIG_ISI is not set
1195CONFIG_SYNCLINKMP=m
1196CONFIG_N_HDLC=m
1197# CONFIG_RISCOM8 is not set
1198# CONFIG_SPECIALIX is not set
1199CONFIG_SX=m
1200CONFIG_RIO=m
1201CONFIG_RIO_OLDPCI=y
1202CONFIG_STALDRV=y
1203CONFIG_STALLION=m
1204CONFIG_ISTALLION=m
1205
1206#
1207# Serial drivers
1208#
1209CONFIG_SERIAL_8250=y
1210CONFIG_SERIAL_8250_CONSOLE=y
1211CONFIG_SERIAL_8250_CS=m
1212CONFIG_SERIAL_8250_NR_UARTS=4
1213CONFIG_SERIAL_8250_RUNTIME_UARTS=4
1214CONFIG_SERIAL_8250_EXTENDED=y
1215CONFIG_SERIAL_8250_MANY_PORTS=y
1216CONFIG_SERIAL_8250_SHARE_IRQ=y
1217# CONFIG_SERIAL_8250_DETECT_IRQ is not set
1218CONFIG_SERIAL_8250_RSA=y
1219
1220#
1221# Non-8250 serial port support
1222#
1223CONFIG_SERIAL_CORE=y
1224CONFIG_SERIAL_CORE_CONSOLE=y
1225CONFIG_UNIX98_PTYS=y
1226CONFIG_LEGACY_PTYS=y
1227CONFIG_LEGACY_PTY_COUNT=256
1228CONFIG_PRINTER=m
1229# CONFIG_LP_CONSOLE is not set
1230CONFIG_PPDEV=m
1231CONFIG_TIPAR=m
1232
1233#
1234# IPMI
1235#
1236CONFIG_IPMI_HANDLER=m
1237# CONFIG_IPMI_PANIC_EVENT is not set
1238CONFIG_IPMI_DEVICE_INTERFACE=m
1239CONFIG_IPMI_SI=m
1240CONFIG_IPMI_WATCHDOG=m
1241CONFIG_IPMI_POWEROFF=m
1242
1243#
1244# Watchdog Cards
1245#
1246CONFIG_WATCHDOG=y
1247# CONFIG_WATCHDOG_NOWAYOUT is not set
1248
1249#
1250# Watchdog Device Drivers
1251#
1252CONFIG_SOFT_WATCHDOG=m
1253
1254#
1255# USB-based Watchdog Cards
1256#
1257CONFIG_USBPCWATCHDOG=m
1258CONFIG_NVRAM=m
1259CONFIG_DTLK=m
1260CONFIG_R3964=m
1261
1262#
1263# Ftape, the floppy tape device driver
1264#
1265
1266#
1267# PCMCIA character devices
1268#
1269CONFIG_SYNCLINK_CS=m
1270# CONFIG_CARDMAN_4000 is not set
1271# CONFIG_CARDMAN_4040 is not set
1272CONFIG_RAW_DRIVER=m
1273CONFIG_MAX_RAW_DEVS=256
1274
1275#
1276# TPM devices
1277#
1278# CONFIG_TCG_TPM is not set
1279# CONFIG_TELCLOCK is not set
1280
1281#
1282# I2C support
1283#
1284CONFIG_I2C=m
1285CONFIG_I2C_CHARDEV=m
1286
1287#
1288# I2C Algorithms
1289#
1290CONFIG_I2C_ALGOBIT=m
1291CONFIG_I2C_ALGOPCF=m
1292CONFIG_I2C_ALGOPCA=m
1293
1294#
1295# I2C Hardware Bus support
1296#
1297CONFIG_I2C_ISA=m
1298CONFIG_I2C_PARPORT=m
1299CONFIG_I2C_PARPORT_LIGHT=m
1300CONFIG_I2C_STUB=m
1301CONFIG_I2C_PCA_ISA=m
1302
1303#
1304# Miscellaneous I2C Chip support
1305#
1306# CONFIG_SENSORS_DS1337 is not set
1307# CONFIG_SENSORS_DS1374 is not set
1308CONFIG_SENSORS_EEPROM=m
1309CONFIG_SENSORS_PCF8574=m
1310# CONFIG_SENSORS_PCA9539 is not set
1311CONFIG_SENSORS_PCF8591=m
1312# CONFIG_SENSORS_MAX6875 is not set
1313# CONFIG_I2C_DEBUG_CORE is not set
1314# CONFIG_I2C_DEBUG_ALGO is not set
1315# CONFIG_I2C_DEBUG_BUS is not set
1316# CONFIG_I2C_DEBUG_CHIP is not set
1317
1318#
1319# SPI support
1320#
1321# CONFIG_SPI is not set
1322# CONFIG_SPI_MASTER is not set
1323
1324#
1325# Dallas's 1-wire bus
1326#
1327CONFIG_W1=m
1328
1329#
1330# 1-wire Bus Masters
1331#
1332# CONFIG_W1_MASTER_DS9490 is not set
1333# CONFIG_W1_MASTER_DS2482 is not set
1334
1335#
1336# 1-wire Slaves
1337#
1338# CONFIG_W1_SLAVE_THERM is not set
1339# CONFIG_W1_SLAVE_SMEM is not set
1340# CONFIG_W1_SLAVE_DS2433 is not set
1341
1342#
1343# Hardware Monitoring support
1344#
1345CONFIG_HWMON=y
1346CONFIG_HWMON_VID=m
1347CONFIG_SENSORS_ADM1021=m
1348CONFIG_SENSORS_ADM1025=m
1349CONFIG_SENSORS_ADM1026=m
1350CONFIG_SENSORS_ADM1031=m
1351# CONFIG_SENSORS_ADM9240 is not set
1352CONFIG_SENSORS_ASB100=m
1353# CONFIG_SENSORS_ATXP1 is not set
1354CONFIG_SENSORS_DS1621=m
1355# CONFIG_SENSORS_F71805F is not set
1356CONFIG_SENSORS_FSCHER=m
1357# CONFIG_SENSORS_FSCPOS is not set
1358CONFIG_SENSORS_GL518SM=m
1359# CONFIG_SENSORS_GL520SM is not set
1360CONFIG_SENSORS_IT87=m
1361CONFIG_SENSORS_LM63=m
1362CONFIG_SENSORS_LM75=m
1363CONFIG_SENSORS_LM77=m
1364CONFIG_SENSORS_LM78=m
1365CONFIG_SENSORS_LM80=m
1366CONFIG_SENSORS_LM83=m
1367CONFIG_SENSORS_LM85=m
1368CONFIG_SENSORS_LM87=m
1369CONFIG_SENSORS_LM90=m
1370# CONFIG_SENSORS_LM92 is not set
1371CONFIG_SENSORS_MAX1619=m
1372CONFIG_SENSORS_PC87360=m
1373CONFIG_SENSORS_SMSC47M1=m
1374# CONFIG_SENSORS_SMSC47B397 is not set
1375CONFIG_SENSORS_W83781D=m
1376# CONFIG_SENSORS_W83792D is not set
1377CONFIG_SENSORS_W83L785TS=m
1378CONFIG_SENSORS_W83627HF=m
1379# CONFIG_SENSORS_W83627EHF is not set
1380# CONFIG_HWMON_DEBUG_CHIP is not set
1381
1382#
1383# Misc devices
1384#
1385
1386#
1387# LED devices
1388#
1389# CONFIG_NEW_LEDS is not set
1390
1391#
1392# Multimedia devices
1393#
1394# CONFIG_VIDEO_DEV is not set
1395
1396#
1397# Digital Video Broadcasting Devices
1398#
1399CONFIG_DVB=y
1400CONFIG_DVB_CORE=m
1401
1402#
1403# Supported USB Adapters
1404#
1405# CONFIG_DVB_USB is not set
1406CONFIG_DVB_TTUSB_BUDGET=m
1407CONFIG_DVB_TTUSB_DEC=m
1408CONFIG_DVB_CINERGYT2=m
1409CONFIG_DVB_CINERGYT2_TUNING=y
1410CONFIG_DVB_CINERGYT2_STREAM_URB_COUNT=32
1411CONFIG_DVB_CINERGYT2_STREAM_BUF_SIZE=512
1412CONFIG_DVB_CINERGYT2_QUERY_INTERVAL=250
1413CONFIG_DVB_CINERGYT2_ENABLE_RC_INPUT_DEVICE=y
1414CONFIG_DVB_CINERGYT2_RC_QUERY_INTERVAL=100
1415
1416#
1417# Supported FlexCopII (B2C2) Adapters
1418#
1419# CONFIG_DVB_B2C2_FLEXCOP is not set
1420
1421#
1422# Supported DVB Frontends
1423#
1424
1425#
1426# Customise DVB Frontends
1427#
1428
1429#
1430# DVB-S (satellite) frontends
1431#
1432CONFIG_DVB_STV0299=m
1433CONFIG_DVB_CX24110=m
1434# CONFIG_DVB_CX24123 is not set
1435CONFIG_DVB_TDA8083=m
1436CONFIG_DVB_MT312=m
1437CONFIG_DVB_VES1X93=m
1438# CONFIG_DVB_S5H1420 is not set
1439
1440#
1441# DVB-T (terrestrial) frontends
1442#
1443CONFIG_DVB_SP8870=m
1444CONFIG_DVB_SP887X=m
1445CONFIG_DVB_CX22700=m
1446CONFIG_DVB_CX22702=m
1447CONFIG_DVB_L64781=m
1448CONFIG_DVB_TDA1004X=m
1449CONFIG_DVB_NXT6000=m
1450CONFIG_DVB_MT352=m
1451# CONFIG_DVB_ZL10353 is not set
1452CONFIG_DVB_DIB3000MB=m
1453CONFIG_DVB_DIB3000MC=m
1454
1455#
1456# DVB-C (cable) frontends
1457#
1458CONFIG_DVB_VES1820=m
1459CONFIG_DVB_TDA10021=m
1460CONFIG_DVB_STV0297=m
1461
1462#
1463# ATSC (North American/Korean Terresterial DTV) frontends
1464#
1465# CONFIG_DVB_NXT200X is not set
1466# CONFIG_DVB_OR51211 is not set
1467# CONFIG_DVB_OR51132 is not set
1468# CONFIG_DVB_BCM3510 is not set
1469# CONFIG_DVB_LGDT330X is not set
1470# CONFIG_USB_DABUSB is not set
1471
1472#
1473# Graphics support
1474#
1475# CONFIG_FB is not set
1476
1477#
1478# Console display driver support
1479#
1480# CONFIG_VGA_CONSOLE is not set
1481CONFIG_DUMMY_CONSOLE=y
1482
1483#
1484# Sound
1485#
1486CONFIG_SOUND=m
1487
1488#
1489# Advanced Linux Sound Architecture
1490#
1491CONFIG_SND=m
1492CONFIG_SND_TIMER=m
1493CONFIG_SND_PCM=m
1494CONFIG_SND_HWDEP=m
1495CONFIG_SND_RAWMIDI=m
1496CONFIG_SND_SEQUENCER=m
1497CONFIG_SND_SEQ_DUMMY=m
1498CONFIG_SND_OSSEMUL=y
1499CONFIG_SND_MIXER_OSS=m
1500CONFIG_SND_PCM_OSS=m
1501CONFIG_SND_PCM_OSS_PLUGINS=y
1502CONFIG_SND_SEQUENCER_OSS=y
1503# CONFIG_SND_DYNAMIC_MINORS is not set
1504CONFIG_SND_SUPPORT_OLD_API=y
1505CONFIG_SND_VERBOSE_PROCFS=y
1506# CONFIG_SND_VERBOSE_PRINTK is not set
1507# CONFIG_SND_DEBUG is not set
1508
1509#
1510# Generic devices
1511#
1512CONFIG_SND_MPU401_UART=m
1513CONFIG_SND_DUMMY=m
1514CONFIG_SND_VIRMIDI=m
1515CONFIG_SND_MTPAV=m
1516CONFIG_SND_SERIAL_U16550=m
1517CONFIG_SND_MPU401=m
1518
1519#
1520# ALSA ARM devices
1521#
1522
1523#
1524# USB devices
1525#
1526CONFIG_SND_USB_AUDIO=m
1527
1528#
1529# PCMCIA devices
1530#
1531
1532#
1533# Open Sound System
1534#
1535CONFIG_SOUND_PRIME=m
1536# CONFIG_OBSOLETE_OSS_DRIVER is not set
1537# CONFIG_SOUND_MSNDCLAS is not set
1538# CONFIG_SOUND_MSNDPIN is not set
1539CONFIG_SOUND_TVMIXER=m
1540
1541#
1542# USB support
1543#
1544CONFIG_USB_ARCH_HAS_HCD=y
1545# CONFIG_USB_ARCH_HAS_OHCI is not set
1546# CONFIG_USB_ARCH_HAS_EHCI is not set
1547CONFIG_USB=m
1548# CONFIG_USB_DEBUG is not set
1549
1550#
1551# Miscellaneous USB options
1552#
1553CONFIG_USB_DEVICEFS=y
1554CONFIG_USB_BANDWIDTH=y
1555# CONFIG_USB_DYNAMIC_MINORS is not set
1556# CONFIG_USB_SUSPEND is not set
1557# CONFIG_USB_OTG is not set
1558
1559#
1560# USB Host Controller Drivers
1561#
1562# CONFIG_USB_ISP116X_HCD is not set
1563CONFIG_USB_SL811_HCD=m
1564# CONFIG_USB_SL811_CS is not set
1565
1566#
1567# USB Device Class drivers
1568#
1569CONFIG_USB_ACM=m
1570CONFIG_USB_PRINTER=m
1571
1572#
1573# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
1574#
1575
1576#
1577# may also be needed; see USB_STORAGE Help for more information
1578#
1579CONFIG_USB_STORAGE=m
1580# CONFIG_USB_STORAGE_DEBUG is not set
1581CONFIG_USB_STORAGE_DATAFAB=y
1582CONFIG_USB_STORAGE_FREECOM=y
1583CONFIG_USB_STORAGE_ISD200=y
1584CONFIG_USB_STORAGE_DPCM=y
1585CONFIG_USB_STORAGE_USBAT=y
1586CONFIG_USB_STORAGE_SDDR09=y
1587CONFIG_USB_STORAGE_SDDR55=y
1588CONFIG_USB_STORAGE_JUMPSHOT=y
1589# CONFIG_USB_STORAGE_ALAUDA is not set
1590# CONFIG_USB_LIBUSUAL is not set
1591
1592#
1593# USB Input Devices
1594#
1595CONFIG_USB_HID=m
1596CONFIG_USB_HIDINPUT=y
1597# CONFIG_USB_HIDINPUT_POWERBOOK is not set
1598# CONFIG_HID_FF is not set
1599CONFIG_USB_HIDDEV=y
1600
1601#
1602# USB HID Boot Protocol drivers
1603#
1604CONFIG_USB_KBD=m
1605CONFIG_USB_MOUSE=m
1606CONFIG_USB_AIPTEK=m
1607CONFIG_USB_WACOM=m
1608# CONFIG_USB_ACECAD is not set
1609CONFIG_USB_KBTAB=m
1610CONFIG_USB_POWERMATE=m
1611CONFIG_USB_MTOUCH=m
1612# CONFIG_USB_ITMTOUCH is not set
1613CONFIG_USB_EGALAX=m
1614# CONFIG_USB_YEALINK is not set
1615CONFIG_USB_XPAD=m
1616CONFIG_USB_ATI_REMOTE=m
1617# CONFIG_USB_ATI_REMOTE2 is not set
1618# CONFIG_USB_KEYSPAN_REMOTE is not set
1619# CONFIG_USB_APPLETOUCH is not set
1620
1621#
1622# USB Imaging devices
1623#
1624CONFIG_USB_MDC800=m
1625CONFIG_USB_MICROTEK=m
1626
1627#
1628# USB Network Adapters
1629#
1630CONFIG_USB_CATC=m
1631CONFIG_USB_KAWETH=m
1632CONFIG_USB_PEGASUS=m
1633CONFIG_USB_RTL8150=m
1634CONFIG_USB_USBNET=m
1635CONFIG_USB_NET_AX8817X=m
1636CONFIG_USB_NET_CDCETHER=m
1637# CONFIG_USB_NET_GL620A is not set
1638CONFIG_USB_NET_NET1080=m
1639# CONFIG_USB_NET_PLUSB is not set
1640# CONFIG_USB_NET_RNDIS_HOST is not set
1641# CONFIG_USB_NET_CDC_SUBSET is not set
1642CONFIG_USB_NET_ZAURUS=m
1643# CONFIG_USB_ZD1201 is not set
1644CONFIG_USB_MON=y
1645
1646#
1647# USB port drivers
1648#
1649CONFIG_USB_USS720=m
1650
1651#
1652# USB Serial Converter support
1653#
1654CONFIG_USB_SERIAL=m
1655CONFIG_USB_SERIAL_GENERIC=y
1656# CONFIG_USB_SERIAL_AIRPRIME is not set
1657# CONFIG_USB_SERIAL_ANYDATA is not set
1658CONFIG_USB_SERIAL_BELKIN=m
1659CONFIG_USB_SERIAL_WHITEHEAT=m
1660CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
1661# CONFIG_USB_SERIAL_CP2101 is not set
1662CONFIG_USB_SERIAL_CYPRESS_M8=m
1663CONFIG_USB_SERIAL_EMPEG=m
1664CONFIG_USB_SERIAL_FTDI_SIO=m
1665CONFIG_USB_SERIAL_VISOR=m
1666CONFIG_USB_SERIAL_IPAQ=m
1667CONFIG_USB_SERIAL_IR=m
1668CONFIG_USB_SERIAL_EDGEPORT=m
1669CONFIG_USB_SERIAL_EDGEPORT_TI=m
1670# CONFIG_USB_SERIAL_GARMIN is not set
1671CONFIG_USB_SERIAL_IPW=m
1672CONFIG_USB_SERIAL_KEYSPAN_PDA=m
1673CONFIG_USB_SERIAL_KEYSPAN=m
1674# CONFIG_USB_SERIAL_KEYSPAN_MPR is not set
1675# CONFIG_USB_SERIAL_KEYSPAN_USA28 is not set
1676# CONFIG_USB_SERIAL_KEYSPAN_USA28X is not set
1677# CONFIG_USB_SERIAL_KEYSPAN_USA28XA is not set
1678# CONFIG_USB_SERIAL_KEYSPAN_USA28XB is not set
1679# CONFIG_USB_SERIAL_KEYSPAN_USA19 is not set
1680# CONFIG_USB_SERIAL_KEYSPAN_USA18X is not set
1681# CONFIG_USB_SERIAL_KEYSPAN_USA19W is not set
1682# CONFIG_USB_SERIAL_KEYSPAN_USA19QW is not set
1683# CONFIG_USB_SERIAL_KEYSPAN_USA19QI is not set
1684# CONFIG_USB_SERIAL_KEYSPAN_USA49W is not set
1685# CONFIG_USB_SERIAL_KEYSPAN_USA49WLC is not set
1686CONFIG_USB_SERIAL_KLSI=m
1687CONFIG_USB_SERIAL_KOBIL_SCT=m
1688CONFIG_USB_SERIAL_MCT_U232=m
1689# CONFIG_USB_SERIAL_NAVMAN is not set
1690CONFIG_USB_SERIAL_PL2303=m
1691# CONFIG_USB_SERIAL_HP4X is not set
1692CONFIG_USB_SERIAL_SAFE=m
1693# CONFIG_USB_SERIAL_SAFE_PADDED is not set
1694# CONFIG_USB_SERIAL_TI is not set
1695CONFIG_USB_SERIAL_CYBERJACK=m
1696CONFIG_USB_SERIAL_XIRCOM=m
1697CONFIG_USB_SERIAL_OMNINET=m
1698CONFIG_USB_EZUSB=y
1699
1700#
1701# USB Miscellaneous drivers
1702#
1703# CONFIG_USB_EMI62 is not set
1704# CONFIG_USB_EMI26 is not set
1705CONFIG_USB_AUERSWALD=m
1706CONFIG_USB_RIO500=m
1707CONFIG_USB_LEGOTOWER=m
1708CONFIG_USB_LCD=m
1709CONFIG_USB_LED=m
1710CONFIG_USB_CYTHERM=m
1711CONFIG_USB_PHIDGETKIT=m
1712CONFIG_USB_PHIDGETSERVO=m
1713# CONFIG_USB_IDMOUSE is not set
1714# CONFIG_USB_LD is not set
1715CONFIG_USB_TEST=m
1716
1717#
1718# USB DSL modem support
1719#
1720CONFIG_USB_ATM=m
1721CONFIG_USB_SPEEDTOUCH=m
1722# CONFIG_USB_CXACRU is not set
1723# CONFIG_USB_UEAGLEATM is not set
1724# CONFIG_USB_XUSBATM is not set
1725
1726#
1727# USB Gadget Support
1728#
1729CONFIG_USB_GADGET=m
1730# CONFIG_USB_GADGET_DEBUG_FILES is not set
1731CONFIG_USB_GADGET_SELECTED=y
1732# CONFIG_USB_GADGET_NET2280 is not set
1733# CONFIG_USB_GADGET_PXA2XX is not set
1734# CONFIG_USB_GADGET_GOKU is not set
1735# CONFIG_USB_GADGET_LH7A40X is not set
1736# CONFIG_USB_GADGET_OMAP is not set
1737# CONFIG_USB_GADGET_AT91 is not set
1738CONFIG_USB_GADGET_DUMMY_HCD=y
1739CONFIG_USB_DUMMY_HCD=m
1740CONFIG_USB_GADGET_DUALSPEED=y
1741CONFIG_USB_ZERO=m
1742CONFIG_USB_ETH=m
1743CONFIG_USB_ETH_RNDIS=y
1744CONFIG_USB_GADGETFS=m
1745CONFIG_USB_FILE_STORAGE=m
1746# CONFIG_USB_FILE_STORAGE_TEST is not set
1747CONFIG_USB_G_SERIAL=m
1748
1749#
1750# MMC/SD Card support
1751#
1752CONFIG_MMC=m
1753# CONFIG_MMC_DEBUG is not set
1754CONFIG_MMC_BLOCK=m
1755
1756#
1757# Real Time Clock
1758#
1759CONFIG_RTC_LIB=y
1760# CONFIG_RTC_CLASS is not set
1761
1762#
1763# File systems
1764#
1765CONFIG_EXT2_FS=y
1766CONFIG_EXT2_FS_XATTR=y
1767CONFIG_EXT2_FS_POSIX_ACL=y
1768CONFIG_EXT2_FS_SECURITY=y
1769# CONFIG_EXT2_FS_XIP is not set
1770CONFIG_EXT3_FS=m
1771CONFIG_EXT3_FS_XATTR=y
1772CONFIG_EXT3_FS_POSIX_ACL=y
1773CONFIG_EXT3_FS_SECURITY=y
1774CONFIG_JBD=m
1775# CONFIG_JBD_DEBUG is not set
1776CONFIG_FS_MBCACHE=y
1777CONFIG_REISERFS_FS=m
1778# CONFIG_REISERFS_CHECK is not set
1779# CONFIG_REISERFS_PROC_INFO is not set
1780CONFIG_REISERFS_FS_XATTR=y
1781CONFIG_REISERFS_FS_POSIX_ACL=y
1782CONFIG_REISERFS_FS_SECURITY=y
1783CONFIG_JFS_FS=m
1784CONFIG_JFS_POSIX_ACL=y
1785# CONFIG_JFS_SECURITY is not set
1786# CONFIG_JFS_DEBUG is not set
1787CONFIG_JFS_STATISTICS=y
1788CONFIG_FS_POSIX_ACL=y
1789CONFIG_XFS_FS=m
1790CONFIG_XFS_EXPORT=y
1791CONFIG_XFS_QUOTA=y
1792CONFIG_XFS_SECURITY=y
1793CONFIG_XFS_POSIX_ACL=y
1794CONFIG_XFS_RT=y
1795# CONFIG_OCFS2_FS is not set
1796CONFIG_MINIX_FS=m
1797CONFIG_ROMFS_FS=m
1798CONFIG_INOTIFY=y
1799CONFIG_QUOTA=y
1800CONFIG_QFMT_V1=m
1801CONFIG_QFMT_V2=m
1802CONFIG_QUOTACTL=y
1803CONFIG_DNOTIFY=y
1804CONFIG_AUTOFS_FS=m
1805CONFIG_AUTOFS4_FS=m
1806# CONFIG_FUSE_FS is not set
1807
1808#
1809# CD-ROM/DVD Filesystems
1810#
1811CONFIG_ISO9660_FS=m
1812CONFIG_JOLIET=y
1813CONFIG_ZISOFS=y
1814CONFIG_ZISOFS_FS=m
1815CONFIG_UDF_FS=m
1816CONFIG_UDF_NLS=y
1817
1818#
1819# DOS/FAT/NT Filesystems
1820#
1821CONFIG_FAT_FS=m
1822CONFIG_MSDOS_FS=m
1823CONFIG_VFAT_FS=m
1824CONFIG_FAT_DEFAULT_CODEPAGE=437
1825CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
1826CONFIG_NTFS_FS=m
1827# CONFIG_NTFS_DEBUG is not set
1828# CONFIG_NTFS_RW is not set
1829
1830#
1831# Pseudo filesystems
1832#
1833CONFIG_PROC_FS=y
1834CONFIG_SYSFS=y
1835CONFIG_TMPFS=y
1836# CONFIG_HUGETLB_PAGE is not set
1837CONFIG_RAMFS=y
1838# CONFIG_CONFIGFS_FS is not set
1839
1840#
1841# Miscellaneous filesystems
1842#
1843CONFIG_ADFS_FS=m
1844# CONFIG_ADFS_FS_RW is not set
1845CONFIG_AFFS_FS=m
1846CONFIG_HFS_FS=m
1847CONFIG_HFSPLUS_FS=m
1848CONFIG_BEFS_FS=m
1849# CONFIG_BEFS_DEBUG is not set
1850CONFIG_BFS_FS=m
1851CONFIG_EFS_FS=m
1852CONFIG_JFFS_FS=m
1853CONFIG_JFFS_FS_VERBOSE=0
1854CONFIG_JFFS_PROC_FS=y
1855CONFIG_JFFS2_FS=m
1856CONFIG_JFFS2_FS_DEBUG=0
1857CONFIG_JFFS2_FS_WRITEBUFFER=y
1858# CONFIG_JFFS2_SUMMARY is not set
1859# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
1860CONFIG_JFFS2_ZLIB=y
1861CONFIG_JFFS2_RTIME=y
1862# CONFIG_JFFS2_RUBIN is not set
1863CONFIG_CRAMFS=y
1864CONFIG_VXFS_FS=m
1865CONFIG_HPFS_FS=m
1866CONFIG_QNX4FS_FS=m
1867CONFIG_SYSV_FS=m
1868CONFIG_UFS_FS=m
1869
1870#
1871# Network File Systems
1872#
1873CONFIG_NFS_FS=m
1874CONFIG_NFS_V3=y
1875# CONFIG_NFS_V3_ACL is not set
1876CONFIG_NFS_V4=y
1877CONFIG_NFS_DIRECTIO=y
1878CONFIG_NFSD=m
1879CONFIG_NFSD_V3=y
1880# CONFIG_NFSD_V3_ACL is not set
1881CONFIG_NFSD_V4=y
1882CONFIG_NFSD_TCP=y
1883CONFIG_LOCKD=m
1884CONFIG_LOCKD_V4=y
1885CONFIG_EXPORTFS=m
1886CONFIG_NFS_COMMON=y
1887CONFIG_SUNRPC=m
1888CONFIG_SUNRPC_GSS=m
1889CONFIG_RPCSEC_GSS_KRB5=m
1890CONFIG_RPCSEC_GSS_SPKM3=m
1891CONFIG_SMB_FS=m
1892# CONFIG_SMB_NLS_DEFAULT is not set
1893CONFIG_CIFS=m
1894# CONFIG_CIFS_STATS is not set
1895# CONFIG_CIFS_XATTR is not set
1896# CONFIG_CIFS_EXPERIMENTAL is not set
1897CONFIG_NCP_FS=m
1898CONFIG_NCPFS_PACKET_SIGNING=y
1899CONFIG_NCPFS_IOCTL_LOCKING=y
1900CONFIG_NCPFS_STRONG=y
1901CONFIG_NCPFS_NFS_NS=y
1902CONFIG_NCPFS_OS2_NS=y
1903# CONFIG_NCPFS_SMALLDOS is not set
1904CONFIG_NCPFS_NLS=y
1905CONFIG_NCPFS_EXTRAS=y
1906CONFIG_CODA_FS=m
1907# CONFIG_CODA_FS_OLD_API is not set
1908CONFIG_AFS_FS=m
1909CONFIG_RXRPC=m
1910# CONFIG_9P_FS is not set
1911
1912#
1913# Partition Types
1914#
1915CONFIG_PARTITION_ADVANCED=y
1916CONFIG_ACORN_PARTITION=y
1917# CONFIG_ACORN_PARTITION_CUMANA is not set
1918# CONFIG_ACORN_PARTITION_EESOX is not set
1919CONFIG_ACORN_PARTITION_ICS=y
1920# CONFIG_ACORN_PARTITION_ADFS is not set
1921# CONFIG_ACORN_PARTITION_POWERTEC is not set
1922CONFIG_ACORN_PARTITION_RISCIX=y
1923CONFIG_OSF_PARTITION=y
1924CONFIG_AMIGA_PARTITION=y
1925CONFIG_ATARI_PARTITION=y
1926CONFIG_MAC_PARTITION=y
1927CONFIG_MSDOS_PARTITION=y
1928CONFIG_BSD_DISKLABEL=y
1929CONFIG_MINIX_SUBPARTITION=y
1930CONFIG_SOLARIS_X86_PARTITION=y
1931CONFIG_UNIXWARE_DISKLABEL=y
1932CONFIG_LDM_PARTITION=y
1933# CONFIG_LDM_DEBUG is not set
1934CONFIG_SGI_PARTITION=y
1935CONFIG_ULTRIX_PARTITION=y
1936CONFIG_SUN_PARTITION=y
1937# CONFIG_KARMA_PARTITION is not set
1938# CONFIG_EFI_PARTITION is not set
1939
1940#
1941# Native Language Support
1942#
1943CONFIG_NLS=y
1944CONFIG_NLS_DEFAULT="cp437"
1945CONFIG_NLS_CODEPAGE_437=m
1946CONFIG_NLS_CODEPAGE_737=m
1947CONFIG_NLS_CODEPAGE_775=m
1948CONFIG_NLS_CODEPAGE_850=m
1949CONFIG_NLS_CODEPAGE_852=m
1950CONFIG_NLS_CODEPAGE_855=m
1951CONFIG_NLS_CODEPAGE_857=m
1952CONFIG_NLS_CODEPAGE_860=m
1953CONFIG_NLS_CODEPAGE_861=m
1954CONFIG_NLS_CODEPAGE_862=m
1955CONFIG_NLS_CODEPAGE_863=m
1956CONFIG_NLS_CODEPAGE_864=m
1957CONFIG_NLS_CODEPAGE_865=m
1958CONFIG_NLS_CODEPAGE_866=m
1959CONFIG_NLS_CODEPAGE_869=m
1960CONFIG_NLS_CODEPAGE_936=m
1961CONFIG_NLS_CODEPAGE_950=m
1962CONFIG_NLS_CODEPAGE_932=m
1963CONFIG_NLS_CODEPAGE_949=m
1964CONFIG_NLS_CODEPAGE_874=m
1965CONFIG_NLS_ISO8859_8=m
1966CONFIG_NLS_CODEPAGE_1250=m
1967CONFIG_NLS_CODEPAGE_1251=m
1968CONFIG_NLS_ASCII=m
1969CONFIG_NLS_ISO8859_1=m
1970CONFIG_NLS_ISO8859_2=m
1971CONFIG_NLS_ISO8859_3=m
1972CONFIG_NLS_ISO8859_4=m
1973CONFIG_NLS_ISO8859_5=m
1974CONFIG_NLS_ISO8859_6=m
1975CONFIG_NLS_ISO8859_7=m
1976CONFIG_NLS_ISO8859_9=m
1977CONFIG_NLS_ISO8859_13=m
1978CONFIG_NLS_ISO8859_14=m
1979CONFIG_NLS_ISO8859_15=m
1980CONFIG_NLS_KOI8_R=m
1981CONFIG_NLS_KOI8_U=m
1982CONFIG_NLS_UTF8=m
1983
1984#
1985# Profiling support
1986#
1987CONFIG_PROFILING=y
1988CONFIG_OPROFILE=m
1989
1990#
1991# Kernel hacking
1992#
1993# CONFIG_PRINTK_TIME is not set
1994CONFIG_MAGIC_SYSRQ=y
1995CONFIG_DEBUG_KERNEL=y
1996CONFIG_LOG_BUF_SHIFT=14
1997CONFIG_DETECT_SOFTLOCKUP=y
1998# CONFIG_SCHEDSTATS is not set
1999# CONFIG_DEBUG_SLAB is not set
2000CONFIG_DEBUG_PREEMPT=y
2001CONFIG_DEBUG_MUTEXES=y
2002# CONFIG_DEBUG_SPINLOCK is not set
2003# CONFIG_DEBUG_SPINLOCK_SLEEP is not set
2004# CONFIG_DEBUG_KOBJECT is not set
2005# CONFIG_DEBUG_BUGVERBOSE is not set
2006CONFIG_DEBUG_INFO=y
2007# CONFIG_DEBUG_FS is not set
2008# CONFIG_DEBUG_VM is not set
2009CONFIG_FRAME_POINTER=y
2010# CONFIG_UNWIND_INFO is not set
2011CONFIG_FORCED_INLINING=y
2012# CONFIG_RCU_TORTURE_TEST is not set
2013# CONFIG_DEBUG_USER is not set
2014# CONFIG_DEBUG_WAITQ is not set
2015# CONFIG_DEBUG_ERRORS is not set
2016CONFIG_DEBUG_LL=y
2017# CONFIG_DEBUG_ICEDCC is not set
2018
2019#
2020# Security options
2021#
2022# CONFIG_KEYS is not set
2023CONFIG_SECURITY=y
2024# CONFIG_SECURITY_NETWORK is not set
2025CONFIG_SECURITY_CAPABILITIES=m
2026CONFIG_SECURITY_ROOTPLUG=m
2027CONFIG_SECURITY_SECLVL=m
2028
2029#
2030# Cryptographic options
2031#
2032CONFIG_CRYPTO=y
2033CONFIG_CRYPTO_HMAC=y
2034CONFIG_CRYPTO_NULL=m
2035CONFIG_CRYPTO_MD4=m
2036CONFIG_CRYPTO_MD5=y
2037CONFIG_CRYPTO_SHA1=m
2038CONFIG_CRYPTO_SHA256=m
2039CONFIG_CRYPTO_SHA512=m
2040CONFIG_CRYPTO_WP512=m
2041# CONFIG_CRYPTO_TGR192 is not set
2042CONFIG_CRYPTO_DES=m
2043CONFIG_CRYPTO_BLOWFISH=m
2044CONFIG_CRYPTO_TWOFISH=m
2045CONFIG_CRYPTO_SERPENT=m
2046CONFIG_CRYPTO_AES=m
2047CONFIG_CRYPTO_CAST5=m
2048CONFIG_CRYPTO_CAST6=m
2049CONFIG_CRYPTO_TEA=m
2050CONFIG_CRYPTO_ARC4=m
2051CONFIG_CRYPTO_KHAZAD=m
2052CONFIG_CRYPTO_ANUBIS=m
2053CONFIG_CRYPTO_DEFLATE=m
2054CONFIG_CRYPTO_MICHAEL_MIC=m
2055CONFIG_CRYPTO_CRC32C=m
2056CONFIG_CRYPTO_TEST=m
2057
2058#
2059# Hardware crypto devices
2060#
2061
2062#
2063# Library routines
2064#
2065CONFIG_CRC_CCITT=m
2066CONFIG_CRC16=m
2067CONFIG_CRC32=y
2068CONFIG_LIBCRC32C=m
2069CONFIG_ZLIB_INFLATE=y
2070CONFIG_ZLIB_DEFLATE=m
2071CONFIG_REED_SOLOMON=m
2072CONFIG_REED_SOLOMON_DEC16=y
diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S
index dbcb11a31f78..b5bcebca1cd6 100644
--- a/arch/arm/kernel/entry-common.S
+++ b/arch/arm/kernel/entry-common.S
@@ -271,7 +271,7 @@ ENTRY(sys_call_table)
271@ r8 = syscall table 271@ r8 = syscall table
272 .type sys_syscall, #function 272 .type sys_syscall, #function
273sys_syscall: 273sys_syscall:
274 eor scno, r0, #__NR_OABI_SYSCALL_BASE 274 bic scno, r0, #__NR_OABI_SYSCALL_BASE
275 cmp scno, #__NR_syscall - __NR_SYSCALL_BASE 275 cmp scno, #__NR_syscall - __NR_SYSCALL_BASE
276 cmpne scno, #NR_syscalls @ check range 276 cmpne scno, #NR_syscalls @ check range
277 stmloia sp, {r5, r6} @ shuffle args 277 stmloia sp, {r5, r6} @ shuffle args
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 2d5896b36181..bcc19fbb32df 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -342,10 +342,10 @@ __do_irq(unsigned int irq, struct irqaction *action, struct pt_regs *regs)
342 342
343#ifdef CONFIG_NO_IDLE_HZ 343#ifdef CONFIG_NO_IDLE_HZ
344 if (!(action->flags & SA_TIMER) && system_timer->dyn_tick != NULL) { 344 if (!(action->flags & SA_TIMER) && system_timer->dyn_tick != NULL) {
345 write_seqlock(&xtime_lock); 345 spin_lock(&system_timer->dyn_tick->lock);
346 if (system_timer->dyn_tick->state & DYN_TICK_ENABLED) 346 if (system_timer->dyn_tick->state & DYN_TICK_ENABLED)
347 system_timer->dyn_tick->handler(irq, 0, regs); 347 system_timer->dyn_tick->handler(irq, 0, regs);
348 write_sequnlock(&xtime_lock); 348 spin_unlock(&system_timer->dyn_tick->lock);
349 } 349 }
350#endif 350#endif
351 351
diff --git a/arch/arm/kernel/time.c b/arch/arm/kernel/time.c
index d6bd435a6857..9c12d4fefbd3 100644
--- a/arch/arm/kernel/time.c
+++ b/arch/arm/kernel/time.c
@@ -379,7 +379,7 @@ static int timer_dyn_tick_enable(void)
379 int ret = -ENODEV; 379 int ret = -ENODEV;
380 380
381 if (dyn_tick) { 381 if (dyn_tick) {
382 write_seqlock_irqsave(&xtime_lock, flags); 382 spin_lock_irqsave(&dyn_tick->lock, flags);
383 ret = 0; 383 ret = 0;
384 if (!(dyn_tick->state & DYN_TICK_ENABLED)) { 384 if (!(dyn_tick->state & DYN_TICK_ENABLED)) {
385 ret = dyn_tick->enable(); 385 ret = dyn_tick->enable();
@@ -387,7 +387,7 @@ static int timer_dyn_tick_enable(void)
387 if (ret == 0) 387 if (ret == 0)
388 dyn_tick->state |= DYN_TICK_ENABLED; 388 dyn_tick->state |= DYN_TICK_ENABLED;
389 } 389 }
390 write_sequnlock_irqrestore(&xtime_lock, flags); 390 spin_unlock_irqrestore(&dyn_tick->lock, flags);
391 } 391 }
392 392
393 return ret; 393 return ret;
@@ -400,7 +400,7 @@ static int timer_dyn_tick_disable(void)
400 int ret = -ENODEV; 400 int ret = -ENODEV;
401 401
402 if (dyn_tick) { 402 if (dyn_tick) {
403 write_seqlock_irqsave(&xtime_lock, flags); 403 spin_lock_irqsave(&dyn_tick->lock, flags);
404 ret = 0; 404 ret = 0;
405 if (dyn_tick->state & DYN_TICK_ENABLED) { 405 if (dyn_tick->state & DYN_TICK_ENABLED) {
406 ret = dyn_tick->disable(); 406 ret = dyn_tick->disable();
@@ -408,7 +408,7 @@ static int timer_dyn_tick_disable(void)
408 if (ret == 0) 408 if (ret == 0)
409 dyn_tick->state &= ~DYN_TICK_ENABLED; 409 dyn_tick->state &= ~DYN_TICK_ENABLED;
410 } 410 }
411 write_sequnlock_irqrestore(&xtime_lock, flags); 411 spin_unlock_irqrestore(&dyn_tick->lock, flags);
412 } 412 }
413 413
414 return ret; 414 return ret;
@@ -422,15 +422,20 @@ static int timer_dyn_tick_disable(void)
422void timer_dyn_reprogram(void) 422void timer_dyn_reprogram(void)
423{ 423{
424 struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick; 424 struct dyn_tick_timer *dyn_tick = system_timer->dyn_tick;
425 unsigned long next, seq; 425 unsigned long next, seq, flags;
426 426
427 if (dyn_tick && (dyn_tick->state & DYN_TICK_ENABLED)) { 427 if (!dyn_tick)
428 return;
429
430 spin_lock_irqsave(&dyn_tick->lock, flags);
431 if (dyn_tick->state & DYN_TICK_ENABLED) {
428 next = next_timer_interrupt(); 432 next = next_timer_interrupt();
429 do { 433 do {
430 seq = read_seqbegin(&xtime_lock); 434 seq = read_seqbegin(&xtime_lock);
431 dyn_tick->reprogram(next_timer_interrupt() - jiffies); 435 dyn_tick->reprogram(next - jiffies);
432 } while (read_seqretry(&xtime_lock, seq)); 436 } while (read_seqretry(&xtime_lock, seq));
433 } 437 }
438 spin_unlock_irqrestore(&dyn_tick->lock, flags);
434} 439}
435 440
436static ssize_t timer_show_dyn_tick(struct sys_device *dev, char *buf) 441static ssize_t timer_show_dyn_tick(struct sys_device *dev, char *buf)
@@ -499,5 +504,10 @@ void __init time_init(void)
499 if (system_timer->offset == NULL) 504 if (system_timer->offset == NULL)
500 system_timer->offset = dummy_gettimeoffset; 505 system_timer->offset = dummy_gettimeoffset;
501 system_timer->init(); 506 system_timer->init();
507
508#ifdef CONFIG_NO_IDLE_HZ
509 if (system_timer->dyn_tick)
510 system_timer->dyn_tick->lock = SPIN_LOCK_UNLOCKED;
511#endif
502} 512}
503 513
diff --git a/arch/arm/mach-lh7a40x/Kconfig b/arch/arm/mach-lh7a40x/Kconfig
index 8a17867a6a24..558a34f53b1c 100644
--- a/arch/arm/mach-lh7a40x/Kconfig
+++ b/arch/arm/mach-lh7a40x/Kconfig
@@ -14,6 +14,7 @@ config MACH_LPD7A400
14 bool "LPD7A400 Card Engine" 14 bool "LPD7A400 Card Engine"
15 select ARCH_LH7A400 15 select ARCH_LH7A400
16# select IDE_POLL 16# select IDE_POLL
17 select HAS_TOUCHSCREEN_ADS7843_LH7
17 help 18 help
18 Say Y here if you are using Logic Product Development's 19 Say Y here if you are using Logic Product Development's
19 LPD7A400 CardEngine. For the time being, the LPD7A400 and 20 LPD7A400 CardEngine. For the time being, the LPD7A400 and
@@ -23,6 +24,7 @@ config MACH_LPD7A404
23 bool "LPD7A404 Card Engine" 24 bool "LPD7A404 Card Engine"
24 select ARCH_LH7A404 25 select ARCH_LH7A404
25# select IDE_POLL 26# select IDE_POLL
27 select HAS_TOUCHSCREEN_ADC_LH7
26 help 28 help
27 Say Y here if you are using Logic Product Development's 29 Say Y here if you are using Logic Product Development's
28 LPD7A404 CardEngine. For the time being, the LPD7A400 and 30 LPD7A404 CardEngine. For the time being, the LPD7A400 and
@@ -34,6 +36,9 @@ config ARCH_LH7A400
34config ARCH_LH7A404 36config ARCH_LH7A404
35 bool 37 bool
36 38
39config LPD7A40X_CPLD_SSP
40 bool
41
37config LH7A40X_CONTIGMEM 42config LH7A40X_CONTIGMEM
38 bool "Disable NUMA Support" 43 bool "Disable NUMA Support"
39 depends on ARCH_LH7A40X 44 depends on ARCH_LH7A40X
diff --git a/arch/arm/mach-lh7a40x/Makefile b/arch/arm/mach-lh7a40x/Makefile
index e90512dbc2d6..94b8615fb3c3 100644
--- a/arch/arm/mach-lh7a40x/Makefile
+++ b/arch/arm/mach-lh7a40x/Makefile
@@ -4,11 +4,14 @@
4 4
5# Object file lists. 5# Object file lists.
6 6
7obj-y := time.o 7obj-y := time.o clocks.o
8obj-$(CONFIG_MACH_KEV7A400) += arch-kev7a400.o irq-lh7a400.o 8obj-m :=
9obj-$(CONFIG_MACH_LPD7A400) += arch-lpd7a40x.o irq-lh7a400.o 9obj-n :=
10obj-$(CONFIG_MACH_LPD7A404) += arch-lpd7a40x.o irq-lh7a404.o 10obj- :=
11 11
12obj-m := 12obj-$(CONFIG_MACH_KEV7A400) += arch-kev7a400.o irq-lh7a400.o
13obj-n := 13obj-$(CONFIG_MACH_LPD7A400) += arch-lpd7a40x.o irq-lh7a400.o
14obj- := 14obj-$(CONFIG_MACH_LPD7A404) += arch-lpd7a40x.o irq-lh7a404.o
15obj-$(CONFIG_LPD7A40X_CPLD_SSP) += ssp-cpld.o
16obj-$(CONFIG_FB_ARMCLCD) += clcd.o
17
diff --git a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
index 12e23277c5ea..c0e6854289f1 100644
--- a/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
+++ b/arch/arm/mach-lh7a40x/arch-lpd7a40x.c
@@ -23,6 +23,28 @@
23 23
24#include "common.h" 24#include "common.h"
25 25
26#define CPLD_INT_NETHERNET (1<<0)
27#define CPLD_INTMASK_ETHERNET (1<<2)
28#if defined (CONFIG_MACH_LPD7A400)
29# define CPLD_INT_NTOUCH (1<<1)
30# define CPLD_INTMASK_TOUCH (1<<3)
31# define CPLD_INT_PEN (1<<4)
32# define CPLD_INTMASK_PEN (1<<4)
33# define CPLD_INT_PIRQ (1<<4)
34#endif
35#define CPLD_INTMASK_CPLD (1<<7)
36#define CPLD_INT_CPLD (1<<6)
37
38#define CPLD_CONTROL_SWINT (1<<7) /* Disable all CPLD IRQs */
39#define CPLD_CONTROL_OCMSK (1<<6) /* Mask USB1 connect IRQ */
40#define CPLD_CONTROL_PDRV (1<<5) /* PCC_nDRV high */
41#define CPLD_CONTROL_USB1C (1<<4) /* USB1 connect IRQ active */
42#define CPLD_CONTROL_USB1P (1<<3) /* USB1 power disable */
43#define CPLD_CONTROL_AWKP (1<<2) /* Auto-wakeup disabled */
44#define CPLD_CONTROL_LCD_ENABLE (1<<1) /* LCD Vee enable */
45#define CPLD_CONTROL_WRLAN_NENABLE (1<<0) /* SMC91x power disable */
46
47
26static struct resource smc91x_resources[] = { 48static struct resource smc91x_resources[] = {
27 [0] = { 49 [0] = {
28 .start = CPLD00_PHYS, 50 .start = CPLD00_PHYS,
@@ -48,12 +70,12 @@ static struct platform_device smc91x_device = {
48static struct resource lh7a40x_usbclient_resources[] = { 70static struct resource lh7a40x_usbclient_resources[] = {
49 [0] = { 71 [0] = {
50 .start = USB_PHYS, 72 .start = USB_PHYS,
51 .end = (USB_PHYS + 0xFF), 73 .end = (USB_PHYS + PAGE_SIZE),
52 .flags = IORESOURCE_MEM, 74 .flags = IORESOURCE_MEM,
53 }, 75 },
54 [1] = { 76 [1] = {
55 .start = IRQ_USBINTR, 77 .start = IRQ_USB,
56 .end = IRQ_USBINTR, 78 .end = IRQ_USB,
57 .flags = IORESOURCE_IRQ, 79 .flags = IORESOURCE_IRQ,
58 }, 80 },
59}; 81};
@@ -61,7 +83,8 @@ static struct resource lh7a40x_usbclient_resources[] = {
61static u64 lh7a40x_usbclient_dma_mask = 0xffffffffUL; 83static u64 lh7a40x_usbclient_dma_mask = 0xffffffffUL;
62 84
63static struct platform_device lh7a40x_usbclient_device = { 85static struct platform_device lh7a40x_usbclient_device = {
64 .name = "lh7a40x_udc", 86// .name = "lh7a40x_udc",
87 .name = "lh7-udc",
65 .id = 0, 88 .id = 0,
66 .dev = { 89 .dev = {
67 .dma_mask = &lh7a40x_usbclient_dma_mask, 90 .dma_mask = &lh7a40x_usbclient_dma_mask,
@@ -101,7 +124,7 @@ static struct platform_device lh7a404_usbhost_device = {
101 124
102#endif 125#endif
103 126
104static struct platform_device *lpd7a40x_devs[] __initdata = { 127static struct platform_device* lpd7a40x_devs[] __initdata = {
105 &smc91x_device, 128 &smc91x_device,
106 &lh7a40x_usbclient_device, 129 &lh7a40x_usbclient_device,
107#if defined (CONFIG_ARCH_LH7A404) 130#if defined (CONFIG_ARCH_LH7A404)
@@ -113,29 +136,52 @@ extern void lpd7a400_map_io (void);
113 136
114static void __init lpd7a40x_init (void) 137static void __init lpd7a40x_init (void)
115{ 138{
116 CPLD_CONTROL |= (1<<6); /* Mask USB1 connection IRQ */ 139#if defined (CONFIG_MACH_LPD7A400)
140 CPLD_CONTROL |= 0
141 | CPLD_CONTROL_SWINT /* Disable software interrupt */
142 | CPLD_CONTROL_OCMSK; /* Mask USB1 connection IRQ */
117 CPLD_CONTROL &= ~(0 143 CPLD_CONTROL &= ~(0
118 | (1<<1) /* Disable LCD */ 144 | CPLD_CONTROL_LCD_ENABLE /* Disable LCD */
119 | (1<<0) /* Enable WLAN */ 145 | CPLD_CONTROL_WRLAN_NENABLE /* Enable SMC91x */
120 ); 146 );
147#endif
148
149#if defined (CONFIG_MACH_LPD7A404)
150 CPLD_CONTROL &= ~(0
151 | CPLD_CONTROL_WRLAN_NENABLE /* Enable SMC91x */
152 );
153#endif
121 154
122 platform_add_devices (lpd7a40x_devs, ARRAY_SIZE (lpd7a40x_devs)); 155 platform_add_devices (lpd7a40x_devs, ARRAY_SIZE (lpd7a40x_devs));
156#if defined (CONFIG_FB_ARMCLCD)
157 lh7a40x_clcd_init ();
158#endif
123} 159}
124 160
125static void lh7a40x_ack_cpld_irq (u32 irq) 161static void lh7a40x_ack_cpld_irq (u32 irq)
126{ 162{
127 /* CPLD doesn't have ack capability */ 163 /* CPLD doesn't have ack capability, but some devices may */
164
165#if defined (CPLD_INTMASK_TOUCH)
166 /* The touch control *must* mask the the interrupt because the
167 * interrupt bit is read by the driver to determine if the pen
168 * is still down. */
169 if (irq == IRQ_TOUCH)
170 CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH;
171#endif
128} 172}
129 173
130static void lh7a40x_mask_cpld_irq (u32 irq) 174static void lh7a40x_mask_cpld_irq (u32 irq)
131{ 175{
132 switch (irq) { 176 switch (irq) {
133 case IRQ_LPD7A40X_ETH_INT: 177 case IRQ_LPD7A40X_ETH_INT:
134 CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x4; 178 CPLD_INTERRUPTS |= CPLD_INTMASK_ETHERNET;
135 break; 179 break;
136 case IRQ_LPD7A400_TS: 180#if defined (IRQ_TOUCH)
137 CPLD_INTERRUPTS = CPLD_INTERRUPTS | 0x8; 181 case IRQ_TOUCH:
182 CPLD_INTERRUPTS |= CPLD_INTMASK_TOUCH;
138 break; 183 break;
184#endif
139 } 185 }
140} 186}
141 187
@@ -143,11 +189,13 @@ static void lh7a40x_unmask_cpld_irq (u32 irq)
143{ 189{
144 switch (irq) { 190 switch (irq) {
145 case IRQ_LPD7A40X_ETH_INT: 191 case IRQ_LPD7A40X_ETH_INT:
146 CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x4; 192 CPLD_INTERRUPTS &= ~CPLD_INTMASK_ETHERNET;
147 break; 193 break;
148 case IRQ_LPD7A400_TS: 194#if defined (IRQ_TOUCH)
149 CPLD_INTERRUPTS = CPLD_INTERRUPTS & ~ 0x8; 195 case IRQ_TOUCH:
196 CPLD_INTERRUPTS &= ~CPLD_INTMASK_TOUCH;
150 break; 197 break;
198#endif
151 } 199 }
152} 200}
153 201
@@ -164,11 +212,13 @@ static void lpd7a40x_cpld_handler (unsigned int irq, struct irqdesc *desc,
164 212
165 desc->chip->ack (irq); 213 desc->chip->ack (irq);
166 214
167 if ((mask & 0x1) == 0) /* WLAN */ 215 if ((mask & (1<<0)) == 0) /* WLAN */
168 IRQ_DISPATCH (IRQ_LPD7A40X_ETH_INT); 216 IRQ_DISPATCH (IRQ_LPD7A40X_ETH_INT);
169 217
170 if ((mask & 0x2) == 0) /* Touch */ 218#if defined (IRQ_TOUCH)
171 IRQ_DISPATCH (IRQ_LPD7A400_TS); 219 if ((mask & (1<<1)) == 0) /* Touch */
220 IRQ_DISPATCH (IRQ_TOUCH);
221#endif
172 222
173 desc->chip->unmask (irq); /* Level-triggered need this */ 223 desc->chip->unmask (irq); /* Level-triggered need this */
174} 224}
@@ -204,9 +254,21 @@ void __init lh7a40x_init_board_irq (void)
204 254
205 /* Then, configure CPLD interrupt */ 255 /* Then, configure CPLD interrupt */
206 256
207 CPLD_INTERRUPTS = 0x9c; /* Disable all CPLD interrupts */ 257 /* Disable all CPLD interrupts */
258#if defined (CONFIG_MACH_LPD7A400)
259 CPLD_INTERRUPTS = CPLD_INTMASK_TOUCH | CPLD_INTMASK_PEN
260 | CPLD_INTMASK_ETHERNET;
261 /* *** FIXME: don't know why we need 7 and 4. 7 is way wrong
262 and 4 is uncefined. */
263 // (1<<7)|(1<<4)|(1<<3)|(1<<2);
264#endif
265#if defined (CONFIG_MACH_LPD7A404)
266 CPLD_INTERRUPTS = CPLD_INTMASK_ETHERNET;
267 /* *** FIXME: don't know why we need 6 and 5, neither is defined. */
268 // (1<<6)|(1<<5)|(1<<3);
269#endif
208 GPIO_PFDD &= ~(1 << pinCPLD); /* Make input */ 270 GPIO_PFDD &= ~(1 << pinCPLD); /* Make input */
209 GPIO_INTTYPE1 |= (1 << pinCPLD); /* Edge triggered */ 271 GPIO_INTTYPE1 &= ~(1 << pinCPLD); /* Level triggered */
210 GPIO_INTTYPE2 &= ~(1 << pinCPLD); /* Active low */ 272 GPIO_INTTYPE2 &= ~(1 << pinCPLD); /* Active low */
211 barrier (); 273 barrier ();
212 GPIO_GPIOFINTEN |= (1 << pinCPLD); /* Enable */ 274 GPIO_GPIOFINTEN |= (1 << pinCPLD); /* Enable */
@@ -216,7 +278,7 @@ void __init lh7a40x_init_board_irq (void)
216 for (irq = IRQ_BOARD_START; 278 for (irq = IRQ_BOARD_START;
217 irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) { 279 irq < IRQ_BOARD_START + NR_IRQ_BOARD; ++irq) {
218 set_irq_chip (irq, &lpd7a40x_cpld_chip); 280 set_irq_chip (irq, &lpd7a40x_cpld_chip);
219 set_irq_handler (irq, do_edge_IRQ); 281 set_irq_handler (irq, do_level_IRQ);
220 set_irq_flags (irq, IRQF_VALID); 282 set_irq_flags (irq, IRQF_VALID);
221 } 283 }
222 284
@@ -226,91 +288,109 @@ void __init lh7a40x_init_board_irq (void)
226 lpd7a40x_cpld_handler); 288 lpd7a40x_cpld_handler);
227} 289}
228 290
229static struct map_desc lpd7a400_io_desc[] __initdata = { 291static struct map_desc lpd7a40x_io_desc[] __initdata = {
230 { 292 {
231 .virtual = IO_VIRT, 293 .virtual = IO_VIRT,
232 .pfn = __phys_to_pfn(IO_PHYS), 294 .pfn = __phys_to_pfn(IO_PHYS),
233 .length = IO_SIZE, 295 .length = IO_SIZE,
234 .type = MT_DEVICE 296 .type = MT_DEVICE
235 }, { /* Mapping added to work around chip select problems */ 297 },
298 { /* Mapping added to work around chip select problems */
236 .virtual = IOBARRIER_VIRT, 299 .virtual = IOBARRIER_VIRT,
237 .pfn = __phys_to_pfn(IOBARRIER_PHYS), 300 .pfn = __phys_to_pfn(IOBARRIER_PHYS),
238 .length = IOBARRIER_SIZE, 301 .length = IOBARRIER_SIZE,
239 .type = MT_DEVICE 302 .type = MT_DEVICE
240 }, { 303 },
304 {
241 .virtual = CF_VIRT, 305 .virtual = CF_VIRT,
242 .pfn = __phys_to_pfn(CF_PHYS), 306 .pfn = __phys_to_pfn(CF_PHYS),
243 .length = CF_SIZE, 307 .length = CF_SIZE,
244 .type = MT_DEVICE 308 .type = MT_DEVICE
245 }, { 309 },
310 {
246 .virtual = CPLD02_VIRT, 311 .virtual = CPLD02_VIRT,
247 .pfn = __phys_to_pfn(CPLD02_PHYS), 312 .pfn = __phys_to_pfn(CPLD02_PHYS),
248 .length = CPLD02_SIZE, 313 .length = CPLD02_SIZE,
249 .type = MT_DEVICE 314 .type = MT_DEVICE
250 }, { 315 },
316 {
251 .virtual = CPLD06_VIRT, 317 .virtual = CPLD06_VIRT,
252 .pfn = __phys_to_pfn(CPLD06_PHYS), 318 .pfn = __phys_to_pfn(CPLD06_PHYS),
253 .length = CPLD06_SIZE, 319 .length = CPLD06_SIZE,
320 .type = MT_DEVICE
321 },
322 {
323 .virtual = CPLD08_VIRT,
324 .pfn = __phys_to_pfn(CPLD08_PHYS),
325 .length = CPLD08_SIZE,
254 .type = MT_DEVICE 326 .type = MT_DEVICE
255 }, { 327 },
328 {
256 .virtual = CPLD08_VIRT, 329 .virtual = CPLD08_VIRT,
257 .pfn = __phys_to_pfn(CPLD08_PHYS), 330 .pfn = __phys_to_pfn(CPLD08_PHYS),
258 .length = CPLD08_SIZE, 331 .length = CPLD08_SIZE,
259 .type = MT_DEVICE 332 .type = MT_DEVICE
260 }, { 333 },
334 {
335 .virtual = CPLD0A_VIRT,
336 .pfn = __phys_to_pfn(CPLD0A_PHYS),
337 .length = CPLD0A_SIZE,
338 .type = MT_DEVICE
339 },
340 {
261 .virtual = CPLD0C_VIRT, 341 .virtual = CPLD0C_VIRT,
262 .pfn = __phys_to_pfn(CPLD0C_PHYS), 342 .pfn = __phys_to_pfn(CPLD0C_PHYS),
263 .length = CPLD0C_SIZE, 343 .length = CPLD0C_SIZE,
264 .type = MT_DEVICE 344 .type = MT_DEVICE
265 }, { 345 },
346 {
266 .virtual = CPLD0E_VIRT, 347 .virtual = CPLD0E_VIRT,
267 .pfn = __phys_to_pfn(CPLD0E_PHYS), 348 .pfn = __phys_to_pfn(CPLD0E_PHYS),
268 .length = CPLD0E_SIZE, 349 .length = CPLD0E_SIZE,
269 .type = MT_DEVICE 350 .type = MT_DEVICE
270 }, { 351 },
352 {
271 .virtual = CPLD10_VIRT, 353 .virtual = CPLD10_VIRT,
272 .pfn = __phys_to_pfn(CPLD10_PHYS), 354 .pfn = __phys_to_pfn(CPLD10_PHYS),
273 .length = CPLD10_SIZE, 355 .length = CPLD10_SIZE,
274 .type = MT_DEVICE 356 .type = MT_DEVICE
275 }, { 357 },
358 {
276 .virtual = CPLD12_VIRT, 359 .virtual = CPLD12_VIRT,
277 .pfn = __phys_to_pfn(CPLD12_PHYS), 360 .pfn = __phys_to_pfn(CPLD12_PHYS),
278 .length = CPLD12_SIZE, 361 .length = CPLD12_SIZE,
279 .type = MT_DEVICE 362 .type = MT_DEVICE
280 }, { 363 },
364 {
281 .virtual = CPLD14_VIRT, 365 .virtual = CPLD14_VIRT,
282 .pfn = __phys_to_pfn(CPLD14_PHYS), 366 .pfn = __phys_to_pfn(CPLD14_PHYS),
283 .length = CPLD14_SIZE, 367 .length = CPLD14_SIZE,
284 .type = MT_DEVICE 368 .type = MT_DEVICE
285 }, { 369 },
370 {
286 .virtual = CPLD16_VIRT, 371 .virtual = CPLD16_VIRT,
287 .pfn = __phys_to_pfn(CPLD16_PHYS), 372 .pfn = __phys_to_pfn(CPLD16_PHYS),
288 .length = CPLD16_SIZE, 373 .length = CPLD16_SIZE,
289 .type = MT_DEVICE 374 .type = MT_DEVICE
290 }, { 375 },
376 {
291 .virtual = CPLD18_VIRT, 377 .virtual = CPLD18_VIRT,
292 .pfn = __phys_to_pfn(CPLD18_PHYS), 378 .pfn = __phys_to_pfn(CPLD18_PHYS),
293 .length = CPLD18_SIZE, 379 .length = CPLD18_SIZE,
294 .type = MT_DEVICE 380 .type = MT_DEVICE
295 }, { 381 },
382 {
296 .virtual = CPLD1A_VIRT, 383 .virtual = CPLD1A_VIRT,
297 .pfn = __phys_to_pfn(CPLD1A_PHYS), 384 .pfn = __phys_to_pfn(CPLD1A_PHYS),
298 .length = CPLD1A_SIZE, 385 .length = CPLD1A_SIZE,
299 .type = MT_DEVICE 386 .type = MT_DEVICE
300 }, 387 },
301 /* This mapping is redundant since the smc driver performs another. */
302/* { CPLD00_VIRT, CPLD00_PHYS, CPLD00_SIZE, MT_DEVICE }, */
303}; 388};
304 389
305void __init 390void __init
306lpd7a400_map_io(void) 391lpd7a40x_map_io(void)
307{ 392{
308 iotable_init (lpd7a400_io_desc, ARRAY_SIZE (lpd7a400_io_desc)); 393 iotable_init (lpd7a40x_io_desc, ARRAY_SIZE (lpd7a40x_io_desc));
309
310 /* Fixup (improve) Static Memory Controller settings */
311 SMC_BCR0 = 0x200039af; /* Boot Flash */
312 SMC_BCR6 = 0x1000fbe0; /* CPLD */
313 SMC_BCR7 = 0x1000b2c2; /* Compact Flash */
314} 394}
315 395
316#ifdef CONFIG_MACH_LPD7A400 396#ifdef CONFIG_MACH_LPD7A400
@@ -320,7 +400,7 @@ MACHINE_START (LPD7A400, "Logic Product Development LPD7A400-10")
320 .phys_io = 0x80000000, 400 .phys_io = 0x80000000,
321 .io_pg_offst = ((io_p2v (0x80000000))>>18) & 0xfffc, 401 .io_pg_offst = ((io_p2v (0x80000000))>>18) & 0xfffc,
322 .boot_params = 0xc0000100, 402 .boot_params = 0xc0000100,
323 .map_io = lpd7a400_map_io, 403 .map_io = lpd7a40x_map_io,
324 .init_irq = lh7a400_init_irq, 404 .init_irq = lh7a400_init_irq,
325 .timer = &lh7a40x_timer, 405 .timer = &lh7a40x_timer,
326 .init_machine = lpd7a40x_init, 406 .init_machine = lpd7a40x_init,
@@ -335,7 +415,7 @@ MACHINE_START (LPD7A404, "Logic Product Development LPD7A404-10")
335 .phys_io = 0x80000000, 415 .phys_io = 0x80000000,
336 .io_pg_offst = ((io_p2v (0x80000000))>>18) & 0xfffc, 416 .io_pg_offst = ((io_p2v (0x80000000))>>18) & 0xfffc,
337 .boot_params = 0xc0000100, 417 .boot_params = 0xc0000100,
338 .map_io = lpd7a400_map_io, 418 .map_io = lpd7a40x_map_io,
339 .init_irq = lh7a404_init_irq, 419 .init_irq = lh7a404_init_irq,
340 .timer = &lh7a40x_timer, 420 .timer = &lh7a40x_timer,
341 .init_machine = lpd7a40x_init, 421 .init_machine = lpd7a40x_init,
diff --git a/arch/arm/mach-lh7a40x/clcd.c b/arch/arm/mach-lh7a40x/clcd.c
new file mode 100644
index 000000000000..93751fee793d
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/clcd.c
@@ -0,0 +1,241 @@
1/*
2 * arch/arm/mach-lh7a40x/clcd.c
3 *
4 * Copyright (C) 2004 Marc Singer
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
9 *
10 */
11#include <linux/config.h>
12#include <linux/init.h>
13#include <linux/device.h>
14#include <linux/dma-mapping.h>
15#include <linux/sysdev.h>
16#include <linux/interrupt.h>
17
18//#include <linux/module.h>
19//#include <linux/time.h>
20//#include <asm/hardware.h>
21
22//#include <asm/mach/time.h>
23#include <asm/irq.h>
24#include <asm/mach/irq.h>
25
26#include <asm/system.h>
27#include <asm/hardware.h>
28#include <linux/amba/bus.h>
29#include <linux/amba/clcd.h>
30
31#define HRTFTC_HRSETUP __REG(HRTFTC_PHYS + 0x00)
32#define HRTFTC_HRCON __REG(HRTFTC_PHYS + 0x04)
33#define HRTFTC_HRTIMING1 __REG(HRTFTC_PHYS + 0x08)
34#define HRTFTC_HRTIMING2 __REG(HRTFTC_PHYS + 0x0c)
35
36#define ALI_SETUP __REG(ALI_PHYS + 0x00)
37#define ALI_CONTROL __REG(ALI_PHYS + 0x04)
38#define ALI_TIMING1 __REG(ALI_PHYS + 0x08)
39#define ALI_TIMING2 __REG(ALI_PHYS + 0x0c)
40
41#include "lcd-panel.h"
42
43static void lh7a40x_clcd_disable (struct clcd_fb *fb)
44{
45#if defined (CONFIG_MACH_LPD7A400)
46 CPLD_CONTROL &= ~(1<<1); /* Disable LCD Vee */
47#endif
48
49#if defined (CONFIG_MACH_LPD7A404)
50 GPIO_PCD &= ~(1<<3); /* Disable LCD Vee */
51#endif
52
53#if defined (CONFIG_ARCH_LH7A400)
54 HRTFTC_HRSETUP &= ~(1<<13); /* Disable HRTFT controller */
55#endif
56
57#if defined (CONFIG_ARCH_LH7A404)
58 ALI_SETUP &= ~(1<<13); /* Disable ALI */
59#endif
60}
61
62static void lh7a40x_clcd_enable (struct clcd_fb *fb)
63{
64 struct clcd_panel_extra* extra
65 = (struct clcd_panel_extra*) fb->board_data;
66
67#if defined (CONFIG_MACH_LPD7A400)
68 CPLD_CONTROL |= (1<<1); /* Enable LCD Vee */
69#endif
70
71#if defined (CONFIG_MACH_LPD7A404)
72 GPIO_PCDD &= ~(1<<3); /* Enable LCD Vee */
73 GPIO_PCD |= (1<<3);
74#endif
75
76#if defined (CONFIG_ARCH_LH7A400)
77
78 if (extra) {
79 HRTFTC_HRSETUP
80 = (1 << 13)
81 | ((fb->fb.var.xres - 1) << 4)
82 | 0xc
83 | (extra->hrmode ? 1 : 0);
84 HRTFTC_HRCON
85 = ((extra->clsen ? 1 : 0) << 1)
86 | ((extra->spsen ? 1 : 0) << 0);
87 HRTFTC_HRTIMING1
88 = (extra->pcdel << 8)
89 | (extra->revdel << 4)
90 | (extra->lpdel << 0);
91 HRTFTC_HRTIMING2
92 = (extra->spldel << 9)
93 | (extra->pc2del << 0);
94 }
95 else
96 HRTFTC_HRSETUP
97 = (1 << 13)
98 | 0xc;
99#endif
100
101#if defined (CONFIG_ARCH_LH7A404)
102
103 if (extra) {
104 ALI_SETUP
105 = (1 << 13)
106 | ((fb->fb.var.xres - 1) << 4)
107 | 0xc
108 | (extra->hrmode ? 1 : 0);
109 ALI_CONTROL
110 = ((extra->clsen ? 1 : 0) << 1)
111 | ((extra->spsen ? 1 : 0) << 0);
112 ALI_TIMING1
113 = (extra->pcdel << 8)
114 | (extra->revdel << 4)
115 | (extra->lpdel << 0);
116 ALI_TIMING2
117 = (extra->spldel << 9)
118 | (extra->pc2del << 0);
119 }
120 else
121 ALI_SETUP
122 = (1 << 13)
123 | 0xc;
124#endif
125
126}
127
128#define FRAMESIZE(s) (((s) + PAGE_SIZE - 1)&PAGE_MASK)
129
130static int lh7a40x_clcd_setup (struct clcd_fb *fb)
131{
132 dma_addr_t dma;
133 u32 len = FRAMESIZE (lcd_panel.mode.xres*lcd_panel.mode.yres
134 *(lcd_panel.bpp/8));
135
136 fb->panel = &lcd_panel;
137
138 /* Enforce the sync polarity defaults */
139 if (!(fb->panel->tim2 & TIM2_IHS))
140 fb->fb.var.sync |= FB_SYNC_HOR_HIGH_ACT;
141 if (!(fb->panel->tim2 & TIM2_IVS))
142 fb->fb.var.sync |= FB_SYNC_VERT_HIGH_ACT;
143
144#if defined (HAS_LCD_PANEL_EXTRA)
145 fb->board_data = &lcd_panel_extra;
146#endif
147
148 fb->fb.screen_base
149 = dma_alloc_writecombine (&fb->dev->dev, len,
150 &dma, GFP_KERNEL);
151 printk ("CLCD: LCD setup fb virt 0x%p phys 0x%p l %x io 0x%p \n",
152 fb->fb.screen_base, (void*) dma, len,
153 (void*) io_p2v (CLCDC_PHYS));
154 printk ("CLCD: pixclock %d\n", lcd_panel.mode.pixclock);
155
156 if (!fb->fb.screen_base) {
157 printk(KERN_ERR "CLCD: unable to map framebuffer\n");
158 return -ENOMEM;
159 }
160
161#if defined (USE_RGB555)
162 fb->fb.var.green.length = 5; /* Panel uses RGB 5:5:5 */
163#endif
164
165 fb->fb.fix.smem_start = dma;
166 fb->fb.fix.smem_len = len;
167
168 /* Drive PE4 high to prevent CPLD crash */
169 GPIO_PEDD |= (1<<4);
170 GPIO_PED |= (1<<4);
171
172 GPIO_PINMUX |= (1<<1) | (1<<0); /* LCDVD[15:4] */
173
174// fb->fb.fbops->fb_check_var (&fb->fb.var, &fb->fb);
175// fb->fb.fbops->fb_set_par (&fb->fb);
176
177 return 0;
178}
179
180static int lh7a40x_clcd_mmap (struct clcd_fb *fb, struct vm_area_struct *vma)
181{
182 return dma_mmap_writecombine(&fb->dev->dev, vma,
183 fb->fb.screen_base,
184 fb->fb.fix.smem_start,
185 fb->fb.fix.smem_len);
186}
187
188static void lh7a40x_clcd_remove (struct clcd_fb *fb)
189{
190 dma_free_writecombine (&fb->dev->dev, fb->fb.fix.smem_len,
191 fb->fb.screen_base, fb->fb.fix.smem_start);
192}
193
194static struct clcd_board clcd_platform_data = {
195 .name = "lh7a40x FB",
196 .check = clcdfb_check,
197 .decode = clcdfb_decode,
198 .enable = lh7a40x_clcd_enable,
199 .setup = lh7a40x_clcd_setup,
200 .mmap = lh7a40x_clcd_mmap,
201 .remove = lh7a40x_clcd_remove,
202 .disable = lh7a40x_clcd_disable,
203};
204
205#define IRQ_CLCDC (IRQ_LCDINTR)
206
207#define AMBA_DEVICE(name,busid,base,plat,pid) \
208static struct amba_device name##_device = { \
209 .dev = { \
210 .coherent_dma_mask = ~0, \
211 .bus_id = busid, \
212 .platform_data = plat, \
213 }, \
214 .res = { \
215 .start = base##_PHYS, \
216 .end = (base##_PHYS) + (4*1024) - 1, \
217 .flags = IORESOURCE_MEM, \
218 }, \
219 .dma_mask = ~0, \
220 .irq = { IRQ_##base, }, \
221 /* .dma = base##_DMA,*/ \
222 .periphid = pid, \
223}
224
225AMBA_DEVICE(clcd, "cldc-lh7a40x", CLCDC, &clcd_platform_data, 0x41110);
226
227static struct amba_device *amba_devs[] __initdata = {
228 &clcd_device,
229};
230
231void __init lh7a40x_clcd_init (void)
232{
233 int i;
234 int result;
235 printk ("CLCD: registering amba devices\n");
236 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
237 struct amba_device *d = amba_devs[i];
238 result = amba_device_register(d, &iomem_resource);
239 printk (" %d -> %d\n", i ,result);
240 }
241}
diff --git a/arch/arm/mach-lh7a40x/clocks.c b/arch/arm/mach-lh7a40x/clocks.c
new file mode 100644
index 000000000000..2291afe9f23e
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/clocks.c
@@ -0,0 +1,199 @@
1/* arch/arm/mach-lh7a40x/clocks.c
2 *
3 * Copyright (C) 2004 Marc Singer
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <linux/config.h>
12#include <linux/cpufreq.h>
13#include <asm/hardware.h>
14#include <asm/arch/clocks.h>
15#include <linux/err.h>
16
17struct module;
18struct icst525_params;
19
20struct clk {
21 struct list_head node;
22 unsigned long rate;
23 struct module *owner;
24 const char *name;
25// void *data;
26// const struct icst525_params *params;
27// void (*setvco)(struct clk *, struct icst525_vco vco);
28};
29
30int clk_register(struct clk *clk);
31void clk_unregister(struct clk *clk);
32
33/* ----- */
34
35#define MAINDIV1(c) (((c) >> 7) & 0x0f)
36#define MAINDIV2(c) (((c) >> 11) & 0x1f)
37#define PS(c) (((c) >> 18) & 0x03)
38#define PREDIV(c) (((c) >> 2) & 0x1f)
39#define HCLKDIV(c) (((c) >> 0) & 0x02)
40#define PCLKDIV(c) (((c) >> 16) & 0x03)
41
42unsigned int cpufreq_get (unsigned int cpu) /* in kHz */
43{
44 return fclkfreq_get ()/1000;
45}
46EXPORT_SYMBOL(cpufreq_get);
47
48unsigned int fclkfreq_get (void)
49{
50 unsigned int clkset = CSC_CLKSET;
51 unsigned int gclk
52 = XTAL_IN
53 / (1 << PS(clkset))
54 * (MAINDIV1(clkset) + 2)
55 / (PREDIV(clkset) + 2)
56 * (MAINDIV2(clkset) + 2)
57 ;
58 return gclk;
59}
60
61unsigned int hclkfreq_get (void)
62{
63 unsigned int clkset = CSC_CLKSET;
64 unsigned int hclk = fclkfreq_get () / (HCLKDIV(clkset) + 1);
65
66 return hclk;
67}
68
69unsigned int pclkfreq_get (void)
70{
71 unsigned int clkset = CSC_CLKSET;
72 int pclkdiv = PCLKDIV(clkset);
73 unsigned int pclk;
74 if (pclkdiv == 0x3)
75 pclkdiv = 0x2;
76 pclk = hclkfreq_get () / (1 << pclkdiv);
77
78 return pclk;
79}
80
81/* ----- */
82
83static LIST_HEAD(clocks);
84static DECLARE_MUTEX(clocks_sem);
85
86struct clk *clk_get (struct device *dev, const char *id)
87{
88 struct clk *p;
89 struct clk *clk = ERR_PTR(-ENOENT);
90
91 down (&clocks_sem);
92 list_for_each_entry (p, &clocks, node) {
93 if (strcmp (id, p->name) == 0
94 && try_module_get(p->owner)) {
95 clk = p;
96 break;
97 }
98 }
99 up (&clocks_sem);
100
101 return clk;
102}
103EXPORT_SYMBOL(clk_get);
104
105void clk_put (struct clk *clk)
106{
107 module_put(clk->owner);
108}
109EXPORT_SYMBOL(clk_put);
110
111int clk_enable (struct clk *clk)
112{
113 return 0;
114}
115EXPORT_SYMBOL(clk_enable);
116
117void clk_disable (struct clk *clk)
118{
119}
120EXPORT_SYMBOL(clk_disable);
121
122int clk_use (struct clk *clk)
123{
124 return 0;
125}
126EXPORT_SYMBOL(clk_use);
127
128void clk_unuse (struct clk *clk)
129{
130}
131EXPORT_SYMBOL(clk_unuse);
132
133unsigned long clk_get_rate (struct clk *clk)
134{
135 return clk->rate;
136}
137EXPORT_SYMBOL(clk_get_rate);
138
139long clk_round_rate (struct clk *clk, unsigned long rate)
140{
141 return rate;
142}
143EXPORT_SYMBOL(clk_round_rate);
144
145int clk_set_rate (struct clk *clk, unsigned long rate)
146{
147 int ret = -EIO;
148 return ret;
149}
150EXPORT_SYMBOL(clk_set_rate);
151
152#if 0
153/*
154 * These are fixed clocks.
155 */
156static struct clk kmi_clk = {
157 .name = "KMIREFCLK",
158 .rate = 24000000,
159};
160
161static struct clk uart_clk = {
162 .name = "UARTCLK",
163 .rate = 24000000,
164};
165
166static struct clk mmci_clk = {
167 .name = "MCLK",
168 .rate = 33000000,
169};
170#endif
171
172static struct clk clcd_clk = {
173 .name = "CLCDCLK",
174 .rate = 0,
175};
176
177int clk_register (struct clk *clk)
178{
179 down (&clocks_sem);
180 list_add (&clk->node, &clocks);
181 up (&clocks_sem);
182 return 0;
183}
184EXPORT_SYMBOL(clk_register);
185
186void clk_unregister (struct clk *clk)
187{
188 down (&clocks_sem);
189 list_del (&clk->node);
190 up (&clocks_sem);
191}
192EXPORT_SYMBOL(clk_unregister);
193
194static int __init clk_init (void)
195{
196 clk_register(&clcd_clk);
197 return 0;
198}
199arch_initcall(clk_init);
diff --git a/arch/arm/mach-lh7a40x/common.h b/arch/arm/mach-lh7a40x/common.h
index ea8de7e3ab1b..18e8bb4eb202 100644
--- a/arch/arm/mach-lh7a40x/common.h
+++ b/arch/arm/mach-lh7a40x/common.h
@@ -12,6 +12,7 @@ extern struct sys_timer lh7a40x_timer;
12 12
13extern void lh7a400_init_irq (void); 13extern void lh7a400_init_irq (void);
14extern void lh7a404_init_irq (void); 14extern void lh7a404_init_irq (void);
15extern void lh7a40x_clcd_init (void);
15extern void lh7a40x_init_board_irq (void); 16extern void lh7a40x_init_board_irq (void);
16 17
17#define IRQ_DISPATCH(irq) desc_handle_irq((irq),(irq_desc + irq), regs) 18#define IRQ_DISPATCH(irq) desc_handle_irq((irq),(irq_desc + irq), regs)
diff --git a/arch/arm/mach-lh7a40x/irq-lh7a404.c b/arch/arm/mach-lh7a40x/irq-lh7a404.c
index e902e3d87da4..2685a81454d2 100644
--- a/arch/arm/mach-lh7a40x/irq-lh7a404.c
+++ b/arch/arm/mach-lh7a40x/irq-lh7a404.c
@@ -28,13 +28,17 @@
28 28
29static unsigned char irq_pri_vic1[] = { 29static unsigned char irq_pri_vic1[] = {
30#if defined (USE_PRIORITIES) 30#if defined (USE_PRIORITIES)
31IRQ_GPIO3INTR, 31 IRQ_GPIO3INTR, /* CPLD */
32 IRQ_DMAM2P4, IRQ_DMAM2P5, /* AC97 */
32#endif 33#endif
33}; 34};
34static unsigned char irq_pri_vic2[] = { 35static unsigned char irq_pri_vic2[] = {
35#if defined (USE_PRIORITIES) 36#if defined (USE_PRIORITIES)
36 IRQ_T3UI, IRQ_GPIO7INTR, 37 IRQ_T3UI, /* Timer */
38 IRQ_GPIO7INTR, /* CPLD */
37 IRQ_UART1INTR, IRQ_UART2INTR, IRQ_UART3INTR, 39 IRQ_UART1INTR, IRQ_UART2INTR, IRQ_UART3INTR,
40 IRQ_LCDINTR, /* LCD */
41 IRQ_TSCINTR, /* ADC/Touchscreen */
38#endif 42#endif
39}; 43};
40 44
@@ -98,10 +102,19 @@ static struct irqchip lh7a404_gpio_vic2_chip = {
98 102
99 /* IRQ initialization */ 103 /* IRQ initialization */
100 104
105#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
106extern void* branch_irq_lh7a400;
107#endif
108
101void __init lh7a404_init_irq (void) 109void __init lh7a404_init_irq (void)
102{ 110{
103 int irq; 111 int irq;
104 112
113#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
114#define NOP 0xe1a00000 /* mov r0, r0 */
115 branch_irq_lh7a400 = NOP;
116#endif
117
105 VIC1_INTENCLR = 0xffffffff; 118 VIC1_INTENCLR = 0xffffffff;
106 VIC2_INTENCLR = 0xffffffff; 119 VIC2_INTENCLR = 0xffffffff;
107 VIC1_INTSEL = 0; /* All IRQs */ 120 VIC1_INTSEL = 0; /* All IRQs */
diff --git a/arch/arm/mach-lh7a40x/lcd-panel.h b/arch/arm/mach-lh7a40x/lcd-panel.h
new file mode 100644
index 000000000000..4fb2efc4950f
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/lcd-panel.h
@@ -0,0 +1,346 @@
1/* lcd-panel.h
2 $Id$
3
4 written by Marc Singer
5 18 Jul 2005
6
7 Copyright (C) 2005 Marc Singer
8
9 -----------
10 DESCRIPTION
11 -----------
12
13 Only one panel may be defined at a time.
14
15 The pixel clock is calculated to be no greater than the target.
16
17 Each timing value is accompanied by a specification comment.
18
19 UNITS/MIN/TYP/MAX
20
21 Most of the units will be in clocks.
22
23 USE_RGB555
24
25 Define this macro to configure the AMBA LCD controller to use an
26 RGB555 encoding for the pels instead of the normal RGB565.
27
28 LPD9520, LPD79524, LPD7A400, LPD7A404-10, LPD7A404-11
29
30 These boards are best approximated by 555 for all panels. Some
31 can use an extra low-order bit of blue in bit 16 of the color
32 value, but we don't have a way to communicate this non-linear
33 mapping to the kernel.
34
35*/
36
37#if !defined (__LCD_PANEL_H__)
38# define __LCD_PANEL_H__
39
40#if defined (MACH_LPD79520)\
41 || defined (MACH_LPD79524)\
42 || defined (MACH_LPD7A400)\
43 || defined (MACH_LPD7A404)
44# define USE_RGB555
45#endif
46
47struct clcd_panel_extra {
48 unsigned int hrmode;
49 unsigned int clsen;
50 unsigned int spsen;
51 unsigned int pcdel;
52 unsigned int revdel;
53 unsigned int lpdel;
54 unsigned int spldel;
55 unsigned int pc2del;
56};
57
58#define NS_TO_CLOCK(ns,c) ((((ns)*((c)/1000) + (1000000 - 1))/1000000))
59#define CLOCK_TO_DIV(e,c) (((c) + (e) - 1)/(e))
60
61#if defined CONFIG_FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT
62
63 /* Logic Product Development LCD 3.5" QVGA HRTFT -10 */
64 /* Sharp PN LQ035Q7DB02 w/HRTFT controller chip */
65
66#define PIX_CLOCK_TARGET (6800000)
67#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
68#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
69
70static struct clcd_panel lcd_panel = {
71 .mode = {
72 .name = "3.5in QVGA (LQ035Q7DB02)",
73 .xres = 240,
74 .yres = 320,
75 .pixclock = PIX_CLOCK,
76 .left_margin = 16,
77 .right_margin = 21,
78 .upper_margin = 8, // line/8/8/8
79 .lower_margin = 5,
80 .hsync_len = 61,
81 .vsync_len = NS_TO_CLOCK (60, PIX_CLOCK),
82 .vmode = FB_VMODE_NONINTERLACED,
83 },
84 .width = -1,
85 .height = -1,
86 .tim2 = TIM2_IPC | (PIX_CLOCK_DIVIDER - 2),
87 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
88 .bpp = 16,
89};
90
91#define HAS_LCD_PANEL_EXTRA
92
93static struct clcd_panel_extra lcd_panel_extra = {
94 .hrmode = 1,
95 .clsen = 1,
96 .spsen = 1,
97 .pcdel = 8,
98 .revdel = 7,
99 .lpdel = 13,
100 .spldel = 77,
101 .pc2del = 208,
102};
103
104#endif
105
106#if defined CONFIG_FB_ARMCLCD_SHARP_LQ057Q3DC02
107
108 /* Logic Product Development LCD 5.7" QVGA -10 */
109 /* Sharp PN LQ057Q3DC02 */
110 /* QVGA mode, V/Q=LOW */
111
112/* From Sharp on 2006.1.3. I believe some of the values are incorrect
113 * based on the datasheet.
114
115 Timing0 TIMING1 TIMING2 CONTROL
116 0x140A0C4C 0x080504EF 0x013F380D 0x00000829
117 HBP= 20 VBP= 8 BCD= 0
118 HFP= 10 VFP= 5 CPL=319
119 HSW= 12 VSW= 1 IOE= 0
120 PPL= 19 LPP=239 IPC= 1
121 IHS= 1
122 IVS= 1
123 ACB= 0
124 CSEL= 0
125 PCD= 13
126
127 */
128
129/* The full horozontal cycle (Th) is clock/360/400/450. */
130/* The full vertical cycle (Tv) is line/251/262/280. */
131
132#define PIX_CLOCK_TARGET (6300000) /* -/6.3/7 MHz */
133#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
134#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
135
136static struct clcd_panel lcd_panel = {
137 .mode = {
138 .name = "5.7in QVGA (LQ057Q3DC02)",
139 .xres = 320,
140 .yres = 240,
141 .pixclock = PIX_CLOCK,
142 .left_margin = 11,
143 .right_margin = 400-11-320-2,
144 .upper_margin = 7, // line/7/7/7
145 .lower_margin = 262-7-240-2,
146 .hsync_len = 2, // clk/2/96/200
147 .vsync_len = 2, // line/2/-/34
148 .vmode = FB_VMODE_NONINTERLACED,
149 },
150 .width = -1,
151 .height = -1,
152 .tim2 = TIM2_IHS | TIM2_IVS
153 | (PIX_CLOCK_DIVIDER - 2),
154 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
155 .bpp = 16,
156};
157
158#endif
159
160#if defined CONFIG_FB_ARMCLCD_SHARP_LQ64D343
161
162 /* Logic Product Development LCD 6.4" VGA -10 */
163 /* Sharp PN LQ64D343 */
164
165/* The full horozontal cycle (Th) is clock/750/800/900. */
166/* The full vertical cycle (Tv) is line/515/525/560. */
167
168#define PIX_CLOCK_TARGET (28330000)
169#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
170#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
171
172static struct clcd_panel lcd_panel = {
173 .mode = {
174 .name = "6.4in QVGA (LQ64D343)",
175 .xres = 640,
176 .yres = 480,
177 .pixclock = PIX_CLOCK,
178 .left_margin = 32,
179 .right_margin = 800-32-640-96,
180 .upper_margin = 32, // line/34/34/34
181 .lower_margin = 540-32-480-2,
182 .hsync_len = 96, // clk/2/96/200
183 .vsync_len = 2, // line/2/-/34
184 .vmode = FB_VMODE_NONINTERLACED,
185 },
186 .width = -1,
187 .height = -1,
188 .tim2 = TIM2_IHS | TIM2_IVS
189 | (PIX_CLOCK_DIVIDER - 2),
190 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
191 .bpp = 16,
192};
193
194#endif
195
196#if defined CONFIG_FB_ARMCLCD_SHARP_LQ10D368
197
198 /* Logic Product Development LCD 10.4" VGA -10 */
199 /* Sharp PN LQ10D368 */
200
201#define PIX_CLOCK_TARGET (28330000)
202#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
203#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
204
205static struct clcd_panel lcd_panel = {
206 .mode = {
207 .name = "10.4in VGA (LQ10D368)",
208 .xres = 640,
209 .yres = 480,
210 .pixclock = PIX_CLOCK,
211 .left_margin = 21,
212 .right_margin = 15,
213 .upper_margin = 34,
214 .lower_margin = 5,
215 .hsync_len = 96,
216 .vsync_len = 16,
217 .vmode = FB_VMODE_NONINTERLACED,
218 },
219 .width = -1,
220 .height = -1,
221 .tim2 = TIM2_IHS | TIM2_IVS
222 | (PIX_CLOCK_DIVIDER - 2),
223 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
224 .bpp = 16,
225};
226
227#endif
228
229#if defined CONFIG_FB_ARMCLCD_SHARP_LQ121S1DG41
230
231 /* Logic Product Development LCD 12.1" SVGA -10 */
232 /* Sharp PN LQ121S1DG41, was LQ121S1DG31 */
233
234/* Note that with a 99993900 Hz HCLK, it is not possible to hit the
235 * target clock frequency range of 35MHz to 42MHz. */
236
237/* If the target pixel clock is substantially lower than the panel
238 * spec, this is done to prevent the LCD display from glitching when
239 * the CPU is under load. A pixel clock higher than 25MHz
240 * (empirically determined) will compete with the CPU for bus cycles
241 * for the Ethernet chip. However, even a pixel clock of 10MHz
242 * competes with Compact Flash interface during some operations
243 * (fdisk, e2fsck). And, at that speed the display may have a visible
244 * flicker. */
245
246/* The full horozontal cycle (Th) is clock/832/1056/1395. */
247
248#define PIX_CLOCK_TARGET (20000000)
249#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
250#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
251
252static struct clcd_panel lcd_panel = {
253 .mode = {
254 .name = "12.1in SVGA (LQ121S1DG41)",
255 .xres = 800,
256 .yres = 600,
257 .pixclock = PIX_CLOCK,
258 .left_margin = 89, // ns/5/-/(1/PIX_CLOCK)-10
259 .right_margin = 1056-800-89-128,
260 .upper_margin = 23, // line/23/23/23
261 .lower_margin = 44,
262 .hsync_len = 128, // clk/2/128/200
263 .vsync_len = 4, // line/2/4/6
264 .vmode = FB_VMODE_NONINTERLACED,
265 },
266 .width = -1,
267 .height = -1,
268 .tim2 = TIM2_IHS | TIM2_IVS
269 | (PIX_CLOCK_DIVIDER - 2),
270 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
271 .bpp = 16,
272};
273
274#endif
275
276#if defined CONFIG_FB_ARMCLCD_HITACHI
277
278 /* Hitachi*/
279 /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */
280
281#define PIX_CLOCK_TARGET (49000000)
282#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
283#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
284
285static struct clcd_panel lcd_panel = {
286 .mode = {
287 .name = "Hitachi 800x480",
288 .xres = 800,
289 .yres = 480,
290 .pixclock = PIX_CLOCK,
291 .left_margin = 88,
292 .right_margin = 40,
293 .upper_margin = 32,
294 .lower_margin = 11,
295 .hsync_len = 128,
296 .vsync_len = 2,
297 .vmode = FB_VMODE_NONINTERLACED,
298 },
299 .width = -1,
300 .height = -1,
301 .tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS
302 | (PIX_CLOCK_DIVIDER - 2),
303 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
304 .bpp = 16,
305};
306
307#endif
308
309
310#if defined CONFIG_FB_ARMCLCD_AUO_A070VW01_WIDE
311
312 /* AU Optotronics A070VW01 7.0 Wide Screen color Display*/
313 /* Submitted by Michele Da Rold <michele.darold@ecsproject.com> */
314
315#define PIX_CLOCK_TARGET (10000000)
316#define PIX_CLOCK_DIVIDER CLOCK_TO_DIV (PIX_CLOCK_TARGET, HCLK)
317#define PIX_CLOCK (HCLK/PIX_CLOCK_DIVIDER)
318
319static struct clcd_panel lcd_panel = {
320 .mode = {
321 .name = "7.0in Wide (A070VW01)",
322 .xres = 480,
323 .yres = 234,
324 .pixclock = PIX_CLOCK,
325 .left_margin = 30,
326 .right_margin = 25,
327 .upper_margin = 14,
328 .lower_margin = 12,
329 .hsync_len = 100,
330 .vsync_len = 1,
331 .vmode = FB_VMODE_NONINTERLACED,
332 },
333 .width = -1,
334 .height = -1,
335 .tim2 = TIM2_IPC | TIM2_IHS | TIM2_IVS
336 | (PIX_CLOCK_DIVIDER - 2),
337 .cntl = CNTL_LCDTFT | CNTL_WATERMARK,
338 .bpp = 16,
339};
340
341#endif
342
343#undef NS_TO_CLOCK
344#undef CLOCK_TO_DIV
345
346#endif /* __LCD_PANEL_H__ */
diff --git a/arch/arm/mach-lh7a40x/ssp-cpld.c b/arch/arm/mach-lh7a40x/ssp-cpld.c
new file mode 100644
index 000000000000..a10830186dac
--- /dev/null
+++ b/arch/arm/mach-lh7a40x/ssp-cpld.c
@@ -0,0 +1,343 @@
1/* arch/arm/mach-lh7a40x/ssp-cpld.c
2 *
3 * Copyright (C) 2004,2005 Marc Singer
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 * SSP/SPI driver for the CardEngine CPLD.
10 *
11 */
12
13/* NOTES
14 -----
15
16 o *** This driver is cribbed from the 7952x implementation.
17 Some comments may not apply.
18
19 o This driver contains sufficient logic to control either the
20 serial EEPROMs or the audio codec. It is included in the kernel
21 to support the codec. The EEPROMs are really the responsibility
22 of the boot loader and should probably be left alone.
23
24 o The code must be augmented to cope with multiple, simultaneous
25 clients.
26 o The audio codec writes to the codec chip whenever playback
27 starts.
28 o The touchscreen driver writes to the ads chip every time it
29 samples.
30 o The audio codec must write 16 bits, but the touch chip writes
31 are 8 bits long.
32 o We need to be able to keep these configurations separate while
33 simultaneously active.
34
35 */
36
37#include <linux/module.h>
38#include <linux/kernel.h>
39//#include <linux/sched.h>
40#include <linux/errno.h>
41#include <linux/interrupt.h>
42//#include <linux/ioport.h>
43#include <linux/init.h>
44#include <linux/delay.h>
45#include <linux/spinlock.h>
46
47#include <asm/io.h>
48#include <asm/irq.h>
49#include <asm/hardware.h>
50
51#include <asm/arch/ssp.h>
52
53//#define TALK
54
55#if defined (TALK)
56#define PRINTK(f...) printk (f)
57#else
58#define PRINTK(f...) do {} while (0)
59#endif
60
61#if defined (CONFIG_ARCH_LH7A400)
62# define CPLD_SPID __REGP16(CPLD06_VIRT) /* SPI data */
63# define CPLD_SPIC __REGP16(CPLD08_VIRT) /* SPI control */
64# define CPLD_SPIC_CS_CODEC (1<<0)
65# define CPLD_SPIC_CS_TOUCH (1<<1)
66# define CPLD_SPIC_WRITE (0<<2)
67# define CPLD_SPIC_READ (1<<2)
68# define CPLD_SPIC_DONE (1<<3) /* r/o */
69# define CPLD_SPIC_LOAD (1<<4)
70# define CPLD_SPIC_START (1<<4)
71# define CPLD_SPIC_LOADED (1<<5) /* r/o */
72#endif
73
74#define CPLD_SPI __REGP16(CPLD0A_VIRT) /* SPI operation */
75#define CPLD_SPI_CS_EEPROM (1<<3)
76#define CPLD_SPI_SCLK (1<<2)
77#define CPLD_SPI_TX_SHIFT (1)
78#define CPLD_SPI_TX (1<<CPLD_SPI_TX_SHIFT)
79#define CPLD_SPI_RX_SHIFT (0)
80#define CPLD_SPI_RX (1<<CPLD_SPI_RX_SHIFT)
81
82/* *** FIXME: these timing values are substantially larger than the
83 *** chip requires. We may implement an nsleep () function. */
84#define T_SKH 1 /* Clock time high (us) */
85#define T_SKL 1 /* Clock time low (us) */
86#define T_CS 1 /* Minimum chip select low time (us) */
87#define T_CSS 1 /* Minimum chip select setup time (us) */
88#define T_DIS 1 /* Data setup time (us) */
89
90 /* EEPROM SPI bits */
91#define P_START (1<<9)
92#define P_WRITE (1<<7)
93#define P_READ (2<<7)
94#define P_ERASE (3<<7)
95#define P_EWDS (0<<7)
96#define P_WRAL (0<<7)
97#define P_ERAL (0<<7)
98#define P_EWEN (0<<7)
99#define P_A_EWDS (0<<5)
100#define P_A_WRAL (1<<5)
101#define P_A_ERAL (2<<5)
102#define P_A_EWEN (3<<5)
103
104struct ssp_configuration {
105 int device;
106 int mode;
107 int speed;
108 int frame_size_write;
109 int frame_size_read;
110};
111
112static struct ssp_configuration ssp_configuration;
113static spinlock_t ssp_lock;
114
115static void enable_cs (void)
116{
117 switch (ssp_configuration.device) {
118 case DEVICE_EEPROM:
119 CPLD_SPI |= CPLD_SPI_CS_EEPROM;
120 break;
121 }
122 udelay (T_CSS);
123}
124
125static void disable_cs (void)
126{
127 switch (ssp_configuration.device) {
128 case DEVICE_EEPROM:
129 CPLD_SPI &= ~CPLD_SPI_CS_EEPROM;
130 break;
131 }
132 udelay (T_CS);
133}
134
135static void pulse_clock (void)
136{
137 CPLD_SPI |= CPLD_SPI_SCLK;
138 udelay (T_SKH);
139 CPLD_SPI &= ~CPLD_SPI_SCLK;
140 udelay (T_SKL);
141}
142
143
144/* execute_spi_command
145
146 sends an spi command to a device. It first sends cwrite bits from
147 v. If cread is greater than zero it will read cread bits
148 (discarding the leading 0 bit) and return them. If cread is less
149 than zero it will check for completetion status and return 0 on
150 success or -1 on timeout. If cread is zero it does nothing other
151 than sending the command.
152
153 On the LPD7A400, we can only read or write multiples of 8 bits on
154 the codec and the touch screen device. Here, we round up.
155
156*/
157
158static int execute_spi_command (int v, int cwrite, int cread)
159{
160 unsigned long l = 0;
161
162#if defined (CONFIG_MACH_LPD7A400)
163 /* The codec and touch devices cannot be bit-banged. Instead,
164 * the CPLD provides an eight-bit shift register and a crude
165 * interface. */
166 if ( ssp_configuration.device == DEVICE_CODEC
167 || ssp_configuration.device == DEVICE_TOUCH) {
168 int select = 0;
169
170 PRINTK ("spi(%d %d.%d) 0x%04x",
171 ssp_configuration.device, cwrite, cread,
172 v);
173#if defined (TALK)
174 if (ssp_configuration.device == DEVICE_CODEC)
175 PRINTK (" 0x%03x -> %2d", v & 0x1ff, (v >> 9) & 0x7f);
176#endif
177 PRINTK ("\n");
178
179 if (ssp_configuration.device == DEVICE_CODEC)
180 select = CPLD_SPIC_CS_CODEC;
181 if (ssp_configuration.device == DEVICE_TOUCH)
182 select = CPLD_SPIC_CS_TOUCH;
183 if (cwrite) {
184 for (cwrite = (cwrite + 7)/8; cwrite-- > 0; ) {
185 CPLD_SPID = (v >> (8*cwrite)) & 0xff;
186 CPLD_SPIC = select | CPLD_SPIC_LOAD;
187 while (!(CPLD_SPIC & CPLD_SPIC_LOADED))
188 ;
189 CPLD_SPIC = select;
190 while (!(CPLD_SPIC & CPLD_SPIC_DONE))
191 ;
192 }
193 v = 0;
194 }
195 if (cread) {
196 mdelay (2); /* *** FIXME: required by ads7843? */
197 v = 0;
198 for (cread = (cread + 7)/8; cread-- > 0;) {
199 CPLD_SPID = 0;
200 CPLD_SPIC = select | CPLD_SPIC_READ
201 | CPLD_SPIC_START;
202 while (!(CPLD_SPIC & CPLD_SPIC_LOADED))
203 ;
204 CPLD_SPIC = select | CPLD_SPIC_READ;
205 while (!(CPLD_SPIC & CPLD_SPIC_DONE))
206 ;
207 v = (v << 8) | CPLD_SPID;
208 }
209 }
210 return v;
211 }
212#endif
213
214 PRINTK ("spi(%d) 0x%04x -> 0x%x\r\n", ssp_configuration.device,
215 v & 0x1ff, (v >> 9) & 0x7f);
216
217 enable_cs ();
218
219 v <<= CPLD_SPI_TX_SHIFT; /* Correction for position of SPI_TX bit */
220 while (cwrite--) {
221 CPLD_SPI
222 = (CPLD_SPI & ~CPLD_SPI_TX)
223 | ((v >> cwrite) & CPLD_SPI_TX);
224 udelay (T_DIS);
225 pulse_clock ();
226 }
227
228 if (cread < 0) {
229 int delay = 10;
230 disable_cs ();
231 udelay (1);
232 enable_cs ();
233
234 l = -1;
235 do {
236 if (CPLD_SPI & CPLD_SPI_RX) {
237 l = 0;
238 break;
239 }
240 } while (udelay (1), --delay);
241 }
242 else
243 /* We pulse the clock before the data to skip the leading zero. */
244 while (cread-- > 0) {
245 pulse_clock ();
246 l = (l<<1)
247 | (((CPLD_SPI & CPLD_SPI_RX)
248 >> CPLD_SPI_RX_SHIFT) & 0x1);
249 }
250
251 disable_cs ();
252 return l;
253}
254
255static int ssp_init (void)
256{
257 spin_lock_init (&ssp_lock);
258 memset (&ssp_configuration, 0, sizeof (ssp_configuration));
259 return 0;
260}
261
262
263/* ssp_chip_select
264
265 drops the chip select line for the CPLD shift-register controlled
266 devices. It doesn't enable chip
267
268*/
269
270static void ssp_chip_select (int enable)
271{
272#if defined (CONFIG_MACH_LPD7A400)
273 int select;
274
275 if (ssp_configuration.device == DEVICE_CODEC)
276 select = CPLD_SPIC_CS_CODEC;
277 else if (ssp_configuration.device == DEVICE_TOUCH)
278 select = CPLD_SPIC_CS_TOUCH;
279 else
280 return;
281
282 if (enable)
283 CPLD_SPIC = select;
284 else
285 CPLD_SPIC = 0;
286#endif
287}
288
289static void ssp_acquire (void)
290{
291 spin_lock (&ssp_lock);
292}
293
294static void ssp_release (void)
295{
296 ssp_chip_select (0); /* just in case */
297 spin_unlock (&ssp_lock);
298}
299
300static int ssp_configure (int device, int mode, int speed,
301 int frame_size_write, int frame_size_read)
302{
303 ssp_configuration.device = device;
304 ssp_configuration.mode = mode;
305 ssp_configuration.speed = speed;
306 ssp_configuration.frame_size_write = frame_size_write;
307 ssp_configuration.frame_size_read = frame_size_read;
308
309 return 0;
310}
311
312static int ssp_read (void)
313{
314 return execute_spi_command (0, 0, ssp_configuration.frame_size_read);
315}
316
317static int ssp_write (u16 data)
318{
319 execute_spi_command (data, ssp_configuration.frame_size_write, 0);
320 return 0;
321}
322
323static int ssp_write_read (u16 data)
324{
325 return execute_spi_command (data, ssp_configuration.frame_size_write,
326 ssp_configuration.frame_size_read);
327}
328
329struct ssp_driver lh7a40x_cpld_ssp_driver = {
330 .init = ssp_init,
331 .acquire = ssp_acquire,
332 .release = ssp_release,
333 .configure = ssp_configure,
334 .chip_select = ssp_chip_select,
335 .read = ssp_read,
336 .write = ssp_write,
337 .write_read = ssp_write_read,
338};
339
340
341MODULE_AUTHOR("Marc Singer");
342MODULE_DESCRIPTION("LPD7A40X CPLD SPI driver");
343MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-lh7a40x/time.c b/arch/arm/mach-lh7a40x/time.c
index be377e331f25..ef9af375fcc4 100644
--- a/arch/arm/mach-lh7a40x/time.c
+++ b/arch/arm/mach-lh7a40x/time.c
@@ -1,4 +1,4 @@
1/* 1/*
2 * arch/arm/mach-lh7a40x/time.c 2 * arch/arm/mach-lh7a40x/time.c
3 * 3 *
4 * Copyright (C) 2004 Logic Product Development 4 * Copyright (C) 2004 Logic Product Development
@@ -57,7 +57,7 @@ static struct irqaction lh7a40x_timer_irq = {
57 .handler = lh7a40x_timer_interrupt, 57 .handler = lh7a40x_timer_interrupt,
58}; 58};
59 59
60static void __init lh7a40x_timer_init(void) 60static void __init lh7a40x_timer_init (void)
61{ 61{
62 /* Stop/disable all timers */ 62 /* Stop/disable all timers */
63 TIMER_CONTROL1 = 0; 63 TIMER_CONTROL1 = 0;
diff --git a/arch/arm/mach-pnx4008/Makefile b/arch/arm/mach-pnx4008/Makefile
new file mode 100644
index 000000000000..b457ca0a431a
--- /dev/null
+++ b/arch/arm/mach-pnx4008/Makefile
@@ -0,0 +1,12 @@
1#
2# Makefile for the linux kernel.
3#
4
5obj-y := core.o irq.o time.o clock.o gpio.o serial.o dma.o
6obj-m :=
7obj-n :=
8obj- :=
9
10# Power Management
11obj-$(CONFIG_PM) += pm.o sleep.o
12
diff --git a/arch/arm/mach-pnx4008/Makefile.boot b/arch/arm/mach-pnx4008/Makefile.boot
new file mode 100644
index 000000000000..44c7117e20dd
--- /dev/null
+++ b/arch/arm/mach-pnx4008/Makefile.boot
@@ -0,0 +1,4 @@
1 zreladdr-y := 0x80008000
2params_phys-y := 0x80000100
3initrd_phys-y := 0x80800000
4
diff --git a/arch/arm/mach-pnx4008/clock.c b/arch/arm/mach-pnx4008/clock.c
new file mode 100644
index 000000000000..285b22f631e9
--- /dev/null
+++ b/arch/arm/mach-pnx4008/clock.c
@@ -0,0 +1,1010 @@
1/*
2 * arch/arm/mach-pnx4008/clock.c
3 *
4 * Clock control driver for PNX4008
5 *
6 * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
7 * Generic clock management functions are partially based on:
8 * linux/arch/arm/mach-omap/clock.c
9 *
10 * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
13 * or implied.
14 */
15
16#include <linux/module.h>
17#include <linux/kernel.h>
18#include <linux/list.h>
19#include <linux/errno.h>
20#include <linux/device.h>
21#include <linux/err.h>
22#include <linux/delay.h>
23
24#include <asm/semaphore.h>
25#include <asm/hardware.h>
26#include <asm/io.h>
27
28#include <asm/arch/clock.h>
29#include "clock.h"
30
31/*forward declaration*/
32static struct clk per_ck;
33static struct clk hclk_ck;
34static struct clk ck_1MHz;
35static struct clk ck_13MHz;
36static struct clk ck_pll1;
37static int local_set_rate(struct clk *clk, u32 rate);
38
39static inline void clock_lock(void)
40{
41 local_irq_disable();
42}
43
44static inline void clock_unlock(void)
45{
46 local_irq_enable();
47}
48
49static void propagate_rate(struct clk *clk)
50{
51 struct clk *tmp_clk;
52
53 tmp_clk = clk;
54 while (tmp_clk->propagate_next) {
55 tmp_clk = tmp_clk->propagate_next;
56 local_set_rate(tmp_clk, tmp_clk->user_rate);
57 }
58}
59
60static inline void clk_reg_disable(struct clk *clk)
61{
62 if (clk->enable_reg)
63 __raw_writel(__raw_readl(clk->enable_reg) &
64 ~(1 << clk->enable_shift), clk->enable_reg);
65}
66
67static inline void clk_reg_enable(struct clk *clk)
68{
69 if (clk->enable_reg)
70 __raw_writel(__raw_readl(clk->enable_reg) |
71 (1 << clk->enable_shift), clk->enable_reg);
72}
73
74static inline void clk_reg_disable1(struct clk *clk)
75{
76 if (clk->enable_reg1)
77 __raw_writel(__raw_readl(clk->enable_reg1) &
78 ~(1 << clk->enable_shift1), clk->enable_reg1);
79}
80
81static inline void clk_reg_enable1(struct clk *clk)
82{
83 if (clk->enable_reg1)
84 __raw_writel(__raw_readl(clk->enable_reg1) |
85 (1 << clk->enable_shift1), clk->enable_reg1);
86}
87
88static int clk_wait_for_pll_lock(struct clk *clk)
89{
90 int i;
91 i = 0;
92 while (i++ < 0xFFF && !(__raw_readl(clk->scale_reg) & 1)) ; /*wait for PLL to lock */
93
94 if (!(__raw_readl(clk->scale_reg) & 1)) {
95 printk(KERN_ERR
96 "%s ERROR: failed to lock, scale reg data: %x\n",
97 clk->name, __raw_readl(clk->scale_reg));
98 return -1;
99 }
100 return 0;
101}
102
103static int switch_to_dirty_13mhz(struct clk *clk)
104{
105 int i;
106 int ret;
107 u32 tmp_reg;
108
109 ret = 0;
110
111 if (!clk->rate)
112 clk_reg_enable1(clk);
113
114 tmp_reg = __raw_readl(clk->parent_switch_reg);
115 /*if 13Mhz clock selected, select 13'MHz (dirty) source from OSC */
116 if (!(tmp_reg & 1)) {
117 tmp_reg |= (1 << 1); /* Trigger switch to 13'MHz (dirty) clock */
118 __raw_writel(tmp_reg, clk->parent_switch_reg);
119 i = 0;
120 while (i++ < 0xFFF && !(__raw_readl(clk->parent_switch_reg) & 1)) ; /*wait for 13'MHz selection status */
121
122 if (!(__raw_readl(clk->parent_switch_reg) & 1)) {
123 printk(KERN_ERR
124 "%s ERROR: failed to select 13'MHz, parent sw reg data: %x\n",
125 clk->name, __raw_readl(clk->parent_switch_reg));
126 ret = -1;
127 }
128 }
129
130 if (!clk->rate)
131 clk_reg_disable1(clk);
132
133 return ret;
134}
135
136static int switch_to_clean_13mhz(struct clk *clk)
137{
138 int i;
139 int ret;
140 u32 tmp_reg;
141
142 ret = 0;
143
144 if (!clk->rate)
145 clk_reg_enable1(clk);
146
147 tmp_reg = __raw_readl(clk->parent_switch_reg);
148 /*if 13'Mhz clock selected, select 13MHz (clean) source from OSC */
149 if (tmp_reg & 1) {
150 tmp_reg &= ~(1 << 1); /* Trigger switch to 13MHz (clean) clock */
151 __raw_writel(tmp_reg, clk->parent_switch_reg);
152 i = 0;
153 while (i++ < 0xFFF && (__raw_readl(clk->parent_switch_reg) & 1)) ; /*wait for 13MHz selection status */
154
155 if (__raw_readl(clk->parent_switch_reg) & 1) {
156 printk(KERN_ERR
157 "%s ERROR: failed to select 13MHz, parent sw reg data: %x\n",
158 clk->name, __raw_readl(clk->parent_switch_reg));
159 ret = -1;
160 }
161 }
162
163 if (!clk->rate)
164 clk_reg_disable1(clk);
165
166 return ret;
167}
168
169static int set_13MHz_parent(struct clk *clk, struct clk *parent)
170{
171 int ret = -EINVAL;
172
173 if (parent == &ck_13MHz)
174 ret = switch_to_clean_13mhz(clk);
175 else if (parent == &ck_pll1)
176 ret = switch_to_dirty_13mhz(clk);
177
178 return ret;
179}
180
181#define PLL160_MIN_FCCO 156000
182#define PLL160_MAX_FCCO 320000
183
184/*
185 * Calculate pll160 settings.
186 * Possible input: up to 320MHz with step of clk->parent->rate.
187 * In PNX4008 parent rate for pll160s may be either 1 or 13MHz.
188 * Ignored paths: "feedback" (bit 13 set), "div-by-N".
189 * Setting ARM PLL4 rate to 0 will put CPU into direct run mode.
190 * Setting PLL5 and PLL3 rate to 0 will disable USB and DSP clock input.
191 * Please refer to PNX4008 IC manual for details.
192 */
193
194static int pll160_set_rate(struct clk *clk, u32 rate)
195{
196 u32 tmp_reg, tmp_m, tmp_2p, i;
197 u32 parent_rate;
198 int ret = -EINVAL;
199
200 parent_rate = clk->parent->rate;
201
202 if (!parent_rate)
203 goto out;
204
205 /* set direct run for ARM or disable output for others */
206 clk_reg_disable(clk);
207
208 /* disable source input as well (ignored for ARM) */
209 clk_reg_disable1(clk);
210
211 tmp_reg = __raw_readl(clk->scale_reg);
212 tmp_reg &= ~0x1ffff; /*clear all settings, power down */
213 __raw_writel(tmp_reg, clk->scale_reg);
214
215 rate -= rate % parent_rate; /*round down the input */
216
217 if (rate > PLL160_MAX_FCCO)
218 rate = PLL160_MAX_FCCO;
219
220 if (!rate) {
221 clk->rate = 0;
222 ret = 0;
223 goto out;
224 }
225
226 clk_reg_enable1(clk);
227 tmp_reg = __raw_readl(clk->scale_reg);
228
229 if (rate == parent_rate) {
230 /*enter direct bypass mode */
231 tmp_reg |= ((1 << 14) | (1 << 15));
232 __raw_writel(tmp_reg, clk->scale_reg);
233 clk->rate = parent_rate;
234 clk_reg_enable(clk);
235 ret = 0;
236 goto out;
237 }
238
239 i = 0;
240 for (tmp_2p = 1; tmp_2p < 16; tmp_2p <<= 1) {
241 if (rate * tmp_2p >= PLL160_MIN_FCCO)
242 break;
243 i++;
244 }
245
246 if (tmp_2p > 1)
247 tmp_reg |= ((i - 1) << 11);
248 else
249 tmp_reg |= (1 << 14); /*direct mode, no divide */
250
251 tmp_m = rate * tmp_2p;
252 tmp_m /= parent_rate;
253
254 tmp_reg |= (tmp_m - 1) << 1; /*calculate M */
255 tmp_reg |= (1 << 16); /*power up PLL */
256 __raw_writel(tmp_reg, clk->scale_reg);
257
258 if (clk_wait_for_pll_lock(clk) < 0) {
259 clk_reg_disable(clk);
260 clk_reg_disable1(clk);
261
262 tmp_reg = __raw_readl(clk->scale_reg);
263 tmp_reg &= ~0x1ffff; /*clear all settings, power down */
264 __raw_writel(tmp_reg, clk->scale_reg);
265 clk->rate = 0;
266 ret = -EFAULT;
267 goto out;
268 }
269
270 clk->rate = (tmp_m * parent_rate) / tmp_2p;
271
272 if (clk->flags & RATE_PROPAGATES)
273 propagate_rate(clk);
274
275 clk_reg_enable(clk);
276 ret = 0;
277
278out:
279 return ret;
280}
281
282/*configure PER_CLK*/
283static int per_clk_set_rate(struct clk *clk, u32 rate)
284{
285 u32 tmp;
286
287 tmp = __raw_readl(clk->scale_reg);
288 tmp &= ~(0x1f << 2);
289 tmp |= ((clk->parent->rate / clk->rate) - 1) << 2;
290 __raw_writel(tmp, clk->scale_reg);
291 clk->rate = rate;
292 return 0;
293}
294
295/*configure HCLK*/
296static int hclk_set_rate(struct clk *clk, u32 rate)
297{
298 u32 tmp;
299 tmp = __raw_readl(clk->scale_reg);
300 tmp = tmp & ~0x3;
301 switch (rate) {
302 case 1:
303 break;
304 case 2:
305 tmp |= 1;
306 break;
307 case 4:
308 tmp |= 2;
309 break;
310 }
311
312 __raw_writel(tmp, clk->scale_reg);
313 clk->rate = rate;
314 return 0;
315}
316
317static u32 hclk_round_rate(struct clk *clk, u32 rate)
318{
319 switch (rate) {
320 case 1:
321 case 4:
322 return rate;
323 }
324 return 2;
325}
326
327static u32 per_clk_round_rate(struct clk *clk, u32 rate)
328{
329 return CLK_RATE_13MHZ;
330}
331
332static int on_off_set_rate(struct clk *clk, u32 rate)
333{
334 if (rate) {
335 clk_reg_enable(clk);
336 clk->rate = 1;
337 } else {
338 clk_reg_disable(clk);
339 clk->rate = 0;
340 }
341 return 0;
342}
343
344static int on_off_inv_set_rate(struct clk *clk, u32 rate)
345{
346 if (rate) {
347 clk_reg_disable(clk); /*enable bit is inverted */
348 clk->rate = 1;
349 } else {
350 clk_reg_enable(clk);
351 clk->rate = 0;
352 }
353 return 0;
354}
355
356static u32 on_off_round_rate(struct clk *clk, u32 rate)
357{
358 return (rate ? 1 : 0);
359}
360
361static u32 pll4_round_rate(struct clk *clk, u32 rate)
362{
363 if (rate > CLK_RATE_208MHZ)
364 rate = CLK_RATE_208MHZ;
365 if (rate == CLK_RATE_208MHZ && hclk_ck.user_rate == 1)
366 rate = CLK_RATE_208MHZ - CLK_RATE_13MHZ;
367 return (rate - (rate % (hclk_ck.user_rate * CLK_RATE_13MHZ)));
368}
369
370static u32 pll3_round_rate(struct clk *clk, u32 rate)
371{
372 if (rate > CLK_RATE_208MHZ)
373 rate = CLK_RATE_208MHZ;
374 return (rate - rate % CLK_RATE_13MHZ);
375}
376
377static u32 pll5_round_rate(struct clk *clk, u32 rate)
378{
379 return (rate ? CLK_RATE_48MHZ : 0);
380}
381
382static u32 ck_13MHz_round_rate(struct clk *clk, u32 rate)
383{
384 return (rate ? CLK_RATE_13MHZ : 0);
385}
386
387static int ck_13MHz_set_rate(struct clk *clk, u32 rate)
388{
389 if (rate) {
390 clk_reg_disable(clk); /*enable bit is inverted */
391 udelay(500);
392 clk->rate = CLK_RATE_13MHZ;
393 ck_1MHz.rate = CLK_RATE_1MHZ;
394 } else {
395 clk_reg_enable(clk);
396 clk->rate = 0;
397 ck_1MHz.rate = 0;
398 }
399 return 0;
400}
401
402static int pll1_set_rate(struct clk *clk, u32 rate)
403{
404#if 0 /* doesn't work on some boards, probably a HW BUG */
405 if (rate) {
406 clk_reg_disable(clk); /*enable bit is inverted */
407 if (!clk_wait_for_pll_lock(clk)) {
408 clk->rate = CLK_RATE_13MHZ;
409 } else {
410 clk_reg_enable(clk);
411 clk->rate = 0;
412 }
413
414 } else {
415 clk_reg_enable(clk);
416 clk->rate = 0;
417 }
418#endif
419 return 0;
420}
421
422/* Clock sources */
423
424static struct clk osc_13MHz = {
425 .name = "osc_13MHz",
426 .flags = FIXED_RATE,
427 .rate = CLK_RATE_13MHZ,
428};
429
430static struct clk ck_13MHz = {
431 .name = "ck_13MHz",
432 .parent = &osc_13MHz,
433 .flags = NEEDS_INITIALIZATION,
434 .round_rate = &ck_13MHz_round_rate,
435 .set_rate = &ck_13MHz_set_rate,
436 .enable_reg = OSC13CTRL_REG,
437 .enable_shift = 0,
438 .rate = CLK_RATE_13MHZ,
439};
440
441static struct clk osc_32KHz = {
442 .name = "osc_32KHz",
443 .flags = FIXED_RATE,
444 .rate = CLK_RATE_32KHZ,
445};
446
447/*attached to PLL5*/
448static struct clk ck_1MHz = {
449 .name = "ck_1MHz",
450 .flags = FIXED_RATE | PARENT_SET_RATE,
451 .parent = &ck_13MHz,
452};
453
454/* PLL1 (397) - provides 13' MHz clock */
455static struct clk ck_pll1 = {
456 .name = "ck_pll1",
457 .parent = &osc_32KHz,
458 .flags = NEEDS_INITIALIZATION,
459 .round_rate = &ck_13MHz_round_rate,
460 .set_rate = &pll1_set_rate,
461 .enable_reg = PLLCTRL_REG,
462 .enable_shift = 1,
463 .scale_reg = PLLCTRL_REG,
464 .rate = CLK_RATE_13MHZ,
465};
466
467/* CPU/Bus PLL */
468static struct clk ck_pll4 = {
469 .name = "ck_pll4",
470 .parent = &ck_pll1,
471 .flags = RATE_PROPAGATES | NEEDS_INITIALIZATION,
472 .propagate_next = &per_ck,
473 .round_rate = &pll4_round_rate,
474 .set_rate = &pll160_set_rate,
475 .rate = CLK_RATE_208MHZ,
476 .scale_reg = HCLKPLLCTRL_REG,
477 .enable_reg = PWRCTRL_REG,
478 .enable_shift = 2,
479 .parent_switch_reg = SYSCLKCTRL_REG,
480 .set_parent = &set_13MHz_parent,
481};
482
483/* USB PLL */
484static struct clk ck_pll5 = {
485 .name = "ck_pll5",
486 .parent = &ck_1MHz,
487 .flags = NEEDS_INITIALIZATION,
488 .round_rate = &pll5_round_rate,
489 .set_rate = &pll160_set_rate,
490 .scale_reg = USBCTRL_REG,
491 .enable_reg = USBCTRL_REG,
492 .enable_shift = 18,
493 .enable_reg1 = USBCTRL_REG,
494 .enable_shift1 = 17,
495};
496
497/* XPERTTeak DSP PLL */
498static struct clk ck_pll3 = {
499 .name = "ck_pll3",
500 .parent = &ck_pll1,
501 .flags = NEEDS_INITIALIZATION,
502 .round_rate = &pll3_round_rate,
503 .set_rate = &pll160_set_rate,
504 .scale_reg = DSPPLLCTRL_REG,
505 .enable_reg = DSPCLKCTRL_REG,
506 .enable_shift = 3,
507 .enable_reg1 = DSPCLKCTRL_REG,
508 .enable_shift1 = 2,
509 .parent_switch_reg = DSPCLKCTRL_REG,
510 .set_parent = &set_13MHz_parent,
511};
512
513static struct clk hclk_ck = {
514 .name = "hclk_ck",
515 .parent = &ck_pll4,
516 .flags = PARENT_SET_RATE,
517 .set_rate = &hclk_set_rate,
518 .round_rate = &hclk_round_rate,
519 .scale_reg = HCLKDIVCTRL_REG,
520 .rate = 2,
521 .user_rate = 2,
522};
523
524static struct clk per_ck = {
525 .name = "per_ck",
526 .parent = &ck_pll4,
527 .flags = FIXED_RATE,
528 .propagate_next = &hclk_ck,
529 .set_rate = &per_clk_set_rate,
530 .round_rate = &per_clk_round_rate,
531 .scale_reg = HCLKDIVCTRL_REG,
532 .rate = CLK_RATE_13MHZ,
533 .user_rate = CLK_RATE_13MHZ,
534};
535
536static struct clk m2hclk_ck = {
537 .name = "m2hclk_ck",
538 .parent = &hclk_ck,
539 .flags = NEEDS_INITIALIZATION,
540 .round_rate = &on_off_round_rate,
541 .set_rate = &on_off_inv_set_rate,
542 .rate = 1,
543 .enable_shift = 6,
544 .enable_reg = PWRCTRL_REG,
545};
546
547static struct clk vfp9_ck = {
548 .name = "vfp9_ck",
549 .parent = &ck_pll4,
550 .flags = NEEDS_INITIALIZATION,
551 .round_rate = &on_off_round_rate,
552 .set_rate = &on_off_set_rate,
553 .rate = 1,
554 .enable_shift = 4,
555 .enable_reg = VFP9CLKCTRL_REG,
556};
557
558static struct clk keyscan_ck = {
559 .name = "keyscan_ck",
560 .parent = &osc_32KHz,
561 .flags = NEEDS_INITIALIZATION,
562 .round_rate = &on_off_round_rate,
563 .set_rate = &on_off_set_rate,
564 .enable_shift = 0,
565 .enable_reg = KEYCLKCTRL_REG,
566};
567
568static struct clk touch_ck = {
569 .name = "touch_ck",
570 .parent = &osc_32KHz,
571 .flags = NEEDS_INITIALIZATION,
572 .round_rate = &on_off_round_rate,
573 .set_rate = &on_off_set_rate,
574 .enable_shift = 0,
575 .enable_reg = TSCLKCTRL_REG,
576};
577
578static struct clk pwm1_ck = {
579 .name = "pwm1_ck",
580 .parent = &osc_32KHz,
581 .flags = NEEDS_INITIALIZATION,
582 .round_rate = &on_off_round_rate,
583 .set_rate = &on_off_set_rate,
584 .enable_shift = 0,
585 .enable_reg = PWMCLKCTRL_REG,
586};
587
588static struct clk pwm2_ck = {
589 .name = "pwm2_ck",
590 .parent = &osc_32KHz,
591 .flags = NEEDS_INITIALIZATION,
592 .round_rate = &on_off_round_rate,
593 .set_rate = &on_off_set_rate,
594 .enable_shift = 2,
595 .enable_reg = PWMCLKCTRL_REG,
596};
597
598static struct clk jpeg_ck = {
599 .name = "jpeg_ck",
600 .parent = &hclk_ck,
601 .flags = NEEDS_INITIALIZATION,
602 .round_rate = &on_off_round_rate,
603 .set_rate = &on_off_set_rate,
604 .enable_shift = 0,
605 .enable_reg = JPEGCLKCTRL_REG,
606};
607
608static struct clk ms_ck = {
609 .name = "ms_ck",
610 .parent = &ck_pll4,
611 .flags = NEEDS_INITIALIZATION,
612 .round_rate = &on_off_round_rate,
613 .set_rate = &on_off_set_rate,
614 .enable_shift = 5,
615 .enable_reg = MSCTRL_REG,
616};
617
618static struct clk dum_ck = {
619 .name = "dum_ck",
620 .parent = &hclk_ck,
621 .flags = NEEDS_INITIALIZATION,
622 .round_rate = &on_off_round_rate,
623 .set_rate = &on_off_set_rate,
624 .enable_shift = 0,
625 .enable_reg = DUMCLKCTRL_REG,
626};
627
628static struct clk flash_ck = {
629 .name = "flash_ck",
630 .parent = &hclk_ck,
631 .round_rate = &on_off_round_rate,
632 .set_rate = &on_off_set_rate,
633 .enable_shift = 1, /* Only MLC clock supported */
634 .enable_reg = FLASHCLKCTRL_REG,
635};
636
637static struct clk i2c0_ck = {
638 .name = "i2c0_ck",
639 .parent = &per_ck,
640 .flags = NEEDS_INITIALIZATION,
641 .round_rate = &on_off_round_rate,
642 .set_rate = &on_off_set_rate,
643 .enable_shift = 0,
644 .enable_reg = I2CCLKCTRL_REG,
645};
646
647static struct clk i2c1_ck = {
648 .name = "i2c1_ck",
649 .parent = &per_ck,
650 .flags = NEEDS_INITIALIZATION,
651 .round_rate = &on_off_round_rate,
652 .set_rate = &on_off_set_rate,
653 .enable_shift = 1,
654 .enable_reg = I2CCLKCTRL_REG,
655};
656
657static struct clk i2c2_ck = {
658 .name = "i2c2_ck",
659 .parent = &per_ck,
660 .flags = NEEDS_INITIALIZATION,
661 .round_rate = &on_off_round_rate,
662 .set_rate = &on_off_set_rate,
663 .enable_shift = 2,
664 .enable_reg = USB_OTG_CLKCTRL_REG,
665};
666
667static struct clk spi0_ck = {
668 .name = "spi0_ck",
669 .parent = &hclk_ck,
670 .flags = NEEDS_INITIALIZATION,
671 .round_rate = &on_off_round_rate,
672 .set_rate = &on_off_set_rate,
673 .enable_shift = 0,
674 .enable_reg = SPICTRL_REG,
675};
676
677static struct clk spi1_ck = {
678 .name = "spi1_ck",
679 .parent = &hclk_ck,
680 .flags = NEEDS_INITIALIZATION,
681 .round_rate = &on_off_round_rate,
682 .set_rate = &on_off_set_rate,
683 .enable_shift = 4,
684 .enable_reg = SPICTRL_REG,
685};
686
687static struct clk dma_ck = {
688 .name = "dma_ck",
689 .parent = &hclk_ck,
690 .round_rate = &on_off_round_rate,
691 .set_rate = &on_off_set_rate,
692 .enable_shift = 0,
693 .enable_reg = DMACLKCTRL_REG,
694};
695
696static struct clk uart3_ck = {
697 .name = "uart3_ck",
698 .parent = &per_ck,
699 .flags = NEEDS_INITIALIZATION,
700 .round_rate = &on_off_round_rate,
701 .set_rate = &on_off_set_rate,
702 .rate = 1,
703 .enable_shift = 0,
704 .enable_reg = UARTCLKCTRL_REG,
705};
706
707static struct clk uart4_ck = {
708 .name = "uart4_ck",
709 .parent = &per_ck,
710 .flags = NEEDS_INITIALIZATION,
711 .round_rate = &on_off_round_rate,
712 .set_rate = &on_off_set_rate,
713 .enable_shift = 1,
714 .enable_reg = UARTCLKCTRL_REG,
715};
716
717static struct clk uart5_ck = {
718 .name = "uart5_ck",
719 .parent = &per_ck,
720 .flags = NEEDS_INITIALIZATION,
721 .round_rate = &on_off_round_rate,
722 .set_rate = &on_off_set_rate,
723 .rate = 1,
724 .enable_shift = 2,
725 .enable_reg = UARTCLKCTRL_REG,
726};
727
728static struct clk uart6_ck = {
729 .name = "uart6_ck",
730 .parent = &per_ck,
731 .flags = NEEDS_INITIALIZATION,
732 .round_rate = &on_off_round_rate,
733 .set_rate = &on_off_set_rate,
734 .enable_shift = 3,
735 .enable_reg = UARTCLKCTRL_REG,
736};
737
738/* These clocks are visible outside this module
739 * and can be initialized
740 */
741static struct clk *onchip_clks[] = {
742 &ck_13MHz,
743 &ck_pll1,
744 &ck_pll4,
745 &ck_pll5,
746 &ck_pll3,
747 &vfp9_ck,
748 &m2hclk_ck,
749 &hclk_ck,
750 &dma_ck,
751 &flash_ck,
752 &dum_ck,
753 &keyscan_ck,
754 &pwm1_ck,
755 &pwm2_ck,
756 &jpeg_ck,
757 &ms_ck,
758 &touch_ck,
759 &i2c0_ck,
760 &i2c1_ck,
761 &i2c2_ck,
762 &spi0_ck,
763 &spi1_ck,
764 &uart3_ck,
765 &uart4_ck,
766 &uart5_ck,
767 &uart6_ck,
768};
769
770static int local_set_rate(struct clk *clk, u32 rate)
771{
772 int ret = -EINVAL;
773 if (clk->set_rate) {
774
775 if (clk->user_rate == clk->rate && clk->parent->rate) {
776 /* if clock enabled or rate not set */
777 clk->user_rate = clk->round_rate(clk, rate);
778 ret = clk->set_rate(clk, clk->user_rate);
779 } else
780 clk->user_rate = clk->round_rate(clk, rate);
781 ret = 0;
782 }
783 return ret;
784}
785
786int clk_set_rate(struct clk *clk, unsigned long rate)
787{
788 int ret = -EINVAL;
789
790 if (clk->flags & FIXED_RATE)
791 goto out;
792
793 clock_lock();
794 if ((clk->flags & PARENT_SET_RATE) && clk->parent) {
795
796 clk->user_rate = clk->round_rate(clk, rate);
797 /* parent clock needs to be refreshed
798 for the setting to take effect */
799 } else {
800 ret = local_set_rate(clk, rate);
801 }
802 ret = 0;
803 clock_unlock();
804
805out:
806 return ret;
807}
808
809EXPORT_SYMBOL(clk_set_rate);
810
811struct clk *clk_get(struct device *dev, const char *id)
812{
813 struct clk *clk = ERR_PTR(-ENOENT);
814 struct clk **clkp;
815
816 clock_lock();
817 for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
818 clkp++) {
819 if (strcmp(id, (*clkp)->name) == 0
820 && try_module_get((*clkp)->owner)) {
821 clk = (*clkp);
822 break;
823 }
824 }
825 clock_unlock();
826
827 return clk;
828}
829EXPORT_SYMBOL(clk_get);
830
831void clk_put(struct clk *clk)
832{
833 clock_lock();
834 if (clk && !IS_ERR(clk))
835 module_put(clk->owner);
836 clock_unlock();
837}
838EXPORT_SYMBOL(clk_put);
839
840unsigned long clk_get_rate(struct clk *clk)
841{
842 unsigned long ret;
843 clock_lock();
844 ret = clk->rate;
845 clock_unlock();
846 return ret;
847}
848EXPORT_SYMBOL(clk_get_rate);
849
850static int local_clk_enable(struct clk *clk)
851{
852 int ret = 0;
853
854 if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
855 && clk->user_rate)
856 ret = clk->set_rate(clk, clk->user_rate);
857 return ret;
858}
859
860static void local_clk_disable(struct clk *clk)
861{
862 if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
863 clk->set_rate(clk, 0);
864}
865
866int clk_enable(struct clk *clk)
867{
868 int ret = 0;
869
870 clock_lock();
871 ret = local_clk_enable(clk);
872 clock_unlock();
873 return ret;
874}
875
876EXPORT_SYMBOL(clk_enable);
877
878void clk_disable(struct clk *clk)
879{
880 clock_lock();
881 local_clk_disable(clk);
882 clock_unlock();
883}
884
885EXPORT_SYMBOL(clk_disable);
886
887static void local_clk_unuse(struct clk *clk)
888{
889 if (clk->usecount > 0 && !(--clk->usecount)) {
890 local_clk_disable(clk);
891 if (clk->parent)
892 local_clk_unuse(clk->parent);
893 }
894}
895
896static int local_clk_use(struct clk *clk)
897{
898 int ret = 0;
899 if (clk->usecount++ == 0) {
900 if (clk->parent)
901 ret = local_clk_use(clk->parent);
902
903 if (ret != 0) {
904 clk->usecount--;
905 goto out;
906 }
907
908 ret = local_clk_enable(clk);
909
910 if (ret != 0 && clk->parent) {
911 local_clk_unuse(clk->parent);
912 clk->usecount--;
913 }
914 }
915out:
916 return ret;
917}
918
919/* The main purpose of clk_use ans clk_unuse functions
920 * is to control switching 13MHz oscillator and PLL1 (13'MHz),
921 * so that they are disabled whenever none of PLL2-5 is using them.
922 * Although in theory these functions should work with any clock,
923 * please use them only on PLL2 - PLL5 to avoid confusion.
924 */
925int clk_use(struct clk *clk)
926{
927 int ret = 0;
928
929 clock_lock();
930 ret = local_clk_use(clk);
931 clock_unlock();
932 return ret;
933}
934EXPORT_SYMBOL(clk_use);
935
936void clk_unuse(struct clk *clk)
937{
938
939 clock_lock();
940 local_clk_unuse(clk);
941 clock_unlock();
942}
943
944EXPORT_SYMBOL(clk_unuse);
945
946long clk_round_rate(struct clk *clk, unsigned long rate)
947{
948 long ret;
949 clock_lock();
950 if (clk->round_rate)
951 ret = clk->round_rate(clk, rate);
952 else
953 ret = clk->rate;
954 clock_unlock();
955 return ret;
956}
957
958EXPORT_SYMBOL(clk_round_rate);
959
960int clk_set_parent(struct clk *clk, struct clk *parent)
961{
962 int ret = -ENODEV;
963 if (!clk->set_parent)
964 goto out;
965
966 clock_lock();
967 ret = clk->set_parent(clk, parent);
968 if (!ret)
969 clk->parent = parent;
970 clock_unlock();
971
972out:
973 return ret;
974}
975
976EXPORT_SYMBOL(clk_set_parent);
977
978static int __init clk_init(void)
979{
980 struct clk **clkp;
981
982 /* Disable autoclocking, as it doesn't seem to work */
983 __raw_writel(0xff, AUTOCLK_CTRL);
984
985 for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
986 clkp++) {
987 if (((*clkp)->flags & NEEDS_INITIALIZATION)
988 && ((*clkp)->set_rate)) {
989 (*clkp)->user_rate = (*clkp)->rate;
990 local_set_rate((*clkp), (*clkp)->user_rate);
991 if ((*clkp)->set_parent)
992 (*clkp)->set_parent((*clkp), (*clkp)->parent);
993 }
994 pr_debug("%s: clock %s, rate %ld\n",
995 __FUNCTION__, (*clkp)->name, (*clkp)->rate);
996 }
997
998 clk_use(&ck_pll4);
999
1000 /* if ck_13MHz is not used, disable it. */
1001 if (ck_13MHz.usecount == 0)
1002 local_clk_disable(&ck_13MHz);
1003
1004 /* Disable autoclocking */
1005 __raw_writeb(0xff, AUTOCLK_CTRL);
1006
1007 return 0;
1008}
1009
1010arch_initcall(clk_init);
diff --git a/arch/arm/mach-pnx4008/clock.h b/arch/arm/mach-pnx4008/clock.h
new file mode 100644
index 000000000000..cd58f372cfd0
--- /dev/null
+++ b/arch/arm/mach-pnx4008/clock.h
@@ -0,0 +1,43 @@
1/*
2 * arch/arm/mach-pnx4008/clock.h
3 *
4 * Clock control driver for PNX4008 - internal header file
5 *
6 * Author: Vitaly Wool <source@mvista.com>
7 *
8 * 2006 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#ifndef __ARCH_ARM_PNX4008_CLOCK_H__
14#define __ARCH_ARM_PNX4008_CLOCK_H__
15
16struct clk {
17 struct list_head node;
18 struct module *owner;
19 const char *name;
20 struct clk *parent;
21 struct clk *propagate_next;
22 u32 rate;
23 u32 user_rate;
24 s8 usecount;
25 u32 flags;
26 u32 scale_reg;
27 u8 enable_shift;
28 u32 enable_reg;
29 u8 enable_shift1;
30 u32 enable_reg1;
31 u32 parent_switch_reg;
32 u32(*round_rate) (struct clk *, u32);
33 int (*set_rate) (struct clk *, u32);
34 int (*set_parent) (struct clk * clk, struct clk * parent);
35};
36
37/* Flags */
38#define RATE_PROPAGATES (1<<0)
39#define NEEDS_INITIALIZATION (1<<1)
40#define PARENT_SET_RATE (1<<2)
41#define FIXED_RATE (1<<3)
42
43#endif
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
new file mode 100644
index 000000000000..ba91daad64fb
--- /dev/null
+++ b/arch/arm/mach-pnx4008/core.c
@@ -0,0 +1,207 @@
1/*
2 * arch/arm/mach-pnx4008/core.c
3 *
4 * PNX4008 core startup code
5 *
6 * Authors: Vitaly Wool, Dmitry Chigirev,
7 * Grigory Tolstolytkin, Dmitry Pervushin <source@mvista.com>
8 *
9 * Based on reference code received from Philips:
10 * Copyright (C) 2003 Philips Semiconductors
11 *
12 * 2005 (c) MontaVista Software, Inc. This file is licensed under
13 * the terms of the GNU General Public License version 2. This program
14 * is licensed "as is" without any warranty of any kind, whether express
15 * or implied.
16 */
17
18#include <linux/kernel.h>
19#include <linux/types.h>
20#include <linux/mm.h>
21#include <linux/interrupt.h>
22#include <linux/list.h>
23#include <linux/init.h>
24#include <linux/ioport.h>
25#include <linux/serial_8250.h>
26#include <linux/device.h>
27#include <linux/spi/spi.h>
28
29#include <asm/hardware.h>
30#include <asm/irq.h>
31#include <asm/io.h>
32#include <asm/setup.h>
33#include <asm/mach-types.h>
34#include <asm/pgtable.h>
35#include <asm/page.h>
36#include <asm/system.h>
37
38#include <asm/mach/arch.h>
39#include <asm/mach/irq.h>
40#include <asm/mach/map.h>
41#include <asm/mach/time.h>
42
43#include <asm/arch/irq.h>
44#include <asm/arch/clock.h>
45#include <asm/arch/dma.h>
46
47struct resource spipnx_0_resources[] = {
48 {
49 .start = PNX4008_SPI1_BASE,
50 .end = PNX4008_SPI1_BASE + SZ_4K,
51 .flags = IORESOURCE_MEM,
52 }, {
53 .start = PER_SPI1_REC_XMIT,
54 .flags = IORESOURCE_DMA,
55 }, {
56 .start = SPI1_INT,
57 .flags = IORESOURCE_IRQ,
58 }, {
59 .flags = 0,
60 },
61};
62
63struct resource spipnx_1_resources[] = {
64 {
65 .start = PNX4008_SPI2_BASE,
66 .end = PNX4008_SPI2_BASE + SZ_4K,
67 .flags = IORESOURCE_MEM,
68 }, {
69 .start = PER_SPI2_REC_XMIT,
70 .flags = IORESOURCE_DMA,
71 }, {
72 .start = SPI2_INT,
73 .flags = IORESOURCE_IRQ,
74 }, {
75 .flags = 0,
76 }
77};
78
79static struct spi_board_info spi_board_info[] __initdata = {
80 {
81 .modalias = "m25p80",
82 .max_speed_hz = 1000000,
83 .bus_num = 1,
84 .chip_select = 0,
85 },
86};
87
88static struct platform_device spipnx_1 = {
89 .name = "spipnx",
90 .id = 1,
91 .num_resources = ARRAY_SIZE(spipnx_0_resources),
92 .resource = spipnx_0_resources,
93 .dev = {
94 .coherent_dma_mask = 0xFFFFFFFF,
95 },
96};
97
98static struct platform_device spipnx_2 = {
99 .name = "spipnx",
100 .id = 2,
101 .num_resources = ARRAY_SIZE(spipnx_1_resources),
102 .resource = spipnx_1_resources,
103 .dev = {
104 .coherent_dma_mask = 0xFFFFFFFF,
105 },
106};
107
108static struct plat_serial8250_port platform_serial_ports[] = {
109 {
110 .membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART5_BASE)),
111 .mapbase = (unsigned long)PNX4008_UART5_BASE,
112 .irq = IIR5_INT,
113 .uartclk = PNX4008_UART_CLK,
114 .regshift = 2,
115 .iotype = UPIO_MEM,
116 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST,
117 },
118 {
119 .membase = (void *)__iomem(IO_ADDRESS(PNX4008_UART3_BASE)),
120 .mapbase = (unsigned long)PNX4008_UART3_BASE,
121 .irq = IIR3_INT,
122 .uartclk = PNX4008_UART_CLK,
123 .regshift = 2,
124 .iotype = UPIO_MEM,
125 .flags = UPF_BOOT_AUTOCONF | UPF_BUGGY_UART | UPF_SKIP_TEST,
126 },
127 {}
128};
129
130static struct platform_device serial_device = {
131 .name = "serial8250",
132 .id = PLAT8250_DEV_PLATFORM,
133 .dev = {
134 .platform_data = &platform_serial_ports,
135 },
136};
137
138static struct platform_device *devices[] __initdata = {
139 &spipnx_1,
140 &spipnx_2,
141 &serial_device,
142};
143
144
145extern void pnx4008_uart_init(void);
146
147static void __init pnx4008_init(void)
148{
149 /*disable all START interrupt sources,
150 and clear all START interrupt flags */
151 __raw_writel(0, START_INT_ER_REG(SE_PIN_BASE_INT));
152 __raw_writel(0, START_INT_ER_REG(SE_INT_BASE_INT));
153 __raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
154 __raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));
155
156 platform_add_devices(devices, ARRAY_SIZE(devices));
157 spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
158 /* Switch on the UART clocks */
159 pnx4008_uart_init();
160}
161
162static struct map_desc pnx4008_io_desc[] __initdata = {
163 {
164 .virtual = IO_ADDRESS(PNX4008_IRAM_BASE),
165 .pfn = __phys_to_pfn(PNX4008_IRAM_BASE),
166 .length = SZ_64K,
167 .type = MT_DEVICE,
168 }, {
169 .virtual = IO_ADDRESS(PNX4008_NDF_FLASH_BASE),
170 .pfn = __phys_to_pfn(PNX4008_NDF_FLASH_BASE),
171 .length = SZ_1M - SZ_128K,
172 .type = MT_DEVICE,
173 }, {
174 .virtual = IO_ADDRESS(PNX4008_JPEG_CONFIG_BASE),
175 .pfn = __phys_to_pfn(PNX4008_JPEG_CONFIG_BASE),
176 .length = SZ_128K * 3,
177 .type = MT_DEVICE,
178 }, {
179 .virtual = IO_ADDRESS(PNX4008_DMA_CONFIG_BASE),
180 .pfn = __phys_to_pfn(PNX4008_DMA_CONFIG_BASE),
181 .length = SZ_1M,
182 .type = MT_DEVICE,
183 }, {
184 .virtual = IO_ADDRESS(PNX4008_AHB2FAB_BASE),
185 .pfn = __phys_to_pfn(PNX4008_AHB2FAB_BASE),
186 .length = SZ_1M,
187 .type = MT_DEVICE,
188 },
189};
190
191void __init pnx4008_map_io(void)
192{
193 iotable_init(pnx4008_io_desc, ARRAY_SIZE(pnx4008_io_desc));
194}
195
196extern struct sys_timer pnx4008_timer;
197
198MACHINE_START(PNX4008, "Philips PNX4008")
199 /* Maintainer: MontaVista Software Inc. */
200 .phys_io = 0x40090000,
201 .io_pg_offst = (0xf4090000 >> 18) & 0xfffc,
202 .boot_params = 0x80000100,
203 .map_io = pnx4008_map_io,
204 .init_irq = pnx4008_init_irq,
205 .init_machine = pnx4008_init,
206 .timer = &pnx4008_timer,
207MACHINE_END
diff --git a/arch/arm/mach-pnx4008/dma.c b/arch/arm/mach-pnx4008/dma.c
new file mode 100644
index 000000000000..981aa9dcdede
--- /dev/null
+++ b/arch/arm/mach-pnx4008/dma.c
@@ -0,0 +1,1109 @@
1/*
2 * linux/arch/arm/mach-pnx4008/dma.c
3 *
4 * PNX4008 DMA registration and IRQ dispatching
5 *
6 * Author: Vitaly Wool
7 * Copyright: MontaVista Software Inc. (c) 2005
8 *
9 * Based on the code from Nicolas Pitre
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/kernel.h>
19#include <linux/interrupt.h>
20#include <linux/errno.h>
21#include <linux/err.h>
22#include <linux/dma-mapping.h>
23#include <linux/clk.h>
24
25#include <asm/system.h>
26#include <asm/irq.h>
27#include <asm/hardware.h>
28#include <asm/dma.h>
29#include <asm/dma-mapping.h>
30#include <asm/io.h>
31#include <asm/mach/dma.h>
32#include <asm/arch/clock.h>
33
34static struct dma_channel {
35 char *name;
36 void (*irq_handler) (int, int, void *, struct pt_regs *);
37 void *data;
38 struct pnx4008_dma_ll *ll;
39 u32 ll_dma;
40 void *target_addr;
41 int target_id;
42} dma_channels[MAX_DMA_CHANNELS];
43
44static struct ll_pool {
45 void *vaddr;
46 void *cur;
47 dma_addr_t dma_addr;
48 int count;
49} ll_pool;
50
51static spinlock_t ll_lock = SPIN_LOCK_UNLOCKED;
52
53struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t * ll_dma)
54{
55 struct pnx4008_dma_ll *ll = NULL;
56 unsigned long flags;
57
58 spin_lock_irqsave(&ll_lock, flags);
59 if (ll_pool.count > 4) { /* can give one more */
60 ll = *(struct pnx4008_dma_ll **) ll_pool.cur;
61 *ll_dma = ll_pool.dma_addr + ((void *)ll - ll_pool.vaddr);
62 *(void **)ll_pool.cur = **(void ***)ll_pool.cur;
63 memset(ll, 0, sizeof(*ll));
64 ll_pool.count--;
65 }
66 spin_unlock_irqrestore(&ll_lock, flags);
67
68 return ll;
69}
70
71EXPORT_SYMBOL_GPL(pnx4008_alloc_ll_entry);
72
73void pnx4008_free_ll_entry(struct pnx4008_dma_ll * ll, dma_addr_t ll_dma)
74{
75 unsigned long flags;
76
77 if (ll) {
78 if ((unsigned long)((long)ll - (long)ll_pool.vaddr) > 0x4000) {
79 printk(KERN_ERR "Trying to free entry not allocated by DMA\n");
80 BUG();
81 }
82
83 if (ll->flags & DMA_BUFFER_ALLOCATED)
84 ll->free(ll->alloc_data);
85
86 spin_lock_irqsave(&ll_lock, flags);
87 *(long *)ll = *(long *)ll_pool.cur;
88 *(long *)ll_pool.cur = (long)ll;
89 ll_pool.count++;
90 spin_unlock_irqrestore(&ll_lock, flags);
91 }
92}
93
94EXPORT_SYMBOL_GPL(pnx4008_free_ll_entry);
95
96void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll * ll)
97{
98 struct pnx4008_dma_ll *ptr;
99 u32 dma;
100
101 while (ll) {
102 dma = ll->next_dma;
103 ptr = ll->next;
104 pnx4008_free_ll_entry(ll, ll_dma);
105
106 ll_dma = dma;
107 ll = ptr;
108 }
109}
110
111EXPORT_SYMBOL_GPL(pnx4008_free_ll);
112
113static int dma_channels_requested = 0;
114
115static inline void dma_increment_usage(void)
116{
117 if (!dma_channels_requested++) {
118 struct clk *clk = clk_get(0, "dma_ck");
119 if (!IS_ERR(clk)) {
120 clk_set_rate(clk, 1);
121 clk_put(clk);
122 }
123 pnx4008_config_dma(-1, -1, 1);
124 }
125}
126static inline void dma_decrement_usage(void)
127{
128 if (!--dma_channels_requested) {
129 struct clk *clk = clk_get(0, "dma_ck");
130 if (!IS_ERR(clk)) {
131 clk_set_rate(clk, 0);
132 clk_put(clk);
133 }
134 pnx4008_config_dma(-1, -1, 0);
135
136 }
137}
138
139static spinlock_t dma_lock = SPIN_LOCK_UNLOCKED;
140
141static inline void pnx4008_dma_lock(void)
142{
143 spin_lock_irq(&dma_lock);
144}
145
146static inline void pnx4008_dma_unlock(void)
147{
148 spin_unlock_irq(&dma_lock);
149}
150
151#define VALID_CHANNEL(c) (((c) >= 0) && ((c) < MAX_DMA_CHANNELS))
152
153int pnx4008_request_channel(char *name, int ch,
154 void (*irq_handler) (int, int, void *,
155 struct pt_regs *), void *data)
156{
157 int i, found = 0;
158
159 /* basic sanity checks */
160 if (!name || (ch != -1 && !VALID_CHANNEL(ch)))
161 return -EINVAL;
162
163 pnx4008_dma_lock();
164
165 /* try grabbing a DMA channel with the requested priority */
166 for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
167 if (!dma_channels[i].name && (ch == -1 || ch == i)) {
168 found = 1;
169 break;
170 }
171 }
172
173 if (found) {
174 dma_increment_usage();
175 dma_channels[i].name = name;
176 dma_channels[i].irq_handler = irq_handler;
177 dma_channels[i].data = data;
178 dma_channels[i].ll = NULL;
179 dma_channels[i].ll_dma = 0;
180 } else {
181 printk(KERN_WARNING "No more available DMA channels for %s\n",
182 name);
183 i = -ENODEV;
184 }
185
186 pnx4008_dma_unlock();
187 return i;
188}
189
190EXPORT_SYMBOL_GPL(pnx4008_request_channel);
191
192void pnx4008_free_channel(int ch)
193{
194 if (!dma_channels[ch].name) {
195 printk(KERN_CRIT
196 "%s: trying to free channel %d which is already freed\n",
197 __FUNCTION__, ch);
198 return;
199 }
200
201 pnx4008_dma_lock();
202 pnx4008_free_ll(dma_channels[ch].ll_dma, dma_channels[ch].ll);
203 dma_channels[ch].ll = NULL;
204 dma_decrement_usage();
205
206 dma_channels[ch].name = NULL;
207 pnx4008_dma_unlock();
208}
209
210EXPORT_SYMBOL_GPL(pnx4008_free_channel);
211
212int pnx4008_config_dma(int ahb_m1_be, int ahb_m2_be, int enable)
213{
214 unsigned long dma_cfg = __raw_readl(DMAC_CONFIG);
215
216 switch (ahb_m1_be) {
217 case 0:
218 dma_cfg &= ~(1 << 1);
219 break;
220 case 1:
221 dma_cfg |= (1 << 1);
222 break;
223 default:
224 break;
225 }
226
227 switch (ahb_m2_be) {
228 case 0:
229 dma_cfg &= ~(1 << 2);
230 break;
231 case 1:
232 dma_cfg |= (1 << 2);
233 break;
234 default:
235 break;
236 }
237
238 switch (enable) {
239 case 0:
240 dma_cfg &= ~(1 << 0);
241 break;
242 case 1:
243 dma_cfg |= (1 << 0);
244 break;
245 default:
246 break;
247 }
248
249 pnx4008_dma_lock();
250 __raw_writel(dma_cfg, DMAC_CONFIG);
251 pnx4008_dma_unlock();
252
253 return 0;
254}
255
256EXPORT_SYMBOL_GPL(pnx4008_config_dma);
257
258int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl * ch_ctrl,
259 unsigned long *ctrl)
260{
261 int i = 0, dbsize, sbsize, err = 0;
262
263 if (!ctrl || !ch_ctrl) {
264 err = -EINVAL;
265 goto out;
266 }
267
268 *ctrl = 0;
269
270 switch (ch_ctrl->tc_mask) {
271 case 0:
272 break;
273 case 1:
274 *ctrl |= (1 << 31);
275 break;
276
277 default:
278 err = -EINVAL;
279 goto out;
280 }
281
282 switch (ch_ctrl->cacheable) {
283 case 0:
284 break;
285 case 1:
286 *ctrl |= (1 << 30);
287 break;
288
289 default:
290 err = -EINVAL;
291 goto out;
292 }
293 switch (ch_ctrl->bufferable) {
294 case 0:
295 break;
296 case 1:
297 *ctrl |= (1 << 29);
298 break;
299
300 default:
301 err = -EINVAL;
302 goto out;
303 }
304 switch (ch_ctrl->priv_mode) {
305 case 0:
306 break;
307 case 1:
308 *ctrl |= (1 << 28);
309 break;
310
311 default:
312 err = -EINVAL;
313 goto out;
314 }
315 switch (ch_ctrl->di) {
316 case 0:
317 break;
318 case 1:
319 *ctrl |= (1 << 27);
320 break;
321
322 default:
323 err = -EINVAL;
324 goto out;
325 }
326 switch (ch_ctrl->si) {
327 case 0:
328 break;
329 case 1:
330 *ctrl |= (1 << 26);
331 break;
332
333 default:
334 err = -EINVAL;
335 goto out;
336 }
337 switch (ch_ctrl->dest_ahb1) {
338 case 0:
339 break;
340 case 1:
341 *ctrl |= (1 << 25);
342 break;
343
344 default:
345 err = -EINVAL;
346 goto out;
347 }
348 switch (ch_ctrl->src_ahb1) {
349 case 0:
350 break;
351 case 1:
352 *ctrl |= (1 << 24);
353 break;
354
355 default:
356 err = -EINVAL;
357 goto out;
358 }
359 switch (ch_ctrl->dwidth) {
360 case WIDTH_BYTE:
361 *ctrl &= ~(7 << 21);
362 break;
363 case WIDTH_HWORD:
364 *ctrl &= ~(7 << 21);
365 *ctrl |= (1 << 21);
366 break;
367 case WIDTH_WORD:
368 *ctrl &= ~(7 << 21);
369 *ctrl |= (2 << 21);
370 break;
371
372 default:
373 err = -EINVAL;
374 goto out;
375 }
376 switch (ch_ctrl->swidth) {
377 case WIDTH_BYTE:
378 *ctrl &= ~(7 << 18);
379 break;
380 case WIDTH_HWORD:
381 *ctrl &= ~(7 << 18);
382 *ctrl |= (1 << 18);
383 break;
384 case WIDTH_WORD:
385 *ctrl &= ~(7 << 18);
386 *ctrl |= (2 << 18);
387 break;
388
389 default:
390 err = -EINVAL;
391 goto out;
392 }
393 dbsize = ch_ctrl->dbsize;
394 while (!(dbsize & 1)) {
395 i++;
396 dbsize >>= 1;
397 }
398 if (ch_ctrl->dbsize != 1 || i > 8 || i == 1) {
399 err = -EINVAL;
400 goto out;
401 } else if (i > 1)
402 i--;
403 *ctrl &= ~(7 << 15);
404 *ctrl |= (i << 15);
405
406 sbsize = ch_ctrl->sbsize;
407 while (!(sbsize & 1)) {
408 i++;
409 sbsize >>= 1;
410 }
411 if (ch_ctrl->sbsize != 1 || i > 8 || i == 1) {
412 err = -EINVAL;
413 goto out;
414 } else if (i > 1)
415 i--;
416 *ctrl &= ~(7 << 12);
417 *ctrl |= (i << 12);
418
419 if (ch_ctrl->tr_size > 0x7ff) {
420 err = -E2BIG;
421 goto out;
422 }
423 *ctrl &= ~0x7ff;
424 *ctrl |= ch_ctrl->tr_size & 0x7ff;
425
426out:
427 return err;
428}
429
430EXPORT_SYMBOL_GPL(pnx4008_dma_pack_control);
431
432int pnx4008_dma_parse_control(unsigned long ctrl,
433 struct pnx4008_dma_ch_ctrl * ch_ctrl)
434{
435 int err = 0;
436
437 if (!ch_ctrl) {
438 err = -EINVAL;
439 goto out;
440 }
441
442 ch_ctrl->tr_size = ctrl & 0x7ff;
443 ctrl >>= 12;
444
445 ch_ctrl->sbsize = 1 << (ctrl & 7);
446 if (ch_ctrl->sbsize > 1)
447 ch_ctrl->sbsize <<= 1;
448 ctrl >>= 3;
449
450 ch_ctrl->dbsize = 1 << (ctrl & 7);
451 if (ch_ctrl->dbsize > 1)
452 ch_ctrl->dbsize <<= 1;
453 ctrl >>= 3;
454
455 switch (ctrl & 7) {
456 case 0:
457 ch_ctrl->swidth = WIDTH_BYTE;
458 break;
459 case 1:
460 ch_ctrl->swidth = WIDTH_HWORD;
461 break;
462 case 2:
463 ch_ctrl->swidth = WIDTH_WORD;
464 break;
465 default:
466 err = -EINVAL;
467 goto out;
468 }
469 ctrl >>= 3;
470
471 switch (ctrl & 7) {
472 case 0:
473 ch_ctrl->dwidth = WIDTH_BYTE;
474 break;
475 case 1:
476 ch_ctrl->dwidth = WIDTH_HWORD;
477 break;
478 case 2:
479 ch_ctrl->dwidth = WIDTH_WORD;
480 break;
481 default:
482 err = -EINVAL;
483 goto out;
484 }
485 ctrl >>= 3;
486
487 ch_ctrl->src_ahb1 = ctrl & 1;
488 ctrl >>= 1;
489
490 ch_ctrl->dest_ahb1 = ctrl & 1;
491 ctrl >>= 1;
492
493 ch_ctrl->si = ctrl & 1;
494 ctrl >>= 1;
495
496 ch_ctrl->di = ctrl & 1;
497 ctrl >>= 1;
498
499 ch_ctrl->priv_mode = ctrl & 1;
500 ctrl >>= 1;
501
502 ch_ctrl->bufferable = ctrl & 1;
503 ctrl >>= 1;
504
505 ch_ctrl->cacheable = ctrl & 1;
506 ctrl >>= 1;
507
508 ch_ctrl->tc_mask = ctrl & 1;
509
510out:
511 return err;
512}
513
514EXPORT_SYMBOL_GPL(pnx4008_dma_parse_control);
515
516int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config * ch_cfg,
517 unsigned long *cfg)
518{
519 int err = 0;
520
521 if (!cfg || !ch_cfg) {
522 err = -EINVAL;
523 goto out;
524 }
525
526 *cfg = 0;
527
528 switch (ch_cfg->halt) {
529 case 0:
530 break;
531 case 1:
532 *cfg |= (1 << 18);
533 break;
534
535 default:
536 err = -EINVAL;
537 goto out;
538 }
539 switch (ch_cfg->active) {
540 case 0:
541 break;
542 case 1:
543 *cfg |= (1 << 17);
544 break;
545
546 default:
547 err = -EINVAL;
548 goto out;
549 }
550 switch (ch_cfg->lock) {
551 case 0:
552 break;
553 case 1:
554 *cfg |= (1 << 16);
555 break;
556
557 default:
558 err = -EINVAL;
559 goto out;
560 }
561 switch (ch_cfg->itc) {
562 case 0:
563 break;
564 case 1:
565 *cfg |= (1 << 15);
566 break;
567
568 default:
569 err = -EINVAL;
570 goto out;
571 }
572 switch (ch_cfg->ie) {
573 case 0:
574 break;
575 case 1:
576 *cfg |= (1 << 14);
577 break;
578
579 default:
580 err = -EINVAL;
581 goto out;
582 }
583 switch (ch_cfg->flow_cntrl) {
584 case FC_MEM2MEM_DMA:
585 *cfg &= ~(7 << 11);
586 break;
587 case FC_MEM2PER_DMA:
588 *cfg &= ~(7 << 11);
589 *cfg |= (1 << 11);
590 break;
591 case FC_PER2MEM_DMA:
592 *cfg &= ~(7 << 11);
593 *cfg |= (2 << 11);
594 break;
595 case FC_PER2PER_DMA:
596 *cfg &= ~(7 << 11);
597 *cfg |= (3 << 11);
598 break;
599 case FC_PER2PER_DPER:
600 *cfg &= ~(7 << 11);
601 *cfg |= (4 << 11);
602 break;
603 case FC_MEM2PER_PER:
604 *cfg &= ~(7 << 11);
605 *cfg |= (5 << 11);
606 break;
607 case FC_PER2MEM_PER:
608 *cfg &= ~(7 << 11);
609 *cfg |= (6 << 11);
610 break;
611 case FC_PER2PER_SPER:
612 *cfg |= (7 << 11);
613 break;
614
615 default:
616 err = -EINVAL;
617 goto out;
618 }
619 *cfg &= ~(0x1f << 6);
620 *cfg |= ((ch_cfg->dest_per & 0x1f) << 6);
621
622 *cfg &= ~(0x1f << 1);
623 *cfg |= ((ch_cfg->src_per & 0x1f) << 1);
624
625out:
626 return err;
627}
628
629EXPORT_SYMBOL_GPL(pnx4008_dma_pack_config);
630
631int pnx4008_dma_parse_config(unsigned long cfg,
632 struct pnx4008_dma_ch_config * ch_cfg)
633{
634 int err = 0;
635
636 if (!ch_cfg) {
637 err = -EINVAL;
638 goto out;
639 }
640
641 cfg >>= 1;
642
643 ch_cfg->src_per = cfg & 0x1f;
644 cfg >>= 5;
645
646 ch_cfg->dest_per = cfg & 0x1f;
647 cfg >>= 5;
648
649 switch (cfg & 7) {
650 case 0:
651 ch_cfg->flow_cntrl = FC_MEM2MEM_DMA;
652 break;
653 case 1:
654 ch_cfg->flow_cntrl = FC_MEM2PER_DMA;
655 break;
656 case 2:
657 ch_cfg->flow_cntrl = FC_PER2MEM_DMA;
658 break;
659 case 3:
660 ch_cfg->flow_cntrl = FC_PER2PER_DMA;
661 break;
662 case 4:
663 ch_cfg->flow_cntrl = FC_PER2PER_DPER;
664 break;
665 case 5:
666 ch_cfg->flow_cntrl = FC_MEM2PER_PER;
667 break;
668 case 6:
669 ch_cfg->flow_cntrl = FC_PER2MEM_PER;
670 break;
671 case 7:
672 ch_cfg->flow_cntrl = FC_PER2PER_SPER;
673 }
674 cfg >>= 3;
675
676 ch_cfg->ie = cfg & 1;
677 cfg >>= 1;
678
679 ch_cfg->itc = cfg & 1;
680 cfg >>= 1;
681
682 ch_cfg->lock = cfg & 1;
683 cfg >>= 1;
684
685 ch_cfg->active = cfg & 1;
686 cfg >>= 1;
687
688 ch_cfg->halt = cfg & 1;
689
690out:
691 return err;
692}
693
694EXPORT_SYMBOL_GPL(pnx4008_dma_parse_config);
695
696void pnx4008_dma_split_head_entry(struct pnx4008_dma_config * config,
697 struct pnx4008_dma_ch_ctrl * ctrl)
698{
699 int new_len = ctrl->tr_size, num_entries = 0;
700 int old_len = new_len;
701 int src_width, dest_width, count = 1;
702
703 switch (ctrl->swidth) {
704 case WIDTH_BYTE:
705 src_width = 1;
706 break;
707 case WIDTH_HWORD:
708 src_width = 2;
709 break;
710 case WIDTH_WORD:
711 src_width = 4;
712 break;
713 default:
714 return;
715 }
716
717 switch (ctrl->dwidth) {
718 case WIDTH_BYTE:
719 dest_width = 1;
720 break;
721 case WIDTH_HWORD:
722 dest_width = 2;
723 break;
724 case WIDTH_WORD:
725 dest_width = 4;
726 break;
727 default:
728 return;
729 }
730
731 while (new_len > 0x7FF) {
732 num_entries++;
733 new_len = (ctrl->tr_size + num_entries) / (num_entries + 1);
734 }
735 if (num_entries != 0) {
736 struct pnx4008_dma_ll *ll = NULL;
737 config->ch_ctrl &= ~0x7ff;
738 config->ch_ctrl |= new_len;
739 if (!config->is_ll) {
740 config->is_ll = 1;
741 while (num_entries) {
742 if (!ll) {
743 config->ll =
744 pnx4008_alloc_ll_entry(&config->
745 ll_dma);
746 ll = config->ll;
747 } else {
748 ll->next =
749 pnx4008_alloc_ll_entry(&ll->
750 next_dma);
751 ll = ll->next;
752 }
753
754 if (ctrl->si)
755 ll->src_addr =
756 config->src_addr +
757 src_width * new_len * count;
758 else
759 ll->src_addr = config->src_addr;
760 if (ctrl->di)
761 ll->dest_addr =
762 config->dest_addr +
763 dest_width * new_len * count;
764 else
765 ll->dest_addr = config->dest_addr;
766 ll->ch_ctrl = config->ch_ctrl & 0x7fffffff;
767 ll->next_dma = 0;
768 ll->next = NULL;
769 num_entries--;
770 count++;
771 }
772 } else {
773 struct pnx4008_dma_ll *ll_old = config->ll;
774 unsigned long ll_dma_old = config->ll_dma;
775 while (num_entries) {
776 if (!ll) {
777 config->ll =
778 pnx4008_alloc_ll_entry(&config->
779 ll_dma);
780 ll = config->ll;
781 } else {
782 ll->next =
783 pnx4008_alloc_ll_entry(&ll->
784 next_dma);
785 ll = ll->next;
786 }
787
788 if (ctrl->si)
789 ll->src_addr =
790 config->src_addr +
791 src_width * new_len * count;
792 else
793 ll->src_addr = config->src_addr;
794 if (ctrl->di)
795 ll->dest_addr =
796 config->dest_addr +
797 dest_width * new_len * count;
798 else
799 ll->dest_addr = config->dest_addr;
800 ll->ch_ctrl = config->ch_ctrl & 0x7fffffff;
801 ll->next_dma = 0;
802 ll->next = NULL;
803 num_entries--;
804 count++;
805 }
806 ll->next_dma = ll_dma_old;
807 ll->next = ll_old;
808 }
809 /* adjust last length/tc */
810 ll->ch_ctrl = config->ch_ctrl & (~0x7ff);
811 ll->ch_ctrl |= old_len - new_len * (count - 1);
812 config->ch_ctrl &= 0x7fffffff;
813 }
814}
815
816EXPORT_SYMBOL_GPL(pnx4008_dma_split_head_entry);
817
818void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll * cur_ll,
819 struct pnx4008_dma_ch_ctrl * ctrl)
820{
821 int new_len = ctrl->tr_size, num_entries = 0;
822 int old_len = new_len;
823 int src_width, dest_width, count = 1;
824
825 switch (ctrl->swidth) {
826 case WIDTH_BYTE:
827 src_width = 1;
828 break;
829 case WIDTH_HWORD:
830 src_width = 2;
831 break;
832 case WIDTH_WORD:
833 src_width = 4;
834 break;
835 default:
836 return;
837 }
838
839 switch (ctrl->dwidth) {
840 case WIDTH_BYTE:
841 dest_width = 1;
842 break;
843 case WIDTH_HWORD:
844 dest_width = 2;
845 break;
846 case WIDTH_WORD:
847 dest_width = 4;
848 break;
849 default:
850 return;
851 }
852
853 while (new_len > 0x7FF) {
854 num_entries++;
855 new_len = (ctrl->tr_size + num_entries) / (num_entries + 1);
856 }
857 if (num_entries != 0) {
858 struct pnx4008_dma_ll *ll = NULL;
859 cur_ll->ch_ctrl &= ~0x7ff;
860 cur_ll->ch_ctrl |= new_len;
861 if (!cur_ll->next) {
862 while (num_entries) {
863 if (!ll) {
864 cur_ll->next =
865 pnx4008_alloc_ll_entry(&cur_ll->
866 next_dma);
867 ll = cur_ll->next;
868 } else {
869 ll->next =
870 pnx4008_alloc_ll_entry(&ll->
871 next_dma);
872 ll = ll->next;
873 }
874
875 if (ctrl->si)
876 ll->src_addr =
877 cur_ll->src_addr +
878 src_width * new_len * count;
879 else
880 ll->src_addr = cur_ll->src_addr;
881 if (ctrl->di)
882 ll->dest_addr =
883 cur_ll->dest_addr +
884 dest_width * new_len * count;
885 else
886 ll->dest_addr = cur_ll->dest_addr;
887 ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff;
888 ll->next_dma = 0;
889 ll->next = NULL;
890 num_entries--;
891 count++;
892 }
893 } else {
894 struct pnx4008_dma_ll *ll_old = cur_ll->next;
895 unsigned long ll_dma_old = cur_ll->next_dma;
896 while (num_entries) {
897 if (!ll) {
898 cur_ll->next =
899 pnx4008_alloc_ll_entry(&cur_ll->
900 next_dma);
901 ll = cur_ll->next;
902 } else {
903 ll->next =
904 pnx4008_alloc_ll_entry(&ll->
905 next_dma);
906 ll = ll->next;
907 }
908
909 if (ctrl->si)
910 ll->src_addr =
911 cur_ll->src_addr +
912 src_width * new_len * count;
913 else
914 ll->src_addr = cur_ll->src_addr;
915 if (ctrl->di)
916 ll->dest_addr =
917 cur_ll->dest_addr +
918 dest_width * new_len * count;
919 else
920 ll->dest_addr = cur_ll->dest_addr;
921 ll->ch_ctrl = cur_ll->ch_ctrl & 0x7fffffff;
922 ll->next_dma = 0;
923 ll->next = NULL;
924 num_entries--;
925 count++;
926 }
927
928 ll->next_dma = ll_dma_old;
929 ll->next = ll_old;
930 }
931 /* adjust last length/tc */
932 ll->ch_ctrl = cur_ll->ch_ctrl & (~0x7ff);
933 ll->ch_ctrl |= old_len - new_len * (count - 1);
934 cur_ll->ch_ctrl &= 0x7fffffff;
935 }
936}
937
938EXPORT_SYMBOL_GPL(pnx4008_dma_split_ll_entry);
939
940int pnx4008_config_channel(int ch, struct pnx4008_dma_config * config)
941{
942 if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
943 return -EINVAL;
944
945 pnx4008_dma_lock();
946 __raw_writel(config->src_addr, DMAC_Cx_SRC_ADDR(ch));
947 __raw_writel(config->dest_addr, DMAC_Cx_DEST_ADDR(ch));
948
949 if (config->is_ll)
950 __raw_writel(config->ll_dma, DMAC_Cx_LLI(ch));
951 else
952 __raw_writel(0, DMAC_Cx_LLI(ch));
953
954 __raw_writel(config->ch_ctrl, DMAC_Cx_CONTROL(ch));
955 __raw_writel(config->ch_cfg, DMAC_Cx_CONFIG(ch));
956 pnx4008_dma_unlock();
957
958 return 0;
959
960}
961
962EXPORT_SYMBOL_GPL(pnx4008_config_channel);
963
964int pnx4008_channel_get_config(int ch, struct pnx4008_dma_config * config)
965{
966 if (!VALID_CHANNEL(ch) || !dma_channels[ch].name || !config)
967 return -EINVAL;
968
969 pnx4008_dma_lock();
970 config->ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
971 config->ch_ctrl = __raw_readl(DMAC_Cx_CONTROL(ch));
972
973 config->ll_dma = __raw_readl(DMAC_Cx_LLI(ch));
974 config->is_ll = config->ll_dma ? 1 : 0;
975
976 config->src_addr = __raw_readl(DMAC_Cx_SRC_ADDR(ch));
977 config->dest_addr = __raw_readl(DMAC_Cx_DEST_ADDR(ch));
978 pnx4008_dma_unlock();
979
980 return 0;
981}
982
983EXPORT_SYMBOL_GPL(pnx4008_channel_get_config);
984
985int pnx4008_dma_ch_enable(int ch)
986{
987 unsigned long ch_cfg;
988
989 if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
990 return -EINVAL;
991
992 pnx4008_dma_lock();
993 ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
994 ch_cfg |= 1;
995 __raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch));
996 pnx4008_dma_unlock();
997
998 return 0;
999}
1000
1001EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enable);
1002
1003int pnx4008_dma_ch_disable(int ch)
1004{
1005 unsigned long ch_cfg;
1006
1007 if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
1008 return -EINVAL;
1009
1010 pnx4008_dma_lock();
1011 ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
1012 ch_cfg &= ~1;
1013 __raw_writel(ch_cfg, DMAC_Cx_CONFIG(ch));
1014 pnx4008_dma_unlock();
1015
1016 return 0;
1017}
1018
1019EXPORT_SYMBOL_GPL(pnx4008_dma_ch_disable);
1020
1021int pnx4008_dma_ch_enabled(int ch)
1022{
1023 unsigned long ch_cfg;
1024
1025 if (!VALID_CHANNEL(ch) || !dma_channels[ch].name)
1026 return -EINVAL;
1027
1028 pnx4008_dma_lock();
1029 ch_cfg = __raw_readl(DMAC_Cx_CONFIG(ch));
1030 pnx4008_dma_unlock();
1031
1032 return ch_cfg & 1;
1033}
1034
1035EXPORT_SYMBOL_GPL(pnx4008_dma_ch_enabled);
1036
1037static irqreturn_t dma_irq_handler(int irq, void *dev_id, struct pt_regs *regs)
1038{
1039 int i;
1040 unsigned long dint = __raw_readl(DMAC_INT_STAT);
1041 unsigned long tcint = __raw_readl(DMAC_INT_TC_STAT);
1042 unsigned long eint = __raw_readl(DMAC_INT_ERR_STAT);
1043 unsigned long i_bit;
1044
1045 for (i = MAX_DMA_CHANNELS - 1; i >= 0; i--) {
1046 i_bit = 1 << i;
1047 if (dint & i_bit) {
1048 struct dma_channel *channel = &dma_channels[i];
1049
1050 if (channel->name && channel->irq_handler) {
1051 int cause = 0;
1052
1053 if (eint & i_bit)
1054 cause |= DMA_ERR_INT;
1055 if (tcint & i_bit)
1056 cause |= DMA_TC_INT;
1057 channel->irq_handler(i, cause, channel->data,
1058 regs);
1059 } else {
1060 /*
1061 * IRQ for an unregistered DMA channel
1062 */
1063 printk(KERN_WARNING
1064 "spurious IRQ for DMA channel %d\n", i);
1065 }
1066 if (tcint & i_bit)
1067 __raw_writel(i_bit, DMAC_INT_TC_CLEAR);
1068 if (eint & i_bit)
1069 __raw_writel(i_bit, DMAC_INT_ERR_CLEAR);
1070 }
1071 }
1072 return IRQ_HANDLED;
1073}
1074
1075static int __init pnx4008_dma_init(void)
1076{
1077 int ret, i;
1078
1079 ret = request_irq(DMA_INT, dma_irq_handler, 0, "DMA", NULL);
1080 if (ret) {
1081 printk(KERN_CRIT "Wow! Can't register IRQ for DMA\n");
1082 goto out;
1083 }
1084
1085 ll_pool.count = 0x4000 / sizeof(struct pnx4008_dma_ll);
1086 ll_pool.cur = ll_pool.vaddr =
1087 dma_alloc_coherent(NULL, ll_pool.count * sizeof(struct pnx4008_dma_ll),
1088 &ll_pool.dma_addr, GFP_KERNEL);
1089
1090 if (!ll_pool.vaddr) {
1091 ret = -ENOMEM;
1092 free_irq(DMA_INT, NULL);
1093 goto out;
1094 }
1095
1096 for (i = 0; i < ll_pool.count - 1; i++) {
1097 void **addr = ll_pool.vaddr + i * sizeof(struct pnx4008_dma_ll);
1098 *addr = (void *)addr + sizeof(struct pnx4008_dma_ll);
1099 }
1100 *(long *)(ll_pool.vaddr +
1101 (ll_pool.count - 1) * sizeof(struct pnx4008_dma_ll)) =
1102 (long)ll_pool.vaddr;
1103
1104 __raw_writel(1, DMAC_CONFIG);
1105
1106out:
1107 return ret;
1108}
1109arch_initcall(pnx4008_dma_init);
diff --git a/arch/arm/mach-pnx4008/gpio.c b/arch/arm/mach-pnx4008/gpio.c
new file mode 100644
index 000000000000..e1ce050d8fe0
--- /dev/null
+++ b/arch/arm/mach-pnx4008/gpio.c
@@ -0,0 +1,330 @@
1/*
2 * arch/arm/mach-pnx4008/gpio.c
3 *
4 * PNX4008 GPIO driver
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
9 * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
10 *
11 * 2005 (c) MontaVista Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16
17#include <linux/config.h>
18#include <linux/types.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <asm/semaphore.h>
22#include <asm/io.h>
23#include <asm/arch/platform.h>
24#include <asm/arch/gpio.h>
25
26/* register definitions */
27#define PIO_VA_BASE IO_ADDRESS(PNX4008_PIO_BASE)
28
29#define PIO_INP_STATE (0x00U)
30#define PIO_OUTP_SET (0x04U)
31#define PIO_OUTP_CLR (0x08U)
32#define PIO_OUTP_STATE (0x0CU)
33#define PIO_DRV_SET (0x10U)
34#define PIO_DRV_CLR (0x14U)
35#define PIO_DRV_STATE (0x18U)
36#define PIO_SDINP_STATE (0x1CU)
37#define PIO_SDOUTP_SET (0x20U)
38#define PIO_SDOUTP_CLR (0x24U)
39#define PIO_MUX_SET (0x28U)
40#define PIO_MUX_CLR (0x2CU)
41#define PIO_MUX_STATE (0x30U)
42
43static inline void gpio_lock(void)
44{
45 local_irq_disable();
46}
47
48static inline void gpio_unlock(void)
49{
50 local_irq_enable();
51}
52
53/* Inline functions */
54static inline int gpio_read_bit(u32 reg, int gpio)
55{
56 u32 bit, val;
57 int ret = -EFAULT;
58
59 if (gpio < 0)
60 goto out;
61
62 bit = GPIO_BIT(gpio);
63 if (bit) {
64 val = __raw_readl(PIO_VA_BASE + reg);
65 ret = (val & bit) ? 1 : 0;
66 }
67out:
68 return ret;
69}
70
71static inline int gpio_set_bit(u32 reg, int gpio)
72{
73 u32 bit, val;
74 int ret = -EFAULT;
75
76 if (gpio < 0)
77 goto out;
78
79 bit = GPIO_BIT(gpio);
80 if (bit) {
81 val = __raw_readl(PIO_VA_BASE + reg);
82 val |= bit;
83 __raw_writel(val, PIO_VA_BASE + reg);
84 ret = 0;
85 }
86out:
87 return ret;
88}
89
90/* Very simple access control, bitmap for allocated/free */
91static unsigned long access_map[4];
92#define INP_INDEX 0
93#define OUTP_INDEX 1
94#define GPIO_INDEX 2
95#define MUX_INDEX 3
96
97/*GPIO to Input Mapping */
98static short gpio_to_inp_map[32] = {
99 -1, -1, -1, -1, -1, -1, -1, -1,
100 -1, -1, -1, -1, -1, -1, -1, -1,
101 -1, -1, -1, -1, -1, -1, -1, -1,
102 -1, 10, 11, 12, 13, 14, 24, -1
103};
104
105/*GPIO to Mux Mapping */
106static short gpio_to_mux_map[32] = {
107 -1, -1, -1, -1, -1, -1, -1, -1,
108 -1, -1, -1, -1, -1, -1, -1, -1,
109 -1, -1, -1, -1, -1, -1, -1, -1,
110 -1, -1, -1, 0, 1, 4, 5, -1
111};
112
113/*Output to Mux Mapping */
114static short outp_to_mux_map[32] = {
115 -1, -1, -1, 6, -1, -1, -1, -1,
116 -1, -1, -1, -1, -1, -1, -1, -1,
117 -1, -1, -1, -1, -1, 2, -1, -1,
118 -1, -1, -1, -1, -1, -1, -1, -1
119};
120
121int pnx4008_gpio_register_pin(unsigned short pin)
122{
123 unsigned long bit = GPIO_BIT(pin);
124 int ret = -EBUSY; /* Already in use */
125
126 gpio_lock();
127
128 if (GPIO_ISBID(pin)) {
129 if (access_map[GPIO_INDEX] & bit)
130 goto out;
131 access_map[GPIO_INDEX] |= bit;
132
133 } else if (GPIO_ISRAM(pin)) {
134 if (access_map[GPIO_INDEX] & bit)
135 goto out;
136 access_map[GPIO_INDEX] |= bit;
137
138 } else if (GPIO_ISMUX(pin)) {
139 if (access_map[MUX_INDEX] & bit)
140 goto out;
141 access_map[MUX_INDEX] |= bit;
142
143 } else if (GPIO_ISOUT(pin)) {
144 if (access_map[OUTP_INDEX] & bit)
145 goto out;
146 access_map[OUTP_INDEX] |= bit;
147
148 } else if (GPIO_ISIN(pin)) {
149 if (access_map[INP_INDEX] & bit)
150 goto out;
151 access_map[INP_INDEX] |= bit;
152 } else
153 goto out;
154 ret = 0;
155
156out:
157 gpio_unlock();
158 return ret;
159}
160
161EXPORT_SYMBOL(pnx4008_gpio_register_pin);
162
163int pnx4008_gpio_unregister_pin(unsigned short pin)
164{
165 unsigned long bit = GPIO_BIT(pin);
166 int ret = -EFAULT; /* Not registered */
167
168 gpio_lock();
169
170 if (GPIO_ISBID(pin)) {
171 if (~access_map[GPIO_INDEX] & bit)
172 goto out;
173 access_map[GPIO_INDEX] &= ~bit;
174 } else if (GPIO_ISRAM(pin)) {
175 if (~access_map[GPIO_INDEX] & bit)
176 goto out;
177 access_map[GPIO_INDEX] &= ~bit;
178 } else if (GPIO_ISMUX(pin)) {
179 if (~access_map[MUX_INDEX] & bit)
180 goto out;
181 access_map[MUX_INDEX] &= ~bit;
182 } else if (GPIO_ISOUT(pin)) {
183 if (~access_map[OUTP_INDEX] & bit)
184 goto out;
185 access_map[OUTP_INDEX] &= ~bit;
186 } else if (GPIO_ISIN(pin)) {
187 if (~access_map[INP_INDEX] & bit)
188 goto out;
189 access_map[INP_INDEX] &= ~bit;
190 } else
191 goto out;
192 ret = 0;
193
194out:
195 gpio_unlock();
196 return ret;
197}
198
199EXPORT_SYMBOL(pnx4008_gpio_unregister_pin);
200
201unsigned long pnx4008_gpio_read_pin(unsigned short pin)
202{
203 unsigned long ret = -EFAULT;
204 int gpio = GPIO_BIT_MASK(pin);
205 gpio_lock();
206 if (GPIO_ISOUT(pin)) {
207 ret = gpio_read_bit(PIO_OUTP_STATE, gpio);
208 } else if (GPIO_ISRAM(pin)) {
209 if (gpio_read_bit(PIO_DRV_STATE, gpio) == 0) {
210 ret = gpio_read_bit(PIO_SDINP_STATE, gpio);
211 }
212 } else if (GPIO_ISBID(pin)) {
213 ret = gpio_read_bit(PIO_DRV_STATE, gpio);
214 if (ret > 0)
215 ret = gpio_read_bit(PIO_OUTP_STATE, gpio);
216 else if (ret == 0)
217 ret =
218 gpio_read_bit(PIO_INP_STATE, gpio_to_inp_map[gpio]);
219 } else if (GPIO_ISIN(pin)) {
220 ret = gpio_read_bit(PIO_INP_STATE, gpio);
221 }
222 gpio_unlock();
223 return ret;
224}
225
226EXPORT_SYMBOL(pnx4008_gpio_read_pin);
227
228/* Write Value to output */
229int pnx4008_gpio_write_pin(unsigned short pin, int output)
230{
231 int gpio = GPIO_BIT_MASK(pin);
232 int ret = -EFAULT;
233
234 gpio_lock();
235 if (GPIO_ISOUT(pin)) {
236 printk( "writing '%x' to '%x'\n",
237 gpio, output ? PIO_OUTP_SET : PIO_OUTP_CLR );
238 ret = gpio_set_bit(output ? PIO_OUTP_SET : PIO_OUTP_CLR, gpio);
239 } else if (GPIO_ISRAM(pin)) {
240 if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0)
241 ret = gpio_set_bit(output ? PIO_SDOUTP_SET :
242 PIO_SDOUTP_CLR, gpio);
243 } else if (GPIO_ISBID(pin)) {
244 if (gpio_read_bit(PIO_DRV_STATE, gpio) > 0)
245 ret = gpio_set_bit(output ? PIO_OUTP_SET :
246 PIO_OUTP_CLR, gpio);
247 }
248 gpio_unlock();
249 return ret;
250}
251
252EXPORT_SYMBOL(pnx4008_gpio_write_pin);
253
254/* Value = 1 : Set GPIO pin as output */
255/* Value = 0 : Set GPIO pin as input */
256int pnx4008_gpio_set_pin_direction(unsigned short pin, int output)
257{
258 int gpio = GPIO_BIT_MASK(pin);
259 int ret = -EFAULT;
260
261 gpio_lock();
262 if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) {
263 ret = gpio_set_bit(output ? PIO_DRV_SET : PIO_DRV_CLR, gpio);
264 }
265 gpio_unlock();
266 return ret;
267}
268
269EXPORT_SYMBOL(pnx4008_gpio_set_pin_direction);
270
271/* Read GPIO pin direction: 0= pin used as input, 1= pin used as output*/
272int pnx4008_gpio_read_pin_direction(unsigned short pin)
273{
274 int gpio = GPIO_BIT_MASK(pin);
275 int ret = -EFAULT;
276
277 gpio_lock();
278 if (GPIO_ISBID(pin) || GPIO_ISRAM(pin)) {
279 ret = gpio_read_bit(PIO_DRV_STATE, gpio);
280 }
281 gpio_unlock();
282 return ret;
283}
284
285EXPORT_SYMBOL(pnx4008_gpio_read_pin_direction);
286
287/* Value = 1 : Set pin to muxed function */
288/* Value = 0 : Set pin as GPIO */
289int pnx4008_gpio_set_pin_mux(unsigned short pin, int output)
290{
291 int gpio = GPIO_BIT_MASK(pin);
292 int ret = -EFAULT;
293
294 gpio_lock();
295 if (GPIO_ISBID(pin)) {
296 ret =
297 gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR,
298 gpio_to_mux_map[gpio]);
299 } else if (GPIO_ISOUT(pin)) {
300 ret =
301 gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR,
302 outp_to_mux_map[gpio]);
303 } else if (GPIO_ISMUX(pin)) {
304 ret = gpio_set_bit(output ? PIO_MUX_SET : PIO_MUX_CLR, gpio);
305 }
306 gpio_unlock();
307 return ret;
308}
309
310EXPORT_SYMBOL(pnx4008_gpio_set_pin_mux);
311
312/* Read pin mux function: 0= pin used as GPIO, 1= pin used for muxed function*/
313int pnx4008_gpio_read_pin_mux(unsigned short pin)
314{
315 int gpio = GPIO_BIT_MASK(pin);
316 int ret = -EFAULT;
317
318 gpio_lock();
319 if (GPIO_ISBID(pin)) {
320 ret = gpio_read_bit(PIO_MUX_STATE, gpio_to_mux_map[gpio]);
321 } else if (GPIO_ISOUT(pin)) {
322 ret = gpio_read_bit(PIO_MUX_STATE, outp_to_mux_map[gpio]);
323 } else if (GPIO_ISMUX(pin)) {
324 ret = gpio_read_bit(PIO_MUX_STATE, gpio);
325 }
326 gpio_unlock();
327 return ret;
328}
329
330EXPORT_SYMBOL(pnx4008_gpio_read_pin_mux);
diff --git a/arch/arm/mach-pnx4008/irq.c b/arch/arm/mach-pnx4008/irq.c
new file mode 100644
index 000000000000..9b0a8e084e99
--- /dev/null
+++ b/arch/arm/mach-pnx4008/irq.c
@@ -0,0 +1,121 @@
1/*
2 * arch/arm/mach-pnx4008/irq.c
3 *
4 * PNX4008 IRQ controller driver
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * Based on reference code received from Philips:
9 * Copyright (C) 2003 Philips Semiconductors
10 *
11 * 2005 (c) MontaVista Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16
17#include <linux/kernel.h>
18#include <linux/types.h>
19#include <linux/mm.h>
20#include <linux/interrupt.h>
21#include <linux/list.h>
22#include <linux/init.h>
23#include <linux/ioport.h>
24#include <linux/device.h>
25#include <asm/hardware.h>
26#include <asm/irq.h>
27#include <asm/io.h>
28#include <asm/setup.h>
29#include <asm/mach-types.h>
30#include <asm/pgtable.h>
31#include <asm/page.h>
32#include <asm/system.h>
33#include <asm/mach/arch.h>
34#include <asm/mach/irq.h>
35#include <asm/mach/map.h>
36#include <asm/arch/irq.h>
37
38static u8 pnx4008_irq_type[NR_IRQS] = PNX4008_IRQ_TYPES;
39
40static void pnx4008_mask_irq(unsigned int irq)
41{
42 __raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */
43}
44
45static void pnx4008_unmask_irq(unsigned int irq)
46{
47 __raw_writel(__raw_readl(INTC_ER(irq)) | INTC_BIT(irq), INTC_ER(irq)); /* unmask interrupt */
48}
49
50static void pnx4008_mask_ack_irq(unsigned int irq)
51{
52 __raw_writel(__raw_readl(INTC_ER(irq)) & ~INTC_BIT(irq), INTC_ER(irq)); /* mask interrupt */
53 __raw_writel(INTC_BIT(irq), INTC_SR(irq)); /* clear interrupt status */
54}
55
56static int pnx4008_set_irq_type(unsigned int irq, unsigned int type)
57{
58 switch (type) {
59 case IRQT_RISING:
60 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
61 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /*rising edge */
62 set_irq_handler(irq, do_edge_IRQ);
63 break;
64 case IRQT_FALLING:
65 __raw_writel(__raw_readl(INTC_ATR(irq)) | INTC_BIT(irq), INTC_ATR(irq)); /*edge sensitive */
66 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*falling edge */
67 set_irq_handler(irq, do_edge_IRQ);
68 break;
69 case IRQT_LOW:
70 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
71 __raw_writel(__raw_readl(INTC_APR(irq)) & ~INTC_BIT(irq), INTC_APR(irq)); /*low level */
72 set_irq_handler(irq, do_level_IRQ);
73 break;
74 case IRQT_HIGH:
75 __raw_writel(__raw_readl(INTC_ATR(irq)) & ~INTC_BIT(irq), INTC_ATR(irq)); /*level sensitive */
76 __raw_writel(__raw_readl(INTC_APR(irq)) | INTC_BIT(irq), INTC_APR(irq)); /* high level */
77 set_irq_handler(irq, do_level_IRQ);
78 break;
79
80 /* IRQT_BOTHEDGE is not supported */
81 default:
82 printk(KERN_ERR "PNX4008 IRQ: Unsupported irq type %d\n", type);
83 return -1;
84 }
85 return 0;
86}
87
88static struct irqchip pnx4008_irq_chip = {
89 .ack = pnx4008_mask_ack_irq,
90 .mask = pnx4008_mask_irq,
91 .unmask = pnx4008_unmask_irq,
92 .set_type = pnx4008_set_irq_type,
93};
94
95void __init pnx4008_init_irq(void)
96{
97 unsigned int i;
98
99 /* configure and enable IRQ 0,1,30,31 (cascade interrupts) mask all others */
100 pnx4008_set_irq_type(SUB1_IRQ_N, pnx4008_irq_type[SUB1_IRQ_N]);
101 pnx4008_set_irq_type(SUB2_IRQ_N, pnx4008_irq_type[SUB2_IRQ_N]);
102 pnx4008_set_irq_type(SUB1_FIQ_N, pnx4008_irq_type[SUB1_FIQ_N]);
103 pnx4008_set_irq_type(SUB2_FIQ_N, pnx4008_irq_type[SUB2_FIQ_N]);
104
105 __raw_writel((1 << SUB2_FIQ_N) | (1 << SUB1_FIQ_N) |
106 (1 << SUB2_IRQ_N) | (1 << SUB1_IRQ_N),
107 INTC_ER(MAIN_BASE_INT));
108 __raw_writel(0, INTC_ER(SIC1_BASE_INT));
109 __raw_writel(0, INTC_ER(SIC2_BASE_INT));
110
111 /* configure all other IRQ's */
112 for (i = 0; i < NR_IRQS; i++) {
113 if (i == SUB2_FIQ_N || i == SUB1_FIQ_N ||
114 i == SUB2_IRQ_N || i == SUB1_IRQ_N)
115 continue;
116 set_irq_flags(i, IRQF_VALID);
117 set_irq_chip(i, &pnx4008_irq_chip);
118 pnx4008_set_irq_type(i, pnx4008_irq_type[i]);
119 }
120}
121
diff --git a/arch/arm/mach-pnx4008/pm.c b/arch/arm/mach-pnx4008/pm.c
new file mode 100644
index 000000000000..3649cd3dfc9a
--- /dev/null
+++ b/arch/arm/mach-pnx4008/pm.c
@@ -0,0 +1,184 @@
1/*
2 * arch/arm/mach-pnx4008/pm.c
3 *
4 * Power Management driver for PNX4008
5 *
6 * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#include <linux/pm.h>
15#include <linux/rtc.h>
16#include <linux/sched.h>
17#include <linux/proc_fs.h>
18#include <linux/pm.h>
19#include <linux/delay.h>
20#include <linux/clk.h>
21
22#include <asm/io.h>
23#include <asm/mach-types.h>
24#include <asm/cacheflush.h>
25#include <asm/arch/pm.h>
26#include <asm/arch/clock.h>
27
28#define SRAM_VA IO_ADDRESS(PNX4008_IRAM_BASE)
29
30static void *saved_sram;
31
32static struct clk *pll4_clk;
33
34static inline void pnx4008_standby(void)
35{
36 void (*pnx4008_cpu_standby_ptr) (void);
37
38 local_irq_disable();
39 local_fiq_disable();
40
41 clk_disable(pll4_clk);
42
43 /*saving portion of SRAM to be used by suspend function. */
44 memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_standby_sz);
45
46 /*make sure SRAM copy gets physically written into SDRAM.
47 SDRAM will be placed into self-refresh during power down */
48 flush_cache_all();
49
50 /*copy suspend function into SRAM */
51 memcpy((void *)SRAM_VA, pnx4008_cpu_standby, pnx4008_cpu_standby_sz);
52
53 /*do suspend */
54 pnx4008_cpu_standby_ptr = (void *)SRAM_VA;
55 pnx4008_cpu_standby_ptr();
56
57 /*restoring portion of SRAM that was used by suspend function */
58 memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_standby_sz);
59
60 clk_enable(pll4_clk);
61
62 local_fiq_enable();
63 local_irq_enable();
64}
65
66static inline void pnx4008_suspend(void)
67{
68 void (*pnx4008_cpu_suspend_ptr) (void);
69
70 local_irq_disable();
71 local_fiq_disable();
72
73 clk_disable(pll4_clk);
74
75 __raw_writel(0xffffffff, START_INT_RSR_REG(SE_PIN_BASE_INT));
76 __raw_writel(0xffffffff, START_INT_RSR_REG(SE_INT_BASE_INT));
77
78 /*saving portion of SRAM to be used by suspend function. */
79 memcpy(saved_sram, (void *)SRAM_VA, pnx4008_cpu_suspend_sz);
80
81 /*make sure SRAM copy gets physically written into SDRAM.
82 SDRAM will be placed into self-refresh during power down */
83 flush_cache_all();
84
85 /*copy suspend function into SRAM */
86 memcpy((void *)SRAM_VA, pnx4008_cpu_suspend, pnx4008_cpu_suspend_sz);
87
88 /*do suspend */
89 pnx4008_cpu_suspend_ptr = (void *)SRAM_VA;
90 pnx4008_cpu_suspend_ptr();
91
92 /*restoring portion of SRAM that was used by suspend function */
93 memcpy((void *)SRAM_VA, saved_sram, pnx4008_cpu_suspend_sz);
94
95 clk_enable(pll4_clk);
96
97 local_fiq_enable();
98 local_irq_enable();
99}
100
101static int pnx4008_pm_enter(suspend_state_t state)
102{
103 switch (state) {
104 case PM_SUSPEND_STANDBY:
105 pnx4008_standby();
106 break;
107 case PM_SUSPEND_MEM:
108 pnx4008_suspend();
109 break;
110 case PM_SUSPEND_DISK:
111 return -ENOTSUPP;
112 default:
113 return -EINVAL;
114 }
115 return 0;
116}
117
118/*
119 * Called after processes are frozen, but before we shut down devices.
120 */
121static int pnx4008_pm_prepare(suspend_state_t state)
122{
123 switch (state) {
124 case PM_SUSPEND_STANDBY:
125 case PM_SUSPEND_MEM:
126 break;
127
128 case PM_SUSPEND_DISK:
129 return -ENOTSUPP;
130 break;
131
132 default:
133 return -EINVAL;
134 break;
135 }
136 return 0;
137}
138
139/*
140 * Called after devices are re-setup, but before processes are thawed.
141 */
142static int pnx4008_pm_finish(suspend_state_t state)
143{
144 return 0;
145}
146
147/*
148 * Set to PM_DISK_FIRMWARE so we can quickly veto suspend-to-disk.
149 */
150static struct pm_ops pnx4008_pm_ops = {
151 .prepare = pnx4008_pm_prepare,
152 .enter = pnx4008_pm_enter,
153 .finish = pnx4008_pm_finish,
154};
155
156static int __init pnx4008_pm_init(void)
157{
158 u32 sram_size_to_allocate;
159
160 pll4_clk = clk_get(0, "ck_pll4");
161 if (IS_ERR(pll4_clk)) {
162 printk(KERN_ERR
163 "PM Suspend cannot acquire ARM(PLL4) clock control\n");
164 return PTR_ERR(pll4_clk);
165 }
166
167 if (pnx4008_cpu_standby_sz > pnx4008_cpu_suspend_sz)
168 sram_size_to_allocate = pnx4008_cpu_standby_sz;
169 else
170 sram_size_to_allocate = pnx4008_cpu_suspend_sz;
171
172 saved_sram = kmalloc(sram_size_to_allocate, GFP_ATOMIC);
173 if (!saved_sram) {
174 printk(KERN_ERR
175 "PM Suspend: cannot allocate memory to save portion of SRAM\n");
176 clk_put(pll4_clk);
177 return -ENOMEM;
178 }
179
180 pm_set_ops(&pnx4008_pm_ops);
181 return 0;
182}
183
184late_initcall(pnx4008_pm_init);
diff --git a/arch/arm/mach-pnx4008/serial.c b/arch/arm/mach-pnx4008/serial.c
new file mode 100644
index 000000000000..2e1e04cc048c
--- /dev/null
+++ b/arch/arm/mach-pnx4008/serial.c
@@ -0,0 +1,69 @@
1/*
2 * linux/arch/arm/mach-pnx4008/serial.c
3 *
4 * PNX4008 UART initialization
5 *
6 * Copyright: MontaVista Software Inc. (c) 2005
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15
16#include <asm/io.h>
17
18#include <asm/arch/platform.h>
19#include <asm/arch/hardware.h>
20
21#include <linux/serial_core.h>
22#include <linux/serial_reg.h>
23#include <asm/arch/pm.h>
24
25#include <asm/arch/clock.h>
26
27#define UART_3 0
28#define UART_4 1
29#define UART_5 2
30#define UART_6 3
31#define UART_UNKNOWN (-1)
32
33#define UART3_BASE_VA IO_ADDRESS(PNX4008_UART3_BASE)
34#define UART4_BASE_VA IO_ADDRESS(PNX4008_UART4_BASE)
35#define UART5_BASE_VA IO_ADDRESS(PNX4008_UART5_BASE)
36#define UART6_BASE_VA IO_ADDRESS(PNX4008_UART6_BASE)
37
38#define UART_FCR_OFFSET 8
39#define UART_FIFO_SIZE 64
40
41void pnx4008_uart_init(void)
42{
43 u32 tmp;
44 int i = UART_FIFO_SIZE;
45
46 __raw_writel(0xC1, UART5_BASE_VA + UART_FCR_OFFSET);
47 __raw_writel(0xC1, UART3_BASE_VA + UART_FCR_OFFSET);
48
49 /* Send a NULL to fix the UART HW bug */
50 __raw_writel(0x00, UART5_BASE_VA);
51 __raw_writel(0x00, UART3_BASE_VA);
52
53 while (i--) {
54 tmp = __raw_readl(UART5_BASE_VA);
55 tmp = __raw_readl(UART3_BASE_VA);
56 }
57 __raw_writel(0, UART5_BASE_VA + UART_FCR_OFFSET);
58 __raw_writel(0, UART3_BASE_VA + UART_FCR_OFFSET);
59
60 /* setup wakeup interrupt */
61 start_int_set_rising_edge(SE_U3_RX_INT);
62 start_int_ack(SE_U3_RX_INT);
63 start_int_umask(SE_U3_RX_INT);
64
65 start_int_set_rising_edge(SE_U5_RX_INT);
66 start_int_ack(SE_U5_RX_INT);
67 start_int_umask(SE_U5_RX_INT);
68}
69
diff --git a/arch/arm/mach-pnx4008/sleep.S b/arch/arm/mach-pnx4008/sleep.S
new file mode 100644
index 000000000000..93c802bac269
--- /dev/null
+++ b/arch/arm/mach-pnx4008/sleep.S
@@ -0,0 +1,196 @@
1/*
2 * linux/arch/arm/mach-pnx4008/sleep.S
3 *
4 * PNX4008 support for STOP mode and SDRAM self-refresh
5 *
6 * Authors: Dmitry Chigirev, Vitaly Wool <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#include <linux/config.h>
15#include <linux/linkage.h>
16#include <asm/assembler.h>
17#include <asm/hardware.h>
18
19#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
20#define PWR_CTRL_REG_OFFS 0x44
21
22#define SDRAM_CFG_VA_BASE IO_ADDRESS(PNX4008_SDRAM_CFG_BASE)
23#define MPMC_STATUS_REG_OFFS 0x4
24
25 .text
26
27ENTRY(pnx4008_cpu_suspend)
28 @this function should be entered in Direct run mode.
29
30 @ save registers on stack
31 stmfd sp!, {r0 - r6, lr}
32
33 @ setup Power Manager base address in r4
34 @ and put it's value in r5
35 mov r4, #(PWRMAN_VA_BASE & 0xff000000)
36 orr r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
37 orr r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
38 orr r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
39 ldr r5, [r4, #PWR_CTRL_REG_OFFS]
40
41 @ setup SDRAM controller base address in r2
42 @ and put it's value in r3
43 mov r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
44 orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
45 orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
46 orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
47 ldr r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
48
49 @ clear SDRAM self-refresh bit latch
50 and r5, r5, #(~(1 << 8))
51 @ clear SDRAM self-refresh bit
52 and r5, r5, #(~(1 << 9))
53 str r5, [r4, #PWR_CTRL_REG_OFFS]
54
55 @ do save current bit settings in r1
56 mov r1, r5
57
58 @ set SDRAM self-refresh bit
59 orr r5, r5, #(1 << 9)
60 str r5, [r4, #PWR_CTRL_REG_OFFS]
61
62 @ set SDRAM self-refresh bit latch
63 orr r5, r5, #(1 << 8)
64 str r5, [r4, #PWR_CTRL_REG_OFFS]
65
66 @ clear SDRAM self-refresh bit latch
67 and r5, r5, #(~(1 << 8))
68 str r5, [r4, #PWR_CTRL_REG_OFFS]
69
70 @ clear SDRAM self-refresh bit
71 and r5, r5, #(~(1 << 9))
72 str r5, [r4, #PWR_CTRL_REG_OFFS]
73
74 @ wait for SDRAM to get into self-refresh mode
752: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
76 tst r3, #(1 << 2)
77 beq 2b
78
79 @ to prepare SDRAM to get out of self-refresh mode after wakeup
80 orr r5, r5, #(1 << 7)
81 str r5, [r4, #PWR_CTRL_REG_OFFS]
82
83 @ do enter stop mode
84 orr r5, r5, #(1 << 0)
85 str r5, [r4, #PWR_CTRL_REG_OFFS]
86 nop
87 nop
88 nop
89 nop
90 nop
91 nop
92 nop
93 nop
94 nop
95
96 @ sleeping now...
97
98 @ coming out of STOP mode into Direct Run mode
99 @ clear STOP mode and SDRAM self-refresh bits
100 str r1, [r4, #PWR_CTRL_REG_OFFS]
101
102 @ wait for SDRAM to get out self-refresh mode
1033: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
104 tst r3, #5
105 bne 3b
106
107 @ restore regs and return
108 ldmfd sp!, {r0 - r6, pc}
109
110ENTRY(pnx4008_cpu_suspend_sz)
111 .word . - pnx4008_cpu_suspend
112
113ENTRY(pnx4008_cpu_standby)
114 @ save registers on stack
115 stmfd sp!, {r0 - r6, lr}
116
117 @ setup Power Manager base address in r4
118 @ and put it's value in r5
119 mov r4, #(PWRMAN_VA_BASE & 0xff000000)
120 orr r4, r4, #(PWRMAN_VA_BASE & 0x00ff0000)
121 orr r4, r4, #(PWRMAN_VA_BASE & 0x0000ff00)
122 orr r4, r4, #(PWRMAN_VA_BASE & 0x000000ff)
123 ldr r5, [r4, #PWR_CTRL_REG_OFFS]
124
125 @ setup SDRAM controller base address in r2
126 @ and put it's value in r3
127 mov r2, #(SDRAM_CFG_VA_BASE & 0xff000000)
128 orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x00ff0000)
129 orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x0000ff00)
130 orr r2, r2, #(SDRAM_CFG_VA_BASE & 0x000000ff)
131 ldr r3, [r2, #MPMC_STATUS_REG_OFFS] @extra read - HW bug workaround
132
133 @ clear SDRAM self-refresh bit latch
134 and r5, r5, #(~(1 << 8))
135 @ clear SDRAM self-refresh bit
136 and r5, r5, #(~(1 << 9))
137 str r5, [r4, #PWR_CTRL_REG_OFFS]
138
139 @ do save current bit settings in r1
140 mov r1, r5
141
142 @ set SDRAM self-refresh bit
143 orr r5, r5, #(1 << 9)
144 str r5, [r4, #PWR_CTRL_REG_OFFS]
145
146 @ set SDRAM self-refresh bit latch
147 orr r5, r5, #(1 << 8)
148 str r5, [r4, #PWR_CTRL_REG_OFFS]
149
150 @ clear SDRAM self-refresh bit latch
151 and r5, r5, #(~(1 << 8))
152 str r5, [r4, #PWR_CTRL_REG_OFFS]
153
154 @ clear SDRAM self-refresh bit
155 and r5, r5, #(~(1 << 9))
156 str r5, [r4, #PWR_CTRL_REG_OFFS]
157
158 @ wait for SDRAM to get into self-refresh mode
1592: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
160 tst r3, #(1 << 2)
161 beq 2b
162
163 @ set 'get out of self-refresh mode after wakeup' bit
164 orr r5, r5, #(1 << 7)
165 str r5, [r4, #PWR_CTRL_REG_OFFS]
166
167 mcr p15, 0, r0, c7, c0, 4 @ kinda sleeping now...
168
169 @ set SDRAM self-refresh bit latch
170 orr r5, r5, #(1 << 8)
171 str r5, [r4, #PWR_CTRL_REG_OFFS]
172
173 @ clear SDRAM self-refresh bit latch
174 and r5, r5, #(~(1 << 8))
175 str r5, [r4, #PWR_CTRL_REG_OFFS]
176
177 @ wait for SDRAM to get out self-refresh mode
1783: ldr r3, [r2, #MPMC_STATUS_REG_OFFS]
179 tst r3, #5
180 bne 3b
181
182 @ restore regs and return
183 ldmfd sp!, {r0 - r6, pc}
184
185ENTRY(pnx4008_cpu_standby_sz)
186 .word . - pnx4008_cpu_standby
187
188ENTRY(pnx4008_cache_clean_invalidate)
189 stmfd sp!, {r0 - r6, lr}
190#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
191 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
192#else
1931: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
194 bne 1b
195#endif
196 ldmfd sp!, {r0 - r6, pc}
diff --git a/arch/arm/mach-pnx4008/time.c b/arch/arm/mach-pnx4008/time.c
new file mode 100644
index 000000000000..4ce680698529
--- /dev/null
+++ b/arch/arm/mach-pnx4008/time.c
@@ -0,0 +1,141 @@
1/*
2 * arch/arm/mach-pnx4008/time.c
3 *
4 * PNX4008 Timers
5 *
6 * Authors: Vitaly Wool, Dmitry Chigirev, Grigory Tolstolytkin <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#include <linux/config.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/sched.h>
20#include <linux/spinlock.h>
21#include <linux/module.h>
22#include <linux/kallsyms.h>
23
24#include <asm/system.h>
25#include <asm/hardware.h>
26#include <asm/io.h>
27#include <asm/leds.h>
28#include <asm/irq.h>
29#include <asm/mach/irq.h>
30#include <asm/mach/time.h>
31
32#include <linux/time.h>
33#include <linux/timex.h>
34#include <asm/errno.h>
35
36/*! Note: all timers are UPCOUNTING */
37
38/*!
39 * Returns number of us since last clock interrupt. Note that interrupts
40 * will have been disabled by do_gettimeoffset()
41 */
42static unsigned long pnx4008_gettimeoffset(void)
43{
44 u32 ticks_to_match =
45 __raw_readl(HSTIM_MATCH0) - __raw_readl(HSTIM_COUNTER);
46 u32 elapsed = LATCH - ticks_to_match;
47 return (elapsed * (tick_nsec / 1000)) / LATCH;
48}
49
50/*!
51 * IRQ handler for the timer
52 */
53static irqreturn_t pnx4008_timer_interrupt(int irq, void *dev_id,
54 struct pt_regs *regs)
55{
56 if (__raw_readl(HSTIM_INT) & MATCH0_INT) {
57
58 write_seqlock(&xtime_lock);
59
60 do {
61 timer_tick(regs);
62
63 /*
64 * this algorithm takes care of possible delay
65 * for this interrupt handling longer than a normal
66 * timer period
67 */
68 __raw_writel(__raw_readl(HSTIM_MATCH0) + LATCH,
69 HSTIM_MATCH0);
70 __raw_writel(MATCH0_INT, HSTIM_INT); /* clear interrupt */
71
72 /*
73 * The goal is to keep incrementing HSTIM_MATCH0
74 * register until HSTIM_MATCH0 indicates time after
75 * what HSTIM_COUNTER indicates.
76 */
77 } while ((signed)
78 (__raw_readl(HSTIM_MATCH0) -
79 __raw_readl(HSTIM_COUNTER)) < 0);
80
81 write_sequnlock(&xtime_lock);
82 }
83
84 return IRQ_HANDLED;
85}
86
87static struct irqaction pnx4008_timer_irq = {
88 .name = "PNX4008 Tick Timer",
89 .flags = SA_INTERRUPT | SA_TIMER,
90 .handler = pnx4008_timer_interrupt
91};
92
93/*!
94 * Set up timer and timer interrupt.
95 */
96static __init void pnx4008_setup_timer(void)
97{
98 __raw_writel(RESET_COUNT, MSTIM_CTRL);
99 while (__raw_readl(MSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */
100 __raw_writel(0, MSTIM_CTRL); /* stop the timer */
101 __raw_writel(0, MSTIM_MCTRL);
102
103 __raw_writel(RESET_COUNT, HSTIM_CTRL);
104 while (__raw_readl(HSTIM_COUNTER)) ; /* wait for reset to complete. 100% guarantee event */
105 __raw_writel(0, HSTIM_CTRL);
106 __raw_writel(0, HSTIM_MCTRL);
107 __raw_writel(0, HSTIM_CCR);
108 __raw_writel(12, HSTIM_PMATCH); /* scale down to 1 MHZ */
109 __raw_writel(LATCH, HSTIM_MATCH0);
110 __raw_writel(MR0_INT, HSTIM_MCTRL);
111
112 setup_irq(HSTIMER_INT, &pnx4008_timer_irq);
113
114 __raw_writel(COUNT_ENAB | DEBUG_EN, HSTIM_CTRL); /*start timer, stop when JTAG active */
115}
116
117/* Timer Clock Control in PM register */
118#define TIMCLK_CTRL_REG IO_ADDRESS((PNX4008_PWRMAN_BASE + 0xBC))
119#define WATCHDOG_CLK_EN 1
120#define TIMER_CLK_EN 2 /* HS and MS timers? */
121
122static u32 timclk_ctrl_reg_save;
123
124void pnx4008_timer_suspend(void)
125{
126 timclk_ctrl_reg_save = __raw_readl(TIMCLK_CTRL_REG);
127 __raw_writel(0, TIMCLK_CTRL_REG); /* disable timers */
128}
129
130void pnx4008_timer_resume(void)
131{
132 __raw_writel(timclk_ctrl_reg_save, TIMCLK_CTRL_REG); /* enable timers */
133}
134
135struct sys_timer pnx4008_timer = {
136 .init = pnx4008_setup_timer,
137 .offset = pnx4008_gettimeoffset,
138 .suspend = pnx4008_timer_suspend,
139 .resume = pnx4008_timer_resume,
140};
141
diff --git a/arch/arm/mach-pxa/lubbock.c b/arch/arm/mach-pxa/lubbock.c
index 3e26d7ce5bb2..1ab26c6914f2 100644
--- a/arch/arm/mach-pxa/lubbock.c
+++ b/arch/arm/mach-pxa/lubbock.c
@@ -22,6 +22,10 @@
22#include <linux/mtd/mtd.h> 22#include <linux/mtd/mtd.h>
23#include <linux/mtd/partitions.h> 23#include <linux/mtd/partitions.h>
24 24
25#include <linux/spi/spi.h>
26#include <linux/spi/ads7846.h>
27#include <asm/arch/pxa2xx_spi.h>
28
25#include <asm/setup.h> 29#include <asm/setup.h>
26#include <asm/memory.h> 30#include <asm/memory.h>
27#include <asm/mach-types.h> 31#include <asm/mach-types.h>
@@ -196,6 +200,78 @@ static struct resource smc91x_resources[] = {
196 }, 200 },
197}; 201};
198 202
203/* ADS7846 is connected through SSP ... and if your board has J5 populated,
204 * you can select it to replace the ucb1400 by switching the touchscreen cable
205 * (to J5) and poking board registers (as done below). Else it's only useful
206 * for the temperature sensors.
207 */
208static struct resource pxa_ssp_resources[] = {
209 [0] = {
210 .start = __PREG(SSCR0_P(1)),
211 .end = __PREG(SSCR0_P(1)) + 0x14,
212 .flags = IORESOURCE_MEM,
213 },
214 [1] = {
215 .start = IRQ_SSP,
216 .end = IRQ_SSP,
217 .flags = IORESOURCE_IRQ,
218 },
219};
220
221static struct pxa2xx_spi_master pxa_ssp_master_info = {
222 .ssp_type = PXA25x_SSP,
223 .clock_enable = CKEN3_SSP,
224 .num_chipselect = 0,
225};
226
227static struct platform_device pxa_ssp = {
228 .name = "pxa2xx-spi",
229 .id = 1,
230 .resource = pxa_ssp_resources,
231 .num_resources = ARRAY_SIZE(pxa_ssp_resources),
232 .dev = {
233 .platform_data = &pxa_ssp_master_info,
234 },
235};
236
237static int lubbock_ads7846_pendown_state(void)
238{
239 /* TS_BUSY is bit 8 in LUB_MISC_RD, but pendown is irq-only */
240 return 0;
241}
242
243static struct ads7846_platform_data ads_info = {
244 .model = 7846,
245 .vref_delay_usecs = 100, /* internal, no cap */
246 .get_pendown_state = lubbock_ads7846_pendown_state,
247 // .x_plate_ohms = 500, /* GUESS! */
248 // .y_plate_ohms = 500, /* GUESS! */
249};
250
251static void ads7846_cs(u32 command)
252{
253 static const unsigned TS_nCS = 1 << 11;
254 lubbock_set_misc_wr(TS_nCS, (command == PXA2XX_CS_ASSERT) ? 0 : TS_nCS);
255}
256
257static struct pxa2xx_spi_chip ads_hw = {
258 .tx_threshold = 1,
259 .rx_threshold = 2,
260 .cs_control = ads7846_cs,
261};
262
263static struct spi_board_info spi_board_info[] __initdata = { {
264 .modalias = "ads7846",
265 .platform_data = &ads_info,
266 .controller_data = &ads_hw,
267 .irq = LUBBOCK_BB_IRQ,
268 .max_speed_hz = 120000 /* max sample rate at 3V */
269 * 26 /* command + data + overhead */,
270 .bus_num = 1,
271 .chip_select = 0,
272},
273};
274
199static struct platform_device smc91x_device = { 275static struct platform_device smc91x_device = {
200 .name = "smc91x", 276 .name = "smc91x",
201 .id = -1, 277 .id = -1,
@@ -272,6 +348,7 @@ static struct platform_device *devices[] __initdata = {
272 &smc91x_device, 348 &smc91x_device,
273 &lubbock_flash_device[0], 349 &lubbock_flash_device[0],
274 &lubbock_flash_device[1], 350 &lubbock_flash_device[1],
351 &pxa_ssp,
275}; 352};
276 353
277static struct pxafb_mach_info sharp_lm8v31 __initdata = { 354static struct pxafb_mach_info sharp_lm8v31 __initdata = {
@@ -400,6 +477,8 @@ static void __init lubbock_init(void)
400 lubbock_flash_data[flashboot^1].name = "application-flash"; 477 lubbock_flash_data[flashboot^1].name = "application-flash";
401 lubbock_flash_data[flashboot].name = "boot-rom"; 478 lubbock_flash_data[flashboot].name = "boot-rom";
402 (void) platform_add_devices(devices, ARRAY_SIZE(devices)); 479 (void) platform_add_devices(devices, ARRAY_SIZE(devices));
480
481 spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
403} 482}
404 483
405static struct map_desc lubbock_io_desc[] __initdata = { 484static struct map_desc lubbock_io_desc[] __initdata = {
@@ -416,6 +495,11 @@ static void __init lubbock_map_io(void)
416 pxa_map_io(); 495 pxa_map_io();
417 iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc)); 496 iotable_init(lubbock_io_desc, ARRAY_SIZE(lubbock_io_desc));
418 497
498 /* SSP data pins */
499 pxa_gpio_mode(GPIO23_SCLK_MD);
500 pxa_gpio_mode(GPIO25_STXD_MD);
501 pxa_gpio_mode(GPIO26_SRXD_MD);
502
419 /* This enables the BTUART */ 503 /* This enables the BTUART */
420 pxa_gpio_mode(GPIO42_BTRXD_MD); 504 pxa_gpio_mode(GPIO42_BTRXD_MD);
421 pxa_gpio_mode(GPIO43_BTTXD_MD); 505 pxa_gpio_mode(GPIO43_BTTXD_MD);
diff --git a/arch/arm/mach-s3c2410/Kconfig b/arch/arm/mach-s3c2410/Kconfig
index 970f98dadffc..0c334136db7c 100644
--- a/arch/arm/mach-s3c2410/Kconfig
+++ b/arch/arm/mach-s3c2410/Kconfig
@@ -70,6 +70,18 @@ config ARCH_S3C2440
70 help 70 help
71 Say Y here if you are using the SMDK2440. 71 Say Y here if you are using the SMDK2440.
72 72
73config SMDK2440_CPU2440
74 bool "SMDK2440 with S3C2440 cpu module"
75 depends on ARCH_S3C2440
76 default y if ARCH_S3C2440
77 select CPU_S3C2440
78
79config SMDK2440_CPU2442
80 bool "SMDM2440 with S3C2442 cpu module"
81 depends on ARCH_S3C2440
82 select CPU_S3C2442
83
84
73config MACH_VR1000 85config MACH_VR1000
74 bool "Thorcom VR1000" 86 bool "Thorcom VR1000"
75 select CPU_S3C2410 87 select CPU_S3C2410
@@ -109,12 +121,26 @@ config CPU_S3C2410
109 Support for S3C2410 and S3C2410A family from the S3C24XX line 121 Support for S3C2410 and S3C2410A family from the S3C24XX line
110 of Samsung Mobile CPUs. 122 of Samsung Mobile CPUs.
111 123
124config CPU_S3C244X
125 bool
126 depends on ARCH_S3C2410 && (CPU_S3C2440 || CPU_S3C2442)
127 help
128 Support for S3C2440 and S3C2442 Samsung Mobile CPU based systems.
129
112config CPU_S3C2440 130config CPU_S3C2440
113 bool 131 bool
114 depends on ARCH_S3C2410 132 depends on ARCH_S3C2410
133 select CPU_S3C244X
115 help 134 help
116 Support for S3C2440 Samsung Mobile CPU based systems. 135 Support for S3C2440 Samsung Mobile CPU based systems.
117 136
137config CPU_S3C2442
138 bool
139 depends on ARCH_S3C2420
140 select CPU_S3C244X
141 help
142 Support for S3C2442 Samsung Mobile CPU based systems.
143
118comment "S3C2410 Boot" 144comment "S3C2410 Boot"
119 145
120config S3C2410_BOOT_WATCHDOG 146config S3C2410_BOOT_WATCHDOG
diff --git a/arch/arm/mach-s3c2410/Makefile b/arch/arm/mach-s3c2410/Makefile
index 3e5712db6b52..5e09355cd4f4 100644
--- a/arch/arm/mach-s3c2410/Makefile
+++ b/arch/arm/mach-s3c2410/Makefile
@@ -24,6 +24,11 @@ obj-$(CONFIG_S3C2410_DMA) += dma.o
24obj-$(CONFIG_PM) += pm.o sleep.o 24obj-$(CONFIG_PM) += pm.o sleep.o
25obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o 25obj-$(CONFIG_PM_SIMTEC) += pm-simtec.o
26 26
27# S3C244X support
28
29obj-$(CONFIG_CPU_S3C244X) += s3c244x.o
30obj-$(CONFIG_CPU_S3C244X) += s3c244x-irq.o
31
27# S3C2440 support 32# S3C2440 support
28 33
29obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o 34obj-$(CONFIG_CPU_S3C2440) += s3c2440.o s3c2440-dsc.o
@@ -31,6 +36,11 @@ obj-$(CONFIG_CPU_S3C2440) += s3c2440-irq.o
31obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o 36obj-$(CONFIG_CPU_S3C2440) += s3c2440-clock.o
32obj-$(CONFIG_CPU_S3C2440) += s3c2410-gpio.o 37obj-$(CONFIG_CPU_S3C2440) += s3c2410-gpio.o
33 38
39# S3C2442 support
40
41obj-$(CONFIG_CPU_S3C2442) += s3c2442.o
42obj-$(CONFIG_CPU_S3C2442) += s3c2442-clock.o
43
34# bast extras 44# bast extras
35 45
36obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o 46obj-$(CONFIG_BAST_PC104_IRQ) += bast-irq.o
diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
index 6de713ad319a..99d174612b53 100644
--- a/arch/arm/mach-s3c2410/clock.c
+++ b/arch/arm/mach-s3c2410/clock.c
@@ -70,7 +70,7 @@ void inline s3c24xx_clk_enable(unsigned int clocks, unsigned int enable)
70 clkcon &= ~clocks; 70 clkcon &= ~clocks;
71 71
72 /* ensure none of the special function bits set */ 72 /* ensure none of the special function bits set */
73 clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER); 73 clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER | 3);
74 74
75 __raw_writel(clkcon, S3C2410_CLKCON); 75 __raw_writel(clkcon, S3C2410_CLKCON);
76} 76}
diff --git a/arch/arm/mach-s3c2410/common-smdk.c b/arch/arm/mach-s3c2410/common-smdk.c
index c940890f621f..a40eaa656177 100644
--- a/arch/arm/mach-s3c2410/common-smdk.c
+++ b/arch/arm/mach-s3c2410/common-smdk.c
@@ -34,6 +34,7 @@
34#include <asm/irq.h> 34#include <asm/irq.h>
35 35
36#include <asm/arch/regs-gpio.h> 36#include <asm/arch/regs-gpio.h>
37#include <asm/arch/leds-gpio.h>
37 38
38#include <asm/arch/nand.h> 39#include <asm/arch/nand.h>
39 40
@@ -41,6 +42,66 @@
41#include "devs.h" 42#include "devs.h"
42#include "pm.h" 43#include "pm.h"
43 44
45/* LED devices */
46
47static struct s3c24xx_led_platdata smdk_pdata_led4 = {
48 .gpio = S3C2410_GPF4,
49 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
50 .name = "led4",
51 .def_trigger = "timer",
52};
53
54static struct s3c24xx_led_platdata smdk_pdata_led5 = {
55 .gpio = S3C2410_GPF5,
56 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
57 .name = "led5",
58 .def_trigger = "nand-disk",
59};
60
61static struct s3c24xx_led_platdata smdk_pdata_led6 = {
62 .gpio = S3C2410_GPF6,
63 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
64 .name = "led6",
65};
66
67static struct s3c24xx_led_platdata smdk_pdata_led7 = {
68 .gpio = S3C2410_GPF7,
69 .flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
70 .name = "led7",
71};
72
73static struct platform_device smdk_led4 = {
74 .name = "s3c24xx_led",
75 .id = 0,
76 .dev = {
77 .platform_data = &smdk_pdata_led4,
78 },
79};
80
81static struct platform_device smdk_led5 = {
82 .name = "s3c24xx_led",
83 .id = 1,
84 .dev = {
85 .platform_data = &smdk_pdata_led5,
86 },
87};
88
89static struct platform_device smdk_led6 = {
90 .name = "s3c24xx_led",
91 .id = 2,
92 .dev = {
93 .platform_data = &smdk_pdata_led6,
94 },
95};
96
97static struct platform_device smdk_led7 = {
98 .name = "s3c24xx_led",
99 .id = 3,
100 .dev = {
101 .platform_data = &smdk_pdata_led7,
102 },
103};
104
44/* NAND parititon from 2.4.18-swl5 */ 105/* NAND parititon from 2.4.18-swl5 */
45 106
46static struct mtd_partition smdk_default_nand_part[] = { 107static struct mtd_partition smdk_default_nand_part[] = {
@@ -111,6 +172,10 @@ static struct s3c2410_platform_nand smdk_nand_info = {
111 172
112static struct platform_device __initdata *smdk_devs[] = { 173static struct platform_device __initdata *smdk_devs[] = {
113 &s3c_device_nand, 174 &s3c_device_nand,
175 &smdk_led4,
176 &smdk_led5,
177 &smdk_led6,
178 &smdk_led7,
114}; 179};
115 180
116void __init smdk_machine_init(void) 181void __init smdk_machine_init(void)
diff --git a/arch/arm/mach-s3c2410/cpu.c b/arch/arm/mach-s3c2410/cpu.c
index 70c34fcf7858..52842e6e86e6 100644
--- a/arch/arm/mach-s3c2410/cpu.c
+++ b/arch/arm/mach-s3c2410/cpu.c
@@ -37,12 +37,16 @@
37#include <asm/mach/map.h> 37#include <asm/mach/map.h>
38 38
39#include <asm/arch/regs-gpio.h> 39#include <asm/arch/regs-gpio.h>
40#include <asm/arch/regs-serial.h>
40 41
41#include "cpu.h" 42#include "cpu.h"
43#include "devs.h"
42#include "clock.h" 44#include "clock.h"
43#include "s3c2400.h" 45#include "s3c2400.h"
44#include "s3c2410.h" 46#include "s3c2410.h"
47#include "s3c244x.h"
45#include "s3c2440.h" 48#include "s3c2440.h"
49#include "s3c2442.h"
46 50
47struct cpu_table { 51struct cpu_table {
48 unsigned long idcode; 52 unsigned long idcode;
@@ -59,6 +63,7 @@ struct cpu_table {
59static const char name_s3c2400[] = "S3C2400"; 63static const char name_s3c2400[] = "S3C2400";
60static const char name_s3c2410[] = "S3C2410"; 64static const char name_s3c2410[] = "S3C2410";
61static const char name_s3c2440[] = "S3C2440"; 65static const char name_s3c2440[] = "S3C2440";
66static const char name_s3c2442[] = "S3C2442";
62static const char name_s3c2410a[] = "S3C2410A"; 67static const char name_s3c2410a[] = "S3C2410A";
63static const char name_s3c2440a[] = "S3C2440A"; 68static const char name_s3c2440a[] = "S3C2440A";
64 69
@@ -84,22 +89,31 @@ static struct cpu_table cpu_ids[] __initdata = {
84 { 89 {
85 .idcode = 0x32440000, 90 .idcode = 0x32440000,
86 .idmask = 0xffffffff, 91 .idmask = 0xffffffff,
87 .map_io = s3c2440_map_io, 92 .map_io = s3c244x_map_io,
88 .init_clocks = s3c2440_init_clocks, 93 .init_clocks = s3c244x_init_clocks,
89 .init_uarts = s3c2440_init_uarts, 94 .init_uarts = s3c244x_init_uarts,
90 .init = s3c2440_init, 95 .init = s3c2440_init,
91 .name = name_s3c2440 96 .name = name_s3c2440
92 }, 97 },
93 { 98 {
94 .idcode = 0x32440001, 99 .idcode = 0x32440001,
95 .idmask = 0xffffffff, 100 .idmask = 0xffffffff,
96 .map_io = s3c2440_map_io, 101 .map_io = s3c244x_map_io,
97 .init_clocks = s3c2440_init_clocks, 102 .init_clocks = s3c244x_init_clocks,
98 .init_uarts = s3c2440_init_uarts, 103 .init_uarts = s3c244x_init_uarts,
99 .init = s3c2440_init, 104 .init = s3c2440_init,
100 .name = name_s3c2440a 105 .name = name_s3c2440a
101 }, 106 },
102 { 107 {
108 .idcode = 0x32440aaa,
109 .idmask = 0xffffffff,
110 .map_io = s3c244x_map_io,
111 .init_clocks = s3c244x_init_clocks,
112 .init_uarts = s3c244x_init_uarts,
113 .init = s3c2442_init,
114 .name = name_s3c2442
115 },
116 {
103 .idcode = 0x0, /* S3C2400 doesn't have an idcode */ 117 .idcode = 0x0, /* S3C2400 doesn't have an idcode */
104 .idmask = 0xffffffff, 118 .idmask = 0xffffffff,
105 .map_io = s3c2400_map_io, 119 .map_io = s3c2400_map_io,
@@ -175,13 +189,13 @@ void __init s3c24xx_init_io(struct map_desc *mach_desc, int size)
175 panic("Unknown S3C24XX CPU"); 189 panic("Unknown S3C24XX CPU");
176 } 190 }
177 191
192 printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
193
178 if (cpu->map_io == NULL || cpu->init == NULL) { 194 if (cpu->map_io == NULL || cpu->init == NULL) {
179 printk(KERN_ERR "CPU %s support not enabled\n", cpu->name); 195 printk(KERN_ERR "CPU %s support not enabled\n", cpu->name);
180 panic("Unsupported S3C24XX CPU"); 196 panic("Unsupported S3C24XX CPU");
181 } 197 }
182 198
183 printk("CPU %s (id 0x%08lx)\n", cpu->name, idcode);
184
185 (cpu->map_io)(mach_desc, size); 199 (cpu->map_io)(mach_desc, size);
186} 200}
187 201
@@ -208,6 +222,49 @@ void __init s3c24xx_init_clocks(int xtal)
208 (cpu->init_clocks)(xtal); 222 (cpu->init_clocks)(xtal);
209} 223}
210 224
225/* uart management */
226
227static int nr_uarts __initdata = 0;
228
229static struct s3c2410_uartcfg uart_cfgs[3];
230
231/* s3c24xx_init_uartdevs
232 *
233 * copy the specified platform data and configuration into our central
234 * set of devices, before the data is thrown away after the init process.
235 *
236 * This also fills in the array passed to the serial driver for the
237 * early initialisation of the console.
238*/
239
240void __init s3c24xx_init_uartdevs(char *name,
241 struct s3c24xx_uart_resources *res,
242 struct s3c2410_uartcfg *cfg, int no)
243{
244 struct platform_device *platdev;
245 struct s3c2410_uartcfg *cfgptr = uart_cfgs;
246 struct s3c24xx_uart_resources *resp;
247 int uart;
248
249 memcpy(cfgptr, cfg, sizeof(struct s3c2410_uartcfg) * no);
250
251 for (uart = 0; uart < no; uart++, cfg++, cfgptr++) {
252 platdev = s3c24xx_uart_src[cfgptr->hwport];
253
254 resp = res + cfgptr->hwport;
255
256 s3c24xx_uart_devs[uart] = platdev;
257
258 platdev->name = name;
259 platdev->resource = resp->resources;
260 platdev->num_resources = resp->nr_resources;
261
262 platdev->dev.platform_data = cfgptr;
263 }
264
265 nr_uarts = no;
266}
267
211void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no) 268void __init s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
212{ 269{
213 if (cpu == NULL) 270 if (cpu == NULL)
@@ -232,6 +289,10 @@ static int __init s3c_arch_init(void)
232 if (ret != 0) 289 if (ret != 0)
233 return ret; 290 return ret;
234 291
292 ret = platform_add_devices(s3c24xx_uart_devs, nr_uarts);
293 if (ret != 0)
294 return ret;
295
235 if (board != NULL) { 296 if (board != NULL) {
236 struct platform_device **ptr = board->devices; 297 struct platform_device **ptr = board->devices;
237 int i; 298 int i;
diff --git a/arch/arm/mach-s3c2410/cpu.h b/arch/arm/mach-s3c2410/cpu.h
index fc1067783f6d..40862899b2f1 100644
--- a/arch/arm/mach-s3c2410/cpu.h
+++ b/arch/arm/mach-s3c2410/cpu.h
@@ -31,6 +31,8 @@
31#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000) 31#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000)
32 32
33/* forward declaration */ 33/* forward declaration */
34struct s3c24xx_uart_resources;
35struct platform_device;
34struct s3c2410_uartcfg; 36struct s3c2410_uartcfg;
35struct map_desc; 37struct map_desc;
36 38
@@ -44,6 +46,10 @@ extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
44 46
45extern void s3c24xx_init_clocks(int xtal); 47extern void s3c24xx_init_clocks(int xtal);
46 48
49extern void s3c24xx_init_uartdevs(char *name,
50 struct s3c24xx_uart_resources *res,
51 struct s3c2410_uartcfg *cfg, int no);
52
47/* the board structure is used at first initialsation time 53/* the board structure is used at first initialsation time
48 * to get info such as the devices to register for this 54 * to get info such as the devices to register for this
49 * board. This is done because platfrom_add_devices() cannot 55 * board. This is done because platfrom_add_devices() cannot
@@ -68,3 +74,4 @@ extern struct sys_timer s3c24xx_timer;
68/* system device classes */ 74/* system device classes */
69 75
70extern struct sysdev_class s3c2440_sysclass; 76extern struct sysdev_class s3c2440_sysclass;
77extern struct sysdev_class s3c2442_sysclass;
diff --git a/arch/arm/mach-s3c2410/devs.c b/arch/arm/mach-s3c2410/devs.c
index ca09ba516e4c..ad3845e329ba 100644
--- a/arch/arm/mach-s3c2410/devs.c
+++ b/arch/arm/mach-s3c2410/devs.c
@@ -38,10 +38,86 @@
38#include <asm/arch/regs-serial.h> 38#include <asm/arch/regs-serial.h>
39 39
40#include "devs.h" 40#include "devs.h"
41#include "cpu.h"
41 42
42/* Serial port registrations */ 43/* Serial port registrations */
43 44
44struct platform_device *s3c24xx_uart_devs[3]; 45static struct resource s3c2410_uart0_resource[] = {
46 [0] = {
47 .start = S3C2410_PA_UART0,
48 .end = S3C2410_PA_UART0 + 0x3fff,
49 .flags = IORESOURCE_MEM,
50 },
51 [1] = {
52 .start = IRQ_S3CUART_RX0,
53 .end = IRQ_S3CUART_ERR0,
54 .flags = IORESOURCE_IRQ,
55 }
56};
57
58static struct resource s3c2410_uart1_resource[] = {
59 [0] = {
60 .start = S3C2410_PA_UART1,
61 .end = S3C2410_PA_UART1 + 0x3fff,
62 .flags = IORESOURCE_MEM,
63 },
64 [1] = {
65 .start = IRQ_S3CUART_RX1,
66 .end = IRQ_S3CUART_ERR1,
67 .flags = IORESOURCE_IRQ,
68 }
69};
70
71static struct resource s3c2410_uart2_resource[] = {
72 [0] = {
73 .start = S3C2410_PA_UART2,
74 .end = S3C2410_PA_UART2 + 0x3fff,
75 .flags = IORESOURCE_MEM,
76 },
77 [1] = {
78 .start = IRQ_S3CUART_RX2,
79 .end = IRQ_S3CUART_ERR2,
80 .flags = IORESOURCE_IRQ,
81 }
82};
83
84struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
85 [0] = {
86 .resources = s3c2410_uart0_resource,
87 .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
88 },
89 [1] = {
90 .resources = s3c2410_uart1_resource,
91 .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
92 },
93 [2] = {
94 .resources = s3c2410_uart2_resource,
95 .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
96 },
97};
98
99/* yart devices */
100
101static struct platform_device s3c24xx_uart_device0 = {
102 .id = 0,
103};
104
105static struct platform_device s3c24xx_uart_device1 = {
106 .id = 1,
107};
108
109static struct platform_device s3c24xx_uart_device2 = {
110 .id = 2,
111};
112
113struct platform_device *s3c24xx_uart_src[3] = {
114 &s3c24xx_uart_device0,
115 &s3c24xx_uart_device1,
116 &s3c24xx_uart_device2,
117};
118
119struct platform_device *s3c24xx_uart_devs[3] = {
120};
45 121
46/* USB Host Controller */ 122/* USB Host Controller */
47 123
diff --git a/arch/arm/mach-s3c2410/devs.h b/arch/arm/mach-s3c2410/devs.h
index 52c4bab5c761..fa124ed920e0 100644
--- a/arch/arm/mach-s3c2410/devs.h
+++ b/arch/arm/mach-s3c2410/devs.h
@@ -17,7 +17,15 @@
17#include <linux/config.h> 17#include <linux/config.h>
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19 19
20struct s3c24xx_uart_resources {
21 struct resource *resources;
22 unsigned long nr_resources;
23};
24
25extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
26
20extern struct platform_device *s3c24xx_uart_devs[]; 27extern struct platform_device *s3c24xx_uart_devs[];
28extern struct platform_device *s3c24xx_uart_src[];
21 29
22extern struct platform_device s3c_device_usb; 30extern struct platform_device s3c_device_usb;
23extern struct platform_device s3c_device_lcd; 31extern struct platform_device s3c_device_lcd;
diff --git a/arch/arm/mach-s3c2410/mach-anubis.c b/arch/arm/mach-s3c2410/mach-anubis.c
index cc97fbf66291..52bf718137d4 100644
--- a/arch/arm/mach-s3c2410/mach-anubis.c
+++ b/arch/arm/mach-s3c2410/mach-anubis.c
@@ -131,7 +131,7 @@ static struct s3c24xx_uart_clksrc anubis_serial_clocks[] = {
131}; 131};
132 132
133 133
134static struct s3c2410_uartcfg anubis_uartcfgs[] = { 134static struct s3c2410_uartcfg anubis_uartcfgs[] __initdata = {
135 [0] = { 135 [0] = {
136 .hwport = 0, 136 .hwport = 0,
137 .flags = 0, 137 .flags = 0,
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 995bb8add331..947234df8160 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -208,7 +208,7 @@ static struct s3c24xx_uart_clksrc bast_serial_clocks[] = {
208}; 208};
209 209
210 210
211static struct s3c2410_uartcfg bast_uartcfgs[] = { 211static struct s3c2410_uartcfg bast_uartcfgs[] __initdata = {
212 [0] = { 212 [0] = {
213 .hwport = 0, 213 .hwport = 0,
214 .flags = 0, 214 .flags = 0,
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 646a3a5d33a5..aec431b2830a 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -72,7 +72,7 @@ static struct map_desc h1940_iodesc[] __initdata = {
72#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB 72#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
73#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE 73#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
74 74
75static struct s3c2410_uartcfg h1940_uartcfgs[] = { 75static struct s3c2410_uartcfg h1940_uartcfgs[] __initdata = {
76 [0] = { 76 [0] = {
77 .hwport = 0, 77 .hwport = 0,
78 .flags = 0, 78 .flags = 0,
diff --git a/arch/arm/mach-s3c2410/mach-nexcoder.c b/arch/arm/mach-s3c2410/mach-nexcoder.c
index 07d09509a626..065a1d4e860b 100644
--- a/arch/arm/mach-s3c2410/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2410/mach-nexcoder.c
@@ -51,7 +51,7 @@ static struct map_desc nexcoder_iodesc[] __initdata = {
51#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB 51#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
52#define UFCON S3C2410_UFCON_RXTRIG12 | S3C2410_UFCON_FIFOMODE 52#define UFCON S3C2410_UFCON_RXTRIG12 | S3C2410_UFCON_FIFOMODE
53 53
54static struct s3c2410_uartcfg nexcoder_uartcfgs[] = { 54static struct s3c2410_uartcfg nexcoder_uartcfgs[] __initdata = {
55 [0] = { 55 [0] = {
56 .hwport = 0, 56 .hwport = 0,
57 .flags = 0, 57 .flags = 0,
diff --git a/arch/arm/mach-s3c2410/mach-osiris.c b/arch/arm/mach-s3c2410/mach-osiris.c
index ae0787557751..858fd03c6bc5 100644
--- a/arch/arm/mach-s3c2410/mach-osiris.c
+++ b/arch/arm/mach-s3c2410/mach-osiris.c
@@ -95,8 +95,7 @@ static struct s3c24xx_uart_clksrc osiris_serial_clocks[] = {
95 } 95 }
96}; 96};
97 97
98 98static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
99static struct s3c2410_uartcfg osiris_uartcfgs[] = {
100 [0] = { 99 [0] = {
101 .hwport = 0, 100 .hwport = 0,
102 .flags = 0, 101 .flags = 0,
@@ -107,7 +106,7 @@ static struct s3c2410_uartcfg osiris_uartcfgs[] = {
107 .clocks_size = ARRAY_SIZE(osiris_serial_clocks) 106 .clocks_size = ARRAY_SIZE(osiris_serial_clocks)
108 }, 107 },
109 [1] = { 108 [1] = {
110 .hwport = 2, 109 .hwport = 1,
111 .flags = 0, 110 .flags = 0,
112 .ucon = UCON, 111 .ucon = UCON,
113 .ulcon = ULCON, 112 .ulcon = ULCON,
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c
index b39daedf93ca..c71673fd9955 100644
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c2410/mach-otom.c
@@ -45,7 +45,7 @@ static struct map_desc otom11_iodesc[] __initdata = {
45#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB 45#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
46#define UFCON S3C2410_UFCON_RXTRIG12 | S3C2410_UFCON_FIFOMODE 46#define UFCON S3C2410_UFCON_RXTRIG12 | S3C2410_UFCON_FIFOMODE
47 47
48static struct s3c2410_uartcfg otom11_uartcfgs[] = { 48static struct s3c2410_uartcfg otom11_uartcfgs[] __initdata = {
49 [0] = { 49 [0] = {
50 .hwport = 0, 50 .hwport = 0,
51 .flags = 0, 51 .flags = 0,
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c
index 2db932d72c5a..25f7e9f4dcee 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
@@ -65,7 +65,7 @@ static struct map_desc smdk2410_iodesc[] __initdata = {
65#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB 65#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
66#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE 66#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
67 67
68static struct s3c2410_uartcfg smdk2410_uartcfgs[] = { 68static struct s3c2410_uartcfg smdk2410_uartcfgs[] __initdata = {
69 [0] = { 69 [0] = {
70 .hwport = 0, 70 .hwport = 0,
71 .flags = 0, 71 .flags = 0,
diff --git a/arch/arm/mach-s3c2410/mach-smdk2440.c b/arch/arm/mach-s3c2410/mach-smdk2440.c
index 5fffd1d51047..d661c6b7ff56 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2440.c
@@ -86,7 +86,7 @@ static struct map_desc smdk2440_iodesc[] __initdata = {
86#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB 86#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
87#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE 87#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE
88 88
89static struct s3c2410_uartcfg smdk2440_uartcfgs[] = { 89static struct s3c2410_uartcfg smdk2440_uartcfgs[] __initdata = {
90 [0] = { 90 [0] = {
91 .hwport = 0, 91 .hwport = 0,
92 .flags = 0, 92 .flags = 0,
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 785fc9cdcf7c..d18efb279d3d 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -166,7 +166,7 @@ static struct s3c24xx_uart_clksrc vr1000_serial_clocks[] = {
166 } 166 }
167}; 167};
168 168
169static struct s3c2410_uartcfg vr1000_uartcfgs[] = { 169static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
170 [0] = { 170 [0] = {
171 .hwport = 0, 171 .hwport = 0,
172 .flags = 0, 172 .flags = 0,
diff --git a/arch/arm/mach-s3c2410/pm.c b/arch/arm/mach-s3c2410/pm.c
index fe57d966a34d..43e9a550a203 100644
--- a/arch/arm/mach-s3c2410/pm.c
+++ b/arch/arm/mach-s3c2410/pm.c
@@ -58,7 +58,11 @@ unsigned long s3c_pm_flags;
58 58
59/* cache functions from arch/arm/mm/proc-arm920.S */ 59/* cache functions from arch/arm/mm/proc-arm920.S */
60 60
61#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
61extern void arm920_flush_kern_cache_all(void); 62extern void arm920_flush_kern_cache_all(void);
63#else
64static void arm920_flush_kern_cache_all(void) { }
65#endif
62 66
63#define PFX "s3c24xx-pm: " 67#define PFX "s3c24xx-pm: "
64 68
diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index 0a2013a76549..0852e87a79c4 100644
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -42,6 +42,7 @@
42 42
43#include "s3c2410.h" 43#include "s3c2410.h"
44#include "cpu.h" 44#include "cpu.h"
45#include "devs.h"
45#include "clock.h" 46#include "clock.h"
46 47
47/* Initial IO mappings */ 48/* Initial IO mappings */
@@ -55,93 +56,13 @@ static struct map_desc s3c2410_iodesc[] __initdata = {
55 IODESC_ENT(WATCHDOG), 56 IODESC_ENT(WATCHDOG),
56}; 57};
57 58
58static struct resource s3c_uart0_resource[] = {
59 [0] = {
60 .start = S3C2410_PA_UART0,
61 .end = S3C2410_PA_UART0 + 0x3fff,
62 .flags = IORESOURCE_MEM,
63 },
64 [1] = {
65 .start = IRQ_S3CUART_RX0,
66 .end = IRQ_S3CUART_ERR0,
67 .flags = IORESOURCE_IRQ,
68 }
69
70};
71
72static struct resource s3c_uart1_resource[] = {
73 [0] = {
74 .start = S3C2410_PA_UART1,
75 .end = S3C2410_PA_UART1 + 0x3fff,
76 .flags = IORESOURCE_MEM,
77 },
78 [1] = {
79 .start = IRQ_S3CUART_RX1,
80 .end = IRQ_S3CUART_ERR1,
81 .flags = IORESOURCE_IRQ,
82 }
83};
84
85static struct resource s3c_uart2_resource[] = {
86 [0] = {
87 .start = S3C2410_PA_UART2,
88 .end = S3C2410_PA_UART2 + 0x3fff,
89 .flags = IORESOURCE_MEM,
90 },
91 [1] = {
92 .start = IRQ_S3CUART_RX2,
93 .end = IRQ_S3CUART_ERR2,
94 .flags = IORESOURCE_IRQ,
95 }
96};
97
98/* our uart devices */ 59/* our uart devices */
99 60
100static struct platform_device s3c_uart0 = {
101 .name = "s3c2410-uart",
102 .id = 0,
103 .num_resources = ARRAY_SIZE(s3c_uart0_resource),
104 .resource = s3c_uart0_resource,
105};
106
107
108static struct platform_device s3c_uart1 = {
109 .name = "s3c2410-uart",
110 .id = 1,
111 .num_resources = ARRAY_SIZE(s3c_uart1_resource),
112 .resource = s3c_uart1_resource,
113};
114
115static struct platform_device s3c_uart2 = {
116 .name = "s3c2410-uart",
117 .id = 2,
118 .num_resources = ARRAY_SIZE(s3c_uart2_resource),
119 .resource = s3c_uart2_resource,
120};
121
122static struct platform_device *uart_devices[] __initdata = {
123 &s3c_uart0,
124 &s3c_uart1,
125 &s3c_uart2
126};
127
128static int s3c2410_uart_count = 0;
129
130/* uart registration process */ 61/* uart registration process */
131 62
132void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no) 63void __init s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no)
133{ 64{
134 struct platform_device *platdev; 65 s3c24xx_init_uartdevs("s3c2410-uart", s3c2410_uart_resources, cfg, no);
135 int uart;
136
137 for (uart = 0; uart < no; uart++, cfg++) {
138 platdev = uart_devices[cfg->hwport];
139
140 s3c24xx_uart_devs[uart] = platdev;
141 platdev->dev.platform_data = cfg;
142 }
143
144 s3c2410_uart_count = uart;
145} 66}
146 67
147/* s3c2410_map_io 68/* s3c2410_map_io
@@ -193,5 +114,5 @@ int __init s3c2410_init(void)
193{ 114{
194 printk("S3C2410: Initialising architecture\n"); 115 printk("S3C2410: Initialising architecture\n");
195 116
196 return platform_add_devices(s3c24xx_uart_devs, s3c2410_uart_count); 117 return 0;
197} 118}
diff --git a/arch/arm/mach-s3c2410/s3c2440-irq.c b/arch/arm/mach-s3c2410/s3c2440-irq.c
index 278d0044c85d..acfe3870727b 100644
--- a/arch/arm/mach-s3c2410/s3c2440-irq.c
+++ b/arch/arm/mach-s3c2410/s3c2440-irq.c
@@ -100,73 +100,12 @@ static struct irqchip s3c_irq_wdtac97 = {
100 .ack = s3c_irq_wdtac97_ack, 100 .ack = s3c_irq_wdtac97_ack,
101}; 101};
102 102
103/* camera irq */
104
105static void s3c_irq_demux_cam(unsigned int irq,
106 struct irqdesc *desc,
107 struct pt_regs *regs)
108{
109 unsigned int subsrc, submsk;
110 struct irqdesc *mydesc;
111
112 /* read the current pending interrupts, and the mask
113 * for what it is available */
114
115 subsrc = __raw_readl(S3C2410_SUBSRCPND);
116 submsk = __raw_readl(S3C2410_INTSUBMSK);
117
118 subsrc &= ~submsk;
119 subsrc >>= 11;
120 subsrc &= 3;
121
122 if (subsrc != 0) {
123 if (subsrc & 1) {
124 mydesc = irq_desc + IRQ_S3C2440_CAM_C;
125 desc_handle_irq(IRQ_S3C2440_CAM_C, mydesc, regs);
126 }
127 if (subsrc & 2) {
128 mydesc = irq_desc + IRQ_S3C2440_CAM_P;
129 desc_handle_irq(IRQ_S3C2440_CAM_P, mydesc, regs);
130 }
131 }
132}
133
134#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
135
136static void
137s3c_irq_cam_mask(unsigned int irqno)
138{
139 s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11);
140}
141
142static void
143s3c_irq_cam_unmask(unsigned int irqno)
144{
145 s3c_irqsub_unmask(irqno, INTMSK_CAM);
146}
147
148static void
149s3c_irq_cam_ack(unsigned int irqno)
150{
151 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
152}
153
154static struct irqchip s3c_irq_cam = {
155 .mask = s3c_irq_cam_mask,
156 .unmask = s3c_irq_cam_unmask,
157 .ack = s3c_irq_cam_ack,
158};
159
160static int s3c2440_irq_add(struct sys_device *sysdev) 103static int s3c2440_irq_add(struct sys_device *sysdev)
161{ 104{
162 unsigned int irqno; 105 unsigned int irqno;
163 106
164 printk("S3C2440: IRQ Support\n"); 107 printk("S3C2440: IRQ Support\n");
165 108
166 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
167 set_irq_handler(IRQ_NFCON, do_level_IRQ);
168 set_irq_flags(IRQ_NFCON, IRQF_VALID);
169
170 /* add new chained handler for wdt, ac7 */ 109 /* add new chained handler for wdt, ac7 */
171 110
172 set_irq_chip(IRQ_WDT, &s3c_irq_level_chip); 111 set_irq_chip(IRQ_WDT, &s3c_irq_level_chip);
@@ -179,18 +118,6 @@ static int s3c2440_irq_add(struct sys_device *sysdev)
179 set_irq_flags(irqno, IRQF_VALID); 118 set_irq_flags(irqno, IRQF_VALID);
180 } 119 }
181 120
182 /* add chained handler for camera */
183
184 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
185 set_irq_handler(IRQ_CAM, do_level_IRQ);
186 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
187
188 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
189 set_irq_chip(irqno, &s3c_irq_cam);
190 set_irq_handler(irqno, do_level_IRQ);
191 set_irq_flags(irqno, IRQF_VALID);
192 }
193
194 return 0; 121 return 0;
195} 122}
196 123
@@ -198,10 +125,10 @@ static struct sysdev_driver s3c2440_irq_driver = {
198 .add = s3c2440_irq_add, 125 .add = s3c2440_irq_add,
199}; 126};
200 127
201static int s3c24xx_irq_driver(void) 128static int s3c2440_irq_init(void)
202{ 129{
203 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver); 130 return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_irq_driver);
204} 131}
205 132
206arch_initcall(s3c24xx_irq_driver); 133arch_initcall(s3c2440_irq_init);
207 134
diff --git a/arch/arm/mach-s3c2410/s3c2440.c b/arch/arm/mach-s3c2410/s3c2440.c
index b7fe6d9453fb..0ab50f44f318 100644
--- a/arch/arm/mach-s3c2410/s3c2440.c
+++ b/arch/arm/mach-s3c2410/s3c2440.c
@@ -1,6 +1,6 @@
1/* linux/arch/arm/mach-s3c2410/s3c2440.c 1/* linux/arch/arm/mach-s3c2410/s3c2440.c
2 * 2 *
3 * Copyright (c) 2004-2005 Simtec Electronics 3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 4 * Ben Dooks <ben@simtec.co.uk>
5 * 5 *
6 * Samsung S3C2440 Mobile CPU support 6 * Samsung S3C2440 Mobile CPU support
@@ -8,16 +8,6 @@
8 * This program is free software; you can redistribute it and/or modify 8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 *
12 * Modifications:
13 * 24-Aug-2004 BJD Start of s3c2440 support
14 * 12-Oct-2004 BJD Moved clock info out to clock.c
15 * 01-Nov-2004 BJD Fixed clock build code
16 * 09-Nov-2004 BJD Added sysdev for power management
17 * 04-Nov-2004 BJD New serial registration
18 * 15-Nov-2004 BJD Rename the i2c device for the s3c2440
19 * 14-Jan-2005 BJD Moved clock init code into seperate function
20 * 14-Jan-2005 BJD Removed un-used clock bits
21*/ 11*/
22 12
23#include <linux/kernel.h> 13#include <linux/kernel.h>
@@ -50,234 +40,20 @@
50#include "cpu.h" 40#include "cpu.h"
51#include "pm.h" 41#include "pm.h"
52 42
53
54static struct map_desc s3c2440_iodesc[] __initdata = {
55 IODESC_ENT(USBHOST),
56 IODESC_ENT(CLKPWR),
57 IODESC_ENT(LCD),
58 IODESC_ENT(TIMER),
59 IODESC_ENT(ADC),
60 IODESC_ENT(WATCHDOG),
61};
62
63static struct resource s3c_uart0_resource[] = {
64 [0] = {
65 .start = S3C2410_PA_UART0,
66 .end = S3C2410_PA_UART0 + 0x3fff,
67 .flags = IORESOURCE_MEM,
68 },
69 [1] = {
70 .start = IRQ_S3CUART_RX0,
71 .end = IRQ_S3CUART_ERR0,
72 .flags = IORESOURCE_IRQ,
73 }
74
75};
76
77static struct resource s3c_uart1_resource[] = {
78 [0] = {
79 .start = S3C2410_PA_UART1,
80 .end = S3C2410_PA_UART1 + 0x3fff,
81 .flags = IORESOURCE_MEM,
82 },
83 [1] = {
84 .start = IRQ_S3CUART_RX1,
85 .end = IRQ_S3CUART_ERR1,
86 .flags = IORESOURCE_IRQ,
87 }
88};
89
90static struct resource s3c_uart2_resource[] = {
91 [0] = {
92 .start = S3C2410_PA_UART2,
93 .end = S3C2410_PA_UART2 + 0x3fff,
94 .flags = IORESOURCE_MEM,
95 },
96 [1] = {
97 .start = IRQ_S3CUART_RX2,
98 .end = IRQ_S3CUART_ERR2,
99 .flags = IORESOURCE_IRQ,
100 }
101};
102
103/* our uart devices */
104
105static struct platform_device s3c_uart0 = {
106 .name = "s3c2440-uart",
107 .id = 0,
108 .num_resources = ARRAY_SIZE(s3c_uart0_resource),
109 .resource = s3c_uart0_resource,
110};
111
112static struct platform_device s3c_uart1 = {
113 .name = "s3c2440-uart",
114 .id = 1,
115 .num_resources = ARRAY_SIZE(s3c_uart1_resource),
116 .resource = s3c_uart1_resource,
117};
118
119static struct platform_device s3c_uart2 = {
120 .name = "s3c2440-uart",
121 .id = 2,
122 .num_resources = ARRAY_SIZE(s3c_uart2_resource),
123 .resource = s3c_uart2_resource,
124};
125
126static struct platform_device *uart_devices[] __initdata = {
127 &s3c_uart0,
128 &s3c_uart1,
129 &s3c_uart2
130};
131
132/* uart initialisation */
133
134static int __initdata s3c2440_uart_count;
135
136void __init s3c2440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
137{
138 struct platform_device *platdev;
139 int uart;
140
141 for (uart = 0; uart < no; uart++, cfg++) {
142 platdev = uart_devices[cfg->hwport];
143
144 s3c24xx_uart_devs[uart] = platdev;
145 platdev->dev.platform_data = cfg;
146 }
147
148 s3c2440_uart_count = uart;
149}
150
151
152#ifdef CONFIG_PM
153
154static struct sleep_save s3c2440_sleep[] = {
155 SAVE_ITEM(S3C2440_DSC0),
156 SAVE_ITEM(S3C2440_DSC1),
157 SAVE_ITEM(S3C2440_GPJDAT),
158 SAVE_ITEM(S3C2440_GPJCON),
159 SAVE_ITEM(S3C2440_GPJUP)
160};
161
162static int s3c2440_suspend(struct sys_device *dev, pm_message_t state)
163{
164 s3c2410_pm_do_save(s3c2440_sleep, ARRAY_SIZE(s3c2440_sleep));
165 return 0;
166}
167
168static int s3c2440_resume(struct sys_device *dev)
169{
170 s3c2410_pm_do_restore(s3c2440_sleep, ARRAY_SIZE(s3c2440_sleep));
171 return 0;
172}
173
174#else
175#define s3c2440_suspend NULL
176#define s3c2440_resume NULL
177#endif
178
179struct sysdev_class s3c2440_sysclass = {
180 set_kset_name("s3c2440-core"),
181 .suspend = s3c2440_suspend,
182 .resume = s3c2440_resume
183};
184
185static struct sys_device s3c2440_sysdev = { 43static struct sys_device s3c2440_sysdev = {
186 .cls = &s3c2440_sysclass, 44 .cls = &s3c2440_sysclass,
187}; 45};
188 46
189void __init s3c2440_map_io(struct map_desc *mach_desc, int size) 47int __init s3c2440_init(void)
190{ 48{
191 /* register our io-tables */ 49 printk("S3C2440: Initialising architecture\n");
192
193 iotable_init(s3c2440_iodesc, ARRAY_SIZE(s3c2440_iodesc));
194 iotable_init(mach_desc, size);
195
196 /* rename any peripherals used differing from the s3c2410 */
197
198 s3c_device_i2c.name = "s3c2440-i2c";
199 s3c_device_nand.name = "s3c2440-nand";
200 50
201 /* change irq for watchdog */ 51 /* change irq for watchdog */
202 52
203 s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT; 53 s3c_device_wdt.resource[1].start = IRQ_S3C2440_WDT;
204 s3c_device_wdt.resource[1].end = IRQ_S3C2440_WDT; 54 s3c_device_wdt.resource[1].end = IRQ_S3C2440_WDT;
205}
206
207void __init s3c2440_init_clocks(int xtal)
208{
209 unsigned long clkdiv;
210 unsigned long camdiv;
211 unsigned long hclk, fclk, pclk;
212 int hdiv = 1;
213
214 /* now we've got our machine bits initialised, work out what
215 * clocks we've got */
216
217 fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
218
219 clkdiv = __raw_readl(S3C2410_CLKDIVN);
220 camdiv = __raw_readl(S3C2440_CAMDIVN);
221
222 /* work out clock scalings */
223
224 switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
225 case S3C2440_CLKDIVN_HDIVN_1:
226 hdiv = 1;
227 break;
228
229 case S3C2440_CLKDIVN_HDIVN_2:
230 hdiv = 2;
231 break;
232
233 case S3C2440_CLKDIVN_HDIVN_4_8:
234 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
235 break;
236
237 case S3C2440_CLKDIVN_HDIVN_3_6:
238 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
239 break;
240 }
241
242 hclk = fclk / hdiv;
243 pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);
244
245 /* print brief summary of clocks, etc */
246
247 printk("S3C2440: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
248 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
249
250 /* initialise the clocks here, to allow other things like the
251 * console to use them, and to add new ones after the initialisation
252 */
253
254 s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
255}
256
257/* need to register class before we actually register the device, and
258 * we also need to ensure that it has been initialised before any of the
259 * drivers even try to use it (even if not on an s3c2440 based system)
260 * as a driver which may support both 2410 and 2440 may try and use it.
261*/
262
263static int __init s3c2440_core_init(void)
264{
265 return sysdev_class_register(&s3c2440_sysclass);
266}
267
268core_initcall(s3c2440_core_init);
269
270int __init s3c2440_init(void)
271{
272 int ret;
273
274 printk("S3C2440: Initialising architecture\n");
275 55
276 ret = sysdev_register(&s3c2440_sysdev); 56 /* register our system device for everything else */
277 if (ret != 0)
278 printk(KERN_ERR "failed to register sysdev for s3c2440\n");
279 else
280 ret = platform_add_devices(s3c24xx_uart_devs, s3c2440_uart_count);
281 57
282 return ret; 58 return sysdev_register(&s3c2440_sysdev);
283} 59}
diff --git a/arch/arm/mach-s3c2410/s3c2442-clock.c b/arch/arm/mach-s3c2410/s3c2442-clock.c
new file mode 100644
index 000000000000..5b7b301eb522
--- /dev/null
+++ b/arch/arm/mach-s3c2410/s3c2442-clock.c
@@ -0,0 +1,171 @@
1/* linux/arch/arm/mach-s3c2410/s3c2442-clock.c
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * http://armlinux.simtec.co.uk/
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * S3C2442 Clock support
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/kernel.h>
27#include <linux/list.h>
28#include <linux/errno.h>
29#include <linux/err.h>
30#include <linux/device.h>
31#include <linux/sysdev.h>
32#include <linux/interrupt.h>
33#include <linux/ioport.h>
34#include <linux/mutex.h>
35#include <linux/clk.h>
36
37#include <asm/hardware.h>
38#include <asm/atomic.h>
39#include <asm/irq.h>
40#include <asm/io.h>
41
42#include <asm/arch/regs-clock.h>
43
44#include "clock.h"
45#include "cpu.h"
46
47/* S3C2442 extended clock support */
48
49static unsigned long s3c2442_camif_upll_round(struct clk *clk,
50 unsigned long rate)
51{
52 unsigned long parent_rate = clk_get_rate(clk->parent);
53 int div;
54
55 if (rate > parent_rate)
56 return parent_rate;
57
58 div = parent_rate / rate;
59
60 if (div == 3)
61 return parent_rate / 3;
62
63 /* note, we remove the +/- 1 calculations for the divisor */
64
65 div /= 2;
66
67 if (div < 1)
68 div = 1;
69 else if (div > 16)
70 div = 16;
71
72 return parent_rate / (div * 2);
73}
74
75static int s3c2442_camif_upll_setrate(struct clk *clk, unsigned long rate)
76{
77 unsigned long parent_rate = clk_get_rate(clk->parent);
78 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
79
80 rate = s3c2442_camif_upll_round(clk, rate);
81
82 camdivn &= ~S3C2442_CAMDIVN_CAMCLK_DIV3;
83
84 if (rate == parent_rate) {
85 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_SEL;
86 } else if ((parent_rate / rate) == 3) {
87 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
88 camdivn |= S3C2442_CAMDIVN_CAMCLK_DIV3;
89 } else {
90 camdivn &= ~S3C2440_CAMDIVN_CAMCLK_MASK;
91 camdivn |= S3C2440_CAMDIVN_CAMCLK_SEL;
92 camdivn |= (((parent_rate / rate) / 2) - 1);
93 }
94
95 __raw_writel(camdivn, S3C2440_CAMDIVN);
96
97 return 0;
98}
99
100/* Extra S3C2442 clocks */
101
102static struct clk s3c2442_clk_cam = {
103 .name = "camif",
104 .id = -1,
105 .enable = s3c24xx_clkcon_enable,
106 .ctrlbit = S3C2440_CLKCON_CAMERA,
107};
108
109static struct clk s3c2442_clk_cam_upll = {
110 .name = "camif-upll",
111 .id = -1,
112 .set_rate = s3c2442_camif_upll_setrate,
113 .round_rate = s3c2442_camif_upll_round,
114};
115
116static int s3c2442_clk_add(struct sys_device *sysdev)
117{
118 unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
119 unsigned long clkdivn;
120 struct clk *clk_h;
121 struct clk *clk_p;
122 struct clk *clk_upll;
123
124 printk("S3C2442: Clock Support, DVS %s\n",
125 (camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
126
127 clk_p = clk_get(NULL, "pclk");
128 clk_h = clk_get(NULL, "hclk");
129 clk_upll = clk_get(NULL, "upll");
130
131 if (IS_ERR(clk_p) || IS_ERR(clk_h) || IS_ERR(clk_upll)) {
132 printk(KERN_ERR "S3C2442: Failed to get parent clocks\n");
133 return -EINVAL;
134 }
135
136 /* check rate of UPLL, and if it is near 96MHz, then change
137 * to using half the UPLL rate for the system */
138
139 if (clk_get_rate(clk_upll) > (94 * MHZ)) {
140 clk_usb_bus.rate = clk_get_rate(clk_upll) / 2;
141
142 mutex_lock(&clocks_mutex);
143
144 clkdivn = __raw_readl(S3C2410_CLKDIVN);
145 clkdivn |= S3C2440_CLKDIVN_UCLK;
146 __raw_writel(clkdivn, S3C2410_CLKDIVN);
147
148 mutex_unlock(&clocks_mutex);
149 }
150
151 s3c2442_clk_cam.parent = clk_h;
152 s3c2442_clk_cam_upll.parent = clk_upll;
153
154 s3c24xx_register_clock(&s3c2442_clk_cam);
155 s3c24xx_register_clock(&s3c2442_clk_cam_upll);
156
157 clk_disable(&s3c2442_clk_cam);
158
159 return 0;
160}
161
162static struct sysdev_driver s3c2442_clk_driver = {
163 .add = s3c2442_clk_add,
164};
165
166static __init int s3c2442_clk_init(void)
167{
168 return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
169}
170
171arch_initcall(s3c2442_clk_init);
diff --git a/arch/arm/mach-s3c2410/s3c2442.c b/arch/arm/mach-s3c2410/s3c2442.c
new file mode 100644
index 000000000000..debae2430557
--- /dev/null
+++ b/arch/arm/mach-s3c2410/s3c2442.c
@@ -0,0 +1,52 @@
1/* linux/arch/arm/mach-s3c2410/s3c2440.c
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2442 Mobile CPU support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/platform_device.h>
20#include <linux/sysdev.h>
21#include <linux/clk.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26
27#include <asm/hardware.h>
28#include <asm/io.h>
29#include <asm/irq.h>
30
31#include <asm/arch/regs-clock.h>
32#include <asm/arch/regs-serial.h>
33#include <asm/arch/regs-gpio.h>
34#include <asm/arch/regs-gpioj.h>
35#include <asm/arch/regs-dsc.h>
36
37#include "s3c2442.h"
38#include "clock.h"
39#include "devs.h"
40#include "cpu.h"
41#include "pm.h"
42
43static struct sys_device s3c2442_sysdev = {
44 .cls = &s3c2442_sysclass,
45};
46
47int __init s3c2442_init(void)
48{
49 printk("S3C2442: Initialising architecture\n");
50
51 return sysdev_register(&s3c2442_sysdev);
52}
diff --git a/arch/arm/mach-s3c2410/s3c2442.h b/arch/arm/mach-s3c2410/s3c2442.h
new file mode 100644
index 000000000000..0ae37d24866c
--- /dev/null
+++ b/arch/arm/mach-s3c2410/s3c2442.h
@@ -0,0 +1,17 @@
1/* arch/arm/mach-s3c2410/s3c2442.h
2 *
3 * Copyright (c) 2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for s3c2442 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifdef CONFIG_CPU_S3C2442
14extern int s3c2442_init(void);
15#else
16#define s3c2442_init NULL
17#endif
diff --git a/arch/arm/mach-s3c2410/s3c244x-irq.c b/arch/arm/mach-s3c2410/s3c244x-irq.c
new file mode 100644
index 000000000000..2aadca1ce7eb
--- /dev/null
+++ b/arch/arm/mach-s3c2410/s3c244x-irq.c
@@ -0,0 +1,142 @@
1/* linux/arch/arm/mach-s3c2410/s3c2440-irq.c
2 *
3 * Copyright (c) 2003,2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * Changelog:
21 * 25-Jul-2005 BJD Split from irq.c
22 *
23*/
24
25#include <linux/init.h>
26#include <linux/module.h>
27#include <linux/interrupt.h>
28#include <linux/ioport.h>
29#include <linux/ptrace.h>
30#include <linux/sysdev.h>
31
32#include <asm/hardware.h>
33#include <asm/irq.h>
34#include <asm/io.h>
35
36#include <asm/mach/irq.h>
37
38#include <asm/arch/regs-irq.h>
39#include <asm/arch/regs-gpio.h>
40
41#include "cpu.h"
42#include "pm.h"
43#include "irq.h"
44
45/* camera irq */
46
47static void s3c_irq_demux_cam(unsigned int irq,
48 struct irqdesc *desc,
49 struct pt_regs *regs)
50{
51 unsigned int subsrc, submsk;
52 struct irqdesc *mydesc;
53
54 /* read the current pending interrupts, and the mask
55 * for what it is available */
56
57 subsrc = __raw_readl(S3C2410_SUBSRCPND);
58 submsk = __raw_readl(S3C2410_INTSUBMSK);
59
60 subsrc &= ~submsk;
61 subsrc >>= 11;
62 subsrc &= 3;
63
64 if (subsrc != 0) {
65 if (subsrc & 1) {
66 mydesc = irq_desc + IRQ_S3C2440_CAM_C;
67 desc_handle_irq(IRQ_S3C2440_CAM_C, mydesc, regs);
68 }
69 if (subsrc & 2) {
70 mydesc = irq_desc + IRQ_S3C2440_CAM_P;
71 desc_handle_irq(IRQ_S3C2440_CAM_P, mydesc, regs);
72 }
73 }
74}
75
76#define INTMSK_CAM (1UL << (IRQ_CAM - IRQ_EINT0))
77
78static void
79s3c_irq_cam_mask(unsigned int irqno)
80{
81 s3c_irqsub_mask(irqno, INTMSK_CAM, 3<<11);
82}
83
84static void
85s3c_irq_cam_unmask(unsigned int irqno)
86{
87 s3c_irqsub_unmask(irqno, INTMSK_CAM);
88}
89
90static void
91s3c_irq_cam_ack(unsigned int irqno)
92{
93 s3c_irqsub_maskack(irqno, INTMSK_CAM, 3<<11);
94}
95
96static struct irqchip s3c_irq_cam = {
97 .mask = s3c_irq_cam_mask,
98 .unmask = s3c_irq_cam_unmask,
99 .ack = s3c_irq_cam_ack,
100};
101
102static int s3c244x_irq_add(struct sys_device *sysdev)
103{
104 unsigned int irqno;
105
106 set_irq_chip(IRQ_NFCON, &s3c_irq_level_chip);
107 set_irq_handler(IRQ_NFCON, do_level_IRQ);
108 set_irq_flags(IRQ_NFCON, IRQF_VALID);
109
110 /* add chained handler for camera */
111
112 set_irq_chip(IRQ_CAM, &s3c_irq_level_chip);
113 set_irq_handler(IRQ_CAM, do_level_IRQ);
114 set_irq_chained_handler(IRQ_CAM, s3c_irq_demux_cam);
115
116 for (irqno = IRQ_S3C2440_CAM_C; irqno <= IRQ_S3C2440_CAM_P; irqno++) {
117 set_irq_chip(irqno, &s3c_irq_cam);
118 set_irq_handler(irqno, do_level_IRQ);
119 set_irq_flags(irqno, IRQF_VALID);
120 }
121
122 return 0;
123}
124
125static struct sysdev_driver s3c244x_irq_driver = {
126 .add = s3c244x_irq_add,
127};
128
129static int s3c2440_irq_init(void)
130{
131 return sysdev_driver_register(&s3c2440_sysclass, &s3c244x_irq_driver);
132}
133
134arch_initcall(s3c2440_irq_init);
135
136
137static int s3c2442_irq_init(void)
138{
139 return sysdev_driver_register(&s3c2442_sysclass, &s3c244x_irq_driver);
140}
141
142arch_initcall(s3c2442_irq_init);
diff --git a/arch/arm/mach-s3c2410/s3c244x.c b/arch/arm/mach-s3c2410/s3c244x.c
new file mode 100644
index 000000000000..96852a7000db
--- /dev/null
+++ b/arch/arm/mach-s3c2410/s3c244x.c
@@ -0,0 +1,182 @@
1/* linux/arch/arm/mach-s3c2410/s3c244x.c
2 *
3 * Copyright (c) 2004-2006 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Samsung S3C2440 and S3C2442 Mobile CPU support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/interrupt.h>
16#include <linux/list.h>
17#include <linux/timer.h>
18#include <linux/init.h>
19#include <linux/platform_device.h>
20#include <linux/sysdev.h>
21#include <linux/clk.h>
22
23#include <asm/mach/arch.h>
24#include <asm/mach/map.h>
25#include <asm/mach/irq.h>
26
27#include <asm/hardware.h>
28#include <asm/io.h>
29#include <asm/irq.h>
30
31#include <asm/arch/regs-clock.h>
32#include <asm/arch/regs-serial.h>
33#include <asm/arch/regs-gpio.h>
34#include <asm/arch/regs-gpioj.h>
35#include <asm/arch/regs-dsc.h>
36
37#include "s3c2440.h"
38#include "s3c244x.h"
39#include "clock.h"
40#include "devs.h"
41#include "cpu.h"
42#include "pm.h"
43
44static struct map_desc s3c244x_iodesc[] __initdata = {
45 IODESC_ENT(CLKPWR),
46 IODESC_ENT(TIMER),
47 IODESC_ENT(WATCHDOG),
48 IODESC_ENT(LCD),
49 IODESC_ENT(ADC),
50 IODESC_ENT(USBHOST),
51};
52
53/* uart initialisation */
54
55void __init s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no)
56{
57 s3c24xx_init_uartdevs("s3c2440-uart", s3c2410_uart_resources, cfg, no);
58}
59
60void __init s3c244x_map_io(struct map_desc *mach_desc, int size)
61{
62 /* register our io-tables */
63
64 iotable_init(s3c244x_iodesc, ARRAY_SIZE(s3c244x_iodesc));
65 iotable_init(mach_desc, size);
66
67 /* rename any peripherals used differing from the s3c2410 */
68
69 s3c_device_i2c.name = "s3c2440-i2c";
70 s3c_device_nand.name = "s3c2440-nand";
71}
72
73void __init s3c244x_init_clocks(int xtal)
74{
75 unsigned long clkdiv;
76 unsigned long camdiv;
77 unsigned long hclk, fclk, pclk;
78 int hdiv = 1;
79
80 /* now we've got our machine bits initialised, work out what
81 * clocks we've got */
82
83 fclk = s3c2410_get_pll(__raw_readl(S3C2410_MPLLCON), xtal) * 2;
84
85 clkdiv = __raw_readl(S3C2410_CLKDIVN);
86 camdiv = __raw_readl(S3C2440_CAMDIVN);
87
88 /* work out clock scalings */
89
90 switch (clkdiv & S3C2440_CLKDIVN_HDIVN_MASK) {
91 case S3C2440_CLKDIVN_HDIVN_1:
92 hdiv = 1;
93 break;
94
95 case S3C2440_CLKDIVN_HDIVN_2:
96 hdiv = 2;
97 break;
98
99 case S3C2440_CLKDIVN_HDIVN_4_8:
100 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK4_HALF) ? 8 : 4;
101 break;
102
103 case S3C2440_CLKDIVN_HDIVN_3_6:
104 hdiv = (camdiv & S3C2440_CAMDIVN_HCLK3_HALF) ? 6 : 3;
105 break;
106 }
107
108 hclk = fclk / hdiv;
109 pclk = hclk / ((clkdiv & S3C2440_CLKDIVN_PDIVN)? 2:1);
110
111 /* print brief summary of clocks, etc */
112
113 printk("S3C244X: core %ld.%03ld MHz, memory %ld.%03ld MHz, peripheral %ld.%03ld MHz\n",
114 print_mhz(fclk), print_mhz(hclk), print_mhz(pclk));
115
116 /* initialise the clocks here, to allow other things like the
117 * console to use them, and to add new ones after the initialisation
118 */
119
120 s3c24xx_setup_clocks(xtal, fclk, hclk, pclk);
121}
122
123#ifdef CONFIG_PM
124
125static struct sleep_save s3c244x_sleep[] = {
126 SAVE_ITEM(S3C2440_DSC0),
127 SAVE_ITEM(S3C2440_DSC1),
128 SAVE_ITEM(S3C2440_GPJDAT),
129 SAVE_ITEM(S3C2440_GPJCON),
130 SAVE_ITEM(S3C2440_GPJUP)
131};
132
133static int s3c244x_suspend(struct sys_device *dev, pm_message_t state)
134{
135 s3c2410_pm_do_save(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
136 return 0;
137}
138
139static int s3c244x_resume(struct sys_device *dev)
140{
141 s3c2410_pm_do_restore(s3c244x_sleep, ARRAY_SIZE(s3c244x_sleep));
142 return 0;
143}
144
145#else
146#define s3c244x_suspend NULL
147#define s3c244x_resume NULL
148#endif
149
150/* Since the S3C2442 and S3C2440 share items, put both sysclasses here */
151
152struct sysdev_class s3c2440_sysclass = {
153 set_kset_name("s3c2440-core"),
154 .suspend = s3c244x_suspend,
155 .resume = s3c244x_resume
156};
157
158struct sysdev_class s3c2442_sysclass = {
159 set_kset_name("s3c2442-core"),
160 .suspend = s3c244x_suspend,
161 .resume = s3c244x_resume
162};
163
164/* need to register class before we actually register the device, and
165 * we also need to ensure that it has been initialised before any of the
166 * drivers even try to use it (even if not on an s3c2440 based system)
167 * as a driver which may support both 2410 and 2440 may try and use it.
168*/
169
170static int __init s3c2440_core_init(void)
171{
172 return sysdev_class_register(&s3c2440_sysclass);
173}
174
175core_initcall(s3c2440_core_init);
176
177static int __init s3c2442_core_init(void)
178{
179 return sysdev_class_register(&s3c2442_sysclass);
180}
181
182core_initcall(s3c2442_core_init);
diff --git a/arch/arm/mach-s3c2410/s3c244x.h b/arch/arm/mach-s3c2410/s3c244x.h
new file mode 100644
index 000000000000..3e7f5f75134d
--- /dev/null
+++ b/arch/arm/mach-s3c2410/s3c244x.h
@@ -0,0 +1,25 @@
1/* arch/arm/mach-s3c2410/s3c2440.h
2 *
3 * Copyright (c) 2004-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Header file for S3C2440 and S3C2442 cpu support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
14
15extern void s3c244x_map_io(struct map_desc *mach_desc, int size);
16
17extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
18
19extern void s3c244x_init_clocks(int xtal);
20
21#else
22#define s3c244x_init_clocks NULL
23#define s3c244x_init_uarts NULL
24#define s3c244x_map_io NULL
25#endif
diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
index 73de2eaca22a..5f6761ed96b2 100644
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c2410/sleep.S
@@ -66,7 +66,9 @@ ENTRY(s3c2410_cpu_suspend)
66 @@ flush the caches to ensure everything is back out to 66 @@ flush the caches to ensure everything is back out to
67 @@ SDRAM before the core powers down 67 @@ SDRAM before the core powers down
68 68
69#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
69 bl arm920_flush_kern_cache_all 70 bl arm920_flush_kern_cache_all
71#endif
70 72
71 @@ prepare cpu to sleep 73 @@ prepare cpu to sleep
72 74
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index c55b739e10ba..1ff2f073a55d 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -121,8 +121,8 @@ config CPU_ARM925T
121# ARM926T 121# ARM926T
122config CPU_ARM926T 122config CPU_ARM926T
123 bool "Support ARM926T processor" 123 bool "Support ARM926T processor"
124 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB 124 depends on ARCH_INTEGRATOR || ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || MACH_REALVIEW_EB || ARCH_PNX4008
125 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX 125 default y if ARCH_VERSATILE_PB || MACH_VERSATILE_AB || ARCH_OMAP730 || ARCH_OMAP16XX || ARCH_PNX4008
126 select CPU_32v5 126 select CPU_32v5
127 select CPU_ABRT_EV5TJ 127 select CPU_ABRT_EV5TJ
128 select CPU_CACHE_VIVT 128 select CPU_CACHE_VIVT
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index f72a4f57905a..bf776125ca38 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -260,15 +260,17 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
260#define RPC_LSA_DEFAULT RPC_LED_TX_RX 260#define RPC_LSA_DEFAULT RPC_LED_TX_RX
261#define RPC_LSB_DEFAULT RPC_LED_100_10 261#define RPC_LSB_DEFAULT RPC_LED_100_10
262 262
263#elif defined(CONFIG_MACH_LPD7A400) || defined(CONFIG_MACH_LPD7A404) 263#elif defined(CONFIG_MACH_LPD79520) \
264 || defined(CONFIG_MACH_LPD7A400) \
265 || defined(CONFIG_MACH_LPD7A404)
264 266
265/* The LPD7A40X_IOBARRIER is necessary to overcome a mismatch between 267/* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
266 * the way that the CPU handles chip selects and the way that the SMC 268 * way that the CPU handles chip selects and the way that the SMC chip
267 * chip expects the chip select to operate. Refer to 269 * expects the chip select to operate. Refer to
268 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from 270 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
269 * IOBARRIER is a byte as a least-common denominator of possible 271 * IOBARRIER is a byte, in order that we read the least-common
270 * regions to use as the barrier. It would be wasteful to read 32 272 * denominator. It would be wasteful to read 32 bits from an 8-bit
271 * bits from a byte oriented region. 273 * accessible region.
272 * 274 *
273 * There is no explicit protection against interrupts intervening 275 * There is no explicit protection against interrupts intervening
274 * between the writew and the IOBARRIER. In SMC ISR there is a 276 * between the writew and the IOBARRIER. In SMC ISR there is a
@@ -287,25 +289,35 @@ SMC_outw(u16 val, void __iomem *ioaddr, int reg)
287#define SMC_CAN_USE_16BIT 1 289#define SMC_CAN_USE_16BIT 1
288#define SMC_CAN_USE_32BIT 0 290#define SMC_CAN_USE_32BIT 0
289#define SMC_NOWAIT 0 291#define SMC_NOWAIT 0
290#define LPD7A40X_IOBARRIER readb (IOBARRIER_VIRT) 292#define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
291 293
292#define SMC_inw(a,r) readw ((void*) ((a) + (r))) 294#define SMC_inw(a,r)\
293#define SMC_insw(a,r,p,l) readsw ((void*) ((a) + (r)), p, l) 295 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
294#define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7A40X_IOBARRIER; }) 296#define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
295 297
296#define SMC_outsw LPD7A40X_SMC_outsw 298#define SMC_insw LPD7_SMC_insw
299static inline void LPD7_SMC_insw (unsigned char* a, int r,
300 unsigned char* p, int l)
301{
302 unsigned short* ps = (unsigned short*) p;
303 while (l-- > 0) {
304 *ps++ = readw (a + r);
305 LPD7X_IOBARRIER;
306 }
307}
297 308
298static inline void LPD7A40X_SMC_outsw(unsigned long a, int r, 309#define SMC_outsw LPD7_SMC_outsw
299 unsigned char* p, int l) 310static inline void LPD7_SMC_outsw (unsigned char* a, int r,
311 unsigned char* p, int l)
300{ 312{
301 unsigned short* ps = (unsigned short*) p; 313 unsigned short* ps = (unsigned short*) p;
302 while (l-- > 0) { 314 while (l-- > 0) {
303 writew (*ps++, a + r); 315 writew (*ps++, a + r);
304 LPD7A40X_IOBARRIER; 316 LPD7X_IOBARRIER;
305 } 317 }
306} 318}
307 319
308#define SMC_INTERRUPT_PREAMBLE LPD7A40X_IOBARRIER 320#define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
309 321
310#define RPC_LSA_DEFAULT RPC_LED_TX_RX 322#define RPC_LSA_DEFAULT RPC_LED_TX_RX
311#define RPC_LSB_DEFAULT RPC_LED_100_10 323#define RPC_LSB_DEFAULT RPC_LED_100_10
diff --git a/drivers/serial/s3c2410.c b/drivers/serial/s3c2410.c
index f5aac92fb798..53c2465bad2d 100644
--- a/drivers/serial/s3c2410.c
+++ b/drivers/serial/s3c2410.c
@@ -1365,7 +1365,7 @@ static inline void s3c2410_serial_exit(void)
1365 1365
1366#endif /* CONFIG_CPU_S3C2410 */ 1366#endif /* CONFIG_CPU_S3C2410 */
1367 1367
1368#ifdef CONFIG_CPU_S3C2440 1368#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
1369 1369
1370static int s3c2440_serial_setsource(struct uart_port *port, 1370static int s3c2440_serial_setsource(struct uart_port *port,
1371 struct s3c24xx_uart_clksrc *clk) 1371 struct s3c24xx_uart_clksrc *clk)
diff --git a/drivers/serial/serial_lh7a40x.c b/drivers/serial/serial_lh7a40x.c
index aa521b8e0d4e..776d4ff06084 100644
--- a/drivers/serial/serial_lh7a40x.c
+++ b/drivers/serial/serial_lh7a40x.c
@@ -145,14 +145,15 @@ lh7a40xuart_rx_chars (struct uart_port* port)
145{ 145{
146 struct tty_struct* tty = port->info->tty; 146 struct tty_struct* tty = port->info->tty;
147 int cbRxMax = 256; /* (Gross) limit on receive */ 147 int cbRxMax = 256; /* (Gross) limit on receive */
148 unsigned int data, flag;/* Received data and status */ 148 unsigned int data; /* Received data and status */
149 unsigned int flag;
149 150
150 while (!(UR (port, UART_R_STATUS) & nRxRdy) && --cbRxMax) { 151 while (!(UR (port, UART_R_STATUS) & nRxRdy) && --cbRxMax) {
151 data = UR (port, UART_R_DATA); 152 data = UR (port, UART_R_DATA);
152 flag = TTY_NORMAL; 153 flag = TTY_NORMAL;
153 ++port->icount.rx; 154 ++port->icount.rx;
154 155
155 if (unlikely(data & RxError)) { /* Quick check, short-circuit */ 156 if (unlikely(data & RxError)) {
156 if (data & RxBreak) { 157 if (data & RxBreak) {
157 data &= ~(RxFramingError | RxParityError); 158 data &= ~(RxFramingError | RxParityError);
158 ++port->icount.brk; 159 ++port->icount.brk;
@@ -303,7 +304,7 @@ static void lh7a40xuart_set_mctrl (struct uart_port* port, unsigned int mctrl)
303 /* Note, kernel appears to be setting DTR and RTS on console. */ 304 /* Note, kernel appears to be setting DTR and RTS on console. */
304 305
305 /* *** FIXME: this deserves more work. There's some work in 306 /* *** FIXME: this deserves more work. There's some work in
306 tracing all of the IO pins. */ 307 tracing all of the IO pins. */
307#if 0 308#if 0
308 if( port->mapbase == UART1_PHYS) { 309 if( port->mapbase == UART1_PHYS) {
309 gpioRegs_t *gpio = (gpioRegs_t *)IO_ADDRESS(GPIO_PHYS); 310 gpioRegs_t *gpio = (gpioRegs_t *)IO_ADDRESS(GPIO_PHYS);
@@ -662,9 +663,13 @@ static int __init lh7a40xuart_init(void)
662 if (ret == 0) { 663 if (ret == 0) {
663 int i; 664 int i;
664 665
665 for (i = 0; i < DEV_NR; i++) 666 for (i = 0; i < DEV_NR; i++) {
667 /* UART3, when used, requires GPIO pin reallocation */
668 if (lh7a40x_ports[i].port.mapbase == UART3_PHYS)
669 GPIO_PINMUX |= 1<<3;
666 uart_add_one_port (&lh7a40x_reg, 670 uart_add_one_port (&lh7a40x_reg,
667 &lh7a40x_ports[i].port); 671 &lh7a40x_ports[i].port);
672 }
668 } 673 }
669 return ret; 674 return ret;
670} 675}
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 5641498725d0..5a2840aeb547 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -167,6 +167,69 @@ config FB_ARMCLCD
167 here and read <file:Documentation/modules.txt>. The module 167 here and read <file:Documentation/modules.txt>. The module
168 will be called amba-clcd. 168 will be called amba-clcd.
169 169
170choice
171
172 depends on FB_ARMCLCD && (ARCH_LH7A40X || ARCH_LH7952X)
173 prompt "LCD Panel"
174 default FB_ARMCLCD_SHARP_LQ035Q7DB02
175
176config FB_ARMCLCD_SHARP_LQ035Q7DB02_HRTFT
177 bool "LogicPD LCD 3.5\" QVGA w/HRTFT IC"
178 help
179 This is an implementation of the Sharp LQ035Q7DB02, a 3.5"
180 color QVGA, HRTFT panel. The LogicPD device includes an
181 an integrated HRTFT controller IC.
182 The native resolution is 240x320.
183
184config FB_ARMCLCD_SHARP_LQ057Q3DC02
185 bool "LogicPD LCD 5.7\" QVGA"
186 help
187 This is an implementation of the Sharp LQ057Q3DC02, a 5.7"
188 color QVGA, TFT panel. The LogicPD device includes an
189 The native resolution is 320x240.
190
191config FB_ARMCLCD_SHARP_LQ64D343
192 bool "LogicPD LCD 6.4\" VGA"
193 help
194 This is an implementation of the Sharp LQ64D343, a 6.4"
195 color VGA, TFT panel. The LogicPD device includes an
196 The native resolution is 640x480.
197
198config FB_ARMCLCD_SHARP_LQ10D368
199 bool "LogicPD LCD 10.4\" VGA"
200 help
201 This is an implementation of the Sharp LQ10D368, a 10.4"
202 color VGA, TFT panel. The LogicPD device includes an
203 The native resolution is 640x480.
204
205
206config FB_ARMCLCD_SHARP_LQ121S1DG41
207 bool "LogicPD LCD 12.1\" SVGA"
208 help
209 This is an implementation of the Sharp LQ121S1DG41, a 12.1"
210 color SVGA, TFT panel. The LogicPD device includes an
211 The native resolution is 800x600.
212
213 This panel requires a clock rate may be an integer fraction
214 of the base LCDCLK frequency. The driver will select the
215 highest frequency available that is lower than the maximum
216 allowed. The panel may flicker if the clock rate is
217 slower than the recommended minimum.
218
219config FB_ARMCLCD_AUO_A070VW01_WIDE
220 bool "AU Optronics A070VW01 LCD 7.0\" WIDE"
221 help
222 This is an implementation of the AU Optronics, a 7.0"
223 WIDE Color. The native resolution is 234x480.
224
225config FB_ARMCLCD_HITACHI
226 bool "Hitachi Wide Screen 800x480"
227 help
228 This is an implementation of the Hitachi 800x480.
229
230endchoice
231
232
170config FB_ACORN 233config FB_ACORN
171 bool "Acorn VIDC support" 234 bool "Acorn VIDC support"
172 depends on (FB = y) && ARM && (ARCH_ACORN || ARCH_CLPS7500) 235 depends on (FB = y) && ARM && (ARCH_ACORN || ARCH_CLPS7500)
diff --git a/include/asm-arm/arch-lh7a40x/clocks.h b/include/asm-arm/arch-lh7a40x/clocks.h
new file mode 100644
index 000000000000..bee02fd8dab1
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/clocks.h
@@ -0,0 +1,20 @@
1/* include/asm-arm/arch-lh7a40x/clocks.h
2 *
3 * Copyright (C) 2004 Marc Singer
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation.
8 *
9 */
10
11#include <linux/config.h>
12
13#ifndef __ASM_ARCH_CLOCKS_H
14#define __ASM_ARCH_CLOCKS_H
15
16unsigned int fclkfreq_get (void);
17unsigned int hclkfreq_get (void);
18unsigned int pclkfreq_get (void);
19
20#endif /* _ASM_ARCH_CLOCKS_H */
diff --git a/include/asm-arm/arch-lh7a40x/constants.h b/include/asm-arm/arch-lh7a40x/constants.h
index 52c1cb9c39c6..2929e891ee03 100644
--- a/include/asm-arm/arch-lh7a40x/constants.h
+++ b/include/asm-arm/arch-lh7a40x/constants.h
@@ -29,8 +29,7 @@
29 29
30#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) 30#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
31 31
32# define IOBARRIER_PHYS 0xc0000000 /* Start of SDRAM */ 32# define IOBARRIER_PHYS 0x10000000 /* Second bank, fastest timing */
33/*# define IOBARRIER_PHYS 0x00000000 */ /* Start of flash */
34# define IOBARRIER_VIRT 0xf0000000 33# define IOBARRIER_VIRT 0xf0000000
35# define IOBARRIER_SIZE PAGE_SIZE 34# define IOBARRIER_SIZE PAGE_SIZE
36 35
@@ -53,6 +52,9 @@
53# define CPLD08_PHYS CPLDX_PHYS (0x08) 52# define CPLD08_PHYS CPLDX_PHYS (0x08)
54# define CPLD08_VIRT CPLDX_VIRT (0x08) 53# define CPLD08_VIRT CPLDX_VIRT (0x08)
55# define CPLD08_SIZE PAGE_SIZE 54# define CPLD08_SIZE PAGE_SIZE
55# define CPLD0A_PHYS CPLDX_PHYS (0x0a)
56# define CPLD0A_VIRT CPLDX_VIRT (0x0a)
57# define CPLD0A_SIZE PAGE_SIZE
56# define CPLD0C_PHYS CPLDX_PHYS (0x0c) 58# define CPLD0C_PHYS CPLDX_PHYS (0x0c)
57# define CPLD0C_VIRT CPLDX_VIRT (0x0c) 59# define CPLD0C_VIRT CPLDX_VIRT (0x0c)
58# define CPLD0C_SIZE PAGE_SIZE 60# define CPLD0C_SIZE PAGE_SIZE
@@ -84,5 +86,7 @@
84#define XTAL_IN 14745600 /* 14.7456 MHz crystal */ 86#define XTAL_IN 14745600 /* 14.7456 MHz crystal */
85#define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */ 87#define PLL_CLOCK (XTAL_IN * 21) /* 309 MHz PLL clock */
86#define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */ 88#define MAX_HCLK_KHZ 100000 /* HCLK max limit ~100MHz */
89#define HCLK (99993600)
90//#define HCLK (119808000)
87 91
88#endif /* __ASM_ARCH_CONSTANTS_H */ 92#endif /* __ASM_ARCH_CONSTANTS_H */
diff --git a/include/asm-arm/arch-lh7a40x/dma.h b/include/asm-arm/arch-lh7a40x/dma.h
index 15492e3253f6..a8cbd14bbf9d 100644
--- a/include/asm-arm/arch-lh7a40x/dma.h
+++ b/include/asm-arm/arch-lh7a40x/dma.h
@@ -1,9 +1,86 @@
1/* include/asm-arm/arch-lh7a40x/dma.h 1/* include/asm-arm/arch-lh7a40x/dma.h
2 * 2 *
3 * Copyright (C) 2003 Coastal Environmental Systems 3 * Copyright (C) 2005 Marc Singer
4 * 4 *
5 * This program is free software; you can redistribute it and/or 5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License 6 * modify it under the terms of the GNU General Public License
7 * version 2 as published by the Free Software Foundation. 7 * version 2 as published by the Free Software Foundation.
8 * 8 *
9 */ 9 */
10
11typedef enum {
12 DMA_M2M0 = 0,
13 DMA_M2M1 = 1,
14 DMA_M2P0 = 2, /* Tx */
15 DMA_M2P1 = 3, /* Rx */
16 DMA_M2P2 = 4, /* Tx */
17 DMA_M2P3 = 5, /* Rx */
18 DMA_M2P4 = 6, /* Tx - AC97 */
19 DMA_M2P5 = 7, /* Rx - AC97 */
20 DMA_M2P6 = 8, /* Tx */
21 DMA_M2P7 = 9, /* Rx */
22} dma_device_t;
23
24#define DMA_LENGTH_MAX ((64*1024) - 4) /* bytes */
25
26#define DMAC_GCA __REG(DMAC_PHYS + 0x2b80)
27#define DMAC_GIR __REG(DMAC_PHYS + 0x2bc0)
28
29#define DMAC_GIR_MMI1 (1<<11)
30#define DMAC_GIR_MMI0 (1<<10)
31#define DMAC_GIR_MPI8 (1<<9)
32#define DMAC_GIR_MPI9 (1<<8)
33#define DMAC_GIR_MPI6 (1<<7)
34#define DMAC_GIR_MPI7 (1<<6)
35#define DMAC_GIR_MPI4 (1<<5)
36#define DMAC_GIR_MPI5 (1<<4)
37#define DMAC_GIR_MPI2 (1<<3)
38#define DMAC_GIR_MPI3 (1<<2)
39#define DMAC_GIR_MPI0 (1<<1)
40#define DMAC_GIR_MPI1 (1<<0)
41
42#define DMAC_M2P0 0x0000
43#define DMAC_M2P1 0x0040
44#define DMAC_M2P2 0x0080
45#define DMAC_M2P3 0x00c0
46#define DMAC_M2P4 0x0240
47#define DMAC_M2P5 0x0200
48#define DMAC_M2P6 0x02c0
49#define DMAC_M2P7 0x0280
50#define DMAC_M2P8 0x0340
51#define DMAC_M2P9 0x0300
52#define DMAC_M2M0 0x0100
53#define DMAC_M2M1 0x0140
54
55#define DMAC_P_PCONTROL(c) __REG(DMAC_PHYS + (c) + 0x00)
56#define DMAC_P_PINTERRUPT(c) __REG(DMAC_PHYS + (c) + 0x04)
57#define DMAC_P_PPALLOC(c) __REG(DMAC_PHYS + (c) + 0x08)
58#define DMAC_P_PSTATUS(c) __REG(DMAC_PHYS + (c) + 0x0c)
59#define DMAC_P_REMAIN(c) __REG(DMAC_PHYS + (c) + 0x14)
60#define DMAC_P_MAXCNT0(c) __REG(DMAC_PHYS + (c) + 0x20)
61#define DMAC_P_BASE0(c) __REG(DMAC_PHYS + (c) + 0x24)
62#define DMAC_P_CURRENT0(c) __REG(DMAC_PHYS + (c) + 0x28)
63#define DMAC_P_MAXCNT1(c) __REG(DMAC_PHYS + (c) + 0x30)
64#define DMAC_P_BASE1(c) __REG(DMAC_PHYS + (c) + 0x34)
65#define DMAC_P_CURRENT1(c) __REG(DMAC_PHYS + (c) + 0x38)
66
67#define DMAC_PCONTROL_ENABLE (1<<4)
68
69#define DMAC_PORT_USB 0
70#define DMAC_PORT_SDMMC 1
71#define DMAC_PORT_AC97_1 2
72#define DMAC_PORT_AC97_2 3
73#define DMAC_PORT_AC97_3 4
74#define DMAC_PORT_UART1 6
75#define DMAC_PORT_UART2 7
76#define DMAC_PORT_UART3 8
77
78#define DMAC_PSTATUS_CURRSTATE_SHIFT 4
79#define DMAC_PSTATUS_CURRSTATE_MASK 0x3
80
81#define DMAC_PSTATUS_NEXTBUF (1<<6)
82#define DMAC_PSTATUS_STALLRINT (1<<0)
83
84#define DMAC_INT_CHE (1<<3)
85#define DMAC_INT_NFB (1<<1)
86#define DMAC_INT_STALL (1<<0)
diff --git a/include/asm-arm/arch-lh7a40x/entry-macro.S b/include/asm-arm/arch-lh7a40x/entry-macro.S
index a2f67c06d9c9..9fc7f4988124 100644
--- a/include/asm-arm/arch-lh7a40x/entry-macro.S
+++ b/include/asm-arm/arch-lh7a40x/entry-macro.S
@@ -10,11 +10,73 @@
10#include <asm/hardware.h> 10#include <asm/hardware.h>
11#include <asm/arch/irqs.h> 11#include <asm/arch/irqs.h>
12 12
13# if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404) 13/* In order to allow there to be support for both of the processor
14# error "LH7A400 and LH7A404 are mutually exclusive" 14 classes at the same time, we make a hack here that isn't very
15# endif 15 pretty. At startup, the link pointed to with the
16 branch_irq_lh7a400 symbol is replaced with a NOP when the CPU is
17 detected as a lh7a404.
16 18
17# if defined (CONFIG_ARCH_LH7A400) 19 *** FIXME: we should clean this up so that there is only one
20 implementation for each CPU's design.
21
22*/
23
24#if defined (CONFIG_ARCH_LH7A400) && defined (CONFIG_ARCH_LH7A404)
25
26 .macro disable_fiq
27 .endm
28
29 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
30
31branch_irq_lh7a400: b 1000f
32
33@ Implementation of the LH7A404 get_irqnr_and_base.
34
35 mov \irqnr, #0 @ VIC1 irq base
36 mov \base, #io_p2v(0x80000000) @ APB registers
37 add \base, \base, #0x8000
38 ldr \tmp, [\base, #0x0030] @ VIC1_VECTADDR
39 tst \tmp, #VA_VECTORED @ Direct vectored
40 bne 1002f
41 tst \tmp, #VA_VIC1DEFAULT @ Default vectored VIC1
42 ldrne \irqstat, [\base, #0] @ VIC1_IRQSTATUS
43 bne 1001f
44 add \base, \base, #(0xa000 - 0x8000)
45 ldr \tmp, [\base, #0x0030] @ VIC2_VECTADDR
46 tst \tmp, #VA_VECTORED @ Direct vectored
47 bne 1002f
48 ldr \irqstat, [\base, #0] @ VIC2_IRQSTATUS
49 mov \irqnr, #32 @ VIC2 irq base
50
511001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
52 bcs 1008f @ Bit set; irq found
53 add \irqnr, \irqnr, #1
54 bne 1001b @ Until no bits
55 b 1009f @ Nothing? Hmm.
561002: and \irqnr, \tmp, #0x3f @ Mask for valid bits
571008: movs \irqstat, #1 @ Force !Z
58 str \tmp, [\base, #0x0030] @ Clear vector
59 b 1009f
60
61@ Implementation of the LH7A400 get_irqnr_and_base.
62
631000: mov \irqnr, #0
64 mov \base, #io_p2v(0x80000000) @ APB registers
65 ldr \irqstat, [\base, #0x500] @ PIC INTSR
66
671001: movs \irqstat, \irqstat, lsr #1 @ Shift into carry
68 bcs 1008f @ Bit set; irq found
69 add \irqnr, \irqnr, #1
70 bne 1001b @ Until no bits
71 b 1009f @ Nothing? Hmm.
721008: movs \irqstat, #1 @ Force !Z
73
741009:
75 .endm
76
77
78
79#elif defined (CONFIG_ARCH_LH7A400)
18 .macro disable_fiq 80 .macro disable_fiq
19 .endm 81 .endm
20 82
diff --git a/include/asm-arm/arch-lh7a40x/hardware.h b/include/asm-arm/arch-lh7a40x/hardware.h
index aeb07c162e25..e9ff74fd7939 100644
--- a/include/asm-arm/arch-lh7a40x/hardware.h
+++ b/include/asm-arm/arch-lh7a40x/hardware.h
@@ -13,6 +13,8 @@
13#ifndef __ASM_ARCH_HARDWARE_H 13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H 14#define __ASM_ARCH_HARDWARE_H
15 15
16#include <asm/sizes.h> /* Added for the sake of amba-clcd driver */
17
16#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff)) 18#define io_p2v(x) (0xf0000000 | (((x) & 0xfff00000) >> 4) | ((x) & 0x0000ffff))
17#define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff)) 19#define io_v2p(x) ( (((x) & 0x0fff0000) << 4) | ((x) & 0x0000ffff))
18 20
@@ -53,6 +55,8 @@ typedef struct { volatile u8 offset[4096]; } __regbase8;
53 55
54#endif 56#endif
55 57
58#define MASK_AND_SET(v,m,s) (v) = ((v)&~(m))|(s)
59
56#include "registers.h" 60#include "registers.h"
57 61
58#endif /* _ASM_ARCH_HARDWARE_H */ 62#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-lh7a40x/irqs.h b/include/asm-arm/arch-lh7a40x/irqs.h
index f91f3e59f3ab..7e8a217200e9 100644
--- a/include/asm-arm/arch-lh7a40x/irqs.h
+++ b/include/asm-arm/arch-lh7a40x/irqs.h
@@ -154,9 +154,10 @@
154#if !defined (IRQ_GPIO0INTR) 154#if !defined (IRQ_GPIO0INTR)
155# define IRQ_GPIO0INTR IRQ_GPIO0FIQ 155# define IRQ_GPIO0INTR IRQ_GPIO0FIQ
156#endif 156#endif
157#define IRQ_TICK IRQ_TINTR 157#define IRQ_TICK IRQ_TINTR
158#define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */ 158#define IRQ_PCC1_RDY IRQ_GPIO6INTR /* PCCard 1 ready */
159#define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */ 159#define IRQ_PCC2_RDY IRQ_GPIO7INTR /* PCCard 2 ready */
160#define IRQ_USB IRQ_USBINTR /* USB device */
160 161
161#ifdef CONFIG_MACH_KEV7A400 162#ifdef CONFIG_MACH_KEV7A400
162# define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */ 163# define IRQ_TS IRQ_GPIOFIQ /* Touchscreen */
@@ -191,6 +192,10 @@
191# define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */ 192# define IRQ_LPD7A400_TS IRQ_LPD7A40X_CPLD + 1 /* Touch screen */
192#endif 193#endif
193 194
195#if defined (CONFIG_MACH_LPD7A400)
196# define IRQ_TOUCH IRQ_LPD7A400_TS
197#endif
198
194#define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD) 199#define NR_IRQS (NR_IRQ_CPU + NR_IRQ_BOARD)
195 200
196#endif 201#endif
diff --git a/include/asm-arm/arch-lh7a40x/registers.h b/include/asm-arm/arch-lh7a40x/registers.h
index 2edb22e35450..544307bb87a2 100644
--- a/include/asm-arm/arch-lh7a40x/registers.h
+++ b/include/asm-arm/arch-lh7a40x/registers.h
@@ -18,7 +18,7 @@
18 18
19 /* Physical register base addresses */ 19 /* Physical register base addresses */
20 20
21#define AC97_PHYS (0x80000000) /* AC97 Controller */ 21#define AC97C_PHYS (0x80000000) /* AC97 Controller */
22#define MMC_PHYS (0x80000100) /* Multimedia Card Controller */ 22#define MMC_PHYS (0x80000100) /* Multimedia Card Controller */
23#define USB_PHYS (0x80000200) /* USB Client */ 23#define USB_PHYS (0x80000200) /* USB Client */
24#define SCI_PHYS (0x80000300) /* Secure Card Interface */ 24#define SCI_PHYS (0x80000300) /* Secure Card Interface */
@@ -35,6 +35,8 @@
35#define RTC_PHYS (0x80000d00) /* Real-time Clock */ 35#define RTC_PHYS (0x80000d00) /* Real-time Clock */
36#define GPIO_PHYS (0x80000e00) /* General Purpose IO */ 36#define GPIO_PHYS (0x80000e00) /* General Purpose IO */
37#define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */ 37#define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */
38#define HRTFTC_PHYS (0x80001000) /* High-res TFT Controller (LH7A400) */
39#define ALI_PHYS (0x80001000) /* Advanced LCD Interface (LH7A404) */
38#define WDT_PHYS (0x80001400) /* Watchdog Timer */ 40#define WDT_PHYS (0x80001400) /* Watchdog Timer */
39#define SMC_PHYS (0x80002000) /* Static Memory Controller */ 41#define SMC_PHYS (0x80002000) /* Static Memory Controller */
40#define SDRC_PHYS (0x80002400) /* SDRAM Controller */ 42#define SDRC_PHYS (0x80002400) /* SDRAM Controller */
@@ -43,6 +45,7 @@
43 45
44 /* Physical registers of the LH7A404 */ 46 /* Physical registers of the LH7A404 */
45 47
48#define ADC_PHYS (0x80001300) /* A/D & Touchscreen Controller */
46#define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */ 49#define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */
47#define USBH_PHYS (0x80009000) /* USB OHCI host controller */ 50#define USBH_PHYS (0x80009000) /* USB OHCI host controller */
48#define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */ 51#define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */
@@ -53,10 +56,32 @@
53 56
54 /* Clock/State Controller register */ 57 /* Clock/State Controller register */
55 58
59#define CSC_PWRSR __REG(CSC_PHYS + 0x00) /* Reset register & ID */
56#define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */ 60#define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */
61#define CSC_CLKSET __REG(CSC_PHYS + 0x20) /* Clock speed control */
62#define CSC_USBDRESET __REG(CSC_PHYS + 0x4c) /* USB Device resets */
57 63
58#define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */ 64#define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */
59 65#define CSC_PWRCNT_DMAC_M2M1_EN (1<<27)
66#define CSC_PWRCNT_DMAC_M2M0_EN (1<<26)
67#define CSC_PWRCNT_DMAC_M2P8_EN (1<<25)
68#define CSC_PWRCNT_DMAC_M2P9_EN (1<<24)
69#define CSC_PWRCNT_DMAC_M2P6_EN (1<<23)
70#define CSC_PWRCNT_DMAC_M2P7_EN (1<<22)
71#define CSC_PWRCNT_DMAC_M2P4_EN (1<<21)
72#define CSC_PWRCNT_DMAC_M2P5_EN (1<<20)
73#define CSC_PWRCNT_DMAC_M2P2_EN (1<<19)
74#define CSC_PWRCNT_DMAC_M2P3_EN (1<<18)
75#define CSC_PWRCNT_DMAC_M2P0_EN (1<<17)
76#define CSC_PWRCNT_DMAC_M2P1_EN (1<<16)
77
78#define CSC_PWRSR_CHIPMAN_SHIFT (24)
79#define CSC_PWRSR_CHIPMAN_MASK (0xff)
80#define CSC_PWRSR_CHIPID_SHIFT (16)
81#define CSC_PWRSR_CHIPID_MASK (0xff)
82
83#define CSC_USBDRESET_APBRESETREG (1<<1)
84#define CSC_USBDRESET_IORESETREG (1<<0)
60 85
61 /* Interrupt Controller registers */ 86 /* Interrupt Controller registers */
62 87
@@ -109,6 +134,13 @@
109#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */ 134#define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
110#define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */ 135#define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
111#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */ 136#define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
137#define GPIO_PINMUX __REG(GPIO_PHYS + 0x2c)
138#define GPIO_PADD __REG(GPIO_PHYS + 0x10)
139#define GPIO_PAD __REG(GPIO_PHYS + 0x00)
140#define GPIO_PCD __REG(GPIO_PHYS + 0x08)
141#define GPIO_PCDD __REG(GPIO_PHYS + 0x18)
142#define GPIO_PEDD __REG(GPIO_PHYS + 0x24)
143#define GPIO_PED __REG(GPIO_PHYS + 0x20)
112 144
113 145
114 /* Static Memory Controller registers */ 146 /* Static Memory Controller registers */
@@ -138,20 +170,21 @@
138#endif 170#endif
139 171
140#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404) 172#if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
141# define CPLD_CONTROL __REG8(CPLD02_PHYS)
142# define CPLD_SPI_DATA __REG8(CPLD06_PHYS)
143# define CPLD_SPI_CONTROL __REG8(CPLD08_PHYS)
144# define CPLD_SPI_EEPROM __REG8(CPLD0A_PHYS)
145# define CPLD_INTERRUPTS __REG8(CPLD0C_PHYS) /* IRQ mask/status */
146# define CPLD_BOOT_MODE __REG8(CPLD0E_PHYS)
147# define CPLD_FLASH __REG8(CPLD10_PHYS)
148# define CPLD_POWER_MGMT __REG8(CPLD12_PHYS)
149# define CPLD_REVISION __REG8(CPLD14_PHYS)
150# define CPLD_GPIO_EXT __REG8(CPLD16_PHYS)
151# define CPLD_GPIO_DATA __REG8(CPLD18_PHYS)
152# define CPLD_GPIO_DIR __REG8(CPLD1A_PHYS)
153#endif
154 173
174# define CPLD_CONTROL __REG16(CPLD02_PHYS)
175# define CPLD_SPI_DATA __REG16(CPLD06_PHYS)
176# define CPLD_SPI_CONTROL __REG16(CPLD08_PHYS)
177# define CPLD_SPI_EEPROM __REG16(CPLD0A_PHYS)
178# define CPLD_INTERRUPTS __REG16(CPLD0C_PHYS) /* IRQ mask/status */
179# define CPLD_BOOT_MODE __REG16(CPLD0E_PHYS)
180# define CPLD_FLASH __REG16(CPLD10_PHYS)
181# define CPLD_POWER_MGMT __REG16(CPLD12_PHYS)
182# define CPLD_REVISION __REG16(CPLD14_PHYS)
183# define CPLD_GPIO_EXT __REG16(CPLD16_PHYS)
184# define CPLD_GPIO_DATA __REG16(CPLD18_PHYS)
185# define CPLD_GPIO_DIR __REG16(CPLD1A_PHYS)
186
187#endif
155 188
156 /* Timer registers */ 189 /* Timer registers */
157 190
@@ -190,4 +223,3 @@
190 223
191 224
192#endif /* _ASM_ARCH_REGISTERS_H */ 225#endif /* _ASM_ARCH_REGISTERS_H */
193
diff --git a/include/asm-arm/arch-lh7a40x/ssp.h b/include/asm-arm/arch-lh7a40x/ssp.h
new file mode 100644
index 000000000000..132b1c4d5ce6
--- /dev/null
+++ b/include/asm-arm/arch-lh7a40x/ssp.h
@@ -0,0 +1,71 @@
1/* ssp.h
2 $Id$
3
4 written by Marc Singer
5 6 Dec 2004
6
7 Copyright (C) 2004 Marc Singer
8
9 -----------
10 DESCRIPTION
11 -----------
12
13 This SSP header is available throughout the kernel, for this
14 machine/architecture, because drivers that use it may be dispersed.
15
16 This file was cloned from the 7952x implementation. It would be
17 better to share them, but we're taking an easier approach for the
18 time being.
19
20*/
21
22#if !defined (__SSP_H__)
23# define __SSP_H__
24
25/* ----- Includes */
26
27/* ----- Types */
28
29struct ssp_driver {
30 int (*init) (void);
31 void (*exit) (void);
32 void (*acquire) (void);
33 void (*release) (void);
34 int (*configure) (int device, int mode, int speed,
35 int frame_size_write, int frame_size_read);
36 void (*chip_select) (int enable);
37 void (*set_callbacks) (void* handle,
38 irqreturn_t (*callback_tx)(void*),
39 irqreturn_t (*callback_rx)(void*));
40 void (*enable) (void);
41 void (*disable) (void);
42// int (*save_state) (void*);
43// void (*restore_state) (void*);
44 int (*read) (void);
45 int (*write) (u16 data);
46 int (*write_read) (u16 data);
47 void (*flush) (void);
48 void (*write_async) (void* pv, size_t cb);
49 size_t (*write_pos) (void);
50};
51
52 /* These modes are only available on the LH79524 */
53#define SSP_MODE_SPI (1)
54#define SSP_MODE_SSI (2)
55#define SSP_MODE_MICROWIRE (3)
56#define SSP_MODE_I2S (4)
57
58 /* CPLD SPI devices */
59#define DEVICE_EEPROM 0 /* Configuration eeprom */
60#define DEVICE_MAC 1 /* MAC eeprom (LPD79524) */
61#define DEVICE_CODEC 2 /* Audio codec */
62#define DEVICE_TOUCH 3 /* Touch screen (LPD79520) */
63
64/* ----- Globals */
65
66/* ----- Prototypes */
67
68//extern struct ssp_driver lh79520_i2s_driver;
69extern struct ssp_driver lh7a400_cpld_ssp_driver;
70
71#endif /* __SSP_H__ */
diff --git a/include/asm-arm/arch-lh7a40x/uncompress.h b/include/asm-arm/arch-lh7a40x/uncompress.h
index f8053346f608..3d1ce0426a33 100644
--- a/include/asm-arm/arch-lh7a40x/uncompress.h
+++ b/include/asm-arm/arch-lh7a40x/uncompress.h
@@ -16,7 +16,7 @@
16#ifndef UART_R_STATUS 16#ifndef UART_R_STATUS
17# define UART_R_STATUS (0x10) 17# define UART_R_STATUS (0x10)
18#endif 18#endif
19#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */ 19#define nTxRdy (0x20) /* Not TxReady (literally Tx FIFO full) */
20 20
21 /* Access UART with physical addresses before MMU is setup */ 21 /* Access UART with physical addresses before MMU is setup */
22#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS)) 22#define UART_STATUS (*(volatile unsigned long*) (UART2_PHYS + UART_R_STATUS))
diff --git a/include/asm-arm/arch-pnx4008/clock.h b/include/asm-arm/arch-pnx4008/clock.h
new file mode 100644
index 000000000000..91ae0030fdf2
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/clock.h
@@ -0,0 +1,61 @@
1/*
2 * include/asm-arm/arch-pnx4008/clock.h
3 *
4 * Clock control driver for PNX4008 - header file
5 *
6 * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#ifndef __PNX4008_CLOCK_H__
14#define __PNX4008_CLOCK_H__
15
16struct module;
17struct clk;
18
19#define PWRMAN_VA_BASE IO_ADDRESS(PNX4008_PWRMAN_BASE)
20#define HCLKDIVCTRL_REG (PWRMAN_VA_BASE + 0x40)
21#define PWRCTRL_REG (PWRMAN_VA_BASE + 0x44)
22#define PLLCTRL_REG (PWRMAN_VA_BASE + 0x48)
23#define OSC13CTRL_REG (PWRMAN_VA_BASE + 0x4c)
24#define SYSCLKCTRL_REG (PWRMAN_VA_BASE + 0x50)
25#define HCLKPLLCTRL_REG (PWRMAN_VA_BASE + 0x58)
26#define USBCTRL_REG (PWRMAN_VA_BASE + 0x64)
27#define SDRAMCLKCTRL_REG (PWRMAN_VA_BASE + 0x68)
28#define MSCTRL_REG (PWRMAN_VA_BASE + 0x80)
29#define BTCLKCTRL (PWRMAN_VA_BASE + 0x84)
30#define DUMCLKCTRL_REG (PWRMAN_VA_BASE + 0x90)
31#define I2CCLKCTRL_REG (PWRMAN_VA_BASE + 0xac)
32#define KEYCLKCTRL_REG (PWRMAN_VA_BASE + 0xb0)
33#define TSCLKCTRL_REG (PWRMAN_VA_BASE + 0xb4)
34#define PWMCLKCTRL_REG (PWRMAN_VA_BASE + 0xb8)
35#define SPICTRL_REG (PWRMAN_VA_BASE + 0xc4)
36#define FLASHCLKCTRL_REG (PWRMAN_VA_BASE + 0xc8)
37#define UART3CLK_REG (PWRMAN_VA_BASE + 0xd0)
38#define UARTCLKCTRL_REG (PWRMAN_VA_BASE + 0xe4)
39#define DMACLKCTRL_REG (PWRMAN_VA_BASE + 0xe8)
40#define AUTOCLK_CTRL (PWRMAN_VA_BASE + 0xec)
41#define JPEGCLKCTRL_REG (PWRMAN_VA_BASE + 0xfc)
42
43#define AUDIOCONFIG_VA_BASE IO_ADDRESS(PNX4008_AUDIOCONFIG_BASE)
44#define DSPPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x60)
45#define DSPCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x64)
46#define AUDIOCLKCTRL_REG (AUDIOCONFIG_VA_BASE + 0x68)
47#define AUDIOPLLCTRL_REG (AUDIOCONFIG_VA_BASE + 0x6C)
48
49#define USB_OTG_CLKCTRL_REG IO_ADDRESS(PNX4008_USB_CONFIG_BASE + 0xff4)
50
51#define VFP9CLKCTRL_REG IO_ADDRESS(PNX4008_DEBUG_BASE)
52
53#define CLK_RATE_13MHZ 13000
54#define CLK_RATE_1MHZ 1000
55#define CLK_RATE_208MHZ 208000
56#define CLK_RATE_48MHZ 48000
57#define CLK_RATE_32KHZ 32
58
59#define PNX4008_UART_CLK CLK_RATE_13MHZ * 1000 /* in MHz */
60
61#endif
diff --git a/include/asm-arm/arch-pnx4008/debug-macro.S b/include/asm-arm/arch-pnx4008/debug-macro.S
new file mode 100644
index 000000000000..eb3839de389a
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/debug-macro.S
@@ -0,0 +1,27 @@
1/* linux/include/asm-arm/arch-pnx4008/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart,rx
15 mrc p15, 0, \rx, c1, c0
16 tst \rx, #1 @ MMU enabled?
17 mov \rx, #0x00090000
18 addeq \rx, \rx, #0x40000000
19 addne \rx, \rx, #0xf4000000
20 .endm
21
22 .macro senduart,rd,rx
23 strb \rd, [\rx, #0x0]
24 .endm
25
26#define UART_SHIFT 2
27#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-pnx4008/dma.h b/include/asm-arm/arch-pnx4008/dma.h
new file mode 100644
index 000000000000..3aee1204795b
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/dma.h
@@ -0,0 +1,162 @@
1/*
2 * linux/include/asm-arm/arch-pnx4008/dma.h
3 *
4 * PNX4008 DMA header file
5 *
6 * Author: Vitaly Wool
7 * Copyright: MontaVista Software Inc. (c) 2005
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef __ASM_ARCH_DMA_H
15#define __ASM_ARCH_DMA_H
16
17#include "platform.h"
18
19#define MAX_DMA_ADDRESS 0xffffffff
20
21#define MAX_DMA_CHANNELS 8
22
23#define DMAC_BASE IO_ADDRESS(PNX4008_DMA_CONFIG_BASE)
24#define DMAC_INT_STAT (DMAC_BASE + 0x0000)
25#define DMAC_INT_TC_STAT (DMAC_BASE + 0x0004)
26#define DMAC_INT_TC_CLEAR (DMAC_BASE + 0x0008)
27#define DMAC_INT_ERR_STAT (DMAC_BASE + 0x000c)
28#define DMAC_INT_ERR_CLEAR (DMAC_BASE + 0x0010)
29#define DMAC_SOFT_SREQ (DMAC_BASE + 0x0024)
30#define DMAC_CONFIG (DMAC_BASE + 0x0030)
31#define DMAC_Cx_SRC_ADDR(c) (DMAC_BASE + 0x0100 + (c) * 0x20)
32#define DMAC_Cx_DEST_ADDR(c) (DMAC_BASE + 0x0104 + (c) * 0x20)
33#define DMAC_Cx_LLI(c) (DMAC_BASE + 0x0108 + (c) * 0x20)
34#define DMAC_Cx_CONTROL(c) (DMAC_BASE + 0x010c + (c) * 0x20)
35#define DMAC_Cx_CONFIG(c) (DMAC_BASE + 0x0110 + (c) * 0x20)
36
37enum {
38 WIDTH_BYTE = 0,
39 WIDTH_HWORD,
40 WIDTH_WORD
41};
42
43enum {
44 FC_MEM2MEM_DMA,
45 FC_MEM2PER_DMA,
46 FC_PER2MEM_DMA,
47 FC_PER2PER_DMA,
48 FC_PER2PER_DPER,
49 FC_MEM2PER_PER,
50 FC_PER2MEM_PER,
51 FC_PER2PER_SPER
52};
53
54enum {
55 DMA_INT_UNKNOWN = 0,
56 DMA_ERR_INT = 1,
57 DMA_TC_INT = 2,
58};
59
60enum {
61 DMA_BUFFER_ALLOCATED = 1,
62 DMA_HAS_LL = 2,
63};
64
65enum {
66 PER_CAM_DMA_1 = 0,
67 PER_NDF_FLASH = 1,
68 PER_MBX_SLAVE_FIFO = 2,
69 PER_SPI2_REC_XMIT = 3,
70 PER_MS_SD_RX_XMIT = 4,
71 PER_HS_UART_1_XMIT = 5,
72 PER_HS_UART_1_RX = 6,
73 PER_HS_UART_2_XMIT = 7,
74 PER_HS_UART_2_RX = 8,
75 PER_HS_UART_7_XMIT = 9,
76 PER_HS_UART_7_RX = 10,
77 PER_SPI1_REC_XMIT = 11,
78 PER_MLC_NDF_SREC = 12,
79 PER_CAM_DMA_2 = 13,
80 PER_PRNG_INFIFO = 14,
81 PER_PRNG_OUTFIFO = 15,
82};
83
84struct pnx4008_dma_ch_ctrl {
85 int tc_mask;
86 int cacheable;
87 int bufferable;
88 int priv_mode;
89 int di;
90 int si;
91 int dest_ahb1;
92 int src_ahb1;
93 int dwidth;
94 int swidth;
95 int dbsize;
96 int sbsize;
97 int tr_size;
98};
99
100struct pnx4008_dma_ch_config {
101 int halt;
102 int active;
103 int lock;
104 int itc;
105 int ie;
106 int flow_cntrl;
107 int dest_per;
108 int src_per;
109};
110
111struct pnx4008_dma_ll {
112 unsigned long src_addr;
113 unsigned long dest_addr;
114 u32 next_dma;
115 unsigned long ch_ctrl;
116 struct pnx4008_dma_ll *next;
117 int flags;
118 void *alloc_data;
119 int (*free) (void *);
120};
121
122struct pnx4008_dma_config {
123 int is_ll;
124 unsigned long src_addr;
125 unsigned long dest_addr;
126 unsigned long ch_ctrl;
127 unsigned long ch_cfg;
128 struct pnx4008_dma_ll *ll;
129 u32 ll_dma;
130 int flags;
131 void *alloc_data;
132 int (*free) (void *);
133};
134
135extern struct pnx4008_dma_ll *pnx4008_alloc_ll_entry(dma_addr_t *);
136extern void pnx4008_free_ll_entry(struct pnx4008_dma_ll *, dma_addr_t);
137extern void pnx4008_free_ll(u32 ll_dma, struct pnx4008_dma_ll *);
138
139extern int pnx4008_request_channel(char *, int,
140 void (*)(int, int, void *, struct pt_regs *),
141 void *);
142extern void pnx4008_free_channel(int);
143extern int pnx4008_config_dma(int, int, int);
144extern int pnx4008_dma_pack_control(const struct pnx4008_dma_ch_ctrl *,
145 unsigned long *);
146extern int pnx4008_dma_parse_control(unsigned long,
147 struct pnx4008_dma_ch_ctrl *);
148extern int pnx4008_dma_pack_config(const struct pnx4008_dma_ch_config *,
149 unsigned long *);
150extern int pnx4008_dma_parse_config(unsigned long,
151 struct pnx4008_dma_ch_config *);
152extern int pnx4008_config_channel(int, struct pnx4008_dma_config *);
153extern int pnx4008_channel_get_config(int, struct pnx4008_dma_config *);
154extern int pnx4008_dma_ch_enable(int);
155extern int pnx4008_dma_ch_disable(int);
156extern int pnx4008_dma_ch_enabled(int);
157extern void pnx4008_dma_split_head_entry(struct pnx4008_dma_config *,
158 struct pnx4008_dma_ch_ctrl *);
159extern void pnx4008_dma_split_ll_entry(struct pnx4008_dma_ll *,
160 struct pnx4008_dma_ch_ctrl *);
161
162#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-pnx4008/entry-macro.S b/include/asm-arm/arch-pnx4008/entry-macro.S
new file mode 100644
index 000000000000..c1c198e3680b
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/entry-macro.S
@@ -0,0 +1,121 @@
1/*
2 * include/asm-arm/arch-pnx4008/entry-macro.S
3 *
4 * Low-level IRQ helper macros for PNX4008-based platforms
5 *
6 * 2005-2006 (c) MontaVista Software, Inc.
7 * Author: Vitaly Wool <vwool@ru.mvista.com>
8 * This file is licensed under the terms of the GNU General Public
9 * License version 2. This program is licensed "as is" without any
10 * warranty of any kind, whether express or implied.
11 */
12
13#include "platform.h"
14
15#define IO_BASE 0xF0000000
16#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
17
18#define INTRC_MASK 0x00
19#define INTRC_RAW_STAT 0x04
20#define INTRC_STAT 0x08
21#define INTRC_POLAR 0x0C
22#define INTRC_ACT_TYPE 0x10
23#define INTRC_TYPE 0x14
24
25#define SIC1_BASE_INT 32
26#define SIC2_BASE_INT 64
27
28 .macro disable_fiq
29 .endm
30
31 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
32/* decode the MIC interrupt numbers */
33 ldr \base, =IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
34 ldr \irqstat, [\base, #INTRC_STAT]
35
36 cmp \irqstat,#1<<16
37 movhs \irqnr,#16
38 movlo \irqnr,#0
39 movhs \irqstat,\irqstat,lsr#16
40 cmp \irqstat,#1<<8
41 addhs \irqnr,\irqnr,#8
42 movhs \irqstat,\irqstat,lsr#8
43 cmp \irqstat,#1<<4
44 addhs \irqnr,\irqnr,#4
45 movhs \irqstat,\irqstat,lsr#4
46 cmp \irqstat,#1<<2
47 addhs \irqnr,\irqnr,#2
48 movhs \irqstat,\irqstat,lsr#2
49 cmp \irqstat,#1<<1
50 addhs \irqnr,\irqnr,#1
51
52/* was there an interrupt ? if not then drop out with EQ status */
53 teq \irqstat,#0
54 beq 1003f
55
56/* and now check for extended IRQ reasons */
57 cmp \irqnr,#1
58 bls 1003f
59 cmp \irqnr,#30
60 blo 1002f
61
62/* IRQ 31,30 : High priority cascade IRQ handle */
63/* read the correct SIC */
64/* decoding status after compare : eq is 30 (SIC1) , ne is 31 (SIC2) */
65/* set the base IRQ number */
66 ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
67 moveq \irqnr,#SIC1_BASE_INT
68 ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
69 movne \irqnr,#SIC2_BASE_INT
70 ldr \irqstat, [\base, #INTRC_STAT]
71 ldr \tmp, [\base, #INTRC_TYPE]
72/* and with inverted mask : low priority interrupts */
73 and \irqstat,\irqstat,\tmp
74 b 1004f
75
761003:
77/* IRQ 1,0 : Low priority cascade IRQ handle */
78/* read the correct SIC */
79/* decoding status after compare : eq is 1 (SIC2) , ne is 0 (SIC1)*/
80/* read the correct SIC */
81/* set the base IRQ number */
82 ldrne \base, =IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
83 movne \irqnr,#SIC1_BASE_INT
84 ldreq \base, =IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
85 moveq \irqnr,#SIC2_BASE_INT
86 ldr \irqstat, [\base, #INTRC_STAT]
87 ldr \tmp, [\base, #INTRC_TYPE]
88/* and with inverted mask : low priority interrupts */
89 bic \irqstat,\irqstat,\tmp
90
911004:
92
93 cmp \irqstat,#1<<16
94 addhs \irqnr,\irqnr,#16
95 movhs \irqstat,\irqstat,lsr#16
96 cmp \irqstat,#1<<8
97 addhs \irqnr,\irqnr,#8
98 movhs \irqstat,\irqstat,lsr#8
99 cmp \irqstat,#1<<4
100 addhs \irqnr,\irqnr,#4
101 movhs \irqstat,\irqstat,lsr#4
102 cmp \irqstat,#1<<2
103 addhs \irqnr,\irqnr,#2
104 movhs \irqstat,\irqstat,lsr#2
105 cmp \irqstat,#1<<1
106 addhs \irqnr,\irqnr,#1
107
108
109/* is irqstat not zero */
110
1111002:
112/* we assert that irqstat is not equal to zero and return ne status if true*/
113 teq \irqstat,#0
1141003:
115 .endm
116
117
118 .macro irq_prio_table
119 .endm
120
121
diff --git a/include/asm-arm/arch-pnx4008/gpio.h b/include/asm-arm/arch-pnx4008/gpio.h
new file mode 100644
index 000000000000..1fa5a77c3010
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/gpio.h
@@ -0,0 +1,139 @@
1/*
2 * include/asm-arm/arch-pnx4008/gpio.h
3 *
4 * PNX4008 GPIO driver - header file
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * Based on reference code by Iwo Mergler and Z.Tabaaloute from Philips:
9 * Copyright (c) 2005 Koninklijke Philips Electronics N.V.
10 *
11 * 2005 (c) MontaVista Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16
17#ifndef _PNX4008_GPIO_H_
18#define _PNX4008_GPIO_H_
19
20
21/* Block numbers */
22#define GPIO_IN (0)
23#define GPIO_OUT (0x100)
24#define GPIO_BID (0x200)
25#define GPIO_RAM (0x300)
26#define GPIO_MUX (0x400)
27
28#define GPIO_TYPE_MASK(K) ((K) & 0x700)
29
30/* INPUT GPIOs */
31/* GPI */
32#define GPI_00 (GPIO_IN | 0)
33#define GPI_01 (GPIO_IN | 1)
34#define GPI_02 (GPIO_IN | 2)
35#define GPI_03 (GPIO_IN | 3)
36#define GPI_04 (GPIO_IN | 4)
37#define GPI_05 (GPIO_IN | 5)
38#define GPI_06 (GPIO_IN | 6)
39#define GPI_07 (GPIO_IN | 7)
40#define GPI_08 (GPIO_IN | 8)
41#define GPI_09 (GPIO_IN | 9)
42#define U1_RX (GPIO_IN | 15)
43#define U2_HTCS (GPIO_IN | 16)
44#define U2_RX (GPIO_IN | 17)
45#define U3_RX (GPIO_IN | 18)
46#define U4_RX (GPIO_IN | 19)
47#define U5_RX (GPIO_IN | 20)
48#define U6_IRRX (GPIO_IN | 21)
49#define U7_HCTS (GPIO_IN | 22)
50#define U7_RX (GPIO_IN | 23)
51/* MISC IN */
52#define SPI1_DATIN (GPIO_IN | 25)
53#define DISP_SYNC (GPIO_IN | 26)
54#define SPI2_DATIN (GPIO_IN | 27)
55#define GPI_11 (GPIO_IN | 28)
56
57#define GPIO_IN_MASK 0x1eff83ff
58
59/* OUTPUT GPIOs */
60/* GPO */
61#define GPO_00 (GPIO_OUT | 0)
62#define GPO_01 (GPIO_OUT | 1)
63#define GPO_02 (GPIO_OUT | 2)
64#define GPO_03 (GPIO_OUT | 3)
65#define GPO_04 (GPIO_OUT | 4)
66#define GPO_05 (GPIO_OUT | 5)
67#define GPO_06 (GPIO_OUT | 6)
68#define GPO_07 (GPIO_OUT | 7)
69#define GPO_08 (GPIO_OUT | 8)
70#define GPO_09 (GPIO_OUT | 9)
71#define GPO_10 (GPIO_OUT | 10)
72#define GPO_11 (GPIO_OUT | 11)
73#define GPO_12 (GPIO_OUT | 12)
74#define GPO_13 (GPIO_OUT | 13)
75#define GPO_14 (GPIO_OUT | 14)
76#define GPO_15 (GPIO_OUT | 15)
77#define GPO_16 (GPIO_OUT | 16)
78#define GPO_17 (GPIO_OUT | 17)
79#define GPO_18 (GPIO_OUT | 18)
80#define GPO_19 (GPIO_OUT | 19)
81#define GPO_20 (GPIO_OUT | 20)
82#define GPO_21 (GPIO_OUT | 21)
83#define GPO_22 (GPIO_OUT | 22)
84#define GPO_23 (GPIO_OUT | 23)
85
86#define GPIO_OUT_MASK 0xffffff
87
88/* BIDIRECTIONAL GPIOs */
89/* RAM pins */
90#define RAM_D19 (GPIO_RAM | 0)
91#define RAM_D20 (GPIO_RAM | 1)
92#define RAM_D21 (GPIO_RAM | 2)
93#define RAM_D22 (GPIO_RAM | 3)
94#define RAM_D23 (GPIO_RAM | 4)
95#define RAM_D24 (GPIO_RAM | 5)
96#define RAM_D25 (GPIO_RAM | 6)
97#define RAM_D26 (GPIO_RAM | 7)
98#define RAM_D27 (GPIO_RAM | 8)
99#define RAM_D28 (GPIO_RAM | 9)
100#define RAM_D29 (GPIO_RAM | 10)
101#define RAM_D30 (GPIO_RAM | 11)
102#define RAM_D31 (GPIO_RAM | 12)
103
104#define GPIO_RAM_MASK 0x1fff
105
106/* I/O pins */
107#define GPIO_00 (GPIO_BID | 25)
108#define GPIO_01 (GPIO_BID | 26)
109#define GPIO_02 (GPIO_BID | 27)
110#define GPIO_03 (GPIO_BID | 28)
111#define GPIO_04 (GPIO_BID | 29)
112#define GPIO_05 (GPIO_BID | 30)
113
114#define GPIO_BID_MASK 0x7e000000
115
116/* Non-GPIO multiplexed PIOs. For multiplexing with GPIO, please use GPIO macros */
117#define GPIO_SDRAM_SEL (GPIO_MUX | 3)
118
119#define GPIO_MUX_MASK 0x8
120
121/* Extraction/assembly macros */
122#define GPIO_BIT_MASK(K) ((K) & 0x1F)
123#define GPIO_BIT(K) (1 << GPIO_BIT_MASK(K))
124#define GPIO_ISMUX(K) ((GPIO_TYPE_MASK(K) == GPIO_MUX) && (GPIO_BIT(K) & GPIO_MUX_MASK))
125#define GPIO_ISRAM(K) ((GPIO_TYPE_MASK(K) == GPIO_RAM) && (GPIO_BIT(K) & GPIO_RAM_MASK))
126#define GPIO_ISBID(K) ((GPIO_TYPE_MASK(K) == GPIO_BID) && (GPIO_BIT(K) & GPIO_BID_MASK))
127#define GPIO_ISOUT(K) ((GPIO_TYPE_MASK(K) == GPIO_OUT) && (GPIO_BIT(K) & GPIO_OUT_MASK))
128#define GPIO_ISIN(K) ((GPIO_TYPE_MASK(K) == GPIO_IN) && (GPIO_BIT(K) & GPIO_IN_MASK))
129
130extern int pnx4008_gpio_register_pin(unsigned short pin);
131extern int pnx4008_gpio_unregister_pin(unsigned short pin);
132extern unsigned long pnx4008_gpio_read_pin(unsigned short pin);
133extern int pnx4008_gpio_write_pin(unsigned short pin, int output);
134extern int pnx4008_gpio_set_pin_direction(unsigned short pin, int output);
135extern int pnx4008_gpio_read_pin_direction(unsigned short pin);
136extern int pnx4008_gpio_set_pin_mux(unsigned short pin, int output);
137extern int pnx4008_gpio_read_pin_mux(unsigned short pin);
138
139#endif /* _PNX4008_GPIO_H_ */
diff --git a/include/asm-arm/arch-pnx4008/hardware.h b/include/asm-arm/arch-pnx4008/hardware.h
new file mode 100644
index 000000000000..a4410397a921
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/hardware.h
@@ -0,0 +1,32 @@
1/*
2 * linux/include/asm-arm/arch-pnx4008/hardware.h
3 *
4 * Copyright (c) 2005 MontaVista Software, Inc. <source@mvista.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_HARDWARE_H
21#define __ASM_ARCH_HARDWARE_H
22
23#include <asm/sizes.h>
24#include <asm/arch/platform.h>
25
26/* Start of virtual addresses for IO devices */
27#define IO_BASE 0xF0000000
28
29/* This macro relies on fact that for all HW i/o addresses bits 20-23 are 0 */
30#define IO_ADDRESS(x) (((((x) & 0xff000000) >> 4) | ((x) & 0xfffff)) | IO_BASE)
31
32#endif
diff --git a/include/asm-arm/arch-pnx4008/io.h b/include/asm-arm/arch-pnx4008/io.h
new file mode 100644
index 000000000000..29ee43955c52
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/io.h
@@ -0,0 +1,21 @@
1
2/*
3 * include/asm-arm/arch-pnx4008/io.h
4 *
5 * Author: Dmitry Chigirev <chigirev@ru.mvista.com>
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13#ifndef __ASM_ARM_ARCH_IO_H
14#define __ASM_ARM_ARCH_IO_H
15
16#define IO_SPACE_LIMIT 0xffffffff
17
18#define __io(a) ((void __iomem *)(a))
19#define __mem_pci(a) (a)
20
21#endif
diff --git a/include/asm-arm/arch-pnx4008/irq.h b/include/asm-arm/arch-pnx4008/irq.h
new file mode 100644
index 000000000000..fabff5dc337f
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/irq.h
@@ -0,0 +1,42 @@
1/*
2 * include/asm-arm/arch-pnx4008/irq.h
3 *
4 * PNX4008 IRQ controller driver - header file
5 * this one is used in entry-arnv.S as well so it cannot contain C code
6 *
7 * Copyright (c) 2005 Philips Semiconductors
8 * Copyright (c) 2005 MontaVista Software, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef __PNX4008_IRQ_H__
16#define __PNX4008_IRQ_H__
17
18#define MIC_VA_BASE IO_ADDRESS(PNX4008_INTCTRLMIC_BASE)
19#define SIC1_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC1_BASE)
20#define SIC2_VA_BASE IO_ADDRESS(PNX4008_INTCTRLSIC2_BASE)
21
22/* Manual: Chapter 20, page 195 */
23
24#define INTC_BIT(irq) (1<< ((irq) & 0x1F))
25
26#define INTC_ER(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x0 + (((irq)&(0x3<<5))<<9)))
27#define INTC_RSR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x4 + (((irq)&(0x3<<5))<<9)))
28#define INTC_SR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x8 + (((irq)&(0x3<<5))<<9)))
29#define INTC_APR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0xC + (((irq)&(0x3<<5))<<9)))
30#define INTC_ATR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x10 + (((irq)&(0x3<<5))<<9)))
31#define INTC_ITR(irq) IO_ADDRESS((PNX4008_INTCTRLMIC_BASE + 0x14 + (((irq)&(0x3<<5))<<9)))
32
33#define START_INT_REG_BIT(irq) (1<<((irq)&0x1F))
34
35#define START_INT_ER_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x20 + (((irq)&(0x1<<5))>>1)))
36#define START_INT_RSR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x24 + (((irq)&(0x1<<5))>>1)))
37#define START_INT_SR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x28 + (((irq)&(0x1<<5))>>1)))
38#define START_INT_APR_REG(irq) IO_ADDRESS((PNX4008_PWRMAN_BASE + 0x2C + (((irq)&(0x1<<5))>>1)))
39
40extern void __init pnx4008_init_irq(void);
41
42#endif /* __PNX4008_IRQ_H__ */
diff --git a/include/asm-arm/arch-pnx4008/irqs.h b/include/asm-arm/arch-pnx4008/irqs.h
new file mode 100644
index 000000000000..13ec7ed0f501
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/irqs.h
@@ -0,0 +1,215 @@
1/*
2 * include/asm-arm/arch-pnx4008/irqs.h
3 *
4 * PNX4008 IRQ controller driver - header file
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13#ifndef __PNX4008_IRQS_h__
14#define __PNX4008_IRQS_h__
15
16#define NR_IRQS 96
17
18/*Manual: table 259, page 199*/
19
20/*SUB2 Interrupt Routing (SIC2)*/
21
22#define SIC2_BASE_INT 64
23
24#define CLK_SWITCH_ARM_INT 95 /*manual: Clkswitch ARM */
25#define CLK_SWITCH_DSP_INT 94 /*manual: ClkSwitch DSP */
26#define CLK_SWITCH_AUD_INT 93 /*manual: Clkswitch AUD */
27#define GPI_06_INT 92
28#define GPI_05_INT 91
29#define GPI_04_INT 90
30#define GPI_03_INT 89
31#define GPI_02_INT 88
32#define GPI_01_INT 87
33#define GPI_00_INT 86
34#define BT_CLKREQ_INT 85
35#define SPI1_DATIN_INT 84
36#define U5_RX_INT 83
37#define SDIO_INT_N 82
38#define CAM_HS_INT 81
39#define CAM_VS_INT 80
40#define GPI_07_INT 79
41#define DISP_SYNC_INT 78
42#define DSP_INT8 77
43#define U7_HCTS_INT 76
44#define GPI_10_INT 75
45#define GPI_09_INT 74
46#define GPI_08_INT 73
47#define DSP_INT7 72
48#define U2_HCTS_INT 71
49#define SPI2_DATIN_INT 70
50#define GPIO_05_INT 69
51#define GPIO_04_INT 68
52#define GPIO_03_INT 67
53#define GPIO_02_INT 66
54#define GPIO_01_INT 65
55#define GPIO_00_INT 64
56
57/*Manual: table 258, page 198*/
58
59/*SUB1 Interrupt Routing (SIC1)*/
60
61#define SIC1_BASE_INT 32
62
63#define USB_I2C_INT 63
64#define USB_DEV_HP_INT 62
65#define USB_DEV_LP_INT 61
66#define USB_DEV_DMA_INT 60
67#define USB_HOST_INT 59
68#define USB_OTG_ATX_INT_N 58
69#define USB_OTG_TIMER_INT 57
70#define SW_INT 56
71#define SPI1_INT 55
72#define KEY_IRQ 54
73#define DSP_M_INT 53
74#define RTC_INT 52
75#define I2C_1_INT 51
76#define I2C_2_INT 50
77#define PLL1_LOCK_INT 49
78#define PLL2_LOCK_INT 48
79#define PLL3_LOCK_INT 47
80#define PLL4_LOCK_INT 46
81#define PLL5_LOCK_INT 45
82#define SPI2_INT 44
83#define DSP_INT1 43
84#define DSP_INT2 42
85#define DSP_TDM_INT2 41
86#define TS_AUX_INT 40
87#define TS_IRQ 39
88#define TS_P_INT 38
89#define UOUT1_TO_PAD_INT 37
90#define GPI_11_INT 36
91#define DSP_INT4 35
92#define JTAG_COMM_RX_INT 34
93#define JTAG_COMM_TX_INT 33
94#define DSP_INT3 32
95
96/*Manual: table 257, page 197*/
97
98/*MAIN Interrupt Routing*/
99
100#define MAIN_BASE_INT 0
101
102#define SUB2_FIQ_N 31 /*active low */
103#define SUB1_FIQ_N 30 /*active low */
104#define JPEG_INT 29
105#define DMA_INT 28
106#define MSTIMER_INT 27
107#define IIR1_INT 26
108#define IIR2_INT 25
109#define IIR7_INT 24
110#define DSP_TDM_INT0 23
111#define DSP_TDM_INT1 22
112#define DSP_P_INT 21
113#define DSP_INT0 20
114#define DUM_INT 19
115#define UOUT0_TO_PAD_INT 18
116#define MP4_ENC_INT 17
117#define MP4_DEC_INT 16
118#define SD0_INT 15
119#define MBX_INT 14
120#define SD1_INT 13
121#define MS_INT_N 12
122#define FLASH_INT 11 /*NAND*/
123#define IIR6_INT 10
124#define IIR5_INT 9
125#define IIR4_INT 8
126#define IIR3_INT 7
127#define WATCH_INT 6
128#define HSTIMER_INT 5
129#define ARCH_TIMER_IRQ HSTIMER_INT
130#define CAM_INT 4
131#define PRNG_INT 3
132#define CRYPTO_INT 2
133#define SUB2_IRQ_N 1 /*active low */
134#define SUB1_IRQ_N 0 /*active low */
135
136#define PNX4008_IRQ_TYPES \
137{ /*IRQ #'s: */ \
138IRQT_LOW, IRQT_LOW, IRQT_LOW, IRQT_HIGH, /* 0, 1, 2, 3 */ \
139IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 4, 5, 6, 7 */ \
140IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 8, 9,10,11 */ \
141IRQT_LOW, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 12,13,14,15 */ \
142IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 16,17,18,19 */ \
143IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 20,21,22,23 */ \
144IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 24,25,26,27 */ \
145IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 28,29,30,31 */ \
146IRQT_HIGH, IRQT_LOW, IRQT_HIGH, IRQT_HIGH, /* 32,33,34,35 */ \
147IRQT_HIGH, IRQT_HIGH, IRQT_FALLING, IRQT_HIGH, /* 36,37,38,39 */ \
148IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 40,41,42,43 */ \
149IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 44,45,46,47 */ \
150IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_LOW, /* 48,49,50,51 */ \
151IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 52,53,54,55 */ \
152IRQT_HIGH, IRQT_HIGH, IRQT_LOW, IRQT_HIGH, /* 56,57,58,59 */ \
153IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 60,61,62,63 */ \
154IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 64,65,66,67 */ \
155IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 68,69,70,71 */ \
156IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 72,73,74,75 */ \
157IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 76,77,78,79 */ \
158IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 80,81,82,83 */ \
159IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 84,85,86,87 */ \
160IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 88,89,90,91 */ \
161IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, IRQT_HIGH, /* 92,93,94,95 */ \
162}
163
164/* Start Enable Pin Interrupts - table 58 page 66 */
165
166#define SE_PIN_BASE_INT 32
167
168#define SE_U7_RX_INT 63
169#define SE_U7_HCTS_INT 62
170#define SE_BT_CLKREQ_INT 61
171#define SE_U6_IRRX_INT 60
172/*59 unused*/
173#define SE_U5_RX_INT 58
174#define SE_GPI_11_INT 57
175#define SE_U3_RX_INT 56
176#define SE_U2_HCTS_INT 55
177#define SE_U2_RX_INT 54
178#define SE_U1_RX_INT 53
179#define SE_DISP_SYNC_INT 52
180/*51 unused*/
181#define SE_SDIO_INT_N 50
182#define SE_MSDIO_START_INT 49
183#define SE_GPI_06_INT 48
184#define SE_GPI_05_INT 47
185#define SE_GPI_04_INT 46
186#define SE_GPI_03_INT 45
187#define SE_GPI_02_INT 44
188#define SE_GPI_01_INT 43
189#define SE_GPI_00_INT 42
190#define SE_SYSCLKEN_PIN_INT 41
191#define SE_SPI1_DATAIN_INT 40
192#define SE_GPI_07_INT 39
193#define SE_SPI2_DATAIN_INT 38
194#define SE_GPI_10_INT 37
195#define SE_GPI_09_INT 36
196#define SE_GPI_08_INT 35
197/*34-32 unused*/
198
199/* Start Enable Internal Interrupts - table 57 page 65 */
200
201#define SE_INT_BASE_INT 0
202
203#define SE_TS_IRQ 31
204#define SE_TS_P_INT 30
205#define SE_TS_AUX_INT 29
206/*27-28 unused*/
207#define SE_USB_AHB_NEED_CLK_INT 26
208#define SE_MSTIMER_INT 25
209#define SE_RTC_INT 24
210#define SE_USB_NEED_CLK_INT 23
211#define SE_USB_INT 22
212#define SE_USB_I2C_INT 21
213#define SE_USB_OTG_TIMER_INT 20
214
215#endif /* __PNX4008_IRQS_h__ */
diff --git a/include/asm-arm/arch-pnx4008/memory.h b/include/asm-arm/arch-pnx4008/memory.h
new file mode 100644
index 000000000000..0d8268a95261
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/memory.h
@@ -0,0 +1,24 @@
1/*
2 * linux/include/asm-arm/arch-pnx4008/memory.h
3 *
4 * Copyright (c) 2005 Philips Semiconductors
5 * Copyright (c) 2005 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16/*
17 * Physical DRAM offset.
18 */
19#define PHYS_OFFSET (0x80000000)
20
21#define __virt_to_bus(x) ((x) - PAGE_OFFSET + PHYS_OFFSET)
22#define __bus_to_virt(x) ((x) + PAGE_OFFSET - PHYS_OFFSET)
23
24#endif
diff --git a/include/asm-arm/arch-pnx4008/param.h b/include/asm-arm/arch-pnx4008/param.h
new file mode 100644
index 000000000000..95d5f547b416
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/param.h
@@ -0,0 +1,21 @@
1/*
2 * linux/include/asm-arm/arch-pnx4008/param.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#define HZ 100
diff --git a/include/asm-arm/arch-pnx4008/platform.h b/include/asm-arm/arch-pnx4008/platform.h
new file mode 100644
index 000000000000..485a3651b4d7
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/platform.h
@@ -0,0 +1,69 @@
1/*
2 * include/asm-arm/arch-pnx4008/platfrom.h
3 *
4 * PNX4008 Base addresses - header file
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * Based on reference code received from Philips:
9 * Copyright (C) 2003 Philips Semiconductors
10 *
11 * 2005 (c) MontaVista Software, Inc. This file is licensed under
12 * the terms of the GNU General Public License version 2. This program
13 * is licensed "as is" without any warranty of any kind, whether express
14 * or implied.
15 */
16
17
18#ifndef __ASM_ARCH_PLATFORM_H__
19#define __ASM_ARCH_PLATFORM_H__
20
21#define PNX4008_IRAM_BASE 0x08000000
22#define PNX4008_IRAM_SIZE 0x00010000
23#define PNX4008_YUV_SLAVE_BASE 0x10000000
24#define PNX4008_DUM_SLAVE_BASE 0x18000000
25#define PNX4008_NDF_FLASH_BASE 0x20020000
26#define PNX4008_SPI1_BASE 0x20088000
27#define PNX4008_SPI2_BASE 0x20090000
28#define PNX4008_SD_CONFIG_BASE 0x20098000
29#define PNX4008_FLASH_DATA 0x200B0000
30#define PNX4008_MLC_FLASH_BASE 0x200B8000
31#define PNX4008_JPEG_CONFIG_BASE 0x300A0000
32#define PNX4008_DMA_CONFIG_BASE 0x31000000
33#define PNX4008_USB_CONFIG_BASE 0x31020000
34#define PNX4008_SDRAM_CFG_BASE 0x31080000
35#define PNX4008_AHB2FAB_BASE 0x40000000
36#define PNX4008_PWRMAN_BASE 0x40004000
37#define PNX4008_INTCTRLMIC_BASE 0x40008000
38#define PNX4008_INTCTRLSIC1_BASE 0x4000C000
39#define PNX4008_INTCTRLSIC2_BASE 0x40010000
40#define PNX4008_HSUART1_BASE 0x40014000
41#define PNX4008_HSUART2_BASE 0x40018000
42#define PNX4008_HSUART7_BASE 0x4001C000
43#define PNX4008_RTC_BASE 0x40024000
44#define PNX4008_PIO_BASE 0x40028000
45#define PNX4008_MSTIMER_BASE 0x40034000
46#define PNX4008_HSTIMER_BASE 0x40038000
47#define PNX4008_WDOG_BASE 0x4003C000
48#define PNX4008_DEBUG_BASE 0x40040000
49#define PNX4008_TOUCH1_BASE 0x40048000
50#define PNX4008_KEYSCAN_BASE 0x40050000
51#define PNX4008_UARTCTRL_BASE 0x40054000
52#define PNX4008_PWM_BASE 0x4005C000
53#define PNX4008_UART3_BASE 0x40080000
54#define PNX4008_UART4_BASE 0x40088000
55#define PNX4008_UART5_BASE 0x40090000
56#define PNX4008_UART6_BASE 0x40098000
57#define PNX4008_I2C1_BASE 0x400A0000
58#define PNX4008_I2C2_BASE 0x400A8000
59#define PNX4008_MAGICGATE_BASE 0x400B0000
60#define PNX4008_DUMCONF_BASE 0x400B8000
61#define PNX4008_DUM_MAINCFG_BASE 0x400BC000
62#define PNX4008_DSP_BASE 0x400C0000
63#define PNX4008_PROFCOUNTER_BASE 0x400C8000
64#define PNX4008_CRYPTO_BASE 0x400D0000
65#define PNX4008_CAMIFCONF_BASE 0x400D8000
66#define PNX4008_YUV2RGB_BASE 0x400E0000
67#define PNX4008_AUDIOCONFIG_BASE 0x400E8000
68
69#endif
diff --git a/include/asm-arm/arch-pnx4008/pm.h b/include/asm-arm/arch-pnx4008/pm.h
new file mode 100644
index 000000000000..c660486670fb
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/pm.h
@@ -0,0 +1,62 @@
1/*
2 * include/asm-arm/arch-pnx4008/pm.h
3 *
4 * PNX4008 Power Management Routiness - header file
5 *
6 * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#ifndef __ASM_ARCH_PNX4008_PM_H
15#define __ASM_ARCH_PNX4008_PM_H
16
17#ifndef __ASSEMBLER__
18#include "irq.h"
19#include "irqs.h"
20#include "clock.h"
21
22extern void pnx4008_pm_idle(void);
23extern void pnx4008_pm_suspend(void);
24extern unsigned int pnx4008_cpu_suspend_sz;
25extern void pnx4008_cpu_suspend(void);
26extern unsigned int pnx4008_cpu_standby_sz;
27extern void pnx4008_cpu_standby(void);
28
29extern int pnx4008_startup_pll(struct clk *);
30extern int pnx4008_shutdown_pll(struct clk *);
31
32static inline void start_int_umask(u8 irq)
33{
34 __raw_writel(__raw_readl(START_INT_ER_REG(irq)) |
35 START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
36}
37
38static inline void start_int_mask(u8 irq)
39{
40 __raw_writel(__raw_readl(START_INT_ER_REG(irq)) &
41 ~START_INT_REG_BIT(irq), START_INT_ER_REG(irq));
42}
43
44static inline void start_int_ack(u8 irq)
45{
46 __raw_writel(START_INT_REG_BIT(irq), START_INT_RSR_REG(irq));
47}
48
49static inline void start_int_set_falling_edge(u8 irq)
50{
51 __raw_writel(__raw_readl(START_INT_APR_REG(irq)) &
52 ~START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
53}
54
55static inline void start_int_set_rising_edge(u8 irq)
56{
57 __raw_writel(__raw_readl(START_INT_APR_REG(irq)) |
58 START_INT_REG_BIT(irq), START_INT_APR_REG(irq));
59}
60
61#endif /* ASSEMBLER */
62#endif /* __ASM_ARCH_PNX4008_PM_H */
diff --git a/include/asm-arm/arch-pnx4008/system.h b/include/asm-arm/arch-pnx4008/system.h
new file mode 100644
index 000000000000..6e3da70ab107
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/system.h
@@ -0,0 +1,38 @@
1/*
2 * linux/include/asm-arm/arch-pnx4008/system.h
3 *
4 * Copyright (C) 2003 Philips Semiconductors
5 * Copyright (C) 2005 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_SYSTEM_H
22#define __ASM_ARCH_SYSTEM_H
23
24#include <asm/hardware.h>
25#include <asm/io.h>
26#include <asm/arch/platform.h>
27
28static void arch_idle(void)
29{
30 cpu_do_idle();
31}
32
33static inline void arch_reset(char mode)
34{
35 cpu_reset(0);
36}
37
38#endif
diff --git a/include/asm-arm/arch-pnx4008/timex.h b/include/asm-arm/arch-pnx4008/timex.h
new file mode 100644
index 000000000000..ee470a39089a
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/timex.h
@@ -0,0 +1,73 @@
1/*
2 * include/asm-arm/arch-pnx4008/timex.h
3 *
4 * PNX4008 timers header file
5 *
6 * Author: Dmitry Chigirev <source@mvista.com>
7 *
8 * 2005 (c) MontaVista Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2. This program
10 * is licensed "as is" without any warranty of any kind, whether express
11 * or implied.
12 */
13
14#ifndef __PNX4008_TIMEX_H
15#define __PNX4008_TIMEX_H
16
17#include <asm/hardware.h>
18#include <asm/io.h>
19
20#define CLOCK_TICK_RATE 1000000
21
22#define TICKS2USECS(x) (x)
23
24/* MilliSecond Timer - Chapter 21 Page 202 */
25
26#define MSTIM_INT IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x0))
27#define MSTIM_CTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x4))
28#define MSTIM_COUNTER IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x8))
29#define MSTIM_MCTRL IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x14))
30#define MSTIM_MATCH0 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x18))
31#define MSTIM_MATCH1 IO_ADDRESS((PNX4008_MSTIMER_BASE + 0x1c))
32
33/* High Speed Timer - Chpater 22, Page 205 */
34
35#define HSTIM_INT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x0))
36#define HSTIM_CTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x4))
37#define HSTIM_COUNTER IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x8))
38#define HSTIM_PMATCH IO_ADDRESS((PNX4008_HSTIMER_BASE + 0xC))
39#define HSTIM_PCOUNT IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x10))
40#define HSTIM_MCTRL IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x14))
41#define HSTIM_MATCH0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x18))
42#define HSTIM_MATCH1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x1c))
43#define HSTIM_MATCH2 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x20))
44#define HSTIM_CCR IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x28))
45#define HSTIM_CR0 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x2C))
46#define HSTIM_CR1 IO_ADDRESS((PNX4008_HSTIMER_BASE + 0x30))
47
48/* IMPORTANT: both timers are UPCOUNTING */
49
50/* xSTIM_MCTRL bit definitions */
51#define MR0_INT 1
52#define RESET_COUNT0 (1<<1)
53#define STOP_COUNT0 (1<<2)
54#define MR1_INT (1<<3)
55#define RESET_COUNT1 (1<<4)
56#define STOP_COUNT1 (1<<5)
57#define MR2_INT (1<<6)
58#define RESET_COUNT2 (1<<7)
59#define STOP_COUNT2 (1<<8)
60
61/* xSTIM_CTRL bit definitions */
62#define COUNT_ENAB 1
63#define RESET_COUNT (1<<1)
64#define DEBUG_EN (1<<2)
65
66/* xSTIM_INT bit definitions */
67#define MATCH0_INT 1
68#define MATCH1_INT (1<<1)
69#define MATCH2_INT (1<<2)
70#define RTC_TICK0 (1<<4)
71#define RTC_TICK1 (1<<5)
72
73#endif
diff --git a/include/asm-arm/arch-pnx4008/uncompress.h b/include/asm-arm/arch-pnx4008/uncompress.h
new file mode 100644
index 000000000000..8fa4d24b72b4
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/uncompress.h
@@ -0,0 +1,46 @@
1/*
2 * linux/include/asm-arm/arch-pnx4008/uncompress.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) 2006 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#define UART5_BASE 0x40090000
23
24#define UART5_DR (*(volatile unsigned char *) (UART5_BASE))
25#define UART5_FR (*(volatile unsigned char *) (UART5_BASE + 18))
26
27static __inline__ void putc(char c)
28{
29 while (UART5_FR & (1 << 5))
30 barrier();
31
32 UART5_DR = c;
33}
34
35/*
36 * This does not append a newline
37 */
38static inline void flush(void)
39{
40}
41
42/*
43 * nothing to do
44 */
45#define arch_decomp_setup()
46#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-pnx4008/vmalloc.h b/include/asm-arm/arch-pnx4008/vmalloc.h
new file mode 100644
index 000000000000..140d925f6f37
--- /dev/null
+++ b/include/asm-arm/arch-pnx4008/vmalloc.h
@@ -0,0 +1,20 @@
1/*
2 * include/asm-arm/arch-pnx4008/vmalloc.h
3 *
4 * Author: Vitaly Wool <source@mvista.com>
5 *
6 * 2006 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11
12/*
13 * Just any arbitrary offset to the start of the vmalloc VM area: the
14 * current 8MB value just means that there will be a 8MB "hole" after the
15 * physical memory until the kernel virtual memory starts. That means that
16 * any out-of-bounds memory accesses will hopefully be caught.
17 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
18 * area for the same reason. ;)
19 */
20#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
diff --git a/include/asm-arm/arch-s3c2410/map.h b/include/asm-arm/arch-s3c2410/map.h
index c380d264a847..5e4c8c37bc66 100644
--- a/include/asm-arm/arch-s3c2410/map.h
+++ b/include/asm-arm/arch-s3c2410/map.h
@@ -126,9 +126,18 @@
126#define S3C24XX_SZ_IIS SZ_1M 126#define S3C24XX_SZ_IIS SZ_1M
127 127
128/* GPIO ports */ 128/* GPIO ports */
129#define S3C24XX_VA_GPIO S3C2410_ADDR(0x00E00000) 129
130/* the calculation for the VA of this must ensure that
131 * it is the same distance apart from the UART in the
132 * phsyical address space, as the initial mapping for the IO
133 * is done as a 1:1 maping. This puts it (currently) at
134 * 0xF6800000, which is not in the way of any current mapping
135 * by the base system.
136*/
137
130#define S3C2400_PA_GPIO (0x15600000) 138#define S3C2400_PA_GPIO (0x15600000)
131#define S3C2410_PA_GPIO (0x56000000) 139#define S3C2410_PA_GPIO (0x56000000)
140#define S3C24XX_VA_GPIO ((S3C2410_PA_GPIO - S3C24XX_PA_UART) + S3C24XX_VA_UART)
132#define S3C24XX_SZ_GPIO SZ_1M 141#define S3C24XX_SZ_GPIO SZ_1M
133 142
134/* RTC */ 143/* RTC */
diff --git a/include/asm-arm/arch-s3c2410/regs-clock.h b/include/asm-arm/arch-s3c2410/regs-clock.h
index 34360706e016..6c92faffe985 100644
--- a/include/asm-arm/arch-s3c2410/regs-clock.h
+++ b/include/asm-arm/arch-s3c2410/regs-clock.h
@@ -114,7 +114,7 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
114 114
115#endif /* __ASSEMBLY__ */ 115#endif /* __ASSEMBLY__ */
116 116
117#ifdef CONFIG_CPU_S3C2440 117#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
118 118
119/* extra registers */ 119/* extra registers */
120#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18) 120#define S3C2440_CAMDIVN S3C2410_CLKREG(0x18)
@@ -136,7 +136,9 @@ s3c2410_get_pll(unsigned int pllval, unsigned int baseclk)
136#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9) 136#define S3C2440_CAMDIVN_HCLK4_HALF (1<<9)
137#define S3C2440_CAMDIVN_DVSEN (1<<12) 137#define S3C2440_CAMDIVN_DVSEN (1<<12)
138 138
139#endif /* CONFIG_CPU_S3C2440 */ 139#define S3C2442_CAMDIVN_CAMCLK_DIV3 (1<<5)
140
141#endif /* CONFIG_CPU_S3C2440 or CONFIG_CPU_S3C2442 */
140 142
141 143
142#endif /* __ASM_ARM_REGS_CLOCK */ 144#endif /* __ASM_ARM_REGS_CLOCK */
diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h
index d2574084697f..5f10334f06bf 100644
--- a/include/asm-arm/arch-s3c2410/regs-gpio.h
+++ b/include/asm-arm/arch-s3c2410/regs-gpio.h
@@ -450,12 +450,14 @@
450#define S3C2410_GPD0_OUTP (0x01 << 0) 450#define S3C2410_GPD0_OUTP (0x01 << 0)
451#define S3C2410_GPD0_VD8 (0x02 << 0) 451#define S3C2410_GPD0_VD8 (0x02 << 0)
452#define S3C2400_GPD0_VFRAME (0x02 << 0) 452#define S3C2400_GPD0_VFRAME (0x02 << 0)
453#define S3C2442_GPD0_nSPICS1 (0x03 << 0)
453 454
454#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1) 455#define S3C2410_GPD1 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 1)
455#define S3C2410_GPD1_INP (0x00 << 2) 456#define S3C2410_GPD1_INP (0x00 << 2)
456#define S3C2410_GPD1_OUTP (0x01 << 2) 457#define S3C2410_GPD1_OUTP (0x01 << 2)
457#define S3C2410_GPD1_VD9 (0x02 << 2) 458#define S3C2410_GPD1_VD9 (0x02 << 2)
458#define S3C2400_GPD1_VM (0x02 << 2) 459#define S3C2400_GPD1_VM (0x02 << 2)
460#define S3C2442_GPD1_SPICLK1 (0x03 << 2)
459 461
460#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2) 462#define S3C2410_GPD2 S3C2410_GPIONO(S3C2410_GPIO_BANKD, 2)
461#define S3C2410_GPD2_INP (0x00 << 4) 463#define S3C2410_GPD2_INP (0x00 << 4)
@@ -858,6 +860,7 @@
858#define S3C2410_GPG12_OUTP (0x01 << 24) 860#define S3C2410_GPG12_OUTP (0x01 << 24)
859#define S3C2410_GPG12_EINT20 (0x02 << 24) 861#define S3C2410_GPG12_EINT20 (0x02 << 24)
860#define S3C2410_GPG12_XMON (0x03 << 24) 862#define S3C2410_GPG12_XMON (0x03 << 24)
863#define S3C2442_GPG12_nSPICS0 (0x03 << 24)
861 864
862#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13) 865#define S3C2410_GPG13 S3C2410_GPIONO(S3C2410_GPIO_BANKG, 13)
863#define S3C2410_GPG13_INP (0x00 << 26) 866#define S3C2410_GPG13_INP (0x00 << 26)
@@ -943,6 +946,7 @@
943#define S3C2410_GPH9_INP (0x00 << 18) 946#define S3C2410_GPH9_INP (0x00 << 18)
944#define S3C2410_GPH9_OUTP (0x01 << 18) 947#define S3C2410_GPH9_OUTP (0x01 << 18)
945#define S3C2410_GPH9_CLKOUT0 (0x02 << 18) 948#define S3C2410_GPH9_CLKOUT0 (0x02 << 18)
949#define S3C2442_GPH9_nSPICS0 (0x03 << 18)
946 950
947#define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10) 951#define S3C2410_GPH10 S3C2410_GPIONO(S3C2410_GPIO_BANKH, 10)
948#define S3C2410_GPH10_INP (0x00 << 20) 952#define S3C2410_GPH10_INP (0x00 << 20)
@@ -1051,6 +1055,7 @@
1051#define S3C2410_GSTATUS1_IDMASK (0xffff0000) 1055#define S3C2410_GSTATUS1_IDMASK (0xffff0000)
1052#define S3C2410_GSTATUS1_2410 (0x32410000) 1056#define S3C2410_GSTATUS1_2410 (0x32410000)
1053#define S3C2410_GSTATUS1_2440 (0x32440000) 1057#define S3C2410_GSTATUS1_2440 (0x32440000)
1058#define S3C2410_GSTATUS1_2442 (0x32440aaa)
1054 1059
1055#define S3C2410_GSTATUS2_WTRESET (1<<2) 1060#define S3C2410_GSTATUS2_WTRESET (1<<2)
1056#define S3C2410_GSTATUS2_OFFRESET (1<<1) 1061#define S3C2410_GSTATUS2_OFFRESET (1<<1)
diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
index a6f6a0e44afa..bbd9ee1ff75a 100644
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -82,7 +82,8 @@ static void putc(int ch)
82 while (1) { 82 while (1) {
83 level = uart_rd(S3C2410_UFSTAT); 83 level = uart_rd(S3C2410_UFSTAT);
84 84
85 if (cpuid == S3C2410_GSTATUS1_2440) { 85 if (cpuid == S3C2410_GSTATUS1_2440 ||
86 cpuid == S3C2410_GSTATUS1_2442) {
86 level &= S3C2440_UFSTAT_TXMASK; 87 level &= S3C2440_UFSTAT_TXMASK;
87 level >>= S3C2440_UFSTAT_TXSHIFT; 88 level >>= S3C2440_UFSTAT_TXSHIFT;
88 } else { 89 } else {
@@ -130,7 +131,7 @@ static void arch_decomp_wdog_start(void)
130{ 131{
131 __raw_writel(WDOG_COUNT, S3C2410_WTDAT); 132 __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
132 __raw_writel(WDOG_COUNT, S3C2410_WTCNT); 133 __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
133 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON); 134 __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
134} 135}
135 136
136#else 137#else
diff --git a/include/asm-arm/mach/time.h b/include/asm-arm/mach/time.h
index 96c6db7dd0e1..9f28073559e8 100644
--- a/include/asm-arm/mach/time.h
+++ b/include/asm-arm/mach/time.h
@@ -50,6 +50,7 @@ struct sys_timer {
50#define DYN_TICK_ENABLED (1 << 1) 50#define DYN_TICK_ENABLED (1 << 1)
51 51
52struct dyn_tick_timer { 52struct dyn_tick_timer {
53 spinlock_t lock;
53 unsigned int state; /* Current state */ 54 unsigned int state; /* Current state */
54 int (*enable)(void); /* Enables dynamic tick */ 55 int (*enable)(void); /* Enables dynamic tick */
55 int (*disable)(void); /* Disables dynamic tick */ 56 int (*disable)(void); /* Disables dynamic tick */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 06:46:05 -0500