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authorArchit Taneja <architt@codeaurora.org>2014-09-29 00:33:08 -0400
committerVinod Koul <vinod.koul@intel.com>2014-11-17 03:20:40 -0500
commitf43669dee7c76dbf188ac9702b5bd22afc3e5469 (patch)
tree130c064e0bdd38dfde47dc6450e26100eb99a9c3
parentfb93f520e0a5df581f5432bdb901539240391568 (diff)
dmaengine: qcom_bam_dma: Add BAM v1.3.0 support
We currently have register offset information only for BAM IPs with revision 1.4.0. We add register offset table entries for the legacy (v1.3.0) version of BAM IPs found on SoCs like APQ8064 and MSM8960. The register offset table pointers are stored in DT data corresponding to the BAM IP version specified in the compatible string. Reviewed-by: Kumar Gala <galak@codeaurora.org> Reviewed-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
-rw-r--r--drivers/dma/qcom_bam_dma.c58
1 files changed, 50 insertions, 8 deletions
diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
index d8fb4303bade..3122a99ec06b 100644
--- a/drivers/dma/qcom_bam_dma.c
+++ b/drivers/dma/qcom_bam_dma.c
@@ -113,7 +113,36 @@ struct reg_offset_data {
113 unsigned int pipe_mult, evnt_mult, ee_mult; 113 unsigned int pipe_mult, evnt_mult, ee_mult;
114}; 114};
115 115
116static const struct reg_offset_data reg_info[] = { 116static const struct reg_offset_data bam_v1_3_reg_info[] = {
117 [BAM_CTRL] = { 0x0F80, 0x00, 0x00, 0x00 },
118 [BAM_REVISION] = { 0x0F84, 0x00, 0x00, 0x00 },
119 [BAM_NUM_PIPES] = { 0x0FBC, 0x00, 0x00, 0x00 },
120 [BAM_DESC_CNT_TRSHLD] = { 0x0F88, 0x00, 0x00, 0x00 },
121 [BAM_IRQ_SRCS] = { 0x0F8C, 0x00, 0x00, 0x00 },
122 [BAM_IRQ_SRCS_MSK] = { 0x0F90, 0x00, 0x00, 0x00 },
123 [BAM_IRQ_SRCS_UNMASKED] = { 0x0FB0, 0x00, 0x00, 0x00 },
124 [BAM_IRQ_STTS] = { 0x0F94, 0x00, 0x00, 0x00 },
125 [BAM_IRQ_CLR] = { 0x0F98, 0x00, 0x00, 0x00 },
126 [BAM_IRQ_EN] = { 0x0F9C, 0x00, 0x00, 0x00 },
127 [BAM_CNFG_BITS] = { 0x0FFC, 0x00, 0x00, 0x00 },
128 [BAM_IRQ_SRCS_EE] = { 0x1800, 0x00, 0x00, 0x80 },
129 [BAM_IRQ_SRCS_MSK_EE] = { 0x1804, 0x00, 0x00, 0x80 },
130 [BAM_P_CTRL] = { 0x0000, 0x80, 0x00, 0x00 },
131 [BAM_P_RST] = { 0x0004, 0x80, 0x00, 0x00 },
132 [BAM_P_HALT] = { 0x0008, 0x80, 0x00, 0x00 },
133 [BAM_P_IRQ_STTS] = { 0x0010, 0x80, 0x00, 0x00 },
134 [BAM_P_IRQ_CLR] = { 0x0014, 0x80, 0x00, 0x00 },
135 [BAM_P_IRQ_EN] = { 0x0018, 0x80, 0x00, 0x00 },
136 [BAM_P_EVNT_DEST_ADDR] = { 0x102C, 0x00, 0x40, 0x00 },
137 [BAM_P_EVNT_REG] = { 0x1018, 0x00, 0x40, 0x00 },
138 [BAM_P_SW_OFSTS] = { 0x1000, 0x00, 0x40, 0x00 },
139 [BAM_P_DATA_FIFO_ADDR] = { 0x1024, 0x00, 0x40, 0x00 },
140 [BAM_P_DESC_FIFO_ADDR] = { 0x101C, 0x00, 0x40, 0x00 },
141 [BAM_P_EVNT_GEN_TRSHLD] = { 0x1028, 0x00, 0x40, 0x00 },
142 [BAM_P_FIFO_SIZES] = { 0x1020, 0x00, 0x40, 0x00 },
143};
144
145static const struct reg_offset_data bam_v1_4_reg_info[] = {
117 [BAM_CTRL] = { 0x0000, 0x00, 0x00, 0x00 }, 146 [BAM_CTRL] = { 0x0000, 0x00, 0x00, 0x00 },
118 [BAM_REVISION] = { 0x0004, 0x00, 0x00, 0x00 }, 147 [BAM_REVISION] = { 0x0004, 0x00, 0x00, 0x00 },
119 [BAM_NUM_PIPES] = { 0x003C, 0x00, 0x00, 0x00 }, 148 [BAM_NUM_PIPES] = { 0x003C, 0x00, 0x00, 0x00 },
@@ -330,6 +359,8 @@ struct bam_device {
330 /* execution environment ID, from DT */ 359 /* execution environment ID, from DT */
331 u32 ee; 360 u32 ee;
332 361
362 const struct reg_offset_data *layout;
363
333 struct clk *bamclk; 364 struct clk *bamclk;
334 int irq; 365 int irq;
335 366
@@ -346,7 +377,7 @@ struct bam_device {
346static inline void __iomem *bam_addr(struct bam_device *bdev, u32 pipe, 377static inline void __iomem *bam_addr(struct bam_device *bdev, u32 pipe,
347 enum bam_reg reg) 378 enum bam_reg reg)
348{ 379{
349 const struct reg_offset_data r = reg_info[reg]; 380 const struct reg_offset_data r = bdev->layout[reg];
350 381
351 return bdev->regs + r.base_offset + 382 return bdev->regs + r.base_offset +
352 r.pipe_mult * pipe + 383 r.pipe_mult * pipe +
@@ -1019,9 +1050,18 @@ static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan,
1019 bchan->vc.desc_free = bam_dma_free_desc; 1050 bchan->vc.desc_free = bam_dma_free_desc;
1020} 1051}
1021 1052
1053static const struct of_device_id bam_of_match[] = {
1054 { .compatible = "qcom,bam-v1.3.0", .data = &bam_v1_3_reg_info },
1055 { .compatible = "qcom,bam-v1.4.0", .data = &bam_v1_4_reg_info },
1056 {}
1057};
1058
1059MODULE_DEVICE_TABLE(of, bam_of_match);
1060
1022static int bam_dma_probe(struct platform_device *pdev) 1061static int bam_dma_probe(struct platform_device *pdev)
1023{ 1062{
1024 struct bam_device *bdev; 1063 struct bam_device *bdev;
1064 const struct of_device_id *match;
1025 struct resource *iores; 1065 struct resource *iores;
1026 int ret, i; 1066 int ret, i;
1027 1067
@@ -1031,6 +1071,14 @@ static int bam_dma_probe(struct platform_device *pdev)
1031 1071
1032 bdev->dev = &pdev->dev; 1072 bdev->dev = &pdev->dev;
1033 1073
1074 match = of_match_node(bam_of_match, pdev->dev.of_node);
1075 if (!match) {
1076 dev_err(&pdev->dev, "Unsupported BAM module\n");
1077 return -ENODEV;
1078 }
1079
1080 bdev->layout = match->data;
1081
1034 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1082 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1035 bdev->regs = devm_ioremap_resource(&pdev->dev, iores); 1083 bdev->regs = devm_ioremap_resource(&pdev->dev, iores);
1036 if (IS_ERR(bdev->regs)) 1084 if (IS_ERR(bdev->regs))
@@ -1154,12 +1202,6 @@ static int bam_dma_remove(struct platform_device *pdev)
1154 return 0; 1202 return 0;
1155} 1203}
1156 1204
1157static const struct of_device_id bam_of_match[] = {
1158 { .compatible = "qcom,bam-v1.4.0", },
1159 {}
1160};
1161MODULE_DEVICE_TABLE(of, bam_of_match);
1162
1163static struct platform_driver bam_dma_driver = { 1205static struct platform_driver bam_dma_driver = {
1164 .probe = bam_dma_probe, 1206 .probe = bam_dma_probe,
1165 .remove = bam_dma_remove, 1207 .remove = bam_dma_remove,