diff options
author | Tony Lindgren <tony@atomide.com> | 2015-05-11 16:23:19 -0400 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2015-05-11 16:23:19 -0400 |
commit | e60a8fe1792dcd3aacda0959e0f4865bfefb7bb5 (patch) | |
tree | 834baff6e4f9ddd11ef3489dbbfa205ebb699347 | |
parent | b0897972edfa42b4af5c3189b2b7a7fac5867828 (diff) | |
parent | a5bf00cd735fbc293da8a9bada589c02861c8132 (diff) |
Merge tag 'for-v4.1-rc/omap-fixes-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v4.1/fixes
ARM: OMAP2+: first set of hwmod fixes for v4.1-rc
Fix a few AM43xx problems: add the VPFE hwmod data, which removes some
warnings; and fix the IP block hardreset implementation.
Basic build, boot, and PM test results are here:
http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.1-rc/20150508130543/
Note that I do not have an AM43xx board in the testbed, and thus
cannot test on that platform.
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod.c | 68 | ||||
-rw-r--r-- | arch/arm/mach-omap2/omap_hwmod_43xx_data.c | 70 | ||||
-rw-r--r-- | arch/arm/mach-omap2/prcm43xx.h | 3 | ||||
-rw-r--r-- | arch/arm/mach-omap2/prminst44xx.c | 20 |
4 files changed, 93 insertions, 68 deletions
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 355b08936871..752969ff9de0 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c | |||
@@ -171,6 +171,12 @@ | |||
171 | */ | 171 | */ |
172 | #define LINKS_PER_OCP_IF 2 | 172 | #define LINKS_PER_OCP_IF 2 |
173 | 173 | ||
174 | /* | ||
175 | * Address offset (in bytes) between the reset control and the reset | ||
176 | * status registers: 4 bytes on OMAP4 | ||
177 | */ | ||
178 | #define OMAP4_RST_CTRL_ST_OFFSET 4 | ||
179 | |||
174 | /** | 180 | /** |
175 | * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations | 181 | * struct omap_hwmod_soc_ops - fn ptrs for some SoC-specific operations |
176 | * @enable_module: function to enable a module (via MODULEMODE) | 182 | * @enable_module: function to enable a module (via MODULEMODE) |
@@ -3016,10 +3022,12 @@ static int _omap4_deassert_hardreset(struct omap_hwmod *oh, | |||
3016 | if (ohri->st_shift) | 3022 | if (ohri->st_shift) |
3017 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", | 3023 | pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n", |
3018 | oh->name, ohri->name); | 3024 | oh->name, ohri->name); |
3019 | return omap_prm_deassert_hardreset(ohri->rst_shift, 0, | 3025 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->rst_shift, |
3020 | oh->clkdm->pwrdm.ptr->prcm_partition, | 3026 | oh->clkdm->pwrdm.ptr->prcm_partition, |
3021 | oh->clkdm->pwrdm.ptr->prcm_offs, | 3027 | oh->clkdm->pwrdm.ptr->prcm_offs, |
3022 | oh->prcm.omap4.rstctrl_offs, 0); | 3028 | oh->prcm.omap4.rstctrl_offs, |
3029 | oh->prcm.omap4.rstctrl_offs + | ||
3030 | OMAP4_RST_CTRL_ST_OFFSET); | ||
3023 | } | 3031 | } |
3024 | 3032 | ||
3025 | /** | 3033 | /** |
@@ -3048,27 +3056,6 @@ static int _omap4_is_hardreset_asserted(struct omap_hwmod *oh, | |||
3048 | } | 3056 | } |
3049 | 3057 | ||
3050 | /** | 3058 | /** |
3051 | * _am33xx_assert_hardreset - call AM33XX PRM hardreset fn with hwmod args | ||
3052 | * @oh: struct omap_hwmod * to assert hardreset | ||
3053 | * @ohri: hardreset line data | ||
3054 | * | ||
3055 | * Call am33xx_prminst_assert_hardreset() with parameters extracted | ||
3056 | * from the hwmod @oh and the hardreset line data @ohri. Only | ||
3057 | * intended for use as an soc_ops function pointer. Passes along the | ||
3058 | * return value from am33xx_prminst_assert_hardreset(). XXX This | ||
3059 | * function is scheduled for removal when the PRM code is moved into | ||
3060 | * drivers/. | ||
3061 | */ | ||
3062 | static int _am33xx_assert_hardreset(struct omap_hwmod *oh, | ||
3063 | struct omap_hwmod_rst_info *ohri) | ||
3064 | |||
3065 | { | ||
3066 | return omap_prm_assert_hardreset(ohri->rst_shift, 0, | ||
3067 | oh->clkdm->pwrdm.ptr->prcm_offs, | ||
3068 | oh->prcm.omap4.rstctrl_offs); | ||
3069 | } | ||
3070 | |||
3071 | /** | ||
3072 | * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args | 3059 | * _am33xx_deassert_hardreset - call AM33XX PRM hardreset fn with hwmod args |
3073 | * @oh: struct omap_hwmod * to deassert hardreset | 3060 | * @oh: struct omap_hwmod * to deassert hardreset |
3074 | * @ohri: hardreset line data | 3061 | * @ohri: hardreset line data |
@@ -3083,32 +3070,13 @@ static int _am33xx_assert_hardreset(struct omap_hwmod *oh, | |||
3083 | static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, | 3070 | static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, |
3084 | struct omap_hwmod_rst_info *ohri) | 3071 | struct omap_hwmod_rst_info *ohri) |
3085 | { | 3072 | { |
3086 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, 0, | 3073 | return omap_prm_deassert_hardreset(ohri->rst_shift, ohri->st_shift, |
3074 | oh->clkdm->pwrdm.ptr->prcm_partition, | ||
3087 | oh->clkdm->pwrdm.ptr->prcm_offs, | 3075 | oh->clkdm->pwrdm.ptr->prcm_offs, |
3088 | oh->prcm.omap4.rstctrl_offs, | 3076 | oh->prcm.omap4.rstctrl_offs, |
3089 | oh->prcm.omap4.rstst_offs); | 3077 | oh->prcm.omap4.rstst_offs); |
3090 | } | 3078 | } |
3091 | 3079 | ||
3092 | /** | ||
3093 | * _am33xx_is_hardreset_asserted - call AM33XX PRM hardreset fn with hwmod args | ||
3094 | * @oh: struct omap_hwmod * to test hardreset | ||
3095 | * @ohri: hardreset line data | ||
3096 | * | ||
3097 | * Call am33xx_prminst_is_hardreset_asserted() with parameters | ||
3098 | * extracted from the hwmod @oh and the hardreset line data @ohri. | ||
3099 | * Only intended for use as an soc_ops function pointer. Passes along | ||
3100 | * the return value from am33xx_prminst_is_hardreset_asserted(). XXX | ||
3101 | * This function is scheduled for removal when the PRM code is moved | ||
3102 | * into drivers/. | ||
3103 | */ | ||
3104 | static int _am33xx_is_hardreset_asserted(struct omap_hwmod *oh, | ||
3105 | struct omap_hwmod_rst_info *ohri) | ||
3106 | { | ||
3107 | return omap_prm_is_hardreset_asserted(ohri->rst_shift, 0, | ||
3108 | oh->clkdm->pwrdm.ptr->prcm_offs, | ||
3109 | oh->prcm.omap4.rstctrl_offs); | ||
3110 | } | ||
3111 | |||
3112 | /* Public functions */ | 3080 | /* Public functions */ |
3113 | 3081 | ||
3114 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) | 3082 | u32 omap_hwmod_read(struct omap_hwmod *oh, u16 reg_offs) |
@@ -3908,21 +3876,13 @@ void __init omap_hwmod_init(void) | |||
3908 | soc_ops.init_clkdm = _init_clkdm; | 3876 | soc_ops.init_clkdm = _init_clkdm; |
3909 | soc_ops.update_context_lost = _omap4_update_context_lost; | 3877 | soc_ops.update_context_lost = _omap4_update_context_lost; |
3910 | soc_ops.get_context_lost = _omap4_get_context_lost; | 3878 | soc_ops.get_context_lost = _omap4_get_context_lost; |
3911 | } else if (soc_is_am43xx()) { | 3879 | } else if (cpu_is_ti816x() || soc_is_am33xx() || soc_is_am43xx()) { |
3912 | soc_ops.enable_module = _omap4_enable_module; | 3880 | soc_ops.enable_module = _omap4_enable_module; |
3913 | soc_ops.disable_module = _omap4_disable_module; | 3881 | soc_ops.disable_module = _omap4_disable_module; |
3914 | soc_ops.wait_target_ready = _omap4_wait_target_ready; | 3882 | soc_ops.wait_target_ready = _omap4_wait_target_ready; |
3915 | soc_ops.assert_hardreset = _omap4_assert_hardreset; | 3883 | soc_ops.assert_hardreset = _omap4_assert_hardreset; |
3916 | soc_ops.deassert_hardreset = _omap4_deassert_hardreset; | ||
3917 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; | ||
3918 | soc_ops.init_clkdm = _init_clkdm; | ||
3919 | } else if (cpu_is_ti816x() || soc_is_am33xx()) { | ||
3920 | soc_ops.enable_module = _omap4_enable_module; | ||
3921 | soc_ops.disable_module = _omap4_disable_module; | ||
3922 | soc_ops.wait_target_ready = _omap4_wait_target_ready; | ||
3923 | soc_ops.assert_hardreset = _am33xx_assert_hardreset; | ||
3924 | soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; | 3884 | soc_ops.deassert_hardreset = _am33xx_deassert_hardreset; |
3925 | soc_ops.is_hardreset_asserted = _am33xx_is_hardreset_asserted; | 3885 | soc_ops.is_hardreset_asserted = _omap4_is_hardreset_asserted; |
3926 | soc_ops.init_clkdm = _init_clkdm; | 3886 | soc_ops.init_clkdm = _init_clkdm; |
3927 | } else { | 3887 | } else { |
3928 | WARN(1, "omap_hwmod: unknown SoC type\n"); | 3888 | WARN(1, "omap_hwmod: unknown SoC type\n"); |
diff --git a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c index e2223148ba4d..17e8004fc20f 100644 --- a/arch/arm/mach-omap2/omap_hwmod_43xx_data.c +++ b/arch/arm/mach-omap2/omap_hwmod_43xx_data.c | |||
@@ -544,6 +544,44 @@ static struct omap_hwmod am43xx_hdq1w_hwmod = { | |||
544 | }, | 544 | }, |
545 | }; | 545 | }; |
546 | 546 | ||
547 | static struct omap_hwmod_class_sysconfig am43xx_vpfe_sysc = { | ||
548 | .rev_offs = 0x0, | ||
549 | .sysc_offs = 0x104, | ||
550 | .sysc_flags = SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE, | ||
551 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | | ||
552 | MSTANDBY_FORCE | MSTANDBY_SMART | MSTANDBY_NO), | ||
553 | .sysc_fields = &omap_hwmod_sysc_type2, | ||
554 | }; | ||
555 | |||
556 | static struct omap_hwmod_class am43xx_vpfe_hwmod_class = { | ||
557 | .name = "vpfe", | ||
558 | .sysc = &am43xx_vpfe_sysc, | ||
559 | }; | ||
560 | |||
561 | static struct omap_hwmod am43xx_vpfe0_hwmod = { | ||
562 | .name = "vpfe0", | ||
563 | .class = &am43xx_vpfe_hwmod_class, | ||
564 | .clkdm_name = "l3s_clkdm", | ||
565 | .prcm = { | ||
566 | .omap4 = { | ||
567 | .modulemode = MODULEMODE_SWCTRL, | ||
568 | .clkctrl_offs = AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET, | ||
569 | }, | ||
570 | }, | ||
571 | }; | ||
572 | |||
573 | static struct omap_hwmod am43xx_vpfe1_hwmod = { | ||
574 | .name = "vpfe1", | ||
575 | .class = &am43xx_vpfe_hwmod_class, | ||
576 | .clkdm_name = "l3s_clkdm", | ||
577 | .prcm = { | ||
578 | .omap4 = { | ||
579 | .modulemode = MODULEMODE_SWCTRL, | ||
580 | .clkctrl_offs = AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET, | ||
581 | }, | ||
582 | }, | ||
583 | }; | ||
584 | |||
547 | /* Interfaces */ | 585 | /* Interfaces */ |
548 | static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = { | 586 | static struct omap_hwmod_ocp_if am43xx_l3_main__l4_hs = { |
549 | .master = &am33xx_l3_main_hwmod, | 587 | .master = &am33xx_l3_main_hwmod, |
@@ -825,6 +863,34 @@ static struct omap_hwmod_ocp_if am43xx_l4_ls__hdq1w = { | |||
825 | .user = OCP_USER_MPU | OCP_USER_SDMA, | 863 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
826 | }; | 864 | }; |
827 | 865 | ||
866 | static struct omap_hwmod_ocp_if am43xx_l3__vpfe0 = { | ||
867 | .master = &am43xx_vpfe0_hwmod, | ||
868 | .slave = &am33xx_l3_main_hwmod, | ||
869 | .clk = "l3_gclk", | ||
870 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
871 | }; | ||
872 | |||
873 | static struct omap_hwmod_ocp_if am43xx_l3__vpfe1 = { | ||
874 | .master = &am43xx_vpfe1_hwmod, | ||
875 | .slave = &am33xx_l3_main_hwmod, | ||
876 | .clk = "l3_gclk", | ||
877 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
878 | }; | ||
879 | |||
880 | static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe0 = { | ||
881 | .master = &am33xx_l4_ls_hwmod, | ||
882 | .slave = &am43xx_vpfe0_hwmod, | ||
883 | .clk = "l4ls_gclk", | ||
884 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
885 | }; | ||
886 | |||
887 | static struct omap_hwmod_ocp_if am43xx_l4_ls__vpfe1 = { | ||
888 | .master = &am33xx_l4_ls_hwmod, | ||
889 | .slave = &am43xx_vpfe1_hwmod, | ||
890 | .clk = "l4ls_gclk", | ||
891 | .user = OCP_USER_MPU | OCP_USER_SDMA, | ||
892 | }; | ||
893 | |||
828 | static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { | 894 | static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { |
829 | &am33xx_l4_wkup__synctimer, | 895 | &am33xx_l4_wkup__synctimer, |
830 | &am43xx_l4_ls__timer8, | 896 | &am43xx_l4_ls__timer8, |
@@ -925,6 +991,10 @@ static struct omap_hwmod_ocp_if *am43xx_hwmod_ocp_ifs[] __initdata = { | |||
925 | &am43xx_l4_ls__dss_dispc, | 991 | &am43xx_l4_ls__dss_dispc, |
926 | &am43xx_l4_ls__dss_rfbi, | 992 | &am43xx_l4_ls__dss_rfbi, |
927 | &am43xx_l4_ls__hdq1w, | 993 | &am43xx_l4_ls__hdq1w, |
994 | &am43xx_l3__vpfe0, | ||
995 | &am43xx_l3__vpfe1, | ||
996 | &am43xx_l4_ls__vpfe0, | ||
997 | &am43xx_l4_ls__vpfe1, | ||
928 | NULL, | 998 | NULL, |
929 | }; | 999 | }; |
930 | 1000 | ||
diff --git a/arch/arm/mach-omap2/prcm43xx.h b/arch/arm/mach-omap2/prcm43xx.h index 48df3b55057e..d0261996db6d 100644 --- a/arch/arm/mach-omap2/prcm43xx.h +++ b/arch/arm/mach-omap2/prcm43xx.h | |||
@@ -144,5 +144,6 @@ | |||
144 | #define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0 | 144 | #define AM43XX_CM_PER_USBPHYOCP2SCP1_CLKCTRL_OFFSET 0x05C0 |
145 | #define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20 | 145 | #define AM43XX_CM_PER_DSS_CLKCTRL_OFFSET 0x0a20 |
146 | #define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET 0x04a0 | 146 | #define AM43XX_CM_PER_HDQ1W_CLKCTRL_OFFSET 0x04a0 |
147 | 147 | #define AM43XX_CM_PER_VPFE0_CLKCTRL_OFFSET 0x0068 | |
148 | #define AM43XX_CM_PER_VPFE1_CLKCTRL_OFFSET 0x0070 | ||
148 | #endif | 149 | #endif |
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c index c4859c4d3646..d0b15dbafa2e 100644 --- a/arch/arm/mach-omap2/prminst44xx.c +++ b/arch/arm/mach-omap2/prminst44xx.c | |||
@@ -87,12 +87,6 @@ u32 omap4_prminst_rmw_inst_reg_bits(u32 mask, u32 bits, u8 part, s16 inst, | |||
87 | return v; | 87 | return v; |
88 | } | 88 | } |
89 | 89 | ||
90 | /* | ||
91 | * Address offset (in bytes) between the reset control and the reset | ||
92 | * status registers: 4 bytes on OMAP4 | ||
93 | */ | ||
94 | #define OMAP4_RST_CTRL_ST_OFFSET 4 | ||
95 | |||
96 | /** | 90 | /** |
97 | * omap4_prminst_is_hardreset_asserted - read the HW reset line state of | 91 | * omap4_prminst_is_hardreset_asserted - read the HW reset line state of |
98 | * submodules contained in the hwmod module | 92 | * submodules contained in the hwmod module |
@@ -141,11 +135,11 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst, | |||
141 | * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and | 135 | * omap4_prminst_deassert_hardreset - deassert a submodule hardreset line and |
142 | * wait | 136 | * wait |
143 | * @shift: register bit shift corresponding to the reset line to deassert | 137 | * @shift: register bit shift corresponding to the reset line to deassert |
144 | * @st_shift: status bit offset, not used for OMAP4+ | 138 | * @st_shift: status bit offset corresponding to the reset line |
145 | * @part: PRM partition | 139 | * @part: PRM partition |
146 | * @inst: PRM instance offset | 140 | * @inst: PRM instance offset |
147 | * @rstctrl_offs: reset register offset | 141 | * @rstctrl_offs: reset register offset |
148 | * @st_offs: reset status register offset, not used for OMAP4+ | 142 | * @rstst_offs: reset status register offset |
149 | * | 143 | * |
150 | * Some IPs like dsp, ipu or iva contain processors that require an HW | 144 | * Some IPs like dsp, ipu or iva contain processors that require an HW |
151 | * reset line to be asserted / deasserted in order to fully enable the | 145 | * reset line to be asserted / deasserted in order to fully enable the |
@@ -157,11 +151,11 @@ int omap4_prminst_assert_hardreset(u8 shift, u8 part, s16 inst, | |||
157 | * of reset, or -EBUSY if the submodule did not exit reset promptly. | 151 | * of reset, or -EBUSY if the submodule did not exit reset promptly. |
158 | */ | 152 | */ |
159 | int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst, | 153 | int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst, |
160 | u16 rstctrl_offs, u16 st_offs) | 154 | u16 rstctrl_offs, u16 rstst_offs) |
161 | { | 155 | { |
162 | int c; | 156 | int c; |
163 | u32 mask = 1 << shift; | 157 | u32 mask = 1 << shift; |
164 | u16 rstst_offs = rstctrl_offs + OMAP4_RST_CTRL_ST_OFFSET; | 158 | u32 st_mask = 1 << st_shift; |
165 | 159 | ||
166 | /* Check the current status to avoid de-asserting the line twice */ | 160 | /* Check the current status to avoid de-asserting the line twice */ |
167 | if (omap4_prminst_is_hardreset_asserted(shift, part, inst, | 161 | if (omap4_prminst_is_hardreset_asserted(shift, part, inst, |
@@ -169,13 +163,13 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 st_shift, u8 part, s16 inst, | |||
169 | return -EEXIST; | 163 | return -EEXIST; |
170 | 164 | ||
171 | /* Clear the reset status by writing 1 to the status bit */ | 165 | /* Clear the reset status by writing 1 to the status bit */ |
172 | omap4_prminst_rmw_inst_reg_bits(0xffffffff, mask, part, inst, | 166 | omap4_prminst_rmw_inst_reg_bits(0xffffffff, st_mask, part, inst, |
173 | rstst_offs); | 167 | rstst_offs); |
174 | /* de-assert the reset control line */ | 168 | /* de-assert the reset control line */ |
175 | omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs); | 169 | omap4_prminst_rmw_inst_reg_bits(mask, 0, part, inst, rstctrl_offs); |
176 | /* wait the status to be set */ | 170 | /* wait the status to be set */ |
177 | omap_test_timeout(omap4_prminst_is_hardreset_asserted(shift, part, inst, | 171 | omap_test_timeout(omap4_prminst_is_hardreset_asserted(st_shift, part, |
178 | rstst_offs), | 172 | inst, rstst_offs), |
179 | MAX_MODULE_HARDRESET_WAIT, c); | 173 | MAX_MODULE_HARDRESET_WAIT, c); |
180 | 174 | ||
181 | return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; | 175 | return (c == MAX_MODULE_HARDRESET_WAIT) ? -EBUSY : 0; |