diff options
author | Xiubo Li <Li.Xiubo@freescale.com> | 2014-08-19 00:38:01 -0400 |
---|---|---|
committer | Thierry Reding <thierry.reding@gmail.com> | 2014-08-20 04:09:54 -0400 |
commit | cd6d92d2aa1556b22cd05acbc5f2cc8e5caafcc4 (patch) | |
tree | 86516b4679ad10da31b581bfa60e69f8da78e705 | |
parent | d717ea73e36dd5659640fae82605ad85c4117f4d (diff) |
pwm: fsl-ftm: Clean up the code
This patch intends to prepare for converting to direct regmap API usage.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
-rw-r--r-- | drivers/pwm/pwm-fsl-ftm.c | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/drivers/pwm/pwm-fsl-ftm.c b/drivers/pwm/pwm-fsl-ftm.c index a18bc8fea385..96982da52d86 100644 --- a/drivers/pwm/pwm-fsl-ftm.c +++ b/drivers/pwm/pwm-fsl-ftm.c | |||
@@ -21,11 +21,10 @@ | |||
21 | #include <linux/slab.h> | 21 | #include <linux/slab.h> |
22 | 22 | ||
23 | #define FTM_SC 0x00 | 23 | #define FTM_SC 0x00 |
24 | #define FTM_SC_CLK_MASK 0x3 | 24 | #define FTM_SC_CLK_MASK_SHIFT 3 |
25 | #define FTM_SC_CLK_SHIFT 3 | 25 | #define FTM_SC_CLK_MASK (3 << FTM_SC_CLK_MASK_SHIFT) |
26 | #define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_SHIFT) | 26 | #define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_MASK_SHIFT) |
27 | #define FTM_SC_PS_MASK 0x7 | 27 | #define FTM_SC_PS_MASK 0x7 |
28 | #define FTM_SC_PS_SHIFT 0 | ||
29 | 28 | ||
30 | #define FTM_CNT 0x04 | 29 | #define FTM_CNT 0x04 |
31 | #define FTM_MOD 0x08 | 30 | #define FTM_MOD 0x08 |
@@ -258,7 +257,7 @@ static int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, | |||
258 | } | 257 | } |
259 | 258 | ||
260 | val = readl(fpc->base + FTM_SC); | 259 | val = readl(fpc->base + FTM_SC); |
261 | val &= ~(FTM_SC_PS_MASK << FTM_SC_PS_SHIFT); | 260 | val &= ~FTM_SC_PS_MASK; |
262 | val |= fpc->clk_ps; | 261 | val |= fpc->clk_ps; |
263 | writel(val, fpc->base + FTM_SC); | 262 | writel(val, fpc->base + FTM_SC); |
264 | writel(period - 1, fpc->base + FTM_MOD); | 263 | writel(period - 1, fpc->base + FTM_MOD); |
@@ -305,7 +304,7 @@ static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc) | |||
305 | 304 | ||
306 | /* select counter clock source */ | 305 | /* select counter clock source */ |
307 | val = readl(fpc->base + FTM_SC); | 306 | val = readl(fpc->base + FTM_SC); |
308 | val &= ~(FTM_SC_CLK_MASK << FTM_SC_CLK_SHIFT); | 307 | val &= ~FTM_SC_CLK_MASK; |
309 | val |= FTM_SC_CLK(fpc->cnt_select); | 308 | val |= FTM_SC_CLK(fpc->cnt_select); |
310 | writel(val, fpc->base + FTM_SC); | 309 | writel(val, fpc->base + FTM_SC); |
311 | 310 | ||
@@ -357,7 +356,7 @@ static void fsl_counter_clock_disable(struct fsl_pwm_chip *fpc) | |||
357 | 356 | ||
358 | /* no users left, disable PWM counter clock */ | 357 | /* no users left, disable PWM counter clock */ |
359 | val = readl(fpc->base + FTM_SC); | 358 | val = readl(fpc->base + FTM_SC); |
360 | val &= ~(FTM_SC_CLK_MASK << FTM_SC_CLK_SHIFT); | 359 | val &= ~FTM_SC_CLK_MASK; |
361 | writel(val, fpc->base + FTM_SC); | 360 | writel(val, fpc->base + FTM_SC); |
362 | 361 | ||
363 | clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); | 362 | clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); |