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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2013-04-29 21:10:09 -0400
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>2013-04-29 21:10:09 -0400
commitbc23100a0d646aedb6e17fbcecdc35a24cd3bf2a (patch)
treeafbf44b177d17a8450d606b6d976e76e8e964273
parent28bf41a1fedad76e9b4de70c9573bb3f8afc3709 (diff)
parent9e2ecdbba3b0745f9ed454ab86961e3ccf9dc224 (diff)
Merge remote-tracking branch 'kumar/next' into next
From Kumar Gala: << Add support for T4 and B4 SoC families from Freescale, e6500 altivec support, some various board fixes and other minor cleanups. >>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/powerpc/fsl/cpus.txt22
-rw-r--r--arch/powerpc/Kconfig6
-rw-r--r--arch/powerpc/boot/dts/b4420qds.dts50
-rw-r--r--arch/powerpc/boot/dts/b4860qds.dts61
-rw-r--r--arch/powerpc/boot/dts/b4qds.dts169
-rw-r--r--arch/powerpc/boot/dts/fsl/b4420si-post.dtsi98
-rw-r--r--arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi73
-rw-r--r--arch/powerpc/boot/dts/fsl/b4860si-post.dtsi142
-rw-r--r--arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi83
-rw-r--r--arch/powerpc/boot/dts/fsl/b4si-post.dtsi268
-rw-r--r--arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi1
-rw-r--r--arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi1
-rw-r--r--arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi65
-rw-r--r--arch/powerpc/boot/dts/fsl/p1023si-post.dtsi1
-rw-r--r--arch/powerpc/boot/dts/fsl/p2041si-post.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/p3041si-post.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/p4080si-post.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/p5020si-post.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/p5040si-post.dtsi2
-rw-r--r--arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi1
-rw-r--r--arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi41
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi1
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi1
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi (renamed from arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi)27
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi1
-rw-r--r--arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi119
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-post.dtsi442
-rw-r--r--arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi128
-rw-r--r--arch/powerpc/boot/dts/mpc8536ds_36b.dts6
-rw-r--r--arch/powerpc/boot/dts/p1021rdb-pc.dtsi12
-rw-r--r--arch/powerpc/boot/dts/p1025rdb_36b.dts5
-rw-r--r--arch/powerpc/boot/dts/t4240qds.dts224
-rw-r--r--arch/powerpc/configs/corenet64_smp_defconfig46
-rw-r--r--arch/powerpc/configs/mpc85xx_defconfig40
-rw-r--r--arch/powerpc/configs/mpc85xx_smp_defconfig32
-rw-r--r--arch/powerpc/include/asm/cputable.h2
-rw-r--r--arch/powerpc/include/asm/kvm_asm.h4
-rw-r--r--arch/powerpc/include/asm/pci-bridge.h11
-rw-r--r--arch/powerpc/kernel/cpu_setup_fsl_booke.S16
-rw-r--r--arch/powerpc/kernel/cputable.c9
-rw-r--r--arch/powerpc/kernel/epapr_hcalls.S2
-rw-r--r--arch/powerpc/kernel/exceptions-64e.S47
-rw-r--r--arch/powerpc/kernel/idle_book3e.S32
-rw-r--r--arch/powerpc/mm/tlb_nohash.c18
-rw-r--r--arch/powerpc/platforms/85xx/Kconfig34
-rw-r--r--arch/powerpc/platforms/85xx/Makefile2
-rw-r--r--arch/powerpc/platforms/85xx/b4_qds.c102
-rw-r--r--arch/powerpc/platforms/85xx/corenet_ds.c5
-rw-r--r--arch/powerpc/platforms/85xx/smp.c2
-rw-r--r--arch/powerpc/platforms/85xx/t4240_qds.c98
-rw-r--r--arch/powerpc/platforms/Kconfig1
-rw-r--r--arch/powerpc/platforms/Kconfig.cputype2
-rw-r--r--arch/powerpc/sysdev/fsl_msi.c4
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c112
-rw-r--r--arch/powerpc/sysdev/fsl_pci.h13
-rw-r--r--arch/powerpc/sysdev/indirect_pci.c10
-rw-r--r--arch/powerpc/sysdev/qe_lib/Kconfig2
60 files changed, 2735 insertions, 92 deletions
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
new file mode 100644
index 000000000000..922c30ad90d1
--- /dev/null
+++ b/Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
@@ -0,0 +1,22 @@
1===================================================================
2Power Architecture CPU Binding
3Copyright 2013 Freescale Semiconductor Inc.
4
5Power Architecture CPUs in Freescale SOCs are represented in device trees as
6per the definition in ePAPR.
7
8In addition to the ePAPR definitions, the properties defined below may be
9present on CPU nodes.
10
11PROPERTIES
12
13 - fsl,eref-*
14 Usage: optional
15 Value type: <empty>
16 Definition: The EREF (EREF: A Programmer.s Reference Manual for
17 Freescale Power Architecture) defines the architecture for Freescale
18 Power CPUs. The EREF defines some architecture categories not defined
19 by the Power ISA. For these EREF-specific categories, the existence of
20 a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
21 name with all uppercase letters converted to lowercase, indicates that
22 the category is supported by the implementation.
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index a9ae67317374..84cb0c932153 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -681,7 +681,6 @@ config SBUS
681config FSL_SOC 681config FSL_SOC
682 bool 682 bool
683 select HAVE_CAN_FLEXCAN if NET && CAN 683 select HAVE_CAN_FLEXCAN if NET && CAN
684 select PPC_CLOCK
685 684
686config FSL_PCI 685config FSL_PCI
687 bool 686 bool
@@ -769,11 +768,6 @@ config PCI_8260
769 select PPC_INDIRECT_PCI 768 select PPC_INDIRECT_PCI
770 default y 769 default y
771 770
772config 8260_PCI9
773 bool "Enable workaround for MPC826x erratum PCI 9"
774 depends on PCI_8260 && !8272
775 default y
776
777source "drivers/pci/pcie/Kconfig" 771source "drivers/pci/pcie/Kconfig"
778 772
779source "drivers/pci/Kconfig" 773source "drivers/pci/Kconfig"
diff --git a/arch/powerpc/boot/dts/b4420qds.dts b/arch/powerpc/boot/dts/b4420qds.dts
new file mode 100644
index 000000000000..923156d03b30
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4420qds.dts
@@ -0,0 +1,50 @@
1/*
2 * B4420DS Device Tree Source
3 *
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * This software is provided by Freescale Semiconductor "as is" and any
24 * express or implied warranties, including, but not limited to, the implied
25 * warranties of merchantability and fitness for a particular purpose are
26 * disclaimed. In no event shall Freescale Semiconductor be liable for any
27 * direct, indirect, incidental, special, exemplary, or consequential damages
28 * (including, but not limited to, procurement of substitute goods or services;
29 * loss of use, data, or profits; or business interruption) however caused and
30 * on any theory of liability, whether in contract, strict liability, or tort
31 * (including negligence or otherwise) arising in any way out of the use of
32 * this software, even if advised of the possibility of such damage.
33 */
34
35/include/ "fsl/b4420si-pre.dtsi"
36/include/ "b4qds.dts"
37
38/ {
39 model = "fsl,B4420QDS";
40 compatible = "fsl,B4420QDS";
41
42 ifc: localbus@ffe124000 {
43 board-control@3,0 {
44 compatible = "fsl,b4420qds-fpga", "fsl,fpga-qixis";
45 };
46 };
47
48};
49
50/include/ "fsl/b4420si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/b4860qds.dts b/arch/powerpc/boot/dts/b4860qds.dts
new file mode 100644
index 000000000000..78907f38bb77
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4860qds.dts
@@ -0,0 +1,61 @@
1/*
2 * B4860DS Device Tree Source
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/b4860si-pre.dtsi"
36/include/ "b4qds.dts"
37
38/ {
39 model = "fsl,B4860QDS";
40 compatible = "fsl,B4860QDS";
41
42 ifc: localbus@ffe124000 {
43 board-control@3,0 {
44 compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
45 };
46 };
47
48 rio: rapidio@ffe0c0000 {
49 reg = <0xf 0xfe0c0000 0 0x11000>;
50
51 port1 {
52 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
53 };
54 port2 {
55 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
56 };
57 };
58
59};
60
61/include/ "fsl/b4860si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/b4qds.dts b/arch/powerpc/boot/dts/b4qds.dts
new file mode 100644
index 000000000000..e6d2f8f90544
--- /dev/null
+++ b/arch/powerpc/boot/dts/b4qds.dts
@@ -0,0 +1,169 @@
1/*
2 * B4420DS Device Tree Source
3 *
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * This software is provided by Freescale Semiconductor "as is" and any
24 * express or implied warranties, including, but not limited to, the implied
25 * warranties of merchantability and fitness for a particular purpose are
26 * disclaimed. In no event shall Freescale Semiconductor be liable for any
27 * direct, indirect, incidental, special, exemplary, or consequential damages
28 * (including, but not limited to, procurement of substitute goods or services;
29 * loss of use, data, or profits; or business interruption) however caused and
30 * on any theory of liability, whether in contract, strict liability, or tort
31 * (including negligence or otherwise) arising in any way out of the use of
32 * this software, even if advised of the possibility of such damage.
33 */
34
35/ {
36 model = "fsl,B4QDS";
37 compatible = "fsl,B4QDS";
38 #address-cells = <2>;
39 #size-cells = <2>;
40 interrupt-parent = <&mpic>;
41
42 ifc: localbus@ffe124000 {
43 reg = <0xf 0xfe124000 0 0x2000>;
44 ranges = <0 0 0xf 0xe8000000 0x08000000
45 2 0 0xf 0xff800000 0x00010000
46 3 0 0xf 0xffdf0000 0x00008000>;
47
48 nor@0,0 {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 compatible = "cfi-flash";
52 reg = <0x0 0x0 0x8000000>;
53 bank-width = <2>;
54 device-width = <1>;
55 };
56
57 nand@2,0 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "fsl,ifc-nand";
61 reg = <0x2 0x0 0x10000>;
62
63 partition@0 {
64 /* This location must not be altered */
65 /* 1MB for u-boot Bootloader Image */
66 reg = <0x0 0x00100000>;
67 label = "NAND U-Boot Image";
68 read-only;
69 };
70
71 partition@100000 {
72 /* 1MB for DTB Image */
73 reg = <0x00100000 0x00100000>;
74 label = "NAND DTB Image";
75 };
76
77 partition@200000 {
78 /* 10MB for Linux Kernel Image */
79 reg = <0x00200000 0x00A00000>;
80 label = "NAND Linux Kernel Image";
81 };
82
83 partition@c00000 {
84 /* 500MB for Root file System Image */
85 reg = <0x00c00000 0x1F400000>;
86 label = "NAND RFS Image";
87 };
88 };
89
90 board-control@3,0 {
91 compatible = "fsl,b4qds-fpga", "fsl,fpga-qixis";
92 reg = <3 0 0x300>;
93 };
94 };
95
96 memory {
97 device_type = "memory";
98 };
99
100 dcsr: dcsr@f00000000 {
101 ranges = <0x00000000 0xf 0x00000000 0x01052000>;
102 };
103
104 soc: soc@ffe000000 {
105 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
106 reg = <0xf 0xfe000000 0 0x00001000>;
107 spi@110000 {
108 flash@0 {
109 #address-cells = <1>;
110 #size-cells = <1>;
111 compatible = "sst,sst25wf040";
112 reg = <0>;
113 spi-max-frequency = <40000000>; /* input clock */
114 };
115 };
116
117 sdhc@114000 {
118 /*Disabled as there is no sdhc connector on B4420QDS board*/
119 status = "disabled";
120 };
121
122 i2c@118000 {
123 eeprom@50 {
124 compatible = "at24,24c64";
125 reg = <0x50>;
126 };
127 eeprom@51 {
128 compatible = "at24,24c256";
129 reg = <0x51>;
130 };
131 eeprom@53 {
132 compatible = "at24,24c256";
133 reg = <0x53>;
134 };
135 eeprom@57 {
136 compatible = "at24,24c256";
137 reg = <0x57>;
138 };
139 rtc@68 {
140 compatible = "dallas,ds3232";
141 reg = <0x68>;
142 };
143 };
144
145 usb@210000 {
146 dr_mode = "host";
147 phy_type = "ulpi";
148 };
149
150 };
151
152 pci0: pcie@ffe200000 {
153 reg = <0xf 0xfe200000 0 0x10000>;
154 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
155 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
156 pcie@0 {
157 ranges = <0x02000000 0 0xe0000000
158 0x02000000 0 0xe0000000
159 0 0x20000000
160
161 0x01000000 0 0x00000000
162 0x01000000 0 0x00000000
163 0 0x00010000>;
164 };
165 };
166
167};
168
169/include/ "fsl/b4si-post.dtsi"
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
new file mode 100644
index 000000000000..5a6615d0ade2
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
@@ -0,0 +1,98 @@
1/*
2 * B4420 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * This software is provided by Freescale Semiconductor "as is" and any
24 * express or implied warranties, including, but not limited to, the implied
25 * warranties of merchantability and fitness for a particular purpose are
26 * disclaimed. In no event shall Freescale Semiconductor be liable for any
27 * direct, indirect, incidental, special, exemplary, or consequential damages
28 * (including, but not limited to, procurement of substitute goods or services;
29 * loss of use, data, or profits; or business interruption) however caused and
30 * on any theory of liability, whether in contract, strict liability, or tort
31 * (including negligence or otherwise) arising in any way out of the use of
32 * this software, even if advised of the possibility of such damage.
33 */
34
35/include/ "b4si-post.dtsi"
36
37/* controller at 0x200000 */
38&pci0 {
39 compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
40};
41
42&dcsr {
43 dcsr-epu@0 {
44 compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
45 };
46 dcsr-npc {
47 compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
48 };
49 dcsr-dpaa@9000 {
50 compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
51 };
52 dcsr-ocn@11000 {
53 compatible = "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn";
54 };
55 dcsr-nal@18000 {
56 compatible = "fsl,b4420-dcsr-nal", "fsl,dcsr-nal";
57 };
58 dcsr-rcpm@22000 {
59 compatible = "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm";
60 };
61 dcsr-snpc@30000 {
62 compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
63 };
64 dcsr-snpc@31000 {
65 compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
66 };
67 dcsr-cpu-sb-proxy@108000 {
68 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
69 cpu-handle = <&cpu1>;
70 reg = <0x108000 0x1000 0x109000 0x1000>;
71 };
72};
73
74&soc {
75 cpc: l3-cache-controller@10000 {
76 compatible = "fsl,b4420-l3-cache-controller", "cache";
77 };
78
79 corenet-cf@18000 {
80 compatible = "fsl,b4420-corenet-cf";
81 };
82
83 guts: global-utilities@e0000 {
84 compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
85 };
86
87 clockgen: global-utilities@e1000 {
88 compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
89 };
90
91 rcpm: global-utilities@e2000 {
92 compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0";
93 };
94
95 L2: l2-cache-controller@c20000 {
96 compatible = "fsl,b4420-l2-cache-controller";
97 };
98};
diff --git a/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
new file mode 100644
index 000000000000..7b4426e0a5a5
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
@@ -0,0 +1,73 @@
1/*
2 * B4420 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * This software is provided by Freescale Semiconductor "as is" and any
24 * express or implied warranties, including, but not limited to, the implied
25 * warranties of merchantability and fitness for a particular purpose are
26 * disclaimed. In no event shall Freescale Semiconductor be liable for any
27 * direct, indirect, incidental, special, exemplary, or consequential damages
28 * (including, but not limited to, procurement of substitute goods or services;
29 * loss of use, data, or profits; or business interruption) however caused and
30 * on any theory of liability, whether in contract, strict liability, or tort
31 * (including negligence or otherwise) arising in any way out of the use of
32 * this software, even if advised of the possibility of such damage.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,B4420";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45 dcsr = &dcsr;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 dma0 = &dma0;
53 dma1 = &dma1;
54 sdhc = &sdhc;
55 };
56
57
58 cpus {
59 #address-cells = <1>;
60 #size-cells = <0>;
61
62 cpu0: PowerPC,e6500@0 {
63 device_type = "cpu";
64 reg = <0 1>;
65 next-level-cache = <&L2>;
66 };
67 cpu1: PowerPC,e6500@2 {
68 device_type = "cpu";
69 reg = <2 3>;
70 next-level-cache = <&L2>;
71 };
72 };
73};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
new file mode 100644
index 000000000000..e5cf6c81dd66
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
@@ -0,0 +1,142 @@
1/*
2 * B4860 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "b4si-post.dtsi"
36
37/* controller at 0x200000 */
38&pci0 {
39 compatible = "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
40};
41
42&rio {
43 compatible = "fsl,srio";
44 interrupts = <16 2 1 11>;
45 #address-cells = <2>;
46 #size-cells = <2>;
47 fsl,iommu-parent = <&pamu0>;
48 ranges;
49
50 port1 {
51 #address-cells = <2>;
52 #size-cells = <2>;
53 cell-index = <1>;
54 fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
55 };
56
57 port2 {
58 #address-cells = <2>;
59 #size-cells = <2>;
60 cell-index = <2>;
61 fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
62 };
63};
64
65&dcsr {
66 dcsr-epu@0 {
67 compatible = "fsl,b4860-dcsr-epu", "fsl,dcsr-epu";
68 };
69 dcsr-npc {
70 compatible = "fsl,b4860-dcsr-cnpc", "fsl,dcsr-cnpc";
71 };
72 dcsr-dpaa@9000 {
73 compatible = "fsl,b4860-dcsr-dpaa", "fsl,dcsr-dpaa";
74 };
75 dcsr-ocn@11000 {
76 compatible = "fsl,b4860-dcsr-ocn", "fsl,dcsr-ocn";
77 };
78 dcsr-ddr@13000 {
79 compatible = "fsl,dcsr-ddr";
80 dev-handle = <&ddr2>;
81 reg = <0x13000 0x1000>;
82 };
83 dcsr-nal@18000 {
84 compatible = "fsl,b4860-dcsr-nal", "fsl,dcsr-nal";
85 };
86 dcsr-rcpm@22000 {
87 compatible = "fsl,b4860-dcsr-rcpm", "fsl,dcsr-rcpm";
88 };
89 dcsr-snpc@30000 {
90 compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
91 };
92 dcsr-snpc@31000 {
93 compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
94 };
95 dcsr-cpu-sb-proxy@108000 {
96 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
97 cpu-handle = <&cpu1>;
98 reg = <0x108000 0x1000 0x109000 0x1000>;
99 };
100 dcsr-cpu-sb-proxy@110000 {
101 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
102 cpu-handle = <&cpu2>;
103 reg = <0x110000 0x1000 0x111000 0x1000>;
104 };
105 dcsr-cpu-sb-proxy@118000 {
106 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
107 cpu-handle = <&cpu3>;
108 reg = <0x118000 0x1000 0x119000 0x1000>;
109 };
110};
111
112&soc {
113 ddr2: memory-controller@9000 {
114 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
115 reg = <0x9000 0x1000>;
116 interrupts = <16 2 1 9>;
117 };
118
119 cpc: l3-cache-controller@10000 {
120 compatible = "fsl,b4860-l3-cache-controller", "cache";
121 };
122
123 corenet-cf@18000 {
124 compatible = "fsl,b4860-corenet-cf";
125 };
126
127 guts: global-utilities@e0000 {
128 compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
129 };
130
131 clockgen: global-utilities@e1000 {
132 compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
133 };
134
135 rcpm: global-utilities@e2000 {
136 compatible = "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2.0";
137 };
138
139 L2: l2-cache-controller@c20000 {
140 compatible = "fsl,b4860-l2-cache-controller";
141 };
142};
diff --git a/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
new file mode 100644
index 000000000000..5263fa46a3fb
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
@@ -0,0 +1,83 @@
1/*
2 * B4860 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/ {
38 compatible = "fsl,B4860";
39 #address-cells = <2>;
40 #size-cells = <2>;
41 interrupt-parent = <&mpic>;
42
43 aliases {
44 ccsr = &soc;
45 dcsr = &dcsr;
46
47 serial0 = &serial0;
48 serial1 = &serial1;
49 serial2 = &serial2;
50 serial3 = &serial3;
51 pci0 = &pci0;
52 dma0 = &dma0;
53 dma1 = &dma1;
54 sdhc = &sdhc;
55 };
56
57
58 cpus {
59 #address-cells = <1>;
60 #size-cells = <0>;
61
62 cpu0: PowerPC,e6500@0 {
63 device_type = "cpu";
64 reg = <0 1>;
65 next-level-cache = <&L2>;
66 };
67 cpu1: PowerPC,e6500@2 {
68 device_type = "cpu";
69 reg = <2 3>;
70 next-level-cache = <&L2>;
71 };
72 cpu2: PowerPC,e6500@4 {
73 device_type = "cpu";
74 reg = <4 5>;
75 next-level-cache = <&L2>;
76 };
77 cpu3: PowerPC,e6500@6 {
78 device_type = "cpu";
79 reg = <6 7>;
80 next-level-cache = <&L2>;
81 };
82 };
83};
diff --git a/arch/powerpc/boot/dts/fsl/b4si-post.dtsi b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
new file mode 100644
index 000000000000..73991547c69b
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/b4si-post.dtsi
@@ -0,0 +1,268 @@
1/*
2 * B4420 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2012 Freescale Semiconductor, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * This software is provided by Freescale Semiconductor "as is" and any
24 * express or implied warranties, including, but not limited to, the implied
25 * warranties of merchantability and fitness for a particular purpose are
26 * disclaimed. In no event shall Freescale Semiconductor be liable for any
27 * direct, indirect, incidental, special, exemplary, or consequential damages
28 * (including, but not limited to, procurement of substitute goods or services;
29 * loss of use, data, or profits; or business interruption) however caused and
30 * on any theory of liability, whether in contract, strict liability, or tort
31 * (including negligence or otherwise) arising in any way out of the use of
32 * this software, even if advised of the possibility of such damage.
33 */
34
35&ifc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
39 interrupts = <25 2 0 0>;
40};
41
42/* controller at 0x200000 */
43&pci0 {
44 compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 interrupts = <20 2 0 0>;
50 fsl,iommu-parent = <&pamu0>;
51 pcie@0 {
52 #interrupt-cells = <1>;
53 #size-cells = <2>;
54 #address-cells = <3>;
55 device_type = "pci";
56 reg = <0 0 0 0 0>;
57 interrupts = <20 2 0 0>;
58 interrupt-map-mask = <0xf800 0 0 7>;
59 interrupt-map = <
60 /* IDSEL 0x0 */
61 0000 0 0 1 &mpic 40 1 0 0
62 0000 0 0 2 &mpic 1 1 0 0
63 0000 0 0 3 &mpic 2 1 0 0
64 0000 0 0 4 &mpic 3 1 0 0
65 >;
66 };
67};
68
69&dcsr {
70 #address-cells = <1>;
71 #size-cells = <1>;
72 compatible = "fsl,dcsr", "simple-bus";
73
74 dcsr-epu@0 {
75 compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
76 interrupts = <52 2 0 0
77 84 2 0 0
78 85 2 0 0
79 94 2 0 0
80 95 2 0 0>;
81 reg = <0x0 0x1000>;
82 };
83 dcsr-npc {
84 compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
85 reg = <0x1000 0x1000 0x1002000 0x10000>;
86 };
87 dcsr-nxc@2000 {
88 compatible = "fsl,dcsr-nxc";
89 reg = <0x2000 0x1000>;
90 };
91 dcsr-corenet {
92 compatible = "fsl,dcsr-corenet";
93 reg = <0x8000 0x1000 0x1A000 0x1000>;
94 };
95 dcsr-dpaa@9000 {
96 compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
97 reg = <0x9000 0x1000>;
98 };
99 dcsr-ocn@11000 {
100 compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
101 reg = <0x11000 0x1000>;
102 };
103 dcsr-ddr@12000 {
104 compatible = "fsl,dcsr-ddr";
105 dev-handle = <&ddr1>;
106 reg = <0x12000 0x1000>;
107 };
108 dcsr-nal@18000 {
109 compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
110 reg = <0x18000 0x1000>;
111 };
112 dcsr-rcpm@22000 {
113 compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
114 reg = <0x22000 0x1000>;
115 };
116 dcsr-snpc@30000 {
117 compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
118 reg = <0x30000 0x1000 0x1022000 0x10000>;
119 };
120 dcsr-snpc@31000 {
121 compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
122 reg = <0x31000 0x1000 0x1042000 0x10000>;
123 };
124 dcsr-cpu-sb-proxy@100000 {
125 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
126 cpu-handle = <&cpu0>;
127 reg = <0x100000 0x1000 0x101000 0x1000>;
128 };
129};
130
131&soc {
132 #address-cells = <1>;
133 #size-cells = <1>;
134 device_type = "soc";
135 compatible = "simple-bus";
136
137 soc-sram-error {
138 compatible = "fsl,soc-sram-error";
139 interrupts = <16 2 1 2>;
140 };
141
142 corenet-law@0 {
143 compatible = "fsl,corenet-law";
144 reg = <0x0 0x1000>;
145 fsl,num-laws = <32>;
146 };
147
148 ddr1: memory-controller@8000 {
149 compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
150 reg = <0x8000 0x1000>;
151 interrupts = <16 2 1 8>;
152 };
153
154 cpc: l3-cache-controller@10000 {
155 compatible = "fsl,b4-l3-cache-controller", "cache";
156 reg = <0x10000 0x1000>;
157 interrupts = <16 2 1 4>;
158 };
159
160 corenet-cf@18000 {
161 compatible = "fsl,b4-corenet-cf";
162 reg = <0x18000 0x1000>;
163 interrupts = <16 2 1 0>;
164 fsl,ccf-num-csdids = <32>;
165 fsl,ccf-num-snoopids = <32>;
166 };
167
168 iommu@20000 {
169 compatible = "fsl,pamu-v1.0", "fsl,pamu";
170 reg = <0x20000 0x4000>;
171 #address-cells = <1>;
172 #size-cells = <1>;
173 interrupts = <
174 24 2 0 0
175 16 2 1 1>;
176
177
178 /* PCIe, DMA, SRIO */
179 pamu0: pamu@0 {
180 reg = <0 0x1000>;
181 fsl,primary-cache-geometry = <8 1>;
182 fsl,secondary-cache-geometry = <32 2>;
183 };
184
185 /* AXI2, Maple */
186 pamu1: pamu@1000 {
187 reg = <0x1000 0x1000>;
188 fsl,primary-cache-geometry = <32 1>;
189 fsl,secondary-cache-geometry = <32 2>;
190 };
191
192 /* Q/BMan */
193 pamu2: pamu@2000 {
194 reg = <0x2000 0x1000>;
195 fsl,primary-cache-geometry = <32 1>;
196 fsl,secondary-cache-geometry = <32 2>;
197 };
198
199 /* AXI1, FMAN */
200 pamu3: pamu@3000 {
201 reg = <0x3000 0x1000>;
202 fsl,primary-cache-geometry = <32 1>;
203 fsl,secondary-cache-geometry = <32 2>;
204 };
205 };
206
207/include/ "qoriq-mpic.dtsi"
208
209 guts: global-utilities@e0000 {
210 compatible = "fsl,b4-device-config";
211 reg = <0xe0000 0xe00>;
212 fsl,has-rstcr;
213 fsl,liodn-bits = <12>;
214 };
215
216 clockgen: global-utilities@e1000 {
217 compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
218 reg = <0xe1000 0x1000>;
219 };
220
221 rcpm: global-utilities@e2000 {
222 compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
223 reg = <0xe2000 0x1000>;
224 };
225
226/include/ "qoriq-dma-0.dtsi"
227 dma@100300 {
228 fsl,iommu-parent = <&pamu0>;
229 fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
230 };
231
232/include/ "qoriq-dma-1.dtsi"
233 dma@101300 {
234 fsl,iommu-parent = <&pamu0>;
235 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
236 };
237
238/include/ "qonverge-usb2-dr-0.dtsi"
239 usb0: usb@210000 {
240 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
241 fsl,iommu-parent = <&pamu1>;
242 fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
243 };
244
245/include/ "qoriq-espi-0.dtsi"
246 spi@110000 {
247 fsl,espi-num-chipselects = <4>;
248 };
249
250/include/ "qoriq-esdhc-0.dtsi"
251 sdhc@114000 {
252 sdhci,auto-cmd12;
253 fsl,iommu-parent = <&pamu1>;
254 fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
255 };
256
257/include/ "qoriq-i2c-0.dtsi"
258/include/ "qoriq-i2c-1.dtsi"
259/include/ "qoriq-duart-0.dtsi"
260/include/ "qoriq-duart-1.dtsi"
261/include/ "qoriq-sec5.3-0.dtsi"
262
263 L2: l2-cache-controller@c20000 {
264 compatible = "fsl,b4-l2-cache-controller";
265 reg = <0xc20000 0x1000>;
266 next-level-cache = <&cpc>;
267 };
268};
diff --git a/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
index 870c6535a053..ea145c91cfbd 100644
--- a/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
+++ b/arch/powerpc/boot/dts/fsl/e500mc_power_isa.dtsi
@@ -53,6 +53,7 @@
53 power-isa-mmc; // Memory Coherence 53 power-isa-mmc; // Memory Coherence
54 power-isa-scpm; // Store Conditional Page Mobility 54 power-isa-scpm; // Store Conditional Page Mobility
55 power-isa-wt; // Wait 55 power-isa-wt; // Wait
56 fsl,eref-deo; // Data Cache Extended Operations
56 mmu-type = "power-embedded"; 57 mmu-type = "power-embedded";
57 }; 58 };
58}; 59};
diff --git a/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
index 3230212f7ad5..c254c981ae87 100644
--- a/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
+++ b/arch/powerpc/boot/dts/fsl/e5500_power_isa.dtsi
@@ -54,6 +54,7 @@
54 power-isa-scpm; // Store Conditional Page Mobility 54 power-isa-scpm; // Store Conditional Page Mobility
55 power-isa-wt; // Wait 55 power-isa-wt; // Wait
56 power-isa-64; // 64-bit 56 power-isa-64; // 64-bit
57 fsl,eref-deo; // Data Cache Extended Operations
57 mmu-type = "power-embedded"; 58 mmu-type = "power-embedded";
58 }; 59 };
59}; 60};
diff --git a/arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi b/arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
new file mode 100644
index 000000000000..a912dbeff359
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
@@ -0,0 +1,65 @@
1/*
2 * e6500 Power ISA Device Tree Source (include)
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/ {
36 cpus {
37 power-isa-version = "2.06";
38 power-isa-b; // Base
39 power-isa-e; // Embedded
40 power-isa-atb; // Alternate Time Base
41 power-isa-cs; // Cache Specification
42 power-isa-ds; // Decorated Storage
43 power-isa-e.ed; // Embedded.Enhanced Debug
44 power-isa-e.pd; // Embedded.External PID
45 power-isa-e.hv; // Embedded.Hypervisor
46 power-isa-e.le; // Embedded.Little-Endian
47 power-isa-e.pm; // Embedded.Performance Monitor
48 power-isa-e.pc; // Embedded.Processor Control
49 power-isa-ecl; // Embedded Cache Locking
50 power-isa-exp; // External Proxy
51 power-isa-fp; // Floating Point
52 power-isa-fp.r; // Floating Point.Record
53 power-isa-mmc; // Memory Coherence
54 power-isa-scpm; // Store Conditional Page Mobility
55 power-isa-wt; // Wait
56 power-isa-64; // 64-bit
57 power-isa-e.pt; // Embedded.Page Table
58 power-isa-e.hv.lrat; // Embedded.Hypervisor.LRAT
59 power-isa-e.em; // Embedded Multi-Threading
60 power-isa-v; // Vector (AltiVec)
61 fsl,eref-er; // Enhanced Reservations (Load and Reserve and Store Cond.)
62 fsl,eref-deo; // Data Cache Extended Operations
63 mmu-type = "power-embedded";
64 };
65};
diff --git a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
index 941fa159cefb..f1105bffa915 100644
--- a/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p1023si-post.dtsi
@@ -148,6 +148,7 @@
148 148
149 crypto: crypto@300000 { 149 crypto: crypto@300000 {
150 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0"; 150 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
151 fsl,sec-era = <3>;
151 #address-cells = <1>; 152 #address-cells = <1>;
152 #size-cells = <1>; 153 #size-cells = <1>;
153 reg = <0x30000 0x10000>; 154 reg = <0x30000 0x10000>;
diff --git a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
index 69ac1acd4349..dc6cc5afd189 100644
--- a/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p2041si-post.dtsi
@@ -155,7 +155,7 @@
155 compatible = "fsl,dcsr", "simple-bus"; 155 compatible = "fsl,dcsr", "simple-bus";
156 156
157 dcsr-epu@0 { 157 dcsr-epu@0 {
158 compatible = "fsl,dcsr-epu"; 158 compatible = "fsl,p2041-dcsr-epu", "fsl,dcsr-epu";
159 interrupts = <52 2 0 0 159 interrupts = <52 2 0 0
160 84 2 0 0 160 84 2 0 0
161 85 2 0 0>; 161 85 2 0 0>;
diff --git a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
index 9b5a81a4529c..3fa1e22d544a 100644
--- a/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p3041si-post.dtsi
@@ -182,7 +182,7 @@
182 compatible = "fsl,dcsr", "simple-bus"; 182 compatible = "fsl,dcsr", "simple-bus";
183 183
184 dcsr-epu@0 { 184 dcsr-epu@0 {
185 compatible = "fsl,dcsr-epu"; 185 compatible = "fsl,p3041-dcsr-epu", "fsl,dcsr-epu";
186 interrupts = <52 2 0 0 186 interrupts = <52 2 0 0
187 84 2 0 0 187 84 2 0 0
188 85 2 0 0>; 188 85 2 0 0>;
diff --git a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
index 19859ad851eb..34769a7eafea 100644
--- a/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p4080si-post.dtsi
@@ -156,7 +156,7 @@
156 compatible = "fsl,dcsr", "simple-bus"; 156 compatible = "fsl,dcsr", "simple-bus";
157 157
158 dcsr-epu@0 { 158 dcsr-epu@0 {
159 compatible = "fsl,dcsr-epu"; 159 compatible = "fsl,p4080-dcsr-epu", "fsl,dcsr-epu";
160 interrupts = <52 2 0 0 160 interrupts = <52 2 0 0
161 84 2 0 0 161 84 2 0 0
162 85 2 0 0>; 162 85 2 0 0>;
diff --git a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
index 9ea77c3513f6..bc3ae5a2252f 100644
--- a/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5020si-post.dtsi
@@ -184,7 +184,7 @@
184 compatible = "fsl,dcsr", "simple-bus"; 184 compatible = "fsl,dcsr", "simple-bus";
185 185
186 dcsr-epu@0 { 186 dcsr-epu@0 {
187 compatible = "fsl,dcsr-epu"; 187 compatible = "fsl,p5020-dcsr-epu", "fsl,dcsr-epu";
188 interrupts = <52 2 0 0 188 interrupts = <52 2 0 0
189 84 2 0 0 189 84 2 0 0
190 85 2 0 0>; 190 85 2 0 0>;
diff --git a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
index 97f8c26f9709..a91897f6af09 100644
--- a/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/p5040si-post.dtsi
@@ -129,7 +129,7 @@
129 compatible = "fsl,dcsr", "simple-bus"; 129 compatible = "fsl,dcsr", "simple-bus";
130 130
131 dcsr-epu@0 { 131 dcsr-epu@0 {
132 compatible = "fsl,dcsr-epu"; 132 compatible = "fsl,p5040-dcsr-epu", "fsl,dcsr-epu";
133 interrupts = <52 2 0 0 133 interrupts = <52 2 0 0
134 84 2 0 0 134 84 2 0 0
135 85 2 0 0>; 135 85 2 0 0>;
diff --git a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
index ffadcb563ada..bb3d8266b5ce 100644
--- a/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/pq3-sec4.4-0.dtsi
@@ -34,6 +34,7 @@
34 34
35crypto@30000 { 35crypto@30000 {
36 compatible = "fsl,sec-v4.4", "fsl,sec-v4.0"; 36 compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
37 #address-cells = <1>; 38 #address-cells = <1>;
38 #size-cells = <1>; 39 #size-cells = <1>;
39 ranges = <0x0 0x30000 0x10000>; 40 ranges = <0x0 0x30000 0x10000>;
diff --git a/arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi b/arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi
new file mode 100644
index 000000000000..29dad723091e
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi
@@ -0,0 +1,41 @@
1/*
2 * QorIQ Qonverge USB Host device tree stub [ controller @ offset 0x210000 ]
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35usb@210000 {
36 compatible = "fsl-usb2-dr";
37 reg = <0x210000 0x1000>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 interrupts = <44 0x2 0 0>;
41};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi
new file mode 100644
index 000000000000..c2f9cdadb604
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi
@@ -0,0 +1,41 @@
1/*
2 * QorIQ GPIO device tree stub [ controller @ offset 0x131000 ]
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35gpio1: gpio@131000 {
36 compatible = "fsl,qoriq-gpio";
37 reg = <0x131000 0x1000>;
38 interrupts = <54 2 0 0>;
39 #gpio-cells = <2>;
40 gpio-controller;
41};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi
new file mode 100644
index 000000000000..33f3ccbac83f
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi
@@ -0,0 +1,41 @@
1/*
2 * QorIQ GPIO device tree stub [ controller @ offset 0x132000 ]
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35gpio2: gpio@132000 {
36 compatible = "fsl,qoriq-gpio";
37 reg = <0x132000 0x1000>;
38 interrupts = <86 2 0 0>;
39 #gpio-cells = <2>;
40 gpio-controller;
41};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi
new file mode 100644
index 000000000000..86954e95ea02
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi
@@ -0,0 +1,41 @@
1/*
2 * QorIQ GPIO device tree stub [ controller @ offset 0x133000 ]
3 *
4 * Copyright 2013 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35gpio3: gpio@133000 {
36 compatible = "fsl,qoriq-gpio";
37 reg = <0x133000 0x1000>;
38 interrupts = <87 2 0 0>;
39 #gpio-cells = <2>;
40 gpio-controller;
41};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi
index 0cbbac329539..02bee5fcbb9a 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec4.0-0.dtsi
@@ -34,6 +34,7 @@
34 34
35crypto: crypto@300000 { 35crypto: crypto@300000 {
36 compatible = "fsl,sec-v4.0"; 36 compatible = "fsl,sec-v4.0";
37 fsl,sec-era = <1>;
37 #address-cells = <1>; 38 #address-cells = <1>;
38 #size-cells = <1>; 39 #size-cells = <1>;
39 reg = <0x300000 0x10000>; 40 reg = <0x300000 0x10000>;
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi
index 7990e0d3d6f2..7f7574e53323 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec4.2-0.dtsi
@@ -34,6 +34,7 @@
34 34
35crypto: crypto@300000 { 35crypto: crypto@300000 {
36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0"; 36 compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
37 fsl,sec-era = <3>;
37 #address-cells = <1>; 38 #address-cells = <1>;
38 #size-cells = <1>; 39 #size-cells = <1>;
39 reg = <0x300000 0x10000>; 40 reg = <0x300000 0x10000>;
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi
index 3308986bba0d..e298efbb0f3e 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-sec4.1-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec5.0-0.dtsi
@@ -1,7 +1,7 @@
1/* 1/*
2 * QorIQ Sec/Crypto 4.1 device tree stub [ controller @ offset 0x300000 ] 2 * QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
3 * 3 *
4 * Copyright 2011 Freescale Semiconductor Inc. 4 * Copyright 2012 Freescale Semiconductor Inc.
5 * 5 *
6 * Redistribution and use in source and binary forms, with or without 6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met: 7 * modification, are permitted provided that the following conditions are met:
@@ -33,7 +33,8 @@
33 */ 33 */
34 34
35crypto: crypto@300000 { 35crypto: crypto@300000 {
36 compatible = "fsl,sec-v4.1", "fsl,sec-v4.0"; 36 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
37 #address-cells = <1>; 38 #address-cells = <1>;
38 #size-cells = <1>; 39 #size-cells = <1>;
39 reg = <0x300000 0x10000>; 40 reg = <0x300000 0x10000>;
@@ -41,35 +42,35 @@ crypto: crypto@300000 {
41 interrupts = <92 2 0 0>; 42 interrupts = <92 2 0 0>;
42 43
43 sec_jr0: jr@1000 { 44 sec_jr0: jr@1000 {
44 compatible = "fsl,sec-v4.1-job-ring", 45 compatible = "fsl,sec-v5.0-job-ring",
45 "fsl,sec-v4.0-job-ring"; 46 "fsl,sec-v4.0-job-ring";
46 reg = <0x1000 0x1000>; 47 reg = <0x1000 0x1000>;
47 interrupts = <88 2 0 0>; 48 interrupts = <88 2 0 0>;
48 }; 49 };
49 50
50 sec_jr1: jr@2000 { 51 sec_jr1: jr@2000 {
51 compatible = "fsl,sec-v4.1-job-ring", 52 compatible = "fsl,sec-v5.0-job-ring",
52 "fsl,sec-v4.0-job-ring"; 53 "fsl,sec-v4.0-job-ring";
53 reg = <0x2000 0x1000>; 54 reg = <0x2000 0x1000>;
54 interrupts = <89 2 0 0>; 55 interrupts = <89 2 0 0>;
55 }; 56 };
56 57
57 sec_jr2: jr@3000 { 58 sec_jr2: jr@3000 {
58 compatible = "fsl,sec-v4.1-job-ring", 59 compatible = "fsl,sec-v5.0-job-ring",
59 "fsl,sec-v4.0-job-ring"; 60 "fsl,sec-v4.0-job-ring";
60 reg = <0x3000 0x1000>; 61 reg = <0x3000 0x1000>;
61 interrupts = <90 2 0 0>; 62 interrupts = <90 2 0 0>;
62 }; 63 };
63 64
64 sec_jr3: jr@4000 { 65 sec_jr3: jr@4000 {
65 compatible = "fsl,sec-v4.1-job-ring", 66 compatible = "fsl,sec-v5.0-job-ring",
66 "fsl,sec-v4.0-job-ring"; 67 "fsl,sec-v4.0-job-ring";
67 reg = <0x4000 0x1000>; 68 reg = <0x4000 0x1000>;
68 interrupts = <91 2 0 0>; 69 interrupts = <91 2 0 0>;
69 }; 70 };
70 71
71 rtic@6000 { 72 rtic@6000 {
72 compatible = "fsl,sec-v4.1-rtic", 73 compatible = "fsl,sec-v5.0-rtic",
73 "fsl,sec-v4.0-rtic"; 74 "fsl,sec-v4.0-rtic";
74 #address-cells = <1>; 75 #address-cells = <1>;
75 #size-cells = <1>; 76 #size-cells = <1>;
@@ -77,25 +78,25 @@ crypto: crypto@300000 {
77 ranges = <0x0 0x6100 0xe00>; 78 ranges = <0x0 0x6100 0xe00>;
78 79
79 rtic_a: rtic-a@0 { 80 rtic_a: rtic-a@0 {
80 compatible = "fsl,sec-v4.1-rtic-memory", 81 compatible = "fsl,sec-v5.0-rtic-memory",
81 "fsl,sec-v4.0-rtic-memory"; 82 "fsl,sec-v4.0-rtic-memory";
82 reg = <0x00 0x20 0x100 0x80>; 83 reg = <0x00 0x20 0x100 0x80>;
83 }; 84 };
84 85
85 rtic_b: rtic-b@20 { 86 rtic_b: rtic-b@20 {
86 compatible = "fsl,sec-v4.1-rtic-memory", 87 compatible = "fsl,sec-v5.0-rtic-memory",
87 "fsl,sec-v4.0-rtic-memory"; 88 "fsl,sec-v4.0-rtic-memory";
88 reg = <0x20 0x20 0x200 0x80>; 89 reg = <0x20 0x20 0x200 0x80>;
89 }; 90 };
90 91
91 rtic_c: rtic-c@40 { 92 rtic_c: rtic-c@40 {
92 compatible = "fsl,sec-v4.1-rtic-memory", 93 compatible = "fsl,sec-v5.0-rtic-memory",
93 "fsl,sec-v4.0-rtic-memory"; 94 "fsl,sec-v4.0-rtic-memory";
94 reg = <0x40 0x20 0x300 0x80>; 95 reg = <0x40 0x20 0x300 0x80>;
95 }; 96 };
96 97
97 rtic_d: rtic-d@60 { 98 rtic_d: rtic-d@60 {
98 compatible = "fsl,sec-v4.1-rtic-memory", 99 compatible = "fsl,sec-v5.0-rtic-memory",
99 "fsl,sec-v4.0-rtic-memory"; 100 "fsl,sec-v4.0-rtic-memory";
100 reg = <0x60 0x20 0x500 0x80>; 101 reg = <0x60 0x20 0x500 0x80>;
101 }; 102 };
@@ -103,7 +104,7 @@ crypto: crypto@300000 {
103}; 104};
104 105
105sec_mon: sec_mon@314000 { 106sec_mon: sec_mon@314000 {
106 compatible = "fsl,sec-v4.1-mon", "fsl,sec-v4.0-mon"; 107 compatible = "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
107 reg = <0x314000 0x1000>; 108 reg = <0x314000 0x1000>;
108 interrupts = <93 2 0 0>; 109 interrupts = <93 2 0 0>;
109}; 110};
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
index 7b2ab8a8c1f4..33ff09d52e05 100644
--- a/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec5.2-0.dtsi
@@ -34,6 +34,7 @@
34 34
35crypto: crypto@300000 { 35crypto: crypto@300000 {
36 compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0"; 36 compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <5>;
37 #address-cells = <1>; 38 #address-cells = <1>;
38 #size-cells = <1>; 39 #size-cells = <1>;
39 reg = <0x300000 0x10000>; 40 reg = <0x300000 0x10000>;
diff --git a/arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi b/arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi
new file mode 100644
index 000000000000..08778221c194
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi
@@ -0,0 +1,119 @@
1/*
2 * QorIQ Sec/Crypto 5.3 device tree stub [ controller @ offset 0x300000 ]
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35crypto: crypto@300000 {
36 compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
37 fsl,sec-era = <4>;
38 #address-cells = <1>;
39 #size-cells = <1>;
40 reg = <0x300000 0x10000>;
41 ranges = <0 0x300000 0x10000>;
42 interrupts = <92 2 0 0>;
43
44 sec_jr0: jr@1000 {
45 compatible = "fsl,sec-v5.3-job-ring",
46 "fsl,sec-v5.0-job-ring",
47 "fsl,sec-v4.0-job-ring";
48 reg = <0x1000 0x1000>;
49 interrupts = <88 2 0 0>;
50 };
51
52 sec_jr1: jr@2000 {
53 compatible = "fsl,sec-v5.3-job-ring",
54 "fsl,sec-v5.0-job-ring",
55 "fsl,sec-v4.0-job-ring";
56 reg = <0x2000 0x1000>;
57 interrupts = <89 2 0 0>;
58 };
59
60 sec_jr2: jr@3000 {
61 compatible = "fsl,sec-v5.3-job-ring",
62 "fsl,sec-v5.0-job-ring",
63 "fsl,sec-v4.0-job-ring";
64 reg = <0x3000 0x1000>;
65 interrupts = <90 2 0 0>;
66 };
67
68 sec_jr3: jr@4000 {
69 compatible = "fsl,sec-v5.3-job-ring",
70 "fsl,sec-v5.0-job-ring",
71 "fsl,sec-v4.0-job-ring";
72 reg = <0x4000 0x1000>;
73 interrupts = <91 2 0 0>;
74 };
75
76 rtic@6000 {
77 compatible = "fsl,sec-v5.3-rtic",
78 "fsl,sec-v5.0-rtic",
79 "fsl,sec-v4.0-rtic";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 reg = <0x6000 0x100>;
83 ranges = <0x0 0x6100 0xe00>;
84
85 rtic_a: rtic-a@0 {
86 compatible = "fsl,sec-v5.3-rtic-memory",
87 "fsl,sec-v5.0-rtic-memory",
88 "fsl,sec-v4.0-rtic-memory";
89 reg = <0x00 0x20 0x100 0x80>;
90 };
91
92 rtic_b: rtic-b@20 {
93 compatible = "fsl,sec-v5.3-rtic-memory",
94 "fsl,sec-v5.0-rtic-memory",
95 "fsl,sec-v4.0-rtic-memory";
96 reg = <0x20 0x20 0x200 0x80>;
97 };
98
99 rtic_c: rtic-c@40 {
100 compatible = "fsl,sec-v5.3-rtic-memory",
101 "fsl,sec-v5.0-rtic-memory",
102 "fsl,sec-v4.0-rtic-memory";
103 reg = <0x40 0x20 0x300 0x80>;
104 };
105
106 rtic_d: rtic-d@60 {
107 compatible = "fsl,sec-v5.3-rtic-memory",
108 "fsl,sec-v5.0-rtic-memory",
109 "fsl,sec-v4.0-rtic-memory";
110 reg = <0x60 0x20 0x500 0x80>;
111 };
112 };
113};
114
115sec_mon: sec_mon@314000 {
116 compatible = "fsl,sec-v5.3-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
117 reg = <0x314000 0x1000>;
118 interrupts = <93 2 0 0>;
119};
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
new file mode 100644
index 000000000000..bd611a9cad32
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
@@ -0,0 +1,442 @@
1/*
2 * T4240 Silicon/SoC Device Tree Source (post include)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35&ifc {
36 #address-cells = <2>;
37 #size-cells = <1>;
38 compatible = "fsl,ifc", "simple-bus";
39 interrupts = <25 2 0 0>;
40};
41
42/* controller at 0x240000 */
43&pci0 {
44 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
45 device_type = "pci";
46 #size-cells = <2>;
47 #address-cells = <3>;
48 bus-range = <0x0 0xff>;
49 interrupts = <20 2 0 0>;
50 pcie@0 {
51 #interrupt-cells = <1>;
52 #size-cells = <2>;
53 #address-cells = <3>;
54 device_type = "pci";
55 reg = <0 0 0 0 0>;
56 interrupts = <20 2 0 0>;
57 interrupt-map-mask = <0xf800 0 0 7>;
58 interrupt-map = <
59 /* IDSEL 0x0 */
60 0000 0 0 1 &mpic 40 1 0 0
61 0000 0 0 2 &mpic 1 1 0 0
62 0000 0 0 3 &mpic 2 1 0 0
63 0000 0 0 4 &mpic 3 1 0 0
64 >;
65 };
66};
67
68/* controller at 0x250000 */
69&pci1 {
70 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
71 device_type = "pci";
72 #size-cells = <2>;
73 #address-cells = <3>;
74 bus-range = <0 0xff>;
75 interrupts = <21 2 0 0>;
76 pcie@0 {
77 #interrupt-cells = <1>;
78 #size-cells = <2>;
79 #address-cells = <3>;
80 device_type = "pci";
81 reg = <0 0 0 0 0>;
82 interrupts = <21 2 0 0>;
83 interrupt-map-mask = <0xf800 0 0 7>;
84 interrupt-map = <
85 /* IDSEL 0x0 */
86 0000 0 0 1 &mpic 41 1 0 0
87 0000 0 0 2 &mpic 5 1 0 0
88 0000 0 0 3 &mpic 6 1 0 0
89 0000 0 0 4 &mpic 7 1 0 0
90 >;
91 };
92};
93
94/* controller at 0x260000 */
95&pci2 {
96 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
97 device_type = "pci";
98 #size-cells = <2>;
99 #address-cells = <3>;
100 bus-range = <0x0 0xff>;
101 interrupts = <22 2 0 0>;
102 pcie@0 {
103 #interrupt-cells = <1>;
104 #size-cells = <2>;
105 #address-cells = <3>;
106 device_type = "pci";
107 reg = <0 0 0 0 0>;
108 interrupts = <22 2 0 0>;
109 interrupt-map-mask = <0xf800 0 0 7>;
110 interrupt-map = <
111 /* IDSEL 0x0 */
112 0000 0 0 1 &mpic 42 1 0 0
113 0000 0 0 2 &mpic 9 1 0 0
114 0000 0 0 3 &mpic 10 1 0 0
115 0000 0 0 4 &mpic 11 1 0 0
116 >;
117 };
118};
119
120/* controller at 0x270000 */
121&pci3 {
122 compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
123 device_type = "pci";
124 #size-cells = <2>;
125 #address-cells = <3>;
126 bus-range = <0x0 0xff>;
127 interrupts = <23 2 0 0>;
128 pcie@0 {
129 #interrupt-cells = <1>;
130 #size-cells = <2>;
131 #address-cells = <3>;
132 device_type = "pci";
133 reg = <0 0 0 0 0>;
134 interrupts = <23 2 0 0>;
135 interrupt-map-mask = <0xf800 0 0 7>;
136 interrupt-map = <
137 /* IDSEL 0x0 */
138 0000 0 0 1 &mpic 43 1 0 0
139 0000 0 0 2 &mpic 0 1 0 0
140 0000 0 0 3 &mpic 4 1 0 0
141 0000 0 0 4 &mpic 8 1 0 0
142 >;
143 };
144};
145
146&rio {
147 compatible = "fsl,srio";
148 interrupts = <16 2 1 11>;
149 #address-cells = <2>;
150 #size-cells = <2>;
151 ranges;
152
153 port1 {
154 #address-cells = <2>;
155 #size-cells = <2>;
156 cell-index = <1>;
157 };
158
159 port2 {
160 #address-cells = <2>;
161 #size-cells = <2>;
162 cell-index = <2>;
163 };
164};
165
166&dcsr {
167 #address-cells = <1>;
168 #size-cells = <1>;
169 compatible = "fsl,dcsr", "simple-bus";
170
171 dcsr-epu@0 {
172 compatible = "fsl,t4240-dcsr-epu", "fsl,dcsr-epu";
173 interrupts = <52 2 0 0
174 84 2 0 0
175 85 2 0 0
176 94 2 0 0
177 95 2 0 0>;
178 reg = <0x0 0x1000>;
179 };
180 dcsr-npc {
181 compatible = "fsl,t4240-dcsr-cnpc", "fsl,dcsr-cnpc";
182 reg = <0x1000 0x1000 0x1002000 0x10000>;
183 };
184 dcsr-nxc@2000 {
185 compatible = "fsl,dcsr-nxc";
186 reg = <0x2000 0x1000>;
187 };
188 dcsr-corenet {
189 compatible = "fsl,dcsr-corenet";
190 reg = <0x8000 0x1000 0x1A000 0x1000>;
191 };
192 dcsr-dpaa@9000 {
193 compatible = "fsl,t4240-dcsr-dpaa", "fsl,dcsr-dpaa";
194 reg = <0x9000 0x1000>;
195 };
196 dcsr-ocn@11000 {
197 compatible = "fsl,t4240-dcsr-ocn", "fsl,dcsr-ocn";
198 reg = <0x11000 0x1000>;
199 };
200 dcsr-ddr@12000 {
201 compatible = "fsl,dcsr-ddr";
202 dev-handle = <&ddr1>;
203 reg = <0x12000 0x1000>;
204 };
205 dcsr-ddr@13000 {
206 compatible = "fsl,dcsr-ddr";
207 dev-handle = <&ddr2>;
208 reg = <0x13000 0x1000>;
209 };
210 dcsr-ddr@14000 {
211 compatible = "fsl,dcsr-ddr";
212 dev-handle = <&ddr3>;
213 reg = <0x14000 0x1000>;
214 };
215 dcsr-nal@18000 {
216 compatible = "fsl,t4240-dcsr-nal", "fsl,dcsr-nal";
217 reg = <0x18000 0x1000>;
218 };
219 dcsr-rcpm@22000 {
220 compatible = "fsl,t4240-dcsr-rcpm", "fsl,dcsr-rcpm";
221 reg = <0x22000 0x1000>;
222 };
223 dcsr-snpc@30000 {
224 compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
225 reg = <0x30000 0x1000 0x1022000 0x10000>;
226 };
227 dcsr-snpc@31000 {
228 compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
229 reg = <0x31000 0x1000 0x1042000 0x10000>;
230 };
231 dcsr-snpc@32000 {
232 compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
233 reg = <0x32000 0x1000 0x1062000 0x10000>;
234 };
235 dcsr-cpu-sb-proxy@100000 {
236 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
237 cpu-handle = <&cpu0>;
238 reg = <0x100000 0x1000 0x101000 0x1000>;
239 };
240 dcsr-cpu-sb-proxy@108000 {
241 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
242 cpu-handle = <&cpu1>;
243 reg = <0x108000 0x1000 0x109000 0x1000>;
244 };
245 dcsr-cpu-sb-proxy@110000 {
246 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
247 cpu-handle = <&cpu2>;
248 reg = <0x110000 0x1000 0x111000 0x1000>;
249 };
250 dcsr-cpu-sb-proxy@118000 {
251 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
252 cpu-handle = <&cpu3>;
253 reg = <0x118000 0x1000 0x119000 0x1000>;
254 };
255 dcsr-cpu-sb-proxy@120000 {
256 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
257 cpu-handle = <&cpu4>;
258 reg = <0x120000 0x1000 0x121000 0x1000>;
259 };
260 dcsr-cpu-sb-proxy@128000 {
261 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
262 cpu-handle = <&cpu5>;
263 reg = <0x128000 0x1000 0x129000 0x1000>;
264 };
265 dcsr-cpu-sb-proxy@130000 {
266 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
267 cpu-handle = <&cpu6>;
268 reg = <0x130000 0x1000 0x131000 0x1000>;
269 };
270 dcsr-cpu-sb-proxy@138000 {
271 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
272 cpu-handle = <&cpu7>;
273 reg = <0x138000 0x1000 0x139000 0x1000>;
274 };
275 dcsr-cpu-sb-proxy@140000 {
276 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
277 cpu-handle = <&cpu8>;
278 reg = <0x140000 0x1000 0x141000 0x1000>;
279 };
280 dcsr-cpu-sb-proxy@148000 {
281 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
282 cpu-handle = <&cpu9>;
283 reg = <0x148000 0x1000 0x149000 0x1000>;
284 };
285 dcsr-cpu-sb-proxy@150000 {
286 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
287 cpu-handle = <&cpu10>;
288 reg = <0x150000 0x1000 0x151000 0x1000>;
289 };
290 dcsr-cpu-sb-proxy@158000 {
291 compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
292 cpu-handle = <&cpu11>;
293 reg = <0x158000 0x1000 0x159000 0x1000>;
294 };
295};
296
297&soc {
298 #address-cells = <1>;
299 #size-cells = <1>;
300 device_type = "soc";
301 compatible = "simple-bus";
302
303 soc-sram-error {
304 compatible = "fsl,soc-sram-error";
305 interrupts = <16 2 1 29>;
306 };
307
308 corenet-law@0 {
309 compatible = "fsl,corenet-law";
310 reg = <0x0 0x1000>;
311 fsl,num-laws = <32>;
312 };
313
314 ddr1: memory-controller@8000 {
315 compatible = "fsl,qoriq-memory-controller-v4.7",
316 "fsl,qoriq-memory-controller";
317 reg = <0x8000 0x1000>;
318 interrupts = <16 2 1 23>;
319 };
320
321 ddr2: memory-controller@9000 {
322 compatible = "fsl,qoriq-memory-controller-v4.7",
323 "fsl,qoriq-memory-controller";
324 reg = <0x9000 0x1000>;
325 interrupts = <16 2 1 22>;
326 };
327
328 ddr3: memory-controller@a000 {
329 compatible = "fsl,qoriq-memory-controller-v4.7",
330 "fsl,qoriq-memory-controller";
331 reg = <0xa000 0x1000>;
332 interrupts = <16 2 1 21>;
333 };
334
335 cpc: l3-cache-controller@10000 {
336 compatible = "fsl,t4240-l3-cache-controller", "cache";
337 reg = <0x10000 0x1000
338 0x11000 0x1000
339 0x12000 0x1000>;
340 interrupts = <16 2 1 27
341 16 2 1 26
342 16 2 1 25>;
343 };
344
345 corenet-cf@18000 {
346 compatible = "fsl,corenet-cf";
347 reg = <0x18000 0x1000>;
348 interrupts = <16 2 1 31>;
349 fsl,ccf-num-csdids = <32>;
350 fsl,ccf-num-snoopids = <32>;
351 };
352
353 iommu@20000 {
354 compatible = "fsl,pamu-v1.0", "fsl,pamu";
355 reg = <0x20000 0x6000>;
356 interrupts = <
357 24 2 0 0
358 16 2 1 30>;
359 };
360
361/include/ "qoriq-mpic.dtsi"
362
363 guts: global-utilities@e0000 {
364 compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
365 reg = <0xe0000 0xe00>;
366 fsl,has-rstcr;
367 fsl,liodn-bits = <12>;
368 };
369
370 clockgen: global-utilities@e1000 {
371 compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
372 reg = <0xe1000 0x1000>;
373 };
374
375 rcpm: global-utilities@e2000 {
376 compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
377 reg = <0xe2000 0x1000>;
378 };
379
380 sfp: sfp@e8000 {
381 compatible = "fsl,t4240-sfp";
382 reg = <0xe8000 0x1000>;
383 };
384
385 serdes: serdes@ea000 {
386 compatible = "fsl,t4240-serdes";
387 reg = <0xea000 0x4000>;
388 };
389
390/include/ "qoriq-dma-0.dtsi"
391/include/ "qoriq-dma-1.dtsi"
392
393/include/ "qoriq-espi-0.dtsi"
394 spi@110000 {
395 fsl,espi-num-chipselects = <4>;
396 };
397
398/include/ "qoriq-esdhc-0.dtsi"
399 sdhc@114000 {
400 compatible = "fsl,t4240-esdhc", "fsl,esdhc";
401 sdhci,auto-cmd12;
402 };
403/include/ "qoriq-i2c-0.dtsi"
404/include/ "qoriq-i2c-1.dtsi"
405/include/ "qoriq-duart-0.dtsi"
406/include/ "qoriq-duart-1.dtsi"
407/include/ "qoriq-gpio-0.dtsi"
408/include/ "qoriq-gpio-1.dtsi"
409/include/ "qoriq-gpio-2.dtsi"
410/include/ "qoriq-gpio-3.dtsi"
411/include/ "qoriq-usb2-mph-0.dtsi"
412 usb0: usb@210000 {
413 compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph";
414 phy_type = "utmi";
415 port0;
416 };
417/include/ "qoriq-usb2-dr-0.dtsi"
418 usb1: usb@211000 {
419 compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
420 dr_mode = "host";
421 phy_type = "utmi";
422 };
423/include/ "qoriq-sata2-0.dtsi"
424/include/ "qoriq-sata2-1.dtsi"
425/include/ "qoriq-sec5.0-0.dtsi"
426
427 L2_1: l2-cache-controller@c20000 {
428 compatible = "fsl,t4240-l2-cache-controller";
429 reg = <0xc20000 0x40000>;
430 next-level-cache = <&cpc>;
431 };
432 L2_2: l2-cache-controller@c60000 {
433 compatible = "fsl,t4240-l2-cache-controller";
434 reg = <0xc60000 0x40000>;
435 next-level-cache = <&cpc>;
436 };
437 L2_3: l2-cache-controller@ca0000 {
438 compatible = "fsl,t4240-l2-cache-controller";
439 reg = <0xca0000 0x40000>;
440 next-level-cache = <&cpc>;
441 };
442};
diff --git a/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
new file mode 100644
index 000000000000..a93c55a88560
--- /dev/null
+++ b/arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
@@ -0,0 +1,128 @@
1/*
2 * T4240 Silicon/SoC Device Tree Source (pre include)
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/dts-v1/;
36
37/include/ "e6500_power_isa.dtsi"
38
39/ {
40 compatible = "fsl,T4240";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
44
45 aliases {
46 ccsr = &soc;
47 dcsr = &dcsr;
48
49 serial0 = &serial0;
50 serial1 = &serial1;
51 serial2 = &serial2;
52 serial3 = &serial3;
53 crypto = &crypto;
54 pci0 = &pci0;
55 pci1 = &pci1;
56 pci2 = &pci2;
57 pci3 = &pci3;
58 dma0 = &dma0;
59 dma1 = &dma1;
60 sdhc = &sdhc;
61 };
62
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 cpu0: PowerPC,e6500@0 {
68 device_type = "cpu";
69 reg = <0 1>;
70 next-level-cache = <&L2_1>;
71 };
72 cpu1: PowerPC,e6500@2 {
73 device_type = "cpu";
74 reg = <2 3>;
75 next-level-cache = <&L2_1>;
76 };
77 cpu2: PowerPC,e6500@4 {
78 device_type = "cpu";
79 reg = <4 5>;
80 next-level-cache = <&L2_1>;
81 };
82 cpu3: PowerPC,e6500@6 {
83 device_type = "cpu";
84 reg = <6 7>;
85 next-level-cache = <&L2_1>;
86 };
87 cpu4: PowerPC,e6500@8 {
88 device_type = "cpu";
89 reg = <8 9>;
90 next-level-cache = <&L2_2>;
91 };
92 cpu5: PowerPC,e6500@10 {
93 device_type = "cpu";
94 reg = <10 11>;
95 next-level-cache = <&L2_2>;
96 };
97 cpu6: PowerPC,e6500@12 {
98 device_type = "cpu";
99 reg = <12 13>;
100 next-level-cache = <&L2_2>;
101 };
102 cpu7: PowerPC,e6500@14 {
103 device_type = "cpu";
104 reg = <14 15>;
105 next-level-cache = <&L2_2>;
106 };
107 cpu8: PowerPC,e6500@16 {
108 device_type = "cpu";
109 reg = <16 17>;
110 next-level-cache = <&L2_3>;
111 };
112 cpu9: PowerPC,e6500@18 {
113 device_type = "cpu";
114 reg = <18 19>;
115 next-level-cache = <&L2_3>;
116 };
117 cpu10: PowerPC,e6500@20 {
118 device_type = "cpu";
119 reg = <20 21>;
120 next-level-cache = <&L2_3>;
121 };
122 cpu11: PowerPC,e6500@22 {
123 device_type = "cpu";
124 reg = <22 23>;
125 next-level-cache = <&L2_3>;
126 };
127 };
128};
diff --git a/arch/powerpc/boot/dts/mpc8536ds_36b.dts b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
index f8a3b3413176..6c723ee108cd 100644
--- a/arch/powerpc/boot/dts/mpc8536ds_36b.dts
+++ b/arch/powerpc/boot/dts/mpc8536ds_36b.dts
@@ -32,7 +32,7 @@
32 reg = <0 0 0 0>; // Filled by U-Boot 32 reg = <0 0 0 0>; // Filled by U-Boot
33 }; 33 };
34 34
35 lbc: localbus@ffe05000 { 35 lbc: localbus@fffe05000 {
36 reg = <0xf 0xffe05000 0 0x1000>; 36 reg = <0xf 0xffe05000 0 0x1000>;
37 37
38 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000 38 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
@@ -44,7 +44,7 @@
44 ranges = <0x0 0xf 0xffe00000 0x100000>; 44 ranges = <0x0 0xf 0xffe00000 0x100000>;
45 }; 45 };
46 46
47 pci0: pci@ffe08000 { 47 pci0: pci@fffe08000 {
48 reg = <0xf 0xffe08000 0 0x1000>; 48 reg = <0xf 0xffe08000 0 0x1000>;
49 ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000 49 ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
50 0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>; 50 0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
@@ -59,7 +59,7 @@
59 0x8800 0 0 4 &mpic 4 1 0 0>; 59 0x8800 0 0 4 &mpic 4 1 0 0>;
60 }; 60 };
61 61
62 pci1: pcie@ffe09000 { 62 pci1: pcie@fffe09000 {
63 reg = <0xf 0xffe09000 0 0x1000>; 63 reg = <0xf 0xffe09000 0 0x1000>;
64 ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000 64 ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000
65 0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>; 65 0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>;
diff --git a/arch/powerpc/boot/dts/p1021rdb-pc.dtsi b/arch/powerpc/boot/dts/p1021rdb-pc.dtsi
index c13abfbbe2e2..d6274c58f496 100644
--- a/arch/powerpc/boot/dts/p1021rdb-pc.dtsi
+++ b/arch/powerpc/boot/dts/p1021rdb-pc.dtsi
@@ -62,11 +62,19 @@
62 }; 62 };
63 63
64 partition@400000 { 64 partition@400000 {
65 /* 11MB for JFFS2 based Root file System */ 65 /* 10.75MB for JFFS2 based Root file System */
66 reg = <0x00400000 0x00b00000>; 66 reg = <0x00400000 0x00ac0000>;
67 label = "NOR JFFS2 Root File System"; 67 label = "NOR JFFS2 Root File System";
68 }; 68 };
69 69
70 partition@ec0000 {
71 /* This location must not be altered */
72 /* 256KB for QE ucode firmware*/
73 reg = <0x00ec0000 0x00040000>;
74 label = "NOR QE microcode firmware";
75 read-only;
76 };
77
70 partition@f00000 { 78 partition@f00000 {
71 /* This location must not be altered */ 79 /* This location must not be altered */
72 /* 512KB for u-boot Bootloader Image */ 80 /* 512KB for u-boot Bootloader Image */
diff --git a/arch/powerpc/boot/dts/p1025rdb_36b.dts b/arch/powerpc/boot/dts/p1025rdb_36b.dts
index 4ce4bfa0eda4..06deb6f341ba 100644
--- a/arch/powerpc/boot/dts/p1025rdb_36b.dts
+++ b/arch/powerpc/boot/dts/p1025rdb_36b.dts
@@ -82,6 +82,11 @@
82 0x0 0x100000>; 82 0x0 0x100000>;
83 }; 83 };
84 }; 84 };
85
86 qe: qe@fffe80000 {
87 status = "disabled"; /* no firmware loaded */
88 };
89
85}; 90};
86 91
87/include/ "p1025rdb.dtsi" 92/include/ "p1025rdb.dtsi"
diff --git a/arch/powerpc/boot/dts/t4240qds.dts b/arch/powerpc/boot/dts/t4240qds.dts
new file mode 100644
index 000000000000..0555976dd0f3
--- /dev/null
+++ b/arch/powerpc/boot/dts/t4240qds.dts
@@ -0,0 +1,224 @@
1/*
2 * T4240QDS Device Tree Source
3 *
4 * Copyright 2012 Freescale Semiconductor Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are met:
8 * * Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * * Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * * Neither the name of Freescale Semiconductor nor the
14 * names of its contributors may be used to endorse or promote products
15 * derived from this software without specific prior written permission.
16 *
17 *
18 * ALTERNATIVELY, this software may be distributed under the terms of the
19 * GNU General Public License ("GPL") as published by the Free Software
20 * Foundation, either version 2 of that License or (at your option) any
21 * later version.
22 *
23 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
24 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
26 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
27 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35/include/ "fsl/t4240si-pre.dtsi"
36
37/ {
38 model = "fsl,T4240QDS";
39 compatible = "fsl,T4240QDS";
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
43
44 ifc: localbus@ffe124000 {
45 reg = <0xf 0xfe124000 0 0x2000>;
46 ranges = <0 0 0xf 0xe8000000 0x08000000
47 2 0 0xf 0xff800000 0x00010000
48 3 0 0xf 0xffdf0000 0x00008000>;
49
50 nor@0,0 {
51 #address-cells = <1>;
52 #size-cells = <1>;
53 compatible = "cfi-flash";
54 reg = <0x0 0x0 0x8000000>;
55
56 bank-width = <2>;
57 device-width = <1>;
58 };
59
60 nand@2,0 {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 compatible = "fsl,ifc-nand";
64 reg = <0x2 0x0 0x10000>;
65
66 partition@0 {
67 /* This location must not be altered */
68 /* 1MB for u-boot Bootloader Image */
69 reg = <0x0 0x00100000>;
70 label = "NAND U-Boot Image";
71 read-only;
72 };
73
74 partition@100000 {
75 /* 1MB for DTB Image */
76 reg = <0x00100000 0x00100000>;
77 label = "NAND DTB Image";
78 };
79
80 partition@200000 {
81 /* 10MB for Linux Kernel Image */
82 reg = <0x00200000 0x00A00000>;
83 label = "NAND Linux Kernel Image";
84 };
85
86 partition@C00000 {
87 /* 500MB for Root file System Image */
88 reg = <0x00c00000 0x1F400000>;
89 label = "NAND RFS Image";
90 };
91 };
92
93 board-control@3,0 {
94 compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis";
95 reg = <3 0 0x300>;
96 };
97 };
98
99 memory {
100 device_type = "memory";
101 };
102
103 dcsr: dcsr@f00000000 {
104 ranges = <0x00000000 0xf 0x00000000 0x01072000>;
105 };
106
107 soc: soc@ffe000000 {
108 ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
109 reg = <0xf 0xfe000000 0 0x00001000>;
110 spi@110000 {
111 flash@0 {
112 #address-cells = <1>;
113 #size-cells = <1>;
114 compatible = "sst,sst25wf040";
115 reg = <0>;
116 spi-max-frequency = <40000000>; /* input clock */
117 };
118 };
119
120 i2c@118000 {
121 eeprom@51 {
122 compatible = "at24,24c256";
123 reg = <0x51>;
124 };
125 eeprom@52 {
126 compatible = "at24,24c256";
127 reg = <0x52>;
128 };
129 eeprom@53 {
130 compatible = "at24,24c256";
131 reg = <0x53>;
132 };
133 eeprom@54 {
134 compatible = "at24,24c256";
135 reg = <0x54>;
136 };
137 eeprom@55 {
138 compatible = "at24,24c256";
139 reg = <0x55>;
140 };
141 eeprom@56 {
142 compatible = "at24,24c256";
143 reg = <0x56>;
144 };
145 rtc@68 {
146 compatible = "dallas,ds3232";
147 reg = <0x68>;
148 interrupts = <0x1 0x1 0 0>;
149 };
150 };
151 };
152
153 pci0: pcie@ffe240000 {
154 reg = <0xf 0xfe240000 0 0x10000>;
155 ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
156 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
157 pcie@0 {
158 ranges = <0x02000000 0 0xe0000000
159 0x02000000 0 0xe0000000
160 0 0x20000000
161
162 0x01000000 0 0x00000000
163 0x01000000 0 0x00000000
164 0 0x00010000>;
165 };
166 };
167
168 pci1: pcie@ffe250000 {
169 reg = <0xf 0xfe250000 0 0x10000>;
170 ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
171 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
172 pcie@0 {
173 ranges = <0x02000000 0 0xe0000000
174 0x02000000 0 0xe0000000
175 0 0x20000000
176
177 0x01000000 0 0x00000000
178 0x01000000 0 0x00000000
179 0 0x00010000>;
180 };
181 };
182
183 pci2: pcie@ffe260000 {
184 reg = <0xf 0xfe260000 0 0x1000>;
185 ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
186 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
187 pcie@0 {
188 ranges = <0x02000000 0 0xe0000000
189 0x02000000 0 0xe0000000
190 0 0x20000000
191
192 0x01000000 0 0x00000000
193 0x01000000 0 0x00000000
194 0 0x00010000>;
195 };
196 };
197
198 pci3: pcie@ffe270000 {
199 reg = <0xf 0xfe270000 0 0x10000>;
200 ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
201 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
202 pcie@0 {
203 ranges = <0x02000000 0 0xe0000000
204 0x02000000 0 0xe0000000
205 0 0x20000000
206
207 0x01000000 0 0x00000000
208 0x01000000 0 0x00000000
209 0 0x00010000>;
210 };
211 };
212 rio: rapidio@ffe0c0000 {
213 reg = <0xf 0xfe0c0000 0 0x11000>;
214
215 port1 {
216 ranges = <0 0 0xc 0x20000000 0 0x10000000>;
217 };
218 port2 {
219 ranges = <0 0 0xc 0x30000000 0 0x10000000>;
220 };
221 };
222};
223
224/include/ "fsl/t4240si-post.dtsi"
diff --git a/arch/powerpc/configs/corenet64_smp_defconfig b/arch/powerpc/configs/corenet64_smp_defconfig
index 3d139fa04050..6c8b020806ff 100644
--- a/arch/powerpc/configs/corenet64_smp_defconfig
+++ b/arch/powerpc/configs/corenet64_smp_defconfig
@@ -1,14 +1,13 @@
1CONFIG_PPC64=y 1CONFIG_PPC64=y
2CONFIG_PPC_BOOK3E_64=y 2CONFIG_PPC_BOOK3E_64=y
3# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set 3CONFIG_ALTIVEC=y
4CONFIG_SMP=y 4CONFIG_SMP=y
5CONFIG_NR_CPUS=2 5CONFIG_NR_CPUS=24
6CONFIG_EXPERIMENTAL=y
7CONFIG_SYSVIPC=y 6CONFIG_SYSVIPC=y
8CONFIG_BSD_PROCESS_ACCT=y
9CONFIG_IRQ_DOMAIN_DEBUG=y 7CONFIG_IRQ_DOMAIN_DEBUG=y
10CONFIG_NO_HZ=y 8CONFIG_NO_HZ=y
11CONFIG_HIGH_RES_TIMERS=y 9CONFIG_HIGH_RES_TIMERS=y
10CONFIG_BSD_PROCESS_ACCT=y
12CONFIG_IKCONFIG=y 11CONFIG_IKCONFIG=y
13CONFIG_IKCONFIG_PROC=y 12CONFIG_IKCONFIG_PROC=y
14CONFIG_LOG_BUF_SHIFT=14 13CONFIG_LOG_BUF_SHIFT=14
@@ -22,10 +21,13 @@ CONFIG_MODVERSIONS=y
22# CONFIG_BLK_DEV_BSG is not set 21# CONFIG_BLK_DEV_BSG is not set
23CONFIG_PARTITION_ADVANCED=y 22CONFIG_PARTITION_ADVANCED=y
24CONFIG_MAC_PARTITION=y 23CONFIG_MAC_PARTITION=y
24CONFIG_B4_QDS=y
25CONFIG_P5020_DS=y 25CONFIG_P5020_DS=y
26CONFIG_P5040_DS=y 26CONFIG_P5040_DS=y
27CONFIG_T4240_QDS=y
27# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set 28# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
28CONFIG_BINFMT_MISC=m 29CONFIG_BINFMT_MISC=m
30CONFIG_FSL_IFC=y
29CONFIG_PCIEPORTBUS=y 31CONFIG_PCIEPORTBUS=y
30CONFIG_PCI_MSI=y 32CONFIG_PCI_MSI=y
31CONFIG_RAPIDIO=y 33CONFIG_RAPIDIO=y
@@ -58,16 +60,33 @@ CONFIG_IP_SCTP=m
58CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 60CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
59CONFIG_DEVTMPFS=y 61CONFIG_DEVTMPFS=y
60CONFIG_MTD=y 62CONFIG_MTD=y
63CONFIG_MTD_PARTITIONS=y
64CONFIG_MTD_OF_PARTS=y
61CONFIG_MTD_CMDLINE_PARTS=y 65CONFIG_MTD_CMDLINE_PARTS=y
62CONFIG_MTD_CHAR=y 66CONFIG_MTD_CHAR=y
67CONFIG_MTD_BLKDEVS=y
63CONFIG_MTD_BLOCK=y 68CONFIG_MTD_BLOCK=y
69CONFIG_FTL=y
64CONFIG_MTD_CFI=y 70CONFIG_MTD_CFI=y
71CONFIG_MTD_GEN_PROBE=y
72CONFIG_MTD_MAP_BANK_WIDTH_1=y
73CONFIG_MTD_MAP_BANK_WIDTH_2=y
74CONFIG_MTD_MAP_BANK_WIDTH_4=y
75CONFIG_MTD_CFI_I1=y
76CONFIG_MTD_CFI_I2=y
77CONFIG_MTD_CFI_INTELEXT=y
65CONFIG_MTD_CFI_AMDSTD=y 78CONFIG_MTD_CFI_AMDSTD=y
66CONFIG_MTD_PHYSMAP_OF=y 79CONFIG_MTD_PHYSMAP_OF=y
67CONFIG_MTD_M25P80=y 80CONFIG_MTD_M25P80=y
81CONFIG_MTD_CFI_UTIL=y
82CONFIG_MTD_NAND_ECC=y
68CONFIG_MTD_NAND=y 83CONFIG_MTD_NAND=y
84CONFIG_MTD_NAND_IDS=y
69CONFIG_MTD_NAND_FSL_ELBC=y 85CONFIG_MTD_NAND_FSL_ELBC=y
70CONFIG_MTD_NAND_FSL_IFC=y 86CONFIG_MTD_NAND_FSL_IFC=y
87CONFIG_MTD_UBI=y
88CONFIG_MTD_UBI_WL_THRESHOLD=4096
89CONFIG_MTD_UBI_BEB_RESERVE=1
71CONFIG_PROC_DEVICETREE=y 90CONFIG_PROC_DEVICETREE=y
72CONFIG_BLK_DEV_LOOP=y 91CONFIG_BLK_DEV_LOOP=y
73CONFIG_BLK_DEV_RAM=y 92CONFIG_BLK_DEV_RAM=y
@@ -78,6 +97,7 @@ CONFIG_SATA_FSL=y
78CONFIG_SATA_SIL24=y 97CONFIG_SATA_SIL24=y
79CONFIG_NETDEVICES=y 98CONFIG_NETDEVICES=y
80CONFIG_DUMMY=y 99CONFIG_DUMMY=y
100CONFIG_E1000E=y
81CONFIG_INPUT_FF_MEMLESS=m 101CONFIG_INPUT_FF_MEMLESS=m
82# CONFIG_INPUT_MOUSEDEV is not set 102# CONFIG_INPUT_MOUSEDEV is not set
83# CONFIG_INPUT_KEYBOARD is not set 103# CONFIG_INPUT_KEYBOARD is not set
@@ -121,7 +141,16 @@ CONFIG_NTFS_FS=y
121CONFIG_PROC_KCORE=y 141CONFIG_PROC_KCORE=y
122CONFIG_TMPFS=y 142CONFIG_TMPFS=y
123CONFIG_HUGETLBFS=y 143CONFIG_HUGETLBFS=y
124# CONFIG_MISC_FILESYSTEMS is not set 144CONFIG_MISC_FILESYSTEMS=y
145CONFIG_JFFS2_FS=y
146CONFIG_JFFS2_FS_DEBUG=1
147CONFIG_JFFS2_FS_WRITEBUFFER=y
148CONFIG_JFFS2_ZLIB=y
149CONFIG_JFFS2_RTIME=y
150CONFIG_UBIFS_FS=y
151CONFIG_UBIFS_FS_XATTR=y
152CONFIG_UBIFS_FS_LZO=y
153CONFIG_UBIFS_FS_ZLIB=y
125CONFIG_NFS_FS=y 154CONFIG_NFS_FS=y
126CONFIG_NFS_V4=y 155CONFIG_NFS_V4=y
127CONFIG_ROOT_NFS=y 156CONFIG_ROOT_NFS=y
@@ -129,6 +158,12 @@ CONFIG_NFSD=m
129CONFIG_NLS_ISO8859_1=y 158CONFIG_NLS_ISO8859_1=y
130CONFIG_NLS_UTF8=m 159CONFIG_NLS_UTF8=m
131CONFIG_CRC_T10DIF=y 160CONFIG_CRC_T10DIF=y
161CONFIG_CRC16=y
162CONFIG_ZLIB_DEFLATE=y
163CONFIG_LZO_COMPRESS=y
164CONFIG_LZO_DECOMPRESS=y
165CONFIG_CRYPTO_DEFLATE=y
166CONFIG_CRYPTO_LZO=y
132CONFIG_FRAME_WARN=1024 167CONFIG_FRAME_WARN=1024
133CONFIG_MAGIC_SYSRQ=y 168CONFIG_MAGIC_SYSRQ=y
134CONFIG_DEBUG_FS=y 169CONFIG_DEBUG_FS=y
@@ -140,6 +175,5 @@ CONFIG_CRYPTO_PCBC=m
140CONFIG_CRYPTO_MD4=y 175CONFIG_CRYPTO_MD4=y
141CONFIG_CRYPTO_SHA256=y 176CONFIG_CRYPTO_SHA256=y
142CONFIG_CRYPTO_SHA512=y 177CONFIG_CRYPTO_SHA512=y
143CONFIG_CRYPTO_AES=y
144# CONFIG_CRYPTO_ANSI_CPRNG is not set 178# CONFIG_CRYPTO_ANSI_CPRNG is not set
145CONFIG_CRYPTO_DEV_FSL_CAAM=y 179CONFIG_CRYPTO_DEV_FSL_CAAM=y
diff --git a/arch/powerpc/configs/mpc85xx_defconfig b/arch/powerpc/configs/mpc85xx_defconfig
index cf815e847cdc..5a58882e351e 100644
--- a/arch/powerpc/configs/mpc85xx_defconfig
+++ b/arch/powerpc/configs/mpc85xx_defconfig
@@ -1,13 +1,12 @@
1CONFIG_PPC_85xx=y 1CONFIG_PPC_85xx=y
2CONFIG_PHYS_64BIT=y 2CONFIG_PHYS_64BIT=y
3CONFIG_EXPERIMENTAL=y
4CONFIG_SYSVIPC=y 3CONFIG_SYSVIPC=y
5CONFIG_POSIX_MQUEUE=y 4CONFIG_POSIX_MQUEUE=y
6CONFIG_BSD_PROCESS_ACCT=y
7CONFIG_AUDIT=y 5CONFIG_AUDIT=y
8CONFIG_IRQ_DOMAIN_DEBUG=y 6CONFIG_IRQ_DOMAIN_DEBUG=y
9CONFIG_NO_HZ=y 7CONFIG_NO_HZ=y
10CONFIG_HIGH_RES_TIMERS=y 8CONFIG_HIGH_RES_TIMERS=y
9CONFIG_BSD_PROCESS_ACCT=y
11CONFIG_IKCONFIG=y 10CONFIG_IKCONFIG=y
12CONFIG_IKCONFIG_PROC=y 11CONFIG_IKCONFIG_PROC=y
13CONFIG_LOG_BUF_SHIFT=14 12CONFIG_LOG_BUF_SHIFT=14
@@ -48,6 +47,7 @@ CONFIG_HIGHMEM=y
48CONFIG_BINFMT_MISC=m 47CONFIG_BINFMT_MISC=m
49CONFIG_MATH_EMULATION=y 48CONFIG_MATH_EMULATION=y
50CONFIG_FORCE_MAX_ZONEORDER=12 49CONFIG_FORCE_MAX_ZONEORDER=12
50CONFIG_FSL_IFC=y
51CONFIG_PCI=y 51CONFIG_PCI=y
52CONFIG_PCI_MSI=y 52CONFIG_PCI_MSI=y
53CONFIG_RAPIDIO=y 53CONFIG_RAPIDIO=y
@@ -79,18 +79,33 @@ CONFIG_IP_SCTP=m
79CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 79CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
80CONFIG_DEVTMPFS=y 80CONFIG_DEVTMPFS=y
81CONFIG_MTD=y 81CONFIG_MTD=y
82CONFIG_MTD_PARTITIONS=y
83CONFIG_MTD_OF_PARTS=y
82CONFIG_MTD_CMDLINE_PARTS=y 84CONFIG_MTD_CMDLINE_PARTS=y
83CONFIG_MTD_CHAR=y 85CONFIG_MTD_CHAR=y
86CONFIG_MTD_BLKDEVS=y
84CONFIG_MTD_BLOCK=y 87CONFIG_MTD_BLOCK=y
85CONFIG_FTL=y 88CONFIG_FTL=y
86CONFIG_MTD_CFI=y 89CONFIG_MTD_CFI=y
90CONFIG_MTD_GEN_PROBE=y
91CONFIG_MTD_MAP_BANK_WIDTH_1=y
92CONFIG_MTD_MAP_BANK_WIDTH_2=y
93CONFIG_MTD_MAP_BANK_WIDTH_4=y
94CONFIG_MTD_CFI_I1=y
95CONFIG_MTD_CFI_I2=y
87CONFIG_MTD_CFI_INTELEXT=y 96CONFIG_MTD_CFI_INTELEXT=y
88CONFIG_MTD_CFI_AMDSTD=y 97CONFIG_MTD_CFI_AMDSTD=y
89CONFIG_MTD_PHYSMAP_OF=y 98CONFIG_MTD_PHYSMAP_OF=y
90CONFIG_MTD_M25P80=y 99CONFIG_MTD_M25P80=y
100CONFIG_MTD_CFI_UTIL=y
101CONFIG_MTD_NAND_ECC=y
91CONFIG_MTD_NAND=y 102CONFIG_MTD_NAND=y
103CONFIG_MTD_NAND_IDS=y
92CONFIG_MTD_NAND_FSL_ELBC=y 104CONFIG_MTD_NAND_FSL_ELBC=y
93CONFIG_MTD_NAND_FSL_IFC=y 105CONFIG_MTD_NAND_FSL_IFC=y
106CONFIG_MTD_UBI=y
107CONFIG_MTD_UBI_WL_THRESHOLD=4096
108CONFIG_MTD_UBI_BEB_RESERVE=1
94CONFIG_PROC_DEVICETREE=y 109CONFIG_PROC_DEVICETREE=y
95CONFIG_BLK_DEV_LOOP=y 110CONFIG_BLK_DEV_LOOP=y
96CONFIG_BLK_DEV_NBD=y 111CONFIG_BLK_DEV_NBD=y
@@ -106,6 +121,7 @@ CONFIG_SCSI_LOGGING=y
106CONFIG_ATA=y 121CONFIG_ATA=y
107CONFIG_SATA_AHCI=y 122CONFIG_SATA_AHCI=y
108CONFIG_SATA_FSL=y 123CONFIG_SATA_FSL=y
124CONFIG_SATA_SIL24=y
109CONFIG_PATA_ALI=y 125CONFIG_PATA_ALI=y
110CONFIG_PATA_VIA=y 126CONFIG_PATA_VIA=y
111CONFIG_NETDEVICES=y 127CONFIG_NETDEVICES=y
@@ -113,6 +129,9 @@ CONFIG_DUMMY=y
113CONFIG_FS_ENET=y 129CONFIG_FS_ENET=y
114CONFIG_UCC_GETH=y 130CONFIG_UCC_GETH=y
115CONFIG_GIANFAR=y 131CONFIG_GIANFAR=y
132CONFIG_E1000=y
133CONFIG_E1000E=y
134CONFIG_IGB=y
116CONFIG_MARVELL_PHY=y 135CONFIG_MARVELL_PHY=y
117CONFIG_DAVICOM_PHY=y 136CONFIG_DAVICOM_PHY=y
118CONFIG_CICADA_PHY=y 137CONFIG_CICADA_PHY=y
@@ -132,7 +151,6 @@ CONFIG_SERIAL_8250_DETECT_IRQ=y
132CONFIG_SERIAL_8250_RSA=y 151CONFIG_SERIAL_8250_RSA=y
133CONFIG_SERIAL_QE=m 152CONFIG_SERIAL_QE=m
134CONFIG_NVRAM=y 153CONFIG_NVRAM=y
135CONFIG_I2C=y
136CONFIG_I2C_CHARDEV=y 154CONFIG_I2C_CHARDEV=y
137CONFIG_I2C_CPM=m 155CONFIG_I2C_CPM=m
138CONFIG_I2C_MPC=y 156CONFIG_I2C_MPC=y
@@ -206,6 +224,15 @@ CONFIG_NTFS_FS=y
206CONFIG_PROC_KCORE=y 224CONFIG_PROC_KCORE=y
207CONFIG_TMPFS=y 225CONFIG_TMPFS=y
208CONFIG_HUGETLBFS=y 226CONFIG_HUGETLBFS=y
227CONFIG_JFFS2_FS=y
228CONFIG_JFFS2_FS_DEBUG=1
229CONFIG_JFFS2_FS_WRITEBUFFER=y
230CONFIG_JFFS2_ZLIB=y
231CONFIG_JFFS2_RTIME=y
232CONFIG_UBIFS_FS=y
233CONFIG_UBIFS_FS_XATTR=y
234CONFIG_UBIFS_FS_LZO=y
235CONFIG_UBIFS_FS_ZLIB=y
209CONFIG_ADFS_FS=m 236CONFIG_ADFS_FS=m
210CONFIG_AFFS_FS=m 237CONFIG_AFFS_FS=m
211CONFIG_HFS_FS=m 238CONFIG_HFS_FS=m
@@ -224,13 +251,18 @@ CONFIG_NFS_V4=y
224CONFIG_ROOT_NFS=y 251CONFIG_ROOT_NFS=y
225CONFIG_NFSD=y 252CONFIG_NFSD=y
226CONFIG_CRC_T10DIF=y 253CONFIG_CRC_T10DIF=y
254CONFIG_CRC16=y
255CONFIG_ZLIB_DEFLATE=y
256CONFIG_LZO_COMPRESS=y
257CONFIG_LZO_DECOMPRESS=y
258CONFIG_CRYPTO_DEFLATE=y
259CONFIG_CRYPTO_LZO=y
227CONFIG_DEBUG_FS=y 260CONFIG_DEBUG_FS=y
228CONFIG_DETECT_HUNG_TASK=y 261CONFIG_DETECT_HUNG_TASK=y
229CONFIG_DEBUG_INFO=y 262CONFIG_DEBUG_INFO=y
230CONFIG_CRYPTO_PCBC=m 263CONFIG_CRYPTO_PCBC=m
231CONFIG_CRYPTO_SHA256=y 264CONFIG_CRYPTO_SHA256=y
232CONFIG_CRYPTO_SHA512=y 265CONFIG_CRYPTO_SHA512=y
233CONFIG_CRYPTO_AES=y
234# CONFIG_CRYPTO_ANSI_CPRNG is not set 266# CONFIG_CRYPTO_ANSI_CPRNG is not set
235CONFIG_CRYPTO_DEV_FSL_CAAM=y 267CONFIG_CRYPTO_DEV_FSL_CAAM=y
236CONFIG_CRYPTO_DEV_TALITOS=y 268CONFIG_CRYPTO_DEV_TALITOS=y
diff --git a/arch/powerpc/configs/mpc85xx_smp_defconfig b/arch/powerpc/configs/mpc85xx_smp_defconfig
index 8d00ea5b8a9f..165e6b32baef 100644
--- a/arch/powerpc/configs/mpc85xx_smp_defconfig
+++ b/arch/powerpc/configs/mpc85xx_smp_defconfig
@@ -50,6 +50,7 @@ CONFIG_HIGHMEM=y
50CONFIG_BINFMT_MISC=m 50CONFIG_BINFMT_MISC=m
51CONFIG_MATH_EMULATION=y 51CONFIG_MATH_EMULATION=y
52CONFIG_FORCE_MAX_ZONEORDER=12 52CONFIG_FORCE_MAX_ZONEORDER=12
53CONFIG_FSL_IFC=y
53CONFIG_PCI=y 54CONFIG_PCI=y
54CONFIG_PCI_MSI=y 55CONFIG_PCI_MSI=y
55CONFIG_RAPIDIO=y 56CONFIG_RAPIDIO=y
@@ -81,18 +82,33 @@ CONFIG_IP_SCTP=m
81CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" 82CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
82CONFIG_DEVTMPFS=y 83CONFIG_DEVTMPFS=y
83CONFIG_MTD=y 84CONFIG_MTD=y
85CONFIG_MTD_PARTITIONS=y
86CONFIG_MTD_OF_PARTS=y
84CONFIG_MTD_CMDLINE_PARTS=y 87CONFIG_MTD_CMDLINE_PARTS=y
85CONFIG_MTD_CHAR=y 88CONFIG_MTD_CHAR=y
89CONFIG_MTD_BLKDEVS=y
86CONFIG_MTD_BLOCK=y 90CONFIG_MTD_BLOCK=y
87CONFIG_FTL=y 91CONFIG_FTL=y
88CONFIG_MTD_CFI=y 92CONFIG_MTD_CFI=y
93CONFIG_MTD_GEN_PROBE=y
94CONFIG_MTD_MAP_BANK_WIDTH_1=y
95CONFIG_MTD_MAP_BANK_WIDTH_2=y
96CONFIG_MTD_MAP_BANK_WIDTH_4=y
97CONFIG_MTD_CFI_I1=y
98CONFIG_MTD_CFI_I2=y
89CONFIG_MTD_CFI_INTELEXT=y 99CONFIG_MTD_CFI_INTELEXT=y
90CONFIG_MTD_CFI_AMDSTD=y 100CONFIG_MTD_CFI_AMDSTD=y
91CONFIG_MTD_PHYSMAP_OF=y 101CONFIG_MTD_PHYSMAP_OF=y
92CONFIG_MTD_M25P80=y 102CONFIG_MTD_M25P80=y
103CONFIG_MTD_CFI_UTIL=y
104CONFIG_MTD_NAND_ECC=y
93CONFIG_MTD_NAND=y 105CONFIG_MTD_NAND=y
106CONFIG_MTD_NAND_IDS=y
94CONFIG_MTD_NAND_FSL_ELBC=y 107CONFIG_MTD_NAND_FSL_ELBC=y
95CONFIG_MTD_NAND_FSL_IFC=y 108CONFIG_MTD_NAND_FSL_IFC=y
109CONFIG_MTD_UBI=y
110CONFIG_MTD_UBI_WL_THRESHOLD=4096
111CONFIG_MTD_UBI_BEB_RESERVE=1
96CONFIG_PROC_DEVICETREE=y 112CONFIG_PROC_DEVICETREE=y
97CONFIG_BLK_DEV_LOOP=y 113CONFIG_BLK_DEV_LOOP=y
98CONFIG_BLK_DEV_NBD=y 114CONFIG_BLK_DEV_NBD=y
@@ -108,6 +124,7 @@ CONFIG_SCSI_LOGGING=y
108CONFIG_ATA=y 124CONFIG_ATA=y
109CONFIG_SATA_AHCI=y 125CONFIG_SATA_AHCI=y
110CONFIG_SATA_FSL=y 126CONFIG_SATA_FSL=y
127CONFIG_SATA_SIL24=y
111CONFIG_PATA_ALI=y 128CONFIG_PATA_ALI=y
112CONFIG_NETDEVICES=y 129CONFIG_NETDEVICES=y
113CONFIG_DUMMY=y 130CONFIG_DUMMY=y
@@ -207,6 +224,15 @@ CONFIG_NTFS_FS=y
207CONFIG_PROC_KCORE=y 224CONFIG_PROC_KCORE=y
208CONFIG_TMPFS=y 225CONFIG_TMPFS=y
209CONFIG_HUGETLBFS=y 226CONFIG_HUGETLBFS=y
227CONFIG_JFFS2_FS=y
228CONFIG_JFFS2_FS_DEBUG=1
229CONFIG_JFFS2_FS_WRITEBUFFER=y
230CONFIG_JFFS2_ZLIB=y
231CONFIG_JFFS2_RTIME=y
232CONFIG_UBIFS_FS=y
233CONFIG_UBIFS_FS_XATTR=y
234CONFIG_UBIFS_FS_LZO=y
235CONFIG_UBIFS_FS_ZLIB=y
210CONFIG_ADFS_FS=m 236CONFIG_ADFS_FS=m
211CONFIG_AFFS_FS=m 237CONFIG_AFFS_FS=m
212CONFIG_HFS_FS=m 238CONFIG_HFS_FS=m
@@ -225,6 +251,12 @@ CONFIG_NFS_V4=y
225CONFIG_ROOT_NFS=y 251CONFIG_ROOT_NFS=y
226CONFIG_NFSD=y 252CONFIG_NFSD=y
227CONFIG_CRC_T10DIF=y 253CONFIG_CRC_T10DIF=y
254CONFIG_CRC16=y
255CONFIG_ZLIB_DEFLATE=y
256CONFIG_LZO_COMPRESS=y
257CONFIG_LZO_DECOMPRESS=y
258CONFIG_CRYPTO_DEFLATE=y
259CONFIG_CRYPTO_LZO=y
228CONFIG_DEBUG_FS=y 260CONFIG_DEBUG_FS=y
229CONFIG_DETECT_HUNG_TASK=y 261CONFIG_DETECT_HUNG_TASK=y
230CONFIG_DEBUG_INFO=y 262CONFIG_DEBUG_INFO=y
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h
index ccadad6db4e4..284e50bc7b68 100644
--- a/arch/powerpc/include/asm/cputable.h
+++ b/arch/powerpc/include/asm/cputable.h
@@ -375,7 +375,7 @@ extern const char *powerpc_base_platform;
375#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \ 375#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
376 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ 376 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
377 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ 377 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
378 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) 378 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP)
379#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) 379#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
380 380
381/* 64-bit CPUs */ 381/* 64-bit CPUs */
diff --git a/arch/powerpc/include/asm/kvm_asm.h b/arch/powerpc/include/asm/kvm_asm.h
index aabcdba8f6b0..b9dd382cb349 100644
--- a/arch/powerpc/include/asm/kvm_asm.h
+++ b/arch/powerpc/include/asm/kvm_asm.h
@@ -67,6 +67,10 @@
67#define BOOKE_INTERRUPT_HV_SYSCALL 40 67#define BOOKE_INTERRUPT_HV_SYSCALL 40
68#define BOOKE_INTERRUPT_HV_PRIV 41 68#define BOOKE_INTERRUPT_HV_PRIV 41
69 69
70/* altivec */
71#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL 42
72#define BOOKE_INTERRUPT_ALTIVEC_ASSIST 43
73
70/* book3s */ 74/* book3s */
71 75
72#define BOOK3S_INTERRUPT_SYSTEM_RESET 0x100 76#define BOOK3S_INTERRUPT_SYSTEM_RESET 0x100
diff --git a/arch/powerpc/include/asm/pci-bridge.h b/arch/powerpc/include/asm/pci-bridge.h
index 025a130729bc..ffbc5fd549ac 100644
--- a/arch/powerpc/include/asm/pci-bridge.h
+++ b/arch/powerpc/include/asm/pci-bridge.h
@@ -70,6 +70,8 @@ struct pci_controller {
70 * BIG_ENDIAN - cfg_addr is a big endian register 70 * BIG_ENDIAN - cfg_addr is a big endian register
71 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on 71 * BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
72 * the PLB4. Effectively disable MRM commands by setting this. 72 * the PLB4. Effectively disable MRM commands by setting this.
73 * FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
74 * link status is in a RC PCIe cfg register (vs being a SoC register)
73 */ 75 */
74#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001 76#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
75#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002 77#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
@@ -77,6 +79,7 @@ struct pci_controller {
77#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008 79#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
78#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010 80#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
79#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020 81#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
82#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
80 u32 indirect_type; 83 u32 indirect_type;
81 /* Currently, we limit ourselves to 1 IO range and 3 mem 84 /* Currently, we limit ourselves to 1 IO range and 3 mem
82 * ranges since the common pci_bus structure can't handle more 85 * ranges since the common pci_bus structure can't handle more
@@ -90,9 +93,9 @@ struct pci_controller {
90 93
91#ifdef CONFIG_PPC64 94#ifdef CONFIG_PPC64
92 unsigned long buid; 95 unsigned long buid;
96#endif /* CONFIG_PPC64 */
93 97
94 void *private_data; 98 void *private_data;
95#endif /* CONFIG_PPC64 */
96}; 99};
97 100
98/* These are used for config access before all the PCI probing 101/* These are used for config access before all the PCI probing
@@ -117,6 +120,12 @@ extern void setup_indirect_pci(struct pci_controller* hose,
117 resource_size_t cfg_addr, 120 resource_size_t cfg_addr,
118 resource_size_t cfg_data, u32 flags); 121 resource_size_t cfg_data, u32 flags);
119 122
123extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
124 int offset, int len, u32 *val);
125
126extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
127 int offset, int len, u32 val);
128
120static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus) 129static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
121{ 130{
122 return bus->sysdata; 131 return bus->sysdata;
diff --git a/arch/powerpc/kernel/cpu_setup_fsl_booke.S b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
index dcd881937f7a..0b9af015bedc 100644
--- a/arch/powerpc/kernel/cpu_setup_fsl_booke.S
+++ b/arch/powerpc/kernel/cpu_setup_fsl_booke.S
@@ -53,6 +53,15 @@ _GLOBAL(__e500_dcache_setup)
53 isync 53 isync
54 blr 54 blr
55 55
56_GLOBAL(__setup_cpu_e6500)
57 mflr r6
58#ifdef CONFIG_PPC64
59 bl .setup_altivec_ivors
60#endif
61 bl __setup_cpu_e5500
62 mtlr r6
63 blr
64
56#ifdef CONFIG_PPC32 65#ifdef CONFIG_PPC32
57_GLOBAL(__setup_cpu_e200) 66_GLOBAL(__setup_cpu_e200)
58 /* enable dedicated debug exception handling resources (Debug APU) */ 67 /* enable dedicated debug exception handling resources (Debug APU) */
@@ -107,6 +116,13 @@ _GLOBAL(__setup_cpu_e5500)
107#endif 116#endif
108 117
109#ifdef CONFIG_PPC_BOOK3E_64 118#ifdef CONFIG_PPC_BOOK3E_64
119_GLOBAL(__restore_cpu_e6500)
120 mflr r5
121 bl .setup_altivec_ivors
122 bl __restore_cpu_e5500
123 mtlr r5
124 blr
125
110_GLOBAL(__restore_cpu_e5500) 126_GLOBAL(__restore_cpu_e5500)
111 mflr r4 127 mflr r4
112 bl __e500_icache_setup 128 bl __e500_icache_setup
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c
index 19599ef352bc..ae9f433daabf 100644
--- a/arch/powerpc/kernel/cputable.c
+++ b/arch/powerpc/kernel/cputable.c
@@ -74,7 +74,9 @@ extern void __restore_cpu_a2(void);
74#endif /* CONFIG_PPC64 */ 74#endif /* CONFIG_PPC64 */
75#if defined(CONFIG_E500) 75#if defined(CONFIG_E500)
76extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec); 76extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
77extern void __setup_cpu_e6500(unsigned long offset, struct cpu_spec* spec);
77extern void __restore_cpu_e5500(void); 78extern void __restore_cpu_e5500(void);
79extern void __restore_cpu_e6500(void);
78#endif /* CONFIG_E500 */ 80#endif /* CONFIG_E500 */
79 81
80/* This table only contains "desktop" CPUs, it need to be filled with embedded 82/* This table only contains "desktop" CPUs, it need to be filled with embedded
@@ -2065,7 +2067,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
2065 .pvr_value = 0x80400000, 2067 .pvr_value = 0x80400000,
2066 .cpu_name = "e6500", 2068 .cpu_name = "e6500",
2067 .cpu_features = CPU_FTRS_E6500, 2069 .cpu_features = CPU_FTRS_E6500,
2068 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, 2070 .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU |
2071 PPC_FEATURE_HAS_ALTIVEC_COMP,
2069 .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS | 2072 .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
2070 MMU_FTR_USE_TLBILX, 2073 MMU_FTR_USE_TLBILX,
2071 .icache_bsize = 64, 2074 .icache_bsize = 64,
@@ -2073,9 +2076,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
2073 .num_pmcs = 4, 2076 .num_pmcs = 4,
2074 .oprofile_cpu_type = "ppc/e6500", 2077 .oprofile_cpu_type = "ppc/e6500",
2075 .oprofile_type = PPC_OPROFILE_FSL_EMB, 2078 .oprofile_type = PPC_OPROFILE_FSL_EMB,
2076 .cpu_setup = __setup_cpu_e5500, 2079 .cpu_setup = __setup_cpu_e6500,
2077#ifndef CONFIG_PPC32 2080#ifndef CONFIG_PPC32
2078 .cpu_restore = __restore_cpu_e5500, 2081 .cpu_restore = __restore_cpu_e6500,
2079#endif 2082#endif
2080 .machine_check = machine_check_e500mc, 2083 .machine_check = machine_check_e500mc,
2081 .platform = "ppce6500", 2084 .platform = "ppce6500",
diff --git a/arch/powerpc/kernel/epapr_hcalls.S b/arch/powerpc/kernel/epapr_hcalls.S
index 62c0dc237826..9f1ebf7338f1 100644
--- a/arch/powerpc/kernel/epapr_hcalls.S
+++ b/arch/powerpc/kernel/epapr_hcalls.S
@@ -17,6 +17,7 @@
17#include <asm/asm-compat.h> 17#include <asm/asm-compat.h>
18#include <asm/asm-offsets.h> 18#include <asm/asm-offsets.h>
19 19
20#ifndef CONFIG_PPC64
20/* epapr_ev_idle() was derived from e500_idle() */ 21/* epapr_ev_idle() was derived from e500_idle() */
21_GLOBAL(epapr_ev_idle) 22_GLOBAL(epapr_ev_idle)
22 CURRENT_THREAD_INFO(r3, r1) 23 CURRENT_THREAD_INFO(r3, r1)
@@ -42,6 +43,7 @@ epapr_ev_idle_start:
42 * _TLF_NAPPING. 43 * _TLF_NAPPING.
43 */ 44 */
44 b idle_loop 45 b idle_loop
46#endif
45 47
46/* Hypercall entry point. Will be patched with device tree instructions. */ 48/* Hypercall entry point. Will be patched with device tree instructions. */
47.global epapr_hypercall_start 49.global epapr_hypercall_start
diff --git a/arch/powerpc/kernel/exceptions-64e.S b/arch/powerpc/kernel/exceptions-64e.S
index ae54553eacd9..42a756eec9ff 100644
--- a/arch/powerpc/kernel/exceptions-64e.S
+++ b/arch/powerpc/kernel/exceptions-64e.S
@@ -299,6 +299,8 @@ interrupt_base_book3e: /* fake trap */
299 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */ 299 EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
300 EXCEPTION_STUB(0x1c0, data_tlb_miss) 300 EXCEPTION_STUB(0x1c0, data_tlb_miss)
301 EXCEPTION_STUB(0x1e0, instruction_tlb_miss) 301 EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
302 EXCEPTION_STUB(0x200, altivec_unavailable) /* 0x0f20 */
303 EXCEPTION_STUB(0x220, altivec_assist) /* 0x1700 */
302 EXCEPTION_STUB(0x260, perfmon) 304 EXCEPTION_STUB(0x260, perfmon)
303 EXCEPTION_STUB(0x280, doorbell) 305 EXCEPTION_STUB(0x280, doorbell)
304 EXCEPTION_STUB(0x2a0, doorbell_crit) 306 EXCEPTION_STUB(0x2a0, doorbell_crit)
@@ -395,6 +397,45 @@ interrupt_end_book3e:
395 bl .kernel_fp_unavailable_exception 397 bl .kernel_fp_unavailable_exception
396 b .ret_from_except 398 b .ret_from_except
397 399
400/* Altivec Unavailable Interrupt */
401 START_EXCEPTION(altivec_unavailable);
402 NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL,
403 PROLOG_ADDITION_NONE)
404 /* we can probably do a shorter exception entry for that one... */
405 EXCEPTION_COMMON(0x200, PACA_EXGEN, INTS_KEEP)
406#ifdef CONFIG_ALTIVEC
407BEGIN_FTR_SECTION
408 ld r12,_MSR(r1)
409 andi. r0,r12,MSR_PR;
410 beq- 1f
411 bl .load_up_altivec
412 b fast_exception_return
4131:
414END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
415#endif
416 INTS_DISABLE
417 bl .save_nvgprs
418 addi r3,r1,STACK_FRAME_OVERHEAD
419 bl .altivec_unavailable_exception
420 b .ret_from_except
421
422/* AltiVec Assist */
423 START_EXCEPTION(altivec_assist);
424 NORMAL_EXCEPTION_PROLOG(0x220, BOOKE_INTERRUPT_ALTIVEC_ASSIST,
425 PROLOG_ADDITION_NONE)
426 EXCEPTION_COMMON(0x220, PACA_EXGEN, INTS_DISABLE)
427 bl .save_nvgprs
428 addi r3,r1,STACK_FRAME_OVERHEAD
429#ifdef CONFIG_ALTIVEC
430BEGIN_FTR_SECTION
431 bl .altivec_assist_exception
432END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
433#else
434 bl .unknown_exception
435#endif
436 b .ret_from_except
437
438
398/* Decrementer Interrupt */ 439/* Decrementer Interrupt */
399 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER, 440 MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
400 decrementer, .timer_interrupt, ACK_DEC) 441 decrementer, .timer_interrupt, ACK_DEC)
@@ -807,6 +848,7 @@ fast_exception_return:
807BAD_STACK_TRAMPOLINE(0x000) 848BAD_STACK_TRAMPOLINE(0x000)
808BAD_STACK_TRAMPOLINE(0x100) 849BAD_STACK_TRAMPOLINE(0x100)
809BAD_STACK_TRAMPOLINE(0x200) 850BAD_STACK_TRAMPOLINE(0x200)
851BAD_STACK_TRAMPOLINE(0x220)
810BAD_STACK_TRAMPOLINE(0x260) 852BAD_STACK_TRAMPOLINE(0x260)
811BAD_STACK_TRAMPOLINE(0x280) 853BAD_STACK_TRAMPOLINE(0x280)
812BAD_STACK_TRAMPOLINE(0x2a0) 854BAD_STACK_TRAMPOLINE(0x2a0)
@@ -1350,6 +1392,11 @@ _GLOBAL(__setup_base_ivors)
1350 1392
1351 blr 1393 blr
1352 1394
1395_GLOBAL(setup_altivec_ivors)
1396 SET_IVOR(32, 0x200) /* AltiVec Unavailable */
1397 SET_IVOR(33, 0x220) /* AltiVec Assist */
1398 blr
1399
1353_GLOBAL(setup_perfmon_ivor) 1400_GLOBAL(setup_perfmon_ivor)
1354 SET_IVOR(35, 0x260) /* Performance Monitor */ 1401 SET_IVOR(35, 0x260) /* Performance Monitor */
1355 blr 1402 blr
diff --git a/arch/powerpc/kernel/idle_book3e.S b/arch/powerpc/kernel/idle_book3e.S
index 4c7cb4008585..bfb73cc209ce 100644
--- a/arch/powerpc/kernel/idle_book3e.S
+++ b/arch/powerpc/kernel/idle_book3e.S
@@ -16,11 +16,13 @@
16#include <asm/ppc-opcode.h> 16#include <asm/ppc-opcode.h>
17#include <asm/processor.h> 17#include <asm/processor.h>
18#include <asm/thread_info.h> 18#include <asm/thread_info.h>
19#include <asm/epapr_hcalls.h>
19 20
20/* 64-bit version only for now */ 21/* 64-bit version only for now */
21#ifdef CONFIG_PPC64 22#ifdef CONFIG_PPC64
22 23
23_GLOBAL(book3e_idle) 24.macro BOOK3E_IDLE name loop
25_GLOBAL(\name)
24 /* Save LR for later */ 26 /* Save LR for later */
25 mflr r0 27 mflr r0
26 std r0,16(r1) 28 std r0,16(r1)
@@ -67,7 +69,33 @@ _GLOBAL(book3e_idle)
67 69
68 /* We can now re-enable hard interrupts and go to sleep */ 70 /* We can now re-enable hard interrupts and go to sleep */
69 wrteei 1 71 wrteei 1
701: PPC_WAIT(0) 72 \loop
73
74.endm
75
76.macro BOOK3E_IDLE_LOOP
771:
78 PPC_WAIT(0)
71 b 1b 79 b 1b
80.endm
81
82/* epapr_ev_idle_start below is patched with the proper hcall
83 opcodes during kernel initialization */
84.macro EPAPR_EV_IDLE_LOOP
85idle_loop:
86 LOAD_REG_IMMEDIATE(r11, EV_HCALL_TOKEN(EV_IDLE))
87
88.global epapr_ev_idle_start
89epapr_ev_idle_start:
90 li r3, -1
91 nop
92 nop
93 nop
94 b idle_loop
95.endm
96
97BOOK3E_IDLE epapr_ev_idle EPAPR_EV_IDLE_LOOP
98
99BOOK3E_IDLE book3e_idle BOOK3E_IDLE_LOOP
72 100
73#endif /* CONFIG_PPC64 */ 101#endif /* CONFIG_PPC64 */
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index df32a838dcfa..6888cad5103d 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -414,9 +414,9 @@ static void setup_page_sizes(void)
414 414
415#ifdef CONFIG_PPC_FSL_BOOK3E 415#ifdef CONFIG_PPC_FSL_BOOK3E
416 unsigned int mmucfg = mfspr(SPRN_MMUCFG); 416 unsigned int mmucfg = mfspr(SPRN_MMUCFG);
417 int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);
417 418
418 if (((mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) && 419 if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
419 (mmu_has_feature(MMU_FTR_TYPE_FSL_E))) {
420 unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG); 420 unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
421 unsigned int min_pg, max_pg; 421 unsigned int min_pg, max_pg;
422 422
@@ -442,6 +442,20 @@ static void setup_page_sizes(void)
442 442
443 goto no_indirect; 443 goto no_indirect;
444 } 444 }
445
446 if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
447 u32 tlb1ps = mfspr(SPRN_TLB1PS);
448
449 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
450 struct mmu_psize_def *def = &mmu_psize_defs[psize];
451
452 if (tlb1ps & (1U << (def->shift - 10))) {
453 def->flags |= MMU_PAGE_SIZE_DIRECT;
454 }
455 }
456
457 goto no_indirect;
458 }
445#endif 459#endif
446 460
447 tlb0cfg = mfspr(SPRN_TLB0CFG); 461 tlb0cfg = mfspr(SPRN_TLB0CFG);
diff --git a/arch/powerpc/platforms/85xx/Kconfig b/arch/powerpc/platforms/85xx/Kconfig
index a0dcd577fb0d..8f02b05f4c96 100644
--- a/arch/powerpc/platforms/85xx/Kconfig
+++ b/arch/powerpc/platforms/85xx/Kconfig
@@ -305,6 +305,40 @@ config PPC_QEMU_E500
305 unset based on the emulated CPU (or actual host CPU in the case 305 unset based on the emulated CPU (or actual host CPU in the case
306 of KVM). 306 of KVM).
307 307
308if PPC64
309
310config T4240_QDS
311 bool "Freescale T4240 QDS"
312 select DEFAULT_UIMAGE
313 select E500
314 select PPC_E500MC
315 select PHYS_64BIT
316 select SWIOTLB
317 select ARCH_REQUIRE_GPIOLIB
318 select GPIO_MPC8XXX
319 select HAS_RAPIDIO
320 select PPC_EPAPR_HV_PIC
321 help
322 This option enables support for the T4240 QDS board
323
324config B4_QDS
325 bool "Freescale B4 QDS"
326 select DEFAULT_UIMAGE
327 select E500
328 select PPC_E500MC
329 select PHYS_64BIT
330 select SWIOTLB
331 select GENERIC_GPIO
332 select ARCH_REQUIRE_GPIOLIB
333 select HAS_RAPIDIO
334 select PPC_EPAPR_HV_PIC
335 help
336 This option enables support for the B4 QDS board
337 The B4 application development system B4 QDS is a complete
338 debugging environment intended for engineers developing
339 applications for the B4.
340
341endif
308endif # FSL_SOC_BOOKE 342endif # FSL_SOC_BOOKE
309 343
310config TQM85xx 344config TQM85xx
diff --git a/arch/powerpc/platforms/85xx/Makefile b/arch/powerpc/platforms/85xx/Makefile
index 07d0dbb141c0..2eab37ea4a9d 100644
--- a/arch/powerpc/platforms/85xx/Makefile
+++ b/arch/powerpc/platforms/85xx/Makefile
@@ -22,6 +22,8 @@ obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
22obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o 22obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
23obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o 23obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
24obj-$(CONFIG_P5040_DS) += p5040_ds.o corenet_ds.o 24obj-$(CONFIG_P5040_DS) += p5040_ds.o corenet_ds.o
25obj-$(CONFIG_T4240_QDS) += t4240_qds.o corenet_ds.o
26obj-$(CONFIG_B4_QDS) += b4_qds.o corenet_ds.o
25obj-$(CONFIG_STX_GP3) += stx_gp3.o 27obj-$(CONFIG_STX_GP3) += stx_gp3.o
26obj-$(CONFIG_TQM85xx) += tqm85xx.o 28obj-$(CONFIG_TQM85xx) += tqm85xx.o
27obj-$(CONFIG_SBC8548) += sbc8548.o 29obj-$(CONFIG_SBC8548) += sbc8548.o
diff --git a/arch/powerpc/platforms/85xx/b4_qds.c b/arch/powerpc/platforms/85xx/b4_qds.c
new file mode 100644
index 000000000000..0c6702f8b88e
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/b4_qds.c
@@ -0,0 +1,102 @@
1/*
2 * B4 QDS Setup
3 * Should apply for QDS platform of B4860 and it's personalities.
4 * viz B4860/B4420/B4220QDS
5 *
6 * Copyright 2012 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/phy.h>
20
21#include <asm/time.h>
22#include <asm/machdep.h>
23#include <asm/pci-bridge.h>
24#include <mm/mmu_decl.h>
25#include <asm/prom.h>
26#include <asm/udbg.h>
27#include <asm/mpic.h>
28
29#include <linux/of_platform.h>
30#include <sysdev/fsl_soc.h>
31#include <sysdev/fsl_pci.h>
32#include <asm/ehv_pic.h>
33
34#include "corenet_ds.h"
35
36/*
37 * Called very early, device-tree isn't unflattened
38 */
39static int __init b4_qds_probe(void)
40{
41 unsigned long root = of_get_flat_dt_root();
42#ifdef CONFIG_SMP
43 extern struct smp_ops_t smp_85xx_ops;
44#endif
45
46 if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS")) ||
47 (of_flat_dt_is_compatible(root, "fsl,B4420QDS")) ||
48 (of_flat_dt_is_compatible(root, "fsl,B4220QDS")))
49 return 1;
50
51 /* Check if we're running under the Freescale hypervisor */
52 if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS-hv")) ||
53 (of_flat_dt_is_compatible(root, "fsl,B4420QDS-hv")) ||
54 (of_flat_dt_is_compatible(root, "fsl,B4220QDS-hv"))) {
55 ppc_md.init_IRQ = ehv_pic_init;
56 ppc_md.get_irq = ehv_pic_get_irq;
57 ppc_md.restart = fsl_hv_restart;
58 ppc_md.power_off = fsl_hv_halt;
59 ppc_md.halt = fsl_hv_halt;
60#ifdef CONFIG_SMP
61 /*
62 * Disable the timebase sync operations because we can't write
63 * to the timebase registers under the hypervisor.
64 */
65 smp_85xx_ops.give_timebase = NULL;
66 smp_85xx_ops.take_timebase = NULL;
67#endif
68 return 1;
69 }
70
71 return 0;
72}
73
74define_machine(b4_qds) {
75 .name = "B4 QDS",
76 .probe = b4_qds_probe,
77 .setup_arch = corenet_ds_setup_arch,
78 .init_IRQ = corenet_ds_pic_init,
79#ifdef CONFIG_PCI
80 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
81#endif
82/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
83#ifdef CONFIG_PPC64
84 .get_irq = mpic_get_irq,
85#else
86 .get_irq = mpic_get_coreint_irq,
87#endif
88 .restart = fsl_rstcr_restart,
89 .calibrate_decr = generic_calibrate_decr,
90 .progress = udbg_progress,
91#ifdef CONFIG_PPC64
92 .power_save = book3e_idle,
93#else
94 .power_save = e500_idle,
95#endif
96};
97
98machine_arch_initcall(b4_qds, corenet_ds_publish_devices);
99
100#ifdef CONFIG_SWIOTLB
101machine_arch_initcall(b4_qds, swiotlb_setup_bus_notifier);
102#endif
diff --git a/arch/powerpc/platforms/85xx/corenet_ds.c b/arch/powerpc/platforms/85xx/corenet_ds.c
index 6f355d8c92f6..c59c617eee93 100644
--- a/arch/powerpc/platforms/85xx/corenet_ds.c
+++ b/arch/powerpc/platforms/85xx/corenet_ds.c
@@ -40,7 +40,7 @@ void __init corenet_ds_pic_init(void)
40 if (ppc_md.get_irq == mpic_get_coreint_irq) 40 if (ppc_md.get_irq == mpic_get_coreint_irq)
41 flags |= MPIC_ENABLE_COREINT; 41 flags |= MPIC_ENABLE_COREINT;
42 42
43 mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC "); 43 mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC ");
44 BUG_ON(mpic == NULL); 44 BUG_ON(mpic == NULL);
45 45
46 mpic_init(mpic); 46 mpic_init(mpic);
@@ -83,6 +83,9 @@ static const struct of_device_id of_device_ids[] = {
83 { 83 {
84 .compatible = "fsl,qoriq-pcie-v2.4", 84 .compatible = "fsl,qoriq-pcie-v2.4",
85 }, 85 },
86 {
87 .compatible = "fsl,qoriq-pcie-v3.0",
88 },
86 /* The following two are for the Freescale hypervisor */ 89 /* The following two are for the Freescale hypervisor */
87 { 90 {
88 .name = "hypervisor", 91 .name = "hypervisor",
diff --git a/arch/powerpc/platforms/85xx/smp.c b/arch/powerpc/platforms/85xx/smp.c
index 148c2f2d9780..6a1759939c6b 100644
--- a/arch/powerpc/platforms/85xx/smp.c
+++ b/arch/powerpc/platforms/85xx/smp.c
@@ -201,7 +201,7 @@ static int __cpuinit smp_85xx_kick_cpu(int nr)
201 * We don't set the BPTR register here since it already points 201 * We don't set the BPTR register here since it already points
202 * to the boot page properly. 202 * to the boot page properly.
203 */ 203 */
204 mpic_reset_core(hw_cpu); 204 mpic_reset_core(nr);
205 205
206 /* 206 /*
207 * wait until core is ready... 207 * wait until core is ready...
diff --git a/arch/powerpc/platforms/85xx/t4240_qds.c b/arch/powerpc/platforms/85xx/t4240_qds.c
new file mode 100644
index 000000000000..5998e9f33304
--- /dev/null
+++ b/arch/powerpc/platforms/85xx/t4240_qds.c
@@ -0,0 +1,98 @@
1/*
2 * T4240 QDS Setup
3 *
4 * Maintained by Kumar Gala (see MAINTAINERS for contact information)
5 *
6 * Copyright 2012 Freescale Semiconductor Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/pci.h>
16#include <linux/kdev_t.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/phy.h>
20
21#include <asm/time.h>
22#include <asm/machdep.h>
23#include <asm/pci-bridge.h>
24#include <mm/mmu_decl.h>
25#include <asm/prom.h>
26#include <asm/udbg.h>
27#include <asm/mpic.h>
28
29#include <linux/of_platform.h>
30#include <sysdev/fsl_soc.h>
31#include <sysdev/fsl_pci.h>
32#include <asm/ehv_pic.h>
33
34#include "corenet_ds.h"
35
36/*
37 * Called very early, device-tree isn't unflattened
38 */
39static int __init t4240_qds_probe(void)
40{
41 unsigned long root = of_get_flat_dt_root();
42#ifdef CONFIG_SMP
43 extern struct smp_ops_t smp_85xx_ops;
44#endif
45
46 if (of_flat_dt_is_compatible(root, "fsl,T4240QDS"))
47 return 1;
48
49 /* Check if we're running under the Freescale hypervisor */
50 if (of_flat_dt_is_compatible(root, "fsl,T4240QDS-hv")) {
51 ppc_md.init_IRQ = ehv_pic_init;
52 ppc_md.get_irq = ehv_pic_get_irq;
53 ppc_md.restart = fsl_hv_restart;
54 ppc_md.power_off = fsl_hv_halt;
55 ppc_md.halt = fsl_hv_halt;
56#ifdef CONFIG_SMP
57 /*
58 * Disable the timebase sync operations because we can't write
59 * to the timebase registers under the hypervisor.
60 */
61 smp_85xx_ops.give_timebase = NULL;
62 smp_85xx_ops.take_timebase = NULL;
63#endif
64 return 1;
65 }
66
67 return 0;
68}
69
70define_machine(t4240_qds) {
71 .name = "T4240 QDS",
72 .probe = t4240_qds_probe,
73 .setup_arch = corenet_ds_setup_arch,
74 .init_IRQ = corenet_ds_pic_init,
75#ifdef CONFIG_PCI
76 .pcibios_fixup_bus = fsl_pcibios_fixup_bus,
77#endif
78/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
79#ifdef CONFIG_PPC64
80 .get_irq = mpic_get_irq,
81#else
82 .get_irq = mpic_get_coreint_irq,
83#endif
84 .restart = fsl_rstcr_restart,
85 .calibrate_decr = generic_calibrate_decr,
86 .progress = udbg_progress,
87#ifdef CONFIG_PPC64
88 .power_save = book3e_idle,
89#else
90 .power_save = e500_idle,
91#endif
92};
93
94machine_arch_initcall(t4240_qds, corenet_ds_publish_devices);
95
96#ifdef CONFIG_SWIOTLB
97machine_arch_initcall(t4240_qds, swiotlb_setup_bus_notifier);
98#endif
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 9089ae71334a..34d224be93ba 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -343,7 +343,6 @@ config FSL_ULI1575
343 343
344config CPM 344config CPM
345 bool 345 bool
346 select PPC_CLOCK
347 346
348config OF_RTC 347config OF_RTC
349 bool 348 bool
diff --git a/arch/powerpc/platforms/Kconfig.cputype b/arch/powerpc/platforms/Kconfig.cputype
index 18e3b76c78d7..54f3936001aa 100644
--- a/arch/powerpc/platforms/Kconfig.cputype
+++ b/arch/powerpc/platforms/Kconfig.cputype
@@ -230,7 +230,7 @@ config PHYS_64BIT
230 230
231config ALTIVEC 231config ALTIVEC
232 bool "AltiVec Support" 232 bool "AltiVec Support"
233 depends on 6xx || POWER4 233 depends on 6xx || POWER4 || (PPC_E500MC && PPC64)
234 ---help--- 234 ---help---
235 This option enables kernel support for the Altivec extensions to the 235 This option enables kernel support for the Altivec extensions to the
236 PowerPC processor. The kernel currently supports saving and restoring 236 PowerPC processor. The kernel currently supports saving and restoring
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index 178c99427b1c..ab02db3d02d8 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -333,6 +333,8 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
333 return 0; 333 return 0;
334} 334}
335 335
336static struct lock_class_key fsl_msi_irq_class;
337
336static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev, 338static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
337 int offset, int irq_index) 339 int offset, int irq_index)
338{ 340{
@@ -351,7 +353,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
351 dev_err(&dev->dev, "No memory for MSI cascade data\n"); 353 dev_err(&dev->dev, "No memory for MSI cascade data\n");
352 return -ENOMEM; 354 return -ENOMEM;
353 } 355 }
354 356 irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class);
355 msi->msi_virqs[irq_index] = virt_msir; 357 msi->msi_virqs[irq_index] = virt_msir;
356 cascade_data->index = offset; 358 cascade_data->index = offset;
357 cascade_data->msi_data = msi; 359 cascade_data->msi_data = msi;
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 682084dba19b..cf81d6516514 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -54,16 +54,63 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
54 return; 54 return;
55} 55}
56 56
57static int __init fsl_pcie_check_link(struct pci_controller *hose) 57static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
58 int, int, u32 *);
59
60static int fsl_pcie_check_link(struct pci_controller *hose)
58{ 61{
59 u32 val; 62 u32 val = 0;
63
64 if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
65 if (hose->ops->read == fsl_indirect_read_config) {
66 struct pci_bus bus;
67 bus.number = 0;
68 bus.sysdata = hose;
69 bus.ops = hose->ops;
70 indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
71 } else
72 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
73 if (val < PCIE_LTSSM_L0)
74 return 1;
75 } else {
76 struct ccsr_pci __iomem *pci = hose->private_data;
77 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
78 val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
79 >> PEX_CSR0_LTSSM_SHIFT;
80 if (val != PEX_CSR0_LTSSM_L0)
81 return 1;
82 }
60 83
61 early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
62 if (val < PCIE_LTSSM_L0)
63 return 1;
64 return 0; 84 return 0;
65} 85}
66 86
87static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
88 int offset, int len, u32 *val)
89{
90 struct pci_controller *hose = pci_bus_to_host(bus);
91
92 if (fsl_pcie_check_link(hose))
93 hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
94 else
95 hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
96
97 return indirect_read_config(bus, devfn, offset, len, val);
98}
99
100static struct pci_ops fsl_indirect_pci_ops =
101{
102 .read = fsl_indirect_read_config,
103 .write = indirect_write_config,
104};
105
106static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
107 resource_size_t cfg_addr,
108 resource_size_t cfg_data, u32 flags)
109{
110 setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
111 hose->ops = &fsl_indirect_pci_ops;
112}
113
67#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx) 114#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
68 115
69#define MAX_PHYS_ADDR_BITS 40 116#define MAX_PHYS_ADDR_BITS 40
@@ -106,7 +153,7 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
106 flags |= 0x10000000; /* enable relaxed ordering */ 153 flags |= 0x10000000; /* enable relaxed ordering */
107 154
108 for (i = 0; size > 0; i++) { 155 for (i = 0; size > 0; i++) {
109 unsigned int bits = min(__ilog2(size), 156 unsigned int bits = min(ilog2(size),
110 __ffs(pci_addr | phys_addr)); 157 __ffs(pci_addr | phys_addr));
111 158
112 if (index + i >= 5) 159 if (index + i >= 5)
@@ -126,10 +173,9 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
126} 173}
127 174
128/* atmu setup for fsl pci/pcie controller */ 175/* atmu setup for fsl pci/pcie controller */
129static void setup_pci_atmu(struct pci_controller *hose, 176static void setup_pci_atmu(struct pci_controller *hose)
130 struct resource *rsrc)
131{ 177{
132 struct ccsr_pci __iomem *pci; 178 struct ccsr_pci __iomem *pci = hose->private_data;
133 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4; 179 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
134 u64 mem, sz, paddr_hi = 0; 180 u64 mem, sz, paddr_hi = 0;
135 u64 paddr_lo = ULLONG_MAX; 181 u64 paddr_lo = ULLONG_MAX;
@@ -140,15 +186,6 @@ static void setup_pci_atmu(struct pci_controller *hose,
140 const u64 *reg; 186 const u64 *reg;
141 int len; 187 int len;
142 188
143 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
144 (u64)rsrc->start, (u64)resource_size(rsrc));
145
146 pci = ioremap(rsrc->start, resource_size(rsrc));
147 if (!pci) {
148 dev_err(hose->parent, "Unable to map ATMU registers\n");
149 return;
150 }
151
152 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 189 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
153 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) { 190 if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
154 win_idx = 2; 191 win_idx = 2;
@@ -196,7 +233,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
196 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12)); 233 out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
197 /* Enable, IO R/W */ 234 /* Enable, IO R/W */
198 out_be32(&pci->pow[j].powar, 0x80088000 235 out_be32(&pci->pow[j].powar, 0x80088000
199 | (__ilog2(hose->io_resource.end 236 | (ilog2(hose->io_resource.end
200 - hose->io_resource.start + 1) - 1)); 237 - hose->io_resource.start + 1) - 1));
201 } 238 }
202 } 239 }
@@ -207,12 +244,12 @@ static void setup_pci_atmu(struct pci_controller *hose,
207 244
208 if (paddr_hi == paddr_lo) { 245 if (paddr_hi == paddr_lo) {
209 pr_err("%s: No outbound window space\n", name); 246 pr_err("%s: No outbound window space\n", name);
210 goto out; 247 return;
211 } 248 }
212 249
213 if (paddr_lo == 0) { 250 if (paddr_lo == 0) {
214 pr_err("%s: No space for inbound window\n", name); 251 pr_err("%s: No space for inbound window\n", name);
215 goto out; 252 return;
216 } 253 }
217 254
218 /* setup PCSRBAR/PEXCSRBAR */ 255 /* setup PCSRBAR/PEXCSRBAR */
@@ -261,7 +298,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
261 } 298 }
262 299
263 sz = min(mem, paddr_lo); 300 sz = min(mem, paddr_lo);
264 mem_log = __ilog2_u64(sz); 301 mem_log = ilog2(sz);
265 302
266 /* PCIe can overmap inbound & outbound since RX & TX are separated */ 303 /* PCIe can overmap inbound & outbound since RX & TX are separated */
267 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 304 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
@@ -290,7 +327,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
290 * SWIOTLB and access the full range of memory 327 * SWIOTLB and access the full range of memory
291 */ 328 */
292 if (sz != mem) { 329 if (sz != mem) {
293 mem_log = __ilog2_u64(mem); 330 mem_log = ilog2(mem);
294 331
295 /* Size window up if we dont fit in exact power-of-2 */ 332 /* Size window up if we dont fit in exact power-of-2 */
296 if ((1ull << mem_log) != mem) 333 if ((1ull << mem_log) != mem)
@@ -327,7 +364,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
327 sz -= 1ull << mem_log; 364 sz -= 1ull << mem_log;
328 365
329 if (sz) { 366 if (sz) {
330 mem_log = __ilog2_u64(sz); 367 mem_log = ilog2(sz);
331 piwar |= (mem_log - 1); 368 piwar |= (mem_log - 1);
332 369
333 out_be32(&pci->piw[win_idx].pitar, paddr >> 12); 370 out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
@@ -358,9 +395,6 @@ static void setup_pci_atmu(struct pci_controller *hose,
358 pr_info("%s: DMA window size is 0x%llx\n", name, 395 pr_info("%s: DMA window size is 0x%llx\n", name,
359 (u64)hose->dma_window_size); 396 (u64)hose->dma_window_size);
360 } 397 }
361
362out:
363 iounmap(pci);
364} 398}
365 399
366static void __init setup_pci_cmd(struct pci_controller *hose) 400static void __init setup_pci_cmd(struct pci_controller *hose)
@@ -429,6 +463,7 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
429 const int *bus_range; 463 const int *bus_range;
430 u8 hdr_type, progif; 464 u8 hdr_type, progif;
431 struct device_node *dev; 465 struct device_node *dev;
466 struct ccsr_pci __iomem *pci;
432 467
433 dev = pdev->dev.of_node; 468 dev = pdev->dev.of_node;
434 469
@@ -461,8 +496,18 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
461 hose->first_busno = bus_range ? bus_range[0] : 0x0; 496 hose->first_busno = bus_range ? bus_range[0] : 0x0;
462 hose->last_busno = bus_range ? bus_range[1] : 0xff; 497 hose->last_busno = bus_range ? bus_range[1] : 0xff;
463 498
464 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4, 499 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
465 PPC_INDIRECT_TYPE_BIG_ENDIAN); 500 (u64)rsrc.start, (u64)resource_size(&rsrc));
501
502 pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
503 if (!hose->private_data)
504 goto no_bridge;
505
506 fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
507 PPC_INDIRECT_TYPE_BIG_ENDIAN);
508
509 if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
510 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
466 511
467 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) { 512 if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
468 /* For PCIE read HEADER_TYPE to identify controler mode */ 513 /* For PCIE read HEADER_TYPE to identify controler mode */
@@ -500,11 +545,12 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
500 pci_process_bridge_OF_ranges(hose, dev, is_primary); 545 pci_process_bridge_OF_ranges(hose, dev, is_primary);
501 546
502 /* Setup PEX window registers */ 547 /* Setup PEX window registers */
503 setup_pci_atmu(hose, &rsrc); 548 setup_pci_atmu(hose);
504 549
505 return 0; 550 return 0;
506 551
507no_bridge: 552no_bridge:
553 iounmap(hose->private_data);
508 /* unmap cfg_data & cfg_addr separately if not on same page */ 554 /* unmap cfg_data & cfg_addr separately if not on same page */
509 if (((unsigned long)hose->cfg_data & PAGE_MASK) != 555 if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
510 ((unsigned long)hose->cfg_addr & PAGE_MASK)) 556 ((unsigned long)hose->cfg_addr & PAGE_MASK))
@@ -681,6 +727,7 @@ static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
681 WARN_ON(hose->dn->data); 727 WARN_ON(hose->dn->data);
682 hose->dn->data = pcie; 728 hose->dn->data = pcie;
683 hose->ops = &mpc83xx_pcie_ops; 729 hose->ops = &mpc83xx_pcie_ops;
730 hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
684 731
685 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0); 732 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
686 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0); 733 out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
@@ -766,8 +813,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
766 if (ret) 813 if (ret)
767 goto err0; 814 goto err0;
768 } else { 815 } else {
769 setup_indirect_pci(hose, rsrc_cfg.start, 816 fsl_setup_indirect_pci(hose, rsrc_cfg.start,
770 rsrc_cfg.start + 4, 0); 817 rsrc_cfg.start + 4, 0);
771 } 818 }
772 819
773 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. " 820 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
@@ -836,6 +883,7 @@ static const struct of_device_id pci_ids[] = {
836 { .compatible = "fsl,qoriq-pcie-v2.2", }, 883 { .compatible = "fsl,qoriq-pcie-v2.2", },
837 { .compatible = "fsl,qoriq-pcie-v2.3", }, 884 { .compatible = "fsl,qoriq-pcie-v2.3", },
838 { .compatible = "fsl,qoriq-pcie-v2.4", }, 885 { .compatible = "fsl,qoriq-pcie-v2.4", },
886 { .compatible = "fsl,qoriq-pcie-v3.0", },
839 887
840 /* 888 /*
841 * The following entries are for compatibility with older device 889 * The following entries are for compatibility with older device
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index c495c00c8740..72b5625330e2 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -14,9 +14,12 @@
14#ifndef __POWERPC_FSL_PCI_H 14#ifndef __POWERPC_FSL_PCI_H
15#define __POWERPC_FSL_PCI_H 15#define __POWERPC_FSL_PCI_H
16 16
17struct platform_device;
18
17#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */ 19#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
18#define PCIE_LTSSM_L0 0x16 /* L0 state */ 20#define PCIE_LTSSM_L0 0x16 /* L0 state */
19#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */ 21#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
22#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
20#define PIWAR_EN 0x80000000 /* Enable */ 23#define PIWAR_EN 0x80000000 /* Enable */
21#define PIWAR_PF 0x20000000 /* prefetch */ 24#define PIWAR_PF 0x20000000 /* prefetch */
22#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ 25#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
@@ -89,6 +92,16 @@ struct ccsr_pci {
89 __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */ 92 __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
90 __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */ 93 __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
91 __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */ 94 __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
95 u8 res_e38[200];
96 __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */
97 u8 res_f04[16];
98 __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/
99#define PEX_CSR0_LTSSM_MASK 0xFC
100#define PEX_CSR0_LTSSM_SHIFT 2
101#define PEX_CSR0_LTSSM_L0 0x11
102 __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/
103 u8 res_f1c[228];
104
92}; 105};
93 106
94extern int fsl_add_bridge(struct platform_device *pdev, int is_primary); 107extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c
index 82fdad885d20..c6c8b526a4f6 100644
--- a/arch/powerpc/sysdev/indirect_pci.c
+++ b/arch/powerpc/sysdev/indirect_pci.c
@@ -20,9 +20,8 @@
20#include <asm/pci-bridge.h> 20#include <asm/pci-bridge.h>
21#include <asm/machdep.h> 21#include <asm/machdep.h>
22 22
23static int 23int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
24indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset, 24 int offset, int len, u32 *val)
25 int len, u32 *val)
26{ 25{
27 struct pci_controller *hose = pci_bus_to_host(bus); 26 struct pci_controller *hose = pci_bus_to_host(bus);
28 volatile void __iomem *cfg_data; 27 volatile void __iomem *cfg_data;
@@ -78,9 +77,8 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
78 return PCIBIOS_SUCCESSFUL; 77 return PCIBIOS_SUCCESSFUL;
79} 78}
80 79
81static int 80int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
82indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset, 81 int offset, int len, u32 val)
83 int len, u32 val)
84{ 82{
85 struct pci_controller *hose = pci_bus_to_host(bus); 83 struct pci_controller *hose = pci_bus_to_host(bus);
86 volatile void __iomem *cfg_data; 84 volatile void __iomem *cfg_data;
diff --git a/arch/powerpc/sysdev/qe_lib/Kconfig b/arch/powerpc/sysdev/qe_lib/Kconfig
index 41ac3dfac98e..3c251993bacd 100644
--- a/arch/powerpc/sysdev/qe_lib/Kconfig
+++ b/arch/powerpc/sysdev/qe_lib/Kconfig
@@ -22,6 +22,6 @@ config UCC
22 22
23config QE_USB 23config QE_USB
24 bool 24 bool
25 default y if USB_GADGET_FSL_QE 25 default y if USB_FSL_QE
26 help 26 help
27 QE USB Controller support 27 QE USB Controller support
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-16 00:28:03 -0500