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authorLinus Walleij <linus.walleij@linaro.org>2013-05-23 09:42:33 -0400
committerLinus Walleij <linus.walleij@linaro.org>2013-06-17 07:54:37 -0400
commitbba5f2cc2f0fe4191ad2699c7c03a6def31f54e2 (patch)
treefb7bc7d023f56292cc7c5b4335cbcfc77b611ba1
parent2165f836c8f7036491fae41e9bc327a3cdf2fea3 (diff)
ARM: u300: move the gated system controller clocks to DT
This moves the slow, fast, AHB bridge and "rest" clocks on the U300 system controller over to registration from the device tree. Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt57
-rw-r--r--arch/arm/boot/dts/ste-u300.dts149
-rw-r--r--arch/arm/mach-u300/timer.c2
-rw-r--r--drivers/clk/clk-u300.c320
4 files changed, 418 insertions, 110 deletions
diff --git a/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
new file mode 100644
index 000000000000..b6a30f5eb580
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ste-u300-syscon-clock.txt
@@ -0,0 +1,57 @@
1Clock bindings for ST-Ericsson U300 System Controller Clocks
2
3Bindings for the gated system controller clocks:
4
5Required properties:
6- compatible: must be "stericsson,u300-syscon-clk"
7- #clock-cells: must be <0>
8- clock-type: specifies the type of clock:
9 0 = slow clock
10 1 = fast clock
11 2 = rest/remaining clock
12- clock-id: specifies the clock in the type range
13
14Optional properties:
15- clocks: parent clock(s)
16
17The available clocks per type are as follows:
18
19Type: ID: Clock:
20-------------------
210 0 Slow peripheral bridge clock
220 1 UART0 clock
230 4 GPIO clock
240 6 RTC clock
250 7 Application timer clock
260 8 Access timer clock
27
281 0 Fast peripheral bridge clock
291 1 I2C bus 0 clock
301 2 I2C bus 1 clock
311 5 MMC interface peripheral (silicon) clock
321 6 SPI clock
33
342 3 CPU clock
352 4 DMA controller clock
362 5 External Memory Interface (EMIF) clock
372 6 NAND flask interface clock
382 8 XGAM graphics engine clock
392 9 Shared External Memory Interface (SEMI) clock
402 10 AHB Subsystem Bridge clock
412 12 Interrupt controller clock
42
43Example:
44
45gpio_clk: gpio_clk@13M {
46 #clock-cells = <0>;
47 compatible = "stericsson,u300-syscon-clk";
48 clock-type = <0>; /* Slow */
49 clock-id = <4>;
50 clocks = <&slow_clk>;
51};
52
53gpio: gpio@c0016000 {
54 compatible = "stericsson,gpio-coh901";
55 (...)
56 clocks = <&gpio_clk>;
57};
diff --git a/arch/arm/boot/dts/ste-u300.dts b/arch/arm/boot/dts/ste-u300.dts
index 203ec1fcbc10..7edc5e58a5a5 100644
--- a/arch/arm/boot/dts/ste-u300.dts
+++ b/arch/arm/boot/dts/ste-u300.dts
@@ -43,6 +43,49 @@
43 compatible = "fixed-clock"; 43 compatible = "fixed-clock";
44 clock-frequency = <13000000>; 44 clock-frequency = <13000000>;
45 }; 45 };
46 /* Slow bridge clocks under PLL13 */
47 slow_clk: slow_clk@13M {
48 #clock-cells = <0>;
49 compatible = "stericsson,u300-syscon-clk";
50 clock-type = <0>; /* Slow */
51 clock-id = <0>;
52 clocks = <&pll13>;
53 };
54 uart0_clk: uart0_clk@13M {
55 #clock-cells = <0>;
56 compatible = "stericsson,u300-syscon-clk";
57 clock-type = <0>; /* Slow */
58 clock-id = <1>;
59 clocks = <&slow_clk>;
60 };
61 gpio_clk: gpio_clk@13M {
62 #clock-cells = <0>;
63 compatible = "stericsson,u300-syscon-clk";
64 clock-type = <0>; /* Slow */
65 clock-id = <4>;
66 clocks = <&slow_clk>;
67 };
68 rtc_clk: rtc_clk@13M {
69 #clock-cells = <0>;
70 compatible = "stericsson,u300-syscon-clk";
71 clock-type = <0>; /* Slow */
72 clock-id = <6>;
73 clocks = <&slow_clk>;
74 };
75 apptimer_clk: app_tmr_clk@13M {
76 #clock-cells = <0>;
77 compatible = "stericsson,u300-syscon-clk";
78 clock-type = <0>; /* Slow */
79 clock-id = <7>;
80 clocks = <&slow_clk>;
81 };
82 acc_tmr_clk@13M {
83 #clock-cells = <0>;
84 compatible = "stericsson,u300-syscon-clk";
85 clock-type = <0>; /* Slow */
86 clock-id = <8>;
87 clocks = <&slow_clk>;
88 };
46 pll208: pll208@208M { 89 pll208: pll208@208M {
47 #clock-cells = <0>; 90 #clock-cells = <0>;
48 compatible = "fixed-clock"; 91 compatible = "fixed-clock";
@@ -55,6 +98,13 @@
55 clock-mult = <1>; 98 clock-mult = <1>;
56 clocks = <&pll208>; 99 clocks = <&pll208>;
57 }; 100 };
101 cpu_clk@208M {
102 #clock-cells = <0>;
103 compatible = "stericsson,u300-syscon-clk";
104 clock-type = <2>; /* Rest */
105 clock-id = <3>;
106 clocks = <&app208>;
107 };
58 app104: app_104_clk@104M { 108 app104: app_104_clk@104M {
59 #clock-cells = <0>; 109 #clock-cells = <0>;
60 compatible = "fixed-factor-clock"; 110 compatible = "fixed-factor-clock";
@@ -62,6 +112,13 @@
62 clock-mult = <1>; 112 clock-mult = <1>;
63 clocks = <&pll208>; 113 clocks = <&pll208>;
64 }; 114 };
115 semi_clk@104M {
116 #clock-cells = <0>;
117 compatible = "stericsson,u300-syscon-clk";
118 clock-type = <2>; /* Rest */
119 clock-id = <9>;
120 clocks = <&app104>;
121 };
65 app52: app_52_clk@52M { 122 app52: app_52_clk@52M {
66 #clock-cells = <0>; 123 #clock-cells = <0>;
67 compatible = "fixed-factor-clock"; 124 compatible = "fixed-factor-clock";
@@ -69,6 +126,49 @@
69 clock-mult = <1>; 126 clock-mult = <1>;
70 clocks = <&pll208>; 127 clocks = <&pll208>;
71 }; 128 };
129 /* AHB subsystem clocks */
130 ahb_clk: ahb_subsys_clk@52M {
131 #clock-cells = <0>;
132 compatible = "stericsson,u300-syscon-clk";
133 clock-type = <2>; /* Rest */
134 clock-id = <10>;
135 clocks = <&app52>;
136 };
137 intcon_clk@52M {
138 #clock-cells = <0>;
139 compatible = "stericsson,u300-syscon-clk";
140 clock-type = <2>; /* Rest */
141 clock-id = <12>;
142 clocks = <&ahb_clk>;
143 };
144 emif_clk@52M {
145 #clock-cells = <0>;
146 compatible = "stericsson,u300-syscon-clk";
147 clock-type = <2>; /* Rest */
148 clock-id = <5>;
149 clocks = <&ahb_clk>;
150 };
151 dmac_clk: dmac_clk@52M {
152 #clock-cells = <0>;
153 compatible = "stericsson,u300-syscon-clk";
154 clock-type = <2>; /* Rest */
155 clock-id = <4>;
156 clocks = <&app52>;
157 };
158 fsmc_clk: fsmc_clk@52M {
159 #clock-cells = <0>;
160 compatible = "stericsson,u300-syscon-clk";
161 clock-type = <2>; /* Rest */
162 clock-id = <6>;
163 clocks = <&app52>;
164 };
165 xgam_clk: xgam_clk@52M {
166 #clock-cells = <0>;
167 compatible = "stericsson,u300-syscon-clk";
168 clock-type = <2>; /* Rest */
169 clock-id = <8>;
170 clocks = <&app52>;
171 };
72 app26: app_26_clk@26M { 172 app26: app_26_clk@26M {
73 #clock-cells = <0>; 173 #clock-cells = <0>;
74 compatible = "fixed-factor-clock"; 174 compatible = "fixed-factor-clock";
@@ -76,6 +176,42 @@
76 clock-mult = <1>; 176 clock-mult = <1>;
77 clocks = <&app52>; 177 clocks = <&app52>;
78 }; 178 };
179 /* Fast bridge clocks */
180 fast_clk: fast_clk@26M {
181 #clock-cells = <0>;
182 compatible = "stericsson,u300-syscon-clk";
183 clock-type = <1>; /* Fast */
184 clock-id = <0>;
185 clocks = <&app26>;
186 };
187 i2c0_clk: i2c0_clk@26M {
188 #clock-cells = <0>;
189 compatible = "stericsson,u300-syscon-clk";
190 clock-type = <1>; /* Fast */
191 clock-id = <1>;
192 clocks = <&fast_clk>;
193 };
194 i2c1_clk: i2c1_clk@26M {
195 #clock-cells = <0>;
196 compatible = "stericsson,u300-syscon-clk";
197 clock-type = <1>; /* Fast */
198 clock-id = <2>;
199 clocks = <&fast_clk>;
200 };
201 mmc_pclk: mmc_p_clk@26M {
202 #clock-cells = <0>;
203 compatible = "stericsson,u300-syscon-clk";
204 clock-type = <1>; /* Fast */
205 clock-id = <5>;
206 clocks = <&fast_clk>;
207 };
208 spi_clk: spi_p_clk@26M {
209 #clock-cells = <0>;
210 compatible = "stericsson,u300-syscon-clk";
211 clock-type = <1>; /* Fast */
212 clock-id = <6>;
213 clocks = <&fast_clk>;
214 };
79 }; 215 };
80 216
81 timer: timer@c0014000 { 217 timer: timer@c0014000 {
@@ -83,6 +219,7 @@
83 reg = <0xc0014000 0x1000>; 219 reg = <0xc0014000 0x1000>;
84 interrupt-parent = <&vica>; 220 interrupt-parent = <&vica>;
85 interrupts = <24 25 26 27>; 221 interrupts = <24 25 26 27>;
222 clocks = <&apptimer_clk>;
86 }; 223 };
87 224
88 gpio: gpio@c0016000 { 225 gpio: gpio@c0016000 {
@@ -90,6 +227,7 @@
90 reg = <0xc0016000 0x1000>; 227 reg = <0xc0016000 0x1000>;
91 interrupt-parent = <&vicb>; 228 interrupt-parent = <&vicb>;
92 interrupts = <0 1 2 18 21 22 23>; 229 interrupts = <0 1 2 18 21 22 23>;
230 clocks = <&gpio_clk>;
93 interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3", 231 interrupt-names = "gpio0", "gpio1", "gpio2", "gpio3",
94 "gpio4", "gpio5", "gpio6"; 232 "gpio4", "gpio5", "gpio6";
95 interrupt-controller; 233 interrupt-controller;
@@ -116,6 +254,7 @@
116 reg = <0xc0017000 0x1000>; 254 reg = <0xc0017000 0x1000>;
117 interrupt-parent = <&vicb>; 255 interrupt-parent = <&vicb>;
118 interrupts = <10>; 256 interrupts = <10>;
257 clocks = <&rtc_clk>;
119 }; 258 };
120 259
121 dmac: dma-controller@c00020000 { 260 dmac: dma-controller@c00020000 {
@@ -125,6 +264,7 @@
125 interrupts = <2>; 264 interrupts = <2>;
126 #dma-cells = <1>; 265 #dma-cells = <1>;
127 dma-channels = <40>; 266 dma-channels = <40>;
267 clocks = <&dmac_clk>;
128 }; 268 };
129 269
130 /* A NAND flash of 128 MiB */ 270 /* A NAND flash of 128 MiB */
@@ -138,6 +278,7 @@
138 <0x80010000 0x4000>; /* NAND Base CMD */ 278 <0x80010000 0x4000>; /* NAND Base CMD */
139 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; 279 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
140 nand-skip-bbtscan; 280 nand-skip-bbtscan;
281 clocks = <&fsmc_clk>;
141 282
142 partition@0 { 283 partition@0 {
143 label = "boot records"; 284 label = "boot records";
@@ -158,6 +299,7 @@
158 reg = <0xc0004000 0x1000>; 299 reg = <0xc0004000 0x1000>;
159 interrupt-parent = <&vicb>; 300 interrupt-parent = <&vicb>;
160 interrupts = <8>; 301 interrupts = <8>;
302 clocks = <&i2c0_clk>;
161 #address-cells = <1>; 303 #address-cells = <1>;
162 #size-cells = <0>; 304 #size-cells = <0>;
163 ab3100: ab3100@0x48 { 305 ab3100: ab3100@0x48 {
@@ -235,6 +377,7 @@
235 reg = <0xc0005000 0x1000>; 377 reg = <0xc0005000 0x1000>;
236 interrupt-parent = <&vicb>; 378 interrupt-parent = <&vicb>;
237 interrupts = <9>; 379 interrupts = <9>;
380 clocks = <&i2c1_clk>;
238 #address-cells = <1>; 381 #address-cells = <1>;
239 #size-cells = <0>; 382 #size-cells = <0>;
240 fwcam0: fwcam@0x10 { 383 fwcam0: fwcam@0x10 {
@@ -270,6 +413,8 @@
270 reg = <0xc0013000 0x1000>; 413 reg = <0xc0013000 0x1000>;
271 interrupt-parent = <&vica>; 414 interrupt-parent = <&vica>;
272 interrupts = <22>; 415 interrupts = <22>;
416 clocks = <&uart0_clk>, <&uart0_clk>;
417 clock-names = "apb_pclk", "uart0_clk";
273 dmas = <&dmac 17 &dmac 18>; 418 dmas = <&dmac 17 &dmac 18>;
274 dma-names = "tx", "rx"; 419 dma-names = "tx", "rx";
275 }; 420 };
@@ -288,6 +433,8 @@
288 reg = <0xc0001000 0x1000>; 433 reg = <0xc0001000 0x1000>;
289 interrupt-parent = <&vicb>; 434 interrupt-parent = <&vicb>;
290 interrupts = <6 7>; 435 interrupts = <6 7>;
436 clocks = <&mmc_pclk>;
437 clock-names = "apb_pclk";
291 max-frequency = <24000000>; 438 max-frequency = <24000000>;
292 bus-width = <4>; // SD-card slot 439 bus-width = <4>; // SD-card slot
293 mmc-cap-mmc-highspeed; 440 mmc-cap-mmc-highspeed;
@@ -304,6 +451,8 @@
304 reg = <0xc0006000 0x1000>; 451 reg = <0xc0006000 0x1000>;
305 interrupt-parent = <&vica>; 452 interrupt-parent = <&vica>;
306 interrupts = <23>; 453 interrupts = <23>;
454 clocks = <&spi_clk>, <&spi_clk>;
455 clock-names = "apb_pclk", "spi_clk";
307 dmas = <&dmac 27 &dmac 28>; 456 dmas = <&dmac 27 &dmac 28>;
308 dma-names = "tx", "rx"; 457 dma-names = "tx", "rx";
309 num-cs = <3>; 458 num-cs = <3>;
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 2e1c81daf3c1..390ae5feb1d0 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -375,7 +375,7 @@ static void __init u300_timer_init_of(struct device_node *np)
375 pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq); 375 pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
376 376
377 /* Clock the interrupt controller */ 377 /* Clock the interrupt controller */
378 clk = clk_get_sys("apptimer", NULL); 378 clk = of_clk_get(np, 0);
379 BUG_ON(IS_ERR(clk)); 379 BUG_ON(IS_ERR(clk));
380 clk_prepare_enable(clk); 380 clk_prepare_enable(clk);
381 rate = clk_get_rate(clk); 381 rate = clk_get_rate(clk);
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index bebd6c973d4b..5f234d37ccbe 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -728,6 +728,213 @@ syscon_clk_register(struct device *dev, const char *name,
728 return clk; 728 return clk;
729} 729}
730 730
731#define U300_CLK_TYPE_SLOW 0
732#define U300_CLK_TYPE_FAST 1
733#define U300_CLK_TYPE_REST 2
734
735/**
736 * struct u300_clock - defines the bits and pieces for a certain clock
737 * @type: the clock type, slow fast or rest
738 * @id: the bit in the slow/fast/rest register for this clock
739 * @hw_ctrld: whether the clock is hardware controlled
740 * @clk_val: a value to poke in the one-write enable/disable registers
741 */
742struct u300_clock {
743 u8 type;
744 u8 id;
745 bool hw_ctrld;
746 u16 clk_val;
747};
748
749struct u300_clock const __initconst u300_clk_lookup[] = {
750 {
751 .type = U300_CLK_TYPE_REST,
752 .id = 3,
753 .hw_ctrld = true,
754 .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
755 },
756 {
757 .type = U300_CLK_TYPE_REST,
758 .id = 4,
759 .hw_ctrld = true,
760 .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
761 },
762 {
763 .type = U300_CLK_TYPE_REST,
764 .id = 5,
765 .hw_ctrld = false,
766 .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
767 },
768 {
769 .type = U300_CLK_TYPE_REST,
770 .id = 6,
771 .hw_ctrld = false,
772 .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
773 },
774 {
775 .type = U300_CLK_TYPE_REST,
776 .id = 8,
777 .hw_ctrld = true,
778 .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
779 },
780 {
781 .type = U300_CLK_TYPE_REST,
782 .id = 9,
783 .hw_ctrld = false,
784 .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
785 },
786 {
787 .type = U300_CLK_TYPE_REST,
788 .id = 10,
789 .hw_ctrld = true,
790 .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
791 },
792 {
793 .type = U300_CLK_TYPE_REST,
794 .id = 12,
795 .hw_ctrld = false,
796 /* INTCON: cannot be enabled, just taken out of reset */
797 .clk_val = 0xFFFFU,
798 },
799 {
800 .type = U300_CLK_TYPE_FAST,
801 .id = 0,
802 .hw_ctrld = true,
803 .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
804 },
805 {
806 .type = U300_CLK_TYPE_FAST,
807 .id = 1,
808 .hw_ctrld = false,
809 .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
810 },
811 {
812 .type = U300_CLK_TYPE_FAST,
813 .id = 2,
814 .hw_ctrld = false,
815 .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
816 },
817 {
818 .type = U300_CLK_TYPE_FAST,
819 .id = 5,
820 .hw_ctrld = false,
821 .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
822 },
823 {
824 .type = U300_CLK_TYPE_FAST,
825 .id = 6,
826 .hw_ctrld = false,
827 .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
828 },
829 {
830 .type = U300_CLK_TYPE_SLOW,
831 .id = 0,
832 .hw_ctrld = true,
833 .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
834 },
835 {
836 .type = U300_CLK_TYPE_SLOW,
837 .id = 1,
838 .hw_ctrld = false,
839 .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
840 },
841 {
842 .type = U300_CLK_TYPE_SLOW,
843 .id = 4,
844 .hw_ctrld = false,
845 .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
846 },
847 {
848 .type = U300_CLK_TYPE_SLOW,
849 .id = 6,
850 .hw_ctrld = true,
851 /* No clock enable register bit */
852 .clk_val = 0xFFFFU,
853 },
854 {
855 .type = U300_CLK_TYPE_SLOW,
856 .id = 7,
857 .hw_ctrld = false,
858 .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
859 },
860 {
861 .type = U300_CLK_TYPE_SLOW,
862 .id = 8,
863 .hw_ctrld = false,
864 .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
865 },
866};
867
868static void __init of_u300_syscon_clk_init(struct device_node *np)
869{
870 struct clk *clk = ERR_PTR(-EINVAL);
871 const char *clk_name = np->name;
872 const char *parent_name;
873 void __iomem *res_reg;
874 void __iomem *en_reg;
875 u32 clk_type;
876 u32 clk_id;
877 int i;
878
879 if (of_property_read_u32(np, "clock-type", &clk_type)) {
880 pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
881 __func__, clk_name);
882 return;
883 }
884 if (of_property_read_u32(np, "clock-id", &clk_id)) {
885 pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
886 __func__, clk_name);
887 return;
888 }
889 parent_name = of_clk_get_parent_name(np, 0);
890
891 switch (clk_type) {
892 case U300_CLK_TYPE_SLOW:
893 res_reg = syscon_vbase + U300_SYSCON_RSR;
894 en_reg = syscon_vbase + U300_SYSCON_CESR;
895 break;
896 case U300_CLK_TYPE_FAST:
897 res_reg = syscon_vbase + U300_SYSCON_RFR;
898 en_reg = syscon_vbase + U300_SYSCON_CEFR;
899 break;
900 case U300_CLK_TYPE_REST:
901 res_reg = syscon_vbase + U300_SYSCON_RRR;
902 en_reg = syscon_vbase + U300_SYSCON_CERR;
903 break;
904 default:
905 pr_err("unknown clock type %x specified\n", clk_type);
906 return;
907 }
908
909 for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
910 const struct u300_clock *u3clk = &u300_clk_lookup[i];
911
912 if (u3clk->type == clk_type && u3clk->id == clk_id)
913 clk = syscon_clk_register(NULL,
914 clk_name, parent_name,
915 0, u3clk->hw_ctrld,
916 res_reg, u3clk->id,
917 en_reg, u3clk->id,
918 u3clk->clk_val);
919 }
920
921 if (!IS_ERR(clk)) {
922 of_clk_add_provider(np, of_clk_src_simple_get, clk);
923
924 /*
925 * Some few system clocks - device tree does not
926 * represent clocks without a corresponding device node.
927 * for now we add these three clocks here.
928 */
929 if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
930 clk_register_clkdev(clk, NULL, "pl172");
931 if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
932 clk_register_clkdev(clk, NULL, "semi");
933 if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
934 clk_register_clkdev(clk, NULL, "intcon");
935 }
936}
937
731/** 938/**
732 * struct clk_mclk - U300 MCLK clock (MMC/SD clock) 939 * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
733 * @hw: corresponding clock hardware entry 940 * @hw: corresponding clock hardware entry
@@ -941,6 +1148,10 @@ static const __initconst struct of_device_id u300_clk_match[] = {
941 .compatible = "fixed-factor-clock", 1148 .compatible = "fixed-factor-clock",
942 .data = of_fixed_factor_clk_setup, 1149 .data = of_fixed_factor_clk_setup,
943 }, 1150 },
1151 {
1152 .compatible = "stericsson,u300-syscon-clk",
1153 .data = of_u300_syscon_clk_init,
1154 },
944}; 1155};
945 1156
946void __init u300_clk_init(void __iomem *base) 1157void __init u300_clk_init(void __iomem *base)
@@ -965,115 +1176,6 @@ void __init u300_clk_init(void __iomem *base)
965 1176
966 of_clk_init(u300_clk_match); 1177 of_clk_init(u300_clk_match);
967 1178
968 /* Directly on the AMBA interconnect */
969 clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
970 syscon_vbase + U300_SYSCON_RRR, 3,
971 syscon_vbase + U300_SYSCON_CERR, 3,
972 U300_SYSCON_SBCER_CPU_CLK_EN);
973 clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
974 syscon_vbase + U300_SYSCON_RRR, 4,
975 syscon_vbase + U300_SYSCON_CERR, 4,
976 U300_SYSCON_SBCER_DMAC_CLK_EN);
977 clk_register_clkdev(clk, NULL, "dma");
978 clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
979 syscon_vbase + U300_SYSCON_RRR, 6,
980 syscon_vbase + U300_SYSCON_CERR, 6,
981 U300_SYSCON_SBCER_NANDIF_CLK_EN);
982 clk_register_clkdev(clk, NULL, "fsmc-nand");
983 clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
984 syscon_vbase + U300_SYSCON_RRR, 8,
985 syscon_vbase + U300_SYSCON_CERR, 8,
986 U300_SYSCON_SBCER_XGAM_CLK_EN);
987 clk_register_clkdev(clk, NULL, "xgam");
988 clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
989 syscon_vbase + U300_SYSCON_RRR, 9,
990 syscon_vbase + U300_SYSCON_CERR, 9,
991 U300_SYSCON_SBCER_SEMI_CLK_EN);
992 clk_register_clkdev(clk, NULL, "semi");
993
994 /* AHB bridge clocks */
995 clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
996 syscon_vbase + U300_SYSCON_RRR, 10,
997 syscon_vbase + U300_SYSCON_CERR, 10,
998 U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
999 clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
1000 syscon_vbase + U300_SYSCON_RRR, 12,
1001 syscon_vbase + U300_SYSCON_CERR, 12,
1002 /* Cannot be enabled, just taken out of reset */
1003 0xFFFFU);
1004 clk_register_clkdev(clk, NULL, "intcon");
1005 clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
1006 syscon_vbase + U300_SYSCON_RRR, 5,
1007 syscon_vbase + U300_SYSCON_CERR, 5,
1008 U300_SYSCON_SBCER_EMIF_CLK_EN);
1009 clk_register_clkdev(clk, NULL, "pl172");
1010
1011 /* FAST bridge clocks */
1012 clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
1013 syscon_vbase + U300_SYSCON_RFR, 0,
1014 syscon_vbase + U300_SYSCON_CEFR, 0,
1015 U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
1016 clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
1017 syscon_vbase + U300_SYSCON_RFR, 1,
1018 syscon_vbase + U300_SYSCON_CEFR, 1,
1019 U300_SYSCON_SBCER_I2C0_CLK_EN);
1020 clk_register_clkdev(clk, NULL, "stu300.0");
1021 clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
1022 syscon_vbase + U300_SYSCON_RFR, 2,
1023 syscon_vbase + U300_SYSCON_CEFR, 2,
1024 U300_SYSCON_SBCER_I2C1_CLK_EN);
1025 clk_register_clkdev(clk, NULL, "stu300.1");
1026 clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
1027 syscon_vbase + U300_SYSCON_RFR, 5,
1028 syscon_vbase + U300_SYSCON_CEFR, 5,
1029 U300_SYSCON_SBCER_MMC_CLK_EN);
1030 clk_register_clkdev(clk, "apb_pclk", "mmci");
1031 clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
1032 syscon_vbase + U300_SYSCON_RFR, 6,
1033 syscon_vbase + U300_SYSCON_CEFR, 6,
1034 U300_SYSCON_SBCER_SPI_CLK_EN);
1035 /* The SPI has no external clock for the outward bus, uses the pclk */
1036 clk_register_clkdev(clk, NULL, "pl022");
1037 clk_register_clkdev(clk, "apb_pclk", "pl022");
1038
1039 /* SLOW bridge clocks */
1040 clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
1041 syscon_vbase + U300_SYSCON_RSR, 0,
1042 syscon_vbase + U300_SYSCON_CESR, 0,
1043 U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
1044 clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
1045 syscon_vbase + U300_SYSCON_RSR, 1,
1046 syscon_vbase + U300_SYSCON_CESR, 1,
1047 U300_SYSCON_SBCER_UART_CLK_EN);
1048 /* Same clock is used for APB and outward bus */
1049 clk_register_clkdev(clk, NULL, "uart0");
1050 clk_register_clkdev(clk, "apb_pclk", "uart0");
1051 clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
1052 syscon_vbase + U300_SYSCON_RSR, 4,
1053 syscon_vbase + U300_SYSCON_CESR, 4,
1054 U300_SYSCON_SBCER_GPIO_CLK_EN);
1055 clk_register_clkdev(clk, NULL, "u300-gpio");
1056 clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
1057 syscon_vbase + U300_SYSCON_RSR, 5,
1058 syscon_vbase + U300_SYSCON_CESR, 6,
1059 U300_SYSCON_SBCER_KEYPAD_CLK_EN);
1060 clk_register_clkdev(clk, NULL, "coh901461-keypad");
1061 clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
1062 syscon_vbase + U300_SYSCON_RSR, 6,
1063 /* No clock enable register bit */
1064 NULL, 0, 0xFFFFU);
1065 clk_register_clkdev(clk, NULL, "rtc-coh901331");
1066 clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
1067 syscon_vbase + U300_SYSCON_RSR, 7,
1068 syscon_vbase + U300_SYSCON_CESR, 7,
1069 U300_SYSCON_SBCER_APP_TMR_CLK_EN);
1070 clk_register_clkdev(clk, NULL, "apptimer");
1071 clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
1072 syscon_vbase + U300_SYSCON_RSR, 8,
1073 syscon_vbase + U300_SYSCON_CESR, 8,
1074 U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
1075 clk_register_clkdev(clk, NULL, "timer");
1076
1077 /* Then this special MMC/SD clock */ 1179 /* Then this special MMC/SD clock */
1078 clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false); 1180 clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
1079 clk_register_clkdev(clk, NULL, "mmci"); 1181 clk_register_clkdev(clk, NULL, "mmci");
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 01:43:59 -0500