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authorSascha Hauer <s.hauer@pengutronix.de>2011-09-20 08:28:17 -0400
committerSascha Hauer <s.hauer@pengutronix.de>2011-09-26 05:40:35 -0400
commitb6de943bdffdc94482dd1a29015ca75e893bb5f2 (patch)
treeea4d085dd1d145bad31a92cb3505de24e882eebf
parentfcb8ce5cfe30ca9ca5c9a79cdfe26d1993e65e0c (diff)
ARM i.MX avic: add handle_irq function
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
-rw-r--r--arch/arm/plat-mxc/avic.c13
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h10
2 files changed, 23 insertions, 0 deletions
diff --git a/arch/arm/plat-mxc/avic.c b/arch/arm/plat-mxc/avic.c
index 55d2534ec727..4d68c5a6faca 100644
--- a/arch/arm/plat-mxc/avic.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -116,6 +116,19 @@ static struct mxc_irq_chip mxc_avic_chip = {
116#endif 116#endif
117}; 117};
118 118
119asmlinkage void __exception_irq_entry avic_handle_irq(struct pt_regs *regs)
120{
121 u32 nivector;
122
123 do {
124 nivector = __raw_readl(avic_base + AVIC_NIVECSR) >> 16;
125 if (nivector == 0xffff)
126 break;
127
128 handle_IRQ(nivector, regs);
129 } while (1);
130}
131
119/* 132/*
120 * This function initializes the AVIC hardware and disables all the 133 * This function initializes the AVIC hardware and disables all the
121 * interrupts. It registers the interrupt enable and disable functions 134 * interrupts. It registers the interrupt enable and disable functions
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 4e3d97890d69..6a6182df1870 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -72,4 +72,14 @@ extern void mxc_arch_reset_init(void __iomem *);
72extern void mx51_efikamx_reset(void); 72extern void mx51_efikamx_reset(void);
73extern int mx53_revision(void); 73extern int mx53_revision(void);
74extern int mx53_display_revision(void); 74extern int mx53_display_revision(void);
75
76void avic_handle_irq(struct pt_regs *);
77
78#define imx1_handle_irq avic_handle_irq
79#define imx21_handle_irq avic_handle_irq
80#define imx25_handle_irq avic_handle_irq
81#define imx27_handle_irq avic_handle_irq
82#define imx31_handle_irq avic_handle_irq
83#define imx35_handle_irq avic_handle_irq
84
75#endif 85#endif