diff options
author | Felipe Balbi <balbi@ti.com> | 2014-09-15 17:15:07 -0400 |
---|---|---|
committer | Tony Lindgren <tony@atomide.com> | 2014-09-16 17:45:00 -0400 |
commit | b30791498a140d9460dfb9cb8edcb6fd1065363c (patch) | |
tree | 04e8f867d7e51679b2a9c1df91652668c248cf22 | |
parent | 9836ee9f87dc669c8ce2b24ba986600a6977ca8b (diff) |
irqchip: omap-intc: enable TURBO idle mode
When TURBO bit is set in the INTC_IDLE register,
the input synchronizer clock will be autogated
based on activity on the INTC.
Because this idle mode increases the interrupt
latency by 2 clock cycles, we're only enabling
it during suspend.
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r-- | drivers/irqchip/irq-omap-intc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/irqchip/irq-omap-intc.c b/drivers/irqchip/irq-omap-intc.c index 7681b1329976..dfa2d9de5361 100644 --- a/drivers/irqchip/irq-omap-intc.c +++ b/drivers/irqchip/irq-omap-intc.c | |||
@@ -51,6 +51,9 @@ | |||
51 | #define INTCPS_NR_ILR_REGS 128 | 51 | #define INTCPS_NR_ILR_REGS 128 |
52 | #define INTCPS_NR_MIR_REGS 3 | 52 | #define INTCPS_NR_MIR_REGS 3 |
53 | 53 | ||
54 | #define INTC_IDLE_FUNCIDLE (1 << 0) | ||
55 | #define INTC_IDLE_TURBO (1 << 1) | ||
56 | |||
54 | #define INTC_PROTECTION_ENABLE (1 << 0) | 57 | #define INTC_PROTECTION_ENABLE (1 << 0) |
55 | 58 | ||
56 | /* | 59 | /* |
@@ -134,12 +137,14 @@ void omap3_intc_prepare_idle(void) | |||
134 | * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) | 137 | * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) |
135 | */ | 138 | */ |
136 | intc_writel(INTC_SYSCONFIG, 0); | 139 | intc_writel(INTC_SYSCONFIG, 0); |
140 | intc_writel(INTC_IDLE, INTC_IDLE_TURBO); | ||
137 | } | 141 | } |
138 | 142 | ||
139 | void omap3_intc_resume_idle(void) | 143 | void omap3_intc_resume_idle(void) |
140 | { | 144 | { |
141 | /* Re-enable autoidle */ | 145 | /* Re-enable autoidle */ |
142 | intc_writel(INTC_SYSCONFIG, 1); | 146 | intc_writel(INTC_SYSCONFIG, 1); |
147 | intc_writel(INTC_IDLE, 0); | ||
143 | } | 148 | } |
144 | 149 | ||
145 | /* XXX: FIQ and additional INTC support (only MPU at the moment) */ | 150 | /* XXX: FIQ and additional INTC support (only MPU at the moment) */ |