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authorThierry Reding <treding@nvidia.com>2015-01-09 05:15:33 -0500
committerThierry Reding <treding@nvidia.com>2015-01-09 10:14:53 -0500
commita9a40a4a58bac4ff92d0c7e5aa82043074533a6a (patch)
tree59a3babf68a3c30fd1d74ccd7989782179aaa6f8
parent9b07eb0537fb5f4d5fed1c2466febf59170f2b2e (diff)
soc/tegra: pmc: Add Tegra132 support
Tegra132 uses the same GPU as Tegra124 and therefore requires the same method to remove clamps. However Tegra132 has a separate chip ID, so in order to avoid having to extend the list of chip IDs for the special case, add a feature flag to the SoC data. Reviewed-by: Paul Walmsley <pwalmsley@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
-rw-r--r--drivers/soc/tegra/pmc.c14
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
index 4bdc654bd747..0f096e76574a 100644
--- a/drivers/soc/tegra/pmc.c
+++ b/drivers/soc/tegra/pmc.c
@@ -88,6 +88,8 @@ struct tegra_pmc_soc {
88 const char *const *powergates; 88 const char *const *powergates;
89 unsigned int num_cpu_powergates; 89 unsigned int num_cpu_powergates;
90 const u8 *cpu_powergates; 90 const u8 *cpu_powergates;
91
92 bool has_gpu_clamps;
91}; 93};
92 94
93/** 95/**
@@ -225,11 +227,11 @@ int tegra_powergate_remove_clamping(int id)
225 return -EINVAL; 227 return -EINVAL;
226 228
227 /* 229 /*
228 * The Tegra124 GPU has a separate register (with different semantics) 230 * On Tegra124 and later, the clamps for the GPU are controlled by a
229 * to remove clamps. 231 * separate register (with different semantics).
230 */ 232 */
231 if (tegra_get_chip_id() == TEGRA124) { 233 if (id == TEGRA_POWERGATE_3D) {
232 if (id == TEGRA_POWERGATE_3D) { 234 if (pmc->soc->has_gpu_clamps) {
233 tegra_pmc_writel(0, GPU_RG_CNTRL); 235 tegra_pmc_writel(0, GPU_RG_CNTRL);
234 return 0; 236 return 0;
235 } 237 }
@@ -773,6 +775,7 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = {
773 .powergates = tegra20_powergates, 775 .powergates = tegra20_powergates,
774 .num_cpu_powergates = 0, 776 .num_cpu_powergates = 0,
775 .cpu_powergates = NULL, 777 .cpu_powergates = NULL,
778 .has_gpu_clamps = false,
776}; 779};
777 780
778static const char * const tegra30_powergates[] = { 781static const char * const tegra30_powergates[] = {
@@ -804,6 +807,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = {
804 .powergates = tegra30_powergates, 807 .powergates = tegra30_powergates,
805 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates), 808 .num_cpu_powergates = ARRAY_SIZE(tegra30_cpu_powergates),
806 .cpu_powergates = tegra30_cpu_powergates, 809 .cpu_powergates = tegra30_cpu_powergates,
810 .has_gpu_clamps = false,
807}; 811};
808 812
809static const char * const tegra114_powergates[] = { 813static const char * const tegra114_powergates[] = {
@@ -839,6 +843,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = {
839 .powergates = tegra114_powergates, 843 .powergates = tegra114_powergates,
840 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates), 844 .num_cpu_powergates = ARRAY_SIZE(tegra114_cpu_powergates),
841 .cpu_powergates = tegra114_cpu_powergates, 845 .cpu_powergates = tegra114_cpu_powergates,
846 .has_gpu_clamps = false,
842}; 847};
843 848
844static const char * const tegra124_powergates[] = { 849static const char * const tegra124_powergates[] = {
@@ -880,6 +885,7 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = {
880 .powergates = tegra124_powergates, 885 .powergates = tegra124_powergates,
881 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates), 886 .num_cpu_powergates = ARRAY_SIZE(tegra124_cpu_powergates),
882 .cpu_powergates = tegra124_cpu_powergates, 887 .cpu_powergates = tegra124_cpu_powergates,
888 .has_gpu_clamps = true,
883}; 889};
884 890
885static const struct of_device_id tegra_pmc_match[] = { 891static const struct of_device_id tegra_pmc_match[] = {