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authorAlan Stern <stern@rowland.harvard.edu>2012-06-25 12:19:03 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-06-26 22:42:11 -0400
commita46af4ebf9ffec35eea0390e89935197b833dc61 (patch)
treec349a8e2e75b334a41cb379d5dc7744a25f5e9c6
parentcf61fdb944534ffa84a824bb8c31a3826cdc169d (diff)
USB: EHCI: define extension registers like normal ones
This patch (as1562) cleans up the definitions of the EHCI extended registers to be consistent with the definitions of the standard registers. This makes the code look a lot nicer, with no functional change. Signed-off-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/usb/host/ehci-hcd.c15
-rw-r--r--drivers/usb/host/ehci-hub.c26
-rw-r--r--include/linux/usb/ehci_def.h28
3 files changed, 34 insertions, 35 deletions
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 800be38c78b4..c49fc1e7895d 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -203,11 +203,9 @@ static int handshake (struct ehci_hcd *ehci, void __iomem *ptr,
203/* check TDI/ARC silicon is in host mode */ 203/* check TDI/ARC silicon is in host mode */
204static int tdi_in_host_mode (struct ehci_hcd *ehci) 204static int tdi_in_host_mode (struct ehci_hcd *ehci)
205{ 205{
206 u32 __iomem *reg_ptr;
207 u32 tmp; 206 u32 tmp;
208 207
209 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 208 tmp = ehci_readl(ehci, &ehci->regs->usbmode);
210 tmp = ehci_readl(ehci, reg_ptr);
211 return (tmp & 3) == USBMODE_CM_HC; 209 return (tmp & 3) == USBMODE_CM_HC;
212} 210}
213 211
@@ -303,11 +301,9 @@ static int handshake_on_error_set_halt(struct ehci_hcd *ehci, void __iomem *ptr,
303/* put TDI/ARC silicon into EHCI mode */ 301/* put TDI/ARC silicon into EHCI mode */
304static void tdi_reset (struct ehci_hcd *ehci) 302static void tdi_reset (struct ehci_hcd *ehci)
305{ 303{
306 u32 __iomem *reg_ptr;
307 u32 tmp; 304 u32 tmp;
308 305
309 reg_ptr = (u32 __iomem *)(((u8 __iomem *)ehci->regs) + USBMODE); 306 tmp = ehci_readl(ehci, &ehci->regs->usbmode);
310 tmp = ehci_readl(ehci, reg_ptr);
311 tmp |= USBMODE_CM_HC; 307 tmp |= USBMODE_CM_HC;
312 /* The default byte access to MMR space is LE after 308 /* The default byte access to MMR space is LE after
313 * controller reset. Set the required endian mode 309 * controller reset. Set the required endian mode
@@ -315,7 +311,7 @@ static void tdi_reset (struct ehci_hcd *ehci)
315 */ 311 */
316 if (ehci_big_endian_mmio(ehci)) 312 if (ehci_big_endian_mmio(ehci))
317 tmp |= USBMODE_BE; 313 tmp |= USBMODE_BE;
318 ehci_writel(ehci, tmp, reg_ptr); 314 ehci_writel(ehci, tmp, &ehci->regs->usbmode);
319} 315}
320 316
321/* reset a non-running (STS_HALT == 1) controller */ 317/* reset a non-running (STS_HALT == 1) controller */
@@ -339,9 +335,8 @@ static int ehci_reset (struct ehci_hcd *ehci)
339 335
340 if (ehci->has_hostpc) { 336 if (ehci->has_hostpc) {
341 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS, 337 ehci_writel(ehci, USBMODE_EX_HC | USBMODE_EX_VBPS,
342 (u32 __iomem *)(((u8 *)ehci->regs) + USBMODE_EX)); 338 &ehci->regs->usbmode_ex);
343 ehci_writel(ehci, TXFIFO_DEFAULT, 339 ehci_writel(ehci, TXFIFO_DEFAULT, &ehci->regs->txfill_tuning);
344 (u32 __iomem *)(((u8 *)ehci->regs) + TXFILLTUNING));
345 } 340 }
346 if (retval) 341 if (retval)
347 return retval; 342 return retval;
diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c
index dd5eef6af6df..db05e358677a 100644
--- a/drivers/usb/host/ehci-hub.c
+++ b/drivers/usb/host/ehci-hub.c
@@ -149,10 +149,8 @@ static __maybe_unused void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
149 if (ehci->has_hostpc) { 149 if (ehci->has_hostpc) {
150 port = HCS_N_PORTS(ehci->hcs_params); 150 port = HCS_N_PORTS(ehci->hcs_params);
151 while (port--) { 151 while (port--) {
152 u32 __iomem *hostpc_reg; 152 u32 __iomem *hostpc_reg = &ehci->regs->hostpc[port];
153 153
154 hostpc_reg = (u32 __iomem *)((u8 *) ehci->regs
155 + HOSTPC0 + 4 * port);
156 temp = ehci_readl(ehci, hostpc_reg); 154 temp = ehci_readl(ehci, hostpc_reg);
157 ehci_writel(ehci, temp & ~HOSTPC_PHCD, hostpc_reg); 155 ehci_writel(ehci, temp & ~HOSTPC_PHCD, hostpc_reg);
158 } 156 }
@@ -185,10 +183,8 @@ static __maybe_unused void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
185 if (ehci->has_hostpc) { 183 if (ehci->has_hostpc) {
186 port = HCS_N_PORTS(ehci->hcs_params); 184 port = HCS_N_PORTS(ehci->hcs_params);
187 while (port--) { 185 while (port--) {
188 u32 __iomem *hostpc_reg; 186 u32 __iomem *hostpc_reg = &ehci->regs->hostpc[port];
189 187
190 hostpc_reg = (u32 __iomem *)((u8 *) ehci->regs
191 + HOSTPC0 + 4 * port);
192 temp = ehci_readl(ehci, hostpc_reg); 188 temp = ehci_readl(ehci, hostpc_reg);
193 ehci_writel(ehci, temp | HOSTPC_PHCD, hostpc_reg); 189 ehci_writel(ehci, temp | HOSTPC_PHCD, hostpc_reg);
194 } 190 }
@@ -285,11 +281,9 @@ static int ehci_bus_suspend (struct usb_hcd *hcd)
285 281
286 port = HCS_N_PORTS(ehci->hcs_params); 282 port = HCS_N_PORTS(ehci->hcs_params);
287 while (port--) { 283 while (port--) {
288 u32 __iomem *hostpc_reg; 284 u32 __iomem *hostpc_reg = &ehci->regs->hostpc[port];
289 u32 t3; 285 u32 t3;
290 286
291 hostpc_reg = (u32 __iomem *)((u8 *) ehci->regs
292 + HOSTPC0 + 4 * port);
293 t3 = ehci_readl(ehci, hostpc_reg); 287 t3 = ehci_readl(ehci, hostpc_reg);
294 ehci_writel(ehci, t3 | HOSTPC_PHCD, hostpc_reg); 288 ehci_writel(ehci, t3 | HOSTPC_PHCD, hostpc_reg);
295 t3 = ehci_readl(ehci, hostpc_reg); 289 t3 = ehci_readl(ehci, hostpc_reg);
@@ -388,10 +382,9 @@ static int ehci_bus_resume (struct usb_hcd *hcd)
388 i = HCS_N_PORTS(ehci->hcs_params); 382 i = HCS_N_PORTS(ehci->hcs_params);
389 while (i--) { 383 while (i--) {
390 if (test_bit(i, &ehci->bus_suspended)) { 384 if (test_bit(i, &ehci->bus_suspended)) {
391 u32 __iomem *hostpc_reg; 385 u32 __iomem *hostpc_reg =
386 &ehci->regs->hostpc[i];
392 387
393 hostpc_reg = (u32 __iomem *)((u8 *) ehci->regs
394 + HOSTPC0 + 4 * i);
395 temp = ehci_readl(ehci, hostpc_reg); 388 temp = ehci_readl(ehci, hostpc_reg);
396 ehci_writel(ehci, temp & ~HOSTPC_PHCD, 389 ehci_writel(ehci, temp & ~HOSTPC_PHCD,
397 hostpc_reg); 390 hostpc_reg);
@@ -667,7 +660,7 @@ static int ehci_hub_control (
667 int ports = HCS_N_PORTS (ehci->hcs_params); 660 int ports = HCS_N_PORTS (ehci->hcs_params);
668 u32 __iomem *status_reg = &ehci->regs->port_status[ 661 u32 __iomem *status_reg = &ehci->regs->port_status[
669 (wIndex & 0xff) - 1]; 662 (wIndex & 0xff) - 1];
670 u32 __iomem *hostpc_reg = NULL; 663 u32 __iomem *hostpc_reg = &ehci->regs->hostpc[(wIndex & 0xff) - 1];
671 u32 temp, temp1, status; 664 u32 temp, temp1, status;
672 unsigned long flags; 665 unsigned long flags;
673 int retval = 0; 666 int retval = 0;
@@ -680,9 +673,6 @@ static int ehci_hub_control (
680 * power, "this is the one", etc. EHCI spec supports this. 673 * power, "this is the one", etc. EHCI spec supports this.
681 */ 674 */
682 675
683 if (ehci->has_hostpc)
684 hostpc_reg = (u32 __iomem *)((u8 *)ehci->regs
685 + HOSTPC0 + 4 * ((wIndex & 0xff) - 1));
686 spin_lock_irqsave (&ehci->lock, flags); 676 spin_lock_irqsave (&ehci->lock, flags);
687 switch (typeReq) { 677 switch (typeReq) {
688 case ClearHubFeature: 678 case ClearHubFeature:
@@ -734,7 +724,7 @@ static int ehci_hub_control (
734 goto error; 724 goto error;
735 725
736 /* clear phy low-power mode before resume */ 726 /* clear phy low-power mode before resume */
737 if (hostpc_reg) { 727 if (ehci->has_hostpc) {
738 temp1 = ehci_readl(ehci, hostpc_reg); 728 temp1 = ehci_readl(ehci, hostpc_reg);
739 ehci_writel(ehci, temp1 & ~HOSTPC_PHCD, 729 ehci_writel(ehci, temp1 & ~HOSTPC_PHCD,
740 hostpc_reg); 730 hostpc_reg);
@@ -984,7 +974,7 @@ static int ehci_hub_control (
984 temp &= ~PORT_WKCONN_E; 974 temp &= ~PORT_WKCONN_E;
985 temp |= PORT_WKDISC_E | PORT_WKOC_E; 975 temp |= PORT_WKDISC_E | PORT_WKOC_E;
986 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg); 976 ehci_writel(ehci, temp | PORT_SUSPEND, status_reg);
987 if (hostpc_reg) { 977 if (ehci->has_hostpc) {
988 spin_unlock_irqrestore(&ehci->lock, flags); 978 spin_unlock_irqrestore(&ehci->lock, flags);
989 msleep(5);/* 5ms for HCD enter low pwr mode */ 979 msleep(5);/* 5ms for HCD enter low pwr mode */
990 spin_lock_irqsave(&ehci->lock, flags); 980 spin_lock_irqsave(&ehci->lock, flags);
diff --git a/include/linux/usb/ehci_def.h b/include/linux/usb/ehci_def.h
index 7cc95ee3606b..de4b9ed5d5dd 100644
--- a/include/linux/usb/ehci_def.h
+++ b/include/linux/usb/ehci_def.h
@@ -111,7 +111,13 @@ struct ehci_regs {
111 /* ASYNCLISTADDR: offset 0x18 */ 111 /* ASYNCLISTADDR: offset 0x18 */
112 u32 async_next; /* address of next async queue head */ 112 u32 async_next; /* address of next async queue head */
113 113
114 u32 reserved[9]; 114 u32 reserved1[2];
115
116 /* TXFILLTUNING: offset 0x24 */
117 u32 txfill_tuning; /* TX FIFO Tuning register */
118#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */
119
120 u32 reserved2[6];
115 121
116 /* CONFIGFLAG: offset 0x40 */ 122 /* CONFIGFLAG: offset 0x40 */
117 u32 configured_flag; 123 u32 configured_flag;
@@ -155,26 +161,34 @@ struct ehci_regs {
155#define PORT_CSC (1<<1) /* connect status change */ 161#define PORT_CSC (1<<1) /* connect status change */
156#define PORT_CONNECT (1<<0) /* device connected */ 162#define PORT_CONNECT (1<<0) /* device connected */
157#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) 163#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
158};
159 164
160#define USBMODE 0x68 /* USB Device mode */ 165 u32 reserved3[9];
166
167 /* USBMODE: offset 0x68 */
168 u32 usbmode; /* USB Device mode */
161#define USBMODE_SDIS (1<<3) /* Stream disable */ 169#define USBMODE_SDIS (1<<3) /* Stream disable */
162#define USBMODE_BE (1<<2) /* BE/LE endianness select */ 170#define USBMODE_BE (1<<2) /* BE/LE endianness select */
163#define USBMODE_CM_HC (3<<0) /* host controller mode */ 171#define USBMODE_CM_HC (3<<0) /* host controller mode */
164#define USBMODE_CM_IDLE (0<<0) /* idle state */ 172#define USBMODE_CM_IDLE (0<<0) /* idle state */
165 173
174 u32 reserved4[7];
175
166/* Moorestown has some non-standard registers, partially due to the fact that 176/* Moorestown has some non-standard registers, partially due to the fact that
167 * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to 177 * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to
168 * PORTSCx 178 * PORTSCx
169 */ 179 */
170#define HOSTPC0 0x84 /* HOSTPC extension */ 180 /* HOSTPC: offset 0x84 */
181 u32 hostpc[0]; /* HOSTPC extension */
171#define HOSTPC_PHCD (1<<22) /* Phy clock disable */ 182#define HOSTPC_PHCD (1<<22) /* Phy clock disable */
172#define HOSTPC_PSPD (3<<25) /* Port speed detection */ 183#define HOSTPC_PSPD (3<<25) /* Port speed detection */
173#define USBMODE_EX 0xc8 /* USB Device mode extension */ 184
185 u32 reserved5[17];
186
187 /* USBMODE_EX: offset 0xc8 */
188 u32 usbmode_ex; /* USB Device mode extension */
174#define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */ 189#define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */
175#define USBMODE_EX_HC (3<<0) /* host controller mode */ 190#define USBMODE_EX_HC (3<<0) /* host controller mode */
176#define TXFILLTUNING 0x24 /* TX FIFO Tuning register */ 191};
177#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */
178 192
179/* Appendix C, Debug port ... intended for use with special "debug devices" 193/* Appendix C, Debug port ... intended for use with special "debug devices"
180 * that can help if there's no serial console. (nonstandard enumeration.) 194 * that can help if there's no serial console. (nonstandard enumeration.)