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authorDmitry Eremin-Solenikov <dbaryshkov@gmail.com>2015-01-14 20:32:26 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2015-01-29 10:24:49 -0500
commita0ea298d325616b58760c5182705df76912e0d73 (patch)
tree8f3c76cb949ff98edfcf097d9650c1c102bd6d1d
parenta82be3f0f1a4a03ec43750b12cb48871ec2a2e28 (diff)
ARM: 8281/1: sa1100: move GPIO-related IRQ code to gpio driver
As a part of driver consolidation, move GPIO-related IRQ code to drivers/gpio/gpio-sa1100.c. The code does not use GPIOLIB_IRQCHIP (yet), because sa1100 does not have a device for gpios, which is a requirement for GPIOLIB_IRQCHIP. This will be the next step. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Tested-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat
-rw-r--r--arch/arm/mach-sa1100/irq.c174
-rw-r--r--drivers/gpio/gpio-sa1100.c197
2 files changed, 197 insertions, 174 deletions
diff --git a/arch/arm/mach-sa1100/irq.c b/arch/arm/mach-sa1100/irq.c
index a9dfe8e16d95..a7d116af4a4f 100644
--- a/arch/arm/mach-sa1100/irq.c
+++ b/arch/arm/mach-sa1100/irq.c
@@ -80,138 +80,6 @@ static struct irq_domain_ops sa1100_normal_irqdomain_ops = {
80 80
81static struct irq_domain *sa1100_normal_irqdomain; 81static struct irq_domain *sa1100_normal_irqdomain;
82 82
83/*
84 * SA1100 GPIO edge detection for IRQs:
85 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
86 * Use this instead of directly setting GRER/GFER.
87 */
88static int GPIO_IRQ_rising_edge;
89static int GPIO_IRQ_falling_edge;
90static int GPIO_IRQ_mask;
91
92static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
93{
94 unsigned int mask;
95
96 mask = BIT(d->hwirq);
97
98 if (type == IRQ_TYPE_PROBE) {
99 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
100 return 0;
101 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
102 }
103
104 if (type & IRQ_TYPE_EDGE_RISING) {
105 GPIO_IRQ_rising_edge |= mask;
106 } else
107 GPIO_IRQ_rising_edge &= ~mask;
108 if (type & IRQ_TYPE_EDGE_FALLING) {
109 GPIO_IRQ_falling_edge |= mask;
110 } else
111 GPIO_IRQ_falling_edge &= ~mask;
112
113 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
114 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
115
116 return 0;
117}
118
119/*
120 * GPIO IRQs must be acknowledged.
121 */
122static void sa1100_gpio_ack(struct irq_data *d)
123{
124 GEDR = BIT(d->hwirq);
125}
126
127static void sa1100_gpio_mask(struct irq_data *d)
128{
129 unsigned int mask = BIT(d->hwirq);
130
131 GPIO_IRQ_mask &= ~mask;
132
133 GRER &= ~mask;
134 GFER &= ~mask;
135}
136
137static void sa1100_gpio_unmask(struct irq_data *d)
138{
139 unsigned int mask = BIT(d->hwirq);
140
141 GPIO_IRQ_mask |= mask;
142
143 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
144 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
145}
146
147static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
148{
149 if (on)
150 PWER |= BIT(d->hwirq);
151 else
152 PWER &= ~BIT(d->hwirq);
153 return 0;
154}
155
156/*
157 * This is for GPIO IRQs
158 */
159static struct irq_chip sa1100_gpio_chip = {
160 .name = "GPIO",
161 .irq_ack = sa1100_gpio_ack,
162 .irq_mask = sa1100_gpio_mask,
163 .irq_unmask = sa1100_gpio_unmask,
164 .irq_set_type = sa1100_gpio_type,
165 .irq_set_wake = sa1100_gpio_wake,
166};
167
168static int sa1100_gpio_irqdomain_map(struct irq_domain *d,
169 unsigned int irq, irq_hw_number_t hwirq)
170{
171 irq_set_chip_and_handler(irq, &sa1100_gpio_chip,
172 handle_edge_irq);
173 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
174
175 return 0;
176}
177
178static struct irq_domain_ops sa1100_gpio_irqdomain_ops = {
179 .map = sa1100_gpio_irqdomain_map,
180 .xlate = irq_domain_xlate_onetwocell,
181};
182
183static struct irq_domain *sa1100_gpio_irqdomain;
184
185/*
186 * IRQ 0-11 (GPIO) handler. We enter here with the
187 * irq_controller_lock held, and IRQs disabled. Decode the IRQ
188 * and call the handler.
189 */
190static void
191sa1100_gpio_handler(unsigned int irq, struct irq_desc *desc)
192{
193 unsigned int mask;
194
195 mask = GEDR;
196 do {
197 /*
198 * clear down all currently active IRQ sources.
199 * We will be processing them all.
200 */
201 GEDR = mask;
202
203 irq = IRQ_GPIO0;
204 do {
205 if (mask & 1)
206 generic_handle_irq(irq);
207 mask >>= 1;
208 irq++;
209 } while (mask);
210
211 mask = GEDR;
212 } while (mask);
213}
214
215static struct resource irq_resource = 83static struct resource irq_resource =
216 DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs"); 84 DEFINE_RES_MEM_NAMED(0x90050000, SZ_64K, "irqs");
217 85
@@ -238,17 +106,6 @@ static int sa1100irq_suspend(void)
238 IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2| 106 IC_GPIO6|IC_GPIO5|IC_GPIO4|IC_GPIO3|IC_GPIO2|
239 IC_GPIO1|IC_GPIO0); 107 IC_GPIO1|IC_GPIO0);
240 108
241 /*
242 * Set the appropriate edges for wakeup.
243 */
244 GRER = PWER & GPIO_IRQ_rising_edge;
245 GFER = PWER & GPIO_IRQ_falling_edge;
246
247 /*
248 * Clear any pending GPIO interrupts.
249 */
250 GEDR = GEDR;
251
252 return 0; 109 return 0;
253} 110}
254 111
@@ -260,9 +117,6 @@ static void sa1100irq_resume(void)
260 ICCR = st->iccr; 117 ICCR = st->iccr;
261 ICLR = st->iclr; 118 ICLR = st->iclr;
262 119
263 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
264 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
265
266 ICMR = st->icmr; 120 ICMR = st->icmr;
267 } 121 }
268} 122}
@@ -307,11 +161,6 @@ void __init sa1100_init_irq(void)
307 /* all IRQs are IRQ, not FIQ */ 161 /* all IRQs are IRQ, not FIQ */
308 ICLR = 0; 162 ICLR = 0;
309 163
310 /* clear all GPIO edge detects */
311 GFER = 0;
312 GRER = 0;
313 GEDR = -1;
314
315 /* 164 /*
316 * Whatever the doc says, this has to be set for the wait-on-irq 165 * Whatever the doc says, this has to be set for the wait-on-irq
317 * instruction to work... on a SA1100 rev 9 at least. 166 * instruction to work... on a SA1100 rev 9 at least.
@@ -322,29 +171,6 @@ void __init sa1100_init_irq(void)
322 32, IRQ_GPIO0_SC, 171 32, IRQ_GPIO0_SC,
323 &sa1100_normal_irqdomain_ops, NULL); 172 &sa1100_normal_irqdomain_ops, NULL);
324 173
325 sa1100_gpio_irqdomain = irq_domain_add_simple(NULL,
326 28, IRQ_GPIO0,
327 &sa1100_gpio_irqdomain_ops, NULL);
328
329 /*
330 * Install handlers for GPIO 0-10 edge detect interrupts
331 */
332 irq_set_chained_handler(IRQ_GPIO0_SC, sa1100_gpio_handler);
333 irq_set_chained_handler(IRQ_GPIO1_SC, sa1100_gpio_handler);
334 irq_set_chained_handler(IRQ_GPIO2_SC, sa1100_gpio_handler);
335 irq_set_chained_handler(IRQ_GPIO3_SC, sa1100_gpio_handler);
336 irq_set_chained_handler(IRQ_GPIO4_SC, sa1100_gpio_handler);
337 irq_set_chained_handler(IRQ_GPIO5_SC, sa1100_gpio_handler);
338 irq_set_chained_handler(IRQ_GPIO6_SC, sa1100_gpio_handler);
339 irq_set_chained_handler(IRQ_GPIO7_SC, sa1100_gpio_handler);
340 irq_set_chained_handler(IRQ_GPIO8_SC, sa1100_gpio_handler);
341 irq_set_chained_handler(IRQ_GPIO9_SC, sa1100_gpio_handler);
342 irq_set_chained_handler(IRQ_GPIO10_SC, sa1100_gpio_handler);
343 /*
344 * Install handler for GPIO 11-27 edge detect interrupts
345 */
346 irq_set_chained_handler(IRQ_GPIO11_27, sa1100_gpio_handler);
347
348 set_handle_irq(sa1100_handle_irq); 174 set_handle_irq(sa1100_handle_irq);
349 175
350 sa1100_init_gpio(); 176 sa1100_init_gpio();
diff --git a/drivers/gpio/gpio-sa1100.c b/drivers/gpio/gpio-sa1100.c
index 5b5d3c7bb84e..bec397a60204 100644
--- a/drivers/gpio/gpio-sa1100.c
+++ b/drivers/gpio/gpio-sa1100.c
@@ -11,6 +11,7 @@
11#include <linux/init.h> 11#include <linux/init.h>
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/syscore_ops.h>
14#include <mach/hardware.h> 15#include <mach/hardware.h>
15#include <mach/irqs.h> 16#include <mach/irqs.h>
16 17
@@ -64,7 +65,203 @@ static struct gpio_chip sa1100_gpio_chip = {
64 .ngpio = GPIO_MAX + 1, 65 .ngpio = GPIO_MAX + 1,
65}; 66};
66 67
68/*
69 * SA1100 GPIO edge detection for IRQs:
70 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
71 * Use this instead of directly setting GRER/GFER.
72 */
73static int GPIO_IRQ_rising_edge;
74static int GPIO_IRQ_falling_edge;
75static int GPIO_IRQ_mask;
76
77static int sa1100_gpio_type(struct irq_data *d, unsigned int type)
78{
79 unsigned int mask;
80
81 mask = BIT(d->hwirq);
82
83 if (type == IRQ_TYPE_PROBE) {
84 if ((GPIO_IRQ_rising_edge | GPIO_IRQ_falling_edge) & mask)
85 return 0;
86 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
87 }
88
89 if (type & IRQ_TYPE_EDGE_RISING)
90 GPIO_IRQ_rising_edge |= mask;
91 else
92 GPIO_IRQ_rising_edge &= ~mask;
93 if (type & IRQ_TYPE_EDGE_FALLING)
94 GPIO_IRQ_falling_edge |= mask;
95 else
96 GPIO_IRQ_falling_edge &= ~mask;
97
98 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
99 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
100
101 return 0;
102}
103
104/*
105 * GPIO IRQs must be acknowledged.
106 */
107static void sa1100_gpio_ack(struct irq_data *d)
108{
109 GEDR = BIT(d->hwirq);
110}
111
112static void sa1100_gpio_mask(struct irq_data *d)
113{
114 unsigned int mask = BIT(d->hwirq);
115
116 GPIO_IRQ_mask &= ~mask;
117
118 GRER &= ~mask;
119 GFER &= ~mask;
120}
121
122static void sa1100_gpio_unmask(struct irq_data *d)
123{
124 unsigned int mask = BIT(d->hwirq);
125
126 GPIO_IRQ_mask |= mask;
127
128 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
129 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
130}
131
132static int sa1100_gpio_wake(struct irq_data *d, unsigned int on)
133{
134 if (on)
135 PWER |= BIT(d->hwirq);
136 else
137 PWER &= ~BIT(d->hwirq);
138 return 0;
139}
140
141/*
142 * This is for GPIO IRQs
143 */
144static struct irq_chip sa1100_gpio_irq_chip = {
145 .name = "GPIO",
146 .irq_ack = sa1100_gpio_ack,
147 .irq_mask = sa1100_gpio_mask,
148 .irq_unmask = sa1100_gpio_unmask,
149 .irq_set_type = sa1100_gpio_type,
150 .irq_set_wake = sa1100_gpio_wake,
151};
152
153static int sa1100_gpio_irqdomain_map(struct irq_domain *d,
154 unsigned int irq, irq_hw_number_t hwirq)
155{
156 irq_set_chip_and_handler(irq, &sa1100_gpio_irq_chip,
157 handle_edge_irq);
158 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
159
160 return 0;
161}
162
163static struct irq_domain_ops sa1100_gpio_irqdomain_ops = {
164 .map = sa1100_gpio_irqdomain_map,
165 .xlate = irq_domain_xlate_onetwocell,
166};
167
168static struct irq_domain *sa1100_gpio_irqdomain;
169
170/*
171 * IRQ 0-11 (GPIO) handler. We enter here with the
172 * irq_controller_lock held, and IRQs disabled. Decode the IRQ
173 * and call the handler.
174 */
175static void
176sa1100_gpio_handler(unsigned int irq, struct irq_desc *desc)
177{
178 unsigned int mask;
179
180 mask = GEDR;
181 do {
182 /*
183 * clear down all currently active IRQ sources.
184 * We will be processing them all.
185 */
186 GEDR = mask;
187
188 irq = IRQ_GPIO0;
189 do {
190 if (mask & 1)
191 generic_handle_irq(irq);
192 mask >>= 1;
193 irq++;
194 } while (mask);
195
196 mask = GEDR;
197 } while (mask);
198}
199
200static int sa1100_gpio_suspend(void)
201{
202 /*
203 * Set the appropriate edges for wakeup.
204 */
205 GRER = PWER & GPIO_IRQ_rising_edge;
206 GFER = PWER & GPIO_IRQ_falling_edge;
207
208 /*
209 * Clear any pending GPIO interrupts.
210 */
211 GEDR = GEDR;
212
213 return 0;
214}
215
216static void sa1100_gpio_resume(void)
217{
218 GRER = GPIO_IRQ_rising_edge & GPIO_IRQ_mask;
219 GFER = GPIO_IRQ_falling_edge & GPIO_IRQ_mask;
220}
221
222static struct syscore_ops sa1100_gpio_syscore_ops = {
223 .suspend = sa1100_gpio_suspend,
224 .resume = sa1100_gpio_resume,
225};
226
227static int __init sa1100_gpio_init_devicefs(void)
228{
229 register_syscore_ops(&sa1100_gpio_syscore_ops);
230 return 0;
231}
232
233device_initcall(sa1100_gpio_init_devicefs);
234
67void __init sa1100_init_gpio(void) 235void __init sa1100_init_gpio(void)
68{ 236{
237 /* clear all GPIO edge detects */
238 GFER = 0;
239 GRER = 0;
240 GEDR = -1;
241
69 gpiochip_add(&sa1100_gpio_chip); 242 gpiochip_add(&sa1100_gpio_chip);
243
244 sa1100_gpio_irqdomain = irq_domain_add_simple(NULL,
245 28, IRQ_GPIO0,
246 &sa1100_gpio_irqdomain_ops, NULL);
247
248 /*
249 * Install handlers for GPIO 0-10 edge detect interrupts
250 */
251 irq_set_chained_handler(IRQ_GPIO0_SC, sa1100_gpio_handler);
252 irq_set_chained_handler(IRQ_GPIO1_SC, sa1100_gpio_handler);
253 irq_set_chained_handler(IRQ_GPIO2_SC, sa1100_gpio_handler);
254 irq_set_chained_handler(IRQ_GPIO3_SC, sa1100_gpio_handler);
255 irq_set_chained_handler(IRQ_GPIO4_SC, sa1100_gpio_handler);
256 irq_set_chained_handler(IRQ_GPIO5_SC, sa1100_gpio_handler);
257 irq_set_chained_handler(IRQ_GPIO6_SC, sa1100_gpio_handler);
258 irq_set_chained_handler(IRQ_GPIO7_SC, sa1100_gpio_handler);
259 irq_set_chained_handler(IRQ_GPIO8_SC, sa1100_gpio_handler);
260 irq_set_chained_handler(IRQ_GPIO9_SC, sa1100_gpio_handler);
261 irq_set_chained_handler(IRQ_GPIO10_SC, sa1100_gpio_handler);
262 /*
263 * Install handler for GPIO 11-27 edge detect interrupts
264 */
265 irq_set_chained_handler(IRQ_GPIO11_27, sa1100_gpio_handler);
266
70} 267}
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