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authorJonghwan Choi <jhbird.choi@samsung.com>2012-12-23 18:57:42 -0500
committerKukjin Kim <kgene.kim@samsung.com>2012-12-23 18:57:42 -0500
commit9d0554fff9a21d846adcfbd14cfb02e82773162c (patch)
tree98926538dc47a6e4025c70a65c5493f60ec19a97
parent857d90f7014f4fe0acc49947ad5309174111a4e8 (diff)
cpufreq: exynos: Use APLL_FREQ macro for cpu divider value
Signed-off-by: Jonghwan Choi <jhbird.choi@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat
-rw-r--r--arch/arm/mach-exynos/include/mach/cpufreq.h16
-rw-r--r--drivers/cpufreq/exynos4210-cpufreq.c135
-rw-r--r--drivers/cpufreq/exynos4x12-cpufreq.c378
-rw-r--r--drivers/cpufreq/exynos5250-cpufreq.c168
4 files changed, 136 insertions, 561 deletions
diff --git a/arch/arm/mach-exynos/include/mach/cpufreq.h b/arch/arm/mach-exynos/include/mach/cpufreq.h
index 39f0dc62122b..b5d39dd03b2a 100644
--- a/arch/arm/mach-exynos/include/mach/cpufreq.h
+++ b/arch/arm/mach-exynos/include/mach/cpufreq.h
@@ -18,6 +18,22 @@ enum cpufreq_level_index {
18 L20, 18 L20,
19}; 19};
20 20
21#define APLL_FREQ(f, a0, a1, a2, a3, a4, a5, a6, a7, b0, b1, b2, m, p, s) \
22 { \
23 .freq = (f) * 1000, \
24 .clk_div_cpu0 = ((a0) | (a1) << 4 | (a2) << 8 | (a3) << 12 | \
25 (a4) << 16 | (a5) << 20 | (a6) << 24 | (a7) << 28), \
26 .clk_div_cpu1 = (b0 << 0 | b1 << 4 | b2 << 8), \
27 .mps = ((m) << 16 | (p) << 8 | (s)), \
28 }
29
30struct apll_freq {
31 unsigned int freq;
32 u32 clk_div_cpu0;
33 u32 clk_div_cpu1;
34 u32 mps;
35};
36
21struct exynos_dvfs_info { 37struct exynos_dvfs_info {
22 unsigned long mpll_freq_khz; 38 unsigned long mpll_freq_khz;
23 unsigned int pll_safe_idx; 39 unsigned int pll_safe_idx;
diff --git a/drivers/cpufreq/exynos4210-cpufreq.c b/drivers/cpufreq/exynos4210-cpufreq.c
index 5ae5c529fca7..250dcf0c0b22 100644
--- a/drivers/cpufreq/exynos4210-cpufreq.c
+++ b/drivers/cpufreq/exynos4210-cpufreq.c
@@ -20,94 +20,37 @@
20#include <mach/regs-clock.h> 20#include <mach/regs-clock.h>
21#include <mach/cpufreq.h> 21#include <mach/cpufreq.h>
22 22
23#define CPUFREQ_LEVEL_END L5
24
25static struct clk *cpu_clk; 23static struct clk *cpu_clk;
26static struct clk *moutcore; 24static struct clk *moutcore;
27static struct clk *mout_mpll; 25static struct clk *mout_mpll;
28static struct clk *mout_apll; 26static struct clk *mout_apll;
29 27
30struct cpufreq_clkdiv { 28static unsigned int exynos4210_volt_table[] = {
31 unsigned int index;
32 unsigned int clkdiv;
33};
34
35static unsigned int exynos4210_volt_table[CPUFREQ_LEVEL_END] = {
36 1250000, 1150000, 1050000, 975000, 950000, 29 1250000, 1150000, 1050000, 975000, 950000,
37}; 30};
38 31
39
40static struct cpufreq_clkdiv exynos4210_clkdiv_table[CPUFREQ_LEVEL_END];
41
42static struct cpufreq_frequency_table exynos4210_freq_table[] = { 32static struct cpufreq_frequency_table exynos4210_freq_table[] = {
43 {L0, 1200*1000}, 33 {L0, 1200 * 1000},
44 {L1, 1000*1000}, 34 {L1, 1000 * 1000},
45 {L2, 800*1000}, 35 {L2, 800 * 1000},
46 {L3, 500*1000}, 36 {L3, 500 * 1000},
47 {L4, 200*1000}, 37 {L4, 200 * 1000},
48 {0, CPUFREQ_TABLE_END}, 38 {0, CPUFREQ_TABLE_END},
49}; 39};
50 40
51static unsigned int clkdiv_cpu0[CPUFREQ_LEVEL_END][7] = { 41static struct apll_freq apll_freq_4210[] = {
52 /* 42 /*
53 * Clock divider value for following 43 * values:
54 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH, 44 * freq
55 * DIVATB, DIVPCLK_DBG, DIVAPLL } 45 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, RESERVED
46 * clock divider for COPY, HPM, RESERVED
47 * PLL M, P, S
56 */ 48 */
57 49 APLL_FREQ(1200, 0, 3, 7, 3, 4, 1, 7, 0, 5, 0, 0, 150, 3, 1),
58 /* ARM L0: 1200MHz */ 50 APLL_FREQ(1000, 0, 3, 7, 3, 4, 1, 7, 0, 4, 0, 0, 250, 6, 1),
59 { 0, 3, 7, 3, 4, 1, 7 }, 51 APLL_FREQ(800, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 200, 6, 1),
60 52 APLL_FREQ(500, 0, 3, 7, 3, 3, 1, 7, 0, 3, 0, 0, 250, 6, 2),
61 /* ARM L1: 1000MHz */ 53 APLL_FREQ(200, 0, 1, 3, 1, 3, 1, 0, 0, 3, 0, 0, 200, 6, 3),
62 { 0, 3, 7, 3, 4, 1, 7 },
63
64 /* ARM L2: 800MHz */
65 { 0, 3, 7, 3, 3, 1, 7 },
66
67 /* ARM L3: 500MHz */
68 { 0, 3, 7, 3, 3, 1, 7 },
69
70 /* ARM L4: 200MHz */
71 { 0, 1, 3, 1, 3, 1, 0 },
72};
73
74static unsigned int clkdiv_cpu1[CPUFREQ_LEVEL_END][2] = {
75 /*
76 * Clock divider value for following
77 * { DIVCOPY, DIVHPM }
78 */
79
80 /* ARM L0: 1200MHz */
81 { 5, 0 },
82
83 /* ARM L1: 1000MHz */
84 { 4, 0 },
85
86 /* ARM L2: 800MHz */
87 { 3, 0 },
88
89 /* ARM L3: 500MHz */
90 { 3, 0 },
91
92 /* ARM L4: 200MHz */
93 { 3, 0 },
94};
95
96static unsigned int exynos4210_apll_pms_table[CPUFREQ_LEVEL_END] = {
97 /* APLL FOUT L0: 1200MHz */
98 ((150 << 16) | (3 << 8) | 1),
99
100 /* APLL FOUT L1: 1000MHz */
101 ((250 << 16) | (6 << 8) | 1),
102
103 /* APLL FOUT L2: 800MHz */
104 ((200 << 16) | (6 << 8) | 1),
105
106 /* APLL FOUT L3: 500MHz */
107 ((250 << 16) | (6 << 8) | 2),
108
109 /* APLL FOUT L4: 200MHz */
110 ((200 << 16) | (6 << 8) | 3),
111}; 54};
112 55
113static void exynos4210_set_clkdiv(unsigned int div_index) 56static void exynos4210_set_clkdiv(unsigned int div_index)
@@ -116,7 +59,7 @@ static void exynos4210_set_clkdiv(unsigned int div_index)
116 59
117 /* Change Divider - CPU0 */ 60 /* Change Divider - CPU0 */
118 61
119 tmp = exynos4210_clkdiv_table[div_index].clkdiv; 62 tmp = apll_freq_4210[div_index].clk_div_cpu0;
120 63
121 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU); 64 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
122 65
@@ -126,12 +69,7 @@ static void exynos4210_set_clkdiv(unsigned int div_index)
126 69
127 /* Change Divider - CPU1 */ 70 /* Change Divider - CPU1 */
128 71
129 tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1); 72 tmp = apll_freq_4210[div_index].clk_div_cpu1;
130
131 tmp &= ~((0x7 << 4) | 0x7);
132
133 tmp |= ((clkdiv_cpu1[div_index][0] << 4) |
134 (clkdiv_cpu1[div_index][1] << 0));
135 73
136 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1); 74 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
137 75
@@ -159,7 +97,7 @@ static void exynos4210_set_apll(unsigned int index)
159 /* 3. Change PLL PMS values */ 97 /* 3. Change PLL PMS values */
160 tmp = __raw_readl(EXYNOS4_APLL_CON0); 98 tmp = __raw_readl(EXYNOS4_APLL_CON0);
161 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); 99 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
162 tmp |= exynos4210_apll_pms_table[index]; 100 tmp |= apll_freq_4210[index].mps;
163 __raw_writel(tmp, EXYNOS4_APLL_CON0); 101 __raw_writel(tmp, EXYNOS4_APLL_CON0);
164 102
165 /* 4. wait_lock_time */ 103 /* 4. wait_lock_time */
@@ -178,8 +116,8 @@ static void exynos4210_set_apll(unsigned int index)
178 116
179bool exynos4210_pms_change(unsigned int old_index, unsigned int new_index) 117bool exynos4210_pms_change(unsigned int old_index, unsigned int new_index)
180{ 118{
181 unsigned int old_pm = (exynos4210_apll_pms_table[old_index] >> 8); 119 unsigned int old_pm = apll_freq_4210[old_index].mps >> 8;
182 unsigned int new_pm = (exynos4210_apll_pms_table[new_index] >> 8); 120 unsigned int new_pm = apll_freq_4210[new_index].mps >> 8;
183 121
184 return (old_pm == new_pm) ? 0 : 1; 122 return (old_pm == new_pm) ? 0 : 1;
185} 123}
@@ -197,7 +135,7 @@ static void exynos4210_set_frequency(unsigned int old_index,
197 /* 2. Change just s value in apll m,p,s value */ 135 /* 2. Change just s value in apll m,p,s value */
198 tmp = __raw_readl(EXYNOS4_APLL_CON0); 136 tmp = __raw_readl(EXYNOS4_APLL_CON0);
199 tmp &= ~(0x7 << 0); 137 tmp &= ~(0x7 << 0);
200 tmp |= (exynos4210_apll_pms_table[new_index] & 0x7); 138 tmp |= apll_freq_4210[new_index].mps & 0x7;
201 __raw_writel(tmp, EXYNOS4_APLL_CON0); 139 __raw_writel(tmp, EXYNOS4_APLL_CON0);
202 } else { 140 } else {
203 /* Clock Configuration Procedure */ 141 /* Clock Configuration Procedure */
@@ -211,7 +149,7 @@ static void exynos4210_set_frequency(unsigned int old_index,
211 /* 1. Change just s value in apll m,p,s value */ 149 /* 1. Change just s value in apll m,p,s value */
212 tmp = __raw_readl(EXYNOS4_APLL_CON0); 150 tmp = __raw_readl(EXYNOS4_APLL_CON0);
213 tmp &= ~(0x7 << 0); 151 tmp &= ~(0x7 << 0);
214 tmp |= (exynos4210_apll_pms_table[new_index] & 0x7); 152 tmp |= apll_freq_4210[new_index].mps & 0x7;
215 __raw_writel(tmp, EXYNOS4_APLL_CON0); 153 __raw_writel(tmp, EXYNOS4_APLL_CON0);
216 154
217 /* 2. Change the system clock divider values */ 155 /* 2. Change the system clock divider values */
@@ -228,8 +166,6 @@ static void exynos4210_set_frequency(unsigned int old_index,
228 166
229int exynos4210_cpufreq_init(struct exynos_dvfs_info *info) 167int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
230{ 168{
231 int i;
232 unsigned int tmp;
233 unsigned long rate; 169 unsigned long rate;
234 170
235 cpu_clk = clk_get(NULL, "armclk"); 171 cpu_clk = clk_get(NULL, "armclk");
@@ -250,29 +186,8 @@ int exynos4210_cpufreq_init(struct exynos_dvfs_info *info)
250 if (IS_ERR(mout_apll)) 186 if (IS_ERR(mout_apll))
251 goto err_mout_apll; 187 goto err_mout_apll;
252 188
253 tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);
254
255 for (i = L0; i < CPUFREQ_LEVEL_END; i++) {
256 tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK |
257 EXYNOS4_CLKDIV_CPU0_COREM0_MASK |
258 EXYNOS4_CLKDIV_CPU0_COREM1_MASK |
259 EXYNOS4_CLKDIV_CPU0_PERIPH_MASK |
260 EXYNOS4_CLKDIV_CPU0_ATB_MASK |
261 EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK |
262 EXYNOS4_CLKDIV_CPU0_APLL_MASK);
263
264 tmp |= ((clkdiv_cpu0[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
265 (clkdiv_cpu0[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
266 (clkdiv_cpu0[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
267 (clkdiv_cpu0[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
268 (clkdiv_cpu0[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
269 (clkdiv_cpu0[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
270 (clkdiv_cpu0[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT));
271
272 exynos4210_clkdiv_table[i].clkdiv = tmp;
273 }
274
275 info->mpll_freq_khz = rate; 189 info->mpll_freq_khz = rate;
190 /* 800Mhz */
276 info->pll_safe_idx = L2; 191 info->pll_safe_idx = L2;
277 info->cpu_clk = cpu_clk; 192 info->cpu_clk = cpu_clk;
278 info->volt_table = exynos4210_volt_table; 193 info->volt_table = exynos4210_volt_table;
diff --git a/drivers/cpufreq/exynos4x12-cpufreq.c b/drivers/cpufreq/exynos4x12-cpufreq.c
index 29b41ab072f5..224445d3fd4f 100644
--- a/drivers/cpufreq/exynos4x12-cpufreq.c
+++ b/drivers/cpufreq/exynos4x12-cpufreq.c
@@ -20,23 +20,18 @@
20#include <mach/regs-clock.h> 20#include <mach/regs-clock.h>
21#include <mach/cpufreq.h> 21#include <mach/cpufreq.h>
22 22
23#define CPUFREQ_LEVEL_END (L13 + 1)
24
25static struct clk *cpu_clk; 23static struct clk *cpu_clk;
26static struct clk *moutcore; 24static struct clk *moutcore;
27static struct clk *mout_mpll; 25static struct clk *mout_mpll;
28static struct clk *mout_apll; 26static struct clk *mout_apll;
29 27
30struct cpufreq_clkdiv { 28static unsigned int exynos4x12_volt_table[] = {
31 unsigned int index; 29 1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
32 unsigned int clkdiv; 30 1000000, 987500, 975000, 950000, 925000, 900000, 900000
33 unsigned int clkdiv1;
34}; 31};
35 32
36static unsigned int exynos4x12_volt_table[CPUFREQ_LEVEL_END];
37
38static struct cpufreq_frequency_table exynos4x12_freq_table[] = { 33static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
39 {L0, 1500 * 1000}, 34 {L0, CPUFREQ_ENTRY_INVALID},
40 {L1, 1400 * 1000}, 35 {L1, 1400 * 1000},
41 {L2, 1300 * 1000}, 36 {L2, 1300 * 1000},
42 {L3, 1200 * 1000}, 37 {L3, 1200 * 1000},
@@ -53,247 +48,54 @@ static struct cpufreq_frequency_table exynos4x12_freq_table[] = {
53 {0, CPUFREQ_TABLE_END}, 48 {0, CPUFREQ_TABLE_END},
54}; 49};
55 50
56static struct cpufreq_clkdiv exynos4x12_clkdiv_table[CPUFREQ_LEVEL_END]; 51static struct apll_freq *apll_freq_4x12;
57 52
58static unsigned int clkdiv_cpu0_4212[CPUFREQ_LEVEL_END][8] = { 53static struct apll_freq apll_freq_4212[] = {
59 /* 54 /*
60 * Clock divider value for following 55 * values:
61 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH, 56 * freq
62 * DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 } 57 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
58 * clock divider for COPY, HPM, RESERVED
59 * PLL M, P, S
63 */ 60 */
64 /* ARM L0: 1500 MHz */ 61 APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 250, 4, 0),
65 { 0, 3, 7, 0, 6, 1, 2, 0 }, 62 APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 2, 0, 175, 3, 0),
66 63 APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 325, 6, 0),
67 /* ARM L1: 1400 MHz */ 64 APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 2, 0, 200, 4, 0),
68 { 0, 3, 7, 0, 6, 1, 2, 0 }, 65 APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 2, 0, 275, 6, 0),
69 66 APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 2, 0, 125, 3, 0),
70 /* ARM L2: 1300 MHz */ 67 APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 150, 4, 0),
71 { 0, 3, 7, 0, 5, 1, 2, 0 }, 68 APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 0),
72 69 APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 175, 3, 1),
73 /* ARM L3: 1200 MHz */ 70 APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 200, 4, 1),
74 { 0, 3, 7, 0, 5, 1, 2, 0 }, 71 APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 125, 3, 1),
75 72 APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 2, 0, 100, 3, 1),
76 /* ARM L4: 1100 MHz */ 73 APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 2, 0, 200, 4, 2),
77 { 0, 3, 6, 0, 4, 1, 2, 0 }, 74 APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 2, 0, 100, 3, 2),
78
79 /* ARM L5: 1000 MHz */
80 { 0, 2, 5, 0, 4, 1, 1, 0 },
81
82 /* ARM L6: 900 MHz */
83 { 0, 2, 5, 0, 3, 1, 1, 0 },
84
85 /* ARM L7: 800 MHz */
86 { 0, 2, 5, 0, 3, 1, 1, 0 },
87
88 /* ARM L8: 700 MHz */
89 { 0, 2, 4, 0, 3, 1, 1, 0 },
90
91 /* ARM L9: 600 MHz */
92 { 0, 2, 4, 0, 3, 1, 1, 0 },
93
94 /* ARM L10: 500 MHz */
95 { 0, 2, 4, 0, 3, 1, 1, 0 },
96
97 /* ARM L11: 400 MHz */
98 { 0, 2, 4, 0, 3, 1, 1, 0 },
99
100 /* ARM L12: 300 MHz */
101 { 0, 2, 4, 0, 2, 1, 1, 0 },
102
103 /* ARM L13: 200 MHz */
104 { 0, 1, 3, 0, 1, 1, 1, 0 },
105}; 75};
106 76
107static unsigned int clkdiv_cpu0_4412[CPUFREQ_LEVEL_END][8] = { 77static struct apll_freq apll_freq_4412[] = {
108 /* 78 /*
109 * Clock divider value for following 79 * values:
110 * { DIVCORE, DIVCOREM0, DIVCOREM1, DIVPERIPH, 80 * freq
111 * DIVATB, DIVPCLK_DBG, DIVAPLL, DIVCORE2 } 81 * clock divider for CORE, COREM0, COREM1, PERIPH, ATB, PCLK_DBG, APLL, CORE2
82 * clock divider for COPY, HPM, CORES
83 * PLL M, P, S
112 */ 84 */
113 /* ARM L0: 1500 MHz */ 85 APLL_FREQ(1500, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 7, 250, 4, 0),
114 { 0, 3, 7, 0, 6, 1, 2, 0 }, 86 APLL_FREQ(1400, 0, 3, 7, 0, 6, 1, 2, 0, 6, 0, 6, 175, 3, 0),
115 87 APLL_FREQ(1300, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 6, 325, 6, 0),
116 /* ARM L1: 1400 MHz */ 88 APLL_FREQ(1200, 0, 3, 7, 0, 5, 1, 2, 0, 5, 0, 5, 200, 4, 0),
117 { 0, 3, 7, 0, 6, 1, 2, 0 }, 89 APLL_FREQ(1100, 0, 3, 6, 0, 4, 1, 2, 0, 4, 0, 5, 275, 6, 0),
118 90 APLL_FREQ(1000, 0, 2, 5, 0, 4, 1, 1, 0, 4, 0, 4, 125, 3, 0),
119 /* ARM L2: 1300 MHz */ 91 APLL_FREQ(900, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 4, 150, 4, 0),
120 { 0, 3, 7, 0, 5, 1, 2, 0 }, 92 APLL_FREQ(800, 0, 2, 5, 0, 3, 1, 1, 0, 3, 0, 3, 100, 3, 0),
121 93 APLL_FREQ(700, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 3, 175, 3, 1),
122 /* ARM L3: 1200 MHz */ 94 APLL_FREQ(600, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 200, 4, 1),
123 { 0, 3, 7, 0, 5, 1, 2, 0 }, 95 APLL_FREQ(500, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 2, 125, 3, 1),
124 96 APLL_FREQ(400, 0, 2, 4, 0, 3, 1, 1, 0, 3, 0, 1, 100, 3, 1),
125 /* ARM L4: 1100 MHz */ 97 APLL_FREQ(300, 0, 2, 4, 0, 2, 1, 1, 0, 3, 0, 1, 200, 4, 2),
126 { 0, 3, 6, 0, 4, 1, 2, 0 }, 98 APLL_FREQ(200, 0, 1, 3, 0, 1, 1, 1, 0, 3, 0, 0, 100, 3, 2),
127
128 /* ARM L5: 1000 MHz */
129 { 0, 2, 5, 0, 4, 1, 1, 0 },
130
131 /* ARM L6: 900 MHz */
132 { 0, 2, 5, 0, 3, 1, 1, 0 },
133
134 /* ARM L7: 800 MHz */
135 { 0, 2, 5, 0, 3, 1, 1, 0 },
136
137 /* ARM L8: 700 MHz */
138 { 0, 2, 4, 0, 3, 1, 1, 0 },
139
140 /* ARM L9: 600 MHz */
141 { 0, 2, 4, 0, 3, 1, 1, 0 },
142
143 /* ARM L10: 500 MHz */
144 { 0, 2, 4, 0, 3, 1, 1, 0 },
145
146 /* ARM L11: 400 MHz */
147 { 0, 2, 4, 0, 3, 1, 1, 0 },
148
149 /* ARM L12: 300 MHz */
150 { 0, 2, 4, 0, 2, 1, 1, 0 },
151
152 /* ARM L13: 200 MHz */
153 { 0, 1, 3, 0, 1, 1, 1, 0 },
154};
155
156static unsigned int clkdiv_cpu1_4212[CPUFREQ_LEVEL_END][2] = {
157 /* Clock divider value for following
158 * { DIVCOPY, DIVHPM }
159 */
160 /* ARM L0: 1500 MHz */
161 { 6, 0 },
162
163 /* ARM L1: 1400 MHz */
164 { 6, 0 },
165
166 /* ARM L2: 1300 MHz */
167 { 5, 0 },
168
169 /* ARM L3: 1200 MHz */
170 { 5, 0 },
171
172 /* ARM L4: 1100 MHz */
173 { 4, 0 },
174
175 /* ARM L5: 1000 MHz */
176 { 4, 0 },
177
178 /* ARM L6: 900 MHz */
179 { 3, 0 },
180
181 /* ARM L7: 800 MHz */
182 { 3, 0 },
183
184 /* ARM L8: 700 MHz */
185 { 3, 0 },
186
187 /* ARM L9: 600 MHz */
188 { 3, 0 },
189
190 /* ARM L10: 500 MHz */
191 { 3, 0 },
192
193 /* ARM L11: 400 MHz */
194 { 3, 0 },
195
196 /* ARM L12: 300 MHz */
197 { 3, 0 },
198
199 /* ARM L13: 200 MHz */
200 { 3, 0 },
201};
202
203static unsigned int clkdiv_cpu1_4412[CPUFREQ_LEVEL_END][3] = {
204 /* Clock divider value for following
205 * { DIVCOPY, DIVHPM, DIVCORES }
206 */
207 /* ARM L0: 1500 MHz */
208 { 6, 0, 7 },
209
210 /* ARM L1: 1400 MHz */
211 { 6, 0, 6 },
212
213 /* ARM L2: 1300 MHz */
214 { 5, 0, 6 },
215
216 /* ARM L3: 1200 MHz */
217 { 5, 0, 5 },
218
219 /* ARM L4: 1100 MHz */
220 { 4, 0, 5 },
221
222 /* ARM L5: 1000 MHz */
223 { 4, 0, 4 },
224
225 /* ARM L6: 900 MHz */
226 { 3, 0, 4 },
227
228 /* ARM L7: 800 MHz */
229 { 3, 0, 3 },
230
231 /* ARM L8: 700 MHz */
232 { 3, 0, 3 },
233
234 /* ARM L9: 600 MHz */
235 { 3, 0, 2 },
236
237 /* ARM L10: 500 MHz */
238 { 3, 0, 2 },
239
240 /* ARM L11: 400 MHz */
241 { 3, 0, 1 },
242
243 /* ARM L12: 300 MHz */
244 { 3, 0, 1 },
245
246 /* ARM L13: 200 MHz */
247 { 3, 0, 0 },
248};
249
250static unsigned int exynos4x12_apll_pms_table[CPUFREQ_LEVEL_END] = {
251 /* APLL FOUT L0: 1500 MHz */
252 ((250 << 16) | (4 << 8) | (0x0)),
253
254 /* APLL FOUT L1: 1400 MHz */
255 ((175 << 16) | (3 << 8) | (0x0)),
256
257 /* APLL FOUT L2: 1300 MHz */
258 ((325 << 16) | (6 << 8) | (0x0)),
259
260 /* APLL FOUT L3: 1200 MHz */
261 ((200 << 16) | (4 << 8) | (0x0)),
262
263 /* APLL FOUT L4: 1100 MHz */
264 ((275 << 16) | (6 << 8) | (0x0)),
265
266 /* APLL FOUT L5: 1000 MHz */
267 ((125 << 16) | (3 << 8) | (0x0)),
268
269 /* APLL FOUT L6: 900 MHz */
270 ((150 << 16) | (4 << 8) | (0x0)),
271
272 /* APLL FOUT L7: 800 MHz */
273 ((100 << 16) | (3 << 8) | (0x0)),
274
275 /* APLL FOUT L8: 700 MHz */
276 ((175 << 16) | (3 << 8) | (0x1)),
277
278 /* APLL FOUT L9: 600 MHz */
279 ((200 << 16) | (4 << 8) | (0x1)),
280
281 /* APLL FOUT L10: 500 MHz */
282 ((125 << 16) | (3 << 8) | (0x1)),
283
284 /* APLL FOUT L11 400 MHz */
285 ((100 << 16) | (3 << 8) | (0x1)),
286
287 /* APLL FOUT L12: 300 MHz */
288 ((200 << 16) | (4 << 8) | (0x2)),
289
290 /* APLL FOUT L13: 200 MHz */
291 ((100 << 16) | (3 << 8) | (0x2)),
292};
293
294static const unsigned int asv_voltage_4x12[CPUFREQ_LEVEL_END] = {
295 1350000, 1287500, 1250000, 1187500, 1137500, 1087500, 1037500,
296 1000000, 987500, 975000, 950000, 925000, 900000, 900000
297}; 99};
298 100
299static void exynos4x12_set_clkdiv(unsigned int div_index) 101static void exynos4x12_set_clkdiv(unsigned int div_index)
@@ -303,7 +105,7 @@ static void exynos4x12_set_clkdiv(unsigned int div_index)
303 105
304 /* Change Divider - CPU0 */ 106 /* Change Divider - CPU0 */
305 107
306 tmp = exynos4x12_clkdiv_table[div_index].clkdiv; 108 tmp = apll_freq_4x12[div_index].clk_div_cpu0;
307 109
308 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU); 110 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU);
309 111
@@ -311,7 +113,7 @@ static void exynos4x12_set_clkdiv(unsigned int div_index)
311 cpu_relax(); 113 cpu_relax();
312 114
313 /* Change Divider - CPU1 */ 115 /* Change Divider - CPU1 */
314 tmp = exynos4x12_clkdiv_table[div_index].clkdiv1; 116 tmp = apll_freq_4x12[div_index].clk_div_cpu1;
315 117
316 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1); 118 __raw_writel(tmp, EXYNOS4_CLKDIV_CPU1);
317 if (soc_is_exynos4212()) 119 if (soc_is_exynos4212())
@@ -338,14 +140,14 @@ static void exynos4x12_set_apll(unsigned int index)
338 } while (tmp != 0x2); 140 } while (tmp != 0x2);
339 141
340 /* 2. Set APLL Lock time */ 142 /* 2. Set APLL Lock time */
341 pdiv = ((exynos4x12_apll_pms_table[index] >> 8) & 0x3f); 143 pdiv = ((apll_freq_4x12[index].mps >> 8) & 0x3f);
342 144
343 __raw_writel((pdiv * 250), EXYNOS4_APLL_LOCK); 145 __raw_writel((pdiv * 250), EXYNOS4_APLL_LOCK);
344 146
345 /* 3. Change PLL PMS values */ 147 /* 3. Change PLL PMS values */
346 tmp = __raw_readl(EXYNOS4_APLL_CON0); 148 tmp = __raw_readl(EXYNOS4_APLL_CON0);
347 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); 149 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
348 tmp |= exynos4x12_apll_pms_table[index]; 150 tmp |= apll_freq_4x12[index].mps;
349 __raw_writel(tmp, EXYNOS4_APLL_CON0); 151 __raw_writel(tmp, EXYNOS4_APLL_CON0);
350 152
351 /* 4. wait_lock_time */ 153 /* 4. wait_lock_time */
@@ -366,8 +168,8 @@ static void exynos4x12_set_apll(unsigned int index)
366 168
367bool exynos4x12_pms_change(unsigned int old_index, unsigned int new_index) 169bool exynos4x12_pms_change(unsigned int old_index, unsigned int new_index)
368{ 170{
369 unsigned int old_pm = exynos4x12_apll_pms_table[old_index] >> 8; 171 unsigned int old_pm = apll_freq_4x12[old_index].mps >> 8;
370 unsigned int new_pm = exynos4x12_apll_pms_table[new_index] >> 8; 172 unsigned int new_pm = apll_freq_4x12[new_index].mps >> 8;
371 173
372 return (old_pm == new_pm) ? 0 : 1; 174 return (old_pm == new_pm) ? 0 : 1;
373} 175}
@@ -384,7 +186,7 @@ static void exynos4x12_set_frequency(unsigned int old_index,
384 /* 2. Change just s value in apll m,p,s value */ 186 /* 2. Change just s value in apll m,p,s value */
385 tmp = __raw_readl(EXYNOS4_APLL_CON0); 187 tmp = __raw_readl(EXYNOS4_APLL_CON0);
386 tmp &= ~(0x7 << 0); 188 tmp &= ~(0x7 << 0);
387 tmp |= (exynos4x12_apll_pms_table[new_index] & 0x7); 189 tmp |= apll_freq_4x12[new_index].mps & 0x7;
388 __raw_writel(tmp, EXYNOS4_APLL_CON0); 190 __raw_writel(tmp, EXYNOS4_APLL_CON0);
389 191
390 } else { 192 } else {
@@ -399,7 +201,7 @@ static void exynos4x12_set_frequency(unsigned int old_index,
399 /* 1. Change just s value in apll m,p,s value */ 201 /* 1. Change just s value in apll m,p,s value */
400 tmp = __raw_readl(EXYNOS4_APLL_CON0); 202 tmp = __raw_readl(EXYNOS4_APLL_CON0);
401 tmp &= ~(0x7 << 0); 203 tmp &= ~(0x7 << 0);
402 tmp |= (exynos4x12_apll_pms_table[new_index] & 0x7); 204 tmp |= apll_freq_4x12[new_index].mps & 0x7;
403 __raw_writel(tmp, EXYNOS4_APLL_CON0); 205 __raw_writel(tmp, EXYNOS4_APLL_CON0);
404 /* 2. Change the system clock divider values */ 206 /* 2. Change the system clock divider values */
405 exynos4x12_set_clkdiv(new_index); 207 exynos4x12_set_clkdiv(new_index);
@@ -413,25 +215,10 @@ static void exynos4x12_set_frequency(unsigned int old_index,
413 } 215 }
414} 216}
415 217
416static void __init set_volt_table(void)
417{
418 unsigned int i;
419
420 /* Not supported */
421 exynos4x12_freq_table[L0].frequency = CPUFREQ_ENTRY_INVALID;
422
423 for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
424 exynos4x12_volt_table[i] = asv_voltage_4x12[i];
425}
426
427int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info) 218int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
428{ 219{
429 int i;
430 unsigned int tmp;
431 unsigned long rate; 220 unsigned long rate;
432 221
433 set_volt_table();
434
435 cpu_clk = clk_get(NULL, "armclk"); 222 cpu_clk = clk_get(NULL, "armclk");
436 if (IS_ERR(cpu_clk)) 223 if (IS_ERR(cpu_clk))
437 return PTR_ERR(cpu_clk); 224 return PTR_ERR(cpu_clk);
@@ -450,62 +237,13 @@ int exynos4x12_cpufreq_init(struct exynos_dvfs_info *info)
450 if (IS_ERR(mout_apll)) 237 if (IS_ERR(mout_apll))
451 goto err_mout_apll; 238 goto err_mout_apll;
452 239
453 for (i = L0; i < CPUFREQ_LEVEL_END; i++) { 240 if (soc_is_exynos4212())
454 241 apll_freq_4x12 = apll_freq_4212;
455 exynos4x12_clkdiv_table[i].index = i; 242 else
456 243 apll_freq_4x12 = apll_freq_4412;
457 tmp = __raw_readl(EXYNOS4_CLKDIV_CPU);
458
459 tmp &= ~(EXYNOS4_CLKDIV_CPU0_CORE_MASK |
460 EXYNOS4_CLKDIV_CPU0_COREM0_MASK |
461 EXYNOS4_CLKDIV_CPU0_COREM1_MASK |
462 EXYNOS4_CLKDIV_CPU0_PERIPH_MASK |
463 EXYNOS4_CLKDIV_CPU0_ATB_MASK |
464 EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK |
465 EXYNOS4_CLKDIV_CPU0_APLL_MASK);
466
467 if (soc_is_exynos4212()) {
468 tmp |= ((clkdiv_cpu0_4212[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
469 (clkdiv_cpu0_4212[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
470 (clkdiv_cpu0_4212[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
471 (clkdiv_cpu0_4212[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
472 (clkdiv_cpu0_4212[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
473 (clkdiv_cpu0_4212[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
474 (clkdiv_cpu0_4212[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT));
475 } else {
476 tmp &= ~EXYNOS4_CLKDIV_CPU0_CORE2_MASK;
477
478 tmp |= ((clkdiv_cpu0_4412[i][0] << EXYNOS4_CLKDIV_CPU0_CORE_SHIFT) |
479 (clkdiv_cpu0_4412[i][1] << EXYNOS4_CLKDIV_CPU0_COREM0_SHIFT) |
480 (clkdiv_cpu0_4412[i][2] << EXYNOS4_CLKDIV_CPU0_COREM1_SHIFT) |
481 (clkdiv_cpu0_4412[i][3] << EXYNOS4_CLKDIV_CPU0_PERIPH_SHIFT) |
482 (clkdiv_cpu0_4412[i][4] << EXYNOS4_CLKDIV_CPU0_ATB_SHIFT) |
483 (clkdiv_cpu0_4412[i][5] << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) |
484 (clkdiv_cpu0_4412[i][6] << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) |
485 (clkdiv_cpu0_4412[i][7] << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT));
486 }
487
488 exynos4x12_clkdiv_table[i].clkdiv = tmp;
489
490 tmp = __raw_readl(EXYNOS4_CLKDIV_CPU1);
491
492 if (soc_is_exynos4212()) {
493 tmp &= ~(EXYNOS4_CLKDIV_CPU1_COPY_MASK |
494 EXYNOS4_CLKDIV_CPU1_HPM_MASK);
495 tmp |= ((clkdiv_cpu1_4212[i][0] << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
496 (clkdiv_cpu1_4212[i][1] << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT));
497 } else {
498 tmp &= ~(EXYNOS4_CLKDIV_CPU1_COPY_MASK |
499 EXYNOS4_CLKDIV_CPU1_HPM_MASK |
500 EXYNOS4_CLKDIV_CPU1_CORES_MASK);
501 tmp |= ((clkdiv_cpu1_4412[i][0] << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) |
502 (clkdiv_cpu1_4412[i][1] << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) |
503 (clkdiv_cpu1_4412[i][2] << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT));
504 }
505 exynos4x12_clkdiv_table[i].clkdiv1 = tmp;
506 }
507 244
508 info->mpll_freq_khz = rate; 245 info->mpll_freq_khz = rate;
246 /* 800Mhz */
509 info->pll_safe_idx = L7; 247 info->pll_safe_idx = L7;
510 info->cpu_clk = cpu_clk; 248 info->cpu_clk = cpu_clk;
511 info->volt_table = exynos4x12_volt_table; 249 info->volt_table = exynos4x12_volt_table;
diff --git a/drivers/cpufreq/exynos5250-cpufreq.c b/drivers/cpufreq/exynos5250-cpufreq.c
index 8a5d7338b795..736a5cfdfd17 100644
--- a/drivers/cpufreq/exynos5250-cpufreq.c
+++ b/drivers/cpufreq/exynos5250-cpufreq.c
@@ -21,21 +21,18 @@
21#include <mach/regs-clock.h> 21#include <mach/regs-clock.h>
22#include <mach/cpufreq.h> 22#include <mach/cpufreq.h>
23 23
24#define CPUFREQ_LEVEL_END (L15 + 1)
25
26static struct clk *cpu_clk; 24static struct clk *cpu_clk;
27static struct clk *moutcore; 25static struct clk *moutcore;
28static struct clk *mout_mpll; 26static struct clk *mout_mpll;
29static struct clk *mout_apll; 27static struct clk *mout_apll;
30 28
31struct cpufreq_clkdiv { 29static unsigned int exynos5250_volt_table[] = {
32 unsigned int index; 30 1300000, 1250000, 1225000, 1200000, 1150000,
33 unsigned int clkdiv; 31 1125000, 1100000, 1075000, 1050000, 1025000,
34 unsigned int clkdiv1; 32 1012500, 1000000, 975000, 950000, 937500,
33 925000
35}; 34};
36 35
37static unsigned int exynos5250_volt_table[CPUFREQ_LEVEL_END];
38
39static struct cpufreq_frequency_table exynos5250_freq_table[] = { 36static struct cpufreq_frequency_table exynos5250_freq_table[] = {
40 {L0, 1700 * 1000}, 37 {L0, 1700 * 1000},
41 {L1, 1600 * 1000}, 38 {L1, 1600 * 1000},
@@ -45,8 +42,8 @@ static struct cpufreq_frequency_table exynos5250_freq_table[] = {
45 {L5, 1200 * 1000}, 42 {L5, 1200 * 1000},
46 {L6, 1100 * 1000}, 43 {L6, 1100 * 1000},
47 {L7, 1000 * 1000}, 44 {L7, 1000 * 1000},
48 {L8, 900 * 1000}, 45 {L8, 900 * 1000},
49 {L9, 800 * 1000}, 46 {L9, 800 * 1000},
50 {L10, 700 * 1000}, 47 {L10, 700 * 1000},
51 {L11, 600 * 1000}, 48 {L11, 600 * 1000},
52 {L12, 500 * 1000}, 49 {L12, 500 * 1000},
@@ -56,78 +53,30 @@ static struct cpufreq_frequency_table exynos5250_freq_table[] = {
56 {0, CPUFREQ_TABLE_END}, 53 {0, CPUFREQ_TABLE_END},
57}; 54};
58 55
59static struct cpufreq_clkdiv exynos5250_clkdiv_table[CPUFREQ_LEVEL_END]; 56static struct apll_freq apll_freq_5250[] = {
60
61static unsigned int clkdiv_cpu0_5250[CPUFREQ_LEVEL_END][8] = {
62 /* 57 /*
63 * Clock divider value for following 58 * values:
64 * { ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2 } 59 * freq
65 */ 60 * clock divider for ARM, CPUD, ACP, PERIPH, ATB, PCLK_DBG, APLL, ARM2
66 { 0, 3, 7, 7, 7, 3, 5, 0 }, /* 1700 MHz */ 61 * clock divider for COPY, HPM, RESERVED
67 { 0, 3, 7, 7, 7, 1, 4, 0 }, /* 1600 MHz */ 62 * PLL M, P, S
68 { 0, 2, 7, 7, 7, 1, 4, 0 }, /* 1500 MHz */
69 { 0, 2, 7, 7, 6, 1, 4, 0 }, /* 1400 MHz */
70 { 0, 2, 7, 7, 6, 1, 3, 0 }, /* 1300 MHz */
71 { 0, 2, 7, 7, 5, 1, 3, 0 }, /* 1200 MHz */
72 { 0, 3, 7, 7, 5, 1, 3, 0 }, /* 1100 MHz */
73 { 0, 1, 7, 7, 4, 1, 2, 0 }, /* 1000 MHz */
74 { 0, 1, 7, 7, 4, 1, 2, 0 }, /* 900 MHz */
75 { 0, 1, 7, 7, 4, 1, 2, 0 }, /* 800 MHz */
76 { 0, 1, 7, 7, 3, 1, 1, 0 }, /* 700 MHz */
77 { 0, 1, 7, 7, 3, 1, 1, 0 }, /* 600 MHz */
78 { 0, 1, 7, 7, 2, 1, 1, 0 }, /* 500 MHz */
79 { 0, 1, 7, 7, 2, 1, 1, 0 }, /* 400 MHz */
80 { 0, 1, 7, 7, 1, 1, 1, 0 }, /* 300 MHz */
81 { 0, 1, 7, 7, 1, 1, 1, 0 }, /* 200 MHz */
82};
83
84static unsigned int clkdiv_cpu1_5250[CPUFREQ_LEVEL_END][2] = {
85 /* Clock divider value for following
86 * { COPY, HPM }
87 */ 63 */
88 { 0, 2 }, /* 1700 MHz */ 64 APLL_FREQ(1700, 0, 3, 7, 7, 7, 3, 5, 0, 0, 2, 0, 425, 6, 0),
89 { 0, 2 }, /* 1600 MHz */ 65 APLL_FREQ(1600, 0, 3, 7, 7, 7, 1, 4, 0, 0, 2, 0, 200, 3, 0),
90 { 0, 2 }, /* 1500 MHz */ 66 APLL_FREQ(1500, 0, 2, 7, 7, 7, 1, 4, 0, 0, 2, 0, 250, 4, 0),
91 { 0, 2 }, /* 1400 MHz */ 67 APLL_FREQ(1400, 0, 2, 7, 7, 6, 1, 4, 0, 0, 2, 0, 175, 3, 0),
92 { 0, 2 }, /* 1300 MHz */ 68 APLL_FREQ(1300, 0, 2, 7, 7, 6, 1, 3, 0, 0, 2, 0, 325, 6, 0),
93 { 0, 2 }, /* 1200 MHz */ 69 APLL_FREQ(1200, 0, 2, 7, 7, 5, 1, 3, 0, 0, 2, 0, 200, 4, 0),
94 { 0, 2 }, /* 1100 MHz */ 70 APLL_FREQ(1100, 0, 3, 7, 7, 5, 1, 3, 0, 0, 2, 0, 275, 6, 0),
95 { 0, 2 }, /* 1000 MHz */ 71 APLL_FREQ(1000, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 125, 3, 0),
96 { 0, 2 }, /* 900 MHz */ 72 APLL_FREQ(900, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 150, 4, 0),
97 { 0, 2 }, /* 800 MHz */ 73 APLL_FREQ(800, 0, 1, 7, 7, 4, 1, 2, 0, 0, 2, 0, 100, 3, 0),
98 { 0, 2 }, /* 700 MHz */ 74 APLL_FREQ(700, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 175, 3, 1),
99 { 0, 2 }, /* 600 MHz */ 75 APLL_FREQ(600, 0, 1, 7, 7, 3, 1, 1, 0, 0, 2, 0, 200, 4, 1),
100 { 0, 2 }, /* 500 MHz */ 76 APLL_FREQ(500, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 125, 3, 1),
101 { 0, 2 }, /* 400 MHz */ 77 APLL_FREQ(400, 0, 1, 7, 7, 2, 1, 1, 0, 0, 2, 0, 100, 3, 1),
102 { 0, 2 }, /* 300 MHz */ 78 APLL_FREQ(300, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 200, 4, 2),
103 { 0, 2 }, /* 200 MHz */ 79 APLL_FREQ(200, 0, 1, 7, 7, 1, 1, 1, 0, 0, 2, 0, 100, 3, 2),
104};
105
106static unsigned int exynos5_apll_pms_table[CPUFREQ_LEVEL_END] = {
107 ((425 << 16) | (6 << 8) | 0), /* 1700 MHz */
108 ((200 << 16) | (3 << 8) | 0), /* 1600 MHz */
109 ((250 << 16) | (4 << 8) | 0), /* 1500 MHz */
110 ((175 << 16) | (3 << 8) | 0), /* 1400 MHz */
111 ((325 << 16) | (6 << 8) | 0), /* 1300 MHz */
112 ((200 << 16) | (4 << 8) | 0), /* 1200 MHz */
113 ((275 << 16) | (6 << 8) | 0), /* 1100 MHz */
114 ((125 << 16) | (3 << 8) | 0), /* 1000 MHz */
115 ((150 << 16) | (4 << 8) | 0), /* 900 MHz */
116 ((100 << 16) | (3 << 8) | 0), /* 800 MHz */
117 ((175 << 16) | (3 << 8) | 1), /* 700 MHz */
118 ((200 << 16) | (4 << 8) | 1), /* 600 MHz */
119 ((125 << 16) | (3 << 8) | 1), /* 500 MHz */
120 ((100 << 16) | (3 << 8) | 1), /* 400 MHz */
121 ((200 << 16) | (4 << 8) | 2), /* 300 MHz */
122 ((100 << 16) | (3 << 8) | 2), /* 200 MHz */
123};
124
125/* ASV group voltage table */
126static const unsigned int asv_voltage_5250[CPUFREQ_LEVEL_END] = {
127 1300000, 1250000, 1225000, 1200000, 1150000,
128 1125000, 1100000, 1075000, 1050000, 1025000,
129 1012500, 1000000, 975000, 950000, 937500,
130 925000
131}; 80};
132 81
133static void set_clkdiv(unsigned int div_index) 82static void set_clkdiv(unsigned int div_index)
@@ -136,7 +85,7 @@ static void set_clkdiv(unsigned int div_index)
136 85
137 /* Change Divider - CPU0 */ 86 /* Change Divider - CPU0 */
138 87
139 tmp = exynos5250_clkdiv_table[div_index].clkdiv; 88 tmp = apll_freq_5250[div_index].clk_div_cpu0;
140 89
141 __raw_writel(tmp, EXYNOS5_CLKDIV_CPU0); 90 __raw_writel(tmp, EXYNOS5_CLKDIV_CPU0);
142 91
@@ -144,7 +93,7 @@ static void set_clkdiv(unsigned int div_index)
144 cpu_relax(); 93 cpu_relax();
145 94
146 /* Change Divider - CPU1 */ 95 /* Change Divider - CPU1 */
147 tmp = exynos5250_clkdiv_table[div_index].clkdiv1; 96 tmp = apll_freq_5250[div_index].clk_div_cpu1;
148 97
149 __raw_writel(tmp, EXYNOS5_CLKDIV_CPU1); 98 __raw_writel(tmp, EXYNOS5_CLKDIV_CPU1);
150 99
@@ -167,14 +116,14 @@ static void set_apll(unsigned int new_index,
167 } while (tmp != 0x2); 116 } while (tmp != 0x2);
168 117
169 /* 2. Set APLL Lock time */ 118 /* 2. Set APLL Lock time */
170 pdiv = ((exynos5_apll_pms_table[new_index] >> 8) & 0x3f); 119 pdiv = ((apll_freq_5250[new_index].mps >> 8) & 0x3f);
171 120
172 __raw_writel((pdiv * 250), EXYNOS5_APLL_LOCK); 121 __raw_writel((pdiv * 250), EXYNOS5_APLL_LOCK);
173 122
174 /* 3. Change PLL PMS values */ 123 /* 3. Change PLL PMS values */
175 tmp = __raw_readl(EXYNOS5_APLL_CON0); 124 tmp = __raw_readl(EXYNOS5_APLL_CON0);
176 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0)); 125 tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
177 tmp |= exynos5_apll_pms_table[new_index]; 126 tmp |= apll_freq_5250[new_index].mps;
178 __raw_writel(tmp, EXYNOS5_APLL_CON0); 127 __raw_writel(tmp, EXYNOS5_APLL_CON0);
179 128
180 /* 4. wait_lock_time */ 129 /* 4. wait_lock_time */
@@ -196,8 +145,8 @@ static void set_apll(unsigned int new_index,
196 145
197bool exynos5250_pms_change(unsigned int old_index, unsigned int new_index) 146bool exynos5250_pms_change(unsigned int old_index, unsigned int new_index)
198{ 147{
199 unsigned int old_pm = (exynos5_apll_pms_table[old_index] >> 8); 148 unsigned int old_pm = apll_freq_5250[old_index].mps >> 8;
200 unsigned int new_pm = (exynos5_apll_pms_table[new_index] >> 8); 149 unsigned int new_pm = apll_freq_5250[new_index].mps >> 8;
201 150
202 return (old_pm == new_pm) ? 0 : 1; 151 return (old_pm == new_pm) ? 0 : 1;
203} 152}
@@ -214,7 +163,7 @@ static void exynos5250_set_frequency(unsigned int old_index,
214 /* 2. Change just s value in apll m,p,s value */ 163 /* 2. Change just s value in apll m,p,s value */
215 tmp = __raw_readl(EXYNOS5_APLL_CON0); 164 tmp = __raw_readl(EXYNOS5_APLL_CON0);
216 tmp &= ~(0x7 << 0); 165 tmp &= ~(0x7 << 0);
217 tmp |= (exynos5_apll_pms_table[new_index] & 0x7); 166 tmp |= apll_freq_5250[new_index].mps & 0x7;
218 __raw_writel(tmp, EXYNOS5_APLL_CON0); 167 __raw_writel(tmp, EXYNOS5_APLL_CON0);
219 168
220 } else { 169 } else {
@@ -229,7 +178,7 @@ static void exynos5250_set_frequency(unsigned int old_index,
229 /* 1. Change just s value in apll m,p,s value */ 178 /* 1. Change just s value in apll m,p,s value */
230 tmp = __raw_readl(EXYNOS5_APLL_CON0); 179 tmp = __raw_readl(EXYNOS5_APLL_CON0);
231 tmp &= ~(0x7 << 0); 180 tmp &= ~(0x7 << 0);
232 tmp |= (exynos5_apll_pms_table[new_index] & 0x7); 181 tmp |= apll_freq_5250[new_index].mps & 0x7;
233 __raw_writel(tmp, EXYNOS5_APLL_CON0); 182 __raw_writel(tmp, EXYNOS5_APLL_CON0);
234 /* 2. Change the system clock divider values */ 183 /* 2. Change the system clock divider values */
235 set_clkdiv(new_index); 184 set_clkdiv(new_index);
@@ -243,22 +192,10 @@ static void exynos5250_set_frequency(unsigned int old_index,
243 } 192 }
244} 193}
245 194
246static void __init set_volt_table(void)
247{
248 unsigned int i;
249
250 for (i = 0 ; i < CPUFREQ_LEVEL_END ; i++)
251 exynos5250_volt_table[i] = asv_voltage_5250[i];
252}
253
254int exynos5250_cpufreq_init(struct exynos_dvfs_info *info) 195int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
255{ 196{
256 int i;
257 unsigned int tmp;
258 unsigned long rate; 197 unsigned long rate;
259 198
260 set_volt_table();
261
262 cpu_clk = clk_get(NULL, "armclk"); 199 cpu_clk = clk_get(NULL, "armclk");
263 if (IS_ERR(cpu_clk)) 200 if (IS_ERR(cpu_clk))
264 return PTR_ERR(cpu_clk); 201 return PTR_ERR(cpu_clk);
@@ -277,37 +214,6 @@ int exynos5250_cpufreq_init(struct exynos_dvfs_info *info)
277 if (IS_ERR(mout_apll)) 214 if (IS_ERR(mout_apll))
278 goto err_mout_apll; 215 goto err_mout_apll;
279 216
280 for (i = L0; i < CPUFREQ_LEVEL_END; i++) {
281
282 exynos5250_clkdiv_table[i].index = i;
283
284 tmp = __raw_readl(EXYNOS5_CLKDIV_CPU0);
285
286 tmp &= ~((0x7 << 0) | (0x7 << 4) | (0x7 << 8) |
287 (0x7 << 12) | (0x7 << 16) | (0x7 << 20) |
288 (0x7 << 24) | (0x7 << 28));
289
290 tmp |= ((clkdiv_cpu0_5250[i][0] << 0) |
291 (clkdiv_cpu0_5250[i][1] << 4) |
292 (clkdiv_cpu0_5250[i][2] << 8) |
293 (clkdiv_cpu0_5250[i][3] << 12) |
294 (clkdiv_cpu0_5250[i][4] << 16) |
295 (clkdiv_cpu0_5250[i][5] << 20) |
296 (clkdiv_cpu0_5250[i][6] << 24) |
297 (clkdiv_cpu0_5250[i][7] << 28));
298
299 exynos5250_clkdiv_table[i].clkdiv = tmp;
300
301 tmp = __raw_readl(EXYNOS5_CLKDIV_CPU1);
302
303 tmp &= ~((0x7 << 0) | (0x7 << 4));
304
305 tmp |= ((clkdiv_cpu1_5250[i][0] << 0) |
306 (clkdiv_cpu1_5250[i][1] << 4));
307
308 exynos5250_clkdiv_table[i].clkdiv1 = tmp;
309 }
310
311 info->mpll_freq_khz = rate; 217 info->mpll_freq_khz = rate;
312 /* 800Mhz */ 218 /* 800Mhz */
313 info->pll_safe_idx = L9; 219 info->pll_safe_idx = L9;
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 08:57:59 -0500