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authorArend van Spriel <arend@broadcom.com>2011-12-12 18:15:02 -0500
committerJohn W. Linville <linville@tuxdriver.com>2011-12-13 15:48:04 -0500
commit8d30b708b82ffa98e04197547e89fd8f18313ce2 (patch)
tree0dc5fb90a631ed4fe016d55312357eb40184e59c
parentb14f16747f143b330d0cef84ff2c590c3f1744a4 (diff)
brcm80211: smac: use bcma core access functions in pmu.c
The code in pmu.c now uses the functions provided by BCMA to access the core registers. Reviewed-by: Pieter-Paul Giesberts <pieterpg@broadcom.com> Reviewed-by: Alwin Beukers <alwin@broadcom.com> Signed-off-by: Arend van Spriel <arend@broadcom.com> Signed-off-by: Franky Lin <frankyl@broadcom.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Diffstat
-rw-r--r--drivers/net/wireless/brcm80211/brcmsmac/pmu.c153
1 files changed, 73 insertions, 80 deletions
diff --git a/drivers/net/wireless/brcm80211/brcmsmac/pmu.c b/drivers/net/wireless/brcm80211/brcmsmac/pmu.c
index ba319f31c9a9..9a4d367228a0 100644
--- a/drivers/net/wireless/brcm80211/brcmsmac/pmu.c
+++ b/drivers/net/wireless/brcm80211/brcmsmac/pmu.c
@@ -140,7 +140,7 @@ static void si_pmu_res_masks(struct si_pub *sih, u32 * pmin, u32 * pmax)
140} 140}
141 141
142static void 142static void
143si_pmu_spuravoid_pllupdate(struct si_pub *sih, struct chipcregs __iomem *cc, 143si_pmu_spuravoid_pllupdate(struct si_pub *sih, struct bcma_device *core,
144 u8 spuravoid) 144 u8 spuravoid)
145{ 145{
146 u32 tmp = 0; 146 u32 tmp = 0;
@@ -149,58 +149,65 @@ si_pmu_spuravoid_pllupdate(struct si_pub *sih, struct chipcregs __iomem *cc,
149 case BCM43224_CHIP_ID: 149 case BCM43224_CHIP_ID:
150 case BCM43225_CHIP_ID: 150 case BCM43225_CHIP_ID:
151 if (spuravoid == 1) { 151 if (spuravoid == 1) {
152 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); 152 bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
153 W_REG(&cc->pllcontrol_data, 0x11500010); 153 PMU1_PLL0_PLLCTL0);
154 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); 154 bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
155 W_REG(&cc->pllcontrol_data, 0x000C0C06); 155 0x11500010);
156 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); 156 bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
157 W_REG(&cc->pllcontrol_data, 0x0F600a08); 157 PMU1_PLL0_PLLCTL1);
158 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); 158 bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
159 W_REG(&cc->pllcontrol_data, 0x00000000); 159 0x000C0C06);
160 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); 160 bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
161 W_REG(&cc->pllcontrol_data, 0x2001E920); 161 PMU1_PLL0_PLLCTL2);
162 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); 162 bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
163 W_REG(&cc->pllcontrol_data, 0x88888815); 163 0x0F600a08);
164 bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
165 PMU1_PLL0_PLLCTL3);
166 bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
167 0x00000000);
168 bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
169 PMU1_PLL0_PLLCTL4);
170 bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
171 0x2001E920);
172 bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
173 PMU1_PLL0_PLLCTL5);
174 bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
175 0x88888815);
164 } else { 176 } else {
165 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0); 177 bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
166 W_REG(&cc->pllcontrol_data, 0x11100010); 178 PMU1_PLL0_PLLCTL0);
167 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1); 179 bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
168 W_REG(&cc->pllcontrol_data, 0x000c0c06); 180 0x11100010);
169 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2); 181 bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
170 W_REG(&cc->pllcontrol_data, 0x03000a08); 182 PMU1_PLL0_PLLCTL1);
171 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3); 183 bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
172 W_REG(&cc->pllcontrol_data, 0x00000000); 184 0x000c0c06);
173 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4); 185 bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
174 W_REG(&cc->pllcontrol_data, 0x200005c0); 186 PMU1_PLL0_PLLCTL2);
175 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5); 187 bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
176 W_REG(&cc->pllcontrol_data, 0x88888815); 188 0x03000a08);
189 bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
190 PMU1_PLL0_PLLCTL3);
191 bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
192 0x00000000);
193 bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
194 PMU1_PLL0_PLLCTL4);
195 bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
196 0x200005c0);
197 bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
198 PMU1_PLL0_PLLCTL5);
199 bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
200 0x88888815);
177 } 201 }
178 tmp = 1 << 10; 202 tmp = 1 << 10;
179 break; 203 break;
180 204
181 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
182 W_REG(&cc->pllcontrol_data, 0x11100008);
183 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
184 W_REG(&cc->pllcontrol_data, 0x0c000c06);
185 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
186 W_REG(&cc->pllcontrol_data, 0x03000a08);
187 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
188 W_REG(&cc->pllcontrol_data, 0x00000000);
189 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
190 W_REG(&cc->pllcontrol_data, 0x200005c0);
191 W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
192 W_REG(&cc->pllcontrol_data, 0x88888855);
193
194 tmp = 1 << 10;
195 break;
196
197 default: 205 default:
198 /* bail out */ 206 /* bail out */
199 return; 207 return;
200 } 208 }
201 209
202 tmp |= R_REG(&cc->pmucontrol); 210 bcma_set32(core, CHIPCREGOFFS(pmucontrol), tmp);
203 W_REG(&cc->pmucontrol, tmp);
204} 211}
205 212
206u16 si_pmu_fast_pwrup_delay(struct si_pub *sih) 213u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
@@ -289,12 +296,12 @@ u32 si_pmu_alp_clock(struct si_pub *sih)
289 296
290void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid) 297void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid)
291{ 298{
292 struct chipcregs __iomem *cc; 299 struct bcma_device *cc;
293 uint origidx, intr_val; 300 uint origidx, intr_val;
294 301
295 /* Remember original core before switch to chipc */ 302 /* switch to chipc */
296 cc = (struct chipcregs __iomem *) 303 cc = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
297 ai_switch_core(sih, CC_CORE_ID, &origidx, &intr_val); 304 ai_switch_core(sih, CC_CORE_ID, &origidx, &intr_val);
298 305
299 /* update the pll changes */ 306 /* update the pll changes */
300 si_pmu_spuravoid_pllupdate(sih, cc, spuravoid); 307 si_pmu_spuravoid_pllupdate(sih, cc, spuravoid);
@@ -306,20 +313,16 @@ void si_pmu_spuravoid(struct si_pub *sih, u8 spuravoid)
306/* initialize PMU */ 313/* initialize PMU */
307void si_pmu_init(struct si_pub *sih) 314void si_pmu_init(struct si_pub *sih)
308{ 315{
309 struct chipcregs __iomem *cc; 316 struct bcma_device *core;
310 uint origidx;
311 317
312 /* Remember original core before switch to chipc */ 318 /* select chipc */
313 origidx = ai_coreidx(sih); 319 core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
314 cc = ai_setcoreidx(sih, SI_CC_IDX);
315 320
316 if (ai_get_pmurev(sih) == 1) 321 if (ai_get_pmurev(sih) == 1)
317 AND_REG(&cc->pmucontrol, ~PCTL_NOILP_ON_WAIT); 322 bcma_mask32(core, CHIPCREGOFFS(pmucontrol),
323 ~PCTL_NOILP_ON_WAIT);
318 else if (ai_get_pmurev(sih) >= 2) 324 else if (ai_get_pmurev(sih) >= 2)
319 OR_REG(&cc->pmucontrol, PCTL_NOILP_ON_WAIT); 325 bcma_set32(core, CHIPCREGOFFS(pmucontrol), PCTL_NOILP_ON_WAIT);
320
321 /* Return to original core */
322 ai_setcoreidx(sih, origidx);
323} 326}
324 327
325/* initialize PMU chip controls and other chip level stuff */ 328/* initialize PMU chip controls and other chip level stuff */
@@ -369,13 +372,11 @@ void si_pmu_pll_init(struct si_pub *sih, uint xtalfreq)
369/* initialize PMU resources */ 372/* initialize PMU resources */
370void si_pmu_res_init(struct si_pub *sih) 373void si_pmu_res_init(struct si_pub *sih)
371{ 374{
372 struct chipcregs __iomem *cc; 375 struct bcma_device *core;
373 uint origidx;
374 u32 min_mask = 0, max_mask = 0; 376 u32 min_mask = 0, max_mask = 0;
375 377
376 /* Remember original core before switch to chipc */ 378 /* select to chipc */
377 origidx = ai_coreidx(sih); 379 core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
378 cc = ai_setcoreidx(sih, SI_CC_IDX);
379 380
380 /* Determine min/max rsrc masks */ 381 /* Determine min/max rsrc masks */
381 si_pmu_res_masks(sih, &min_mask, &max_mask); 382 si_pmu_res_masks(sih, &min_mask, &max_mask);
@@ -385,55 +386,50 @@ void si_pmu_res_init(struct si_pub *sih)
385 /* Program max resource mask */ 386 /* Program max resource mask */
386 387
387 if (max_mask) 388 if (max_mask)
388 W_REG(&cc->max_res_mask, max_mask); 389 bcma_write32(core, CHIPCREGOFFS(max_res_mask), max_mask);
389 390
390 /* Program min resource mask */ 391 /* Program min resource mask */
391 392
392 if (min_mask) 393 if (min_mask)
393 W_REG(&cc->min_res_mask, min_mask); 394 bcma_write32(core, CHIPCREGOFFS(min_res_mask), min_mask);
394 395
395 /* Add some delay; allow resources to come up and settle. */ 396 /* Add some delay; allow resources to come up and settle. */
396 mdelay(2); 397 mdelay(2);
397
398 /* Return to original core */
399 ai_setcoreidx(sih, origidx);
400} 398}
401 399
402u32 si_pmu_measure_alpclk(struct si_pub *sih) 400u32 si_pmu_measure_alpclk(struct si_pub *sih)
403{ 401{
404 struct chipcregs __iomem *cc; 402 struct bcma_device *core;
405 uint origidx;
406 u32 alp_khz; 403 u32 alp_khz;
407 404
408 if (ai_get_pmurev(sih) < 10) 405 if (ai_get_pmurev(sih) < 10)
409 return 0; 406 return 0;
410 407
411 /* Remember original core before switch to chipc */ 408 /* Remember original core before switch to chipc */
412 origidx = ai_coreidx(sih); 409 core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
413 cc = ai_setcoreidx(sih, SI_CC_IDX);
414 410
415 if (R_REG(&cc->pmustatus) & PST_EXTLPOAVAIL) { 411 if (bcma_read32(core, CHIPCREGOFFS(pmustatus)) & PST_EXTLPOAVAIL) {
416 u32 ilp_ctr, alp_hz; 412 u32 ilp_ctr, alp_hz;
417 413
418 /* 414 /*
419 * Enable the reg to measure the freq, 415 * Enable the reg to measure the freq,
420 * in case it was disabled before 416 * in case it was disabled before
421 */ 417 */
422 W_REG(&cc->pmu_xtalfreq, 418 bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq),
423 1U << PMU_XTALFREQ_REG_MEASURE_SHIFT); 419 1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
424 420
425 /* Delay for well over 4 ILP clocks */ 421 /* Delay for well over 4 ILP clocks */
426 udelay(1000); 422 udelay(1000);
427 423
428 /* Read the latched number of ALP ticks per 4 ILP ticks */ 424 /* Read the latched number of ALP ticks per 4 ILP ticks */
429 ilp_ctr = 425 ilp_ctr = bcma_read32(core, CHIPCREGOFFS(pmu_xtalfreq)) &
430 R_REG(&cc->pmu_xtalfreq) & PMU_XTALFREQ_REG_ILPCTR_MASK; 426 PMU_XTALFREQ_REG_ILPCTR_MASK;
431 427
432 /* 428 /*
433 * Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT 429 * Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT
434 * bit to save power 430 * bit to save power
435 */ 431 */
436 W_REG(&cc->pmu_xtalfreq, 0); 432 bcma_write32(core, CHIPCREGOFFS(pmu_xtalfreq), 0);
437 433
438 /* Calculate ALP frequency */ 434 /* Calculate ALP frequency */
439 alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4; 435 alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;
@@ -446,8 +442,5 @@ u32 si_pmu_measure_alpclk(struct si_pub *sih)
446 } else 442 } else
447 alp_khz = 0; 443 alp_khz = 0;
448 444
449 /* Return to original core */
450 ai_setcoreidx(sih, origidx);
451
452 return alp_khz; 445 return alp_khz;
453} 446}
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