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authorLinus Torvalds <torvalds@linux-foundation.org>2013-02-28 23:00:40 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2013-02-28 23:00:40 -0500
commit7307c00f335a4e986586b12334696098d2fc2bcd (patch)
tree3427b10ffc57570cf6153056f6ae1dac200cb3b3
parentf8f466c81795a3ed2b8a74c8feebc280aec3db81 (diff)
parent55ccb1a8b4c14c086427fd6b7272448fbd0c4449 (diff)
Merge tag 'late-omap' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late OMAP changes from Olof Johansson: "This branch contains changes for OMAP that came in late during the release staging, close to when the merge window opened. It contains, among other things: - OMAP PM fixes and some patches for audio device integration - OMAP clock fixes related to common clock conversion - A set of patches cleaning up WFI entry and blocking. - A set of fixes and IP block support for PM on TI AM33xx SoCs (Beaglebone, etc) - A set of smaller fixes and cleanups around AM33xx restart and revision detection, as well as removal of some dead code (CONFIG_32K_TIMER_HZ)" * tag 'late-omap' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (34 commits) ARM: omap2: include linux/errno.h in hwmod_reset ARM: OMAP2+: fix some omap_device_build() calls that aren't compiled by default ARM: OMAP4: hwmod data: Enable AESS hwmod device ARM: OMAP4: hwmod data: Update AESS data with memory bank area ARM: OMAP4+: AESS: enable internal auto-gating during initial setup ASoC: TI AESS: add autogating-enable function, callable from architecture code ARM: OMAP2+: hwmod: add enable_preprogram hook ARM: OMAP4: clock data: Add missing clkdm association for dpll_usb ARM: OMAP2+: PM: Fix the dt return condition in pm_late_init() ARM: OMAP2: am33xx-hwmod: Fix "register offset NULL check" bug ARM: OMAP2+: AM33xx: hwmod: add missing HWMOD_NO_IDLEST flags ARM: OMAP: AM33xx hwmod: Add parent-child relationship for PWM subsystem ARM: OMAP: AM33xx hwmod: Corrects PWM subsystem HWMOD entries ARM: DTS: AM33XX: Add nodes for OCMC RAM and WKUP-M3 ARM: OMAP2+: AM33XX: Update the hardreset API ARM: OMAP2+: AM33XX: hwmod: Update the WKUP-M3 hwmod with reset status bit ARM: OMAP2+: AM33XX: hwmod: Fixup cpgmac0 hwmod entry ARM: OMAP2+: AM33XX: hwmod: Update TPTC0 hwmod with the right flags ARM: OMAP2+: AM33XX: hwmod: Register OCMC RAM hwmod ARM: OMAP2+: AM33XX: CM/PRM: Use __ASSEMBLER__ macros in header files ...
Diffstat
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi14
-rw-r--r--arch/arm/mach-omap2/Makefile3
-rw-r--r--arch/arm/mach-omap2/am33xx-restart.c34
-rw-r--r--arch/arm/mach-omap2/am35xx-emac.c3
-rw-r--r--arch/arm/mach-omap2/board-generic.c1
-rw-r--r--arch/arm/mach-omap2/cclock33xx_data.c10
-rw-r--r--arch/arm/mach-omap2/cclock3xxx_data.c10
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c13
-rw-r--r--arch/arm/mach-omap2/clock.h11
-rw-r--r--arch/arm/mach-omap2/cm33xx.c3
-rw-r--r--arch/arm/mach-omap2/cm33xx.h9
-rw-r--r--arch/arm/mach-omap2/common.h8
-rw-r--r--arch/arm/mach-omap2/devices.c2
-rw-r--r--arch/arm/mach-omap2/dpll3xxx.c5
-rw-r--r--arch/arm/mach-omap2/id.c14
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c23
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h8
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_data.c443
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_3xxx_data.c7
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c51
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_reset.c53
-rw-r--r--arch/arm/mach-omap2/pm.c20
-rw-r--r--arch/arm/mach-omap2/pm24xx.c12
-rw-r--r--arch/arm/mach-omap2/pm44xx.c21
-rw-r--r--arch/arm/mach-omap2/prm33xx.c11
-rw-r--r--arch/arm/mach-omap2/prm33xx.h4
-rw-r--r--arch/arm/mach-omap2/sleep24xx.S19
-rw-r--r--arch/arm/mach-omap2/soc.h1
-rw-r--r--arch/arm/mach-omap2/sr_device.c2
-rw-r--r--arch/arm/plat-omap/Kconfig9
-rw-r--r--arch/arm/plat-omap/include/plat/timex.h8
-rw-r--r--drivers/media/platform/omap3isp/isp.c18
-rw-r--r--drivers/media/platform/omap3isp/isp.h8
-rw-r--r--include/sound/aess.h53
35 files changed, 633 insertions, 279 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0e16cca1d011..5b714695b01b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1676,7 +1676,6 @@ config HZ
1676 int 1676 int
1677 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ 1677 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1678 ARCH_S5PV210 || ARCH_EXYNOS4 1678 ARCH_S5PV210 || ARCH_EXYNOS4
1679 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1680 default AT91_TIMER_HZ if ARCH_AT91 1679 default AT91_TIMER_HZ if ARCH_AT91
1681 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE 1680 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1682 default 100 1681 default 100
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index c2f14e875eb6..0957645b73af 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -385,5 +385,19 @@
385 mac-address = [ 00 00 00 00 00 00 ]; 385 mac-address = [ 00 00 00 00 00 00 ];
386 }; 386 };
387 }; 387 };
388
389 ocmcram: ocmcram@40300000 {
390 compatible = "ti,am3352-ocmcram";
391 reg = <0x40300000 0x10000>;
392 ti,hwmods = "ocmcram";
393 ti,no_idle_on_suspend;
394 };
395
396 wkup_m3: wkup_m3@44d00000 {
397 compatible = "ti,am3353-wkup-m3";
398 reg = <0x44d00000 0x4000 /* M3 UMEM */
399 0x44d80000 0x2000>; /* M3 DMEM */
400 ti,hwmods = "wkup_m3";
401 };
388 }; 402 };
389}; 403};
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index ff528df70119..b068b7fe99ef 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -11,7 +11,7 @@ obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \
11 omap_device.o sram.o 11 omap_device.o sram.o
12 12
13omap-2-3-common = irq.o 13omap-2-3-common = irq.o
14hwmod-common = omap_hwmod.o \ 14hwmod-common = omap_hwmod.o omap_hwmod_reset.o \
15 omap_hwmod_common_data.o 15 omap_hwmod_common_data.o
16clock-common = clock.o clock_common_data.o \ 16clock-common = clock.o clock_common_data.o \
17 clkt_dpll.o clkt_clksel.o 17 clkt_dpll.o clkt_clksel.o
@@ -56,6 +56,7 @@ AFLAGS_sram34xx.o :=-Wa,-march=armv7-a
56# Restart code (OMAP4/5 currently in omap4-common.c) 56# Restart code (OMAP4/5 currently in omap4-common.c)
57obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o 57obj-$(CONFIG_SOC_OMAP2420) += omap2-restart.o
58obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o 58obj-$(CONFIG_SOC_OMAP2430) += omap2-restart.o
59obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o
59obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o 60obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o
60 61
61# Pin multiplexing 62# Pin multiplexing
diff --git a/arch/arm/mach-omap2/am33xx-restart.c b/arch/arm/mach-omap2/am33xx-restart.c
new file mode 100644
index 000000000000..88e4fa8af031
--- /dev/null
+++ b/arch/arm/mach-omap2/am33xx-restart.c
@@ -0,0 +1,34 @@
1/*
2 * am33xx-restart.c - Code common to all AM33xx machines.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8#include <linux/kernel.h>
9
10#include "common.h"
11#include "prm-regbits-33xx.h"
12#include "prm33xx.h"
13
14/**
15 * am3xx_restart - trigger a software restart of the SoC
16 * @mode: the "reboot mode", see arch/arm/kernel/{setup,process}.c
17 * @cmd: passed from the userspace program rebooting the system (if provided)
18 *
19 * Resets the SoC. For @cmd, see the 'reboot' syscall in
20 * kernel/sys.c. No return value.
21 */
22void am33xx_restart(char mode, const char *cmd)
23{
24 /* TODO: Handle mode and cmd if necessary */
25
26 am33xx_prm_rmw_reg_bits(AM33XX_GLOBAL_WARM_SW_RST_MASK,
27 AM33XX_GLOBAL_WARM_SW_RST_MASK,
28 AM33XX_PRM_DEVICE_MOD,
29 AM33XX_PRM_RSTCTRL_OFFSET);
30
31 /* OCP barrier */
32 (void)am33xx_prm_read_reg(AM33XX_PRM_DEVICE_MOD,
33 AM33XX_PRM_RSTCTRL_OFFSET);
34}
diff --git a/arch/arm/mach-omap2/am35xx-emac.c b/arch/arm/mach-omap2/am35xx-emac.c
index a00d39107a21..25b79a297365 100644
--- a/arch/arm/mach-omap2/am35xx-emac.c
+++ b/arch/arm/mach-omap2/am35xx-emac.c
@@ -62,8 +62,7 @@ static int __init omap_davinci_emac_dev_init(struct omap_hwmod *oh,
62{ 62{
63 struct platform_device *pdev; 63 struct platform_device *pdev;
64 64
65 pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len, 65 pdev = omap_device_build(oh->class->name, 0, oh, pdata, pdata_len);
66 false);
67 if (IS_ERR(pdev)) { 66 if (IS_ERR(pdev)) {
68 WARN(1, "Can't build omap_device for %s:%s.\n", 67 WARN(1, "Can't build omap_device for %s:%s.\n",
69 oh->class->name, oh->name); 68 oh->class->name, oh->name);
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index 2590463e4b57..0274ff7a2a2b 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -140,6 +140,7 @@ DT_MACHINE_START(AM33XX_DT, "Generic AM33XX (Flattened Device Tree)")
140 .init_machine = omap_generic_init, 140 .init_machine = omap_generic_init,
141 .init_time = omap3_am33xx_gptimer_timer_init, 141 .init_time = omap3_am33xx_gptimer_timer_init,
142 .dt_compat = am33xx_boards_compat, 142 .dt_compat = am33xx_boards_compat,
143 .restart = am33xx_restart,
143MACHINE_END 144MACHINE_END
144#endif 145#endif
145 146
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index ea64ad606759..476b82066cb6 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -284,9 +284,10 @@ DEFINE_STRUCT_CLK(dpll_disp_ck, dpll_core_ck_parents, dpll_ddr_ck_ops);
284 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2 284 * TODO: Add clksel here (sys_clkin, CORE_CLKOUTM6, PER_CLKOUTM2
285 * and ALT_CLK1/2) 285 * and ALT_CLK1/2)
286 */ 286 */
287DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck, 0x0, 287DEFINE_CLK_DIVIDER(dpll_disp_m2_ck, "dpll_disp_ck", &dpll_disp_ck,
288 AM33XX_CM_DIV_M2_DPLL_DISP, AM33XX_DPLL_CLKOUT_DIV_SHIFT, 288 CLK_SET_RATE_PARENT, AM33XX_CM_DIV_M2_DPLL_DISP,
289 AM33XX_DPLL_CLKOUT_DIV_WIDTH, CLK_DIVIDER_ONE_BASED, NULL); 289 AM33XX_DPLL_CLKOUT_DIV_SHIFT, AM33XX_DPLL_CLKOUT_DIV_WIDTH,
290 CLK_DIVIDER_ONE_BASED, NULL);
290 291
291/* DPLL_PER */ 292/* DPLL_PER */
292static struct dpll_data dpll_per_dd = { 293static struct dpll_data dpll_per_dd = {
@@ -723,7 +724,8 @@ static struct clk_hw_omap lcd_gclk_hw = {
723 .clksel_mask = AM33XX_CLKSEL_0_1_MASK, 724 .clksel_mask = AM33XX_CLKSEL_0_1_MASK,
724}; 725};
725 726
726DEFINE_STRUCT_CLK(lcd_gclk, lcd_ck_parents, gpio_fck_ops); 727DEFINE_STRUCT_CLK_FLAGS(lcd_gclk, lcd_ck_parents,
728 gpio_fck_ops, CLK_SET_RATE_PARENT);
727 729
728DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2); 730DEFINE_CLK_FIXED_FACTOR(mmc_clk, "dpll_per_m2_ck", &dpll_per_m2_ck, 0x0, 1, 2);
729 731
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 6ef87580c33f..4579c3c5338f 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -426,6 +426,7 @@ static struct clk dpll4_m5x2_ck_3630 = {
426 .parent_names = dpll4_m5x2_ck_parent_names, 426 .parent_names = dpll4_m5x2_ck_parent_names,
427 .num_parents = ARRAY_SIZE(dpll4_m5x2_ck_parent_names), 427 .num_parents = ARRAY_SIZE(dpll4_m5x2_ck_parent_names),
428 .ops = &dpll4_m5x2_ck_3630_ops, 428 .ops = &dpll4_m5x2_ck_3630_ops,
429 .flags = CLK_SET_RATE_PARENT,
429}; 430};
430 431
431static struct clk cam_mclk; 432static struct clk cam_mclk;
@@ -443,7 +444,14 @@ static struct clk_hw_omap cam_mclk_hw = {
443 .clkdm_name = "cam_clkdm", 444 .clkdm_name = "cam_clkdm",
444}; 445};
445 446
446DEFINE_STRUCT_CLK(cam_mclk, cam_mclk_parent_names, aes2_ick_ops); 447static struct clk cam_mclk = {
448 .name = "cam_mclk",
449 .hw = &cam_mclk_hw.hw,
450 .parent_names = cam_mclk_parent_names,
451 .num_parents = ARRAY_SIZE(cam_mclk_parent_names),
452 .ops = &aes2_ick_ops,
453 .flags = CLK_SET_RATE_PARENT,
454};
447 455
448static const struct clksel_rate clkout2_src_core_rates[] = { 456static const struct clksel_rate clkout2_src_core_rates[] = {
449 { .div = 1, .val = 0, .flags = RATE_IN_3XXX }, 457 { .div = 1, .val = 0, .flags = RATE_IN_3XXX },
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index cebe2b31943e..3d58f335f173 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -605,15 +605,26 @@ static const char *dpll_usb_ck_parents[] = {
605 605
606static struct clk dpll_usb_ck; 606static struct clk dpll_usb_ck;
607 607
608static const struct clk_ops dpll_usb_ck_ops = {
609 .enable = &omap3_noncore_dpll_enable,
610 .disable = &omap3_noncore_dpll_disable,
611 .recalc_rate = &omap3_dpll_recalc,
612 .round_rate = &omap2_dpll_round_rate,
613 .set_rate = &omap3_noncore_dpll_set_rate,
614 .get_parent = &omap2_init_dpll_parent,
615 .init = &omap2_init_clk_clkdm,
616};
617
608static struct clk_hw_omap dpll_usb_ck_hw = { 618static struct clk_hw_omap dpll_usb_ck_hw = {
609 .hw = { 619 .hw = {
610 .clk = &dpll_usb_ck, 620 .clk = &dpll_usb_ck,
611 }, 621 },
612 .dpll_data = &dpll_usb_dd, 622 .dpll_data = &dpll_usb_dd,
623 .clkdm_name = "l3_init_clkdm",
613 .ops = &clkhwops_omap3_dpll, 624 .ops = &clkhwops_omap3_dpll,
614}; 625};
615 626
616DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_ck_ops); 627DEFINE_STRUCT_CLK(dpll_usb_ck, dpll_usb_ck_parents, dpll_usb_ck_ops);
617 628
618static const char *dpll_usb_clkdcoldo_ck_parents[] = { 629static const char *dpll_usb_clkdcoldo_ck_parents[] = {
619 "dpll_usb_ck", 630 "dpll_usb_ck",
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index b40204837bd7..60ddd8612b4d 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -65,6 +65,17 @@ struct clockdomain;
65 .ops = &_clkops_name, \ 65 .ops = &_clkops_name, \
66 }; 66 };
67 67
68#define DEFINE_STRUCT_CLK_FLAGS(_name, _parent_array_name, \
69 _clkops_name, _flags) \
70 static struct clk _name = { \
71 .name = #_name, \
72 .hw = &_name##_hw.hw, \
73 .parent_names = _parent_array_name, \
74 .num_parents = ARRAY_SIZE(_parent_array_name), \
75 .ops = &_clkops_name, \
76 .flags = _flags, \
77 };
78
68#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \ 79#define DEFINE_STRUCT_CLK_HW_OMAP(_name, _clkdm_name) \
69 static struct clk_hw_omap _name##_hw = { \ 80 static struct clk_hw_omap _name##_hw = { \
70 .hw = { \ 81 .hw = { \
diff --git a/arch/arm/mach-omap2/cm33xx.c b/arch/arm/mach-omap2/cm33xx.c
index 058ce3c0873e..325a51576576 100644
--- a/arch/arm/mach-omap2/cm33xx.c
+++ b/arch/arm/mach-omap2/cm33xx.c
@@ -241,9 +241,6 @@ int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs, u16 clkctrl_offs)
241{ 241{
242 int i = 0; 242 int i = 0;
243 243
244 if (!clkctrl_offs)
245 return 0;
246
247 omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs), 244 omap_test_timeout(_is_module_ready(inst, cdoffs, clkctrl_offs),
248 MAX_MODULE_READY_TIME, i); 245 MAX_MODULE_READY_TIME, i);
249 246
diff --git a/arch/arm/mach-omap2/cm33xx.h b/arch/arm/mach-omap2/cm33xx.h
index 5fa0b62e1a79..64f4bafe7bd9 100644
--- a/arch/arm/mach-omap2/cm33xx.h
+++ b/arch/arm/mach-omap2/cm33xx.h
@@ -17,16 +17,11 @@
17#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H 17#ifndef __ARCH_ARM_MACH_OMAP2_CM_33XX_H
18#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H 18#define __ARCH_ARM_MACH_OMAP2_CM_33XX_H
19 19
20#include <linux/delay.h>
21#include <linux/errno.h>
22#include <linux/err.h>
23#include <linux/io.h>
24
25#include "common.h" 20#include "common.h"
26 21
27#include "cm.h" 22#include "cm.h"
28#include "cm-regbits-33xx.h" 23#include "cm-regbits-33xx.h"
29#include "cm33xx.h" 24#include "iomap.h"
30 25
31/* CM base address */ 26/* CM base address */
32#define AM33XX_CM_BASE 0x44e00000 27#define AM33XX_CM_BASE 0x44e00000
@@ -381,6 +376,7 @@
381#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020) 376#define AM33XX_CM_CEFUSE_CEFUSE_CLKCTRL AM33XX_CM_REGADDR(AM33XX_CM_CEFUSE_MOD, 0x0020)
382 377
383 378
379#ifndef __ASSEMBLER__
384extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs); 380extern bool am33xx_cm_is_clkdm_in_hwsup(s16 inst, u16 cdoffs);
385extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs); 381extern void am33xx_cm_clkdm_enable_hwsup(s16 inst, u16 cdoffs);
386extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs); 382extern void am33xx_cm_clkdm_disable_hwsup(s16 inst, u16 cdoffs);
@@ -417,4 +413,5 @@ static inline int am33xx_cm_wait_module_ready(u16 inst, s16 cdoffs,
417} 413}
418#endif 414#endif
419 415
416#endif /* ASSEMBLER */
420#endif 417#endif
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index b4350274361b..0a6b9c7a63da 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -119,6 +119,14 @@ static inline void omap2xxx_restart(char mode, const char *cmd)
119} 119}
120#endif 120#endif
121 121
122#ifdef CONFIG_SOC_AM33XX
123void am33xx_restart(char mode, const char *cmd);
124#else
125static inline void am33xx_restart(char mode, const char *cmd)
126{
127}
128#endif
129
122#ifdef CONFIG_ARCH_OMAP3 130#ifdef CONFIG_ARCH_OMAP3
123void omap3xxx_restart(char mode, const char *cmd); 131void omap3xxx_restart(char mode, const char *cmd);
124#else 132#else
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 142d9c616f1b..1ec7f0597710 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -426,7 +426,7 @@ static void __init omap_init_hdmi_audio(void)
426 return; 426 return;
427 } 427 }
428 428
429 pdev = omap_device_build("omap-hdmi-audio-dai", -1, oh, NULL, 0, 0); 429 pdev = omap_device_build("omap-hdmi-audio-dai", -1, oh, NULL, 0);
430 WARN(IS_ERR(pdev), 430 WARN(IS_ERR(pdev),
431 "Can't build omap_device for omap-hdmi-audio-dai.\n"); 431 "Can't build omap_device for omap-hdmi-audio-dai.\n");
432 432
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 0a02aab5df67..3aed4b0b9563 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -500,8 +500,9 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
500 if (dd->last_rounded_rate == 0) 500 if (dd->last_rounded_rate == 0)
501 return -EINVAL; 501 return -EINVAL;
502 502
503 /* No freqsel on OMAP4 and OMAP3630 */ 503 /* No freqsel on AM335x, OMAP4 and OMAP3630 */
504 if (!cpu_is_omap44xx() && !cpu_is_omap3630()) { 504 if (!soc_is_am33xx() && !cpu_is_omap44xx() &&
505 !cpu_is_omap3630()) {
505 freqsel = _omap3_dpll_compute_freqsel(clk, 506 freqsel = _omap3_dpll_compute_freqsel(clk,
506 dd->last_rounded_n); 507 dd->last_rounded_n);
507 WARN_ON(!freqsel); 508 WARN_ON(!freqsel);
diff --git a/arch/arm/mach-omap2/id.c b/arch/arm/mach-omap2/id.c
index 45cc7ed4dd58..8a68f1ec66b9 100644
--- a/arch/arm/mach-omap2/id.c
+++ b/arch/arm/mach-omap2/id.c
@@ -399,8 +399,18 @@ void __init omap3xxx_check_revision(void)
399 } 399 }
400 break; 400 break;
401 case 0xb944: 401 case 0xb944:
402 omap_revision = AM335X_REV_ES1_0; 402 switch (rev) {
403 cpu_rev = "1.0"; 403 case 0:
404 omap_revision = AM335X_REV_ES1_0;
405 cpu_rev = "1.0";
406 break;
407 case 1:
408 /* FALLTHROUGH */
409 default:
410 omap_revision = AM335X_REV_ES2_0;
411 cpu_rev = "2.0";
412 break;
413 }
404 break; 414 break;
405 case 0xb8f2: 415 case 0xb8f2:
406 switch (rev) { 416 switch (rev) {
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index a8984989dec8..c2c798c08c2b 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -2055,6 +2055,23 @@ static int _omap4_get_context_lost(struct omap_hwmod *oh)
2055} 2055}
2056 2056
2057/** 2057/**
2058 * _enable_preprogram - Pre-program an IP block during the _enable() process
2059 * @oh: struct omap_hwmod *
2060 *
2061 * Some IP blocks (such as AESS) require some additional programming
2062 * after enable before they can enter idle. If a function pointer to
2063 * do so is present in the hwmod data, then call it and pass along the
2064 * return value; otherwise, return 0.
2065 */
2066static int __init _enable_preprogram(struct omap_hwmod *oh)
2067{
2068 if (!oh->class->enable_preprogram)
2069 return 0;
2070
2071 return oh->class->enable_preprogram(oh);
2072}
2073
2074/**
2058 * _enable - enable an omap_hwmod 2075 * _enable - enable an omap_hwmod
2059 * @oh: struct omap_hwmod * 2076 * @oh: struct omap_hwmod *
2060 * 2077 *
@@ -2160,6 +2177,7 @@ static int _enable(struct omap_hwmod *oh)
2160 _update_sysc_cache(oh); 2177 _update_sysc_cache(oh);
2161 _enable_sysc(oh); 2178 _enable_sysc(oh);
2162 } 2179 }
2180 r = _enable_preprogram(oh);
2163 } else { 2181 } else {
2164 if (soc_ops.disable_module) 2182 if (soc_ops.disable_module)
2165 soc_ops.disable_module(oh); 2183 soc_ops.disable_module(oh);
@@ -3049,11 +3067,8 @@ static int _am33xx_assert_hardreset(struct omap_hwmod *oh,
3049static int _am33xx_deassert_hardreset(struct omap_hwmod *oh, 3067static int _am33xx_deassert_hardreset(struct omap_hwmod *oh,
3050 struct omap_hwmod_rst_info *ohri) 3068 struct omap_hwmod_rst_info *ohri)
3051{ 3069{
3052 if (ohri->st_shift)
3053 pr_err("omap_hwmod: %s: %s: hwmod data error: OMAP4 does not support st_shift\n",
3054 oh->name, ohri->name);
3055
3056 return am33xx_prm_deassert_hardreset(ohri->rst_shift, 3070 return am33xx_prm_deassert_hardreset(ohri->rst_shift,
3071 ohri->st_shift,
3057 oh->clkdm->pwrdm.ptr->prcm_offs, 3072 oh->clkdm->pwrdm.ptr->prcm_offs,
3058 oh->prcm.omap4.rstctrl_offs, 3073 oh->prcm.omap4.rstctrl_offs,
3059 oh->prcm.omap4.rstst_offs); 3074 oh->prcm.omap4.rstst_offs);
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index 80c00e706d69..d43d9b608eda 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -510,6 +510,7 @@ struct omap_hwmod_omap4_prcm {
510 * @rev: revision of the IP class 510 * @rev: revision of the IP class
511 * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown 511 * @pre_shutdown: ptr to fn to be executed immediately prior to device shutdown
512 * @reset: ptr to fn to be executed in place of the standard hwmod reset fn 512 * @reset: ptr to fn to be executed in place of the standard hwmod reset fn
513 * @enable_preprogram: ptr to fn to be executed during device enable
513 * 514 *
514 * Represent the class of a OMAP hardware "modules" (e.g. timer, 515 * Represent the class of a OMAP hardware "modules" (e.g. timer,
515 * smartreflex, gpio, uart...) 516 * smartreflex, gpio, uart...)
@@ -533,6 +534,7 @@ struct omap_hwmod_class {
533 u32 rev; 534 u32 rev;
534 int (*pre_shutdown)(struct omap_hwmod *oh); 535 int (*pre_shutdown)(struct omap_hwmod *oh);
535 int (*reset)(struct omap_hwmod *oh); 536 int (*reset)(struct omap_hwmod *oh);
537 int (*enable_preprogram)(struct omap_hwmod *oh);
536}; 538};
537 539
538/** 540/**
@@ -680,6 +682,12 @@ extern void __init omap_hwmod_init(void);
680const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh); 682const char *omap_hwmod_get_main_clk(struct omap_hwmod *oh);
681 683
682/* 684/*
685 *
686 */
687
688extern int omap_hwmod_aess_preprogram(struct omap_hwmod *oh);
689
690/*
683 * Chip variant-specific hwmod init routines - XXX should be converted 691 * Chip variant-specific hwmod init routines - XXX should be converted
684 * to use initcalls once the initial boot ordering is straightened out 692 * to use initcalls once the initial boot ordering is straightened out
685 */ 693 */
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index 646c14d9fdb9..26eee4a556ad 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -262,13 +262,15 @@ static struct omap_hwmod am33xx_wkup_m3_hwmod = {
262 .name = "wkup_m3", 262 .name = "wkup_m3",
263 .class = &am33xx_wkup_m3_hwmod_class, 263 .class = &am33xx_wkup_m3_hwmod_class,
264 .clkdm_name = "l4_wkup_aon_clkdm", 264 .clkdm_name = "l4_wkup_aon_clkdm",
265 .flags = HWMOD_INIT_NO_RESET, /* Keep hardreset asserted */ 265 /* Keep hardreset asserted */
266 .flags = HWMOD_INIT_NO_RESET | HWMOD_NO_IDLEST,
266 .mpu_irqs = am33xx_wkup_m3_irqs, 267 .mpu_irqs = am33xx_wkup_m3_irqs,
267 .main_clk = "dpll_core_m4_div2_ck", 268 .main_clk = "dpll_core_m4_div2_ck",
268 .prcm = { 269 .prcm = {
269 .omap4 = { 270 .omap4 = {
270 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET, 271 .clkctrl_offs = AM33XX_CM_WKUP_WKUP_M3_CLKCTRL_OFFSET,
271 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET, 272 .rstctrl_offs = AM33XX_RM_WKUP_RSTCTRL_OFFSET,
273 .rstst_offs = AM33XX_RM_WKUP_RSTST_OFFSET,
272 .modulemode = MODULEMODE_SWCTRL, 274 .modulemode = MODULEMODE_SWCTRL,
273 }, 275 },
274 }, 276 },
@@ -414,7 +416,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
414 * - cEFUSE (doesn't fall under any ocp_if) 416 * - cEFUSE (doesn't fall under any ocp_if)
415 * - clkdiv32k 417 * - clkdiv32k
416 * - debugss 418 * - debugss
417 * - ocmc ram
418 * - ocp watch point 419 * - ocp watch point
419 * - aes0 420 * - aes0
420 * - sha0 421 * - sha0
@@ -481,25 +482,6 @@ static struct omap_hwmod am33xx_debugss_hwmod = {
481 }, 482 },
482}; 483};
483 484
484/* ocmcram */
485static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
486 .name = "ocmcram",
487};
488
489static struct omap_hwmod am33xx_ocmcram_hwmod = {
490 .name = "ocmcram",
491 .class = &am33xx_ocmcram_hwmod_class,
492 .clkdm_name = "l3_clkdm",
493 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
494 .main_clk = "l3_gclk",
495 .prcm = {
496 .omap4 = {
497 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
498 .modulemode = MODULEMODE_SWCTRL,
499 },
500 },
501};
502
503/* ocpwp */ 485/* ocpwp */
504static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { 486static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
505 .name = "ocpwp", 487 .name = "ocpwp",
@@ -570,6 +552,25 @@ static struct omap_hwmod am33xx_sha0_hwmod = {
570 552
571#endif 553#endif
572 554
555/* ocmcram */
556static struct omap_hwmod_class am33xx_ocmcram_hwmod_class = {
557 .name = "ocmcram",
558};
559
560static struct omap_hwmod am33xx_ocmcram_hwmod = {
561 .name = "ocmcram",
562 .class = &am33xx_ocmcram_hwmod_class,
563 .clkdm_name = "l3_clkdm",
564 .flags = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET),
565 .main_clk = "l3_gclk",
566 .prcm = {
567 .omap4 = {
568 .clkctrl_offs = AM33XX_CM_PER_OCMCRAM_CLKCTRL_OFFSET,
569 .modulemode = MODULEMODE_SWCTRL,
570 },
571 },
572};
573
573/* 'smartreflex' class */ 574/* 'smartreflex' class */
574static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { 575static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
575 .name = "smartreflex", 576 .name = "smartreflex",
@@ -783,9 +784,7 @@ static struct omap_hwmod am33xx_elm_hwmod = {
783 }, 784 },
784}; 785};
785 786
786/* 787/* pwmss */
787 * 'epwmss' class: ecap0,1,2, ehrpwm0,1,2
788 */
789static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = { 788static struct omap_hwmod_class_sysconfig am33xx_epwmss_sysc = {
790 .rev_offs = 0x0, 789 .rev_offs = 0x0,
791 .sysc_offs = 0x4, 790 .sysc_offs = 0x4,
@@ -801,18 +800,23 @@ static struct omap_hwmod_class am33xx_epwmss_hwmod_class = {
801 .sysc = &am33xx_epwmss_sysc, 800 .sysc = &am33xx_epwmss_sysc,
802}; 801};
803 802
804/* ehrpwm0 */ 803static struct omap_hwmod_class am33xx_ecap_hwmod_class = {
805static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = { 804 .name = "ecap",
806 { .name = "int", .irq = 86 + OMAP_INTC_START, },
807 { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
808 { .irq = -1 },
809}; 805};
810 806
811static struct omap_hwmod am33xx_ehrpwm0_hwmod = { 807static struct omap_hwmod_class am33xx_eqep_hwmod_class = {
812 .name = "ehrpwm0", 808 .name = "eqep",
809};
810
811static struct omap_hwmod_class am33xx_ehrpwm_hwmod_class = {
812 .name = "ehrpwm",
813};
814
815/* epwmss0 */
816static struct omap_hwmod am33xx_epwmss0_hwmod = {
817 .name = "epwmss0",
813 .class = &am33xx_epwmss_hwmod_class, 818 .class = &am33xx_epwmss_hwmod_class,
814 .clkdm_name = "l4ls_clkdm", 819 .clkdm_name = "l4ls_clkdm",
815 .mpu_irqs = am33xx_ehrpwm0_irqs,
816 .main_clk = "l4ls_gclk", 820 .main_clk = "l4ls_gclk",
817 .prcm = { 821 .prcm = {
818 .omap4 = { 822 .omap4 = {
@@ -822,63 +826,58 @@ static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
822 }, 826 },
823}; 827};
824 828
825/* ehrpwm1 */ 829/* ecap0 */
826static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = { 830static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = {
827 { .name = "int", .irq = 87 + OMAP_INTC_START, }, 831 { .irq = 31 + OMAP_INTC_START, },
828 { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
829 { .irq = -1 }, 832 { .irq = -1 },
830}; 833};
831 834
832static struct omap_hwmod am33xx_ehrpwm1_hwmod = { 835static struct omap_hwmod am33xx_ecap0_hwmod = {
833 .name = "ehrpwm1", 836 .name = "ecap0",
834 .class = &am33xx_epwmss_hwmod_class, 837 .class = &am33xx_ecap_hwmod_class,
835 .clkdm_name = "l4ls_clkdm", 838 .clkdm_name = "l4ls_clkdm",
836 .mpu_irqs = am33xx_ehrpwm1_irqs, 839 .mpu_irqs = am33xx_ecap0_irqs,
837 .main_clk = "l4ls_gclk", 840 .main_clk = "l4ls_gclk",
838 .prcm = {
839 .omap4 = {
840 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
841 .modulemode = MODULEMODE_SWCTRL,
842 },
843 },
844}; 841};
845 842
846/* ehrpwm2 */ 843/* eqep0 */
847static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = { 844static struct omap_hwmod_irq_info am33xx_eqep0_irqs[] = {
848 { .name = "int", .irq = 39 + OMAP_INTC_START, }, 845 { .irq = 79 + OMAP_INTC_START, },
849 { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
850 { .irq = -1 }, 846 { .irq = -1 },
851}; 847};
852 848
853static struct omap_hwmod am33xx_ehrpwm2_hwmod = { 849static struct omap_hwmod am33xx_eqep0_hwmod = {
854 .name = "ehrpwm2", 850 .name = "eqep0",
855 .class = &am33xx_epwmss_hwmod_class, 851 .class = &am33xx_eqep_hwmod_class,
856 .clkdm_name = "l4ls_clkdm", 852 .clkdm_name = "l4ls_clkdm",
857 .mpu_irqs = am33xx_ehrpwm2_irqs, 853 .mpu_irqs = am33xx_eqep0_irqs,
858 .main_clk = "l4ls_gclk", 854 .main_clk = "l4ls_gclk",
859 .prcm = {
860 .omap4 = {
861 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
862 .modulemode = MODULEMODE_SWCTRL,
863 },
864 },
865}; 855};
866 856
867/* ecap0 */ 857/* ehrpwm0 */
868static struct omap_hwmod_irq_info am33xx_ecap0_irqs[] = { 858static struct omap_hwmod_irq_info am33xx_ehrpwm0_irqs[] = {
869 { .irq = 31 + OMAP_INTC_START, }, 859 { .name = "int", .irq = 86 + OMAP_INTC_START, },
860 { .name = "tzint", .irq = 58 + OMAP_INTC_START, },
870 { .irq = -1 }, 861 { .irq = -1 },
871}; 862};
872 863
873static struct omap_hwmod am33xx_ecap0_hwmod = { 864static struct omap_hwmod am33xx_ehrpwm0_hwmod = {
874 .name = "ecap0", 865 .name = "ehrpwm0",
866 .class = &am33xx_ehrpwm_hwmod_class,
867 .clkdm_name = "l4ls_clkdm",
868 .mpu_irqs = am33xx_ehrpwm0_irqs,
869 .main_clk = "l4ls_gclk",
870};
871
872/* epwmss1 */
873static struct omap_hwmod am33xx_epwmss1_hwmod = {
874 .name = "epwmss1",
875 .class = &am33xx_epwmss_hwmod_class, 875 .class = &am33xx_epwmss_hwmod_class,
876 .clkdm_name = "l4ls_clkdm", 876 .clkdm_name = "l4ls_clkdm",
877 .mpu_irqs = am33xx_ecap0_irqs,
878 .main_clk = "l4ls_gclk", 877 .main_clk = "l4ls_gclk",
879 .prcm = { 878 .prcm = {
880 .omap4 = { 879 .omap4 = {
881 .clkctrl_offs = AM33XX_CM_PER_EPWMSS0_CLKCTRL_OFFSET, 880 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET,
882 .modulemode = MODULEMODE_SWCTRL, 881 .modulemode = MODULEMODE_SWCTRL,
883 }, 882 },
884 }, 883 },
@@ -892,13 +891,50 @@ static struct omap_hwmod_irq_info am33xx_ecap1_irqs[] = {
892 891
893static struct omap_hwmod am33xx_ecap1_hwmod = { 892static struct omap_hwmod am33xx_ecap1_hwmod = {
894 .name = "ecap1", 893 .name = "ecap1",
895 .class = &am33xx_epwmss_hwmod_class, 894 .class = &am33xx_ecap_hwmod_class,
896 .clkdm_name = "l4ls_clkdm", 895 .clkdm_name = "l4ls_clkdm",
897 .mpu_irqs = am33xx_ecap1_irqs, 896 .mpu_irqs = am33xx_ecap1_irqs,
898 .main_clk = "l4ls_gclk", 897 .main_clk = "l4ls_gclk",
898};
899
900/* eqep1 */
901static struct omap_hwmod_irq_info am33xx_eqep1_irqs[] = {
902 { .irq = 88 + OMAP_INTC_START, },
903 { .irq = -1 },
904};
905
906static struct omap_hwmod am33xx_eqep1_hwmod = {
907 .name = "eqep1",
908 .class = &am33xx_eqep_hwmod_class,
909 .clkdm_name = "l4ls_clkdm",
910 .mpu_irqs = am33xx_eqep1_irqs,
911 .main_clk = "l4ls_gclk",
912};
913
914/* ehrpwm1 */
915static struct omap_hwmod_irq_info am33xx_ehrpwm1_irqs[] = {
916 { .name = "int", .irq = 87 + OMAP_INTC_START, },
917 { .name = "tzint", .irq = 59 + OMAP_INTC_START, },
918 { .irq = -1 },
919};
920
921static struct omap_hwmod am33xx_ehrpwm1_hwmod = {
922 .name = "ehrpwm1",
923 .class = &am33xx_ehrpwm_hwmod_class,
924 .clkdm_name = "l4ls_clkdm",
925 .mpu_irqs = am33xx_ehrpwm1_irqs,
926 .main_clk = "l4ls_gclk",
927};
928
929/* epwmss2 */
930static struct omap_hwmod am33xx_epwmss2_hwmod = {
931 .name = "epwmss2",
932 .class = &am33xx_epwmss_hwmod_class,
933 .clkdm_name = "l4ls_clkdm",
934 .main_clk = "l4ls_gclk",
899 .prcm = { 935 .prcm = {
900 .omap4 = { 936 .omap4 = {
901 .clkctrl_offs = AM33XX_CM_PER_EPWMSS1_CLKCTRL_OFFSET, 937 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
902 .modulemode = MODULEMODE_SWCTRL, 938 .modulemode = MODULEMODE_SWCTRL,
903 }, 939 },
904 }, 940 },
@@ -912,16 +948,39 @@ static struct omap_hwmod_irq_info am33xx_ecap2_irqs[] = {
912 948
913static struct omap_hwmod am33xx_ecap2_hwmod = { 949static struct omap_hwmod am33xx_ecap2_hwmod = {
914 .name = "ecap2", 950 .name = "ecap2",
951 .class = &am33xx_ecap_hwmod_class,
952 .clkdm_name = "l4ls_clkdm",
915 .mpu_irqs = am33xx_ecap2_irqs, 953 .mpu_irqs = am33xx_ecap2_irqs,
916 .class = &am33xx_epwmss_hwmod_class, 954 .main_clk = "l4ls_gclk",
955};
956
957/* eqep2 */
958static struct omap_hwmod_irq_info am33xx_eqep2_irqs[] = {
959 { .irq = 89 + OMAP_INTC_START, },
960 { .irq = -1 },
961};
962
963static struct omap_hwmod am33xx_eqep2_hwmod = {
964 .name = "eqep2",
965 .class = &am33xx_eqep_hwmod_class,
917 .clkdm_name = "l4ls_clkdm", 966 .clkdm_name = "l4ls_clkdm",
967 .mpu_irqs = am33xx_eqep2_irqs,
968 .main_clk = "l4ls_gclk",
969};
970
971/* ehrpwm2 */
972static struct omap_hwmod_irq_info am33xx_ehrpwm2_irqs[] = {
973 { .name = "int", .irq = 39 + OMAP_INTC_START, },
974 { .name = "tzint", .irq = 60 + OMAP_INTC_START, },
975 { .irq = -1 },
976};
977
978static struct omap_hwmod am33xx_ehrpwm2_hwmod = {
979 .name = "ehrpwm2",
980 .class = &am33xx_ehrpwm_hwmod_class,
981 .clkdm_name = "l4ls_clkdm",
982 .mpu_irqs = am33xx_ehrpwm2_irqs,
918 .main_clk = "l4ls_gclk", 983 .main_clk = "l4ls_gclk",
919 .prcm = {
920 .omap4 = {
921 .clkctrl_offs = AM33XX_CM_PER_EPWMSS2_CLKCTRL_OFFSET,
922 .modulemode = MODULEMODE_SWCTRL,
923 },
924 },
925}; 984};
926 985
927/* 986/*
@@ -1824,6 +1883,7 @@ static struct omap_hwmod am33xx_tptc0_hwmod = {
1824 .class = &am33xx_tptc_hwmod_class, 1883 .class = &am33xx_tptc_hwmod_class,
1825 .clkdm_name = "l3_clkdm", 1884 .clkdm_name = "l3_clkdm",
1826 .mpu_irqs = am33xx_tptc0_irqs, 1885 .mpu_irqs = am33xx_tptc0_irqs,
1886 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1827 .main_clk = "l3_gclk", 1887 .main_clk = "l3_gclk",
1828 .prcm = { 1888 .prcm = {
1829 .omap4 = { 1889 .omap4 = {
@@ -2496,7 +2556,6 @@ static struct omap_hwmod_addr_space am33xx_cpgmac0_addr_space[] = {
2496 { 2556 {
2497 .pa_start = 0x4a100000, 2557 .pa_start = 0x4a100000,
2498 .pa_end = 0x4a100000 + SZ_2K - 1, 2558 .pa_end = 0x4a100000 + SZ_2K - 1,
2499 .flags = ADDR_TYPE_RT,
2500 }, 2559 },
2501 /* cpsw wr */ 2560 /* cpsw wr */
2502 { 2561 {
@@ -2547,162 +2606,202 @@ static struct omap_hwmod_ocp_if am33xx_l4_ls__elm = {
2547 .user = OCP_USER_MPU, 2606 .user = OCP_USER_MPU,
2548}; 2607};
2549 2608
2550/* 2609static struct omap_hwmod_addr_space am33xx_epwmss0_addr_space[] = {
2551 * Splitting the resources to handle access of PWMSS config space
2552 * and module specific part independently
2553 */
2554static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2555 { 2610 {
2556 .pa_start = 0x48300000, 2611 .pa_start = 0x48300000,
2557 .pa_end = 0x48300000 + SZ_16 - 1, 2612 .pa_end = 0x48300000 + SZ_16 - 1,
2558 .flags = ADDR_TYPE_RT 2613 .flags = ADDR_TYPE_RT
2559 }, 2614 },
2560 {
2561 .pa_start = 0x48300200,
2562 .pa_end = 0x48300200 + SZ_256 - 1,
2563 .flags = ADDR_TYPE_RT
2564 },
2565 { } 2615 { }
2566}; 2616};
2567 2617
2568static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm0 = { 2618static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss0 = {
2569 .master = &am33xx_l4_ls_hwmod, 2619 .master = &am33xx_l4_ls_hwmod,
2570 .slave = &am33xx_ehrpwm0_hwmod, 2620 .slave = &am33xx_epwmss0_hwmod,
2571 .clk = "l4ls_gclk", 2621 .clk = "l4ls_gclk",
2572 .addr = am33xx_ehrpwm0_addr_space, 2622 .addr = am33xx_epwmss0_addr_space,
2573 .user = OCP_USER_MPU, 2623 .user = OCP_USER_MPU,
2574}; 2624};
2575 2625
2576/* 2626static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2577 * Splitting the resources to handle access of PWMSS config space
2578 * and module specific part independently
2579 */
2580static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2581 {
2582 .pa_start = 0x48302000,
2583 .pa_end = 0x48302000 + SZ_16 - 1,
2584 .flags = ADDR_TYPE_RT
2585 },
2586 { 2627 {
2587 .pa_start = 0x48302200, 2628 .pa_start = 0x48300100,
2588 .pa_end = 0x48302200 + SZ_256 - 1, 2629 .pa_end = 0x48300100 + SZ_128 - 1,
2589 .flags = ADDR_TYPE_RT
2590 }, 2630 },
2591 { } 2631 { }
2592}; 2632};
2593 2633
2594static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm1 = { 2634static struct omap_hwmod_ocp_if am33xx_epwmss0__ecap0 = {
2595 .master = &am33xx_l4_ls_hwmod, 2635 .master = &am33xx_epwmss0_hwmod,
2596 .slave = &am33xx_ehrpwm1_hwmod, 2636 .slave = &am33xx_ecap0_hwmod,
2597 .clk = "l4ls_gclk", 2637 .clk = "l4ls_gclk",
2598 .addr = am33xx_ehrpwm1_addr_space, 2638 .addr = am33xx_ecap0_addr_space,
2599 .user = OCP_USER_MPU, 2639 .user = OCP_USER_MPU,
2600}; 2640};
2601 2641
2602/* 2642static struct omap_hwmod_addr_space am33xx_eqep0_addr_space[] = {
2603 * Splitting the resources to handle access of PWMSS config space
2604 * and module specific part independently
2605 */
2606static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2607 { 2643 {
2608 .pa_start = 0x48304000, 2644 .pa_start = 0x48300180,
2609 .pa_end = 0x48304000 + SZ_16 - 1, 2645 .pa_end = 0x48300180 + SZ_128 - 1,
2610 .flags = ADDR_TYPE_RT
2611 },
2612 {
2613 .pa_start = 0x48304200,
2614 .pa_end = 0x48304200 + SZ_256 - 1,
2615 .flags = ADDR_TYPE_RT
2616 }, 2646 },
2617 { } 2647 { }
2618}; 2648};
2619 2649
2620static struct omap_hwmod_ocp_if am33xx_l4_ls__ehrpwm2 = { 2650static struct omap_hwmod_ocp_if am33xx_epwmss0__eqep0 = {
2621 .master = &am33xx_l4_ls_hwmod, 2651 .master = &am33xx_epwmss0_hwmod,
2622 .slave = &am33xx_ehrpwm2_hwmod, 2652 .slave = &am33xx_eqep0_hwmod,
2623 .clk = "l4ls_gclk", 2653 .clk = "l4ls_gclk",
2624 .addr = am33xx_ehrpwm2_addr_space, 2654 .addr = am33xx_eqep0_addr_space,
2625 .user = OCP_USER_MPU, 2655 .user = OCP_USER_MPU,
2626}; 2656};
2627 2657
2628/* 2658static struct omap_hwmod_addr_space am33xx_ehrpwm0_addr_space[] = {
2629 * Splitting the resources to handle access of PWMSS config space
2630 * and module specific part independently
2631 */
2632static struct omap_hwmod_addr_space am33xx_ecap0_addr_space[] = {
2633 {
2634 .pa_start = 0x48300000,
2635 .pa_end = 0x48300000 + SZ_16 - 1,
2636 .flags = ADDR_TYPE_RT
2637 },
2638 { 2659 {
2639 .pa_start = 0x48300100, 2660 .pa_start = 0x48300200,
2640 .pa_end = 0x48300100 + SZ_256 - 1, 2661 .pa_end = 0x48300200 + SZ_128 - 1,
2641 .flags = ADDR_TYPE_RT
2642 }, 2662 },
2643 { } 2663 { }
2644}; 2664};
2645 2665
2646static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap0 = { 2666static struct omap_hwmod_ocp_if am33xx_epwmss0__ehrpwm0 = {
2647 .master = &am33xx_l4_ls_hwmod, 2667 .master = &am33xx_epwmss0_hwmod,
2648 .slave = &am33xx_ecap0_hwmod, 2668 .slave = &am33xx_ehrpwm0_hwmod,
2649 .clk = "l4ls_gclk", 2669 .clk = "l4ls_gclk",
2650 .addr = am33xx_ecap0_addr_space, 2670 .addr = am33xx_ehrpwm0_addr_space,
2651 .user = OCP_USER_MPU, 2671 .user = OCP_USER_MPU,
2652}; 2672};
2653 2673
2654/* 2674
2655 * Splitting the resources to handle access of PWMSS config space 2675static struct omap_hwmod_addr_space am33xx_epwmss1_addr_space[] = {
2656 * and module specific part independently
2657 */
2658static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2659 { 2676 {
2660 .pa_start = 0x48302000, 2677 .pa_start = 0x48302000,
2661 .pa_end = 0x48302000 + SZ_16 - 1, 2678 .pa_end = 0x48302000 + SZ_16 - 1,
2662 .flags = ADDR_TYPE_RT 2679 .flags = ADDR_TYPE_RT
2663 }, 2680 },
2681 { }
2682};
2683
2684static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss1 = {
2685 .master = &am33xx_l4_ls_hwmod,
2686 .slave = &am33xx_epwmss1_hwmod,
2687 .clk = "l4ls_gclk",
2688 .addr = am33xx_epwmss1_addr_space,
2689 .user = OCP_USER_MPU,
2690};
2691
2692static struct omap_hwmod_addr_space am33xx_ecap1_addr_space[] = {
2664 { 2693 {
2665 .pa_start = 0x48302100, 2694 .pa_start = 0x48302100,
2666 .pa_end = 0x48302100 + SZ_256 - 1, 2695 .pa_end = 0x48302100 + SZ_128 - 1,
2667 .flags = ADDR_TYPE_RT
2668 }, 2696 },
2669 { } 2697 { }
2670}; 2698};
2671 2699
2672static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap1 = { 2700static struct omap_hwmod_ocp_if am33xx_epwmss1__ecap1 = {
2673 .master = &am33xx_l4_ls_hwmod, 2701 .master = &am33xx_epwmss1_hwmod,
2674 .slave = &am33xx_ecap1_hwmod, 2702 .slave = &am33xx_ecap1_hwmod,
2675 .clk = "l4ls_gclk", 2703 .clk = "l4ls_gclk",
2676 .addr = am33xx_ecap1_addr_space, 2704 .addr = am33xx_ecap1_addr_space,
2677 .user = OCP_USER_MPU, 2705 .user = OCP_USER_MPU,
2678}; 2706};
2679 2707
2680/* 2708static struct omap_hwmod_addr_space am33xx_eqep1_addr_space[] = {
2681 * Splitting the resources to handle access of PWMSS config space 2709 {
2682 * and module specific part independently 2710 .pa_start = 0x48302180,
2683 */ 2711 .pa_end = 0x48302180 + SZ_128 - 1,
2684static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = { 2712 },
2713 { }
2714};
2715
2716static struct omap_hwmod_ocp_if am33xx_epwmss1__eqep1 = {
2717 .master = &am33xx_epwmss1_hwmod,
2718 .slave = &am33xx_eqep1_hwmod,
2719 .clk = "l4ls_gclk",
2720 .addr = am33xx_eqep1_addr_space,
2721 .user = OCP_USER_MPU,
2722};
2723
2724static struct omap_hwmod_addr_space am33xx_ehrpwm1_addr_space[] = {
2725 {
2726 .pa_start = 0x48302200,
2727 .pa_end = 0x48302200 + SZ_128 - 1,
2728 },
2729 { }
2730};
2731
2732static struct omap_hwmod_ocp_if am33xx_epwmss1__ehrpwm1 = {
2733 .master = &am33xx_epwmss1_hwmod,
2734 .slave = &am33xx_ehrpwm1_hwmod,
2735 .clk = "l4ls_gclk",
2736 .addr = am33xx_ehrpwm1_addr_space,
2737 .user = OCP_USER_MPU,
2738};
2739
2740static struct omap_hwmod_addr_space am33xx_epwmss2_addr_space[] = {
2685 { 2741 {
2686 .pa_start = 0x48304000, 2742 .pa_start = 0x48304000,
2687 .pa_end = 0x48304000 + SZ_16 - 1, 2743 .pa_end = 0x48304000 + SZ_16 - 1,
2688 .flags = ADDR_TYPE_RT 2744 .flags = ADDR_TYPE_RT
2689 }, 2745 },
2746 { }
2747};
2748
2749static struct omap_hwmod_ocp_if am33xx_l4_ls__epwmss2 = {
2750 .master = &am33xx_l4_ls_hwmod,
2751 .slave = &am33xx_epwmss2_hwmod,
2752 .clk = "l4ls_gclk",
2753 .addr = am33xx_epwmss2_addr_space,
2754 .user = OCP_USER_MPU,
2755};
2756
2757static struct omap_hwmod_addr_space am33xx_ecap2_addr_space[] = {
2690 { 2758 {
2691 .pa_start = 0x48304100, 2759 .pa_start = 0x48304100,
2692 .pa_end = 0x48304100 + SZ_256 - 1, 2760 .pa_end = 0x48304100 + SZ_128 - 1,
2693 .flags = ADDR_TYPE_RT
2694 }, 2761 },
2695 { } 2762 { }
2696}; 2763};
2697 2764
2698static struct omap_hwmod_ocp_if am33xx_l4_ls__ecap2 = { 2765static struct omap_hwmod_ocp_if am33xx_epwmss2__ecap2 = {
2699 .master = &am33xx_l4_ls_hwmod, 2766 .master = &am33xx_epwmss2_hwmod,
2700 .slave = &am33xx_ecap2_hwmod, 2767 .slave = &am33xx_ecap2_hwmod,
2701 .clk = "l4ls_gclk", 2768 .clk = "l4ls_gclk",
2702 .addr = am33xx_ecap2_addr_space, 2769 .addr = am33xx_ecap2_addr_space,
2703 .user = OCP_USER_MPU, 2770 .user = OCP_USER_MPU,
2704}; 2771};
2705 2772
2773static struct omap_hwmod_addr_space am33xx_eqep2_addr_space[] = {
2774 {
2775 .pa_start = 0x48304180,
2776 .pa_end = 0x48304180 + SZ_128 - 1,
2777 },
2778 { }
2779};
2780
2781static struct omap_hwmod_ocp_if am33xx_epwmss2__eqep2 = {
2782 .master = &am33xx_epwmss2_hwmod,
2783 .slave = &am33xx_eqep2_hwmod,
2784 .clk = "l4ls_gclk",
2785 .addr = am33xx_eqep2_addr_space,
2786 .user = OCP_USER_MPU,
2787};
2788
2789static struct omap_hwmod_addr_space am33xx_ehrpwm2_addr_space[] = {
2790 {
2791 .pa_start = 0x48304200,
2792 .pa_end = 0x48304200 + SZ_128 - 1,
2793 },
2794 { }
2795};
2796
2797static struct omap_hwmod_ocp_if am33xx_epwmss2__ehrpwm2 = {
2798 .master = &am33xx_epwmss2_hwmod,
2799 .slave = &am33xx_ehrpwm2_hwmod,
2800 .clk = "l4ls_gclk",
2801 .addr = am33xx_ehrpwm2_addr_space,
2802 .user = OCP_USER_MPU,
2803};
2804
2706/* l3s cfg -> gpmc */ 2805/* l3s cfg -> gpmc */
2707static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = { 2806static struct omap_hwmod_addr_space am33xx_gpmc_addr_space[] = {
2708 { 2807 {
@@ -3328,6 +3427,13 @@ static struct omap_hwmod_ocp_if am33xx_l3_s__usbss = {
3328 .flags = OCPIF_SWSUP_IDLE, 3427 .flags = OCPIF_SWSUP_IDLE,
3329}; 3428};
3330 3429
3430/* l3 main -> ocmc */
3431static struct omap_hwmod_ocp_if am33xx_l3_main__ocmc = {
3432 .master = &am33xx_l3_main_hwmod,
3433 .slave = &am33xx_ocmcram_hwmod,
3434 .user = OCP_USER_MPU | OCP_USER_SDMA,
3435};
3436
3331static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = { 3437static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3332 &am33xx_l4_fw__emif_fw, 3438 &am33xx_l4_fw__emif_fw,
3333 &am33xx_l3_main__emif, 3439 &am33xx_l3_main__emif,
@@ -3385,12 +3491,18 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3385 &am33xx_l4_ls__uart6, 3491 &am33xx_l4_ls__uart6,
3386 &am33xx_l4_ls__spinlock, 3492 &am33xx_l4_ls__spinlock,
3387 &am33xx_l4_ls__elm, 3493 &am33xx_l4_ls__elm,
3388 &am33xx_l4_ls__ehrpwm0, 3494 &am33xx_l4_ls__epwmss0,
3389 &am33xx_l4_ls__ehrpwm1, 3495 &am33xx_epwmss0__ecap0,
3390 &am33xx_l4_ls__ehrpwm2, 3496 &am33xx_epwmss0__eqep0,
3391 &am33xx_l4_ls__ecap0, 3497 &am33xx_epwmss0__ehrpwm0,
3392 &am33xx_l4_ls__ecap1, 3498 &am33xx_l4_ls__epwmss1,
3393 &am33xx_l4_ls__ecap2, 3499 &am33xx_epwmss1__ecap1,
3500 &am33xx_epwmss1__eqep1,
3501 &am33xx_epwmss1__ehrpwm1,
3502 &am33xx_l4_ls__epwmss2,
3503 &am33xx_epwmss2__ecap2,
3504 &am33xx_epwmss2__eqep2,
3505 &am33xx_epwmss2__ehrpwm2,
3394 &am33xx_l3_s__gpmc, 3506 &am33xx_l3_s__gpmc,
3395 &am33xx_l3_main__lcdc, 3507 &am33xx_l3_main__lcdc,
3396 &am33xx_l4_ls__mcspi0, 3508 &am33xx_l4_ls__mcspi0,
@@ -3398,6 +3510,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
3398 &am33xx_l3_main__tptc0, 3510 &am33xx_l3_main__tptc0,
3399 &am33xx_l3_main__tptc1, 3511 &am33xx_l3_main__tptc1,
3400 &am33xx_l3_main__tptc2, 3512 &am33xx_l3_main__tptc2,
3513 &am33xx_l3_main__ocmc,
3401 &am33xx_l3_s__usbss, 3514 &am33xx_l3_s__usbss,
3402 &am33xx_l4_hs__cpgmac0, 3515 &am33xx_l4_hs__cpgmac0,
3403 &am33xx_cpgmac0__mdio, 3516 &am33xx_cpgmac0__mdio,
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 8bb2628df34e..ac7e03ec952f 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -3493,7 +3493,12 @@ static struct omap_hwmod am35xx_emac_hwmod = {
3493 .name = "davinci_emac", 3493 .name = "davinci_emac",
3494 .mpu_irqs = am35xx_emac_mpu_irqs, 3494 .mpu_irqs = am35xx_emac_mpu_irqs,
3495 .class = &am35xx_emac_class, 3495 .class = &am35xx_emac_class,
3496 .flags = HWMOD_NO_IDLEST, 3496 /*
3497 * According to Mark Greer, the MPU will not return from WFI
3498 * when the EMAC signals an interrupt.
3499 * http://www.spinics.net/lists/arm-kernel/msg174734.html
3500 */
3501 .flags = (HWMOD_NO_IDLEST | HWMOD_BLOCK_WFI),
3497}; 3502};
3498 3503
3499/* l3_core -> davinci emac interface */ 3504/* l3_core -> davinci emac interface */
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index 7ec1083ff604..0e47d2e1687c 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -322,6 +322,7 @@ static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = {
322static struct omap_hwmod_class omap44xx_aess_hwmod_class = { 322static struct omap_hwmod_class omap44xx_aess_hwmod_class = {
323 .name = "aess", 323 .name = "aess",
324 .sysc = &omap44xx_aess_sysc, 324 .sysc = &omap44xx_aess_sysc,
325 .enable_preprogram = omap_hwmod_aess_preprogram,
325}; 326};
326 327
327/* aess */ 328/* aess */
@@ -348,7 +349,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
348 .clkdm_name = "abe_clkdm", 349 .clkdm_name = "abe_clkdm",
349 .mpu_irqs = omap44xx_aess_irqs, 350 .mpu_irqs = omap44xx_aess_irqs,
350 .sdma_reqs = omap44xx_aess_sdma_reqs, 351 .sdma_reqs = omap44xx_aess_sdma_reqs,
351 .main_clk = "aess_fck", 352 .main_clk = "aess_fclk",
352 .prcm = { 353 .prcm = {
353 .omap4 = { 354 .omap4 = {
354 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, 355 .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
@@ -4241,6 +4242,27 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
4241 4242
4242static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { 4243static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = {
4243 { 4244 {
4245 .name = "dmem",
4246 .pa_start = 0x40180000,
4247 .pa_end = 0x4018ffff
4248 },
4249 {
4250 .name = "cmem",
4251 .pa_start = 0x401a0000,
4252 .pa_end = 0x401a1fff
4253 },
4254 {
4255 .name = "smem",
4256 .pa_start = 0x401c0000,
4257 .pa_end = 0x401c5fff
4258 },
4259 {
4260 .name = "pmem",
4261 .pa_start = 0x401e0000,
4262 .pa_end = 0x401e1fff
4263 },
4264 {
4265 .name = "mpu",
4244 .pa_start = 0x401f1000, 4266 .pa_start = 0x401f1000,
4245 .pa_end = 0x401f13ff, 4267 .pa_end = 0x401f13ff,
4246 .flags = ADDR_TYPE_RT 4268 .flags = ADDR_TYPE_RT
@@ -4259,6 +4281,27 @@ static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l4_abe__aess = {
4259 4281
4260static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { 4282static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = {
4261 { 4283 {
4284 .name = "dmem_dma",
4285 .pa_start = 0x49080000,
4286 .pa_end = 0x4908ffff
4287 },
4288 {
4289 .name = "cmem_dma",
4290 .pa_start = 0x490a0000,
4291 .pa_end = 0x490a1fff
4292 },
4293 {
4294 .name = "smem_dma",
4295 .pa_start = 0x490c0000,
4296 .pa_end = 0x490c5fff
4297 },
4298 {
4299 .name = "pmem_dma",
4300 .pa_start = 0x490e0000,
4301 .pa_end = 0x490e1fff
4302 },
4303 {
4304 .name = "dma",
4262 .pa_start = 0x490f1000, 4305 .pa_start = 0x490f1000,
4263 .pa_end = 0x490f13ff, 4306 .pa_end = 0x490f13ff,
4264 .flags = ADDR_TYPE_RT 4307 .flags = ADDR_TYPE_RT
@@ -6268,7 +6311,7 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6268 &omap44xx_l3_main_1__l3_main_3, 6311 &omap44xx_l3_main_1__l3_main_3,
6269 &omap44xx_l3_main_2__l3_main_3, 6312 &omap44xx_l3_main_2__l3_main_3,
6270 &omap44xx_l4_cfg__l3_main_3, 6313 &omap44xx_l4_cfg__l3_main_3,
6271 /* &omap44xx_aess__l4_abe, */ 6314 &omap44xx_aess__l4_abe,
6272 &omap44xx_dsp__l4_abe, 6315 &omap44xx_dsp__l4_abe,
6273 &omap44xx_l3_main_1__l4_abe, 6316 &omap44xx_l3_main_1__l4_abe,
6274 &omap44xx_mpu__l4_abe, 6317 &omap44xx_mpu__l4_abe,
@@ -6277,8 +6320,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
6277 &omap44xx_l4_cfg__l4_wkup, 6320 &omap44xx_l4_cfg__l4_wkup,
6278 &omap44xx_mpu__mpu_private, 6321 &omap44xx_mpu__mpu_private,
6279 &omap44xx_l4_cfg__ocp_wp_noc, 6322 &omap44xx_l4_cfg__ocp_wp_noc,
6280 /* &omap44xx_l4_abe__aess, */ 6323 &omap44xx_l4_abe__aess,
6281 /* &omap44xx_l4_abe__aess_dma, */ 6324 &omap44xx_l4_abe__aess_dma,
6282 &omap44xx_l3_main_2__c2c, 6325 &omap44xx_l3_main_2__c2c,
6283 &omap44xx_l4_wkup__counter_32k, 6326 &omap44xx_l4_wkup__counter_32k,
6284 &omap44xx_l4_cfg__ctrl_module_core, 6327 &omap44xx_l4_cfg__ctrl_module_core,
diff --git a/arch/arm/mach-omap2/omap_hwmod_reset.c b/arch/arm/mach-omap2/omap_hwmod_reset.c
new file mode 100644
index 000000000000..65e186c9df55
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_reset.c
@@ -0,0 +1,53 @@
1/*
2 * OMAP IP block custom reset and preprogramming stubs
3 *
4 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley
6 *
7 * A small number of IP blocks need custom reset and preprogramming
8 * functions. The stubs in this file provide a standard way for the
9 * hwmod code to call these functions, which are to be located under
10 * drivers/.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation version 2.
15 *
16 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
17 * kind, whether express or implied; without even the implied warranty
18 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 * 02110-1301 USA
25 */
26#include <linux/kernel.h>
27#include <linux/errno.h>
28
29#include <sound/aess.h>
30
31#include "omap_hwmod.h"
32
33/**
34 * omap_hwmod_aess_preprogram - enable AESS internal autogating
35 * @oh: struct omap_hwmod *
36 *
37 * The AESS will not IdleAck to the PRCM until its internal autogating
38 * is enabled. Since internal autogating is disabled by default after
39 * AESS reset, we must enable autogating after the hwmod code resets
40 * the AESS. Returns 0.
41 */
42int omap_hwmod_aess_preprogram(struct omap_hwmod *oh)
43{
44 void __iomem *va;
45
46 va = omap_hwmod_get_mpu_rt_va(oh);
47 if (!va)
48 return -EINVAL;
49
50 aess_enable_autogating(va);
51
52 return 0;
53}
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index cd6682df5625..673a4c1d1d76 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -282,19 +282,19 @@ int __init omap2_common_pm_late_init(void)
282 * a completely different mechanism. 282 * a completely different mechanism.
283 * Disable this part if a DT blob is available. 283 * Disable this part if a DT blob is available.
284 */ 284 */
285 if (of_have_populated_dt()) 285 if (!of_have_populated_dt()) {
286 return 0;
287 286
288 /* Init the voltage layer */ 287 /* Init the voltage layer */
289 omap_pmic_late_init(); 288 omap_pmic_late_init();
290 omap_voltage_late_init(); 289 omap_voltage_late_init();
291 290
292 /* Initialize the voltages */ 291 /* Initialize the voltages */
293 omap3_init_voltages(); 292 omap3_init_voltages();
294 omap4_init_voltages(); 293 omap4_init_voltages();
295 294
296 /* Smartreflex device init */ 295 /* Smartreflex device init */
297 omap_devinit_smartreflex(); 296 omap_devinit_smartreflex();
297 }
298 298
299#ifdef CONFIG_SUSPEND 299#ifdef CONFIG_SUSPEND
300 suspend_set_ops(&omap_pm_ops); 300 suspend_set_ops(&omap_pm_ops);
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index b2a4df623545..b59d93908341 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -54,7 +54,6 @@
54#include "powerdomain.h" 54#include "powerdomain.h"
55#include "clockdomain.h" 55#include "clockdomain.h"
56 56
57static void (*omap2_sram_idle)(void);
58static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl, 57static void (*omap2_sram_suspend)(u32 dllctrl, void __iomem *sdrc_dlla_ctrl,
59 void __iomem *sdrc_power); 58 void __iomem *sdrc_power);
60 59
@@ -163,6 +162,8 @@ static int omap2_allow_mpu_retention(void)
163 162
164static void omap2_enter_mpu_retention(void) 163static void omap2_enter_mpu_retention(void)
165{ 164{
165 const int zero = 0;
166
166 /* The peripherals seem not to be able to wake up the MPU when 167 /* The peripherals seem not to be able to wake up the MPU when
167 * it is in retention mode. */ 168 * it is in retention mode. */
168 if (omap2_allow_mpu_retention()) { 169 if (omap2_allow_mpu_retention()) {
@@ -179,7 +180,8 @@ static void omap2_enter_mpu_retention(void)
179 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 180 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
180 } 181 }
181 182
182 omap2_sram_idle(); 183 /* WFI */
184 asm("mcr p15, 0, %0, c7, c0, 4" : : "r" (zero) : "memory", "cc");
183 185
184 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); 186 pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON);
185} 187}
@@ -333,11 +335,9 @@ int __init omap2_pm_init(void)
333 /* 335 /*
334 * We copy the assembler sleep/wakeup routines to SRAM. 336 * We copy the assembler sleep/wakeup routines to SRAM.
335 * These routines need to be in SRAM as that's the only 337 * These routines need to be in SRAM as that's the only
336 * memory the MPU can see when it wakes up. 338 * memory the MPU can see when it wakes up after the entire
339 * chip enters idle.
337 */ 340 */
338 omap2_sram_idle = omap_sram_push(omap24xx_idle_loop_suspend,
339 omap24xx_idle_loop_suspend_sz);
340
341 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend, 341 omap2_sram_suspend = omap_sram_push(omap24xx_cpu_suspend,
342 omap24xx_cpu_suspend_sz); 342 omap24xx_cpu_suspend_sz);
343 343
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index aa6fd98f606e..ea62e75ef21d 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -77,10 +77,20 @@ static int omap4_pm_suspend(void)
77 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state); 77 omap_set_pwrdm_state(pwrst->pwrdm, pwrst->saved_state);
78 pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state); 78 pwrdm_set_logic_retst(pwrst->pwrdm, pwrst->saved_logic_state);
79 } 79 }
80 if (ret) 80 if (ret) {
81 pr_crit("Could not enter target state in pm_suspend\n"); 81 pr_crit("Could not enter target state in pm_suspend\n");
82 else 82 /*
83 * OMAP4 chip PM currently works only with certain (newer)
84 * versions of bootloaders. This is due to missing code in the
85 * kernel to properly reset and initialize some devices.
86 * Warn the user about the bootloader version being one of the
87 * possible causes.
88 * http://www.spinics.net/lists/arm-kernel/msg218641.html
89 */
90 pr_warn("A possible cause could be an old bootloader - try u-boot >= v2012.07\n");
91 } else {
83 pr_info("Successfully put all powerdomains to target state\n"); 92 pr_info("Successfully put all powerdomains to target state\n");
93 }
84 94
85 return 0; 95 return 0;
86} 96}
@@ -146,6 +156,13 @@ int __init omap4_pm_init(void)
146 } 156 }
147 157
148 pr_err("Power Management for TI OMAP4.\n"); 158 pr_err("Power Management for TI OMAP4.\n");
159 /*
160 * OMAP4 chip PM currently works only with certain (newer)
161 * versions of bootloaders. This is due to missing code in the
162 * kernel to properly reset and initialize some devices.
163 * http://www.spinics.net/lists/arm-kernel/msg218641.html
164 */
165 pr_warn("OMAP4 PM: u-boot >= v2012.07 is required for full PM support\n");
149 166
150 ret = pwrdm_for_each(pwrdms_setup, NULL); 167 ret = pwrdm_for_each(pwrdms_setup, NULL);
151 if (ret) { 168 if (ret) {
diff --git a/arch/arm/mach-omap2/prm33xx.c b/arch/arm/mach-omap2/prm33xx.c
index 1ac73883f891..44c0d7216aa7 100644
--- a/arch/arm/mach-omap2/prm33xx.c
+++ b/arch/arm/mach-omap2/prm33xx.c
@@ -110,11 +110,11 @@ int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs)
110 * -EINVAL upon an argument error, -EEXIST if the submodule was already out 110 * -EINVAL upon an argument error, -EEXIST if the submodule was already out
111 * of reset, or -EBUSY if the submodule did not exit reset promptly. 111 * of reset, or -EBUSY if the submodule did not exit reset promptly.
112 */ 112 */
113int am33xx_prm_deassert_hardreset(u8 shift, s16 inst, 113int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
114 u16 rstctrl_offs, u16 rstst_offs) 114 u16 rstctrl_offs, u16 rstst_offs)
115{ 115{
116 int c; 116 int c;
117 u32 mask = 1 << shift; 117 u32 mask = 1 << st_shift;
118 118
119 /* Check the current status to avoid de-asserting the line twice */ 119 /* Check the current status to avoid de-asserting the line twice */
120 if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0) 120 if (am33xx_prm_is_hardreset_asserted(shift, inst, rstctrl_offs) == 0)
@@ -122,11 +122,14 @@ int am33xx_prm_deassert_hardreset(u8 shift, s16 inst,
122 122
123 /* Clear the reset status by writing 1 to the status bit */ 123 /* Clear the reset status by writing 1 to the status bit */
124 am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs); 124 am33xx_prm_rmw_reg_bits(0xffffffff, mask, inst, rstst_offs);
125
125 /* de-assert the reset control line */ 126 /* de-assert the reset control line */
127 mask = 1 << shift;
128
126 am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs); 129 am33xx_prm_rmw_reg_bits(mask, 0, inst, rstctrl_offs);
127 /* wait the status to be set */
128 130
129 omap_test_timeout(am33xx_prm_is_hardreset_asserted(shift, inst, 131 /* wait the status to be set */
132 omap_test_timeout(am33xx_prm_is_hardreset_asserted(st_shift, inst,
130 rstst_offs), 133 rstst_offs),
131 MAX_MODULE_HARDRESET_WAIT, c); 134 MAX_MODULE_HARDRESET_WAIT, c);
132 135
diff --git a/arch/arm/mach-omap2/prm33xx.h b/arch/arm/mach-omap2/prm33xx.h
index 3f25c563a821..9b9918dfb119 100644
--- a/arch/arm/mach-omap2/prm33xx.h
+++ b/arch/arm/mach-omap2/prm33xx.h
@@ -117,6 +117,7 @@
117#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004 117#define AM33XX_PM_CEFUSE_PWRSTST_OFFSET 0x0004
118#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004) 118#define AM33XX_PM_CEFUSE_PWRSTST AM33XX_PRM_REGADDR(AM33XX_PRM_CEFUSE_MOD, 0x0004)
119 119
120#ifndef __ASSEMBLER__
120extern u32 am33xx_prm_read_reg(s16 inst, u16 idx); 121extern u32 am33xx_prm_read_reg(s16 inst, u16 idx);
121extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx); 122extern void am33xx_prm_write_reg(u32 val, s16 inst, u16 idx);
122extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx); 123extern u32 am33xx_prm_rmw_reg_bits(u32 mask, u32 bits, s16 inst, s16 idx);
@@ -124,6 +125,7 @@ extern void am33xx_prm_global_warm_sw_reset(void);
124extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst, 125extern int am33xx_prm_is_hardreset_asserted(u8 shift, s16 inst,
125 u16 rstctrl_offs); 126 u16 rstctrl_offs);
126extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs); 127extern int am33xx_prm_assert_hardreset(u8 shift, s16 inst, u16 rstctrl_offs);
127extern int am33xx_prm_deassert_hardreset(u8 shift, s16 inst, 128extern int am33xx_prm_deassert_hardreset(u8 shift, u8 st_shift, s16 inst,
128 u16 rstctrl_offs, u16 rstst_offs); 129 u16 rstctrl_offs, u16 rstst_offs);
130#endif /* ASSEMBLER */
129#endif 131#endif
diff --git a/arch/arm/mach-omap2/sleep24xx.S b/arch/arm/mach-omap2/sleep24xx.S
index ce0ccd26efbd..1d3cb25c9629 100644
--- a/arch/arm/mach-omap2/sleep24xx.S
+++ b/arch/arm/mach-omap2/sleep24xx.S
@@ -37,25 +37,6 @@
37 .text 37 .text
38 38
39/* 39/*
40 * Forces OMAP into idle state
41 *
42 * omap24xx_idle_loop_suspend() - This bit of code just executes the WFI
43 * for normal idles.
44 *
45 * Note: This code get's copied to internal SRAM at boot. When the OMAP
46 * wakes up it continues execution at the point it went to sleep.
47 */
48 .align 3
49ENTRY(omap24xx_idle_loop_suspend)
50 stmfd sp!, {r0, lr} @ save registers on stack
51 mov r0, #0 @ clear for mcr setup
52 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
53 ldmfd sp!, {r0, pc} @ restore regs and return
54
55ENTRY(omap24xx_idle_loop_suspend_sz)
56 .word . - omap24xx_idle_loop_suspend
57
58/*
59 * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing 40 * omap24xx_cpu_suspend() - Forces OMAP into deep sleep state by completing
60 * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore 41 * SDRC shutdown then ARM shutdown. Upon wake MPU is back on so just restore
61 * SDRC. 42 * SDRC.
diff --git a/arch/arm/mach-omap2/soc.h b/arch/arm/mach-omap2/soc.h
index 092aedd7ed13..c62116bbc760 100644
--- a/arch/arm/mach-omap2/soc.h
+++ b/arch/arm/mach-omap2/soc.h
@@ -395,6 +395,7 @@ IS_OMAP_TYPE(3430, 0x3430)
395 395
396#define AM335X_CLASS 0x33500033 396#define AM335X_CLASS 0x33500033
397#define AM335X_REV_ES1_0 AM335X_CLASS 397#define AM335X_REV_ES1_0 AM335X_CLASS
398#define AM335X_REV_ES2_0 (AM335X_CLASS | (0x1 << 8))
398 399
399#define OMAP443X_CLASS 0x44300044 400#define OMAP443X_CLASS 0x44300044
400#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8)) 401#define OMAP4430_REV_ES1_0 (OMAP443X_CLASS | (0x10 << 8))
diff --git a/arch/arm/mach-omap2/sr_device.c b/arch/arm/mach-omap2/sr_device.c
index bb829e065400..d7bc33f15344 100644
--- a/arch/arm/mach-omap2/sr_device.c
+++ b/arch/arm/mach-omap2/sr_device.c
@@ -152,7 +152,7 @@ static int __init sr_dev_init(struct omap_hwmod *oh, void *user)
152 152
153 sr_data->enable_on_init = sr_enable_on_init; 153 sr_data->enable_on_init = sr_enable_on_init;
154 154
155 pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data), 0); 155 pdev = omap_device_build(name, i, oh, sr_data, sizeof(*sr_data));
156 if (IS_ERR(pdev)) 156 if (IS_ERR(pdev))
157 pr_warning("%s: Could not build omap_device for %s: %s.\n\n", 157 pr_warning("%s: Could not build omap_device for %s: %s.\n\n",
158 __func__, name, oh->name); 158 __func__, name, oh->name);
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 67c859cf16bc..ce66eb9be481 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -147,15 +147,6 @@ config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
147 help 147 help
148 PPA routine service ID for setting L2 auxiliary control register. 148 PPA routine service ID for setting L2 auxiliary control register.
149 149
150config OMAP_32K_TIMER_HZ
151 int "Kernel internal timer frequency for 32KHz timer"
152 range 32 1024
153 depends on OMAP_32K_TIMER
154 default "128"
155 help
156 Kernel internal timer frequency should be a divisor of 32768,
157 such as 64 or 128.
158
159config OMAP_DM_TIMER 150config OMAP_DM_TIMER
160 bool "Use dual-mode timer" 151 bool "Use dual-mode timer"
161 depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS 152 depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS
diff --git a/arch/arm/plat-omap/include/plat/timex.h b/arch/arm/plat-omap/include/plat/timex.h
index 6d35767bc48f..e27d2daa7790 100644
--- a/arch/arm/plat-omap/include/plat/timex.h
+++ b/arch/arm/plat-omap/include/plat/timex.h
@@ -28,14 +28,6 @@
28#if !defined(__ASM_ARCH_OMAP_TIMEX_H) 28#if !defined(__ASM_ARCH_OMAP_TIMEX_H)
29#define __ASM_ARCH_OMAP_TIMEX_H 29#define __ASM_ARCH_OMAP_TIMEX_H
30 30
31/*
32 * OMAP 32KHz timer updates time one jiffie at a time from a secondary timer,
33 * and that's why the CLOCK_TICK_RATE is not 32768.
34 */
35#ifdef CONFIG_OMAP_32K_TIMER
36#define CLOCK_TICK_RATE (CONFIG_OMAP_32K_TIMER_HZ)
37#else
38#define CLOCK_TICK_RATE (HZ * 100000UL) 31#define CLOCK_TICK_RATE (HZ * 100000UL)
39#endif
40 32
41#endif /* __ASM_ARCH_OMAP_TIMEX_H */ 33#endif /* __ASM_ARCH_OMAP_TIMEX_H */
diff --git a/drivers/media/platform/omap3isp/isp.c b/drivers/media/platform/omap3isp/isp.c
index 383a727b8aa0..6e5ad8ec0a22 100644
--- a/drivers/media/platform/omap3isp/isp.c
+++ b/drivers/media/platform/omap3isp/isp.c
@@ -1338,28 +1338,15 @@ static int isp_enable_clocks(struct isp_device *isp)
1338{ 1338{
1339 int r; 1339 int r;
1340 unsigned long rate; 1340 unsigned long rate;
1341 int divisor;
1342
1343 /*
1344 * cam_mclk clock chain:
1345 * dpll4 -> dpll4_m5 -> dpll4_m5x2 -> cam_mclk
1346 *
1347 * In OMAP3630 dpll4_m5x2 != 2 x dpll4_m5 but both are
1348 * set to the same value. Hence the rate set for dpll4_m5
1349 * has to be twice of what is set on OMAP3430 to get
1350 * the required value for cam_mclk
1351 */
1352 divisor = isp->revision == ISP_REVISION_15_0 ? 1 : 2;
1353 1341
1354 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_ICK]); 1342 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_ICK]);
1355 if (r) { 1343 if (r) {
1356 dev_err(isp->dev, "failed to enable cam_ick clock\n"); 1344 dev_err(isp->dev, "failed to enable cam_ick clock\n");
1357 goto out_clk_enable_ick; 1345 goto out_clk_enable_ick;
1358 } 1346 }
1359 r = clk_set_rate(isp->clock[ISP_CLK_DPLL4_M5_CK], 1347 r = clk_set_rate(isp->clock[ISP_CLK_CAM_MCLK], CM_CAM_MCLK_HZ);
1360 CM_CAM_MCLK_HZ/divisor);
1361 if (r) { 1348 if (r) {
1362 dev_err(isp->dev, "clk_set_rate for dpll4_m5_ck failed\n"); 1349 dev_err(isp->dev, "clk_set_rate for cam_mclk failed\n");
1363 goto out_clk_enable_mclk; 1350 goto out_clk_enable_mclk;
1364 } 1351 }
1365 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_MCLK]); 1352 r = clk_prepare_enable(isp->clock[ISP_CLK_CAM_MCLK]);
@@ -1401,7 +1388,6 @@ static void isp_disable_clocks(struct isp_device *isp)
1401static const char *isp_clocks[] = { 1388static const char *isp_clocks[] = {
1402 "cam_ick", 1389 "cam_ick",
1403 "cam_mclk", 1390 "cam_mclk",
1404 "dpll4_m5_ck",
1405 "csi2_96m_fck", 1391 "csi2_96m_fck",
1406 "l3_ick", 1392 "l3_ick",
1407}; 1393};
diff --git a/drivers/media/platform/omap3isp/isp.h b/drivers/media/platform/omap3isp/isp.h
index 517d348ce32b..c77e1f2ae5ca 100644
--- a/drivers/media/platform/omap3isp/isp.h
+++ b/drivers/media/platform/omap3isp/isp.h
@@ -147,7 +147,6 @@ struct isp_platform_callback {
147 * @ref_count: Reference count for handling multiple ISP requests. 147 * @ref_count: Reference count for handling multiple ISP requests.
148 * @cam_ick: Pointer to camera interface clock structure. 148 * @cam_ick: Pointer to camera interface clock structure.
149 * @cam_mclk: Pointer to camera functional clock structure. 149 * @cam_mclk: Pointer to camera functional clock structure.
150 * @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure.
151 * @csi2_fck: Pointer to camera CSI2 complexIO clock structure. 150 * @csi2_fck: Pointer to camera CSI2 complexIO clock structure.
152 * @l3_ick: Pointer to OMAP3 L3 bus interface clock. 151 * @l3_ick: Pointer to OMAP3 L3 bus interface clock.
153 * @irq: Currently attached ISP ISR callbacks information structure. 152 * @irq: Currently attached ISP ISR callbacks information structure.
@@ -189,10 +188,9 @@ struct isp_device {
189 u32 xclk_divisor[2]; /* Two clocks, a and b. */ 188 u32 xclk_divisor[2]; /* Two clocks, a and b. */
190#define ISP_CLK_CAM_ICK 0 189#define ISP_CLK_CAM_ICK 0
191#define ISP_CLK_CAM_MCLK 1 190#define ISP_CLK_CAM_MCLK 1
192#define ISP_CLK_DPLL4_M5_CK 2 191#define ISP_CLK_CSI2_FCK 2
193#define ISP_CLK_CSI2_FCK 3 192#define ISP_CLK_L3_ICK 3
194#define ISP_CLK_L3_ICK 4 193 struct clk *clock[4];
195 struct clk *clock[5];
196 194
197 /* ISP modules */ 195 /* ISP modules */
198 struct ispstat isp_af; 196 struct ispstat isp_af;
diff --git a/include/sound/aess.h b/include/sound/aess.h
new file mode 100644
index 000000000000..cee0d09fadbd
--- /dev/null
+++ b/include/sound/aess.h
@@ -0,0 +1,53 @@
1/*
2 * AESS IP block reset
3 *
4 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation version 2.
10 *
11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
12 * kind, whether express or implied; without even the implied warranty
13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 */
21#ifndef __SOUND_AESS_H__
22#define __SOUND_AESS_H__
23
24#include <linux/kernel.h>
25#include <linux/io.h>
26
27/*
28 * AESS_AUTO_GATING_ENABLE_OFFSET: offset in bytes of the AESS IP
29 * block's AESS_AUTO_GATING_ENABLE__1 register from the IP block's
30 * base address
31 */
32#define AESS_AUTO_GATING_ENABLE_OFFSET 0x07c
33
34/* Register bitfields in the AESS_AUTO_GATING_ENABLE__1 register */
35#define AESS_AUTO_GATING_ENABLE_SHIFT 0
36
37/**
38 * aess_enable_autogating - enable AESS internal autogating
39 * @oh: struct omap_hwmod *
40 *
41 * Enable internal autogating on the AESS. This allows the AESS to
42 * indicate that it is idle to the OMAP PRCM. Returns 0.
43 */
44static inline void aess_enable_autogating(void __iomem *base)
45{
46 u32 v;
47
48 /* Set AESS_AUTO_GATING_ENABLE__1.ENABLE to allow idle entry */
49 v = 1 << AESS_AUTO_GATING_ENABLE_SHIFT;
50 writel(v, base + AESS_AUTO_GATING_ENABLE_OFFSET);
51}
52
53#endif /* __SOUND_AESS_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 03:08:54 -0400