MIPS: inst.h: define MT yield op

The opcode for the MT ASE yield instruction within the spec3 group was
missing. This patch adds it for use by a subsequent patch.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>

1 files changed, 11 insertions, 10 deletions

diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 044123bfab90..b7492c69aa00 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -74,16 +74,17 @@ enum spec2_op {
 enum spec3_op {
         ext_op, dextm_op, dextu_op, dext_op,
         ins_op, dinsm_op, dinsu_op, dins_op,
-        lx_op     = 0x0a, lwle_op   = 0x19,
-        lwre_op   = 0x1a, cachee_op = 0x1b,
-        sbe_op    = 0x1c, she_op    = 0x1d,
-        sce_op    = 0x1e, swe_op    = 0x1f,
-        bshfl_op  = 0x20, swle_op   = 0x21,
-        swre_op   = 0x22, prefe_op  = 0x23,
-        dbshfl_op = 0x24, lbue_op   = 0x28,
-        lhue_op   = 0x29, lbe_op    = 0x2c,
-        lhe_op    = 0x2d, lle_op    = 0x2e,
-        lwe_op    = 0x2f, rdhwr_op  = 0x3b
+        yield_op  = 0x09, lx_op     = 0x0a,
+        lwle_op   = 0x19, lwre_op   = 0x1a,
+        cachee_op = 0x1b, sbe_op    = 0x1c,
+        she_op    = 0x1d, sce_op    = 0x1e,
+        swe_op    = 0x1f, bshfl_op  = 0x20,
+        swle_op   = 0x21, swre_op   = 0x22,
+        prefe_op  = 0x23, dbshfl_op = 0x24,
+        lbue_op   = 0x28, lhue_op   = 0x29,
+        lbe_op    = 0x2c, lhe_op    = 0x2d,
+        lle_op    = 0x2e, lwe_op    = 0x2f,
+        rdhwr_op  = 0x3b
 };
 
 /*