diff options
author | Len Brown <len.brown@intel.com> | 2012-06-01 19:45:32 -0400 |
---|---|---|
committer | Len Brown <len.brown@intel.com> | 2012-06-05 15:39:11 -0400 |
commit | 6edab08c24f9141d69cfa4683a0a027d86ab303e (patch) | |
tree | ab0482f3ea7288866c380e541b54b254bbb10b28 | |
parent | 76e10d158efb6d4516018846f60c2ab5501900bc (diff) |
intel_idle: initial IVB support
From an OS point of view, IVB looks like SNB, but quicker.
Signed-off-by: Len Brown <len.brown@intel.com>
-rw-r--r-- | drivers/idle/intel_idle.c | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c index d0f59c3f87ef..a759a4c4bb0a 100644 --- a/drivers/idle/intel_idle.c +++ b/drivers/idle/intel_idle.c | |||
@@ -169,6 +169,38 @@ static struct cpuidle_state snb_cstates[MWAIT_MAX_NUM_CSTATES] = { | |||
169 | .enter = &intel_idle }, | 169 | .enter = &intel_idle }, |
170 | }; | 170 | }; |
171 | 171 | ||
172 | static struct cpuidle_state ivb_cstates[MWAIT_MAX_NUM_CSTATES] = { | ||
173 | { /* MWAIT C0 */ }, | ||
174 | { /* MWAIT C1 */ | ||
175 | .name = "C1-IVB", | ||
176 | .desc = "MWAIT 0x00", | ||
177 | .flags = CPUIDLE_FLAG_TIME_VALID, | ||
178 | .exit_latency = 1, | ||
179 | .target_residency = 1, | ||
180 | .enter = &intel_idle }, | ||
181 | { /* MWAIT C2 */ | ||
182 | .name = "C3-IVB", | ||
183 | .desc = "MWAIT 0x10", | ||
184 | .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | ||
185 | .exit_latency = 59, | ||
186 | .target_residency = 156, | ||
187 | .enter = &intel_idle }, | ||
188 | { /* MWAIT C3 */ | ||
189 | .name = "C6-IVB", | ||
190 | .desc = "MWAIT 0x20", | ||
191 | .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | ||
192 | .exit_latency = 80, | ||
193 | .target_residency = 300, | ||
194 | .enter = &intel_idle }, | ||
195 | { /* MWAIT C4 */ | ||
196 | .name = "C7-IVB", | ||
197 | .desc = "MWAIT 0x30", | ||
198 | .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, | ||
199 | .exit_latency = 87, | ||
200 | .target_residency = 300, | ||
201 | .enter = &intel_idle }, | ||
202 | }; | ||
203 | |||
172 | static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = { | 204 | static struct cpuidle_state atom_cstates[MWAIT_MAX_NUM_CSTATES] = { |
173 | { /* MWAIT C0 */ }, | 205 | { /* MWAIT C0 */ }, |
174 | { /* MWAIT C1 */ | 206 | { /* MWAIT C1 */ |
@@ -347,6 +379,10 @@ static const struct idle_cpu idle_cpu_snb = { | |||
347 | .state_table = snb_cstates, | 379 | .state_table = snb_cstates, |
348 | }; | 380 | }; |
349 | 381 | ||
382 | static const struct idle_cpu idle_cpu_ivb = { | ||
383 | .state_table = ivb_cstates, | ||
384 | }; | ||
385 | |||
350 | #define ICPU(model, cpu) \ | 386 | #define ICPU(model, cpu) \ |
351 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu } | 387 | { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu } |
352 | 388 | ||
@@ -362,6 +398,7 @@ static const struct x86_cpu_id intel_idle_ids[] = { | |||
362 | ICPU(0x2f, idle_cpu_nehalem), | 398 | ICPU(0x2f, idle_cpu_nehalem), |
363 | ICPU(0x2a, idle_cpu_snb), | 399 | ICPU(0x2a, idle_cpu_snb), |
364 | ICPU(0x2d, idle_cpu_snb), | 400 | ICPU(0x2d, idle_cpu_snb), |
401 | ICPU(0x3a, idle_cpu_ivb), | ||
365 | {} | 402 | {} |
366 | }; | 403 | }; |
367 | MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids); | 404 | MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids); |