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authorLinus Torvalds <torvalds@linux-foundation.org>2013-09-09 19:35:29 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2013-09-09 19:35:29 -0400
commit640414171818c6293c23e74a28d1c69b2a1a7fe5 (patch)
treecb3b10578f0ae39eac2930ce3b2c8a1616f5ba70
parentfa91515cbf2375a64c8bd0a033a05b0859dff591 (diff)
parenta2bdc32a527e817fdfa6c56eaa6c70f217da6c6c (diff)
Merge tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC late changes from Kevin Hilman: "These are changes that arrived a little late before the merge window, or had dependencies on previous branches. Highlights: - ux500: misc. cleanup, fixup I2C devices - exynos: DT updates for RTC; PM updates - at91: DT updates for NAND; new platforms added to generic defconfig - sunxi: DT updates: cubieboard2, pinctrl driver, gated clocks - highbank: LPAE fixes, select necessary ARM errata - omap: PM fixes and improvements; OMAP5 mailbox support - omap: basic support for new DRA7xx SoCs" * tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits) ARM: dts: vexpress: Add CCI node to TC2 device-tree ARM: EXYNOS: Skip C1 cpuidle state for exynos5440 ARM: EXYNOS: always enable PM domains support for EXYNOS4X12 ARM: highbank: clean-up some unused includes ARM: sun7i: Enable the A20 clocks in the DTSI ARM: sun6i: Enable clock support in the DTSI ARM: sun5i: dt: Use the A10s gates in the DTSI ARM: at91: at91_dt_defconfig: enable rm9200 support ARM: dts: add ADC device tree node for exynos5420/5250 ARM: dts: Add RTC DT node to Exynos5420 SoC ARM: dts: Update the "status" property of RTC DT node for Exynos5250 SoC ARM: dts: Fix the RTC DT node name for Exynos5250 irqchip: mmp: avoid to include irqs head file ARM: mmp: avoid to include head file in mach-mmp irqchip: mmp: support irqchip irqchip: move mmp irq driver ARM: OMAP: AM33xx: clock: Add RNG clock data ARM: OMAP: TI81XX: add always-on powerdomain for TI81XX ARM: OMAP4: clock: Lock PLLs in the right sequence ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSS ...
Diffstat
-rw-r--r--arch/arm/Kconfig1
-rw-r--r--arch/arm/boot/dts/Makefile1
-rw-r--r--arch/arm/boot/dts/exynos5.dtsi2
-rw-r--r--arch/arm/boot/dts/exynos5250-arndale.dts4
-rw-r--r--arch/arm/boot/dts/exynos5250-snow.dts4
-rw-r--r--arch/arm/boot/dts/exynos5250.dtsi14
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi17
-rw-r--r--arch/arm/boot/dts/sama5d3.dtsi19
-rw-r--r--arch/arm/boot/dts/sama5d3xcm.dtsi2
-rw-r--r--arch/arm/boot/dts/sun5i-a10s.dtsi36
-rw-r--r--arch/arm/boot/dts/sun6i-a31-colombus.dts2
-rw-r--r--arch/arm/boot/dts/sun6i-a31.dtsi161
-rw-r--r--arch/arm/boot/dts/sun7i-a20-cubieboard2.dts53
-rw-r--r--arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts27
-rw-r--r--arch/arm/boot/dts/sun7i-a20.dtsi157
-rw-r--r--arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts25
-rw-r--r--arch/arm/configs/at91_dt_defconfig4
-rw-r--r--arch/arm/include/asm/mach/arch.h2
-rw-r--r--arch/arm/include/asm/outercache.h4
-rw-r--r--arch/arm/mach-at91/include/mach/hardware.h1
-rw-r--r--arch/arm/mach-at91/include/mach/sama5d3.h8
-rw-r--r--arch/arm/mach-at91/include/mach/uncompress.h13
-rw-r--r--arch/arm/mach-exynos/Kconfig7
-rw-r--r--arch/arm/mach-exynos/cpuidle.c3
-rw-r--r--arch/arm/mach-highbank/Kconfig6
-rw-r--r--arch/arm/mach-highbank/highbank.c20
-rw-r--r--arch/arm/mach-mmp/Makefile2
-rw-r--r--arch/arm/mach-mmp/common.h1
-rw-r--r--arch/arm/mach-mmp/include/mach/entry-macro.S26
-rw-r--r--arch/arm/mach-mmp/include/mach/pxa168.h1
-rw-r--r--arch/arm/mach-mmp/include/mach/pxa910.h1
-rw-r--r--arch/arm/mach-mmp/mmp-dt.c8
-rw-r--r--arch/arm/mach-mmp/mmp2-dt.c8
-rw-r--r--arch/arm/mach-mmp/mmp2.c6
-rw-r--r--arch/arm/mach-mmp/pxa910.c7
-rw-r--r--arch/arm/mach-omap2/Makefile4
-rw-r--r--arch/arm/mach-omap2/board-generic.c1
-rw-r--r--arch/arm/mach-omap2/cclock33xx_data.c5
-rw-r--r--arch/arm/mach-omap2/cclock44xx_data.c20
-rw-r--r--arch/arm/mach-omap2/clockdomain.h1
-rw-r--r--arch/arm/mach-omap2/clockdomains7xx_data.c740
-rw-r--r--arch/arm/mach-omap2/cm-regbits-7xx.h51
-rw-r--r--arch/arm/mach-omap2/cm1_7xx.h324
-rw-r--r--arch/arm/mach-omap2/cm2_7xx.h513
-rw-r--r--arch/arm/mach-omap2/io.c5
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c4
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_33xx_data.c69
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_54xx_data.c42
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c2724
-rw-r--r--arch/arm/mach-omap2/powerdomain.h1
-rw-r--r--arch/arm/mach-omap2/powerdomains3xxx_data.c8
-rw-r--r--arch/arm/mach-omap2/powerdomains7xx_data.c454
-rw-r--r--arch/arm/mach-omap2/prcm-common.h1
-rw-r--r--arch/arm/mach-omap2/prcm44xx.h5
-rw-r--r--arch/arm/mach-omap2/prcm_mpu7xx.h78
-rw-r--r--arch/arm/mach-omap2/prm44xx.c12
-rw-r--r--arch/arm/mach-omap2/prm7xx.h678
-rw-r--r--arch/arm/mach-omap2/prminst44xx.c20
-rw-r--r--arch/arm/mach-ux500/board-mop500-audio.c1
-rw-r--r--arch/arm/mach-ux500/board-mop500-pins.c1
-rw-r--r--arch/arm/mach-ux500/board-mop500.c33
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c3
-rw-r--r--arch/arm/mach-ux500/pins-db8500.h746
-rw-r--r--arch/arm/mm/init.c2
-rw-r--r--drivers/dma/amba-pl08x.c23
-rw-r--r--drivers/irqchip/Makefile1
-rw-r--r--drivers/irqchip/irq-mmp.c (renamed from arch/arm/mach-mmp/irq.c)338
-rw-r--r--include/linux/irqchip/mmp.h6
69 files changed, 6486 insertions, 1082 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a00f4c1c7d71..c8a916fcd54b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -557,6 +557,7 @@ config ARCH_MMP
557 select GENERIC_CLOCKEVENTS 557 select GENERIC_CLOCKEVENTS
558 select GPIO_PXA 558 select GPIO_PXA
559 select IRQ_DOMAIN 559 select IRQ_DOMAIN
560 select MULTI_IRQ_HANDLER
560 select NEED_MACH_GPIO_H 561 select NEED_MACH_GPIO_H
561 select PINCTRL 562 select PINCTRL
562 select PLAT_PXA 563 select PLAT_PXA
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4e02f1b6c8a2..cc0f1fb61753 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -231,6 +231,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += \
231 sun5i-a10s-olinuxino-micro.dtb \ 231 sun5i-a10s-olinuxino-micro.dtb \
232 sun5i-a13-olinuxino.dtb \ 232 sun5i-a13-olinuxino.dtb \
233 sun6i-a31-colombus.dtb \ 233 sun6i-a31-colombus.dtb \
234 sun7i-a20-cubieboard2.dtb \
234 sun7i-a20-olinuxino-micro.dtb 235 sun7i-a20-olinuxino-micro.dtb
235dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \ 236dtb-$(CONFIG_ARCH_TEGRA) += tegra20-harmony.dtb \
236 tegra20-iris-512.dtb \ 237 tegra20-iris-512.dtb \
diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi
index 6afa57d2fecc..074739d39e2d 100644
--- a/arch/arm/boot/dts/exynos5.dtsi
+++ b/arch/arm/boot/dts/exynos5.dtsi
@@ -95,7 +95,7 @@
95 interrupts = <0 54 0>; 95 interrupts = <0 54 0>;
96 }; 96 };
97 97
98 rtc { 98 rtc@101E0000 {
99 compatible = "samsung,s3c6410-rtc"; 99 compatible = "samsung,s3c6410-rtc";
100 reg = <0x101E0000 0x100>; 100 reg = <0x101E0000 0x100>;
101 interrupts = <0 43 0>, <0 44 0>; 101 interrupts = <0 43 0>, <0 44 0>;
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index 452d0b04d273..cee55fa33731 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -538,10 +538,6 @@
538 }; 538 };
539 }; 539 };
540 540
541 rtc {
542 status = "okay";
543 };
544
545 usb_hub_bus { 541 usb_hub_bus {
546 compatible = "simple-bus"; 542 compatible = "simple-bus";
547 #address-cells = <1>; 543 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/exynos5250-snow.dts b/arch/arm/boot/dts/exynos5250-snow.dts
index e79331dba12d..fd711e245e8d 100644
--- a/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/arch/arm/boot/dts/exynos5250-snow.dts
@@ -171,10 +171,6 @@
171 }; 171 };
172 }; 172 };
173 173
174 rtc {
175 status = "okay";
176 };
177
178 /* 174 /*
179 * On Snow we've got SIP WiFi and so can keep drive strengths low to 175 * On Snow we've got SIP WiFi and so can keep drive strengths low to
180 * reduce EMI. 176 * reduce EMI.
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index f7e2d3493f82..7d7cc777ff7b 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -180,9 +180,10 @@
180 clock-names = "mfc"; 180 clock-names = "mfc";
181 }; 181 };
182 182
183 rtc { 183 rtc@101E0000 {
184 clocks = <&clock 337>; 184 clocks = <&clock 337>;
185 clock-names = "rtc"; 185 clock-names = "rtc";
186 status = "okay";
186 }; 187 };
187 188
188 tmu@10060000 { 189 tmu@10060000 {
@@ -638,4 +639,15 @@
638 clocks = <&clock 133>, <&clock 339>; 639 clocks = <&clock 133>, <&clock 339>;
639 clock-names = "sclk_fimd", "fimd"; 640 clock-names = "sclk_fimd", "fimd";
640 }; 641 };
642
643 adc: adc@12D10000 {
644 compatible = "samsung,exynos-adc-v1";
645 reg = <0x12D10000 0x100>, <0x10040718 0x4>;
646 interrupts = <0 106 0>;
647 clocks = <&clock 303>;
648 clock-names = "adc";
649 #io-channel-cells = <1>;
650 io-channel-ranges;
651 status = "disabled";
652 };
641}; 653};
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 5353e32897a4..d537cd704e19 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -180,6 +180,12 @@
180 interrupts = <0 47 0>; 180 interrupts = <0 47 0>;
181 }; 181 };
182 182
183 rtc@101E0000 {
184 clocks = <&clock 317>;
185 clock-names = "rtc";
186 status = "okay";
187 };
188
183 serial@12C00000 { 189 serial@12C00000 {
184 clocks = <&clock 257>, <&clock 128>; 190 clocks = <&clock 257>, <&clock 128>;
185 clock-names = "uart", "clk_uart_baud0"; 191 clock-names = "uart", "clk_uart_baud0";
@@ -218,4 +224,15 @@
218 clocks = <&clock 147>, <&clock 421>; 224 clocks = <&clock 147>, <&clock 421>;
219 clock-names = "sclk_fimd", "fimd"; 225 clock-names = "sclk_fimd", "fimd";
220 }; 226 };
227
228 adc: adc@12D10000 {
229 compatible = "samsung,exynos-adc-v2";
230 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
231 interrupts = <0 106 0>;
232 clocks = <&clock 270>;
233 clock-names = "adc";
234 #io-channel-cells = <1>;
235 io-channel-ranges;
236 status = "disabled";
237 };
221}; 238};
diff --git a/arch/arm/boot/dts/sama5d3.dtsi b/arch/arm/boot/dts/sama5d3.dtsi
index ff63fbbd18ab..b7f49615120d 100644
--- a/arch/arm/boot/dts/sama5d3.dtsi
+++ b/arch/arm/boot/dts/sama5d3.dtsi
@@ -1034,21 +1034,30 @@
1034 compatible = "atmel,at91rm9200-nand"; 1034 compatible = "atmel,at91rm9200-nand";
1035 #address-cells = <1>; 1035 #address-cells = <1>;
1036 #size-cells = <1>; 1036 #size-cells = <1>;
1037 ranges;
1037 reg = < 0x60000000 0x01000000 /* EBI CS3 */ 1038 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1038 0xffffc070 0x00000490 /* SMC PMECC regs */ 1039 0xffffc070 0x00000490 /* SMC PMECC regs */
1039 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ 1040 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
1040 0x00100000 0x00100000 /* ROM code */ 1041 0x00110000 0x00018000 /* ROM code */
1041 0x70000000 0x10000000 /* NFC Command Registers */
1042 0xffffc000 0x00000070 /* NFC HSMC regs */
1043 0x00200000 0x00100000 /* NFC SRAM banks */
1044 >; 1042 >;
1045 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; 1043 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
1046 atmel,nand-addr-offset = <21>; 1044 atmel,nand-addr-offset = <21>;
1047 atmel,nand-cmd-offset = <22>; 1045 atmel,nand-cmd-offset = <22>;
1048 pinctrl-names = "default"; 1046 pinctrl-names = "default";
1049 pinctrl-0 = <&pinctrl_nand0_ale_cle>; 1047 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
1050 atmel,pmecc-lookup-table-offset = <0x10000 0x18000>; 1048 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
1051 status = "disabled"; 1049 status = "disabled";
1050
1051 nfc@70000000 {
1052 compatible = "atmel,sama5d3-nfc";
1053 #address-cells = <1>;
1054 #size-cells = <1>;
1055 reg = <
1056 0x70000000 0x10000000 /* NFC Command Registers */
1057 0xffffc000 0x00000070 /* NFC HSMC regs */
1058 0x00200000 0x00100000 /* NFC SRAM banks */
1059 >;
1060 };
1052 }; 1061 };
1053 }; 1062 };
1054}; 1063};
diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi
index 1f8050813a54..31ed9e3bb649 100644
--- a/arch/arm/boot/dts/sama5d3xcm.dtsi
+++ b/arch/arm/boot/dts/sama5d3xcm.dtsi
@@ -47,8 +47,6 @@
47 atmel,has-pmecc; 47 atmel,has-pmecc;
48 atmel,pmecc-cap = <4>; 48 atmel,pmecc-cap = <4>;
49 atmel,pmecc-sector-size = <512>; 49 atmel,pmecc-sector-size = <512>;
50 atmel,has-nfc;
51 atmel,use-nfc-sram;
52 nand-on-flash-bbt; 50 nand-on-flash-bbt;
53 status = "okay"; 51 status = "okay";
54 52
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index ee0ff9ba1bca..3b4a0574f068 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -95,20 +95,16 @@
95 95
96 ahb_gates: ahb_gates@01c20060 { 96 ahb_gates: ahb_gates@01c20060 {
97 #clock-cells = <1>; 97 #clock-cells = <1>;
98 compatible = "allwinner,sun4i-ahb-gates-clk"; 98 compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
99 reg = <0x01c20060 0x8>; 99 reg = <0x01c20060 0x8>;
100 clocks = <&ahb>; 100 clocks = <&ahb>;
101 clock-output-names = "ahb_usb0", "ahb_ehci0", 101 clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
102 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", 102 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
103 "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", 103 "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
104 "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", 104 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
105 "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", 105 "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve",
106 "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", 106 "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi",
107 "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", 107 "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400";
108 "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
109 "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
110 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
111 "ahb_de_fe1", "ahb_mp", "ahb_mali400";
112 }; 108 };
113 109
114 apb0: apb0@01c20054 { 110 apb0: apb0@01c20054 {
@@ -120,12 +116,11 @@
120 116
121 apb0_gates: apb0_gates@01c20068 { 117 apb0_gates: apb0_gates@01c20068 {
122 #clock-cells = <1>; 118 #clock-cells = <1>;
123 compatible = "allwinner,sun4i-apb0-gates-clk"; 119 compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
124 reg = <0x01c20068 0x4>; 120 reg = <0x01c20068 0x4>;
125 clocks = <&apb0>; 121 clocks = <&apb0>;
126 clock-output-names = "apb0_codec", "apb0_spdif", 122 clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio",
127 "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", 123 "apb0_ir", "apb0_keypad";
128 "apb0_ir1", "apb0_keypad";
129 }; 124 };
130 125
131 /* dummy is pll62 */ 126 /* dummy is pll62 */
@@ -145,15 +140,12 @@
145 140
146 apb1_gates: apb1_gates@01c2006c { 141 apb1_gates: apb1_gates@01c2006c {
147 #clock-cells = <1>; 142 #clock-cells = <1>;
148 compatible = "allwinner,sun4i-apb1-gates-clk"; 143 compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
149 reg = <0x01c2006c 0x4>; 144 reg = <0x01c2006c 0x4>;
150 clocks = <&apb1>; 145 clocks = <&apb1>;
151 clock-output-names = "apb1_i2c0", "apb1_i2c1", 146 clock-output-names = "apb1_i2c0", "apb1_i2c1",
152 "apb1_i2c2", "apb1_can", "apb1_scr", 147 "apb1_i2c2", "apb1_uart0", "apb1_uart1",
153 "apb1_ps20", "apb1_ps21", "apb1_uart0", 148 "apb1_uart2", "apb1_uart3";
154 "apb1_uart1", "apb1_uart2", "apb1_uart3",
155 "apb1_uart4", "apb1_uart5", "apb1_uart6",
156 "apb1_uart7";
157 }; 149 };
158 }; 150 };
159 151
diff --git a/arch/arm/boot/dts/sun6i-a31-colombus.dts b/arch/arm/boot/dts/sun6i-a31-colombus.dts
index 99c4b1847cab..e5adae30899b 100644
--- a/arch/arm/boot/dts/sun6i-a31-colombus.dts
+++ b/arch/arm/boot/dts/sun6i-a31-colombus.dts
@@ -24,6 +24,8 @@
24 24
25 soc@01c00000 { 25 soc@01c00000 {
26 uart0: serial@01c28000 { 26 uart0: serial@01c28000 {
27 pinctrl-names = "default";
28 pinctrl-0 = <&uart0_pins_a>;
27 status = "okay"; 29 status = "okay";
28 }; 30 };
29 }; 31 };
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 4d076ec24885..f244f5f02365 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -51,13 +51,137 @@
51 51
52 clocks { 52 clocks {
53 #address-cells = <1>; 53 #address-cells = <1>;
54 #size-cells = <0>; 54 #size-cells = <1>;
55 ranges;
55 56
56 osc: oscillator { 57 osc24M: osc24M {
57 #clock-cells = <0>; 58 #clock-cells = <0>;
58 compatible = "fixed-clock"; 59 compatible = "fixed-clock";
59 clock-frequency = <24000000>; 60 clock-frequency = <24000000>;
60 }; 61 };
62
63 osc32k: osc32k {
64 #clock-cells = <0>;
65 compatible = "fixed-clock";
66 clock-frequency = <32768>;
67 };
68
69 pll1: pll1@01c20000 {
70 #clock-cells = <0>;
71 compatible = "allwinner,sun6i-a31-pll1-clk";
72 reg = <0x01c20000 0x4>;
73 clocks = <&osc24M>;
74 };
75
76 /*
77 * This is a dummy clock, to be used as placeholder on
78 * other mux clocks when a specific parent clock is not
79 * yet implemented. It should be dropped when the driver
80 * is complete.
81 */
82 pll6: pll6 {
83 #clock-cells = <0>;
84 compatible = "fixed-clock";
85 clock-frequency = <0>;
86 };
87
88 cpu: cpu@01c20050 {
89 #clock-cells = <0>;
90 compatible = "allwinner,sun4i-cpu-clk";
91 reg = <0x01c20050 0x4>;
92
93 /*
94 * PLL1 is listed twice here.
95 * While it looks suspicious, it's actually documented
96 * that way both in the datasheet and in the code from
97 * Allwinner.
98 */
99 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
100 };
101
102 axi: axi@01c20050 {
103 #clock-cells = <0>;
104 compatible = "allwinner,sun4i-axi-clk";
105 reg = <0x01c20050 0x4>;
106 clocks = <&cpu>;
107 };
108
109 ahb1_mux: ahb1_mux@01c20054 {
110 #clock-cells = <0>;
111 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
112 reg = <0x01c20054 0x4>;
113 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
114 };
115
116 ahb1: ahb1@01c20054 {
117 #clock-cells = <0>;
118 compatible = "allwinner,sun4i-ahb-clk";
119 reg = <0x01c20054 0x4>;
120 clocks = <&ahb1_mux>;
121 };
122
123 ahb1_gates: ahb1_gates@01c20060 {
124 #clock-cells = <1>;
125 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
126 reg = <0x01c20060 0x8>;
127 clocks = <&ahb1>;
128 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
129 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
130 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
131 "ahb1_nand0", "ahb1_sdram",
132 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
133 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
134 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
135 "ahb1_ehci1", "ahb1_ohci0",
136 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
137 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
138 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
139 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
140 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
141 "ahb1_drc0", "ahb1_drc1";
142 };
143
144 apb1: apb1@01c20054 {
145 #clock-cells = <0>;
146 compatible = "allwinner,sun4i-apb0-clk";
147 reg = <0x01c20054 0x4>;
148 clocks = <&ahb1>;
149 };
150
151 apb1_gates: apb1_gates@01c20060 {
152 #clock-cells = <1>;
153 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
154 reg = <0x01c20068 0x4>;
155 clocks = <&apb1>;
156 clock-output-names = "apb1_codec", "apb1_digital_mic",
157 "apb1_pio", "apb1_daudio0",
158 "apb1_daudio1";
159 };
160
161 apb2_mux: apb2_mux@01c20058 {
162 #clock-cells = <0>;
163 compatible = "allwinner,sun4i-apb1-mux-clk";
164 reg = <0x01c20058 0x4>;
165 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
166 };
167
168 apb2: apb2@01c20058 {
169 #clock-cells = <0>;
170 compatible = "allwinner,sun6i-a31-apb2-div-clk";
171 reg = <0x01c20058 0x4>;
172 clocks = <&apb2_mux>;
173 };
174
175 apb2_gates: apb2_gates@01c2006c {
176 #clock-cells = <1>;
177 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
178 reg = <0x01c2006c 0x8>;
179 clocks = <&apb2>;
180 clock-output-names = "apb2_i2c0", "apb2_i2c1",
181 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
182 "apb2_uart1", "apb2_uart2", "apb2_uart3",
183 "apb2_uart4", "apb2_uart5";
184 };
61 }; 185 };
62 186
63 soc@01c00000 { 187 soc@01c00000 {
@@ -66,6 +190,25 @@
66 #size-cells = <1>; 190 #size-cells = <1>;
67 ranges; 191 ranges;
68 192
193 pio: pinctrl@01c20800 {
194 compatible = "allwinner,sun6i-a31-pinctrl";
195 reg = <0x01c20800 0x400>;
196 interrupts = <0 11 1>, <0 15 1>, <0 16 1>, <0 17 1>;
197 clocks = <&apb1_gates 5>;
198 gpio-controller;
199 interrupt-controller;
200 #address-cells = <1>;
201 #size-cells = <0>;
202 #gpio-cells = <3>;
203
204 uart0_pins_a: uart0@0 {
205 allwinner,pins = "PH20", "PH21";
206 allwinner,function = "uart0";
207 allwinner,drive = <0>;
208 allwinner,pull = <0>;
209 };
210 };
211
69 timer@01c20c00 { 212 timer@01c20c00 {
70 compatible = "allwinner,sun4i-timer"; 213 compatible = "allwinner,sun4i-timer";
71 reg = <0x01c20c00 0xa0>; 214 reg = <0x01c20c00 0xa0>;
@@ -74,7 +217,7 @@
74 <0 20 1>, 217 <0 20 1>,
75 <0 21 1>, 218 <0 21 1>,
76 <0 22 1>; 219 <0 22 1>;
77 clocks = <&osc>; 220 clocks = <&osc24M>;
78 }; 221 };
79 222
80 wdt1: watchdog@01c20ca0 { 223 wdt1: watchdog@01c20ca0 {
@@ -88,7 +231,7 @@
88 interrupts = <0 0 1>; 231 interrupts = <0 0 1>;
89 reg-shift = <2>; 232 reg-shift = <2>;
90 reg-io-width = <4>; 233 reg-io-width = <4>;
91 clocks = <&osc>; 234 clocks = <&apb2_gates 16>;
92 status = "disabled"; 235 status = "disabled";
93 }; 236 };
94 237
@@ -98,7 +241,7 @@
98 interrupts = <0 1 1>; 241 interrupts = <0 1 1>;
99 reg-shift = <2>; 242 reg-shift = <2>;
100 reg-io-width = <4>; 243 reg-io-width = <4>;
101 clocks = <&osc>; 244 clocks = <&apb2_gates 17>;
102 status = "disabled"; 245 status = "disabled";
103 }; 246 };
104 247
@@ -108,7 +251,7 @@
108 interrupts = <0 2 1>; 251 interrupts = <0 2 1>;
109 reg-shift = <2>; 252 reg-shift = <2>;
110 reg-io-width = <4>; 253 reg-io-width = <4>;
111 clocks = <&osc>; 254 clocks = <&apb2_gates 18>;
112 status = "disabled"; 255 status = "disabled";
113 }; 256 };
114 257
@@ -118,7 +261,7 @@
118 interrupts = <0 3 1>; 261 interrupts = <0 3 1>;
119 reg-shift = <2>; 262 reg-shift = <2>;
120 reg-io-width = <4>; 263 reg-io-width = <4>;
121 clocks = <&osc>; 264 clocks = <&apb2_gates 19>;
122 status = "disabled"; 265 status = "disabled";
123 }; 266 };
124 267
@@ -128,7 +271,7 @@
128 interrupts = <0 4 1>; 271 interrupts = <0 4 1>;
129 reg-shift = <2>; 272 reg-shift = <2>;
130 reg-io-width = <4>; 273 reg-io-width = <4>;
131 clocks = <&osc>; 274 clocks = <&apb2_gates 20>;
132 status = "disabled"; 275 status = "disabled";
133 }; 276 };
134 277
@@ -138,7 +281,7 @@
138 interrupts = <0 5 1>; 281 interrupts = <0 5 1>;
139 reg-shift = <2>; 282 reg-shift = <2>;
140 reg-io-width = <4>; 283 reg-io-width = <4>;
141 clocks = <&osc>; 284 clocks = <&apb2_gates 21>;
142 status = "disabled"; 285 status = "disabled";
143 }; 286 };
144 287
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
new file mode 100644
index 000000000000..31b76f08b3ad
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -0,0 +1,53 @@
1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/dts-v1/;
15/include/ "sun7i-a20.dtsi"
16
17/ {
18 model = "Cubietech Cubieboard2";
19 compatible = "cubietech,cubieboard2", "allwinner,sun7i-a20";
20
21 soc@01c00000 {
22 pinctrl@01c20800 {
23 led_pins_cubieboard2: led_pins@0 {
24 allwinner,pins = "PH20", "PH21";
25 allwinner,function = "gpio_out";
26 allwinner,drive = <0>;
27 allwinner,pull = <0>;
28 };
29 };
30
31 uart0: serial@01c28000 {
32 pinctrl-names = "default";
33 pinctrl-0 = <&uart0_pins_a>;
34 status = "okay";
35 };
36 };
37
38 leds {
39 compatible = "gpio-leds";
40 pinctrl-names = "default";
41 pinctrl-0 = <&led_pins_cubieboard2>;
42
43 blue {
44 label = "cubieboard2:blue:usr";
45 gpios = <&pio 7 21 0>;
46 };
47
48 green {
49 label = "cubieboard2:green:usr";
50 gpios = <&pio 7 20 0>;
51 };
52 };
53};
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index d3395846491c..34a6c02a7c72 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -19,16 +19,43 @@
19 compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20"; 19 compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
20 20
21 soc@01c00000 { 21 soc@01c00000 {
22 pinctrl@01c20800 {
23 led_pins_olinuxino: led_pins@0 {
24 allwinner,pins = "PH2";
25 allwinner,function = "gpio_out";
26 allwinner,drive = <1>;
27 allwinner,pull = <0>;
28 };
29 };
30
22 uart0: serial@01c28000 { 31 uart0: serial@01c28000 {
32 pinctrl-names = "default";
33 pinctrl-0 = <&uart0_pins_a>;
23 status = "okay"; 34 status = "okay";
24 }; 35 };
25 36
26 uart6: serial@01c29800 { 37 uart6: serial@01c29800 {
38 pinctrl-names = "default";
39 pinctrl-0 = <&uart6_pins_a>;
27 status = "okay"; 40 status = "okay";
28 }; 41 };
29 42
30 uart7: serial@01c29c00 { 43 uart7: serial@01c29c00 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&uart7_pins_a>;
31 status = "okay"; 46 status = "okay";
32 }; 47 };
33 }; 48 };
49
50 leds {
51 compatible = "gpio-leds";
52 pinctrl-names = "default";
53 pinctrl-0 = <&led_pins_olinuxino>;
54
55 green {
56 label = "a20-olinuxino-micro:green:usr";
57 gpios = <&pio 7 2 0>;
58 default-state = "on";
59 };
60 };
34}; 61};
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 33391517118c..999ff45cb77e 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -44,7 +44,8 @@
44 44
45 osc24M: osc24M@01c20050 { 45 osc24M: osc24M@01c20050 {
46 #clock-cells = <0>; 46 #clock-cells = <0>;
47 compatible = "fixed-clock"; 47 compatible = "allwinner,sun4i-osc-clk";
48 reg = <0x01c20050 0x4>;
48 clock-frequency = <24000000>; 49 clock-frequency = <24000000>;
49 }; 50 };
50 51
@@ -53,6 +54,111 @@
53 compatible = "fixed-clock"; 54 compatible = "fixed-clock";
54 clock-frequency = <32768>; 55 clock-frequency = <32768>;
55 }; 56 };
57
58 pll1: pll1@01c20000 {
59 #clock-cells = <0>;
60 compatible = "allwinner,sun4i-pll1-clk";
61 reg = <0x01c20000 0x4>;
62 clocks = <&osc24M>;
63 };
64
65 /*
66 * This is a dummy clock, to be used as placeholder on
67 * other mux clocks when a specific parent clock is not
68 * yet implemented. It should be dropped when the driver
69 * is complete.
70 */
71 pll6: pll6 {
72 #clock-cells = <0>;
73 compatible = "fixed-clock";
74 clock-frequency = <0>;
75 };
76
77 cpu: cpu@01c20054 {
78 #clock-cells = <0>;
79 compatible = "allwinner,sun4i-cpu-clk";
80 reg = <0x01c20054 0x4>;
81 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6>;
82 };
83
84 axi: axi@01c20054 {
85 #clock-cells = <0>;
86 compatible = "allwinner,sun4i-axi-clk";
87 reg = <0x01c20054 0x4>;
88 clocks = <&cpu>;
89 };
90
91 ahb: ahb@01c20054 {
92 #clock-cells = <0>;
93 compatible = "allwinner,sun4i-ahb-clk";
94 reg = <0x01c20054 0x4>;
95 clocks = <&axi>;
96 };
97
98 ahb_gates: ahb_gates@01c20060 {
99 #clock-cells = <1>;
100 compatible = "allwinner,sun7i-a20-ahb-gates-clk";
101 reg = <0x01c20060 0x8>;
102 clocks = <&ahb>;
103 clock-output-names = "ahb_usb0", "ahb_ehci0",
104 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
105 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
106 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
107 "ahb_nand", "ahb_sdram", "ahb_ace",
108 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
109 "ahb_spi2", "ahb_spi3", "ahb_sata",
110 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
111 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
112 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
113 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
114 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
115 "ahb_mali";
116 };
117
118 apb0: apb0@01c20054 {
119 #clock-cells = <0>;
120 compatible = "allwinner,sun4i-apb0-clk";
121 reg = <0x01c20054 0x4>;
122 clocks = <&ahb>;
123 };
124
125 apb0_gates: apb0_gates@01c20068 {
126 #clock-cells = <1>;
127 compatible = "allwinner,sun7i-a20-apb0-gates-clk";
128 reg = <0x01c20068 0x4>;
129 clocks = <&apb0>;
130 clock-output-names = "apb0_codec", "apb0_spdif",
131 "apb0_ac97", "apb0_iis0", "apb0_iis1",
132 "apb0_pio", "apb0_ir0", "apb0_ir1",
133 "apb0_iis2", "apb0_keypad";
134 };
135
136 apb1_mux: apb1_mux@01c20058 {
137 #clock-cells = <0>;
138 compatible = "allwinner,sun4i-apb1-mux-clk";
139 reg = <0x01c20058 0x4>;
140 clocks = <&osc24M>, <&pll6>, <&osc32k>;
141 };
142
143 apb1: apb1@01c20058 {
144 #clock-cells = <0>;
145 compatible = "allwinner,sun4i-apb1-clk";
146 reg = <0x01c20058 0x4>;
147 clocks = <&apb1_mux>;
148 };
149
150 apb1_gates: apb1_gates@01c2006c {
151 #clock-cells = <1>;
152 compatible = "allwinner,sun7i-a20-apb1-gates-clk";
153 reg = <0x01c2006c 0x4>;
154 clocks = <&apb1>;
155 clock-output-names = "apb1_i2c0", "apb1_i2c1",
156 "apb1_i2c2", "apb1_i2c3", "apb1_can",
157 "apb1_scr", "apb1_ps20", "apb1_ps21",
158 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
159 "apb1_uart2", "apb1_uart3", "apb1_uart4",
160 "apb1_uart5", "apb1_uart6", "apb1_uart7";
161 };
56 }; 162 };
57 163
58 soc@01c00000 { 164 soc@01c00000 {
@@ -61,6 +167,39 @@
61 #size-cells = <1>; 167 #size-cells = <1>;
62 ranges; 168 ranges;
63 169
170 pio: pinctrl@01c20800 {
171 compatible = "allwinner,sun7i-a20-pinctrl";
172 reg = <0x01c20800 0x400>;
173 interrupts = <0 28 1>;
174 clocks = <&apb0_gates 5>;
175 gpio-controller;
176 interrupt-controller;
177 #address-cells = <1>;
178 #size-cells = <0>;
179 #gpio-cells = <3>;
180
181 uart0_pins_a: uart0@0 {
182 allwinner,pins = "PB22", "PB23";
183 allwinner,function = "uart0";
184 allwinner,drive = <0>;
185 allwinner,pull = <0>;
186 };
187
188 uart6_pins_a: uart6@0 {
189 allwinner,pins = "PI12", "PI13";
190 allwinner,function = "uart6";
191 allwinner,drive = <0>;
192 allwinner,pull = <0>;
193 };
194
195 uart7_pins_a: uart7@0 {
196 allwinner,pins = "PI20", "PI21";
197 allwinner,function = "uart7";
198 allwinner,drive = <0>;
199 allwinner,pull = <0>;
200 };
201 };
202
64 timer@01c20c00 { 203 timer@01c20c00 {
65 compatible = "allwinner,sun4i-timer"; 204 compatible = "allwinner,sun4i-timer";
66 reg = <0x01c20c00 0x90>; 205 reg = <0x01c20c00 0x90>;
@@ -84,7 +223,7 @@
84 interrupts = <0 1 1>; 223 interrupts = <0 1 1>;
85 reg-shift = <2>; 224 reg-shift = <2>;
86 reg-io-width = <4>; 225 reg-io-width = <4>;
87 clocks = <&osc24M>; 226 clocks = <&apb1_gates 16>;
88 status = "disabled"; 227 status = "disabled";
89 }; 228 };
90 229
@@ -94,7 +233,7 @@
94 interrupts = <0 2 1>; 233 interrupts = <0 2 1>;
95 reg-shift = <2>; 234 reg-shift = <2>;
96 reg-io-width = <4>; 235 reg-io-width = <4>;
97 clocks = <&osc24M>; 236 clocks = <&apb1_gates 17>;
98 status = "disabled"; 237 status = "disabled";
99 }; 238 };
100 239
@@ -104,7 +243,7 @@
104 interrupts = <0 3 1>; 243 interrupts = <0 3 1>;
105 reg-shift = <2>; 244 reg-shift = <2>;
106 reg-io-width = <4>; 245 reg-io-width = <4>;
107 clocks = <&osc24M>; 246 clocks = <&apb1_gates 18>;
108 status = "disabled"; 247 status = "disabled";
109 }; 248 };
110 249
@@ -114,7 +253,7 @@
114 interrupts = <0 4 1>; 253 interrupts = <0 4 1>;
115 reg-shift = <2>; 254 reg-shift = <2>;
116 reg-io-width = <4>; 255 reg-io-width = <4>;
117 clocks = <&osc24M>; 256 clocks = <&apb1_gates 19>;
118 status = "disabled"; 257 status = "disabled";
119 }; 258 };
120 259
@@ -124,7 +263,7 @@
124 interrupts = <0 17 1>; 263 interrupts = <0 17 1>;
125 reg-shift = <2>; 264 reg-shift = <2>;
126 reg-io-width = <4>; 265 reg-io-width = <4>;
127 clocks = <&osc24M>; 266 clocks = <&apb1_gates 20>;
128 status = "disabled"; 267 status = "disabled";
129 }; 268 };
130 269
@@ -134,7 +273,7 @@
134 interrupts = <0 18 1>; 273 interrupts = <0 18 1>;
135 reg-shift = <2>; 274 reg-shift = <2>;
136 reg-io-width = <4>; 275 reg-io-width = <4>;
137 clocks = <&osc24M>; 276 clocks = <&apb1_gates 21>;
138 status = "disabled"; 277 status = "disabled";
139 }; 278 };
140 279
@@ -144,7 +283,7 @@
144 interrupts = <0 19 1>; 283 interrupts = <0 19 1>;
145 reg-shift = <2>; 284 reg-shift = <2>;
146 reg-io-width = <4>; 285 reg-io-width = <4>;
147 clocks = <&osc24M>; 286 clocks = <&apb1_gates 22>;
148 status = "disabled"; 287 status = "disabled";
149 }; 288 };
150 289
@@ -154,7 +293,7 @@
154 interrupts = <0 20 1>; 293 interrupts = <0 20 1>;
155 reg-shift = <2>; 294 reg-shift = <2>;
156 reg-io-width = <4>; 295 reg-io-width = <4>;
157 clocks = <&osc24M>; 296 clocks = <&apb1_gates 23>;
158 status = "disabled"; 297 status = "disabled";
159 }; 298 };
160 299
diff --git a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
index 759b0cd20013..15f98cbcb75a 100644
--- a/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
+++ b/arch/arm/boot/dts/vexpress-v2p-ca15_a7.dts
@@ -37,30 +37,35 @@
37 device_type = "cpu"; 37 device_type = "cpu";
38 compatible = "arm,cortex-a15"; 38 compatible = "arm,cortex-a15";
39 reg = <0>; 39 reg = <0>;
40 cci-control-port = <&cci_control1>;
40 }; 41 };
41 42
42 cpu1: cpu@1 { 43 cpu1: cpu@1 {
43 device_type = "cpu"; 44 device_type = "cpu";
44 compatible = "arm,cortex-a15"; 45 compatible = "arm,cortex-a15";
45 reg = <1>; 46 reg = <1>;
47 cci-control-port = <&cci_control1>;
46 }; 48 };
47 49
48 cpu2: cpu@2 { 50 cpu2: cpu@2 {
49 device_type = "cpu"; 51 device_type = "cpu";
50 compatible = "arm,cortex-a7"; 52 compatible = "arm,cortex-a7";
51 reg = <0x100>; 53 reg = <0x100>;
54 cci-control-port = <&cci_control2>;
52 }; 55 };
53 56
54 cpu3: cpu@3 { 57 cpu3: cpu@3 {
55 device_type = "cpu"; 58 device_type = "cpu";
56 compatible = "arm,cortex-a7"; 59 compatible = "arm,cortex-a7";
57 reg = <0x101>; 60 reg = <0x101>;
61 cci-control-port = <&cci_control2>;
58 }; 62 };
59 63
60 cpu4: cpu@4 { 64 cpu4: cpu@4 {
61 device_type = "cpu"; 65 device_type = "cpu";
62 compatible = "arm,cortex-a7"; 66 compatible = "arm,cortex-a7";
63 reg = <0x102>; 67 reg = <0x102>;
68 cci-control-port = <&cci_control2>;
64 }; 69 };
65 }; 70 };
66 71
@@ -104,6 +109,26 @@
104 interrupts = <1 9 0xf04>; 109 interrupts = <1 9 0xf04>;
105 }; 110 };
106 111
112 cci@2c090000 {
113 compatible = "arm,cci-400";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 reg = <0 0x2c090000 0 0x1000>;
117 ranges = <0x0 0x0 0x2c090000 0x10000>;
118
119 cci_control1: slave-if@4000 {
120 compatible = "arm,cci-400-ctrl-if";
121 interface-type = "ace";
122 reg = <0x4000 0x1000>;
123 };
124
125 cci_control2: slave-if@5000 {
126 compatible = "arm,cci-400-ctrl-if";
127 interface-type = "ace";
128 reg = <0x5000 0x1000>;
129 };
130 };
131
107 memory-controller@7ffd0000 { 132 memory-controller@7ffd0000 {
108 compatible = "arm,pl354", "arm,primecell"; 133 compatible = "arm,pl354", "arm,primecell";
109 reg = <0 0x7ffd0000 0 0x1000>; 134 reg = <0 0x7ffd0000 0 0x1000>;
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 75fd842d4071..690e89273230 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -14,11 +14,13 @@ CONFIG_MODULE_UNLOAD=y
14# CONFIG_IOSCHED_DEADLINE is not set 14# CONFIG_IOSCHED_DEADLINE is not set
15# CONFIG_IOSCHED_CFQ is not set 15# CONFIG_IOSCHED_CFQ is not set
16CONFIG_ARCH_AT91=y 16CONFIG_ARCH_AT91=y
17CONFIG_SOC_AT91RM9200=y
17CONFIG_SOC_AT91SAM9260=y 18CONFIG_SOC_AT91SAM9260=y
18CONFIG_SOC_AT91SAM9263=y 19CONFIG_SOC_AT91SAM9263=y
19CONFIG_SOC_AT91SAM9G45=y 20CONFIG_SOC_AT91SAM9G45=y
20CONFIG_SOC_AT91SAM9X5=y 21CONFIG_SOC_AT91SAM9X5=y
21CONFIG_SOC_AT91SAM9N12=y 22CONFIG_SOC_AT91SAM9N12=y
23CONFIG_MACH_AT91RM9200_DT=y
22CONFIG_MACH_AT91SAM9_DT=y 24CONFIG_MACH_AT91SAM9_DT=y
23CONFIG_AT91_PROGRAMMABLE_CLOCKS=y 25CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
24CONFIG_AT91_TIMER_HZ=128 26CONFIG_AT91_TIMER_HZ=128
@@ -62,6 +64,7 @@ CONFIG_MTD=y
62CONFIG_MTD_CMDLINE_PARTS=y 64CONFIG_MTD_CMDLINE_PARTS=y
63CONFIG_MTD_CHAR=y 65CONFIG_MTD_CHAR=y
64CONFIG_MTD_BLOCK=y 66CONFIG_MTD_BLOCK=y
67CONFIG_MTD_DATAFLASH=y
65CONFIG_MTD_NAND=y 68CONFIG_MTD_NAND=y
66CONFIG_MTD_NAND_ATMEL=y 69CONFIG_MTD_NAND_ATMEL=y
67CONFIG_MTD_UBI=y 70CONFIG_MTD_UBI=y
@@ -78,7 +81,6 @@ CONFIG_BLK_DEV_SD=y
78CONFIG_SCSI_MULTI_LUN=y 81CONFIG_SCSI_MULTI_LUN=y
79# CONFIG_SCSI_LOWLEVEL is not set 82# CONFIG_SCSI_LOWLEVEL is not set
80CONFIG_NETDEVICES=y 83CONFIG_NETDEVICES=y
81CONFIG_MII=y
82CONFIG_MACB=y 84CONFIG_MACB=y
83# CONFIG_NET_VENDOR_BROADCOM is not set 85# CONFIG_NET_VENDOR_BROADCOM is not set
84# CONFIG_NET_VENDOR_FARADAY is not set 86# CONFIG_NET_VENDOR_FARADAY is not set
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index 69b879ac0289..402a2bc6aa68 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -35,7 +35,7 @@ struct machine_desc {
35 unsigned int nr_irqs; /* number of IRQs */ 35 unsigned int nr_irqs; /* number of IRQs */
36 36
37#ifdef CONFIG_ZONE_DMA 37#ifdef CONFIG_ZONE_DMA
38 unsigned long dma_zone_size; /* size of DMA-able area */ 38 phys_addr_t dma_zone_size; /* size of DMA-able area */
39#endif 39#endif
40 40
41 unsigned int video_start; /* start of video RAM */ 41 unsigned int video_start; /* start of video RAM */
diff --git a/arch/arm/include/asm/outercache.h b/arch/arm/include/asm/outercache.h
index 12f71a190422..f94784f0e3a6 100644
--- a/arch/arm/include/asm/outercache.h
+++ b/arch/arm/include/asm/outercache.h
@@ -37,10 +37,10 @@ struct outer_cache_fns {
37 void (*resume)(void); 37 void (*resume)(void);
38}; 38};
39 39
40#ifdef CONFIG_OUTER_CACHE
41
42extern struct outer_cache_fns outer_cache; 40extern struct outer_cache_fns outer_cache;
43 41
42#ifdef CONFIG_OUTER_CACHE
43
44static inline void outer_inv_range(phys_addr_t start, phys_addr_t end) 44static inline void outer_inv_range(phys_addr_t start, phys_addr_t end)
45{ 45{
46 if (outer_cache.inv_range) 46 if (outer_cache.inv_range)
diff --git a/arch/arm/mach-at91/include/mach/hardware.h b/arch/arm/mach-at91/include/mach/hardware.h
index a832e0707611..f17aa3150019 100644
--- a/arch/arm/mach-at91/include/mach/hardware.h
+++ b/arch/arm/mach-at91/include/mach/hardware.h
@@ -33,6 +33,7 @@
33#include <mach/at91sam9g45.h> 33#include <mach/at91sam9g45.h>
34#include <mach/at91sam9x5.h> 34#include <mach/at91sam9x5.h>
35#include <mach/at91sam9n12.h> 35#include <mach/at91sam9n12.h>
36#include <mach/sama5d3.h>
36 37
37/* 38/*
38 * On all at91 except rm9200 and x40 have the System Controller starts 39 * On all at91 except rm9200 and x40 have the System Controller starts
diff --git a/arch/arm/mach-at91/include/mach/sama5d3.h b/arch/arm/mach-at91/include/mach/sama5d3.h
index 6dc81ee38048..31096a8aaf1d 100644
--- a/arch/arm/mach-at91/include/mach/sama5d3.h
+++ b/arch/arm/mach-at91/include/mach/sama5d3.h
@@ -65,6 +65,14 @@
65#define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */ 65#define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */
66 66
67/* 67/*
68 * User Peripheral physical base addresses.
69 */
70#define SAMA5D3_BASE_USART0 0xf001c000
71#define SAMA5D3_BASE_USART1 0xf0020000
72#define SAMA5D3_BASE_USART2 0xf8020000
73#define SAMA5D3_BASE_USART3 0xf8024000
74
75/*
68 * Internal Memory 76 * Internal Memory
69 */ 77 */
70#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */ 78#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */
diff --git a/arch/arm/mach-at91/include/mach/uncompress.h b/arch/arm/mach-at91/include/mach/uncompress.h
index 5659f7c72120..4bb644f8e87c 100644
--- a/arch/arm/mach-at91/include/mach/uncompress.h
+++ b/arch/arm/mach-at91/include/mach/uncompress.h
@@ -94,6 +94,15 @@ static const u32 uarts_sam9x5[] = {
94 0, 94 0,
95}; 95};
96 96
97static const u32 uarts_sama5[] = {
98 AT91_BASE_DBGU1,
99 SAMA5D3_BASE_USART0,
100 SAMA5D3_BASE_USART1,
101 SAMA5D3_BASE_USART2,
102 SAMA5D3_BASE_USART3,
103 0,
104};
105
97static inline const u32* decomp_soc_detect(void __iomem *dbgu_base) 106static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
98{ 107{
99 u32 cidr, socid; 108 u32 cidr, socid;
@@ -121,8 +130,12 @@ static inline const u32* decomp_soc_detect(void __iomem *dbgu_base)
121 case ARCH_ID_AT91SAM9RL64: 130 case ARCH_ID_AT91SAM9RL64:
122 return uarts_sam9rl; 131 return uarts_sam9rl;
123 132
133 case ARCH_ID_AT91SAM9N12:
124 case ARCH_ID_AT91SAM9X5: 134 case ARCH_ID_AT91SAM9X5:
125 return uarts_sam9x5; 135 return uarts_sam9x5;
136
137 case ARCH_ID_SAMA5D3:
138 return uarts_sama5;
126 } 139 }
127 140
128 /* at91sam9g10 */ 141 /* at91sam9g10 */
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 5952e68c76c4..56fe819ee10b 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -36,6 +36,7 @@ config CPU_EXYNOS4210
36 bool "SAMSUNG EXYNOS4210" 36 bool "SAMSUNG EXYNOS4210"
37 default y 37 default y
38 depends on ARCH_EXYNOS4 38 depends on ARCH_EXYNOS4
39 select ARCH_HAS_BANDGAP
39 select ARM_CPU_SUSPEND if PM 40 select ARM_CPU_SUSPEND if PM
40 select PINCTRL_EXYNOS 41 select PINCTRL_EXYNOS
41 select PM_GENERIC_DOMAINS if PM 42 select PM_GENERIC_DOMAINS if PM
@@ -49,7 +50,9 @@ config SOC_EXYNOS4212
49 bool "SAMSUNG EXYNOS4212" 50 bool "SAMSUNG EXYNOS4212"
50 default y 51 default y
51 depends on ARCH_EXYNOS4 52 depends on ARCH_EXYNOS4
53 select ARCH_HAS_BANDGAP
52 select PINCTRL_EXYNOS 54 select PINCTRL_EXYNOS
55 select PM_GENERIC_DOMAINS if PM
53 select S5P_PM if PM 56 select S5P_PM if PM
54 select S5P_SLEEP if PM 57 select S5P_SLEEP if PM
55 select SAMSUNG_DMADEV 58 select SAMSUNG_DMADEV
@@ -60,7 +63,9 @@ config SOC_EXYNOS4412
60 bool "SAMSUNG EXYNOS4412" 63 bool "SAMSUNG EXYNOS4412"
61 default y 64 default y
62 depends on ARCH_EXYNOS4 65 depends on ARCH_EXYNOS4
66 select ARCH_HAS_BANDGAP
63 select PINCTRL_EXYNOS 67 select PINCTRL_EXYNOS
68 select PM_GENERIC_DOMAINS if PM
64 select SAMSUNG_DMADEV 69 select SAMSUNG_DMADEV
65 help 70 help
66 Enable EXYNOS4412 SoC support 71 Enable EXYNOS4412 SoC support
@@ -69,6 +74,7 @@ config SOC_EXYNOS5250
69 bool "SAMSUNG EXYNOS5250" 74 bool "SAMSUNG EXYNOS5250"
70 default y 75 default y
71 depends on ARCH_EXYNOS5 76 depends on ARCH_EXYNOS5
77 select ARCH_HAS_BANDGAP
72 select PINCTRL_EXYNOS 78 select PINCTRL_EXYNOS
73 select PM_GENERIC_DOMAINS if PM 79 select PM_GENERIC_DOMAINS if PM
74 select S5P_PM if PM 80 select S5P_PM if PM
@@ -93,6 +99,7 @@ config SOC_EXYNOS5440
93 default y 99 default y
94 depends on ARCH_EXYNOS5 100 depends on ARCH_EXYNOS5
95 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE 101 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
102 select ARCH_HAS_BANDGAP
96 select ARCH_HAS_OPP 103 select ARCH_HAS_OPP
97 select HAVE_ARM_ARCH_TIMER 104 select HAVE_ARM_ARCH_TIMER
98 select AUTO_ZRELADDR 105 select AUTO_ZRELADDR
diff --git a/arch/arm/mach-exynos/cpuidle.c b/arch/arm/mach-exynos/cpuidle.c
index 225ee8431c72..ac139226d63c 100644
--- a/arch/arm/mach-exynos/cpuidle.c
+++ b/arch/arm/mach-exynos/cpuidle.c
@@ -200,6 +200,9 @@ static int __init exynos4_init_cpuidle(void)
200 if (soc_is_exynos5250()) 200 if (soc_is_exynos5250())
201 exynos5_core_down_clk(); 201 exynos5_core_down_clk();
202 202
203 if (soc_is_exynos5440())
204 exynos4_idle_driver.state_count = 1;
205
203 ret = cpuidle_register_driver(&exynos4_idle_driver); 206 ret = cpuidle_register_driver(&exynos4_idle_driver);
204 if (ret) { 207 if (ret) {
205 printk(KERN_ERR "CPUidle failed to register driver\n"); 208 printk(KERN_ERR "CPUidle failed to register driver\n");
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 6acbdabf6222..8e8437dea3ce 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -1,9 +1,14 @@
1config ARCH_HIGHBANK 1config ARCH_HIGHBANK
2 bool "Calxeda ECX-1000/2000 (Highbank/Midway)" if ARCH_MULTI_V7 2 bool "Calxeda ECX-1000/2000 (Highbank/Midway)" if ARCH_MULTI_V7
3 select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
3 select ARCH_HAS_CPUFREQ 4 select ARCH_HAS_CPUFREQ
5 select ARCH_HAS_HOLES_MEMORYMODEL
4 select ARCH_HAS_OPP 6 select ARCH_HAS_OPP
5 select ARCH_WANT_OPTIONAL_GPIOLIB 7 select ARCH_WANT_OPTIONAL_GPIOLIB
6 select ARM_AMBA 8 select ARM_AMBA
9 select ARM_ERRATA_764369
10 select ARM_ERRATA_775420
11 select ARM_ERRATA_798181
7 select ARM_GIC 12 select ARM_GIC
8 select ARM_TIMER_SP804 13 select ARM_TIMER_SP804
9 select CACHE_L2X0 14 select CACHE_L2X0
@@ -18,3 +23,4 @@ config ARCH_HIGHBANK
18 select PL320_MBOX 23 select PL320_MBOX
19 select SPARSE_IRQ 24 select SPARSE_IRQ
20 select USE_OF 25 select USE_OF
26 select ZONE_DMA if ARM_LPAE
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index 88815795fe26..8e63ccdb0de3 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -18,14 +18,11 @@
18#include <linux/clocksource.h> 18#include <linux/clocksource.h>
19#include <linux/dma-mapping.h> 19#include <linux/dma-mapping.h>
20#include <linux/io.h> 20#include <linux/io.h>
21#include <linux/irq.h>
22#include <linux/irqchip.h> 21#include <linux/irqchip.h>
23#include <linux/irqdomain.h>
24#include <linux/of.h> 22#include <linux/of.h>
25#include <linux/of_irq.h> 23#include <linux/of_irq.h>
26#include <linux/of_platform.h> 24#include <linux/of_platform.h>
27#include <linux/of_address.h> 25#include <linux/of_address.h>
28#include <linux/smp.h>
29#include <linux/amba/bus.h> 26#include <linux/amba/bus.h>
30#include <linux/clk-provider.h> 27#include <linux/clk-provider.h>
31 28
@@ -35,7 +32,6 @@
35#include <asm/hardware/cache-l2x0.h> 32#include <asm/hardware/cache-l2x0.h>
36#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
37#include <asm/mach/map.h> 34#include <asm/mach/map.h>
38#include <asm/mach/time.h>
39 35
40#include "core.h" 36#include "core.h"
41#include "sysregs.h" 37#include "sysregs.h"
@@ -65,13 +61,11 @@ void highbank_set_cpu_jump(int cpu, void *jump_addr)
65 HB_JUMP_TABLE_PHYS(cpu) + 15); 61 HB_JUMP_TABLE_PHYS(cpu) + 15);
66} 62}
67 63
68#ifdef CONFIG_CACHE_L2X0
69static void highbank_l2x0_disable(void) 64static void highbank_l2x0_disable(void)
70{ 65{
71 /* Disable PL310 L2 Cache controller */ 66 /* Disable PL310 L2 Cache controller */
72 highbank_smc1(0x102, 0x0); 67 highbank_smc1(0x102, 0x0);
73} 68}
74#endif
75 69
76static void __init highbank_init_irq(void) 70static void __init highbank_init_irq(void)
77{ 71{
@@ -80,12 +74,13 @@ static void __init highbank_init_irq(void)
80 if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9")) 74 if (of_find_compatible_node(NULL, NULL, "arm,cortex-a9"))
81 highbank_scu_map_io(); 75 highbank_scu_map_io();
82 76
83#ifdef CONFIG_CACHE_L2X0
84 /* Enable PL310 L2 Cache controller */ 77 /* Enable PL310 L2 Cache controller */
85 highbank_smc1(0x102, 0x1); 78 if (IS_ENABLED(CONFIG_CACHE_L2X0) &&
86 l2x0_of_init(0, ~0UL); 79 of_find_compatible_node(NULL, NULL, "arm,pl310-cache")) {
87 outer_cache.disable = highbank_l2x0_disable; 80 highbank_smc1(0x102, 0x1);
88#endif 81 l2x0_of_init(0, ~0UL);
82 outer_cache.disable = highbank_l2x0_disable;
83 }
89} 84}
90 85
91static void __init highbank_timer_init(void) 86static void __init highbank_timer_init(void)
@@ -176,6 +171,9 @@ static const char *highbank_match[] __initconst = {
176}; 171};
177 172
178DT_MACHINE_START(HIGHBANK, "Highbank") 173DT_MACHINE_START(HIGHBANK, "Highbank")
174#if defined(CONFIG_ZONE_DMA) && defined(CONFIG_ARM_LPAE)
175 .dma_zone_size = (4ULL * SZ_1G),
176#endif
179 .smp = smp_ops(highbank_smp_ops), 177 .smp = smp_ops(highbank_smp_ops),
180 .init_irq = highbank_init_irq, 178 .init_irq = highbank_init_irq,
181 .init_time = highbank_timer_init, 179 .init_time = highbank_timer_init,
diff --git a/arch/arm/mach-mmp/Makefile b/arch/arm/mach-mmp/Makefile
index 095c155d6fb8..9b702a1dc7b0 100644
--- a/arch/arm/mach-mmp/Makefile
+++ b/arch/arm/mach-mmp/Makefile
@@ -2,7 +2,7 @@
2# Makefile for Marvell's PXA168 processors line 2# Makefile for Marvell's PXA168 processors line
3# 3#
4 4
5obj-y += common.o devices.o time.o irq.o 5obj-y += common.o devices.o time.o
6 6
7# SoC support 7# SoC support
8obj-$(CONFIG_CPU_PXA168) += pxa168.o 8obj-$(CONFIG_CPU_PXA168) += pxa168.o
diff --git a/arch/arm/mach-mmp/common.h b/arch/arm/mach-mmp/common.h
index 991d7e9877de..cf445bae6d77 100644
--- a/arch/arm/mach-mmp/common.h
+++ b/arch/arm/mach-mmp/common.h
@@ -3,7 +3,6 @@
3 3
4extern void timer_init(int irq); 4extern void timer_init(int irq);
5 5
6extern void __init icu_init_irq(void);
7extern void __init mmp_map_io(void); 6extern void __init mmp_map_io(void);
8extern void mmp_restart(enum reboot_mode, const char *); 7extern void mmp_restart(enum reboot_mode, const char *);
9extern void __init pxa168_clk_init(void); 8extern void __init pxa168_clk_init(void);
diff --git a/arch/arm/mach-mmp/include/mach/entry-macro.S b/arch/arm/mach-mmp/include/mach/entry-macro.S
deleted file mode 100644
index bd152e24e6d7..000000000000
--- a/arch/arm/mach-mmp/include/mach/entry-macro.S
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/entry-macro.S
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#include <asm/irq.h>
10#include <mach/regs-icu.h>
11
12 .macro get_irqnr_preamble, base, tmp
13 mrc p15, 0, \tmp, c0, c0, 0 @ CPUID
14 and \tmp, \tmp, #0xff00
15 cmp \tmp, #0x5800
16 ldr \base, =mmp_icu_base
17 ldr \base, [\base, #0]
18 addne \base, \base, #0x10c @ PJ1 AP INT SEL register
19 addeq \base, \base, #0x104 @ PJ4 IRQ SEL register
20 .endm
21
22 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
23 ldr \tmp, [\base, #0]
24 and \irqnr, \tmp, #0x3f
25 tst \tmp, #(1 << 6)
26 .endm
diff --git a/arch/arm/mach-mmp/include/mach/pxa168.h b/arch/arm/mach-mmp/include/mach/pxa168.h
index 459c2d03eb5c..a83ba7cb525d 100644
--- a/arch/arm/mach-mmp/include/mach/pxa168.h
+++ b/arch/arm/mach-mmp/include/mach/pxa168.h
@@ -4,6 +4,7 @@
4#include <linux/reboot.h> 4#include <linux/reboot.h>
5 5
6extern void pxa168_timer_init(void); 6extern void pxa168_timer_init(void);
7extern void __init icu_init_irq(void);
7extern void __init pxa168_init_irq(void); 8extern void __init pxa168_init_irq(void);
8extern void pxa168_restart(enum reboot_mode, const char *); 9extern void pxa168_restart(enum reboot_mode, const char *);
9extern void pxa168_clear_keypad_wakeup(void); 10extern void pxa168_clear_keypad_wakeup(void);
diff --git a/arch/arm/mach-mmp/include/mach/pxa910.h b/arch/arm/mach-mmp/include/mach/pxa910.h
index b914afa1fcdc..92253203f5b4 100644
--- a/arch/arm/mach-mmp/include/mach/pxa910.h
+++ b/arch/arm/mach-mmp/include/mach/pxa910.h
@@ -2,6 +2,7 @@
2#define __ASM_MACH_PXA910_H 2#define __ASM_MACH_PXA910_H
3 3
4extern void pxa910_timer_init(void); 4extern void pxa910_timer_init(void);
5extern void __init icu_init_irq(void);
5extern void __init pxa910_init_irq(void); 6extern void __init pxa910_init_irq(void);
6 7
7#include <linux/i2c.h> 8#include <linux/i2c.h>
diff --git a/arch/arm/mach-mmp/mmp-dt.c b/arch/arm/mach-mmp/mmp-dt.c
index b37915dc4470..cca529ceecb7 100644
--- a/arch/arm/mach-mmp/mmp-dt.c
+++ b/arch/arm/mach-mmp/mmp-dt.c
@@ -9,17 +9,13 @@
9 * publishhed by the Free Software Foundation. 9 * publishhed by the Free Software Foundation.
10 */ 10 */
11 11
12#include <linux/irq.h> 12#include <linux/irqchip.h>
13#include <linux/irqdomain.h>
14#include <linux/of_irq.h>
15#include <linux/of_platform.h> 13#include <linux/of_platform.h>
16#include <asm/mach/arch.h> 14#include <asm/mach/arch.h>
17#include <asm/mach/time.h> 15#include <asm/mach/time.h>
18#include <mach/irqs.h>
19 16
20#include "common.h" 17#include "common.h"
21 18
22extern void __init mmp_dt_irq_init(void);
23extern void __init mmp_dt_init_timer(void); 19extern void __init mmp_dt_init_timer(void);
24 20
25static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = { 21static const struct of_dev_auxdata pxa168_auxdata_lookup[] __initconst = {
@@ -64,7 +60,6 @@ static const char *mmp_dt_board_compat[] __initdata = {
64 60
65DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)") 61DT_MACHINE_START(PXA168_DT, "Marvell PXA168 (Device Tree Support)")
66 .map_io = mmp_map_io, 62 .map_io = mmp_map_io,
67 .init_irq = mmp_dt_irq_init,
68 .init_time = mmp_dt_init_timer, 63 .init_time = mmp_dt_init_timer,
69 .init_machine = pxa168_dt_init, 64 .init_machine = pxa168_dt_init,
70 .dt_compat = mmp_dt_board_compat, 65 .dt_compat = mmp_dt_board_compat,
@@ -72,7 +67,6 @@ MACHINE_END
72 67
73DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)") 68DT_MACHINE_START(PXA910_DT, "Marvell PXA910 (Device Tree Support)")
74 .map_io = mmp_map_io, 69 .map_io = mmp_map_io,
75 .init_irq = mmp_dt_irq_init,
76 .init_time = mmp_dt_init_timer, 70 .init_time = mmp_dt_init_timer,
77 .init_machine = pxa910_dt_init, 71 .init_machine = pxa910_dt_init,
78 .dt_compat = mmp_dt_board_compat, 72 .dt_compat = mmp_dt_board_compat,
diff --git a/arch/arm/mach-mmp/mmp2-dt.c b/arch/arm/mach-mmp/mmp2-dt.c
index 4ac256720f7d..023cb453f157 100644
--- a/arch/arm/mach-mmp/mmp2-dt.c
+++ b/arch/arm/mach-mmp/mmp2-dt.c
@@ -10,18 +10,13 @@
10 */ 10 */
11 11
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/irq.h> 13#include <linux/irqchip.h>
14#include <linux/irqdomain.h>
15#include <linux/of_irq.h>
16#include <linux/of_platform.h> 14#include <linux/of_platform.h>
17#include <asm/mach/arch.h> 15#include <asm/mach/arch.h>
18#include <asm/mach/time.h> 16#include <asm/mach/time.h>
19#include <mach/irqs.h>
20#include <mach/regs-apbc.h>
21 17
22#include "common.h" 18#include "common.h"
23 19
24extern void __init mmp_dt_irq_init(void);
25extern void __init mmp_dt_init_timer(void); 20extern void __init mmp_dt_init_timer(void);
26 21
27static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = { 22static const struct of_dev_auxdata mmp2_auxdata_lookup[] __initconst = {
@@ -49,7 +44,6 @@ static const char *mmp2_dt_board_compat[] __initdata = {
49 44
50DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)") 45DT_MACHINE_START(MMP2_DT, "Marvell MMP2 (Device Tree Support)")
51 .map_io = mmp_map_io, 46 .map_io = mmp_map_io,
52 .init_irq = mmp_dt_irq_init,
53 .init_time = mmp_dt_init_timer, 47 .init_time = mmp_dt_init_timer,
54 .init_machine = mmp2_dt_init, 48 .init_machine = mmp2_dt_init,
55 .dt_compat = mmp2_dt_board_compat, 49 .dt_compat = mmp2_dt_board_compat,
diff --git a/arch/arm/mach-mmp/mmp2.c b/arch/arm/mach-mmp/mmp2.c
index c7592f168bbd..a70b5530bd42 100644
--- a/arch/arm/mach-mmp/mmp2.c
+++ b/arch/arm/mach-mmp/mmp2.c
@@ -13,6 +13,8 @@
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/io.h> 15#include <linux/io.h>
16#include <linux/irq.h>
17#include <linux/irqchip/mmp.h>
16#include <linux/platform_device.h> 18#include <linux/platform_device.h>
17 19
18#include <asm/hardware/cache-tauros2.h> 20#include <asm/hardware/cache-tauros2.h>
@@ -26,6 +28,7 @@
26#include <mach/mfp.h> 28#include <mach/mfp.h>
27#include <mach/devices.h> 29#include <mach/devices.h>
28#include <mach/mmp2.h> 30#include <mach/mmp2.h>
31#include <mach/pm-mmp2.h>
29 32
30#include "common.h" 33#include "common.h"
31 34
@@ -94,6 +97,9 @@ void mmp2_clear_pmic_int(void)
94void __init mmp2_init_irq(void) 97void __init mmp2_init_irq(void)
95{ 98{
96 mmp2_init_icu(); 99 mmp2_init_icu();
100#ifdef CONFIG_PM
101 icu_irq_chip.irq_set_wake = mmp2_set_wake;
102#endif
97} 103}
98 104
99static int __init mmp2_init(void) 105static int __init mmp2_init(void)
diff --git a/arch/arm/mach-mmp/pxa910.c b/arch/arm/mach-mmp/pxa910.c
index ce6393acad86..eb57ee196842 100644
--- a/arch/arm/mach-mmp/pxa910.c
+++ b/arch/arm/mach-mmp/pxa910.c
@@ -12,6 +12,8 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/list.h> 13#include <linux/list.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/irqchip/mmp.h>
15#include <linux/platform_device.h> 17#include <linux/platform_device.h>
16 18
17#include <asm/hardware/cache-tauros2.h> 19#include <asm/hardware/cache-tauros2.h>
@@ -23,6 +25,8 @@
23#include <mach/dma.h> 25#include <mach/dma.h>
24#include <mach/mfp.h> 26#include <mach/mfp.h>
25#include <mach/devices.h> 27#include <mach/devices.h>
28#include <mach/pm-pxa910.h>
29#include <mach/pxa910.h>
26 30
27#include "common.h" 31#include "common.h"
28 32
@@ -79,6 +83,9 @@ static struct mfp_addr_map pxa910_mfp_addr_map[] __initdata =
79void __init pxa910_init_irq(void) 83void __init pxa910_init_irq(void)
80{ 84{
81 icu_init_irq(); 85 icu_init_irq();
86#ifdef CONFIG_PM
87 icu_irq_chip.irq_set_wake = pxa910_set_wake;
88#endif
82} 89}
83 90
84static int __init pxa910_init(void) 91static int __init pxa910_init(void)
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index cc36bfe104fe..afb457c3135b 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -63,6 +63,7 @@ obj-$(CONFIG_SOC_AM33XX) += am33xx-restart.o
63obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o 63obj-$(CONFIG_ARCH_OMAP3) += omap3-restart.o
64obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o 64obj-$(CONFIG_ARCH_OMAP4) += omap4-restart.o
65obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o 65obj-$(CONFIG_SOC_OMAP5) += omap4-restart.o
66obj-$(CONFIG_SOC_DRA7XX) += omap4-restart.o
66 67
67# Pin multiplexing 68# Pin multiplexing
68obj-$(CONFIG_SOC_OMAP2420) += mux2420.o 69obj-$(CONFIG_SOC_OMAP2420) += mux2420.o
@@ -148,6 +149,7 @@ obj-$(CONFIG_SOC_AM43XX) += $(powerdomain-common)
148obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common) 149obj-$(CONFIG_SOC_OMAP5) += $(powerdomain-common)
149obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o 150obj-$(CONFIG_SOC_OMAP5) += powerdomains54xx_data.o
150obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common) 151obj-$(CONFIG_SOC_DRA7XX) += $(powerdomain-common)
152obj-$(CONFIG_SOC_DRA7XX) += powerdomains7xx_data.o
151 153
152# PRCM clockdomain control 154# PRCM clockdomain control
153clockdomain-common += clockdomain.o 155clockdomain-common += clockdomain.o
@@ -166,6 +168,7 @@ obj-$(CONFIG_SOC_AM43XX) += $(clockdomain-common)
166obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common) 168obj-$(CONFIG_SOC_OMAP5) += $(clockdomain-common)
167obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o 169obj-$(CONFIG_SOC_OMAP5) += clockdomains54xx_data.o
168obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common) 170obj-$(CONFIG_SOC_DRA7XX) += $(clockdomain-common)
171obj-$(CONFIG_SOC_DRA7XX) += clockdomains7xx_data.o
169 172
170# Clock framework 173# Clock framework
171obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o 174obj-$(CONFIG_ARCH_OMAP2) += $(clock-common) clock2xxx.o
@@ -209,6 +212,7 @@ obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
209obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o 212obj-$(CONFIG_SOC_AM33XX) += omap_hwmod_33xx_data.o
210obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o 213obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
211obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o 214obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
215obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
212 216
213# EMU peripherals 217# EMU peripherals
214obj-$(CONFIG_OMAP3_EMU) += emu.o 218obj-$(CONFIG_OMAP3_EMU) += emu.o
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index b89e55ba2c13..39c78387ddec 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -238,5 +238,6 @@ DT_MACHINE_START(DRA7XX_DT, "Generic DRA7XX (Flattened Device Tree)")
238 .init_machine = omap_generic_init, 238 .init_machine = omap_generic_init,
239 .init_time = omap5_realtime_timer_init, 239 .init_time = omap5_realtime_timer_init,
240 .dt_compat = dra7xx_boards_compat, 240 .dt_compat = dra7xx_boards_compat,
241 .restart = omap44xx_restart,
241MACHINE_END 242MACHINE_END
242#endif 243#endif
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index ba6534d7f155..865d30ee812f 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -421,6 +421,10 @@ static struct clk aes0_fck;
421DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL); 421DEFINE_STRUCT_CLK_HW_OMAP(aes0_fck, NULL);
422DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null); 422DEFINE_STRUCT_CLK(aes0_fck, dpll_core_ck_parents, clk_ops_null);
423 423
424static struct clk rng_fck;
425DEFINE_STRUCT_CLK_HW_OMAP(rng_fck, NULL);
426DEFINE_STRUCT_CLK(rng_fck, dpll_core_ck_parents, clk_ops_null);
427
424/* 428/*
425 * Modules clock nodes 429 * Modules clock nodes
426 * 430 *
@@ -966,6 +970,7 @@ static struct omap_clk am33xx_clks[] = {
966 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck), 970 CLK(NULL, "smartreflex1_fck", &smartreflex1_fck),
967 CLK(NULL, "sha0_fck", &sha0_fck), 971 CLK(NULL, "sha0_fck", &sha0_fck),
968 CLK(NULL, "aes0_fck", &aes0_fck), 972 CLK(NULL, "aes0_fck", &aes0_fck),
973 CLK(NULL, "rng_fck", &rng_fck),
969 CLK(NULL, "timer1_fck", &timer1_fck), 974 CLK(NULL, "timer1_fck", &timer1_fck),
970 CLK(NULL, "timer2_fck", &timer2_fck), 975 CLK(NULL, "timer2_fck", &timer2_fck),
971 CLK(NULL, "timer3_fck", &timer3_fck), 976 CLK(NULL, "timer3_fck", &timer3_fck),
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 88e37a474334..1d5b5290d2af 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -1707,6 +1707,18 @@ int __init omap4xxx_clk_init(void)
1707 omap2_clk_disable_autoidle_all(); 1707 omap2_clk_disable_autoidle_all();
1708 1708
1709 /* 1709 /*
1710 * A set rate of ABE DPLL inturn triggers a set rate of USB DPLL
1711 * when its in bypass. So always lock USB before ABE DPLL.
1712 */
1713 /*
1714 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
1715 * domain can transition to retention state when not in use.
1716 */
1717 rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
1718 if (rc)
1719 pr_err("%s: failed to configure USB DPLL!\n", __func__);
1720
1721 /*
1710 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power 1722 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
1711 * state when turning the ABE clock domain. Workaround this by 1723 * state when turning the ABE clock domain. Workaround this by
1712 * locking the ABE DPLL on boot. 1724 * locking the ABE DPLL on boot.
@@ -1718,13 +1730,5 @@ int __init omap4xxx_clk_init(void)
1718 if (rc) 1730 if (rc)
1719 pr_err("%s: failed to configure ABE DPLL!\n", __func__); 1731 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
1720 1732
1721 /*
1722 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
1723 * domain can transition to retention state when not in use.
1724 */
1725 rc = clk_set_rate(&dpll_usb_ck, OMAP4_DPLL_USB_DEFFREQ);
1726 if (rc)
1727 pr_err("%s: failed to configure USB DPLL!\n", __func__);
1728
1729 return 0; 1733 return 0;
1730} 1734}
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index daeecf1b89fa..4b03394fa0c5 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -217,6 +217,7 @@ extern void __init omap3xxx_clockdomains_init(void);
217extern void __init am33xx_clockdomains_init(void); 217extern void __init am33xx_clockdomains_init(void);
218extern void __init omap44xx_clockdomains_init(void); 218extern void __init omap44xx_clockdomains_init(void);
219extern void __init omap54xx_clockdomains_init(void); 219extern void __init omap54xx_clockdomains_init(void);
220extern void __init dra7xx_clockdomains_init(void);
220 221
221extern void clkdm_add_autodeps(struct clockdomain *clkdm); 222extern void clkdm_add_autodeps(struct clockdomain *clkdm);
222extern void clkdm_del_autodeps(struct clockdomain *clkdm); 223extern void clkdm_del_autodeps(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c b/arch/arm/mach-omap2/clockdomains7xx_data.c
new file mode 100644
index 000000000000..57d5df0c1fbd
--- /dev/null
+++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
@@ -0,0 +1,740 @@
1/*
2 * DRA7xx Clock domains framework
3 *
4 * Copyright (C) 2009-2013 Texas Instruments, Inc.
5 * Copyright (C) 2009-2011 Nokia Corporation
6 *
7 * Generated by code originally written by:
8 * Abhijit Pagare (abhijitpagare@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 * Paul Walmsley (paul@pwsan.com)
11 *
12 * This file is automatically generated from the OMAP hardware databases.
13 * We respectfully ask that any modifications to this file be coordinated
14 * with the public linux-omap@vger.kernel.org mailing list and the
15 * authors above to ensure that the autogeneration scripts are kept
16 * up-to-date with the file contents.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/kernel.h>
24#include <linux/io.h>
25
26#include "clockdomain.h"
27#include "cm1_7xx.h"
28#include "cm2_7xx.h"
29
30#include "cm-regbits-7xx.h"
31#include "prm7xx.h"
32#include "prcm44xx.h"
33#include "prcm_mpu7xx.h"
34
35/* Static Dependencies for DRA7xx Clock Domains */
36
37static struct clkdm_dep cam_wkup_sleep_deps[] = {
38 { .clkdm_name = "emif_clkdm" },
39 { NULL },
40};
41
42static struct clkdm_dep dma_wkup_sleep_deps[] = {
43 { .clkdm_name = "dss_clkdm" },
44 { .clkdm_name = "emif_clkdm" },
45 { .clkdm_name = "ipu_clkdm" },
46 { .clkdm_name = "ipu1_clkdm" },
47 { .clkdm_name = "ipu2_clkdm" },
48 { .clkdm_name = "iva_clkdm" },
49 { .clkdm_name = "l3init_clkdm" },
50 { .clkdm_name = "l4cfg_clkdm" },
51 { .clkdm_name = "l4per_clkdm" },
52 { .clkdm_name = "l4per2_clkdm" },
53 { .clkdm_name = "l4per3_clkdm" },
54 { .clkdm_name = "l4sec_clkdm" },
55 { .clkdm_name = "pcie_clkdm" },
56 { .clkdm_name = "wkupaon_clkdm" },
57 { NULL },
58};
59
60static struct clkdm_dep dsp1_wkup_sleep_deps[] = {
61 { .clkdm_name = "atl_clkdm" },
62 { .clkdm_name = "cam_clkdm" },
63 { .clkdm_name = "dsp2_clkdm" },
64 { .clkdm_name = "dss_clkdm" },
65 { .clkdm_name = "emif_clkdm" },
66 { .clkdm_name = "eve1_clkdm" },
67 { .clkdm_name = "eve2_clkdm" },
68 { .clkdm_name = "eve3_clkdm" },
69 { .clkdm_name = "eve4_clkdm" },
70 { .clkdm_name = "gmac_clkdm" },
71 { .clkdm_name = "gpu_clkdm" },
72 { .clkdm_name = "ipu_clkdm" },
73 { .clkdm_name = "ipu1_clkdm" },
74 { .clkdm_name = "ipu2_clkdm" },
75 { .clkdm_name = "iva_clkdm" },
76 { .clkdm_name = "l3init_clkdm" },
77 { .clkdm_name = "l4per_clkdm" },
78 { .clkdm_name = "l4per2_clkdm" },
79 { .clkdm_name = "l4per3_clkdm" },
80 { .clkdm_name = "l4sec_clkdm" },
81 { .clkdm_name = "pcie_clkdm" },
82 { .clkdm_name = "vpe_clkdm" },
83 { .clkdm_name = "wkupaon_clkdm" },
84 { NULL },
85};
86
87static struct clkdm_dep dsp2_wkup_sleep_deps[] = {
88 { .clkdm_name = "atl_clkdm" },
89 { .clkdm_name = "cam_clkdm" },
90 { .clkdm_name = "dsp1_clkdm" },
91 { .clkdm_name = "dss_clkdm" },
92 { .clkdm_name = "emif_clkdm" },
93 { .clkdm_name = "eve1_clkdm" },
94 { .clkdm_name = "eve2_clkdm" },
95 { .clkdm_name = "eve3_clkdm" },
96 { .clkdm_name = "eve4_clkdm" },
97 { .clkdm_name = "gmac_clkdm" },
98 { .clkdm_name = "gpu_clkdm" },
99 { .clkdm_name = "ipu_clkdm" },
100 { .clkdm_name = "ipu1_clkdm" },
101 { .clkdm_name = "ipu2_clkdm" },
102 { .clkdm_name = "iva_clkdm" },
103 { .clkdm_name = "l3init_clkdm" },
104 { .clkdm_name = "l4per_clkdm" },
105 { .clkdm_name = "l4per2_clkdm" },
106 { .clkdm_name = "l4per3_clkdm" },
107 { .clkdm_name = "l4sec_clkdm" },
108 { .clkdm_name = "pcie_clkdm" },
109 { .clkdm_name = "vpe_clkdm" },
110 { .clkdm_name = "wkupaon_clkdm" },
111 { NULL },
112};
113
114static struct clkdm_dep dss_wkup_sleep_deps[] = {
115 { .clkdm_name = "emif_clkdm" },
116 { .clkdm_name = "iva_clkdm" },
117 { NULL },
118};
119
120static struct clkdm_dep eve1_wkup_sleep_deps[] = {
121 { .clkdm_name = "emif_clkdm" },
122 { .clkdm_name = "eve2_clkdm" },
123 { .clkdm_name = "eve3_clkdm" },
124 { .clkdm_name = "eve4_clkdm" },
125 { .clkdm_name = "iva_clkdm" },
126 { NULL },
127};
128
129static struct clkdm_dep eve2_wkup_sleep_deps[] = {
130 { .clkdm_name = "emif_clkdm" },
131 { .clkdm_name = "eve1_clkdm" },
132 { .clkdm_name = "eve3_clkdm" },
133 { .clkdm_name = "eve4_clkdm" },
134 { .clkdm_name = "iva_clkdm" },
135 { NULL },
136};
137
138static struct clkdm_dep eve3_wkup_sleep_deps[] = {
139 { .clkdm_name = "emif_clkdm" },
140 { .clkdm_name = "eve1_clkdm" },
141 { .clkdm_name = "eve2_clkdm" },
142 { .clkdm_name = "eve4_clkdm" },
143 { .clkdm_name = "iva_clkdm" },
144 { NULL },
145};
146
147static struct clkdm_dep eve4_wkup_sleep_deps[] = {
148 { .clkdm_name = "emif_clkdm" },
149 { .clkdm_name = "eve1_clkdm" },
150 { .clkdm_name = "eve2_clkdm" },
151 { .clkdm_name = "eve3_clkdm" },
152 { .clkdm_name = "iva_clkdm" },
153 { NULL },
154};
155
156static struct clkdm_dep gmac_wkup_sleep_deps[] = {
157 { .clkdm_name = "emif_clkdm" },
158 { .clkdm_name = "l4per2_clkdm" },
159 { NULL },
160};
161
162static struct clkdm_dep gpu_wkup_sleep_deps[] = {
163 { .clkdm_name = "emif_clkdm" },
164 { .clkdm_name = "iva_clkdm" },
165 { NULL },
166};
167
168static struct clkdm_dep ipu1_wkup_sleep_deps[] = {
169 { .clkdm_name = "atl_clkdm" },
170 { .clkdm_name = "dsp1_clkdm" },
171 { .clkdm_name = "dsp2_clkdm" },
172 { .clkdm_name = "dss_clkdm" },
173 { .clkdm_name = "emif_clkdm" },
174 { .clkdm_name = "eve1_clkdm" },
175 { .clkdm_name = "eve2_clkdm" },
176 { .clkdm_name = "eve3_clkdm" },
177 { .clkdm_name = "eve4_clkdm" },
178 { .clkdm_name = "gmac_clkdm" },
179 { .clkdm_name = "gpu_clkdm" },
180 { .clkdm_name = "ipu_clkdm" },
181 { .clkdm_name = "ipu2_clkdm" },
182 { .clkdm_name = "iva_clkdm" },
183 { .clkdm_name = "l3init_clkdm" },
184 { .clkdm_name = "l3main1_clkdm" },
185 { .clkdm_name = "l4cfg_clkdm" },
186 { .clkdm_name = "l4per_clkdm" },
187 { .clkdm_name = "l4per2_clkdm" },
188 { .clkdm_name = "l4per3_clkdm" },
189 { .clkdm_name = "l4sec_clkdm" },
190 { .clkdm_name = "pcie_clkdm" },
191 { .clkdm_name = "vpe_clkdm" },
192 { .clkdm_name = "wkupaon_clkdm" },
193 { NULL },
194};
195
196static struct clkdm_dep ipu2_wkup_sleep_deps[] = {
197 { .clkdm_name = "atl_clkdm" },
198 { .clkdm_name = "dsp1_clkdm" },
199 { .clkdm_name = "dsp2_clkdm" },
200 { .clkdm_name = "dss_clkdm" },
201 { .clkdm_name = "emif_clkdm" },
202 { .clkdm_name = "eve1_clkdm" },
203 { .clkdm_name = "eve2_clkdm" },
204 { .clkdm_name = "eve3_clkdm" },
205 { .clkdm_name = "eve4_clkdm" },
206 { .clkdm_name = "gmac_clkdm" },
207 { .clkdm_name = "gpu_clkdm" },
208 { .clkdm_name = "ipu_clkdm" },
209 { .clkdm_name = "ipu1_clkdm" },
210 { .clkdm_name = "iva_clkdm" },
211 { .clkdm_name = "l3init_clkdm" },
212 { .clkdm_name = "l3main1_clkdm" },
213 { .clkdm_name = "l4cfg_clkdm" },
214 { .clkdm_name = "l4per_clkdm" },
215 { .clkdm_name = "l4per2_clkdm" },
216 { .clkdm_name = "l4per3_clkdm" },
217 { .clkdm_name = "l4sec_clkdm" },
218 { .clkdm_name = "pcie_clkdm" },
219 { .clkdm_name = "vpe_clkdm" },
220 { .clkdm_name = "wkupaon_clkdm" },
221 { NULL },
222};
223
224static struct clkdm_dep iva_wkup_sleep_deps[] = {
225 { .clkdm_name = "emif_clkdm" },
226 { NULL },
227};
228
229static struct clkdm_dep l3init_wkup_sleep_deps[] = {
230 { .clkdm_name = "emif_clkdm" },
231 { .clkdm_name = "iva_clkdm" },
232 { .clkdm_name = "l4cfg_clkdm" },
233 { .clkdm_name = "l4per_clkdm" },
234 { .clkdm_name = "l4per3_clkdm" },
235 { .clkdm_name = "l4sec_clkdm" },
236 { .clkdm_name = "wkupaon_clkdm" },
237 { NULL },
238};
239
240static struct clkdm_dep l4per2_wkup_sleep_deps[] = {
241 { .clkdm_name = "dsp1_clkdm" },
242 { .clkdm_name = "dsp2_clkdm" },
243 { .clkdm_name = "ipu1_clkdm" },
244 { .clkdm_name = "ipu2_clkdm" },
245 { NULL },
246};
247
248static struct clkdm_dep l4sec_wkup_sleep_deps[] = {
249 { .clkdm_name = "emif_clkdm" },
250 { .clkdm_name = "l4per_clkdm" },
251 { NULL },
252};
253
254static struct clkdm_dep mpu_wkup_sleep_deps[] = {
255 { .clkdm_name = "cam_clkdm" },
256 { .clkdm_name = "dsp1_clkdm" },
257 { .clkdm_name = "dsp2_clkdm" },
258 { .clkdm_name = "dss_clkdm" },
259 { .clkdm_name = "emif_clkdm" },
260 { .clkdm_name = "eve1_clkdm" },
261 { .clkdm_name = "eve2_clkdm" },
262 { .clkdm_name = "eve3_clkdm" },
263 { .clkdm_name = "eve4_clkdm" },
264 { .clkdm_name = "gmac_clkdm" },
265 { .clkdm_name = "gpu_clkdm" },
266 { .clkdm_name = "ipu_clkdm" },
267 { .clkdm_name = "ipu1_clkdm" },
268 { .clkdm_name = "ipu2_clkdm" },
269 { .clkdm_name = "iva_clkdm" },
270 { .clkdm_name = "l3init_clkdm" },
271 { .clkdm_name = "l3main1_clkdm" },
272 { .clkdm_name = "l4cfg_clkdm" },
273 { .clkdm_name = "l4per_clkdm" },
274 { .clkdm_name = "l4per2_clkdm" },
275 { .clkdm_name = "l4per3_clkdm" },
276 { .clkdm_name = "l4sec_clkdm" },
277 { .clkdm_name = "pcie_clkdm" },
278 { .clkdm_name = "vpe_clkdm" },
279 { .clkdm_name = "wkupaon_clkdm" },
280 { NULL },
281};
282
283static struct clkdm_dep pcie_wkup_sleep_deps[] = {
284 { .clkdm_name = "atl_clkdm" },
285 { .clkdm_name = "cam_clkdm" },
286 { .clkdm_name = "dsp1_clkdm" },
287 { .clkdm_name = "dsp2_clkdm" },
288 { .clkdm_name = "dss_clkdm" },
289 { .clkdm_name = "emif_clkdm" },
290 { .clkdm_name = "eve1_clkdm" },
291 { .clkdm_name = "eve2_clkdm" },
292 { .clkdm_name = "eve3_clkdm" },
293 { .clkdm_name = "eve4_clkdm" },
294 { .clkdm_name = "gmac_clkdm" },
295 { .clkdm_name = "gpu_clkdm" },
296 { .clkdm_name = "ipu_clkdm" },
297 { .clkdm_name = "ipu1_clkdm" },
298 { .clkdm_name = "iva_clkdm" },
299 { .clkdm_name = "l3init_clkdm" },
300 { .clkdm_name = "l4cfg_clkdm" },
301 { .clkdm_name = "l4per_clkdm" },
302 { .clkdm_name = "l4per2_clkdm" },
303 { .clkdm_name = "l4per3_clkdm" },
304 { .clkdm_name = "l4sec_clkdm" },
305 { .clkdm_name = "vpe_clkdm" },
306 { NULL },
307};
308
309static struct clkdm_dep vpe_wkup_sleep_deps[] = {
310 { .clkdm_name = "emif_clkdm" },
311 { .clkdm_name = "l4per3_clkdm" },
312 { NULL },
313};
314
315static struct clockdomain l4per3_7xx_clkdm = {
316 .name = "l4per3_clkdm",
317 .pwrdm = { .name = "l4per_pwrdm" },
318 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
319 .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
320 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS,
321 .dep_bit = DRA7XX_L4PER3_STATDEP_SHIFT,
322 .flags = CLKDM_CAN_HWSUP_SWSUP,
323};
324
325static struct clockdomain l4per2_7xx_clkdm = {
326 .name = "l4per2_clkdm",
327 .pwrdm = { .name = "l4per_pwrdm" },
328 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
329 .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
330 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS,
331 .dep_bit = DRA7XX_L4PER2_STATDEP_SHIFT,
332 .wkdep_srcs = l4per2_wkup_sleep_deps,
333 .sleepdep_srcs = l4per2_wkup_sleep_deps,
334 .flags = CLKDM_CAN_HWSUP_SWSUP,
335};
336
337static struct clockdomain mpu0_7xx_clkdm = {
338 .name = "mpu0_clkdm",
339 .pwrdm = { .name = "cpu0_pwrdm" },
340 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
341 .cm_inst = DRA7XX_MPU_PRCM_CM_C0_INST,
342 .clkdm_offs = DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS,
343 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
344};
345
346static struct clockdomain iva_7xx_clkdm = {
347 .name = "iva_clkdm",
348 .pwrdm = { .name = "iva_pwrdm" },
349 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
350 .cm_inst = DRA7XX_CM_CORE_IVA_INST,
351 .clkdm_offs = DRA7XX_CM_CORE_IVA_IVA_CDOFFS,
352 .dep_bit = DRA7XX_IVA_STATDEP_SHIFT,
353 .wkdep_srcs = iva_wkup_sleep_deps,
354 .sleepdep_srcs = iva_wkup_sleep_deps,
355 .flags = CLKDM_CAN_HWSUP_SWSUP,
356};
357
358static struct clockdomain coreaon_7xx_clkdm = {
359 .name = "coreaon_clkdm",
360 .pwrdm = { .name = "coreaon_pwrdm" },
361 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
362 .cm_inst = DRA7XX_CM_CORE_COREAON_INST,
363 .clkdm_offs = DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS,
364 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
365};
366
367static struct clockdomain ipu1_7xx_clkdm = {
368 .name = "ipu1_clkdm",
369 .pwrdm = { .name = "ipu_pwrdm" },
370 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
371 .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
372 .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS,
373 .dep_bit = DRA7XX_IPU1_STATDEP_SHIFT,
374 .wkdep_srcs = ipu1_wkup_sleep_deps,
375 .sleepdep_srcs = ipu1_wkup_sleep_deps,
376 .flags = CLKDM_CAN_HWSUP_SWSUP,
377};
378
379static struct clockdomain ipu2_7xx_clkdm = {
380 .name = "ipu2_clkdm",
381 .pwrdm = { .name = "core_pwrdm" },
382 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
383 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
384 .clkdm_offs = DRA7XX_CM_CORE_CORE_IPU2_CDOFFS,
385 .dep_bit = DRA7XX_IPU2_STATDEP_SHIFT,
386 .wkdep_srcs = ipu2_wkup_sleep_deps,
387 .sleepdep_srcs = ipu2_wkup_sleep_deps,
388 .flags = CLKDM_CAN_HWSUP_SWSUP,
389};
390
391static struct clockdomain l3init_7xx_clkdm = {
392 .name = "l3init_clkdm",
393 .pwrdm = { .name = "l3init_pwrdm" },
394 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
395 .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
396 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS,
397 .dep_bit = DRA7XX_L3INIT_STATDEP_SHIFT,
398 .wkdep_srcs = l3init_wkup_sleep_deps,
399 .sleepdep_srcs = l3init_wkup_sleep_deps,
400 .flags = CLKDM_CAN_HWSUP_SWSUP,
401};
402
403static struct clockdomain l4sec_7xx_clkdm = {
404 .name = "l4sec_clkdm",
405 .pwrdm = { .name = "l4per_pwrdm" },
406 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
407 .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
408 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS,
409 .dep_bit = DRA7XX_L4SEC_STATDEP_SHIFT,
410 .wkdep_srcs = l4sec_wkup_sleep_deps,
411 .sleepdep_srcs = l4sec_wkup_sleep_deps,
412 .flags = CLKDM_CAN_HWSUP_SWSUP,
413};
414
415static struct clockdomain l3main1_7xx_clkdm = {
416 .name = "l3main1_clkdm",
417 .pwrdm = { .name = "core_pwrdm" },
418 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
419 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
420 .clkdm_offs = DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS,
421 .dep_bit = DRA7XX_L3MAIN1_STATDEP_SHIFT,
422 .flags = CLKDM_CAN_HWSUP,
423};
424
425static struct clockdomain vpe_7xx_clkdm = {
426 .name = "vpe_clkdm",
427 .pwrdm = { .name = "vpe_pwrdm" },
428 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
429 .cm_inst = DRA7XX_CM_CORE_AON_VPE_INST,
430 .clkdm_offs = DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS,
431 .dep_bit = DRA7XX_VPE_STATDEP_SHIFT,
432 .wkdep_srcs = vpe_wkup_sleep_deps,
433 .sleepdep_srcs = vpe_wkup_sleep_deps,
434 .flags = CLKDM_CAN_HWSUP_SWSUP,
435};
436
437static struct clockdomain mpu_7xx_clkdm = {
438 .name = "mpu_clkdm",
439 .pwrdm = { .name = "mpu_pwrdm" },
440 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
441 .cm_inst = DRA7XX_CM_CORE_AON_MPU_INST,
442 .clkdm_offs = DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS,
443 .wkdep_srcs = mpu_wkup_sleep_deps,
444 .sleepdep_srcs = mpu_wkup_sleep_deps,
445 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
446};
447
448static struct clockdomain custefuse_7xx_clkdm = {
449 .name = "custefuse_clkdm",
450 .pwrdm = { .name = "custefuse_pwrdm" },
451 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
452 .cm_inst = DRA7XX_CM_CORE_CUSTEFUSE_INST,
453 .clkdm_offs = DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS,
454 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
455};
456
457static struct clockdomain ipu_7xx_clkdm = {
458 .name = "ipu_clkdm",
459 .pwrdm = { .name = "ipu_pwrdm" },
460 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
461 .cm_inst = DRA7XX_CM_CORE_AON_IPU_INST,
462 .clkdm_offs = DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS,
463 .dep_bit = DRA7XX_IPU_STATDEP_SHIFT,
464 .flags = CLKDM_CAN_HWSUP_SWSUP,
465};
466
467static struct clockdomain mpu1_7xx_clkdm = {
468 .name = "mpu1_clkdm",
469 .pwrdm = { .name = "cpu1_pwrdm" },
470 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
471 .cm_inst = DRA7XX_MPU_PRCM_CM_C1_INST,
472 .clkdm_offs = DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS,
473 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
474};
475
476static struct clockdomain gmac_7xx_clkdm = {
477 .name = "gmac_clkdm",
478 .pwrdm = { .name = "l3init_pwrdm" },
479 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
480 .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
481 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS,
482 .dep_bit = DRA7XX_GMAC_STATDEP_SHIFT,
483 .wkdep_srcs = gmac_wkup_sleep_deps,
484 .sleepdep_srcs = gmac_wkup_sleep_deps,
485 .flags = CLKDM_CAN_HWSUP_SWSUP,
486};
487
488static struct clockdomain l4cfg_7xx_clkdm = {
489 .name = "l4cfg_clkdm",
490 .pwrdm = { .name = "core_pwrdm" },
491 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
492 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
493 .clkdm_offs = DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS,
494 .dep_bit = DRA7XX_L4CFG_STATDEP_SHIFT,
495 .flags = CLKDM_CAN_HWSUP,
496};
497
498static struct clockdomain dma_7xx_clkdm = {
499 .name = "dma_clkdm",
500 .pwrdm = { .name = "core_pwrdm" },
501 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
502 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
503 .clkdm_offs = DRA7XX_CM_CORE_CORE_DMA_CDOFFS,
504 .wkdep_srcs = dma_wkup_sleep_deps,
505 .sleepdep_srcs = dma_wkup_sleep_deps,
506 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
507};
508
509static struct clockdomain rtc_7xx_clkdm = {
510 .name = "rtc_clkdm",
511 .pwrdm = { .name = "rtc_pwrdm" },
512 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
513 .cm_inst = DRA7XX_CM_CORE_AON_RTC_INST,
514 .clkdm_offs = DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS,
515 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
516};
517
518static struct clockdomain pcie_7xx_clkdm = {
519 .name = "pcie_clkdm",
520 .pwrdm = { .name = "l3init_pwrdm" },
521 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
522 .cm_inst = DRA7XX_CM_CORE_L3INIT_INST,
523 .clkdm_offs = DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS,
524 .dep_bit = DRA7XX_PCIE_STATDEP_SHIFT,
525 .wkdep_srcs = pcie_wkup_sleep_deps,
526 .sleepdep_srcs = pcie_wkup_sleep_deps,
527 .flags = CLKDM_CAN_HWSUP_SWSUP,
528};
529
530static struct clockdomain atl_7xx_clkdm = {
531 .name = "atl_clkdm",
532 .pwrdm = { .name = "core_pwrdm" },
533 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
534 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
535 .clkdm_offs = DRA7XX_CM_CORE_CORE_ATL_CDOFFS,
536 .dep_bit = DRA7XX_ATL_STATDEP_SHIFT,
537 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
538};
539
540static struct clockdomain l3instr_7xx_clkdm = {
541 .name = "l3instr_clkdm",
542 .pwrdm = { .name = "core_pwrdm" },
543 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
544 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
545 .clkdm_offs = DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS,
546};
547
548static struct clockdomain dss_7xx_clkdm = {
549 .name = "dss_clkdm",
550 .pwrdm = { .name = "dss_pwrdm" },
551 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
552 .cm_inst = DRA7XX_CM_CORE_DSS_INST,
553 .clkdm_offs = DRA7XX_CM_CORE_DSS_DSS_CDOFFS,
554 .dep_bit = DRA7XX_DSS_STATDEP_SHIFT,
555 .wkdep_srcs = dss_wkup_sleep_deps,
556 .sleepdep_srcs = dss_wkup_sleep_deps,
557 .flags = CLKDM_CAN_HWSUP_SWSUP,
558};
559
560static struct clockdomain emif_7xx_clkdm = {
561 .name = "emif_clkdm",
562 .pwrdm = { .name = "core_pwrdm" },
563 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
564 .cm_inst = DRA7XX_CM_CORE_CORE_INST,
565 .clkdm_offs = DRA7XX_CM_CORE_CORE_EMIF_CDOFFS,
566 .dep_bit = DRA7XX_EMIF_STATDEP_SHIFT,
567 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
568};
569
570static struct clockdomain emu_7xx_clkdm = {
571 .name = "emu_clkdm",
572 .pwrdm = { .name = "emu_pwrdm" },
573 .prcm_partition = DRA7XX_PRM_PARTITION,
574 .cm_inst = DRA7XX_PRM_EMU_CM_INST,
575 .clkdm_offs = DRA7XX_PRM_EMU_CM_EMU_CDOFFS,
576 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
577};
578
579static struct clockdomain dsp2_7xx_clkdm = {
580 .name = "dsp2_clkdm",
581 .pwrdm = { .name = "dsp2_pwrdm" },
582 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
583 .cm_inst = DRA7XX_CM_CORE_AON_DSP2_INST,
584 .clkdm_offs = DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS,
585 .dep_bit = DRA7XX_DSP2_STATDEP_SHIFT,
586 .wkdep_srcs = dsp2_wkup_sleep_deps,
587 .sleepdep_srcs = dsp2_wkup_sleep_deps,
588 .flags = CLKDM_CAN_HWSUP_SWSUP,
589};
590
591static struct clockdomain dsp1_7xx_clkdm = {
592 .name = "dsp1_clkdm",
593 .pwrdm = { .name = "dsp1_pwrdm" },
594 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
595 .cm_inst = DRA7XX_CM_CORE_AON_DSP1_INST,
596 .clkdm_offs = DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS,
597 .dep_bit = DRA7XX_DSP1_STATDEP_SHIFT,
598 .wkdep_srcs = dsp1_wkup_sleep_deps,
599 .sleepdep_srcs = dsp1_wkup_sleep_deps,
600 .flags = CLKDM_CAN_HWSUP_SWSUP,
601};
602
603static struct clockdomain cam_7xx_clkdm = {
604 .name = "cam_clkdm",
605 .pwrdm = { .name = "cam_pwrdm" },
606 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
607 .cm_inst = DRA7XX_CM_CORE_CAM_INST,
608 .clkdm_offs = DRA7XX_CM_CORE_CAM_CAM_CDOFFS,
609 .dep_bit = DRA7XX_CAM_STATDEP_SHIFT,
610 .wkdep_srcs = cam_wkup_sleep_deps,
611 .sleepdep_srcs = cam_wkup_sleep_deps,
612 .flags = CLKDM_CAN_HWSUP_SWSUP,
613};
614
615static struct clockdomain l4per_7xx_clkdm = {
616 .name = "l4per_clkdm",
617 .pwrdm = { .name = "l4per_pwrdm" },
618 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
619 .cm_inst = DRA7XX_CM_CORE_L4PER_INST,
620 .clkdm_offs = DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS,
621 .dep_bit = DRA7XX_L4PER_STATDEP_SHIFT,
622 .flags = CLKDM_CAN_HWSUP_SWSUP,
623};
624
625static struct clockdomain gpu_7xx_clkdm = {
626 .name = "gpu_clkdm",
627 .pwrdm = { .name = "gpu_pwrdm" },
628 .prcm_partition = DRA7XX_CM_CORE_PARTITION,
629 .cm_inst = DRA7XX_CM_CORE_GPU_INST,
630 .clkdm_offs = DRA7XX_CM_CORE_GPU_GPU_CDOFFS,
631 .dep_bit = DRA7XX_GPU_STATDEP_SHIFT,
632 .wkdep_srcs = gpu_wkup_sleep_deps,
633 .sleepdep_srcs = gpu_wkup_sleep_deps,
634 .flags = CLKDM_CAN_HWSUP_SWSUP,
635};
636
637static struct clockdomain eve4_7xx_clkdm = {
638 .name = "eve4_clkdm",
639 .pwrdm = { .name = "eve4_pwrdm" },
640 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
641 .cm_inst = DRA7XX_CM_CORE_AON_EVE4_INST,
642 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS,
643 .dep_bit = DRA7XX_EVE4_STATDEP_SHIFT,
644 .wkdep_srcs = eve4_wkup_sleep_deps,
645 .sleepdep_srcs = eve4_wkup_sleep_deps,
646 .flags = CLKDM_CAN_HWSUP_SWSUP,
647};
648
649static struct clockdomain eve2_7xx_clkdm = {
650 .name = "eve2_clkdm",
651 .pwrdm = { .name = "eve2_pwrdm" },
652 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
653 .cm_inst = DRA7XX_CM_CORE_AON_EVE2_INST,
654 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS,
655 .dep_bit = DRA7XX_EVE2_STATDEP_SHIFT,
656 .wkdep_srcs = eve2_wkup_sleep_deps,
657 .sleepdep_srcs = eve2_wkup_sleep_deps,
658 .flags = CLKDM_CAN_HWSUP_SWSUP,
659};
660
661static struct clockdomain eve3_7xx_clkdm = {
662 .name = "eve3_clkdm",
663 .pwrdm = { .name = "eve3_pwrdm" },
664 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
665 .cm_inst = DRA7XX_CM_CORE_AON_EVE3_INST,
666 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS,
667 .dep_bit = DRA7XX_EVE3_STATDEP_SHIFT,
668 .wkdep_srcs = eve3_wkup_sleep_deps,
669 .sleepdep_srcs = eve3_wkup_sleep_deps,
670 .flags = CLKDM_CAN_HWSUP_SWSUP,
671};
672
673static struct clockdomain wkupaon_7xx_clkdm = {
674 .name = "wkupaon_clkdm",
675 .pwrdm = { .name = "wkupaon_pwrdm" },
676 .prcm_partition = DRA7XX_PRM_PARTITION,
677 .cm_inst = DRA7XX_PRM_WKUPAON_CM_INST,
678 .clkdm_offs = DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS,
679 .dep_bit = DRA7XX_WKUPAON_STATDEP_SHIFT,
680 .flags = CLKDM_CAN_FORCE_WAKEUP | CLKDM_CAN_HWSUP,
681};
682
683static struct clockdomain eve1_7xx_clkdm = {
684 .name = "eve1_clkdm",
685 .pwrdm = { .name = "eve1_pwrdm" },
686 .prcm_partition = DRA7XX_CM_CORE_AON_PARTITION,
687 .cm_inst = DRA7XX_CM_CORE_AON_EVE1_INST,
688 .clkdm_offs = DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS,
689 .dep_bit = DRA7XX_EVE1_STATDEP_SHIFT,
690 .wkdep_srcs = eve1_wkup_sleep_deps,
691 .sleepdep_srcs = eve1_wkup_sleep_deps,
692 .flags = CLKDM_CAN_HWSUP_SWSUP,
693};
694
695/* As clockdomains are added or removed above, this list must also be changed */
696static struct clockdomain *clockdomains_dra7xx[] __initdata = {
697 &l4per3_7xx_clkdm,
698 &l4per2_7xx_clkdm,
699 &mpu0_7xx_clkdm,
700 &iva_7xx_clkdm,
701 &coreaon_7xx_clkdm,
702 &ipu1_7xx_clkdm,
703 &ipu2_7xx_clkdm,
704 &l3init_7xx_clkdm,
705 &l4sec_7xx_clkdm,
706 &l3main1_7xx_clkdm,
707 &vpe_7xx_clkdm,
708 &mpu_7xx_clkdm,
709 &custefuse_7xx_clkdm,
710 &ipu_7xx_clkdm,
711 &mpu1_7xx_clkdm,
712 &gmac_7xx_clkdm,
713 &l4cfg_7xx_clkdm,
714 &dma_7xx_clkdm,
715 &rtc_7xx_clkdm,
716 &pcie_7xx_clkdm,
717 &atl_7xx_clkdm,
718 &l3instr_7xx_clkdm,
719 &dss_7xx_clkdm,
720 &emif_7xx_clkdm,
721 &emu_7xx_clkdm,
722 &dsp2_7xx_clkdm,
723 &dsp1_7xx_clkdm,
724 &cam_7xx_clkdm,
725 &l4per_7xx_clkdm,
726 &gpu_7xx_clkdm,
727 &eve4_7xx_clkdm,
728 &eve2_7xx_clkdm,
729 &eve3_7xx_clkdm,
730 &wkupaon_7xx_clkdm,
731 &eve1_7xx_clkdm,
732 NULL
733};
734
735void __init dra7xx_clockdomains_init(void)
736{
737 clkdm_register_platform_funcs(&omap4_clkdm_operations);
738 clkdm_register_clkdms(clockdomains_dra7xx);
739 clkdm_complete_init();
740}
diff --git a/arch/arm/mach-omap2/cm-regbits-7xx.h b/arch/arm/mach-omap2/cm-regbits-7xx.h
new file mode 100644
index 000000000000..ad8f81ce9b16
--- /dev/null
+++ b/arch/arm/mach-omap2/cm-regbits-7xx.h
@@ -0,0 +1,51 @@
1/*
2 * DRA7xx Clock Management register bits
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_7XX_H
24
25#define DRA7XX_ATL_STATDEP_SHIFT 30
26#define DRA7XX_CAM_STATDEP_SHIFT 9
27#define DRA7XX_DSP1_STATDEP_SHIFT 1
28#define DRA7XX_DSP2_STATDEP_SHIFT 18
29#define DRA7XX_DSS_STATDEP_SHIFT 8
30#define DRA7XX_EMIF_STATDEP_SHIFT 4
31#define DRA7XX_EVE1_STATDEP_SHIFT 19
32#define DRA7XX_EVE2_STATDEP_SHIFT 20
33#define DRA7XX_EVE3_STATDEP_SHIFT 21
34#define DRA7XX_EVE4_STATDEP_SHIFT 22
35#define DRA7XX_GMAC_STATDEP_SHIFT 25
36#define DRA7XX_GPU_STATDEP_SHIFT 10
37#define DRA7XX_IPU1_STATDEP_SHIFT 23
38#define DRA7XX_IPU2_STATDEP_SHIFT 0
39#define DRA7XX_IPU_STATDEP_SHIFT 24
40#define DRA7XX_IVA_STATDEP_SHIFT 2
41#define DRA7XX_L3INIT_STATDEP_SHIFT 7
42#define DRA7XX_L3MAIN1_STATDEP_SHIFT 5
43#define DRA7XX_L4CFG_STATDEP_SHIFT 12
44#define DRA7XX_L4PER2_STATDEP_SHIFT 26
45#define DRA7XX_L4PER3_STATDEP_SHIFT 27
46#define DRA7XX_L4PER_STATDEP_SHIFT 13
47#define DRA7XX_L4SEC_STATDEP_SHIFT 14
48#define DRA7XX_PCIE_STATDEP_SHIFT 29
49#define DRA7XX_VPE_STATDEP_SHIFT 28
50#define DRA7XX_WKUPAON_STATDEP_SHIFT 15
51#endif
diff --git a/arch/arm/mach-omap2/cm1_7xx.h b/arch/arm/mach-omap2/cm1_7xx.h
new file mode 100644
index 000000000000..ca6fa1febaac
--- /dev/null
+++ b/arch/arm/mach-omap2/cm1_7xx.h
@@ -0,0 +1,324 @@
1/*
2 * DRA7xx CM1 instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 *
21 */
22
23#ifndef __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
24#define __ARCH_ARM_MACH_OMAP2_CM1_7XX_H
25
26#include "cm_44xx_54xx.h"
27
28/* CM1 base address */
29#define DRA7XX_CM_CORE_AON_BASE 0x4a005000
30
31#define DRA7XX_CM_CORE_AON_REGADDR(inst, reg) \
32 OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))
33
34/* CM_CORE_AON instances */
35#define DRA7XX_CM_CORE_AON_OCP_SOCKET_INST 0x0000
36#define DRA7XX_CM_CORE_AON_CKGEN_INST 0x0100
37#define DRA7XX_CM_CORE_AON_MPU_INST 0x0300
38#define DRA7XX_CM_CORE_AON_DSP1_INST 0x0400
39#define DRA7XX_CM_CORE_AON_IPU_INST 0x0500
40#define DRA7XX_CM_CORE_AON_DSP2_INST 0x0600
41#define DRA7XX_CM_CORE_AON_EVE1_INST 0x0640
42#define DRA7XX_CM_CORE_AON_EVE2_INST 0x0680
43#define DRA7XX_CM_CORE_AON_EVE3_INST 0x06c0
44#define DRA7XX_CM_CORE_AON_EVE4_INST 0x0700
45#define DRA7XX_CM_CORE_AON_RTC_INST 0x0740
46#define DRA7XX_CM_CORE_AON_VPE_INST 0x0760
47#define DRA7XX_CM_CORE_AON_RESTORE_INST 0x0e00
48#define DRA7XX_CM_CORE_AON_INSTR_INST 0x0f00
49
50/* CM_CORE_AON clockdomain register offsets (from instance start) */
51#define DRA7XX_CM_CORE_AON_MPU_MPU_CDOFFS 0x0000
52#define DRA7XX_CM_CORE_AON_DSP1_DSP1_CDOFFS 0x0000
53#define DRA7XX_CM_CORE_AON_IPU_IPU1_CDOFFS 0x0000
54#define DRA7XX_CM_CORE_AON_IPU_IPU_CDOFFS 0x0040
55#define DRA7XX_CM_CORE_AON_DSP2_DSP2_CDOFFS 0x0000
56#define DRA7XX_CM_CORE_AON_EVE1_EVE1_CDOFFS 0x0000
57#define DRA7XX_CM_CORE_AON_EVE2_EVE2_CDOFFS 0x0000
58#define DRA7XX_CM_CORE_AON_EVE3_EVE3_CDOFFS 0x0000
59#define DRA7XX_CM_CORE_AON_EVE4_EVE4_CDOFFS 0x0000
60#define DRA7XX_CM_CORE_AON_RTC_RTC_CDOFFS 0x0000
61#define DRA7XX_CM_CORE_AON_VPE_VPE_CDOFFS 0x0000
62
63/* CM_CORE_AON */
64
65/* CM_CORE_AON.OCP_SOCKET_CM_CORE_AON register offsets */
66#define DRA7XX_REVISION_CM_CORE_AON_OFFSET 0x0000
67#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL_OFFSET 0x0040
68#define DRA7XX_CM_CM_CORE_AON_PROFILING_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_OCP_SOCKET_INST, 0x0040)
69#define DRA7XX_CM_CORE_AON_DEBUG_OUT_OFFSET 0x00ec
70#define DRA7XX_CM_CORE_AON_DEBUG_CFG0_OFFSET 0x00f0
71#define DRA7XX_CM_CORE_AON_DEBUG_CFG1_OFFSET 0x00f4
72#define DRA7XX_CM_CORE_AON_DEBUG_CFG2_OFFSET 0x00f8
73#define DRA7XX_CM_CORE_AON_DEBUG_CFG3_OFFSET 0x00fc
74
75/* CM_CORE_AON.CKGEN_CM_CORE_AON register offsets */
76#define DRA7XX_CM_CLKSEL_CORE_OFFSET 0x0000
77#define DRA7XX_CM_CLKSEL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0000)
78#define DRA7XX_CM_CLKSEL_ABE_OFFSET 0x0008
79#define DRA7XX_CM_CLKSEL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0008)
80#define DRA7XX_CM_DLL_CTRL_OFFSET 0x0010
81#define DRA7XX_CM_CLKMODE_DPLL_CORE_OFFSET 0x0020
82#define DRA7XX_CM_CLKMODE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0020)
83#define DRA7XX_CM_IDLEST_DPLL_CORE_OFFSET 0x0024
84#define DRA7XX_CM_IDLEST_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0024)
85#define DRA7XX_CM_AUTOIDLE_DPLL_CORE_OFFSET 0x0028
86#define DRA7XX_CM_AUTOIDLE_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0028)
87#define DRA7XX_CM_CLKSEL_DPLL_CORE_OFFSET 0x002c
88#define DRA7XX_CM_CLKSEL_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x002c)
89#define DRA7XX_CM_DIV_M2_DPLL_CORE_OFFSET 0x0030
90#define DRA7XX_CM_DIV_M2_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0030)
91#define DRA7XX_CM_DIV_M3_DPLL_CORE_OFFSET 0x0034
92#define DRA7XX_CM_DIV_M3_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0034)
93#define DRA7XX_CM_DIV_H11_DPLL_CORE_OFFSET 0x0038
94#define DRA7XX_CM_DIV_H11_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0038)
95#define DRA7XX_CM_DIV_H12_DPLL_CORE_OFFSET 0x003c
96#define DRA7XX_CM_DIV_H12_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x003c)
97#define DRA7XX_CM_DIV_H13_DPLL_CORE_OFFSET 0x0040
98#define DRA7XX_CM_DIV_H13_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0040)
99#define DRA7XX_CM_DIV_H14_DPLL_CORE_OFFSET 0x0044
100#define DRA7XX_CM_DIV_H14_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0044)
101#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_CORE_OFFSET 0x0048
102#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_CORE_OFFSET 0x004c
103#define DRA7XX_CM_DIV_H21_DPLL_CORE_OFFSET 0x0050
104#define DRA7XX_CM_DIV_H21_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0050)
105#define DRA7XX_CM_DIV_H22_DPLL_CORE_OFFSET 0x0054
106#define DRA7XX_CM_DIV_H22_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0054)
107#define DRA7XX_CM_DIV_H23_DPLL_CORE_OFFSET 0x0058
108#define DRA7XX_CM_DIV_H23_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0058)
109#define DRA7XX_CM_DIV_H24_DPLL_CORE_OFFSET 0x005c
110#define DRA7XX_CM_DIV_H24_DPLL_CORE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x005c)
111#define DRA7XX_CM_CLKMODE_DPLL_MPU_OFFSET 0x0060
112#define DRA7XX_CM_CLKMODE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0060)
113#define DRA7XX_CM_IDLEST_DPLL_MPU_OFFSET 0x0064
114#define DRA7XX_CM_IDLEST_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0064)
115#define DRA7XX_CM_AUTOIDLE_DPLL_MPU_OFFSET 0x0068
116#define DRA7XX_CM_AUTOIDLE_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0068)
117#define DRA7XX_CM_CLKSEL_DPLL_MPU_OFFSET 0x006c
118#define DRA7XX_CM_CLKSEL_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x006c)
119#define DRA7XX_CM_DIV_M2_DPLL_MPU_OFFSET 0x0070
120#define DRA7XX_CM_DIV_M2_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0070)
121#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_MPU_OFFSET 0x0088
122#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_MPU_OFFSET 0x008c
123#define DRA7XX_CM_BYPCLK_DPLL_MPU_OFFSET 0x009c
124#define DRA7XX_CM_BYPCLK_DPLL_MPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x009c)
125#define DRA7XX_CM_CLKMODE_DPLL_IVA_OFFSET 0x00a0
126#define DRA7XX_CM_CLKMODE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a0)
127#define DRA7XX_CM_IDLEST_DPLL_IVA_OFFSET 0x00a4
128#define DRA7XX_CM_IDLEST_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a4)
129#define DRA7XX_CM_AUTOIDLE_DPLL_IVA_OFFSET 0x00a8
130#define DRA7XX_CM_AUTOIDLE_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00a8)
131#define DRA7XX_CM_CLKSEL_DPLL_IVA_OFFSET 0x00ac
132#define DRA7XX_CM_CLKSEL_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ac)
133#define DRA7XX_CM_DIV_M2_DPLL_IVA_OFFSET 0x00b0
134#define DRA7XX_CM_DIV_M2_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b0)
135#define DRA7XX_CM_DIV_M3_DPLL_IVA_OFFSET 0x00b4
136#define DRA7XX_CM_DIV_M3_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00b4)
137#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_IVA_OFFSET 0x00c8
138#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_IVA_OFFSET 0x00cc
139#define DRA7XX_CM_BYPCLK_DPLL_IVA_OFFSET 0x00dc
140#define DRA7XX_CM_BYPCLK_DPLL_IVA DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00dc)
141#define DRA7XX_CM_CLKMODE_DPLL_ABE_OFFSET 0x00e0
142#define DRA7XX_CM_CLKMODE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e0)
143#define DRA7XX_CM_IDLEST_DPLL_ABE_OFFSET 0x00e4
144#define DRA7XX_CM_IDLEST_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e4)
145#define DRA7XX_CM_AUTOIDLE_DPLL_ABE_OFFSET 0x00e8
146#define DRA7XX_CM_AUTOIDLE_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00e8)
147#define DRA7XX_CM_CLKSEL_DPLL_ABE_OFFSET 0x00ec
148#define DRA7XX_CM_CLKSEL_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00ec)
149#define DRA7XX_CM_DIV_M2_DPLL_ABE_OFFSET 0x00f0
150#define DRA7XX_CM_DIV_M2_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f0)
151#define DRA7XX_CM_DIV_M3_DPLL_ABE_OFFSET 0x00f4
152#define DRA7XX_CM_DIV_M3_DPLL_ABE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x00f4)
153#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_ABE_OFFSET 0x0108
154#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_ABE_OFFSET 0x010c
155#define DRA7XX_CM_CLKMODE_DPLL_DDR_OFFSET 0x0110
156#define DRA7XX_CM_CLKMODE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0110)
157#define DRA7XX_CM_IDLEST_DPLL_DDR_OFFSET 0x0114
158#define DRA7XX_CM_IDLEST_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0114)
159#define DRA7XX_CM_AUTOIDLE_DPLL_DDR_OFFSET 0x0118
160#define DRA7XX_CM_AUTOIDLE_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0118)
161#define DRA7XX_CM_CLKSEL_DPLL_DDR_OFFSET 0x011c
162#define DRA7XX_CM_CLKSEL_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x011c)
163#define DRA7XX_CM_DIV_M2_DPLL_DDR_OFFSET 0x0120
164#define DRA7XX_CM_DIV_M2_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0120)
165#define DRA7XX_CM_DIV_M3_DPLL_DDR_OFFSET 0x0124
166#define DRA7XX_CM_DIV_M3_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0124)
167#define DRA7XX_CM_DIV_H11_DPLL_DDR_OFFSET 0x0128
168#define DRA7XX_CM_DIV_H11_DPLL_DDR DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0128)
169#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DDR_OFFSET 0x012c
170#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DDR_OFFSET 0x0130
171#define DRA7XX_CM_CLKMODE_DPLL_DSP_OFFSET 0x0134
172#define DRA7XX_CM_CLKMODE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0134)
173#define DRA7XX_CM_IDLEST_DPLL_DSP_OFFSET 0x0138
174#define DRA7XX_CM_IDLEST_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0138)
175#define DRA7XX_CM_AUTOIDLE_DPLL_DSP_OFFSET 0x013c
176#define DRA7XX_CM_AUTOIDLE_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x013c)
177#define DRA7XX_CM_CLKSEL_DPLL_DSP_OFFSET 0x0140
178#define DRA7XX_CM_CLKSEL_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0140)
179#define DRA7XX_CM_DIV_M2_DPLL_DSP_OFFSET 0x0144
180#define DRA7XX_CM_DIV_M2_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0144)
181#define DRA7XX_CM_DIV_M3_DPLL_DSP_OFFSET 0x0148
182#define DRA7XX_CM_DIV_M3_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0148)
183#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_DSP_OFFSET 0x014c
184#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_DSP_OFFSET 0x0150
185#define DRA7XX_CM_BYPCLK_DPLL_DSP_OFFSET 0x0154
186#define DRA7XX_CM_BYPCLK_DPLL_DSP DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0154)
187#define DRA7XX_CM_SHADOW_FREQ_CONFIG1_OFFSET 0x0160
188#define DRA7XX_CM_SHADOW_FREQ_CONFIG2_OFFSET 0x0164
189#define DRA7XX_CM_DYN_DEP_PRESCAL_OFFSET 0x0170
190#define DRA7XX_CM_RESTORE_ST_OFFSET 0x0180
191#define DRA7XX_CM_CLKMODE_DPLL_EVE_OFFSET 0x0184
192#define DRA7XX_CM_CLKMODE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0184)
193#define DRA7XX_CM_IDLEST_DPLL_EVE_OFFSET 0x0188
194#define DRA7XX_CM_IDLEST_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0188)
195#define DRA7XX_CM_AUTOIDLE_DPLL_EVE_OFFSET 0x018c
196#define DRA7XX_CM_AUTOIDLE_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x018c)
197#define DRA7XX_CM_CLKSEL_DPLL_EVE_OFFSET 0x0190
198#define DRA7XX_CM_CLKSEL_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0190)
199#define DRA7XX_CM_DIV_M2_DPLL_EVE_OFFSET 0x0194
200#define DRA7XX_CM_DIV_M2_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0194)
201#define DRA7XX_CM_DIV_M3_DPLL_EVE_OFFSET 0x0198
202#define DRA7XX_CM_DIV_M3_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x0198)
203#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_EVE_OFFSET 0x019c
204#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_EVE_OFFSET 0x01a0
205#define DRA7XX_CM_BYPCLK_DPLL_EVE_OFFSET 0x01a4
206#define DRA7XX_CM_BYPCLK_DPLL_EVE DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a4)
207#define DRA7XX_CM_CLKMODE_DPLL_GMAC_OFFSET 0x01a8
208#define DRA7XX_CM_CLKMODE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01a8)
209#define DRA7XX_CM_IDLEST_DPLL_GMAC_OFFSET 0x01ac
210#define DRA7XX_CM_IDLEST_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ac)
211#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC_OFFSET 0x01b0
212#define DRA7XX_CM_AUTOIDLE_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b0)
213#define DRA7XX_CM_CLKSEL_DPLL_GMAC_OFFSET 0x01b4
214#define DRA7XX_CM_CLKSEL_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b4)
215#define DRA7XX_CM_DIV_M2_DPLL_GMAC_OFFSET 0x01b8
216#define DRA7XX_CM_DIV_M2_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01b8)
217#define DRA7XX_CM_DIV_M3_DPLL_GMAC_OFFSET 0x01bc
218#define DRA7XX_CM_DIV_M3_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01bc)
219#define DRA7XX_CM_DIV_H11_DPLL_GMAC_OFFSET 0x01c0
220#define DRA7XX_CM_DIV_H11_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c0)
221#define DRA7XX_CM_DIV_H12_DPLL_GMAC_OFFSET 0x01c4
222#define DRA7XX_CM_DIV_H12_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c4)
223#define DRA7XX_CM_DIV_H13_DPLL_GMAC_OFFSET 0x01c8
224#define DRA7XX_CM_DIV_H13_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01c8)
225#define DRA7XX_CM_DIV_H14_DPLL_GMAC_OFFSET 0x01cc
226#define DRA7XX_CM_DIV_H14_DPLL_GMAC DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01cc)
227#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GMAC_OFFSET 0x01d0
228#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GMAC_OFFSET 0x01d4
229#define DRA7XX_CM_CLKMODE_DPLL_GPU_OFFSET 0x01d8
230#define DRA7XX_CM_CLKMODE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01d8)
231#define DRA7XX_CM_IDLEST_DPLL_GPU_OFFSET 0x01dc
232#define DRA7XX_CM_IDLEST_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01dc)
233#define DRA7XX_CM_AUTOIDLE_DPLL_GPU_OFFSET 0x01e0
234#define DRA7XX_CM_AUTOIDLE_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e0)
235#define DRA7XX_CM_CLKSEL_DPLL_GPU_OFFSET 0x01e4
236#define DRA7XX_CM_CLKSEL_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e4)
237#define DRA7XX_CM_DIV_M2_DPLL_GPU_OFFSET 0x01e8
238#define DRA7XX_CM_DIV_M2_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01e8)
239#define DRA7XX_CM_DIV_M3_DPLL_GPU_OFFSET 0x01ec
240#define DRA7XX_CM_DIV_M3_DPLL_GPU DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_CKGEN_INST, 0x01ec)
241#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_GPU_OFFSET 0x01f0
242#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_GPU_OFFSET 0x01f4
243
244/* CM_CORE_AON.MPU_CM_CORE_AON register offsets */
245#define DRA7XX_CM_MPU_CLKSTCTRL_OFFSET 0x0000
246#define DRA7XX_CM_MPU_STATICDEP_OFFSET 0x0004
247#define DRA7XX_CM_MPU_DYNAMICDEP_OFFSET 0x0008
248#define DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET 0x0020
249#define DRA7XX_CM_MPU_MPU_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0020)
250#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL_OFFSET 0x0028
251#define DRA7XX_CM_MPU_MPU_MPU_DBG_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_MPU_INST, 0x0028)
252
253/* CM_CORE_AON.DSP1_CM_CORE_AON register offsets */
254#define DRA7XX_CM_DSP1_CLKSTCTRL_OFFSET 0x0000
255#define DRA7XX_CM_DSP1_STATICDEP_OFFSET 0x0004
256#define DRA7XX_CM_DSP1_DYNAMICDEP_OFFSET 0x0008
257#define DRA7XX_CM_DSP1_DSP1_CLKCTRL_OFFSET 0x0020
258#define DRA7XX_CM_DSP1_DSP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP1_INST, 0x0020)
259
260/* CM_CORE_AON.IPU_CM_CORE_AON register offsets */
261#define DRA7XX_CM_IPU1_CLKSTCTRL_OFFSET 0x0000
262#define DRA7XX_CM_IPU1_STATICDEP_OFFSET 0x0004
263#define DRA7XX_CM_IPU1_DYNAMICDEP_OFFSET 0x0008
264#define DRA7XX_CM_IPU1_IPU1_CLKCTRL_OFFSET 0x0020
265#define DRA7XX_CM_IPU1_IPU1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0020)
266#define DRA7XX_CM_IPU_CLKSTCTRL_OFFSET 0x0040
267#define DRA7XX_CM_IPU_MCASP1_CLKCTRL_OFFSET 0x0050
268#define DRA7XX_CM_IPU_MCASP1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0050)
269#define DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET 0x0058
270#define DRA7XX_CM_IPU_TIMER5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0058)
271#define DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET 0x0060
272#define DRA7XX_CM_IPU_TIMER6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0060)
273#define DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET 0x0068
274#define DRA7XX_CM_IPU_TIMER7_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0068)
275#define DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET 0x0070
276#define DRA7XX_CM_IPU_TIMER8_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0070)
277#define DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET 0x0078
278#define DRA7XX_CM_IPU_I2C5_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0078)
279#define DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET 0x0080
280#define DRA7XX_CM_IPU_UART6_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_IPU_INST, 0x0080)
281
282/* CM_CORE_AON.DSP2_CM_CORE_AON register offsets */
283#define DRA7XX_CM_DSP2_CLKSTCTRL_OFFSET 0x0000
284#define DRA7XX_CM_DSP2_STATICDEP_OFFSET 0x0004
285#define DRA7XX_CM_DSP2_DYNAMICDEP_OFFSET 0x0008
286#define DRA7XX_CM_DSP2_DSP2_CLKCTRL_OFFSET 0x0020
287#define DRA7XX_CM_DSP2_DSP2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_DSP2_INST, 0x0020)
288
289/* CM_CORE_AON.EVE1_CM_CORE_AON register offsets */
290#define DRA7XX_CM_EVE1_CLKSTCTRL_OFFSET 0x0000
291#define DRA7XX_CM_EVE1_STATICDEP_OFFSET 0x0004
292#define DRA7XX_CM_EVE1_EVE1_CLKCTRL_OFFSET 0x0020
293#define DRA7XX_CM_EVE1_EVE1_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE1_INST, 0x0020)
294
295/* CM_CORE_AON.EVE2_CM_CORE_AON register offsets */
296#define DRA7XX_CM_EVE2_CLKSTCTRL_OFFSET 0x0000
297#define DRA7XX_CM_EVE2_STATICDEP_OFFSET 0x0004
298#define DRA7XX_CM_EVE2_EVE2_CLKCTRL_OFFSET 0x0020
299#define DRA7XX_CM_EVE2_EVE2_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE2_INST, 0x0020)
300
301/* CM_CORE_AON.EVE3_CM_CORE_AON register offsets */
302#define DRA7XX_CM_EVE3_CLKSTCTRL_OFFSET 0x0000
303#define DRA7XX_CM_EVE3_STATICDEP_OFFSET 0x0004
304#define DRA7XX_CM_EVE3_EVE3_CLKCTRL_OFFSET 0x0020
305#define DRA7XX_CM_EVE3_EVE3_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE3_INST, 0x0020)
306
307/* CM_CORE_AON.EVE4_CM_CORE_AON register offsets */
308#define DRA7XX_CM_EVE4_CLKSTCTRL_OFFSET 0x0000
309#define DRA7XX_CM_EVE4_STATICDEP_OFFSET 0x0004
310#define DRA7XX_CM_EVE4_EVE4_CLKCTRL_OFFSET 0x0020
311#define DRA7XX_CM_EVE4_EVE4_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_EVE4_INST, 0x0020)
312
313/* CM_CORE_AON.RTC_CM_CORE_AON register offsets */
314#define DRA7XX_CM_RTC_CLKSTCTRL_OFFSET 0x0000
315#define DRA7XX_CM_RTC_RTCSS_CLKCTRL_OFFSET 0x0004
316#define DRA7XX_CM_RTC_RTCSS_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_RTC_INST, 0x0004)
317
318/* CM_CORE_AON.VPE_CM_CORE_AON register offsets */
319#define DRA7XX_CM_VPE_CLKSTCTRL_OFFSET 0x0000
320#define DRA7XX_CM_VPE_VPE_CLKCTRL_OFFSET 0x0004
321#define DRA7XX_CM_VPE_VPE_CLKCTRL DRA7XX_CM_CORE_AON_REGADDR(DRA7XX_CM_CORE_AON_VPE_INST, 0x0004)
322#define DRA7XX_CM_VPE_STATICDEP_OFFSET 0x0008
323
324#endif
diff --git a/arch/arm/mach-omap2/cm2_7xx.h b/arch/arm/mach-omap2/cm2_7xx.h
new file mode 100644
index 000000000000..9ad7594e7622
--- /dev/null
+++ b/arch/arm/mach-omap2/cm2_7xx.h
@@ -0,0 +1,513 @@
1/*
2 * DRA7xx CM2 instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
23#define __ARCH_ARM_MACH_OMAP2_CM2_7XX_H
24
25#include "cm_44xx_54xx.h"
26
27/* CM2 base address */
28#define DRA7XX_CM_CORE_BASE 0x4a008000
29
30#define DRA7XX_CM_CORE_REGADDR(inst, reg) \
31 OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg))
32
33/* CM_CORE instances */
34#define DRA7XX_CM_CORE_OCP_SOCKET_INST 0x0000
35#define DRA7XX_CM_CORE_CKGEN_INST 0x0104
36#define DRA7XX_CM_CORE_COREAON_INST 0x0600
37#define DRA7XX_CM_CORE_CORE_INST 0x0700
38#define DRA7XX_CM_CORE_IVA_INST 0x0f00
39#define DRA7XX_CM_CORE_CAM_INST 0x1000
40#define DRA7XX_CM_CORE_DSS_INST 0x1100
41#define DRA7XX_CM_CORE_GPU_INST 0x1200
42#define DRA7XX_CM_CORE_L3INIT_INST 0x1300
43#define DRA7XX_CM_CORE_CUSTEFUSE_INST 0x1600
44#define DRA7XX_CM_CORE_L4PER_INST 0x1700
45#define DRA7XX_CM_CORE_RESTORE_INST 0x1e18
46
47/* CM_CORE clockdomain register offsets (from instance start) */
48#define DRA7XX_CM_CORE_COREAON_COREAON_CDOFFS 0x0000
49#define DRA7XX_CM_CORE_CORE_L3MAIN1_CDOFFS 0x0000
50#define DRA7XX_CM_CORE_CORE_IPU2_CDOFFS 0x0200
51#define DRA7XX_CM_CORE_CORE_DMA_CDOFFS 0x0300
52#define DRA7XX_CM_CORE_CORE_EMIF_CDOFFS 0x0400
53#define DRA7XX_CM_CORE_CORE_ATL_CDOFFS 0x0520
54#define DRA7XX_CM_CORE_CORE_L4CFG_CDOFFS 0x0600
55#define DRA7XX_CM_CORE_CORE_L3INSTR_CDOFFS 0x0700
56#define DRA7XX_CM_CORE_IVA_IVA_CDOFFS 0x0000
57#define DRA7XX_CM_CORE_CAM_CAM_CDOFFS 0x0000
58#define DRA7XX_CM_CORE_DSS_DSS_CDOFFS 0x0000
59#define DRA7XX_CM_CORE_GPU_GPU_CDOFFS 0x0000
60#define DRA7XX_CM_CORE_L3INIT_L3INIT_CDOFFS 0x0000
61#define DRA7XX_CM_CORE_L3INIT_PCIE_CDOFFS 0x00a0
62#define DRA7XX_CM_CORE_L3INIT_GMAC_CDOFFS 0x00c0
63#define DRA7XX_CM_CORE_CUSTEFUSE_CUSTEFUSE_CDOFFS 0x0000
64#define DRA7XX_CM_CORE_L4PER_L4PER_CDOFFS 0x0000
65#define DRA7XX_CM_CORE_L4PER_L4SEC_CDOFFS 0x0180
66#define DRA7XX_CM_CORE_L4PER_L4PER2_CDOFFS 0x01fc
67#define DRA7XX_CM_CORE_L4PER_L4PER3_CDOFFS 0x0210
68
69/* CM_CORE */
70
71/* CM_CORE.OCP_SOCKET_CM_CORE register offsets */
72#define DRA7XX_REVISION_CM_CORE_OFFSET 0x0000
73#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL_OFFSET 0x0040
74#define DRA7XX_CM_CM_CORE_PROFILING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_OCP_SOCKET_INST, 0x0040)
75#define DRA7XX_CM_CORE_DEBUG_CFG_OFFSET 0x00f0
76
77/* CM_CORE.CKGEN_CM_CORE register offsets */
78#define DRA7XX_CM_CLKSEL_USB_60MHZ_OFFSET 0x0000
79#define DRA7XX_CM_CLKSEL_USB_60MHZ DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0000)
80#define DRA7XX_CM_CLKMODE_DPLL_PER_OFFSET 0x003c
81#define DRA7XX_CM_CLKMODE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x003c)
82#define DRA7XX_CM_IDLEST_DPLL_PER_OFFSET 0x0040
83#define DRA7XX_CM_IDLEST_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0040)
84#define DRA7XX_CM_AUTOIDLE_DPLL_PER_OFFSET 0x0044
85#define DRA7XX_CM_AUTOIDLE_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0044)
86#define DRA7XX_CM_CLKSEL_DPLL_PER_OFFSET 0x0048
87#define DRA7XX_CM_CLKSEL_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0048)
88#define DRA7XX_CM_DIV_M2_DPLL_PER_OFFSET 0x004c
89#define DRA7XX_CM_DIV_M2_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x004c)
90#define DRA7XX_CM_DIV_M3_DPLL_PER_OFFSET 0x0050
91#define DRA7XX_CM_DIV_M3_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0050)
92#define DRA7XX_CM_DIV_H11_DPLL_PER_OFFSET 0x0054
93#define DRA7XX_CM_DIV_H11_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0054)
94#define DRA7XX_CM_DIV_H12_DPLL_PER_OFFSET 0x0058
95#define DRA7XX_CM_DIV_H12_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0058)
96#define DRA7XX_CM_DIV_H13_DPLL_PER_OFFSET 0x005c
97#define DRA7XX_CM_DIV_H13_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x005c)
98#define DRA7XX_CM_DIV_H14_DPLL_PER_OFFSET 0x0060
99#define DRA7XX_CM_DIV_H14_DPLL_PER DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0060)
100#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PER_OFFSET 0x0064
101#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PER_OFFSET 0x0068
102#define DRA7XX_CM_CLKMODE_DPLL_USB_OFFSET 0x007c
103#define DRA7XX_CM_CLKMODE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x007c)
104#define DRA7XX_CM_IDLEST_DPLL_USB_OFFSET 0x0080
105#define DRA7XX_CM_IDLEST_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0080)
106#define DRA7XX_CM_AUTOIDLE_DPLL_USB_OFFSET 0x0084
107#define DRA7XX_CM_AUTOIDLE_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0084)
108#define DRA7XX_CM_CLKSEL_DPLL_USB_OFFSET 0x0088
109#define DRA7XX_CM_CLKSEL_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0088)
110#define DRA7XX_CM_DIV_M2_DPLL_USB_OFFSET 0x008c
111#define DRA7XX_CM_DIV_M2_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x008c)
112#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_USB_OFFSET 0x00a4
113#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_USB_OFFSET 0x00a8
114#define DRA7XX_CM_CLKDCOLDO_DPLL_USB_OFFSET 0x00b0
115#define DRA7XX_CM_CLKDCOLDO_DPLL_USB DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00b0)
116#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF_OFFSET 0x00fc
117#define DRA7XX_CM_CLKMODE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x00fc)
118#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF_OFFSET 0x0100
119#define DRA7XX_CM_IDLEST_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0100)
120#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF_OFFSET 0x0104
121#define DRA7XX_CM_AUTOIDLE_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0104)
122#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF_OFFSET 0x0108
123#define DRA7XX_CM_CLKSEL_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0108)
124#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF_OFFSET 0x010c
125#define DRA7XX_CM_DIV_M2_DPLL_PCIE_REF DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x010c)
126#define DRA7XX_CM_SSC_DELTAMSTEP_DPLL_PCIE_REF_OFFSET 0x0110
127#define DRA7XX_CM_SSC_MODFREQDIV_DPLL_PCIE_REF_OFFSET 0x0114
128#define DRA7XX_CM_CLKMODE_APLL_PCIE_OFFSET 0x0118
129#define DRA7XX_CM_CLKMODE_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0118)
130#define DRA7XX_CM_IDLEST_APLL_PCIE_OFFSET 0x011c
131#define DRA7XX_CM_IDLEST_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x011c)
132#define DRA7XX_CM_DIV_M2_APLL_PCIE_OFFSET 0x0120
133#define DRA7XX_CM_DIV_M2_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0120)
134#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE_OFFSET 0x0124
135#define DRA7XX_CM_CLKVCOLDO_APLL_PCIE DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CKGEN_INST, 0x0124)
136
137/* CM_CORE.COREAON_CM_CORE register offsets */
138#define DRA7XX_CM_COREAON_CLKSTCTRL_OFFSET 0x0000
139#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET 0x0028
140#define DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0028)
141#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET 0x0038
142#define DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0038)
143#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL_OFFSET 0x0040
144#define DRA7XX_CM_COREAON_USB_PHY1_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0040)
145#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0050
146#define DRA7XX_CM_COREAON_IO_SRCOMP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0050)
147#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL_OFFSET 0x0058
148#define DRA7XX_CM_COREAON_SMARTREFLEX_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0058)
149#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL_OFFSET 0x0068
150#define DRA7XX_CM_COREAON_SMARTREFLEX_DSPEVE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0068)
151#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL_OFFSET 0x0078
152#define DRA7XX_CM_COREAON_SMARTREFLEX_IVAHD_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0078)
153#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL_OFFSET 0x0088
154#define DRA7XX_CM_COREAON_USB_PHY2_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0088)
155#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL_OFFSET 0x0098
156#define DRA7XX_CM_COREAON_USB_PHY3_CORE_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x0098)
157#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL_OFFSET 0x00a0
158#define DRA7XX_CM_COREAON_DUMMY_MODULE1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00a0)
159#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL_OFFSET 0x00b0
160#define DRA7XX_CM_COREAON_DUMMY_MODULE2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00b0)
161#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL_OFFSET 0x00c0
162#define DRA7XX_CM_COREAON_DUMMY_MODULE3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00c0)
163#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL_OFFSET 0x00d0
164#define DRA7XX_CM_COREAON_DUMMY_MODULE4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_COREAON_INST, 0x00d0)
165
166/* CM_CORE.CORE_CM_CORE register offsets */
167#define DRA7XX_CM_L3MAIN1_CLKSTCTRL_OFFSET 0x0000
168#define DRA7XX_CM_L3MAIN1_DYNAMICDEP_OFFSET 0x0008
169#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET 0x0020
170#define DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0020)
171#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET 0x0028
172#define DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0028)
173#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL_OFFSET 0x0030
174#define DRA7XX_CM_L3MAIN1_MMU_EDMA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0030)
175#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL_OFFSET 0x0050
176#define DRA7XX_CM_L3MAIN1_OCMC_RAM1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0050)
177#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL_OFFSET 0x0058
178#define DRA7XX_CM_L3MAIN1_OCMC_RAM2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0058)
179#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL_OFFSET 0x0060
180#define DRA7XX_CM_L3MAIN1_OCMC_RAM3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0060)
181#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL_OFFSET 0x0068
182#define DRA7XX_CM_L3MAIN1_OCMC_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0068)
183#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL_OFFSET 0x0070
184#define DRA7XX_CM_L3MAIN1_TPCC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0070)
185#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL_OFFSET 0x0078
186#define DRA7XX_CM_L3MAIN1_TPTC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0078)
187#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL_OFFSET 0x0080
188#define DRA7XX_CM_L3MAIN1_TPTC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0080)
189#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET 0x0088
190#define DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0088)
191#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET 0x0090
192#define DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0090)
193#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL_OFFSET 0x0098
194#define DRA7XX_CM_L3MAIN1_SPARE_CME_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0098)
195#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL_OFFSET 0x00a0
196#define DRA7XX_CM_L3MAIN1_SPARE_HDMI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a0)
197#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL_OFFSET 0x00a8
198#define DRA7XX_CM_L3MAIN1_SPARE_ICM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00a8)
199#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL_OFFSET 0x00b0
200#define DRA7XX_CM_L3MAIN1_SPARE_IVA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b0)
201#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL_OFFSET 0x00b8
202#define DRA7XX_CM_L3MAIN1_SPARE_SATA2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00b8)
203#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL_OFFSET 0x00c0
204#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c0)
205#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL_OFFSET 0x00c8
206#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00c8)
207#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL_OFFSET 0x00d0
208#define DRA7XX_CM_L3MAIN1_SPARE_UNKNOWN6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d0)
209#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL_OFFSET 0x00d8
210#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00d8)
211#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL_OFFSET 0x00f0
212#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f0)
213#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL_OFFSET 0x00f8
214#define DRA7XX_CM_L3MAIN1_SPARE_VIDEOPLL3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x00f8)
215#define DRA7XX_CM_IPU2_CLKSTCTRL_OFFSET 0x0200
216#define DRA7XX_CM_IPU2_STATICDEP_OFFSET 0x0204
217#define DRA7XX_CM_IPU2_DYNAMICDEP_OFFSET 0x0208
218#define DRA7XX_CM_IPU2_IPU2_CLKCTRL_OFFSET 0x0220
219#define DRA7XX_CM_IPU2_IPU2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0220)
220#define DRA7XX_CM_DMA_CLKSTCTRL_OFFSET 0x0300
221#define DRA7XX_CM_DMA_STATICDEP_OFFSET 0x0304
222#define DRA7XX_CM_DMA_DYNAMICDEP_OFFSET 0x0308
223#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET 0x0320
224#define DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0320)
225#define DRA7XX_CM_EMIF_CLKSTCTRL_OFFSET 0x0400
226#define DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET 0x0420
227#define DRA7XX_CM_EMIF_DMM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0420)
228#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL_OFFSET 0x0428
229#define DRA7XX_CM_EMIF_EMIF_OCP_FW_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0428)
230#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET 0x0430
231#define DRA7XX_CM_EMIF_EMIF1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0430)
232#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET 0x0438
233#define DRA7XX_CM_EMIF_EMIF2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0438)
234#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL_OFFSET 0x0440
235#define DRA7XX_CM_EMIF_EMIF_DLL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0440)
236#define DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET 0x0500
237#define DRA7XX_CM_ATL_ATL_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0500)
238#define DRA7XX_CM_ATL_CLKSTCTRL_OFFSET 0x0520
239#define DRA7XX_CM_L4CFG_CLKSTCTRL_OFFSET 0x0600
240#define DRA7XX_CM_L4CFG_DYNAMICDEP_OFFSET 0x0608
241#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET 0x0620
242#define DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0620)
243#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET 0x0628
244#define DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0628)
245#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL_OFFSET 0x0630
246#define DRA7XX_CM_L4CFG_MAILBOX1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0630)
247#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL_OFFSET 0x0638
248#define DRA7XX_CM_L4CFG_SAR_ROM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0638)
249#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL_OFFSET 0x0640
250#define DRA7XX_CM_L4CFG_OCP2SCP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0640)
251#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL_OFFSET 0x0648
252#define DRA7XX_CM_L4CFG_MAILBOX2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0648)
253#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL_OFFSET 0x0650
254#define DRA7XX_CM_L4CFG_MAILBOX3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0650)
255#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL_OFFSET 0x0658
256#define DRA7XX_CM_L4CFG_MAILBOX4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0658)
257#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL_OFFSET 0x0660
258#define DRA7XX_CM_L4CFG_MAILBOX5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0660)
259#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL_OFFSET 0x0668
260#define DRA7XX_CM_L4CFG_MAILBOX6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0668)
261#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL_OFFSET 0x0670
262#define DRA7XX_CM_L4CFG_MAILBOX7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0670)
263#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL_OFFSET 0x0678
264#define DRA7XX_CM_L4CFG_MAILBOX8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0678)
265#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL_OFFSET 0x0680
266#define DRA7XX_CM_L4CFG_MAILBOX9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0680)
267#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL_OFFSET 0x0688
268#define DRA7XX_CM_L4CFG_MAILBOX10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0688)
269#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL_OFFSET 0x0690
270#define DRA7XX_CM_L4CFG_MAILBOX11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0690)
271#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL_OFFSET 0x0698
272#define DRA7XX_CM_L4CFG_MAILBOX12_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0698)
273#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL_OFFSET 0x06a0
274#define DRA7XX_CM_L4CFG_MAILBOX13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a0)
275#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL_OFFSET 0x06a8
276#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_RTC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06a8)
277#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL_OFFSET 0x06b0
278#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b0)
279#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL_OFFSET 0x06b8
280#define DRA7XX_CM_L4CFG_SPARE_SMARTREFLEX_WKUP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06b8)
281#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL_OFFSET 0x06c0
282#define DRA7XX_CM_L4CFG_IO_DELAY_BLOCK_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x06c0)
283#define DRA7XX_CM_L3INSTR_CLKSTCTRL_OFFSET 0x0700
284#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET 0x0720
285#define DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0720)
286#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET 0x0728
287#define DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0728)
288#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL_OFFSET 0x0740
289#define DRA7XX_CM_L3INSTR_OCP_WP_NOC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0740)
290#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL_OFFSET 0x0748
291#define DRA7XX_CM_L3INSTR_DLL_AGING_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0748)
292#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL_OFFSET 0x0750
293#define DRA7XX_CM_L3INSTR_CTRL_MODULE_BANDGAP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CORE_INST, 0x0750)
294
295/* CM_CORE.IVA_CM_CORE register offsets */
296#define DRA7XX_CM_IVA_CLKSTCTRL_OFFSET 0x0000
297#define DRA7XX_CM_IVA_STATICDEP_OFFSET 0x0004
298#define DRA7XX_CM_IVA_DYNAMICDEP_OFFSET 0x0008
299#define DRA7XX_CM_IVA_IVA_CLKCTRL_OFFSET 0x0020
300#define DRA7XX_CM_IVA_IVA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0020)
301#define DRA7XX_CM_IVA_SL2_CLKCTRL_OFFSET 0x0028
302#define DRA7XX_CM_IVA_SL2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_IVA_INST, 0x0028)
303
304/* CM_CORE.CAM_CM_CORE register offsets */
305#define DRA7XX_CM_CAM_CLKSTCTRL_OFFSET 0x0000
306#define DRA7XX_CM_CAM_STATICDEP_OFFSET 0x0004
307#define DRA7XX_CM_CAM_VIP1_CLKCTRL_OFFSET 0x0020
308#define DRA7XX_CM_CAM_VIP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0020)
309#define DRA7XX_CM_CAM_VIP2_CLKCTRL_OFFSET 0x0028
310#define DRA7XX_CM_CAM_VIP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0028)
311#define DRA7XX_CM_CAM_VIP3_CLKCTRL_OFFSET 0x0030
312#define DRA7XX_CM_CAM_VIP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0030)
313#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL_OFFSET 0x0038
314#define DRA7XX_CM_CAM_LVDSRX_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0038)
315#define DRA7XX_CM_CAM_CSI1_CLKCTRL_OFFSET 0x0040
316#define DRA7XX_CM_CAM_CSI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0040)
317#define DRA7XX_CM_CAM_CSI2_CLKCTRL_OFFSET 0x0048
318#define DRA7XX_CM_CAM_CSI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CAM_INST, 0x0048)
319
320/* CM_CORE.DSS_CM_CORE register offsets */
321#define DRA7XX_CM_DSS_CLKSTCTRL_OFFSET 0x0000
322#define DRA7XX_CM_DSS_STATICDEP_OFFSET 0x0004
323#define DRA7XX_CM_DSS_DYNAMICDEP_OFFSET 0x0008
324#define DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET 0x0020
325#define DRA7XX_CM_DSS_DSS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0020)
326#define DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET 0x0030
327#define DRA7XX_CM_DSS_BB2D_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x0030)
328#define DRA7XX_CM_DSS_SDVENC_CLKCTRL_OFFSET 0x003c
329#define DRA7XX_CM_DSS_SDVENC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_DSS_INST, 0x003c)
330
331/* CM_CORE.GPU_CM_CORE register offsets */
332#define DRA7XX_CM_GPU_CLKSTCTRL_OFFSET 0x0000
333#define DRA7XX_CM_GPU_STATICDEP_OFFSET 0x0004
334#define DRA7XX_CM_GPU_DYNAMICDEP_OFFSET 0x0008
335#define DRA7XX_CM_GPU_GPU_CLKCTRL_OFFSET 0x0020
336#define DRA7XX_CM_GPU_GPU_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_GPU_INST, 0x0020)
337
338/* CM_CORE.L3INIT_CM_CORE register offsets */
339#define DRA7XX_CM_L3INIT_CLKSTCTRL_OFFSET 0x0000
340#define DRA7XX_CM_L3INIT_STATICDEP_OFFSET 0x0004
341#define DRA7XX_CM_L3INIT_DYNAMICDEP_OFFSET 0x0008
342#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET 0x0028
343#define DRA7XX_CM_L3INIT_MMC1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0028)
344#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET 0x0030
345#define DRA7XX_CM_L3INIT_MMC2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0030)
346#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET 0x0040
347#define DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0040)
348#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET 0x0048
349#define DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0048)
350#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET 0x0050
351#define DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0050)
352#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL_OFFSET 0x0058
353#define DRA7XX_CM_L3INIT_MLB_SS_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0058)
354#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL_OFFSET 0x0078
355#define DRA7XX_CM_L3INIT_IEEE1500_2_OCP_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0078)
356#define DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET 0x0088
357#define DRA7XX_CM_L3INIT_SATA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x0088)
358#define DRA7XX_CM_PCIE_CLKSTCTRL_OFFSET 0x00a0
359#define DRA7XX_CM_PCIE_STATICDEP_OFFSET 0x00a4
360#define DRA7XX_CM_GMAC_CLKSTCTRL_OFFSET 0x00c0
361#define DRA7XX_CM_GMAC_STATICDEP_OFFSET 0x00c4
362#define DRA7XX_CM_GMAC_DYNAMICDEP_OFFSET 0x00c8
363#define DRA7XX_CM_GMAC_GMAC_CLKCTRL_OFFSET 0x00d0
364#define DRA7XX_CM_GMAC_GMAC_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00d0)
365#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET 0x00e0
366#define DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e0)
367#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL_OFFSET 0x00e8
368#define DRA7XX_CM_L3INIT_OCP2SCP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00e8)
369#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET 0x00f0
370#define DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L3INIT_INST, 0x00f0)
371
372/* CM_CORE.CUSTEFUSE_CM_CORE register offsets */
373#define DRA7XX_CM_CUSTEFUSE_CLKSTCTRL_OFFSET 0x0000
374#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL_OFFSET 0x0020
375#define DRA7XX_CM_CUSTEFUSE_EFUSE_CTRL_CUST_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_CUSTEFUSE_INST, 0x0020)
376
377/* CM_CORE.L4PER_CM_CORE register offsets */
378#define DRA7XX_CM_L4PER_CLKSTCTRL_OFFSET 0x0000
379#define DRA7XX_CM_L4PER_DYNAMICDEP_OFFSET 0x0008
380#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET 0x000c
381#define DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x000c)
382#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET 0x0014
383#define DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0014)
384#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL_OFFSET 0x0018
385#define DRA7XX_CM_L4PER2_PRUSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0018)
386#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL_OFFSET 0x0020
387#define DRA7XX_CM_L4PER2_PRUSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0020)
388#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET 0x0028
389#define DRA7XX_CM_L4PER_TIMER10_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0028)
390#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET 0x0030
391#define DRA7XX_CM_L4PER_TIMER11_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0030)
392#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET 0x0038
393#define DRA7XX_CM_L4PER_TIMER2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0038)
394#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET 0x0040
395#define DRA7XX_CM_L4PER_TIMER3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0040)
396#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET 0x0048
397#define DRA7XX_CM_L4PER_TIMER4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0048)
398#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET 0x0050
399#define DRA7XX_CM_L4PER_TIMER9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0050)
400#define DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET 0x0058
401#define DRA7XX_CM_L4PER_ELM_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0058)
402#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET 0x0060
403#define DRA7XX_CM_L4PER_GPIO2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0060)
404#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET 0x0068
405#define DRA7XX_CM_L4PER_GPIO3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0068)
406#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET 0x0070
407#define DRA7XX_CM_L4PER_GPIO4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0070)
408#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET 0x0078
409#define DRA7XX_CM_L4PER_GPIO5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0078)
410#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET 0x0080
411#define DRA7XX_CM_L4PER_GPIO6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0080)
412#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET 0x0088
413#define DRA7XX_CM_L4PER_HDQ1W_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0088)
414#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL_OFFSET 0x0090
415#define DRA7XX_CM_L4PER2_PWMSS2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0090)
416#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL_OFFSET 0x0098
417#define DRA7XX_CM_L4PER2_PWMSS3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0098)
418#define DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET 0x00a0
419#define DRA7XX_CM_L4PER_I2C1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a0)
420#define DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET 0x00a8
421#define DRA7XX_CM_L4PER_I2C2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00a8)
422#define DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET 0x00b0
423#define DRA7XX_CM_L4PER_I2C3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b0)
424#define DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET 0x00b8
425#define DRA7XX_CM_L4PER_I2C4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00b8)
426#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET 0x00c0
427#define DRA7XX_CM_L4PER_L4_PER1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c0)
428#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL_OFFSET 0x00c4
429#define DRA7XX_CM_L4PER2_PWMSS1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c4)
430#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL_OFFSET 0x00c8
431#define DRA7XX_CM_L4PER3_TIMER13_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00c8)
432#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL_OFFSET 0x00d0
433#define DRA7XX_CM_L4PER3_TIMER14_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d0)
434#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL_OFFSET 0x00d8
435#define DRA7XX_CM_L4PER3_TIMER15_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00d8)
436#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET 0x00f0
437#define DRA7XX_CM_L4PER_MCSPI1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f0)
438#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET 0x00f8
439#define DRA7XX_CM_L4PER_MCSPI2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x00f8)
440#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET 0x0100
441#define DRA7XX_CM_L4PER_MCSPI3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0100)
442#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET 0x0108
443#define DRA7XX_CM_L4PER_MCSPI4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0108)
444#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET 0x0110
445#define DRA7XX_CM_L4PER_GPIO7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0110)
446#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET 0x0118
447#define DRA7XX_CM_L4PER_GPIO8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0118)
448#define DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET 0x0120
449#define DRA7XX_CM_L4PER_MMC3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0120)
450#define DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET 0x0128
451#define DRA7XX_CM_L4PER_MMC4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0128)
452#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL_OFFSET 0x0130
453#define DRA7XX_CM_L4PER3_TIMER16_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0130)
454#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET 0x0138
455#define DRA7XX_CM_L4PER2_QSPI_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0138)
456#define DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET 0x0140
457#define DRA7XX_CM_L4PER_UART1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0140)
458#define DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET 0x0148
459#define DRA7XX_CM_L4PER_UART2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0148)
460#define DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET 0x0150
461#define DRA7XX_CM_L4PER_UART3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0150)
462#define DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET 0x0158
463#define DRA7XX_CM_L4PER_UART4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0158)
464#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL_OFFSET 0x0160
465#define DRA7XX_CM_L4PER2_MCASP2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0160)
466#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL_OFFSET 0x0168
467#define DRA7XX_CM_L4PER2_MCASP3_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0168)
468#define DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET 0x0170
469#define DRA7XX_CM_L4PER_UART5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0170)
470#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL_OFFSET 0x0178
471#define DRA7XX_CM_L4PER2_MCASP5_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0178)
472#define DRA7XX_CM_L4SEC_CLKSTCTRL_OFFSET 0x0180
473#define DRA7XX_CM_L4SEC_STATICDEP_OFFSET 0x0184
474#define DRA7XX_CM_L4SEC_DYNAMICDEP_OFFSET 0x0188
475#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL_OFFSET 0x0190
476#define DRA7XX_CM_L4PER2_MCASP8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0190)
477#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL_OFFSET 0x0198
478#define DRA7XX_CM_L4PER2_MCASP4_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0198)
479#define DRA7XX_CM_L4SEC_AES1_CLKCTRL_OFFSET 0x01a0
480#define DRA7XX_CM_L4SEC_AES1_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a0)
481#define DRA7XX_CM_L4SEC_AES2_CLKCTRL_OFFSET 0x01a8
482#define DRA7XX_CM_L4SEC_AES2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01a8)
483#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL_OFFSET 0x01b0
484#define DRA7XX_CM_L4SEC_DES3DES_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b0)
485#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL_OFFSET 0x01b8
486#define DRA7XX_CM_L4SEC_FPKA_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01b8)
487#define DRA7XX_CM_L4SEC_RNG_CLKCTRL_OFFSET 0x01c0
488#define DRA7XX_CM_L4SEC_RNG_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c0)
489#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL_OFFSET 0x01c8
490#define DRA7XX_CM_L4SEC_SHA2MD51_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01c8)
491#define DRA7XX_CM_L4PER2_UART7_CLKCTRL_OFFSET 0x01d0
492#define DRA7XX_CM_L4PER2_UART7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d0)
493#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL_OFFSET 0x01d8
494#define DRA7XX_CM_L4SEC_DMA_CRYPTO_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01d8)
495#define DRA7XX_CM_L4PER2_UART8_CLKCTRL_OFFSET 0x01e0
496#define DRA7XX_CM_L4PER2_UART8_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e0)
497#define DRA7XX_CM_L4PER2_UART9_CLKCTRL_OFFSET 0x01e8
498#define DRA7XX_CM_L4PER2_UART9_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01e8)
499#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET 0x01f0
500#define DRA7XX_CM_L4PER2_DCAN2_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f0)
501#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL_OFFSET 0x01f8
502#define DRA7XX_CM_L4SEC_SHA2MD52_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x01f8)
503#define DRA7XX_CM_L4PER2_CLKSTCTRL_OFFSET 0x01fc
504#define DRA7XX_CM_L4PER2_DYNAMICDEP_OFFSET 0x0200
505#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL_OFFSET 0x0204
506#define DRA7XX_CM_L4PER2_MCASP6_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0204)
507#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL_OFFSET 0x0208
508#define DRA7XX_CM_L4PER2_MCASP7_CLKCTRL DRA7XX_CM_CORE_REGADDR(DRA7XX_CM_CORE_L4PER_INST, 0x0208)
509#define DRA7XX_CM_L4PER2_STATICDEP_OFFSET 0x020c
510#define DRA7XX_CM_L4PER3_CLKSTCTRL_OFFSET 0x0210
511#define DRA7XX_CM_L4PER3_DYNAMICDEP_OFFSET 0x0214
512
513#endif
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 3656b8009a1c..ff2113ce4014 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -665,6 +665,11 @@ void __init dra7xx_init_early(void)
665 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); 665 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE));
666 omap_prm_base_init(); 666 omap_prm_base_init();
667 omap_cm_base_init(); 667 omap_cm_base_init();
668 omap44xx_prm_init();
669 dra7xx_powerdomains_init();
670 dra7xx_clockdomains_init();
671 dra7xx_hwmod_init();
672 omap_hwmod_init_postsetup();
668} 673}
669#endif 674#endif
670 675
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index b4ecd2c7db8e..d9ee0ff094d4 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -1405,7 +1405,9 @@ static void _enable_sysc(struct omap_hwmod *oh)
1405 (sf & SYSC_HAS_CLOCKACTIVITY)) 1405 (sf & SYSC_HAS_CLOCKACTIVITY))
1406 _set_clockactivity(oh, oh->class->sysc->clockact, &v); 1406 _set_clockactivity(oh, oh->class->sysc->clockact, &v);
1407 1407
1408 _write_sysconfig(v, oh); 1408 /* If the cached value is the same as the new value, skip the write */
1409 if (oh->_sysc_cache != v)
1410 _write_sysconfig(v, oh);
1409 1411
1410 /* 1412 /*
1411 * Set the autoidle bit only after setting the smartidle bit 1413 * Set the autoidle bit only after setting the smartidle bit
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index e1482a9b3bc2..d02acf9308d3 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -751,6 +751,7 @@ extern int omap3xxx_hwmod_init(void);
751extern int omap44xx_hwmod_init(void); 751extern int omap44xx_hwmod_init(void);
752extern int omap54xx_hwmod_init(void); 752extern int omap54xx_hwmod_init(void);
753extern int am33xx_hwmod_init(void); 753extern int am33xx_hwmod_init(void);
754extern int dra7xx_hwmod_init(void);
754 755
755extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois); 756extern int __init omap_hwmod_register_links(struct omap_hwmod_ocp_if **ois);
756 757
diff --git a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
index eb2f3b93b51c..215894f8910d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_33xx_data.c
@@ -325,7 +325,6 @@ static struct omap_hwmod am33xx_adc_tsc_hwmod = {
325 * 325 *
326 * - cEFUSE (doesn't fall under any ocp_if) 326 * - cEFUSE (doesn't fall under any ocp_if)
327 * - clkdiv32k 327 * - clkdiv32k
328 * - debugss
329 * - ocp watch point 328 * - ocp watch point
330 */ 329 */
331#if 0 330#if 0
@@ -369,27 +368,6 @@ static struct omap_hwmod am33xx_clkdiv32k_hwmod = {
369 }, 368 },
370}; 369};
371 370
372/*
373 * 'debugss' class
374 * debug sub system
375 */
376static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
377 .name = "debugss",
378};
379
380static struct omap_hwmod am33xx_debugss_hwmod = {
381 .name = "debugss",
382 .class = &am33xx_debugss_hwmod_class,
383 .clkdm_name = "l3_aon_clkdm",
384 .main_clk = "debugss_ick",
385 .prcm = {
386 .omap4 = {
387 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
388 .modulemode = MODULEMODE_SWCTRL,
389 },
390 },
391};
392
393/* ocpwp */ 371/* ocpwp */
394static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = { 372static struct omap_hwmod_class am33xx_ocpwp_hwmod_class = {
395 .name = "ocpwp", 373 .name = "ocpwp",
@@ -482,6 +460,34 @@ static struct omap_hwmod am33xx_ocmcram_hwmod = {
482 }, 460 },
483}; 461};
484 462
463/*
464 * 'debugss' class
465 * debug sub system
466 */
467static struct omap_hwmod_opt_clk debugss_opt_clks[] = {
468 { .role = "dbg_sysclk", .clk = "dbg_sysclk_ck" },
469 { .role = "dbg_clka", .clk = "dbg_clka_ck" },
470};
471
472static struct omap_hwmod_class am33xx_debugss_hwmod_class = {
473 .name = "debugss",
474};
475
476static struct omap_hwmod am33xx_debugss_hwmod = {
477 .name = "debugss",
478 .class = &am33xx_debugss_hwmod_class,
479 .clkdm_name = "l3_aon_clkdm",
480 .main_clk = "trace_clk_div_ck",
481 .prcm = {
482 .omap4 = {
483 .clkctrl_offs = AM33XX_CM_WKUP_DEBUGSS_CLKCTRL_OFFSET,
484 .modulemode = MODULEMODE_SWCTRL,
485 },
486 },
487 .opt_clks = debugss_opt_clks,
488 .opt_clks_cnt = ARRAY_SIZE(debugss_opt_clks),
489};
490
485/* 'smartreflex' class */ 491/* 'smartreflex' class */
486static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = { 492static struct omap_hwmod_class am33xx_smartreflex_hwmod_class = {
487 .name = "smartreflex", 493 .name = "smartreflex",
@@ -1796,6 +1802,24 @@ static struct omap_hwmod_ocp_if am33xx_l3_main__gfx = {
1796 .user = OCP_USER_MPU | OCP_USER_SDMA, 1802 .user = OCP_USER_MPU | OCP_USER_SDMA,
1797}; 1803};
1798 1804
1805/* l3_main -> debugss */
1806static struct omap_hwmod_addr_space am33xx_debugss_addrs[] = {
1807 {
1808 .pa_start = 0x4b000000,
1809 .pa_end = 0x4b000000 + SZ_16M - 1,
1810 .flags = ADDR_TYPE_RT
1811 },
1812 { }
1813};
1814
1815static struct omap_hwmod_ocp_if am33xx_l3_main__debugss = {
1816 .master = &am33xx_l3_main_hwmod,
1817 .slave = &am33xx_debugss_hwmod,
1818 .clk = "dpll_core_m4_ck",
1819 .addr = am33xx_debugss_addrs,
1820 .user = OCP_USER_MPU,
1821};
1822
1799/* l4 wkup -> smartreflex0 */ 1823/* l4 wkup -> smartreflex0 */
1800static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = { 1824static struct omap_hwmod_ocp_if am33xx_l4_wkup__smartreflex0 = {
1801 .master = &am33xx_l4_wkup_hwmod, 1825 .master = &am33xx_l4_wkup_hwmod,
@@ -2470,6 +2494,7 @@ static struct omap_hwmod_ocp_if *am33xx_hwmod_ocp_ifs[] __initdata = {
2470 &am33xx_pruss__l3_main, 2494 &am33xx_pruss__l3_main,
2471 &am33xx_wkup_m3__l4_wkup, 2495 &am33xx_wkup_m3__l4_wkup,
2472 &am33xx_gfx__l3_main, 2496 &am33xx_gfx__l3_main,
2497 &am33xx_l3_main__debugss,
2473 &am33xx_l4_wkup__wkup_m3, 2498 &am33xx_l4_wkup__wkup_m3,
2474 &am33xx_l4_wkup__control, 2499 &am33xx_l4_wkup__control,
2475 &am33xx_l4_wkup__smartreflex0, 2500 &am33xx_l4_wkup__smartreflex0,
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index b4d04748576b..cde415570e04 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -740,6 +740,39 @@ static struct omap_hwmod omap54xx_kbd_hwmod = {
740}; 740};
741 741
742/* 742/*
743 * 'mailbox' class
744 * mailbox module allowing communication between the on-chip processors using a
745 * queued mailbox-interrupt mechanism.
746 */
747
748static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
749 .rev_offs = 0x0000,
750 .sysc_offs = 0x0010,
751 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
752 SYSC_HAS_SOFTRESET),
753 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
754 .sysc_fields = &omap_hwmod_sysc_type2,
755};
756
757static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
758 .name = "mailbox",
759 .sysc = &omap54xx_mailbox_sysc,
760};
761
762/* mailbox */
763static struct omap_hwmod omap54xx_mailbox_hwmod = {
764 .name = "mailbox",
765 .class = &omap54xx_mailbox_hwmod_class,
766 .clkdm_name = "l4cfg_clkdm",
767 .prcm = {
768 .omap4 = {
769 .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
770 .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
771 },
772 },
773};
774
775/*
743 * 'mcbsp' class 776 * 'mcbsp' class
744 * multi channel buffered serial port controller 777 * multi channel buffered serial port controller
745 */ 778 */
@@ -1807,6 +1840,14 @@ static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
1807 .user = OCP_USER_MPU | OCP_USER_SDMA, 1840 .user = OCP_USER_MPU | OCP_USER_SDMA,
1808}; 1841};
1809 1842
1843/* l4_cfg -> mailbox */
1844static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
1845 .master = &omap54xx_l4_cfg_hwmod,
1846 .slave = &omap54xx_mailbox_hwmod,
1847 .clk = "l4_root_clk_div",
1848 .user = OCP_USER_MPU | OCP_USER_SDMA,
1849};
1850
1810/* l4_abe -> mcbsp1 */ 1851/* l4_abe -> mcbsp1 */
1811static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = { 1852static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
1812 .master = &omap54xx_l4_abe_hwmod, 1853 .master = &omap54xx_l4_abe_hwmod,
@@ -2107,6 +2148,7 @@ static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2107 &omap54xx_l4_per__i2c4, 2148 &omap54xx_l4_per__i2c4,
2108 &omap54xx_l4_per__i2c5, 2149 &omap54xx_l4_per__i2c5,
2109 &omap54xx_l4_wkup__kbd, 2150 &omap54xx_l4_wkup__kbd,
2151 &omap54xx_l4_cfg__mailbox,
2110 &omap54xx_l4_abe__mcbsp1, 2152 &omap54xx_l4_abe__mcbsp1,
2111 &omap54xx_l4_abe__mcbsp2, 2153 &omap54xx_l4_abe__mcbsp2,
2112 &omap54xx_l4_abe__mcbsp3, 2154 &omap54xx_l4_abe__mcbsp3,
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
new file mode 100644
index 000000000000..db32d5380b11
--- /dev/null
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -0,0 +1,2724 @@
1/*
2 * Hardware modules present on the DRA7xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
22#include <linux/power/smartreflex.h>
23#include <linux/i2c-omap.h>
24
25#include <linux/omap-dma.h>
26#include <linux/platform_data/spi-omap2-mcspi.h>
27#include <linux/platform_data/asoc-ti-mcbsp.h>
28#include <plat/dmtimer.h>
29
30#include "omap_hwmod.h"
31#include "omap_hwmod_common_data.h"
32#include "cm1_7xx.h"
33#include "cm2_7xx.h"
34#include "prm7xx.h"
35#include "i2c.h"
36#include "mmc.h"
37#include "wd_timer.h"
38
39/* Base offset for all DRA7XX interrupts external to MPUSS */
40#define DRA7XX_IRQ_GIC_START 32
41
42/* Base offset for all DRA7XX dma requests */
43#define DRA7XX_DMA_REQ_START 1
44
45
46/*
47 * IP blocks
48 */
49
50/*
51 * 'l3' class
52 * instance(s): l3_instr, l3_main_1, l3_main_2
53 */
54static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
55 .name = "l3",
56};
57
58/* l3_instr */
59static struct omap_hwmod dra7xx_l3_instr_hwmod = {
60 .name = "l3_instr",
61 .class = &dra7xx_l3_hwmod_class,
62 .clkdm_name = "l3instr_clkdm",
63 .prcm = {
64 .omap4 = {
65 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
66 .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
67 .modulemode = MODULEMODE_HWCTRL,
68 },
69 },
70};
71
72/* l3_main_1 */
73static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
74 .name = "l3_main_1",
75 .class = &dra7xx_l3_hwmod_class,
76 .clkdm_name = "l3main1_clkdm",
77 .prcm = {
78 .omap4 = {
79 .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
80 .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
81 },
82 },
83};
84
85/* l3_main_2 */
86static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
87 .name = "l3_main_2",
88 .class = &dra7xx_l3_hwmod_class,
89 .clkdm_name = "l3instr_clkdm",
90 .prcm = {
91 .omap4 = {
92 .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
93 .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
94 .modulemode = MODULEMODE_HWCTRL,
95 },
96 },
97};
98
99/*
100 * 'l4' class
101 * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
102 */
103static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
104 .name = "l4",
105};
106
107/* l4_cfg */
108static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
109 .name = "l4_cfg",
110 .class = &dra7xx_l4_hwmod_class,
111 .clkdm_name = "l4cfg_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
115 .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
116 },
117 },
118};
119
120/* l4_per1 */
121static struct omap_hwmod dra7xx_l4_per1_hwmod = {
122 .name = "l4_per1",
123 .class = &dra7xx_l4_hwmod_class,
124 .clkdm_name = "l4per_clkdm",
125 .prcm = {
126 .omap4 = {
127 .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
128 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
129 },
130 },
131};
132
133/* l4_per2 */
134static struct omap_hwmod dra7xx_l4_per2_hwmod = {
135 .name = "l4_per2",
136 .class = &dra7xx_l4_hwmod_class,
137 .clkdm_name = "l4per2_clkdm",
138 .prcm = {
139 .omap4 = {
140 .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
141 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
142 },
143 },
144};
145
146/* l4_per3 */
147static struct omap_hwmod dra7xx_l4_per3_hwmod = {
148 .name = "l4_per3",
149 .class = &dra7xx_l4_hwmod_class,
150 .clkdm_name = "l4per3_clkdm",
151 .prcm = {
152 .omap4 = {
153 .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
154 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
155 },
156 },
157};
158
159/* l4_wkup */
160static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
161 .name = "l4_wkup",
162 .class = &dra7xx_l4_hwmod_class,
163 .clkdm_name = "wkupaon_clkdm",
164 .prcm = {
165 .omap4 = {
166 .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
167 .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
168 },
169 },
170};
171
172/*
173 * 'atl' class
174 *
175 */
176
177static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
178 .name = "atl",
179};
180
181/* atl */
182static struct omap_hwmod dra7xx_atl_hwmod = {
183 .name = "atl",
184 .class = &dra7xx_atl_hwmod_class,
185 .clkdm_name = "atl_clkdm",
186 .main_clk = "atl_gfclk_mux",
187 .prcm = {
188 .omap4 = {
189 .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
190 .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
191 .modulemode = MODULEMODE_SWCTRL,
192 },
193 },
194};
195
196/*
197 * 'bb2d' class
198 *
199 */
200
201static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
202 .name = "bb2d",
203};
204
205/* bb2d */
206static struct omap_hwmod dra7xx_bb2d_hwmod = {
207 .name = "bb2d",
208 .class = &dra7xx_bb2d_hwmod_class,
209 .clkdm_name = "dss_clkdm",
210 .main_clk = "dpll_core_h24x2_ck",
211 .prcm = {
212 .omap4 = {
213 .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
214 .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
215 .modulemode = MODULEMODE_SWCTRL,
216 },
217 },
218};
219
220/*
221 * 'counter' class
222 *
223 */
224
225static struct omap_hwmod_class_sysconfig dra7xx_counter_sysc = {
226 .rev_offs = 0x0000,
227 .sysc_offs = 0x0010,
228 .sysc_flags = SYSC_HAS_SIDLEMODE,
229 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
230 SIDLE_SMART_WKUP),
231 .sysc_fields = &omap_hwmod_sysc_type1,
232};
233
234static struct omap_hwmod_class dra7xx_counter_hwmod_class = {
235 .name = "counter",
236 .sysc = &dra7xx_counter_sysc,
237};
238
239/* counter_32k */
240static struct omap_hwmod dra7xx_counter_32k_hwmod = {
241 .name = "counter_32k",
242 .class = &dra7xx_counter_hwmod_class,
243 .clkdm_name = "wkupaon_clkdm",
244 .flags = HWMOD_SWSUP_SIDLE,
245 .main_clk = "wkupaon_iclk_mux",
246 .prcm = {
247 .omap4 = {
248 .clkctrl_offs = DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
249 .context_offs = DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
250 },
251 },
252};
253
254/*
255 * 'ctrl_module' class
256 *
257 */
258
259static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
260 .name = "ctrl_module",
261};
262
263/* ctrl_module_wkup */
264static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
265 .name = "ctrl_module_wkup",
266 .class = &dra7xx_ctrl_module_hwmod_class,
267 .clkdm_name = "wkupaon_clkdm",
268 .prcm = {
269 .omap4 = {
270 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
271 },
272 },
273};
274
275/*
276 * 'dcan' class
277 *
278 */
279
280static struct omap_hwmod_class dra7xx_dcan_hwmod_class = {
281 .name = "dcan",
282};
283
284/* dcan1 */
285static struct omap_hwmod dra7xx_dcan1_hwmod = {
286 .name = "dcan1",
287 .class = &dra7xx_dcan_hwmod_class,
288 .clkdm_name = "wkupaon_clkdm",
289 .main_clk = "dcan1_sys_clk_mux",
290 .prcm = {
291 .omap4 = {
292 .clkctrl_offs = DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET,
293 .context_offs = DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET,
294 .modulemode = MODULEMODE_SWCTRL,
295 },
296 },
297};
298
299/* dcan2 */
300static struct omap_hwmod dra7xx_dcan2_hwmod = {
301 .name = "dcan2",
302 .class = &dra7xx_dcan_hwmod_class,
303 .clkdm_name = "l4per2_clkdm",
304 .main_clk = "sys_clkin1",
305 .prcm = {
306 .omap4 = {
307 .clkctrl_offs = DRA7XX_CM_L4PER2_DCAN2_CLKCTRL_OFFSET,
308 .context_offs = DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET,
309 .modulemode = MODULEMODE_SWCTRL,
310 },
311 },
312};
313
314/*
315 * 'dma' class
316 *
317 */
318
319static struct omap_hwmod_class_sysconfig dra7xx_dma_sysc = {
320 .rev_offs = 0x0000,
321 .sysc_offs = 0x002c,
322 .syss_offs = 0x0028,
323 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
324 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
325 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
326 SYSS_HAS_RESET_STATUS),
327 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
328 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
329 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
330 .sysc_fields = &omap_hwmod_sysc_type1,
331};
332
333static struct omap_hwmod_class dra7xx_dma_hwmod_class = {
334 .name = "dma",
335 .sysc = &dra7xx_dma_sysc,
336};
337
338/* dma dev_attr */
339static struct omap_dma_dev_attr dma_dev_attr = {
340 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
341 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
342 .lch_count = 32,
343};
344
345/* dma_system */
346static struct omap_hwmod_irq_info dra7xx_dma_system_irqs[] = {
347 { .name = "0", .irq = 12 + DRA7XX_IRQ_GIC_START },
348 { .name = "1", .irq = 13 + DRA7XX_IRQ_GIC_START },
349 { .name = "2", .irq = 14 + DRA7XX_IRQ_GIC_START },
350 { .name = "3", .irq = 15 + DRA7XX_IRQ_GIC_START },
351 { .irq = -1 }
352};
353
354static struct omap_hwmod dra7xx_dma_system_hwmod = {
355 .name = "dma_system",
356 .class = &dra7xx_dma_hwmod_class,
357 .clkdm_name = "dma_clkdm",
358 .mpu_irqs = dra7xx_dma_system_irqs,
359 .main_clk = "l3_iclk_div",
360 .prcm = {
361 .omap4 = {
362 .clkctrl_offs = DRA7XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
363 .context_offs = DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
364 },
365 },
366 .dev_attr = &dma_dev_attr,
367};
368
369/*
370 * 'dss' class
371 *
372 */
373
374static struct omap_hwmod_class_sysconfig dra7xx_dss_sysc = {
375 .rev_offs = 0x0000,
376 .syss_offs = 0x0014,
377 .sysc_flags = SYSS_HAS_RESET_STATUS,
378};
379
380static struct omap_hwmod_class dra7xx_dss_hwmod_class = {
381 .name = "dss",
382 .sysc = &dra7xx_dss_sysc,
383 .reset = omap_dss_reset,
384};
385
386/* dss */
387static struct omap_hwmod_dma_info dra7xx_dss_sdma_reqs[] = {
388 { .dma_req = 75 + DRA7XX_DMA_REQ_START },
389 { .dma_req = -1 }
390};
391
392static struct omap_hwmod_opt_clk dss_opt_clks[] = {
393 { .role = "dss_clk", .clk = "dss_dss_clk" },
394 { .role = "hdmi_phy_clk", .clk = "dss_48mhz_clk" },
395 { .role = "32khz_clk", .clk = "dss_32khz_clk" },
396 { .role = "video2_clk", .clk = "dss_video2_clk" },
397 { .role = "video1_clk", .clk = "dss_video1_clk" },
398 { .role = "hdmi_clk", .clk = "dss_hdmi_clk" },
399};
400
401static struct omap_hwmod dra7xx_dss_hwmod = {
402 .name = "dss_core",
403 .class = &dra7xx_dss_hwmod_class,
404 .clkdm_name = "dss_clkdm",
405 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
406 .sdma_reqs = dra7xx_dss_sdma_reqs,
407 .main_clk = "dss_dss_clk",
408 .prcm = {
409 .omap4 = {
410 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
411 .context_offs = DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET,
412 .modulemode = MODULEMODE_SWCTRL,
413 },
414 },
415 .opt_clks = dss_opt_clks,
416 .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks),
417};
418
419/*
420 * 'dispc' class
421 * display controller
422 */
423
424static struct omap_hwmod_class_sysconfig dra7xx_dispc_sysc = {
425 .rev_offs = 0x0000,
426 .sysc_offs = 0x0010,
427 .syss_offs = 0x0014,
428 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
429 SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE |
430 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
431 SYSS_HAS_RESET_STATUS),
432 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
433 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
434 .sysc_fields = &omap_hwmod_sysc_type1,
435};
436
437static struct omap_hwmod_class dra7xx_dispc_hwmod_class = {
438 .name = "dispc",
439 .sysc = &dra7xx_dispc_sysc,
440};
441
442/* dss_dispc */
443/* dss_dispc dev_attr */
444static struct omap_dss_dispc_dev_attr dss_dispc_dev_attr = {
445 .has_framedonetv_irq = 1,
446 .manager_count = 4,
447};
448
449static struct omap_hwmod dra7xx_dss_dispc_hwmod = {
450 .name = "dss_dispc",
451 .class = &dra7xx_dispc_hwmod_class,
452 .clkdm_name = "dss_clkdm",
453 .main_clk = "dss_dss_clk",
454 .prcm = {
455 .omap4 = {
456 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
457 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
458 },
459 },
460 .dev_attr = &dss_dispc_dev_attr,
461};
462
463/*
464 * 'hdmi' class
465 * hdmi controller
466 */
467
468static struct omap_hwmod_class_sysconfig dra7xx_hdmi_sysc = {
469 .rev_offs = 0x0000,
470 .sysc_offs = 0x0010,
471 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
472 SYSC_HAS_SOFTRESET),
473 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
474 SIDLE_SMART_WKUP),
475 .sysc_fields = &omap_hwmod_sysc_type2,
476};
477
478static struct omap_hwmod_class dra7xx_hdmi_hwmod_class = {
479 .name = "hdmi",
480 .sysc = &dra7xx_hdmi_sysc,
481};
482
483/* dss_hdmi */
484
485static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = {
486 { .role = "sys_clk", .clk = "dss_hdmi_clk" },
487};
488
489static struct omap_hwmod dra7xx_dss_hdmi_hwmod = {
490 .name = "dss_hdmi",
491 .class = &dra7xx_hdmi_hwmod_class,
492 .clkdm_name = "dss_clkdm",
493 .main_clk = "dss_48mhz_clk",
494 .prcm = {
495 .omap4 = {
496 .clkctrl_offs = DRA7XX_CM_DSS_DSS_CLKCTRL_OFFSET,
497 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
498 },
499 },
500 .opt_clks = dss_hdmi_opt_clks,
501 .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks),
502};
503
504/*
505 * 'elm' class
506 *
507 */
508
509static struct omap_hwmod_class_sysconfig dra7xx_elm_sysc = {
510 .rev_offs = 0x0000,
511 .sysc_offs = 0x0010,
512 .syss_offs = 0x0014,
513 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
514 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
515 SYSS_HAS_RESET_STATUS),
516 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
517 SIDLE_SMART_WKUP),
518 .sysc_fields = &omap_hwmod_sysc_type1,
519};
520
521static struct omap_hwmod_class dra7xx_elm_hwmod_class = {
522 .name = "elm",
523 .sysc = &dra7xx_elm_sysc,
524};
525
526/* elm */
527
528static struct omap_hwmod dra7xx_elm_hwmod = {
529 .name = "elm",
530 .class = &dra7xx_elm_hwmod_class,
531 .clkdm_name = "l4per_clkdm",
532 .main_clk = "l3_iclk_div",
533 .prcm = {
534 .omap4 = {
535 .clkctrl_offs = DRA7XX_CM_L4PER_ELM_CLKCTRL_OFFSET,
536 .context_offs = DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET,
537 },
538 },
539};
540
541/*
542 * 'gpio' class
543 *
544 */
545
546static struct omap_hwmod_class_sysconfig dra7xx_gpio_sysc = {
547 .rev_offs = 0x0000,
548 .sysc_offs = 0x0010,
549 .syss_offs = 0x0114,
550 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
551 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
552 SYSS_HAS_RESET_STATUS),
553 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
554 SIDLE_SMART_WKUP),
555 .sysc_fields = &omap_hwmod_sysc_type1,
556};
557
558static struct omap_hwmod_class dra7xx_gpio_hwmod_class = {
559 .name = "gpio",
560 .sysc = &dra7xx_gpio_sysc,
561 .rev = 2,
562};
563
564/* gpio dev_attr */
565static struct omap_gpio_dev_attr gpio_dev_attr = {
566 .bank_width = 32,
567 .dbck_flag = true,
568};
569
570/* gpio1 */
571static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
572 { .role = "dbclk", .clk = "gpio1_dbclk" },
573};
574
575static struct omap_hwmod dra7xx_gpio1_hwmod = {
576 .name = "gpio1",
577 .class = &dra7xx_gpio_hwmod_class,
578 .clkdm_name = "wkupaon_clkdm",
579 .main_clk = "wkupaon_iclk_mux",
580 .prcm = {
581 .omap4 = {
582 .clkctrl_offs = DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
583 .context_offs = DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
584 .modulemode = MODULEMODE_HWCTRL,
585 },
586 },
587 .opt_clks = gpio1_opt_clks,
588 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
589 .dev_attr = &gpio_dev_attr,
590};
591
592/* gpio2 */
593static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
594 { .role = "dbclk", .clk = "gpio2_dbclk" },
595};
596
597static struct omap_hwmod dra7xx_gpio2_hwmod = {
598 .name = "gpio2",
599 .class = &dra7xx_gpio_hwmod_class,
600 .clkdm_name = "l4per_clkdm",
601 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
602 .main_clk = "l3_iclk_div",
603 .prcm = {
604 .omap4 = {
605 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
606 .context_offs = DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
607 .modulemode = MODULEMODE_HWCTRL,
608 },
609 },
610 .opt_clks = gpio2_opt_clks,
611 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
612 .dev_attr = &gpio_dev_attr,
613};
614
615/* gpio3 */
616static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
617 { .role = "dbclk", .clk = "gpio3_dbclk" },
618};
619
620static struct omap_hwmod dra7xx_gpio3_hwmod = {
621 .name = "gpio3",
622 .class = &dra7xx_gpio_hwmod_class,
623 .clkdm_name = "l4per_clkdm",
624 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
625 .main_clk = "l3_iclk_div",
626 .prcm = {
627 .omap4 = {
628 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
629 .context_offs = DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
630 .modulemode = MODULEMODE_HWCTRL,
631 },
632 },
633 .opt_clks = gpio3_opt_clks,
634 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
635 .dev_attr = &gpio_dev_attr,
636};
637
638/* gpio4 */
639static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
640 { .role = "dbclk", .clk = "gpio4_dbclk" },
641};
642
643static struct omap_hwmod dra7xx_gpio4_hwmod = {
644 .name = "gpio4",
645 .class = &dra7xx_gpio_hwmod_class,
646 .clkdm_name = "l4per_clkdm",
647 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
648 .main_clk = "l3_iclk_div",
649 .prcm = {
650 .omap4 = {
651 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
652 .context_offs = DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
653 .modulemode = MODULEMODE_HWCTRL,
654 },
655 },
656 .opt_clks = gpio4_opt_clks,
657 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
658 .dev_attr = &gpio_dev_attr,
659};
660
661/* gpio5 */
662static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
663 { .role = "dbclk", .clk = "gpio5_dbclk" },
664};
665
666static struct omap_hwmod dra7xx_gpio5_hwmod = {
667 .name = "gpio5",
668 .class = &dra7xx_gpio_hwmod_class,
669 .clkdm_name = "l4per_clkdm",
670 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
671 .main_clk = "l3_iclk_div",
672 .prcm = {
673 .omap4 = {
674 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
675 .context_offs = DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
676 .modulemode = MODULEMODE_HWCTRL,
677 },
678 },
679 .opt_clks = gpio5_opt_clks,
680 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
681 .dev_attr = &gpio_dev_attr,
682};
683
684/* gpio6 */
685static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
686 { .role = "dbclk", .clk = "gpio6_dbclk" },
687};
688
689static struct omap_hwmod dra7xx_gpio6_hwmod = {
690 .name = "gpio6",
691 .class = &dra7xx_gpio_hwmod_class,
692 .clkdm_name = "l4per_clkdm",
693 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
694 .main_clk = "l3_iclk_div",
695 .prcm = {
696 .omap4 = {
697 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
698 .context_offs = DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
699 .modulemode = MODULEMODE_HWCTRL,
700 },
701 },
702 .opt_clks = gpio6_opt_clks,
703 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
704 .dev_attr = &gpio_dev_attr,
705};
706
707/* gpio7 */
708static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
709 { .role = "dbclk", .clk = "gpio7_dbclk" },
710};
711
712static struct omap_hwmod dra7xx_gpio7_hwmod = {
713 .name = "gpio7",
714 .class = &dra7xx_gpio_hwmod_class,
715 .clkdm_name = "l4per_clkdm",
716 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
717 .main_clk = "l3_iclk_div",
718 .prcm = {
719 .omap4 = {
720 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
721 .context_offs = DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
722 .modulemode = MODULEMODE_HWCTRL,
723 },
724 },
725 .opt_clks = gpio7_opt_clks,
726 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
727 .dev_attr = &gpio_dev_attr,
728};
729
730/* gpio8 */
731static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
732 { .role = "dbclk", .clk = "gpio8_dbclk" },
733};
734
735static struct omap_hwmod dra7xx_gpio8_hwmod = {
736 .name = "gpio8",
737 .class = &dra7xx_gpio_hwmod_class,
738 .clkdm_name = "l4per_clkdm",
739 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
740 .main_clk = "l3_iclk_div",
741 .prcm = {
742 .omap4 = {
743 .clkctrl_offs = DRA7XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
744 .context_offs = DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
745 .modulemode = MODULEMODE_HWCTRL,
746 },
747 },
748 .opt_clks = gpio8_opt_clks,
749 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
750 .dev_attr = &gpio_dev_attr,
751};
752
753/*
754 * 'gpmc' class
755 *
756 */
757
758static struct omap_hwmod_class_sysconfig dra7xx_gpmc_sysc = {
759 .rev_offs = 0x0000,
760 .sysc_offs = 0x0010,
761 .syss_offs = 0x0014,
762 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
763 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
764 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
765 SIDLE_SMART_WKUP),
766 .sysc_fields = &omap_hwmod_sysc_type1,
767};
768
769static struct omap_hwmod_class dra7xx_gpmc_hwmod_class = {
770 .name = "gpmc",
771 .sysc = &dra7xx_gpmc_sysc,
772};
773
774/* gpmc */
775
776static struct omap_hwmod dra7xx_gpmc_hwmod = {
777 .name = "gpmc",
778 .class = &dra7xx_gpmc_hwmod_class,
779 .clkdm_name = "l3main1_clkdm",
780 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
781 .main_clk = "l3_iclk_div",
782 .prcm = {
783 .omap4 = {
784 .clkctrl_offs = DRA7XX_CM_L3MAIN1_GPMC_CLKCTRL_OFFSET,
785 .context_offs = DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET,
786 .modulemode = MODULEMODE_HWCTRL,
787 },
788 },
789};
790
791/*
792 * 'hdq1w' class
793 *
794 */
795
796static struct omap_hwmod_class_sysconfig dra7xx_hdq1w_sysc = {
797 .rev_offs = 0x0000,
798 .sysc_offs = 0x0014,
799 .syss_offs = 0x0018,
800 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET |
801 SYSS_HAS_RESET_STATUS),
802 .sysc_fields = &omap_hwmod_sysc_type1,
803};
804
805static struct omap_hwmod_class dra7xx_hdq1w_hwmod_class = {
806 .name = "hdq1w",
807 .sysc = &dra7xx_hdq1w_sysc,
808};
809
810/* hdq1w */
811
812static struct omap_hwmod dra7xx_hdq1w_hwmod = {
813 .name = "hdq1w",
814 .class = &dra7xx_hdq1w_hwmod_class,
815 .clkdm_name = "l4per_clkdm",
816 .flags = HWMOD_INIT_NO_RESET,
817 .main_clk = "func_12m_fclk",
818 .prcm = {
819 .omap4 = {
820 .clkctrl_offs = DRA7XX_CM_L4PER_HDQ1W_CLKCTRL_OFFSET,
821 .context_offs = DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET,
822 .modulemode = MODULEMODE_SWCTRL,
823 },
824 },
825};
826
827/*
828 * 'i2c' class
829 *
830 */
831
832static struct omap_hwmod_class_sysconfig dra7xx_i2c_sysc = {
833 .sysc_offs = 0x0010,
834 .syss_offs = 0x0090,
835 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
836 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
837 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
838 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
839 SIDLE_SMART_WKUP),
840 .clockact = CLOCKACT_TEST_ICLK,
841 .sysc_fields = &omap_hwmod_sysc_type1,
842};
843
844static struct omap_hwmod_class dra7xx_i2c_hwmod_class = {
845 .name = "i2c",
846 .sysc = &dra7xx_i2c_sysc,
847 .reset = &omap_i2c_reset,
848 .rev = OMAP_I2C_IP_VERSION_2,
849};
850
851/* i2c dev_attr */
852static struct omap_i2c_dev_attr i2c_dev_attr = {
853 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
854};
855
856/* i2c1 */
857static struct omap_hwmod dra7xx_i2c1_hwmod = {
858 .name = "i2c1",
859 .class = &dra7xx_i2c_hwmod_class,
860 .clkdm_name = "l4per_clkdm",
861 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
862 .main_clk = "func_96m_fclk",
863 .prcm = {
864 .omap4 = {
865 .clkctrl_offs = DRA7XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
866 .context_offs = DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
867 .modulemode = MODULEMODE_SWCTRL,
868 },
869 },
870 .dev_attr = &i2c_dev_attr,
871};
872
873/* i2c2 */
874static struct omap_hwmod dra7xx_i2c2_hwmod = {
875 .name = "i2c2",
876 .class = &dra7xx_i2c_hwmod_class,
877 .clkdm_name = "l4per_clkdm",
878 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
879 .main_clk = "func_96m_fclk",
880 .prcm = {
881 .omap4 = {
882 .clkctrl_offs = DRA7XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
883 .context_offs = DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
884 .modulemode = MODULEMODE_SWCTRL,
885 },
886 },
887 .dev_attr = &i2c_dev_attr,
888};
889
890/* i2c3 */
891static struct omap_hwmod dra7xx_i2c3_hwmod = {
892 .name = "i2c3",
893 .class = &dra7xx_i2c_hwmod_class,
894 .clkdm_name = "l4per_clkdm",
895 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
896 .main_clk = "func_96m_fclk",
897 .prcm = {
898 .omap4 = {
899 .clkctrl_offs = DRA7XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
900 .context_offs = DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
901 .modulemode = MODULEMODE_SWCTRL,
902 },
903 },
904 .dev_attr = &i2c_dev_attr,
905};
906
907/* i2c4 */
908static struct omap_hwmod dra7xx_i2c4_hwmod = {
909 .name = "i2c4",
910 .class = &dra7xx_i2c_hwmod_class,
911 .clkdm_name = "l4per_clkdm",
912 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
913 .main_clk = "func_96m_fclk",
914 .prcm = {
915 .omap4 = {
916 .clkctrl_offs = DRA7XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
917 .context_offs = DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
918 .modulemode = MODULEMODE_SWCTRL,
919 },
920 },
921 .dev_attr = &i2c_dev_attr,
922};
923
924/* i2c5 */
925static struct omap_hwmod dra7xx_i2c5_hwmod = {
926 .name = "i2c5",
927 .class = &dra7xx_i2c_hwmod_class,
928 .clkdm_name = "ipu_clkdm",
929 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
930 .main_clk = "func_96m_fclk",
931 .prcm = {
932 .omap4 = {
933 .clkctrl_offs = DRA7XX_CM_IPU_I2C5_CLKCTRL_OFFSET,
934 .context_offs = DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET,
935 .modulemode = MODULEMODE_SWCTRL,
936 },
937 },
938 .dev_attr = &i2c_dev_attr,
939};
940
941/*
942 * 'mcspi' class
943 *
944 */
945
946static struct omap_hwmod_class_sysconfig dra7xx_mcspi_sysc = {
947 .rev_offs = 0x0000,
948 .sysc_offs = 0x0010,
949 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
950 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
951 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
952 SIDLE_SMART_WKUP),
953 .sysc_fields = &omap_hwmod_sysc_type2,
954};
955
956static struct omap_hwmod_class dra7xx_mcspi_hwmod_class = {
957 .name = "mcspi",
958 .sysc = &dra7xx_mcspi_sysc,
959 .rev = OMAP4_MCSPI_REV,
960};
961
962/* mcspi1 */
963/* mcspi1 dev_attr */
964static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
965 .num_chipselect = 4,
966};
967
968static struct omap_hwmod dra7xx_mcspi1_hwmod = {
969 .name = "mcspi1",
970 .class = &dra7xx_mcspi_hwmod_class,
971 .clkdm_name = "l4per_clkdm",
972 .main_clk = "func_48m_fclk",
973 .prcm = {
974 .omap4 = {
975 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
976 .context_offs = DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
977 .modulemode = MODULEMODE_SWCTRL,
978 },
979 },
980 .dev_attr = &mcspi1_dev_attr,
981};
982
983/* mcspi2 */
984/* mcspi2 dev_attr */
985static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
986 .num_chipselect = 2,
987};
988
989static struct omap_hwmod dra7xx_mcspi2_hwmod = {
990 .name = "mcspi2",
991 .class = &dra7xx_mcspi_hwmod_class,
992 .clkdm_name = "l4per_clkdm",
993 .main_clk = "func_48m_fclk",
994 .prcm = {
995 .omap4 = {
996 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
997 .context_offs = DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
998 .modulemode = MODULEMODE_SWCTRL,
999 },
1000 },
1001 .dev_attr = &mcspi2_dev_attr,
1002};
1003
1004/* mcspi3 */
1005/* mcspi3 dev_attr */
1006static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
1007 .num_chipselect = 2,
1008};
1009
1010static struct omap_hwmod dra7xx_mcspi3_hwmod = {
1011 .name = "mcspi3",
1012 .class = &dra7xx_mcspi_hwmod_class,
1013 .clkdm_name = "l4per_clkdm",
1014 .main_clk = "func_48m_fclk",
1015 .prcm = {
1016 .omap4 = {
1017 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
1018 .context_offs = DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
1019 .modulemode = MODULEMODE_SWCTRL,
1020 },
1021 },
1022 .dev_attr = &mcspi3_dev_attr,
1023};
1024
1025/* mcspi4 */
1026/* mcspi4 dev_attr */
1027static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
1028 .num_chipselect = 1,
1029};
1030
1031static struct omap_hwmod dra7xx_mcspi4_hwmod = {
1032 .name = "mcspi4",
1033 .class = &dra7xx_mcspi_hwmod_class,
1034 .clkdm_name = "l4per_clkdm",
1035 .main_clk = "func_48m_fclk",
1036 .prcm = {
1037 .omap4 = {
1038 .clkctrl_offs = DRA7XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1039 .context_offs = DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1040 .modulemode = MODULEMODE_SWCTRL,
1041 },
1042 },
1043 .dev_attr = &mcspi4_dev_attr,
1044};
1045
1046/*
1047 * 'mmc' class
1048 *
1049 */
1050
1051static struct omap_hwmod_class_sysconfig dra7xx_mmc_sysc = {
1052 .rev_offs = 0x0000,
1053 .sysc_offs = 0x0010,
1054 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1055 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1056 SYSC_HAS_SOFTRESET),
1057 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1058 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1059 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1060 .sysc_fields = &omap_hwmod_sysc_type2,
1061};
1062
1063static struct omap_hwmod_class dra7xx_mmc_hwmod_class = {
1064 .name = "mmc",
1065 .sysc = &dra7xx_mmc_sysc,
1066};
1067
1068/* mmc1 */
1069static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1070 { .role = "clk32k", .clk = "mmc1_clk32k" },
1071};
1072
1073/* mmc1 dev_attr */
1074static struct omap_mmc_dev_attr mmc1_dev_attr = {
1075 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1076};
1077
1078static struct omap_hwmod dra7xx_mmc1_hwmod = {
1079 .name = "mmc1",
1080 .class = &dra7xx_mmc_hwmod_class,
1081 .clkdm_name = "l3init_clkdm",
1082 .main_clk = "mmc1_fclk_div",
1083 .prcm = {
1084 .omap4 = {
1085 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1086 .context_offs = DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1087 .modulemode = MODULEMODE_SWCTRL,
1088 },
1089 },
1090 .opt_clks = mmc1_opt_clks,
1091 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1092 .dev_attr = &mmc1_dev_attr,
1093};
1094
1095/* mmc2 */
1096static struct omap_hwmod_opt_clk mmc2_opt_clks[] = {
1097 { .role = "clk32k", .clk = "mmc2_clk32k" },
1098};
1099
1100static struct omap_hwmod dra7xx_mmc2_hwmod = {
1101 .name = "mmc2",
1102 .class = &dra7xx_mmc_hwmod_class,
1103 .clkdm_name = "l3init_clkdm",
1104 .main_clk = "mmc2_fclk_div",
1105 .prcm = {
1106 .omap4 = {
1107 .clkctrl_offs = DRA7XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1108 .context_offs = DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1109 .modulemode = MODULEMODE_SWCTRL,
1110 },
1111 },
1112 .opt_clks = mmc2_opt_clks,
1113 .opt_clks_cnt = ARRAY_SIZE(mmc2_opt_clks),
1114};
1115
1116/* mmc3 */
1117static struct omap_hwmod_opt_clk mmc3_opt_clks[] = {
1118 { .role = "clk32k", .clk = "mmc3_clk32k" },
1119};
1120
1121static struct omap_hwmod dra7xx_mmc3_hwmod = {
1122 .name = "mmc3",
1123 .class = &dra7xx_mmc_hwmod_class,
1124 .clkdm_name = "l4per_clkdm",
1125 .main_clk = "mmc3_gfclk_div",
1126 .prcm = {
1127 .omap4 = {
1128 .clkctrl_offs = DRA7XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1129 .context_offs = DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1130 .modulemode = MODULEMODE_SWCTRL,
1131 },
1132 },
1133 .opt_clks = mmc3_opt_clks,
1134 .opt_clks_cnt = ARRAY_SIZE(mmc3_opt_clks),
1135};
1136
1137/* mmc4 */
1138static struct omap_hwmod_opt_clk mmc4_opt_clks[] = {
1139 { .role = "clk32k", .clk = "mmc4_clk32k" },
1140};
1141
1142static struct omap_hwmod dra7xx_mmc4_hwmod = {
1143 .name = "mmc4",
1144 .class = &dra7xx_mmc_hwmod_class,
1145 .clkdm_name = "l4per_clkdm",
1146 .main_clk = "mmc4_gfclk_div",
1147 .prcm = {
1148 .omap4 = {
1149 .clkctrl_offs = DRA7XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1150 .context_offs = DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1151 .modulemode = MODULEMODE_SWCTRL,
1152 },
1153 },
1154 .opt_clks = mmc4_opt_clks,
1155 .opt_clks_cnt = ARRAY_SIZE(mmc4_opt_clks),
1156};
1157
1158/*
1159 * 'mpu' class
1160 *
1161 */
1162
1163static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
1164 .name = "mpu",
1165};
1166
1167/* mpu */
1168static struct omap_hwmod dra7xx_mpu_hwmod = {
1169 .name = "mpu",
1170 .class = &dra7xx_mpu_hwmod_class,
1171 .clkdm_name = "mpu_clkdm",
1172 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1173 .main_clk = "dpll_mpu_m2_ck",
1174 .prcm = {
1175 .omap4 = {
1176 .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1177 .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
1178 },
1179 },
1180};
1181
1182/*
1183 * 'ocp2scp' class
1184 *
1185 */
1186
1187static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
1188 .rev_offs = 0x0000,
1189 .sysc_offs = 0x0010,
1190 .syss_offs = 0x0014,
1191 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
1192 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1193 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1194 SIDLE_SMART_WKUP),
1195 .sysc_fields = &omap_hwmod_sysc_type1,
1196};
1197
1198static struct omap_hwmod_class dra7xx_ocp2scp_hwmod_class = {
1199 .name = "ocp2scp",
1200 .sysc = &dra7xx_ocp2scp_sysc,
1201};
1202
1203/* ocp2scp1 */
1204static struct omap_hwmod dra7xx_ocp2scp1_hwmod = {
1205 .name = "ocp2scp1",
1206 .class = &dra7xx_ocp2scp_hwmod_class,
1207 .clkdm_name = "l3init_clkdm",
1208 .main_clk = "l4_root_clk_div",
1209 .prcm = {
1210 .omap4 = {
1211 .clkctrl_offs = DRA7XX_CM_L3INIT_OCP2SCP1_CLKCTRL_OFFSET,
1212 .context_offs = DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET,
1213 .modulemode = MODULEMODE_HWCTRL,
1214 },
1215 },
1216};
1217
1218/*
1219 * 'qspi' class
1220 *
1221 */
1222
1223static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
1224 .sysc_offs = 0x0010,
1225 .sysc_flags = SYSC_HAS_SIDLEMODE,
1226 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1227 SIDLE_SMART_WKUP),
1228 .sysc_fields = &omap_hwmod_sysc_type2,
1229};
1230
1231static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
1232 .name = "qspi",
1233 .sysc = &dra7xx_qspi_sysc,
1234};
1235
1236/* qspi */
1237static struct omap_hwmod dra7xx_qspi_hwmod = {
1238 .name = "qspi",
1239 .class = &dra7xx_qspi_hwmod_class,
1240 .clkdm_name = "l4per2_clkdm",
1241 .main_clk = "qspi_gfclk_div",
1242 .prcm = {
1243 .omap4 = {
1244 .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
1245 .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
1246 .modulemode = MODULEMODE_SWCTRL,
1247 },
1248 },
1249};
1250
1251/*
1252 * 'sata' class
1253 *
1254 */
1255
1256static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
1257 .sysc_offs = 0x0000,
1258 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
1259 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1260 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1261 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1262 .sysc_fields = &omap_hwmod_sysc_type2,
1263};
1264
1265static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
1266 .name = "sata",
1267 .sysc = &dra7xx_sata_sysc,
1268};
1269
1270/* sata */
1271static struct omap_hwmod_opt_clk sata_opt_clks[] = {
1272 { .role = "ref_clk", .clk = "sata_ref_clk" },
1273};
1274
1275static struct omap_hwmod dra7xx_sata_hwmod = {
1276 .name = "sata",
1277 .class = &dra7xx_sata_hwmod_class,
1278 .clkdm_name = "l3init_clkdm",
1279 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
1280 .main_clk = "func_48m_fclk",
1281 .prcm = {
1282 .omap4 = {
1283 .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
1284 .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
1285 .modulemode = MODULEMODE_SWCTRL,
1286 },
1287 },
1288 .opt_clks = sata_opt_clks,
1289 .opt_clks_cnt = ARRAY_SIZE(sata_opt_clks),
1290};
1291
1292/*
1293 * 'smartreflex' class
1294 *
1295 */
1296
1297/* The IP is not compliant to type1 / type2 scheme */
1298static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = {
1299 .sidle_shift = 24,
1300 .enwkup_shift = 26,
1301};
1302
1303static struct omap_hwmod_class_sysconfig dra7xx_smartreflex_sysc = {
1304 .sysc_offs = 0x0038,
1305 .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE),
1306 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1307 SIDLE_SMART_WKUP),
1308 .sysc_fields = &omap_hwmod_sysc_type_smartreflex,
1309};
1310
1311static struct omap_hwmod_class dra7xx_smartreflex_hwmod_class = {
1312 .name = "smartreflex",
1313 .sysc = &dra7xx_smartreflex_sysc,
1314 .rev = 2,
1315};
1316
1317/* smartreflex_core */
1318/* smartreflex_core dev_attr */
1319static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = {
1320 .sensor_voltdm_name = "core",
1321};
1322
1323static struct omap_hwmod dra7xx_smartreflex_core_hwmod = {
1324 .name = "smartreflex_core",
1325 .class = &dra7xx_smartreflex_hwmod_class,
1326 .clkdm_name = "coreaon_clkdm",
1327 .main_clk = "wkupaon_iclk_mux",
1328 .prcm = {
1329 .omap4 = {
1330 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_CORE_CLKCTRL_OFFSET,
1331 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET,
1332 .modulemode = MODULEMODE_SWCTRL,
1333 },
1334 },
1335 .dev_attr = &smartreflex_core_dev_attr,
1336};
1337
1338/* smartreflex_mpu */
1339/* smartreflex_mpu dev_attr */
1340static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = {
1341 .sensor_voltdm_name = "mpu",
1342};
1343
1344static struct omap_hwmod dra7xx_smartreflex_mpu_hwmod = {
1345 .name = "smartreflex_mpu",
1346 .class = &dra7xx_smartreflex_hwmod_class,
1347 .clkdm_name = "coreaon_clkdm",
1348 .main_clk = "wkupaon_iclk_mux",
1349 .prcm = {
1350 .omap4 = {
1351 .clkctrl_offs = DRA7XX_CM_COREAON_SMARTREFLEX_MPU_CLKCTRL_OFFSET,
1352 .context_offs = DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET,
1353 .modulemode = MODULEMODE_SWCTRL,
1354 },
1355 },
1356 .dev_attr = &smartreflex_mpu_dev_attr,
1357};
1358
1359/*
1360 * 'spinlock' class
1361 *
1362 */
1363
1364static struct omap_hwmod_class_sysconfig dra7xx_spinlock_sysc = {
1365 .rev_offs = 0x0000,
1366 .sysc_offs = 0x0010,
1367 .syss_offs = 0x0014,
1368 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1369 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1370 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1371 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1372 SIDLE_SMART_WKUP),
1373 .sysc_fields = &omap_hwmod_sysc_type1,
1374};
1375
1376static struct omap_hwmod_class dra7xx_spinlock_hwmod_class = {
1377 .name = "spinlock",
1378 .sysc = &dra7xx_spinlock_sysc,
1379};
1380
1381/* spinlock */
1382static struct omap_hwmod dra7xx_spinlock_hwmod = {
1383 .name = "spinlock",
1384 .class = &dra7xx_spinlock_hwmod_class,
1385 .clkdm_name = "l4cfg_clkdm",
1386 .main_clk = "l3_iclk_div",
1387 .prcm = {
1388 .omap4 = {
1389 .clkctrl_offs = DRA7XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1390 .context_offs = DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1391 },
1392 },
1393};
1394
1395/*
1396 * 'timer' class
1397 *
1398 * This class contains several variants: ['timer_1ms', 'timer_secure',
1399 * 'timer']
1400 */
1401
1402static struct omap_hwmod_class_sysconfig dra7xx_timer_1ms_sysc = {
1403 .rev_offs = 0x0000,
1404 .sysc_offs = 0x0010,
1405 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1406 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1407 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1408 SIDLE_SMART_WKUP),
1409 .sysc_fields = &omap_hwmod_sysc_type2,
1410};
1411
1412static struct omap_hwmod_class dra7xx_timer_1ms_hwmod_class = {
1413 .name = "timer",
1414 .sysc = &dra7xx_timer_1ms_sysc,
1415};
1416
1417static struct omap_hwmod_class_sysconfig dra7xx_timer_secure_sysc = {
1418 .rev_offs = 0x0000,
1419 .sysc_offs = 0x0010,
1420 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1421 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1422 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1423 SIDLE_SMART_WKUP),
1424 .sysc_fields = &omap_hwmod_sysc_type2,
1425};
1426
1427static struct omap_hwmod_class dra7xx_timer_secure_hwmod_class = {
1428 .name = "timer",
1429 .sysc = &dra7xx_timer_secure_sysc,
1430};
1431
1432static struct omap_hwmod_class_sysconfig dra7xx_timer_sysc = {
1433 .rev_offs = 0x0000,
1434 .sysc_offs = 0x0010,
1435 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1436 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1437 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1438 SIDLE_SMART_WKUP),
1439 .sysc_fields = &omap_hwmod_sysc_type2,
1440};
1441
1442static struct omap_hwmod_class dra7xx_timer_hwmod_class = {
1443 .name = "timer",
1444 .sysc = &dra7xx_timer_sysc,
1445};
1446
1447/* timer1 */
1448static struct omap_hwmod dra7xx_timer1_hwmod = {
1449 .name = "timer1",
1450 .class = &dra7xx_timer_1ms_hwmod_class,
1451 .clkdm_name = "wkupaon_clkdm",
1452 .main_clk = "timer1_gfclk_mux",
1453 .prcm = {
1454 .omap4 = {
1455 .clkctrl_offs = DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1456 .context_offs = DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1457 .modulemode = MODULEMODE_SWCTRL,
1458 },
1459 },
1460};
1461
1462/* timer2 */
1463static struct omap_hwmod dra7xx_timer2_hwmod = {
1464 .name = "timer2",
1465 .class = &dra7xx_timer_1ms_hwmod_class,
1466 .clkdm_name = "l4per_clkdm",
1467 .main_clk = "timer2_gfclk_mux",
1468 .prcm = {
1469 .omap4 = {
1470 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1471 .context_offs = DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1472 .modulemode = MODULEMODE_SWCTRL,
1473 },
1474 },
1475};
1476
1477/* timer3 */
1478static struct omap_hwmod dra7xx_timer3_hwmod = {
1479 .name = "timer3",
1480 .class = &dra7xx_timer_hwmod_class,
1481 .clkdm_name = "l4per_clkdm",
1482 .main_clk = "timer3_gfclk_mux",
1483 .prcm = {
1484 .omap4 = {
1485 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1486 .context_offs = DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1487 .modulemode = MODULEMODE_SWCTRL,
1488 },
1489 },
1490};
1491
1492/* timer4 */
1493static struct omap_hwmod dra7xx_timer4_hwmod = {
1494 .name = "timer4",
1495 .class = &dra7xx_timer_secure_hwmod_class,
1496 .clkdm_name = "l4per_clkdm",
1497 .main_clk = "timer4_gfclk_mux",
1498 .prcm = {
1499 .omap4 = {
1500 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1501 .context_offs = DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1502 .modulemode = MODULEMODE_SWCTRL,
1503 },
1504 },
1505};
1506
1507/* timer5 */
1508static struct omap_hwmod dra7xx_timer5_hwmod = {
1509 .name = "timer5",
1510 .class = &dra7xx_timer_hwmod_class,
1511 .clkdm_name = "ipu_clkdm",
1512 .main_clk = "timer5_gfclk_mux",
1513 .prcm = {
1514 .omap4 = {
1515 .clkctrl_offs = DRA7XX_CM_IPU_TIMER5_CLKCTRL_OFFSET,
1516 .context_offs = DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET,
1517 .modulemode = MODULEMODE_SWCTRL,
1518 },
1519 },
1520};
1521
1522/* timer6 */
1523static struct omap_hwmod dra7xx_timer6_hwmod = {
1524 .name = "timer6",
1525 .class = &dra7xx_timer_hwmod_class,
1526 .clkdm_name = "ipu_clkdm",
1527 .main_clk = "timer6_gfclk_mux",
1528 .prcm = {
1529 .omap4 = {
1530 .clkctrl_offs = DRA7XX_CM_IPU_TIMER6_CLKCTRL_OFFSET,
1531 .context_offs = DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET,
1532 .modulemode = MODULEMODE_SWCTRL,
1533 },
1534 },
1535};
1536
1537/* timer7 */
1538static struct omap_hwmod dra7xx_timer7_hwmod = {
1539 .name = "timer7",
1540 .class = &dra7xx_timer_hwmod_class,
1541 .clkdm_name = "ipu_clkdm",
1542 .main_clk = "timer7_gfclk_mux",
1543 .prcm = {
1544 .omap4 = {
1545 .clkctrl_offs = DRA7XX_CM_IPU_TIMER7_CLKCTRL_OFFSET,
1546 .context_offs = DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET,
1547 .modulemode = MODULEMODE_SWCTRL,
1548 },
1549 },
1550};
1551
1552/* timer8 */
1553static struct omap_hwmod dra7xx_timer8_hwmod = {
1554 .name = "timer8",
1555 .class = &dra7xx_timer_hwmod_class,
1556 .clkdm_name = "ipu_clkdm",
1557 .main_clk = "timer8_gfclk_mux",
1558 .prcm = {
1559 .omap4 = {
1560 .clkctrl_offs = DRA7XX_CM_IPU_TIMER8_CLKCTRL_OFFSET,
1561 .context_offs = DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET,
1562 .modulemode = MODULEMODE_SWCTRL,
1563 },
1564 },
1565};
1566
1567/* timer9 */
1568static struct omap_hwmod dra7xx_timer9_hwmod = {
1569 .name = "timer9",
1570 .class = &dra7xx_timer_hwmod_class,
1571 .clkdm_name = "l4per_clkdm",
1572 .main_clk = "timer9_gfclk_mux",
1573 .prcm = {
1574 .omap4 = {
1575 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1576 .context_offs = DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1577 .modulemode = MODULEMODE_SWCTRL,
1578 },
1579 },
1580};
1581
1582/* timer10 */
1583static struct omap_hwmod dra7xx_timer10_hwmod = {
1584 .name = "timer10",
1585 .class = &dra7xx_timer_1ms_hwmod_class,
1586 .clkdm_name = "l4per_clkdm",
1587 .main_clk = "timer10_gfclk_mux",
1588 .prcm = {
1589 .omap4 = {
1590 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1591 .context_offs = DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1592 .modulemode = MODULEMODE_SWCTRL,
1593 },
1594 },
1595};
1596
1597/* timer11 */
1598static struct omap_hwmod dra7xx_timer11_hwmod = {
1599 .name = "timer11",
1600 .class = &dra7xx_timer_hwmod_class,
1601 .clkdm_name = "l4per_clkdm",
1602 .main_clk = "timer11_gfclk_mux",
1603 .prcm = {
1604 .omap4 = {
1605 .clkctrl_offs = DRA7XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1606 .context_offs = DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1607 .modulemode = MODULEMODE_SWCTRL,
1608 },
1609 },
1610};
1611
1612/*
1613 * 'uart' class
1614 *
1615 */
1616
1617static struct omap_hwmod_class_sysconfig dra7xx_uart_sysc = {
1618 .rev_offs = 0x0050,
1619 .sysc_offs = 0x0054,
1620 .syss_offs = 0x0058,
1621 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1622 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1623 SYSS_HAS_RESET_STATUS),
1624 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1625 SIDLE_SMART_WKUP),
1626 .sysc_fields = &omap_hwmod_sysc_type1,
1627};
1628
1629static struct omap_hwmod_class dra7xx_uart_hwmod_class = {
1630 .name = "uart",
1631 .sysc = &dra7xx_uart_sysc,
1632};
1633
1634/* uart1 */
1635static struct omap_hwmod dra7xx_uart1_hwmod = {
1636 .name = "uart1",
1637 .class = &dra7xx_uart_hwmod_class,
1638 .clkdm_name = "l4per_clkdm",
1639 .main_clk = "uart1_gfclk_mux",
1640 .flags = HWMOD_SWSUP_SIDLE_ACT,
1641 .prcm = {
1642 .omap4 = {
1643 .clkctrl_offs = DRA7XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1644 .context_offs = DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1645 .modulemode = MODULEMODE_SWCTRL,
1646 },
1647 },
1648};
1649
1650/* uart2 */
1651static struct omap_hwmod dra7xx_uart2_hwmod = {
1652 .name = "uart2",
1653 .class = &dra7xx_uart_hwmod_class,
1654 .clkdm_name = "l4per_clkdm",
1655 .main_clk = "uart2_gfclk_mux",
1656 .flags = HWMOD_SWSUP_SIDLE_ACT,
1657 .prcm = {
1658 .omap4 = {
1659 .clkctrl_offs = DRA7XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1660 .context_offs = DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1661 .modulemode = MODULEMODE_SWCTRL,
1662 },
1663 },
1664};
1665
1666/* uart3 */
1667static struct omap_hwmod dra7xx_uart3_hwmod = {
1668 .name = "uart3",
1669 .class = &dra7xx_uart_hwmod_class,
1670 .clkdm_name = "l4per_clkdm",
1671 .main_clk = "uart3_gfclk_mux",
1672 .flags = HWMOD_SWSUP_SIDLE_ACT,
1673 .prcm = {
1674 .omap4 = {
1675 .clkctrl_offs = DRA7XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1676 .context_offs = DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1677 .modulemode = MODULEMODE_SWCTRL,
1678 },
1679 },
1680};
1681
1682/* uart4 */
1683static struct omap_hwmod dra7xx_uart4_hwmod = {
1684 .name = "uart4",
1685 .class = &dra7xx_uart_hwmod_class,
1686 .clkdm_name = "l4per_clkdm",
1687 .main_clk = "uart4_gfclk_mux",
1688 .flags = HWMOD_SWSUP_SIDLE_ACT,
1689 .prcm = {
1690 .omap4 = {
1691 .clkctrl_offs = DRA7XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1692 .context_offs = DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1693 .modulemode = MODULEMODE_SWCTRL,
1694 },
1695 },
1696};
1697
1698/* uart5 */
1699static struct omap_hwmod dra7xx_uart5_hwmod = {
1700 .name = "uart5",
1701 .class = &dra7xx_uart_hwmod_class,
1702 .clkdm_name = "l4per_clkdm",
1703 .main_clk = "uart5_gfclk_mux",
1704 .flags = HWMOD_SWSUP_SIDLE_ACT,
1705 .prcm = {
1706 .omap4 = {
1707 .clkctrl_offs = DRA7XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1708 .context_offs = DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1709 .modulemode = MODULEMODE_SWCTRL,
1710 },
1711 },
1712};
1713
1714/* uart6 */
1715static struct omap_hwmod dra7xx_uart6_hwmod = {
1716 .name = "uart6",
1717 .class = &dra7xx_uart_hwmod_class,
1718 .clkdm_name = "ipu_clkdm",
1719 .main_clk = "uart6_gfclk_mux",
1720 .flags = HWMOD_SWSUP_SIDLE_ACT,
1721 .prcm = {
1722 .omap4 = {
1723 .clkctrl_offs = DRA7XX_CM_IPU_UART6_CLKCTRL_OFFSET,
1724 .context_offs = DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET,
1725 .modulemode = MODULEMODE_SWCTRL,
1726 },
1727 },
1728};
1729
1730/*
1731 * 'usb_otg_ss' class
1732 *
1733 */
1734
1735static struct omap_hwmod_class dra7xx_usb_otg_ss_hwmod_class = {
1736 .name = "usb_otg_ss",
1737};
1738
1739/* usb_otg_ss1 */
1740static struct omap_hwmod_opt_clk usb_otg_ss1_opt_clks[] = {
1741 { .role = "refclk960m", .clk = "usb_otg_ss1_refclk960m" },
1742};
1743
1744static struct omap_hwmod dra7xx_usb_otg_ss1_hwmod = {
1745 .name = "usb_otg_ss1",
1746 .class = &dra7xx_usb_otg_ss_hwmod_class,
1747 .clkdm_name = "l3init_clkdm",
1748 .main_clk = "dpll_core_h13x2_ck",
1749 .prcm = {
1750 .omap4 = {
1751 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS1_CLKCTRL_OFFSET,
1752 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET,
1753 .modulemode = MODULEMODE_HWCTRL,
1754 },
1755 },
1756 .opt_clks = usb_otg_ss1_opt_clks,
1757 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss1_opt_clks),
1758};
1759
1760/* usb_otg_ss2 */
1761static struct omap_hwmod_opt_clk usb_otg_ss2_opt_clks[] = {
1762 { .role = "refclk960m", .clk = "usb_otg_ss2_refclk960m" },
1763};
1764
1765static struct omap_hwmod dra7xx_usb_otg_ss2_hwmod = {
1766 .name = "usb_otg_ss2",
1767 .class = &dra7xx_usb_otg_ss_hwmod_class,
1768 .clkdm_name = "l3init_clkdm",
1769 .main_clk = "dpll_core_h13x2_ck",
1770 .prcm = {
1771 .omap4 = {
1772 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS2_CLKCTRL_OFFSET,
1773 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET,
1774 .modulemode = MODULEMODE_HWCTRL,
1775 },
1776 },
1777 .opt_clks = usb_otg_ss2_opt_clks,
1778 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss2_opt_clks),
1779};
1780
1781/* usb_otg_ss3 */
1782static struct omap_hwmod dra7xx_usb_otg_ss3_hwmod = {
1783 .name = "usb_otg_ss3",
1784 .class = &dra7xx_usb_otg_ss_hwmod_class,
1785 .clkdm_name = "l3init_clkdm",
1786 .main_clk = "dpll_core_h13x2_ck",
1787 .prcm = {
1788 .omap4 = {
1789 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS3_CLKCTRL_OFFSET,
1790 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET,
1791 .modulemode = MODULEMODE_HWCTRL,
1792 },
1793 },
1794};
1795
1796/* usb_otg_ss4 */
1797static struct omap_hwmod dra7xx_usb_otg_ss4_hwmod = {
1798 .name = "usb_otg_ss4",
1799 .class = &dra7xx_usb_otg_ss_hwmod_class,
1800 .clkdm_name = "l3init_clkdm",
1801 .main_clk = "dpll_core_h13x2_ck",
1802 .prcm = {
1803 .omap4 = {
1804 .clkctrl_offs = DRA7XX_CM_L3INIT_USB_OTG_SS4_CLKCTRL_OFFSET,
1805 .context_offs = DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET,
1806 .modulemode = MODULEMODE_HWCTRL,
1807 },
1808 },
1809};
1810
1811/*
1812 * 'vcp' class
1813 *
1814 */
1815
1816static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
1817 .name = "vcp",
1818};
1819
1820/* vcp1 */
1821static struct omap_hwmod dra7xx_vcp1_hwmod = {
1822 .name = "vcp1",
1823 .class = &dra7xx_vcp_hwmod_class,
1824 .clkdm_name = "l3main1_clkdm",
1825 .main_clk = "l3_iclk_div",
1826 .prcm = {
1827 .omap4 = {
1828 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
1829 .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
1830 },
1831 },
1832};
1833
1834/* vcp2 */
1835static struct omap_hwmod dra7xx_vcp2_hwmod = {
1836 .name = "vcp2",
1837 .class = &dra7xx_vcp_hwmod_class,
1838 .clkdm_name = "l3main1_clkdm",
1839 .main_clk = "l3_iclk_div",
1840 .prcm = {
1841 .omap4 = {
1842 .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
1843 .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
1844 },
1845 },
1846};
1847
1848/*
1849 * 'wd_timer' class
1850 *
1851 */
1852
1853static struct omap_hwmod_class_sysconfig dra7xx_wd_timer_sysc = {
1854 .rev_offs = 0x0000,
1855 .sysc_offs = 0x0010,
1856 .syss_offs = 0x0014,
1857 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1858 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1859 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1860 SIDLE_SMART_WKUP),
1861 .sysc_fields = &omap_hwmod_sysc_type1,
1862};
1863
1864static struct omap_hwmod_class dra7xx_wd_timer_hwmod_class = {
1865 .name = "wd_timer",
1866 .sysc = &dra7xx_wd_timer_sysc,
1867 .pre_shutdown = &omap2_wd_timer_disable,
1868 .reset = &omap2_wd_timer_reset,
1869};
1870
1871/* wd_timer2 */
1872static struct omap_hwmod dra7xx_wd_timer2_hwmod = {
1873 .name = "wd_timer2",
1874 .class = &dra7xx_wd_timer_hwmod_class,
1875 .clkdm_name = "wkupaon_clkdm",
1876 .main_clk = "sys_32k_ck",
1877 .prcm = {
1878 .omap4 = {
1879 .clkctrl_offs = DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1880 .context_offs = DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1881 .modulemode = MODULEMODE_SWCTRL,
1882 },
1883 },
1884};
1885
1886
1887/*
1888 * Interfaces
1889 */
1890
1891/* l3_main_2 -> l3_instr */
1892static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
1893 .master = &dra7xx_l3_main_2_hwmod,
1894 .slave = &dra7xx_l3_instr_hwmod,
1895 .clk = "l3_iclk_div",
1896 .user = OCP_USER_MPU | OCP_USER_SDMA,
1897};
1898
1899/* l4_cfg -> l3_main_1 */
1900static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
1901 .master = &dra7xx_l4_cfg_hwmod,
1902 .slave = &dra7xx_l3_main_1_hwmod,
1903 .clk = "l3_iclk_div",
1904 .user = OCP_USER_MPU | OCP_USER_SDMA,
1905};
1906
1907/* mpu -> l3_main_1 */
1908static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
1909 .master = &dra7xx_mpu_hwmod,
1910 .slave = &dra7xx_l3_main_1_hwmod,
1911 .clk = "l3_iclk_div",
1912 .user = OCP_USER_MPU,
1913};
1914
1915/* l3_main_1 -> l3_main_2 */
1916static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
1917 .master = &dra7xx_l3_main_1_hwmod,
1918 .slave = &dra7xx_l3_main_2_hwmod,
1919 .clk = "l3_iclk_div",
1920 .user = OCP_USER_MPU,
1921};
1922
1923/* l4_cfg -> l3_main_2 */
1924static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
1925 .master = &dra7xx_l4_cfg_hwmod,
1926 .slave = &dra7xx_l3_main_2_hwmod,
1927 .clk = "l3_iclk_div",
1928 .user = OCP_USER_MPU | OCP_USER_SDMA,
1929};
1930
1931/* l3_main_1 -> l4_cfg */
1932static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
1933 .master = &dra7xx_l3_main_1_hwmod,
1934 .slave = &dra7xx_l4_cfg_hwmod,
1935 .clk = "l3_iclk_div",
1936 .user = OCP_USER_MPU | OCP_USER_SDMA,
1937};
1938
1939/* l3_main_1 -> l4_per1 */
1940static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
1941 .master = &dra7xx_l3_main_1_hwmod,
1942 .slave = &dra7xx_l4_per1_hwmod,
1943 .clk = "l3_iclk_div",
1944 .user = OCP_USER_MPU | OCP_USER_SDMA,
1945};
1946
1947/* l3_main_1 -> l4_per2 */
1948static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
1949 .master = &dra7xx_l3_main_1_hwmod,
1950 .slave = &dra7xx_l4_per2_hwmod,
1951 .clk = "l3_iclk_div",
1952 .user = OCP_USER_MPU | OCP_USER_SDMA,
1953};
1954
1955/* l3_main_1 -> l4_per3 */
1956static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
1957 .master = &dra7xx_l3_main_1_hwmod,
1958 .slave = &dra7xx_l4_per3_hwmod,
1959 .clk = "l3_iclk_div",
1960 .user = OCP_USER_MPU | OCP_USER_SDMA,
1961};
1962
1963/* l3_main_1 -> l4_wkup */
1964static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
1965 .master = &dra7xx_l3_main_1_hwmod,
1966 .slave = &dra7xx_l4_wkup_hwmod,
1967 .clk = "wkupaon_iclk_mux",
1968 .user = OCP_USER_MPU | OCP_USER_SDMA,
1969};
1970
1971/* l4_per2 -> atl */
1972static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
1973 .master = &dra7xx_l4_per2_hwmod,
1974 .slave = &dra7xx_atl_hwmod,
1975 .clk = "l3_iclk_div",
1976 .user = OCP_USER_MPU | OCP_USER_SDMA,
1977};
1978
1979/* l3_main_1 -> bb2d */
1980static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
1981 .master = &dra7xx_l3_main_1_hwmod,
1982 .slave = &dra7xx_bb2d_hwmod,
1983 .clk = "l3_iclk_div",
1984 .user = OCP_USER_MPU | OCP_USER_SDMA,
1985};
1986
1987/* l4_wkup -> counter_32k */
1988static struct omap_hwmod_ocp_if dra7xx_l4_wkup__counter_32k = {
1989 .master = &dra7xx_l4_wkup_hwmod,
1990 .slave = &dra7xx_counter_32k_hwmod,
1991 .clk = "wkupaon_iclk_mux",
1992 .user = OCP_USER_MPU | OCP_USER_SDMA,
1993};
1994
1995/* l4_wkup -> ctrl_module_wkup */
1996static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
1997 .master = &dra7xx_l4_wkup_hwmod,
1998 .slave = &dra7xx_ctrl_module_wkup_hwmod,
1999 .clk = "wkupaon_iclk_mux",
2000 .user = OCP_USER_MPU | OCP_USER_SDMA,
2001};
2002
2003/* l4_wkup -> dcan1 */
2004static struct omap_hwmod_ocp_if dra7xx_l4_wkup__dcan1 = {
2005 .master = &dra7xx_l4_wkup_hwmod,
2006 .slave = &dra7xx_dcan1_hwmod,
2007 .clk = "wkupaon_iclk_mux",
2008 .user = OCP_USER_MPU | OCP_USER_SDMA,
2009};
2010
2011/* l4_per2 -> dcan2 */
2012static struct omap_hwmod_ocp_if dra7xx_l4_per2__dcan2 = {
2013 .master = &dra7xx_l4_per2_hwmod,
2014 .slave = &dra7xx_dcan2_hwmod,
2015 .clk = "l3_iclk_div",
2016 .user = OCP_USER_MPU | OCP_USER_SDMA,
2017};
2018
2019static struct omap_hwmod_addr_space dra7xx_dma_system_addrs[] = {
2020 {
2021 .pa_start = 0x4a056000,
2022 .pa_end = 0x4a056fff,
2023 .flags = ADDR_TYPE_RT
2024 },
2025 { }
2026};
2027
2028/* l4_cfg -> dma_system */
2029static struct omap_hwmod_ocp_if dra7xx_l4_cfg__dma_system = {
2030 .master = &dra7xx_l4_cfg_hwmod,
2031 .slave = &dra7xx_dma_system_hwmod,
2032 .clk = "l3_iclk_div",
2033 .addr = dra7xx_dma_system_addrs,
2034 .user = OCP_USER_MPU | OCP_USER_SDMA,
2035};
2036
2037static struct omap_hwmod_addr_space dra7xx_dss_addrs[] = {
2038 {
2039 .name = "family",
2040 .pa_start = 0x58000000,
2041 .pa_end = 0x5800007f,
2042 .flags = ADDR_TYPE_RT
2043 },
2044};
2045
2046/* l3_main_1 -> dss */
2047static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dss = {
2048 .master = &dra7xx_l3_main_1_hwmod,
2049 .slave = &dra7xx_dss_hwmod,
2050 .clk = "l3_iclk_div",
2051 .addr = dra7xx_dss_addrs,
2052 .user = OCP_USER_MPU | OCP_USER_SDMA,
2053};
2054
2055static struct omap_hwmod_addr_space dra7xx_dss_dispc_addrs[] = {
2056 {
2057 .name = "dispc",
2058 .pa_start = 0x58001000,
2059 .pa_end = 0x58001fff,
2060 .flags = ADDR_TYPE_RT
2061 },
2062};
2063
2064/* l3_main_1 -> dispc */
2065static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dispc = {
2066 .master = &dra7xx_l3_main_1_hwmod,
2067 .slave = &dra7xx_dss_dispc_hwmod,
2068 .clk = "l3_iclk_div",
2069 .addr = dra7xx_dss_dispc_addrs,
2070 .user = OCP_USER_MPU | OCP_USER_SDMA,
2071};
2072
2073static struct omap_hwmod_addr_space dra7xx_dss_hdmi_addrs[] = {
2074 {
2075 .name = "hdmi_wp",
2076 .pa_start = 0x58040000,
2077 .pa_end = 0x580400ff,
2078 .flags = ADDR_TYPE_RT
2079 },
2080 { }
2081};
2082
2083/* l3_main_1 -> dispc */
2084static struct omap_hwmod_ocp_if dra7xx_l3_main_1__hdmi = {
2085 .master = &dra7xx_l3_main_1_hwmod,
2086 .slave = &dra7xx_dss_hdmi_hwmod,
2087 .clk = "l3_iclk_div",
2088 .addr = dra7xx_dss_hdmi_addrs,
2089 .user = OCP_USER_MPU | OCP_USER_SDMA,
2090};
2091
2092static struct omap_hwmod_addr_space dra7xx_elm_addrs[] = {
2093 {
2094 .pa_start = 0x48078000,
2095 .pa_end = 0x48078fff,
2096 .flags = ADDR_TYPE_RT
2097 },
2098 { }
2099};
2100
2101/* l4_per1 -> elm */
2102static struct omap_hwmod_ocp_if dra7xx_l4_per1__elm = {
2103 .master = &dra7xx_l4_per1_hwmod,
2104 .slave = &dra7xx_elm_hwmod,
2105 .clk = "l3_iclk_div",
2106 .addr = dra7xx_elm_addrs,
2107 .user = OCP_USER_MPU | OCP_USER_SDMA,
2108};
2109
2110/* l4_wkup -> gpio1 */
2111static struct omap_hwmod_ocp_if dra7xx_l4_wkup__gpio1 = {
2112 .master = &dra7xx_l4_wkup_hwmod,
2113 .slave = &dra7xx_gpio1_hwmod,
2114 .clk = "wkupaon_iclk_mux",
2115 .user = OCP_USER_MPU | OCP_USER_SDMA,
2116};
2117
2118/* l4_per1 -> gpio2 */
2119static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio2 = {
2120 .master = &dra7xx_l4_per1_hwmod,
2121 .slave = &dra7xx_gpio2_hwmod,
2122 .clk = "l3_iclk_div",
2123 .user = OCP_USER_MPU | OCP_USER_SDMA,
2124};
2125
2126/* l4_per1 -> gpio3 */
2127static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio3 = {
2128 .master = &dra7xx_l4_per1_hwmod,
2129 .slave = &dra7xx_gpio3_hwmod,
2130 .clk = "l3_iclk_div",
2131 .user = OCP_USER_MPU | OCP_USER_SDMA,
2132};
2133
2134/* l4_per1 -> gpio4 */
2135static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio4 = {
2136 .master = &dra7xx_l4_per1_hwmod,
2137 .slave = &dra7xx_gpio4_hwmod,
2138 .clk = "l3_iclk_div",
2139 .user = OCP_USER_MPU | OCP_USER_SDMA,
2140};
2141
2142/* l4_per1 -> gpio5 */
2143static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio5 = {
2144 .master = &dra7xx_l4_per1_hwmod,
2145 .slave = &dra7xx_gpio5_hwmod,
2146 .clk = "l3_iclk_div",
2147 .user = OCP_USER_MPU | OCP_USER_SDMA,
2148};
2149
2150/* l4_per1 -> gpio6 */
2151static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio6 = {
2152 .master = &dra7xx_l4_per1_hwmod,
2153 .slave = &dra7xx_gpio6_hwmod,
2154 .clk = "l3_iclk_div",
2155 .user = OCP_USER_MPU | OCP_USER_SDMA,
2156};
2157
2158/* l4_per1 -> gpio7 */
2159static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio7 = {
2160 .master = &dra7xx_l4_per1_hwmod,
2161 .slave = &dra7xx_gpio7_hwmod,
2162 .clk = "l3_iclk_div",
2163 .user = OCP_USER_MPU | OCP_USER_SDMA,
2164};
2165
2166/* l4_per1 -> gpio8 */
2167static struct omap_hwmod_ocp_if dra7xx_l4_per1__gpio8 = {
2168 .master = &dra7xx_l4_per1_hwmod,
2169 .slave = &dra7xx_gpio8_hwmod,
2170 .clk = "l3_iclk_div",
2171 .user = OCP_USER_MPU | OCP_USER_SDMA,
2172};
2173
2174static struct omap_hwmod_addr_space dra7xx_gpmc_addrs[] = {
2175 {
2176 .pa_start = 0x50000000,
2177 .pa_end = 0x500003ff,
2178 .flags = ADDR_TYPE_RT
2179 },
2180 { }
2181};
2182
2183/* l3_main_1 -> gpmc */
2184static struct omap_hwmod_ocp_if dra7xx_l3_main_1__gpmc = {
2185 .master = &dra7xx_l3_main_1_hwmod,
2186 .slave = &dra7xx_gpmc_hwmod,
2187 .clk = "l3_iclk_div",
2188 .addr = dra7xx_gpmc_addrs,
2189 .user = OCP_USER_MPU | OCP_USER_SDMA,
2190};
2191
2192static struct omap_hwmod_addr_space dra7xx_hdq1w_addrs[] = {
2193 {
2194 .pa_start = 0x480b2000,
2195 .pa_end = 0x480b201f,
2196 .flags = ADDR_TYPE_RT
2197 },
2198 { }
2199};
2200
2201/* l4_per1 -> hdq1w */
2202static struct omap_hwmod_ocp_if dra7xx_l4_per1__hdq1w = {
2203 .master = &dra7xx_l4_per1_hwmod,
2204 .slave = &dra7xx_hdq1w_hwmod,
2205 .clk = "l3_iclk_div",
2206 .addr = dra7xx_hdq1w_addrs,
2207 .user = OCP_USER_MPU | OCP_USER_SDMA,
2208};
2209
2210/* l4_per1 -> i2c1 */
2211static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c1 = {
2212 .master = &dra7xx_l4_per1_hwmod,
2213 .slave = &dra7xx_i2c1_hwmod,
2214 .clk = "l3_iclk_div",
2215 .user = OCP_USER_MPU | OCP_USER_SDMA,
2216};
2217
2218/* l4_per1 -> i2c2 */
2219static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c2 = {
2220 .master = &dra7xx_l4_per1_hwmod,
2221 .slave = &dra7xx_i2c2_hwmod,
2222 .clk = "l3_iclk_div",
2223 .user = OCP_USER_MPU | OCP_USER_SDMA,
2224};
2225
2226/* l4_per1 -> i2c3 */
2227static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c3 = {
2228 .master = &dra7xx_l4_per1_hwmod,
2229 .slave = &dra7xx_i2c3_hwmod,
2230 .clk = "l3_iclk_div",
2231 .user = OCP_USER_MPU | OCP_USER_SDMA,
2232};
2233
2234/* l4_per1 -> i2c4 */
2235static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c4 = {
2236 .master = &dra7xx_l4_per1_hwmod,
2237 .slave = &dra7xx_i2c4_hwmod,
2238 .clk = "l3_iclk_div",
2239 .user = OCP_USER_MPU | OCP_USER_SDMA,
2240};
2241
2242/* l4_per1 -> i2c5 */
2243static struct omap_hwmod_ocp_if dra7xx_l4_per1__i2c5 = {
2244 .master = &dra7xx_l4_per1_hwmod,
2245 .slave = &dra7xx_i2c5_hwmod,
2246 .clk = "l3_iclk_div",
2247 .user = OCP_USER_MPU | OCP_USER_SDMA,
2248};
2249
2250/* l4_per1 -> mcspi1 */
2251static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi1 = {
2252 .master = &dra7xx_l4_per1_hwmod,
2253 .slave = &dra7xx_mcspi1_hwmod,
2254 .clk = "l3_iclk_div",
2255 .user = OCP_USER_MPU | OCP_USER_SDMA,
2256};
2257
2258/* l4_per1 -> mcspi2 */
2259static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi2 = {
2260 .master = &dra7xx_l4_per1_hwmod,
2261 .slave = &dra7xx_mcspi2_hwmod,
2262 .clk = "l3_iclk_div",
2263 .user = OCP_USER_MPU | OCP_USER_SDMA,
2264};
2265
2266/* l4_per1 -> mcspi3 */
2267static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi3 = {
2268 .master = &dra7xx_l4_per1_hwmod,
2269 .slave = &dra7xx_mcspi3_hwmod,
2270 .clk = "l3_iclk_div",
2271 .user = OCP_USER_MPU | OCP_USER_SDMA,
2272};
2273
2274/* l4_per1 -> mcspi4 */
2275static struct omap_hwmod_ocp_if dra7xx_l4_per1__mcspi4 = {
2276 .master = &dra7xx_l4_per1_hwmod,
2277 .slave = &dra7xx_mcspi4_hwmod,
2278 .clk = "l3_iclk_div",
2279 .user = OCP_USER_MPU | OCP_USER_SDMA,
2280};
2281
2282/* l4_per1 -> mmc1 */
2283static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc1 = {
2284 .master = &dra7xx_l4_per1_hwmod,
2285 .slave = &dra7xx_mmc1_hwmod,
2286 .clk = "l3_iclk_div",
2287 .user = OCP_USER_MPU | OCP_USER_SDMA,
2288};
2289
2290/* l4_per1 -> mmc2 */
2291static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc2 = {
2292 .master = &dra7xx_l4_per1_hwmod,
2293 .slave = &dra7xx_mmc2_hwmod,
2294 .clk = "l3_iclk_div",
2295 .user = OCP_USER_MPU | OCP_USER_SDMA,
2296};
2297
2298/* l4_per1 -> mmc3 */
2299static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc3 = {
2300 .master = &dra7xx_l4_per1_hwmod,
2301 .slave = &dra7xx_mmc3_hwmod,
2302 .clk = "l3_iclk_div",
2303 .user = OCP_USER_MPU | OCP_USER_SDMA,
2304};
2305
2306/* l4_per1 -> mmc4 */
2307static struct omap_hwmod_ocp_if dra7xx_l4_per1__mmc4 = {
2308 .master = &dra7xx_l4_per1_hwmod,
2309 .slave = &dra7xx_mmc4_hwmod,
2310 .clk = "l3_iclk_div",
2311 .user = OCP_USER_MPU | OCP_USER_SDMA,
2312};
2313
2314/* l4_cfg -> mpu */
2315static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
2316 .master = &dra7xx_l4_cfg_hwmod,
2317 .slave = &dra7xx_mpu_hwmod,
2318 .clk = "l3_iclk_div",
2319 .user = OCP_USER_MPU | OCP_USER_SDMA,
2320};
2321
2322static struct omap_hwmod_addr_space dra7xx_ocp2scp1_addrs[] = {
2323 {
2324 .pa_start = 0x4a080000,
2325 .pa_end = 0x4a08001f,
2326 .flags = ADDR_TYPE_RT
2327 },
2328 { }
2329};
2330
2331/* l4_cfg -> ocp2scp1 */
2332static struct omap_hwmod_ocp_if dra7xx_l4_cfg__ocp2scp1 = {
2333 .master = &dra7xx_l4_cfg_hwmod,
2334 .slave = &dra7xx_ocp2scp1_hwmod,
2335 .clk = "l4_root_clk_div",
2336 .addr = dra7xx_ocp2scp1_addrs,
2337 .user = OCP_USER_MPU | OCP_USER_SDMA,
2338};
2339
2340static struct omap_hwmod_addr_space dra7xx_qspi_addrs[] = {
2341 {
2342 .pa_start = 0x4b300000,
2343 .pa_end = 0x4b30007f,
2344 .flags = ADDR_TYPE_RT
2345 },
2346 { }
2347};
2348
2349/* l3_main_1 -> qspi */
2350static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
2351 .master = &dra7xx_l3_main_1_hwmod,
2352 .slave = &dra7xx_qspi_hwmod,
2353 .clk = "l3_iclk_div",
2354 .addr = dra7xx_qspi_addrs,
2355 .user = OCP_USER_MPU | OCP_USER_SDMA,
2356};
2357
2358static struct omap_hwmod_addr_space dra7xx_sata_addrs[] = {
2359 {
2360 .name = "sysc",
2361 .pa_start = 0x4a141100,
2362 .pa_end = 0x4a141107,
2363 .flags = ADDR_TYPE_RT
2364 },
2365 { }
2366};
2367
2368/* l4_cfg -> sata */
2369static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
2370 .master = &dra7xx_l4_cfg_hwmod,
2371 .slave = &dra7xx_sata_hwmod,
2372 .clk = "l3_iclk_div",
2373 .addr = dra7xx_sata_addrs,
2374 .user = OCP_USER_MPU | OCP_USER_SDMA,
2375};
2376
2377static struct omap_hwmod_addr_space dra7xx_smartreflex_core_addrs[] = {
2378 {
2379 .pa_start = 0x4a0dd000,
2380 .pa_end = 0x4a0dd07f,
2381 .flags = ADDR_TYPE_RT
2382 },
2383 { }
2384};
2385
2386/* l4_cfg -> smartreflex_core */
2387static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_core = {
2388 .master = &dra7xx_l4_cfg_hwmod,
2389 .slave = &dra7xx_smartreflex_core_hwmod,
2390 .clk = "l4_root_clk_div",
2391 .addr = dra7xx_smartreflex_core_addrs,
2392 .user = OCP_USER_MPU | OCP_USER_SDMA,
2393};
2394
2395static struct omap_hwmod_addr_space dra7xx_smartreflex_mpu_addrs[] = {
2396 {
2397 .pa_start = 0x4a0d9000,
2398 .pa_end = 0x4a0d907f,
2399 .flags = ADDR_TYPE_RT
2400 },
2401 { }
2402};
2403
2404/* l4_cfg -> smartreflex_mpu */
2405static struct omap_hwmod_ocp_if dra7xx_l4_cfg__smartreflex_mpu = {
2406 .master = &dra7xx_l4_cfg_hwmod,
2407 .slave = &dra7xx_smartreflex_mpu_hwmod,
2408 .clk = "l4_root_clk_div",
2409 .addr = dra7xx_smartreflex_mpu_addrs,
2410 .user = OCP_USER_MPU | OCP_USER_SDMA,
2411};
2412
2413static struct omap_hwmod_addr_space dra7xx_spinlock_addrs[] = {
2414 {
2415 .pa_start = 0x4a0f6000,
2416 .pa_end = 0x4a0f6fff,
2417 .flags = ADDR_TYPE_RT
2418 },
2419 { }
2420};
2421
2422/* l4_cfg -> spinlock */
2423static struct omap_hwmod_ocp_if dra7xx_l4_cfg__spinlock = {
2424 .master = &dra7xx_l4_cfg_hwmod,
2425 .slave = &dra7xx_spinlock_hwmod,
2426 .clk = "l3_iclk_div",
2427 .addr = dra7xx_spinlock_addrs,
2428 .user = OCP_USER_MPU | OCP_USER_SDMA,
2429};
2430
2431/* l4_wkup -> timer1 */
2432static struct omap_hwmod_ocp_if dra7xx_l4_wkup__timer1 = {
2433 .master = &dra7xx_l4_wkup_hwmod,
2434 .slave = &dra7xx_timer1_hwmod,
2435 .clk = "wkupaon_iclk_mux",
2436 .user = OCP_USER_MPU | OCP_USER_SDMA,
2437};
2438
2439/* l4_per1 -> timer2 */
2440static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer2 = {
2441 .master = &dra7xx_l4_per1_hwmod,
2442 .slave = &dra7xx_timer2_hwmod,
2443 .clk = "l3_iclk_div",
2444 .user = OCP_USER_MPU | OCP_USER_SDMA,
2445};
2446
2447/* l4_per1 -> timer3 */
2448static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer3 = {
2449 .master = &dra7xx_l4_per1_hwmod,
2450 .slave = &dra7xx_timer3_hwmod,
2451 .clk = "l3_iclk_div",
2452 .user = OCP_USER_MPU | OCP_USER_SDMA,
2453};
2454
2455/* l4_per1 -> timer4 */
2456static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer4 = {
2457 .master = &dra7xx_l4_per1_hwmod,
2458 .slave = &dra7xx_timer4_hwmod,
2459 .clk = "l3_iclk_div",
2460 .user = OCP_USER_MPU | OCP_USER_SDMA,
2461};
2462
2463/* l4_per3 -> timer5 */
2464static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer5 = {
2465 .master = &dra7xx_l4_per3_hwmod,
2466 .slave = &dra7xx_timer5_hwmod,
2467 .clk = "l3_iclk_div",
2468 .user = OCP_USER_MPU | OCP_USER_SDMA,
2469};
2470
2471/* l4_per3 -> timer6 */
2472static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer6 = {
2473 .master = &dra7xx_l4_per3_hwmod,
2474 .slave = &dra7xx_timer6_hwmod,
2475 .clk = "l3_iclk_div",
2476 .user = OCP_USER_MPU | OCP_USER_SDMA,
2477};
2478
2479/* l4_per3 -> timer7 */
2480static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer7 = {
2481 .master = &dra7xx_l4_per3_hwmod,
2482 .slave = &dra7xx_timer7_hwmod,
2483 .clk = "l3_iclk_div",
2484 .user = OCP_USER_MPU | OCP_USER_SDMA,
2485};
2486
2487/* l4_per3 -> timer8 */
2488static struct omap_hwmod_ocp_if dra7xx_l4_per3__timer8 = {
2489 .master = &dra7xx_l4_per3_hwmod,
2490 .slave = &dra7xx_timer8_hwmod,
2491 .clk = "l3_iclk_div",
2492 .user = OCP_USER_MPU | OCP_USER_SDMA,
2493};
2494
2495/* l4_per1 -> timer9 */
2496static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer9 = {
2497 .master = &dra7xx_l4_per1_hwmod,
2498 .slave = &dra7xx_timer9_hwmod,
2499 .clk = "l3_iclk_div",
2500 .user = OCP_USER_MPU | OCP_USER_SDMA,
2501};
2502
2503/* l4_per1 -> timer10 */
2504static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer10 = {
2505 .master = &dra7xx_l4_per1_hwmod,
2506 .slave = &dra7xx_timer10_hwmod,
2507 .clk = "l3_iclk_div",
2508 .user = OCP_USER_MPU | OCP_USER_SDMA,
2509};
2510
2511/* l4_per1 -> timer11 */
2512static struct omap_hwmod_ocp_if dra7xx_l4_per1__timer11 = {
2513 .master = &dra7xx_l4_per1_hwmod,
2514 .slave = &dra7xx_timer11_hwmod,
2515 .clk = "l3_iclk_div",
2516 .user = OCP_USER_MPU | OCP_USER_SDMA,
2517};
2518
2519/* l4_per1 -> uart1 */
2520static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart1 = {
2521 .master = &dra7xx_l4_per1_hwmod,
2522 .slave = &dra7xx_uart1_hwmod,
2523 .clk = "l3_iclk_div",
2524 .user = OCP_USER_MPU | OCP_USER_SDMA,
2525};
2526
2527/* l4_per1 -> uart2 */
2528static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart2 = {
2529 .master = &dra7xx_l4_per1_hwmod,
2530 .slave = &dra7xx_uart2_hwmod,
2531 .clk = "l3_iclk_div",
2532 .user = OCP_USER_MPU | OCP_USER_SDMA,
2533};
2534
2535/* l4_per1 -> uart3 */
2536static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart3 = {
2537 .master = &dra7xx_l4_per1_hwmod,
2538 .slave = &dra7xx_uart3_hwmod,
2539 .clk = "l3_iclk_div",
2540 .user = OCP_USER_MPU | OCP_USER_SDMA,
2541};
2542
2543/* l4_per1 -> uart4 */
2544static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart4 = {
2545 .master = &dra7xx_l4_per1_hwmod,
2546 .slave = &dra7xx_uart4_hwmod,
2547 .clk = "l3_iclk_div",
2548 .user = OCP_USER_MPU | OCP_USER_SDMA,
2549};
2550
2551/* l4_per1 -> uart5 */
2552static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart5 = {
2553 .master = &dra7xx_l4_per1_hwmod,
2554 .slave = &dra7xx_uart5_hwmod,
2555 .clk = "l3_iclk_div",
2556 .user = OCP_USER_MPU | OCP_USER_SDMA,
2557};
2558
2559/* l4_per1 -> uart6 */
2560static struct omap_hwmod_ocp_if dra7xx_l4_per1__uart6 = {
2561 .master = &dra7xx_l4_per1_hwmod,
2562 .slave = &dra7xx_uart6_hwmod,
2563 .clk = "l3_iclk_div",
2564 .user = OCP_USER_MPU | OCP_USER_SDMA,
2565};
2566
2567/* l4_per3 -> usb_otg_ss1 */
2568static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss1 = {
2569 .master = &dra7xx_l4_per3_hwmod,
2570 .slave = &dra7xx_usb_otg_ss1_hwmod,
2571 .clk = "dpll_core_h13x2_ck",
2572 .user = OCP_USER_MPU | OCP_USER_SDMA,
2573};
2574
2575/* l4_per3 -> usb_otg_ss2 */
2576static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss2 = {
2577 .master = &dra7xx_l4_per3_hwmod,
2578 .slave = &dra7xx_usb_otg_ss2_hwmod,
2579 .clk = "dpll_core_h13x2_ck",
2580 .user = OCP_USER_MPU | OCP_USER_SDMA,
2581};
2582
2583/* l4_per3 -> usb_otg_ss3 */
2584static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss3 = {
2585 .master = &dra7xx_l4_per3_hwmod,
2586 .slave = &dra7xx_usb_otg_ss3_hwmod,
2587 .clk = "dpll_core_h13x2_ck",
2588 .user = OCP_USER_MPU | OCP_USER_SDMA,
2589};
2590
2591/* l4_per3 -> usb_otg_ss4 */
2592static struct omap_hwmod_ocp_if dra7xx_l4_per3__usb_otg_ss4 = {
2593 .master = &dra7xx_l4_per3_hwmod,
2594 .slave = &dra7xx_usb_otg_ss4_hwmod,
2595 .clk = "dpll_core_h13x2_ck",
2596 .user = OCP_USER_MPU | OCP_USER_SDMA,
2597};
2598
2599/* l3_main_1 -> vcp1 */
2600static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
2601 .master = &dra7xx_l3_main_1_hwmod,
2602 .slave = &dra7xx_vcp1_hwmod,
2603 .clk = "l3_iclk_div",
2604 .user = OCP_USER_MPU | OCP_USER_SDMA,
2605};
2606
2607/* l4_per2 -> vcp1 */
2608static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
2609 .master = &dra7xx_l4_per2_hwmod,
2610 .slave = &dra7xx_vcp1_hwmod,
2611 .clk = "l3_iclk_div",
2612 .user = OCP_USER_MPU | OCP_USER_SDMA,
2613};
2614
2615/* l3_main_1 -> vcp2 */
2616static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
2617 .master = &dra7xx_l3_main_1_hwmod,
2618 .slave = &dra7xx_vcp2_hwmod,
2619 .clk = "l3_iclk_div",
2620 .user = OCP_USER_MPU | OCP_USER_SDMA,
2621};
2622
2623/* l4_per2 -> vcp2 */
2624static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
2625 .master = &dra7xx_l4_per2_hwmod,
2626 .slave = &dra7xx_vcp2_hwmod,
2627 .clk = "l3_iclk_div",
2628 .user = OCP_USER_MPU | OCP_USER_SDMA,
2629};
2630
2631/* l4_wkup -> wd_timer2 */
2632static struct omap_hwmod_ocp_if dra7xx_l4_wkup__wd_timer2 = {
2633 .master = &dra7xx_l4_wkup_hwmod,
2634 .slave = &dra7xx_wd_timer2_hwmod,
2635 .clk = "wkupaon_iclk_mux",
2636 .user = OCP_USER_MPU | OCP_USER_SDMA,
2637};
2638
2639static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
2640 &dra7xx_l3_main_2__l3_instr,
2641 &dra7xx_l4_cfg__l3_main_1,
2642 &dra7xx_mpu__l3_main_1,
2643 &dra7xx_l3_main_1__l3_main_2,
2644 &dra7xx_l4_cfg__l3_main_2,
2645 &dra7xx_l3_main_1__l4_cfg,
2646 &dra7xx_l3_main_1__l4_per1,
2647 &dra7xx_l3_main_1__l4_per2,
2648 &dra7xx_l3_main_1__l4_per3,
2649 &dra7xx_l3_main_1__l4_wkup,
2650 &dra7xx_l4_per2__atl,
2651 &dra7xx_l3_main_1__bb2d,
2652 &dra7xx_l4_wkup__counter_32k,
2653 &dra7xx_l4_wkup__ctrl_module_wkup,
2654 &dra7xx_l4_wkup__dcan1,
2655 &dra7xx_l4_per2__dcan2,
2656 &dra7xx_l4_cfg__dma_system,
2657 &dra7xx_l3_main_1__dss,
2658 &dra7xx_l3_main_1__dispc,
2659 &dra7xx_l3_main_1__hdmi,
2660 &dra7xx_l4_per1__elm,
2661 &dra7xx_l4_wkup__gpio1,
2662 &dra7xx_l4_per1__gpio2,
2663 &dra7xx_l4_per1__gpio3,
2664 &dra7xx_l4_per1__gpio4,
2665 &dra7xx_l4_per1__gpio5,
2666 &dra7xx_l4_per1__gpio6,
2667 &dra7xx_l4_per1__gpio7,
2668 &dra7xx_l4_per1__gpio8,
2669 &dra7xx_l3_main_1__gpmc,
2670 &dra7xx_l4_per1__hdq1w,
2671 &dra7xx_l4_per1__i2c1,
2672 &dra7xx_l4_per1__i2c2,
2673 &dra7xx_l4_per1__i2c3,
2674 &dra7xx_l4_per1__i2c4,
2675 &dra7xx_l4_per1__i2c5,
2676 &dra7xx_l4_per1__mcspi1,
2677 &dra7xx_l4_per1__mcspi2,
2678 &dra7xx_l4_per1__mcspi3,
2679 &dra7xx_l4_per1__mcspi4,
2680 &dra7xx_l4_per1__mmc1,
2681 &dra7xx_l4_per1__mmc2,
2682 &dra7xx_l4_per1__mmc3,
2683 &dra7xx_l4_per1__mmc4,
2684 &dra7xx_l4_cfg__mpu,
2685 &dra7xx_l4_cfg__ocp2scp1,
2686 &dra7xx_l3_main_1__qspi,
2687 &dra7xx_l4_cfg__sata,
2688 &dra7xx_l4_cfg__smartreflex_core,
2689 &dra7xx_l4_cfg__smartreflex_mpu,
2690 &dra7xx_l4_cfg__spinlock,
2691 &dra7xx_l4_wkup__timer1,
2692 &dra7xx_l4_per1__timer2,
2693 &dra7xx_l4_per1__timer3,
2694 &dra7xx_l4_per1__timer4,
2695 &dra7xx_l4_per3__timer5,
2696 &dra7xx_l4_per3__timer6,
2697 &dra7xx_l4_per3__timer7,
2698 &dra7xx_l4_per3__timer8,
2699 &dra7xx_l4_per1__timer9,
2700 &dra7xx_l4_per1__timer10,
2701 &dra7xx_l4_per1__timer11,
2702 &dra7xx_l4_per1__uart1,
2703 &dra7xx_l4_per1__uart2,
2704 &dra7xx_l4_per1__uart3,
2705 &dra7xx_l4_per1__uart4,
2706 &dra7xx_l4_per1__uart5,
2707 &dra7xx_l4_per1__uart6,
2708 &dra7xx_l4_per3__usb_otg_ss1,
2709 &dra7xx_l4_per3__usb_otg_ss2,
2710 &dra7xx_l4_per3__usb_otg_ss3,
2711 &dra7xx_l4_per3__usb_otg_ss4,
2712 &dra7xx_l3_main_1__vcp1,
2713 &dra7xx_l4_per2__vcp1,
2714 &dra7xx_l3_main_1__vcp2,
2715 &dra7xx_l4_per2__vcp2,
2716 &dra7xx_l4_wkup__wd_timer2,
2717 NULL,
2718};
2719
2720int __init dra7xx_hwmod_init(void)
2721{
2722 omap_hwmod_init();
2723 return omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
2724}
diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h
index e4d7bd6f94b8..baf3d8bf6bea 100644
--- a/arch/arm/mach-omap2/powerdomain.h
+++ b/arch/arm/mach-omap2/powerdomain.h
@@ -256,6 +256,7 @@ extern void omap3xxx_powerdomains_init(void);
256extern void am33xx_powerdomains_init(void); 256extern void am33xx_powerdomains_init(void);
257extern void omap44xx_powerdomains_init(void); 257extern void omap44xx_powerdomains_init(void);
258extern void omap54xx_powerdomains_init(void); 258extern void omap54xx_powerdomains_init(void);
259extern void dra7xx_powerdomains_init(void);
259 260
260extern struct pwrdm_ops omap2_pwrdm_operations; 261extern struct pwrdm_ops omap2_pwrdm_operations;
261extern struct pwrdm_ops omap3_pwrdm_operations; 262extern struct pwrdm_ops omap3_pwrdm_operations;
diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c
index e2d4bd804523..328c1037cb60 100644
--- a/arch/arm/mach-omap2/powerdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c
@@ -336,6 +336,13 @@ static struct powerdomain dpll5_pwrdm = {
336 .voltdm = { .name = "core" }, 336 .voltdm = { .name = "core" },
337}; 337};
338 338
339static struct powerdomain alwon_81xx_pwrdm = {
340 .name = "alwon_pwrdm",
341 .prcm_offs = TI81XX_PRM_ALWON_MOD,
342 .pwrsts = PWRSTS_OFF_ON,
343 .voltdm = { .name = "core" },
344};
345
339static struct powerdomain device_81xx_pwrdm = { 346static struct powerdomain device_81xx_pwrdm = {
340 .name = "device_pwrdm", 347 .name = "device_pwrdm",
341 .prcm_offs = TI81XX_PRM_DEVICE_MOD, 348 .prcm_offs = TI81XX_PRM_DEVICE_MOD,
@@ -442,6 +449,7 @@ static struct powerdomain *powerdomains_am35x[] __initdata = {
442}; 449};
443 450
444static struct powerdomain *powerdomains_ti81xx[] __initdata = { 451static struct powerdomain *powerdomains_ti81xx[] __initdata = {
452 &alwon_81xx_pwrdm,
445 &device_81xx_pwrdm, 453 &device_81xx_pwrdm,
446 &active_816x_pwrdm, 454 &active_816x_pwrdm,
447 &default_816x_pwrdm, 455 &default_816x_pwrdm,
diff --git a/arch/arm/mach-omap2/powerdomains7xx_data.c b/arch/arm/mach-omap2/powerdomains7xx_data.c
new file mode 100644
index 000000000000..48151d1cfde0
--- /dev/null
+++ b/arch/arm/mach-omap2/powerdomains7xx_data.c
@@ -0,0 +1,454 @@
1/*
2 * DRA7xx Power domains framework
3 *
4 * Copyright (C) 2009-2013 Texas Instruments, Inc.
5 * Copyright (C) 2009-2011 Nokia Corporation
6 *
7 * Generated by code originally written by:
8 * Abhijit Pagare (abhijitpagare@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 * Paul Walmsley (paul@pwsan.com)
11 *
12 * This file is automatically generated from the OMAP hardware databases.
13 * We respectfully ask that any modifications to this file be coordinated
14 * with the public linux-omap@vger.kernel.org mailing list and the
15 * authors above to ensure that the autogeneration scripts are kept
16 * up-to-date with the file contents.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25
26#include "powerdomain.h"
27
28#include "prcm-common.h"
29#include "prcm44xx.h"
30#include "prm7xx.h"
31#include "prcm_mpu7xx.h"
32
33/* iva_7xx_pwrdm: IVA-HD power domain */
34static struct powerdomain iva_7xx_pwrdm = {
35 .name = "iva_pwrdm",
36 .prcm_offs = DRA7XX_PRM_IVA_INST,
37 .prcm_partition = DRA7XX_PRM_PARTITION,
38 .pwrsts = PWRSTS_OFF_RET_ON,
39 .pwrsts_logic_ret = PWRSTS_OFF,
40 .banks = 4,
41 .pwrsts_mem_ret = {
42 [0] = PWRSTS_OFF_RET, /* hwa_mem */
43 [1] = PWRSTS_OFF_RET, /* sl2_mem */
44 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
45 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
46 },
47 .pwrsts_mem_on = {
48 [0] = PWRSTS_OFF_RET, /* hwa_mem */
49 [1] = PWRSTS_OFF_RET, /* sl2_mem */
50 [2] = PWRSTS_OFF_RET, /* tcm1_mem */
51 [3] = PWRSTS_OFF_RET, /* tcm2_mem */
52 },
53 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
54};
55
56/* rtc_7xx_pwrdm: */
57static struct powerdomain rtc_7xx_pwrdm = {
58 .name = "rtc_pwrdm",
59 .prcm_offs = DRA7XX_PRM_RTC_INST,
60 .prcm_partition = DRA7XX_PRM_PARTITION,
61 .pwrsts = PWRSTS_ON,
62};
63
64/* custefuse_7xx_pwrdm: Customer efuse controller power domain */
65static struct powerdomain custefuse_7xx_pwrdm = {
66 .name = "custefuse_pwrdm",
67 .prcm_offs = DRA7XX_PRM_CUSTEFUSE_INST,
68 .prcm_partition = DRA7XX_PRM_PARTITION,
69 .pwrsts = PWRSTS_OFF_ON,
70 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
71};
72
73/* ipu_7xx_pwrdm: Audio back end power domain */
74static struct powerdomain ipu_7xx_pwrdm = {
75 .name = "ipu_pwrdm",
76 .prcm_offs = DRA7XX_PRM_IPU_INST,
77 .prcm_partition = DRA7XX_PRM_PARTITION,
78 .pwrsts = PWRSTS_OFF_RET_ON,
79 .pwrsts_logic_ret = PWRSTS_OFF,
80 .banks = 2,
81 .pwrsts_mem_ret = {
82 [0] = PWRSTS_OFF_RET, /* aessmem */
83 [1] = PWRSTS_OFF_RET, /* periphmem */
84 },
85 .pwrsts_mem_on = {
86 [0] = PWRSTS_OFF_RET, /* aessmem */
87 [1] = PWRSTS_OFF_RET, /* periphmem */
88 },
89 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
90};
91
92/* dss_7xx_pwrdm: Display subsystem power domain */
93static struct powerdomain dss_7xx_pwrdm = {
94 .name = "dss_pwrdm",
95 .prcm_offs = DRA7XX_PRM_DSS_INST,
96 .prcm_partition = DRA7XX_PRM_PARTITION,
97 .pwrsts = PWRSTS_OFF_RET_ON,
98 .pwrsts_logic_ret = PWRSTS_OFF,
99 .banks = 1,
100 .pwrsts_mem_ret = {
101 [0] = PWRSTS_OFF_RET, /* dss_mem */
102 },
103 .pwrsts_mem_on = {
104 [0] = PWRSTS_OFF_RET, /* dss_mem */
105 },
106 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
107};
108
109/* l4per_7xx_pwrdm: Target peripherals power domain */
110static struct powerdomain l4per_7xx_pwrdm = {
111 .name = "l4per_pwrdm",
112 .prcm_offs = DRA7XX_PRM_L4PER_INST,
113 .prcm_partition = DRA7XX_PRM_PARTITION,
114 .pwrsts = PWRSTS_RET_ON,
115 .pwrsts_logic_ret = PWRSTS_OFF_RET,
116 .banks = 2,
117 .pwrsts_mem_ret = {
118 [0] = PWRSTS_OFF_RET, /* nonretained_bank */
119 [1] = PWRSTS_OFF_RET, /* retained_bank */
120 },
121 .pwrsts_mem_on = {
122 [0] = PWRSTS_OFF_RET, /* nonretained_bank */
123 [1] = PWRSTS_OFF_RET, /* retained_bank */
124 },
125 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
126};
127
128/* gpu_7xx_pwrdm: 3D accelerator power domain */
129static struct powerdomain gpu_7xx_pwrdm = {
130 .name = "gpu_pwrdm",
131 .prcm_offs = DRA7XX_PRM_GPU_INST,
132 .prcm_partition = DRA7XX_PRM_PARTITION,
133 .pwrsts = PWRSTS_OFF_ON,
134 .banks = 1,
135 .pwrsts_mem_ret = {
136 [0] = PWRSTS_OFF_RET, /* gpu_mem */
137 },
138 .pwrsts_mem_on = {
139 [0] = PWRSTS_OFF_RET, /* gpu_mem */
140 },
141 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
142};
143
144/* wkupaon_7xx_pwrdm: Wake-up power domain */
145static struct powerdomain wkupaon_7xx_pwrdm = {
146 .name = "wkupaon_pwrdm",
147 .prcm_offs = DRA7XX_PRM_WKUPAON_INST,
148 .prcm_partition = DRA7XX_PRM_PARTITION,
149 .pwrsts = PWRSTS_ON,
150 .banks = 1,
151 .pwrsts_mem_ret = {
152 },
153 .pwrsts_mem_on = {
154 [0] = PWRSTS_ON, /* wkup_bank */
155 },
156};
157
158/* core_7xx_pwrdm: CORE power domain */
159static struct powerdomain core_7xx_pwrdm = {
160 .name = "core_pwrdm",
161 .prcm_offs = DRA7XX_PRM_CORE_INST,
162 .prcm_partition = DRA7XX_PRM_PARTITION,
163 .pwrsts = PWRSTS_RET_ON,
164 .pwrsts_logic_ret = PWRSTS_OFF_RET,
165 .banks = 5,
166 .pwrsts_mem_ret = {
167 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
168 [1] = PWRSTS_OFF_RET, /* core_ocmram */
169 [2] = PWRSTS_OFF_RET, /* core_other_bank */
170 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
171 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
172 },
173 .pwrsts_mem_on = {
174 [0] = PWRSTS_OFF_RET, /* core_nret_bank */
175 [1] = PWRSTS_OFF_RET, /* core_ocmram */
176 [2] = PWRSTS_OFF_RET, /* core_other_bank */
177 [3] = PWRSTS_OFF_RET, /* ipu_l2ram */
178 [4] = PWRSTS_OFF_RET, /* ipu_unicache */
179 },
180 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
181};
182
183/* coreaon_7xx_pwrdm: Always ON logic that sits in VDD_CORE voltage domain */
184static struct powerdomain coreaon_7xx_pwrdm = {
185 .name = "coreaon_pwrdm",
186 .prcm_offs = DRA7XX_PRM_COREAON_INST,
187 .prcm_partition = DRA7XX_PRM_PARTITION,
188 .pwrsts = PWRSTS_ON,
189};
190
191/* cpu0_7xx_pwrdm: MPU0 processor and Neon coprocessor power domain */
192static struct powerdomain cpu0_7xx_pwrdm = {
193 .name = "cpu0_pwrdm",
194 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C0_INST,
195 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
196 .pwrsts = PWRSTS_OFF_RET_ON,
197 .pwrsts_logic_ret = PWRSTS_OFF_RET,
198 .banks = 1,
199 .pwrsts_mem_ret = {
200 [0] = PWRSTS_OFF_RET, /* cpu0_l1 */
201 },
202 .pwrsts_mem_on = {
203 [0] = PWRSTS_ON, /* cpu0_l1 */
204 },
205};
206
207/* cpu1_7xx_pwrdm: MPU1 processor and Neon coprocessor power domain */
208static struct powerdomain cpu1_7xx_pwrdm = {
209 .name = "cpu1_pwrdm",
210 .prcm_offs = DRA7XX_MPU_PRCM_PRM_C1_INST,
211 .prcm_partition = DRA7XX_MPU_PRCM_PARTITION,
212 .pwrsts = PWRSTS_OFF_RET_ON,
213 .pwrsts_logic_ret = PWRSTS_OFF_RET,
214 .banks = 1,
215 .pwrsts_mem_ret = {
216 [0] = PWRSTS_OFF_RET, /* cpu1_l1 */
217 },
218 .pwrsts_mem_on = {
219 [0] = PWRSTS_ON, /* cpu1_l1 */
220 },
221};
222
223/* vpe_7xx_pwrdm: */
224static struct powerdomain vpe_7xx_pwrdm = {
225 .name = "vpe_pwrdm",
226 .prcm_offs = DRA7XX_PRM_VPE_INST,
227 .prcm_partition = DRA7XX_PRM_PARTITION,
228 .pwrsts = PWRSTS_OFF_RET_ON,
229 .pwrsts_logic_ret = PWRSTS_OFF_RET,
230 .banks = 1,
231 .pwrsts_mem_ret = {
232 [0] = PWRSTS_OFF_RET, /* vpe_bank */
233 },
234 .pwrsts_mem_on = {
235 [0] = PWRSTS_OFF_RET, /* vpe_bank */
236 },
237 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
238};
239
240/* mpu_7xx_pwrdm: Modena processor and the Neon coprocessor power domain */
241static struct powerdomain mpu_7xx_pwrdm = {
242 .name = "mpu_pwrdm",
243 .prcm_offs = DRA7XX_PRM_MPU_INST,
244 .prcm_partition = DRA7XX_PRM_PARTITION,
245 .pwrsts = PWRSTS_RET_ON,
246 .pwrsts_logic_ret = PWRSTS_OFF_RET,
247 .banks = 2,
248 .pwrsts_mem_ret = {
249 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
250 [1] = PWRSTS_RET, /* mpu_ram */
251 },
252 .pwrsts_mem_on = {
253 [0] = PWRSTS_OFF_RET, /* mpu_l2 */
254 [1] = PWRSTS_OFF_RET, /* mpu_ram */
255 },
256};
257
258/* l3init_7xx_pwrdm: L3 initators pheripherals power domain */
259static struct powerdomain l3init_7xx_pwrdm = {
260 .name = "l3init_pwrdm",
261 .prcm_offs = DRA7XX_PRM_L3INIT_INST,
262 .prcm_partition = DRA7XX_PRM_PARTITION,
263 .pwrsts = PWRSTS_RET_ON,
264 .pwrsts_logic_ret = PWRSTS_OFF_RET,
265 .banks = 3,
266 .pwrsts_mem_ret = {
267 [0] = PWRSTS_OFF_RET, /* gmac_bank */
268 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */
269 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
270 },
271 .pwrsts_mem_on = {
272 [0] = PWRSTS_OFF_RET, /* gmac_bank */
273 [1] = PWRSTS_OFF_RET, /* l3init_bank1 */
274 [2] = PWRSTS_OFF_RET, /* l3init_bank2 */
275 },
276 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
277};
278
279/* eve3_7xx_pwrdm: */
280static struct powerdomain eve3_7xx_pwrdm = {
281 .name = "eve3_pwrdm",
282 .prcm_offs = DRA7XX_PRM_EVE3_INST,
283 .prcm_partition = DRA7XX_PRM_PARTITION,
284 .pwrsts = PWRSTS_OFF_ON,
285 .banks = 1,
286 .pwrsts_mem_ret = {
287 [0] = PWRSTS_OFF_RET, /* eve3_bank */
288 },
289 .pwrsts_mem_on = {
290 [0] = PWRSTS_OFF_RET, /* eve3_bank */
291 },
292 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
293};
294
295/* emu_7xx_pwrdm: Emulation power domain */
296static struct powerdomain emu_7xx_pwrdm = {
297 .name = "emu_pwrdm",
298 .prcm_offs = DRA7XX_PRM_EMU_INST,
299 .prcm_partition = DRA7XX_PRM_PARTITION,
300 .pwrsts = PWRSTS_OFF_ON,
301 .banks = 1,
302 .pwrsts_mem_ret = {
303 [0] = PWRSTS_OFF_RET, /* emu_bank */
304 },
305 .pwrsts_mem_on = {
306 [0] = PWRSTS_OFF_RET, /* emu_bank */
307 },
308};
309
310/* dsp2_7xx_pwrdm: */
311static struct powerdomain dsp2_7xx_pwrdm = {
312 .name = "dsp2_pwrdm",
313 .prcm_offs = DRA7XX_PRM_DSP2_INST,
314 .prcm_partition = DRA7XX_PRM_PARTITION,
315 .pwrsts = PWRSTS_OFF_ON,
316 .banks = 3,
317 .pwrsts_mem_ret = {
318 [0] = PWRSTS_OFF_RET, /* dsp2_edma */
319 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */
320 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
321 },
322 .pwrsts_mem_on = {
323 [0] = PWRSTS_OFF_RET, /* dsp2_edma */
324 [1] = PWRSTS_OFF_RET, /* dsp2_l1 */
325 [2] = PWRSTS_OFF_RET, /* dsp2_l2 */
326 },
327 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
328};
329
330/* dsp1_7xx_pwrdm: Tesla processor power domain */
331static struct powerdomain dsp1_7xx_pwrdm = {
332 .name = "dsp1_pwrdm",
333 .prcm_offs = DRA7XX_PRM_DSP1_INST,
334 .prcm_partition = DRA7XX_PRM_PARTITION,
335 .pwrsts = PWRSTS_OFF_ON,
336 .banks = 3,
337 .pwrsts_mem_ret = {
338 [0] = PWRSTS_OFF_RET, /* dsp1_edma */
339 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */
340 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
341 },
342 .pwrsts_mem_on = {
343 [0] = PWRSTS_OFF_RET, /* dsp1_edma */
344 [1] = PWRSTS_OFF_RET, /* dsp1_l1 */
345 [2] = PWRSTS_OFF_RET, /* dsp1_l2 */
346 },
347 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
348};
349
350/* cam_7xx_pwrdm: Camera subsystem power domain */
351static struct powerdomain cam_7xx_pwrdm = {
352 .name = "cam_pwrdm",
353 .prcm_offs = DRA7XX_PRM_CAM_INST,
354 .prcm_partition = DRA7XX_PRM_PARTITION,
355 .pwrsts = PWRSTS_OFF_ON,
356 .banks = 1,
357 .pwrsts_mem_ret = {
358 [0] = PWRSTS_OFF_RET, /* vip_bank */
359 },
360 .pwrsts_mem_on = {
361 [0] = PWRSTS_OFF_RET, /* vip_bank */
362 },
363 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
364};
365
366/* eve4_7xx_pwrdm: */
367static struct powerdomain eve4_7xx_pwrdm = {
368 .name = "eve4_pwrdm",
369 .prcm_offs = DRA7XX_PRM_EVE4_INST,
370 .prcm_partition = DRA7XX_PRM_PARTITION,
371 .pwrsts = PWRSTS_OFF_ON,
372 .banks = 1,
373 .pwrsts_mem_ret = {
374 [0] = PWRSTS_OFF_RET, /* eve4_bank */
375 },
376 .pwrsts_mem_on = {
377 [0] = PWRSTS_OFF_RET, /* eve4_bank */
378 },
379 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
380};
381
382/* eve2_7xx_pwrdm: */
383static struct powerdomain eve2_7xx_pwrdm = {
384 .name = "eve2_pwrdm",
385 .prcm_offs = DRA7XX_PRM_EVE2_INST,
386 .prcm_partition = DRA7XX_PRM_PARTITION,
387 .pwrsts = PWRSTS_OFF_ON,
388 .banks = 1,
389 .pwrsts_mem_ret = {
390 [0] = PWRSTS_OFF_RET, /* eve2_bank */
391 },
392 .pwrsts_mem_on = {
393 [0] = PWRSTS_OFF_RET, /* eve2_bank */
394 },
395 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
396};
397
398/* eve1_7xx_pwrdm: */
399static struct powerdomain eve1_7xx_pwrdm = {
400 .name = "eve1_pwrdm",
401 .prcm_offs = DRA7XX_PRM_EVE1_INST,
402 .prcm_partition = DRA7XX_PRM_PARTITION,
403 .pwrsts = PWRSTS_OFF_ON,
404 .banks = 1,
405 .pwrsts_mem_ret = {
406 [0] = PWRSTS_OFF_RET, /* eve1_bank */
407 },
408 .pwrsts_mem_on = {
409 [0] = PWRSTS_OFF_RET, /* eve1_bank */
410 },
411 .flags = PWRDM_HAS_LOWPOWERSTATECHANGE,
412};
413
414/*
415 * The following power domains are not under SW control
416 *
417 * mpuaon
418 * mmaon
419 */
420
421/* As powerdomains are added or removed above, this list must also be changed */
422static struct powerdomain *powerdomains_dra7xx[] __initdata = {
423 &iva_7xx_pwrdm,
424 &rtc_7xx_pwrdm,
425 &custefuse_7xx_pwrdm,
426 &ipu_7xx_pwrdm,
427 &dss_7xx_pwrdm,
428 &l4per_7xx_pwrdm,
429 &gpu_7xx_pwrdm,
430 &wkupaon_7xx_pwrdm,
431 &core_7xx_pwrdm,
432 &coreaon_7xx_pwrdm,
433 &cpu0_7xx_pwrdm,
434 &cpu1_7xx_pwrdm,
435 &vpe_7xx_pwrdm,
436 &mpu_7xx_pwrdm,
437 &l3init_7xx_pwrdm,
438 &eve3_7xx_pwrdm,
439 &emu_7xx_pwrdm,
440 &dsp2_7xx_pwrdm,
441 &dsp1_7xx_pwrdm,
442 &cam_7xx_pwrdm,
443 &eve4_7xx_pwrdm,
444 &eve2_7xx_pwrdm,
445 &eve1_7xx_pwrdm,
446 NULL
447};
448
449void __init dra7xx_powerdomains_init(void)
450{
451 pwrdm_register_platform_funcs(&omap4_pwrdm_operations);
452 pwrdm_register_pwrdms(powerdomains_dra7xx);
453 pwrdm_complete_init();
454}
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index ff1ac4a82a04..0e841fd9498a 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -58,6 +58,7 @@
58#define TI816X_PRM_IVAHD1_MOD 0x0d00 58#define TI816X_PRM_IVAHD1_MOD 0x0d00
59#define TI816X_PRM_IVAHD2_MOD 0x0e00 59#define TI816X_PRM_IVAHD2_MOD 0x0e00
60#define TI816X_PRM_SGX_MOD 0x0f00 60#define TI816X_PRM_SGX_MOD 0x0f00
61#define TI81XX_PRM_ALWON_MOD 0x1800
61 62
62/* 24XX register bits shared between CM & PRM registers */ 63/* 24XX register bits shared between CM & PRM registers */
63 64
diff --git a/arch/arm/mach-omap2/prcm44xx.h b/arch/arm/mach-omap2/prcm44xx.h
index f429cdd5a118..4fea2cfdf2c3 100644
--- a/arch/arm/mach-omap2/prcm44xx.h
+++ b/arch/arm/mach-omap2/prcm44xx.h
@@ -38,6 +38,11 @@
38#define OMAP54XX_SCRM_PARTITION 4 38#define OMAP54XX_SCRM_PARTITION 4
39#define OMAP54XX_PRCM_MPU_PARTITION 5 39#define OMAP54XX_PRCM_MPU_PARTITION 5
40 40
41#define DRA7XX_PRM_PARTITION 1
42#define DRA7XX_CM_CORE_AON_PARTITION 2
43#define DRA7XX_CM_CORE_PARTITION 3
44#define DRA7XX_MPU_PRCM_PARTITION 5
45
41/* 46/*
42 * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition 47 * OMAP4_MAX_PRCM_PARTITIONS: set to the highest value of the PRCM partition
43 * IDs, plus one 48 * IDs, plus one
diff --git a/arch/arm/mach-omap2/prcm_mpu7xx.h b/arch/arm/mach-omap2/prcm_mpu7xx.h
new file mode 100644
index 000000000000..9ebb5ce0878f
--- /dev/null
+++ b/arch/arm/mach-omap2/prcm_mpu7xx.h
@@ -0,0 +1,78 @@
1/*
2 * DRA7xx PRCM MPU instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
23#define __ARCH_ARM_MACH_OMAP2_PRCM_MPU7XX_H
24
25#include "prcm_mpu_44xx_54xx.h"
26
27#define DRA7XX_PRCM_MPU_BASE 0x48243000
28
29#define DRA7XX_PRCM_MPU_REGADDR(inst, reg) \
30 OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))
31
32/* MPU_PRCM instances */
33#define DRA7XX_MPU_PRCM_OCP_SOCKET_INST 0x0000
34#define DRA7XX_MPU_PRCM_DEVICE_INST 0x0200
35#define DRA7XX_MPU_PRCM_PRM_C0_INST 0x0400
36#define DRA7XX_MPU_PRCM_CM_C0_INST 0x0600
37#define DRA7XX_MPU_PRCM_PRM_C1_INST 0x0800
38#define DRA7XX_MPU_PRCM_CM_C1_INST 0x0a00
39
40/* PRCM_MPU clockdomain register offsets (from instance start) */
41#define DRA7XX_MPU_PRCM_CM_C0_CPU0_CDOFFS 0x0000
42#define DRA7XX_MPU_PRCM_CM_C1_CPU1_CDOFFS 0x0000
43
44
45/* MPU_PRCM */
46
47/* MPU_PRCM.PRCM_MPU_OCP_SOCKET register offsets */
48#define DRA7XX_REVISION_PRCM_MPU_OFFSET 0x0000
49
50/* MPU_PRCM.PRCM_MPU_DEVICE register offsets */
51#define DRA7XX_PRM_FRAC_INCREMENTER_NUMERATOR_OFFSET 0x0010
52#define DRA7XX_PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x0014
53
54/* MPU_PRCM.PRCM_MPU_PRM_C0 register offsets */
55#define DRA7XX_PM_CPU0_PWRSTCTRL_OFFSET 0x0000
56#define DRA7XX_PM_CPU0_PWRSTST_OFFSET 0x0004
57#define DRA7XX_RM_CPU0_CPU0_RSTCTRL_OFFSET 0x0010
58#define DRA7XX_RM_CPU0_CPU0_RSTST_OFFSET 0x0014
59#define DRA7XX_RM_CPU0_CPU0_CONTEXT_OFFSET 0x0024
60
61/* MPU_PRCM.PRCM_MPU_CM_C0 register offsets */
62#define DRA7XX_CM_CPU0_CLKSTCTRL_OFFSET 0x0000
63#define DRA7XX_CM_CPU0_CPU0_CLKCTRL_OFFSET 0x0020
64#define DRA7XX_CM_CPU0_CPU0_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C0_INST, 0x0020)
65
66/* MPU_PRCM.PRCM_MPU_PRM_C1 register offsets */
67#define DRA7XX_PM_CPU1_PWRSTCTRL_OFFSET 0x0000
68#define DRA7XX_PM_CPU1_PWRSTST_OFFSET 0x0004
69#define DRA7XX_RM_CPU1_CPU1_RSTCTRL_OFFSET 0x0010
70#define DRA7XX_RM_CPU1_CPU1_RSTST_OFFSET 0x0014
71#define DRA7XX_RM_CPU1_CPU1_CONTEXT_OFFSET 0x0024
72
73/* MPU_PRCM.PRCM_MPU_CM_C1 register offsets */
74#define DRA7XX_CM_CPU1_CLKSTCTRL_OFFSET 0x0000
75#define DRA7XX_CM_CPU1_CPU1_CLKCTRL_OFFSET 0x0020
76#define DRA7XX_CM_CPU1_CPU1_CLKCTRL DRA7XX_MPU_PRCM_REGADDR(DRA7XX_MPU_PRCM_CM_C1_INST, 0x0020)
77
78#endif
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 415c7e0c9393..03a603476cfc 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -620,6 +620,15 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
620 return 0; 620 return 0;
621} 621}
622 622
623static int omap4_check_vcvp(void)
624{
625 /* No VC/VP on dra7xx devices */
626 if (soc_is_dra7xx())
627 return 0;
628
629 return 1;
630}
631
623struct pwrdm_ops omap4_pwrdm_operations = { 632struct pwrdm_ops omap4_pwrdm_operations = {
624 .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst, 633 .pwrdm_set_next_pwrst = omap4_pwrdm_set_next_pwrst,
625 .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst, 634 .pwrdm_read_next_pwrst = omap4_pwrdm_read_next_pwrst,
@@ -637,6 +646,7 @@ struct pwrdm_ops omap4_pwrdm_operations = {
637 .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst, 646 .pwrdm_set_mem_onst = omap4_pwrdm_set_mem_onst,
638 .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst, 647 .pwrdm_set_mem_retst = omap4_pwrdm_set_mem_retst,
639 .pwrdm_wait_transition = omap4_pwrdm_wait_transition, 648 .pwrdm_wait_transition = omap4_pwrdm_wait_transition,
649 .pwrdm_has_voltdm = omap4_check_vcvp,
640}; 650};
641 651
642/* 652/*
@@ -650,7 +660,7 @@ static struct prm_ll_data omap44xx_prm_ll_data = {
650 660
651int __init omap44xx_prm_init(void) 661int __init omap44xx_prm_init(void)
652{ 662{
653 if (!cpu_is_omap44xx() && !soc_is_omap54xx()) 663 if (!cpu_is_omap44xx() && !soc_is_omap54xx() && !soc_is_dra7xx())
654 return 0; 664 return 0;
655 665
656 return prm_register(&omap44xx_prm_ll_data); 666 return prm_register(&omap44xx_prm_ll_data);
diff --git a/arch/arm/mach-omap2/prm7xx.h b/arch/arm/mach-omap2/prm7xx.h
new file mode 100644
index 000000000000..d92a8404edc7
--- /dev/null
+++ b/arch/arm/mach-omap2/prm7xx.h
@@ -0,0 +1,678 @@
1/*
2 * DRA7xx PRM instance offset macros
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Generated by code originally written by:
7 * Paul Walmsley (paul@pwsan.com)
8 * Rajendra Nayak (rnayak@ti.com)
9 * Benoit Cousson (b-cousson@ti.com)
10 *
11 * This file is automatically generated from the OMAP hardware databases.
12 * We respectfully ask that any modifications to this file be coordinated
13 * with the public linux-omap@vger.kernel.org mailing list and the
14 * authors above to ensure that the autogeneration scripts are kept
15 * up-to-date with the file contents.
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License version 2 as
19 * published by the Free Software Foundation.
20 */
21
22#ifndef __ARCH_ARM_MACH_OMAP2_PRM7XX_H
23#define __ARCH_ARM_MACH_OMAP2_PRM7XX_H
24
25#include "prm44xx_54xx.h"
26#include "prcm-common.h"
27#include "prm.h"
28
29#define DRA7XX_PRM_BASE 0x4ae06000
30
31#define DRA7XX_PRM_REGADDR(inst, reg) \
32 OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg))
33
34
35/* PRM instances */
36#define DRA7XX_PRM_OCP_SOCKET_INST 0x0000
37#define DRA7XX_PRM_CKGEN_INST 0x0100
38#define DRA7XX_PRM_MPU_INST 0x0300
39#define DRA7XX_PRM_DSP1_INST 0x0400
40#define DRA7XX_PRM_IPU_INST 0x0500
41#define DRA7XX_PRM_COREAON_INST 0x0628
42#define DRA7XX_PRM_CORE_INST 0x0700
43#define DRA7XX_PRM_IVA_INST 0x0f00
44#define DRA7XX_PRM_CAM_INST 0x1000
45#define DRA7XX_PRM_DSS_INST 0x1100
46#define DRA7XX_PRM_GPU_INST 0x1200
47#define DRA7XX_PRM_L3INIT_INST 0x1300
48#define DRA7XX_PRM_L4PER_INST 0x1400
49#define DRA7XX_PRM_CUSTEFUSE_INST 0x1600
50#define DRA7XX_PRM_WKUPAON_INST 0x1724
51#define DRA7XX_PRM_WKUPAON_CM_INST 0x1800
52#define DRA7XX_PRM_EMU_INST 0x1900
53#define DRA7XX_PRM_EMU_CM_INST 0x1a00
54#define DRA7XX_PRM_DSP2_INST 0x1b00
55#define DRA7XX_PRM_EVE1_INST 0x1b40
56#define DRA7XX_PRM_EVE2_INST 0x1b80
57#define DRA7XX_PRM_EVE3_INST 0x1bc0
58#define DRA7XX_PRM_EVE4_INST 0x1c00
59#define DRA7XX_PRM_RTC_INST 0x1c60
60#define DRA7XX_PRM_VPE_INST 0x1c80
61#define DRA7XX_PRM_DEVICE_INST 0x1d00
62#define DRA7XX_PRM_INSTR_INST 0x1f00
63
64/* PRM clockdomain register offsets (from instance start) */
65#define DRA7XX_PRM_WKUPAON_CM_WKUPAON_CDOFFS 0x0000
66#define DRA7XX_PRM_EMU_CM_EMU_CDOFFS 0x0000
67
68/* PRM */
69
70/* PRM.OCP_SOCKET_PRM register offsets */
71#define DRA7XX_REVISION_PRM_OFFSET 0x0000
72#define DRA7XX_PRM_IRQSTATUS_MPU_OFFSET 0x0010
73#define DRA7XX_PRM_IRQSTATUS_MPU_2_OFFSET 0x0014
74#define DRA7XX_PRM_IRQENABLE_MPU_OFFSET 0x0018
75#define DRA7XX_PRM_IRQENABLE_MPU_2_OFFSET 0x001c
76#define DRA7XX_PRM_IRQSTATUS_IPU2_OFFSET 0x0020
77#define DRA7XX_PRM_IRQENABLE_IPU2_OFFSET 0x0028
78#define DRA7XX_PRM_IRQSTATUS_DSP1_OFFSET 0x0030
79#define DRA7XX_PRM_IRQENABLE_DSP1_OFFSET 0x0038
80#define DRA7XX_CM_PRM_PROFILING_CLKCTRL_OFFSET 0x0040
81#define DRA7XX_CM_PRM_PROFILING_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_OCP_SOCKET_INST, 0x0040)
82#define DRA7XX_PRM_IRQENABLE_DSP2_OFFSET 0x0044
83#define DRA7XX_PRM_IRQENABLE_EVE1_OFFSET 0x0048
84#define DRA7XX_PRM_IRQENABLE_EVE2_OFFSET 0x004c
85#define DRA7XX_PRM_IRQENABLE_EVE3_OFFSET 0x0050
86#define DRA7XX_PRM_IRQENABLE_EVE4_OFFSET 0x0054
87#define DRA7XX_PRM_IRQENABLE_IPU1_OFFSET 0x0058
88#define DRA7XX_PRM_IRQSTATUS_DSP2_OFFSET 0x005c
89#define DRA7XX_PRM_IRQSTATUS_EVE1_OFFSET 0x0060
90#define DRA7XX_PRM_IRQSTATUS_EVE2_OFFSET 0x0064
91#define DRA7XX_PRM_IRQSTATUS_EVE3_OFFSET 0x0068
92#define DRA7XX_PRM_IRQSTATUS_EVE4_OFFSET 0x006c
93#define DRA7XX_PRM_IRQSTATUS_IPU1_OFFSET 0x0070
94#define DRA7XX_PRM_DEBUG_CFG1_OFFSET 0x00e4
95#define DRA7XX_PRM_DEBUG_CFG2_OFFSET 0x00e8
96#define DRA7XX_PRM_DEBUG_CFG3_OFFSET 0x00ec
97#define DRA7XX_PRM_DEBUG_OUT_OFFSET 0x00f4
98
99/* PRM.CKGEN_PRM register offsets */
100#define DRA7XX_CM_CLKSEL_SYSCLK1_OFFSET 0x0000
101#define DRA7XX_CM_CLKSEL_SYSCLK1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0000)
102#define DRA7XX_CM_CLKSEL_WKUPAON_OFFSET 0x0008
103#define DRA7XX_CM_CLKSEL_WKUPAON DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0008)
104#define DRA7XX_CM_CLKSEL_ABE_PLL_REF_OFFSET 0x000c
105#define DRA7XX_CM_CLKSEL_ABE_PLL_REF DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x000c)
106#define DRA7XX_CM_CLKSEL_SYS_OFFSET 0x0010
107#define DRA7XX_CM_CLKSEL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0010)
108#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS_OFFSET 0x0014
109#define DRA7XX_CM_CLKSEL_ABE_PLL_BYPAS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0014)
110#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS_OFFSET 0x0018
111#define DRA7XX_CM_CLKSEL_ABE_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0018)
112#define DRA7XX_CM_CLKSEL_ABE_24M_OFFSET 0x001c
113#define DRA7XX_CM_CLKSEL_ABE_24M DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x001c)
114#define DRA7XX_CM_CLKSEL_ABE_SYS_OFFSET 0x0020
115#define DRA7XX_CM_CLKSEL_ABE_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0020)
116#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX_OFFSET 0x0024
117#define DRA7XX_CM_CLKSEL_HDMI_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0024)
118#define DRA7XX_CM_CLKSEL_HDMI_TIMER_OFFSET 0x0028
119#define DRA7XX_CM_CLKSEL_HDMI_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0028)
120#define DRA7XX_CM_CLKSEL_MCASP_SYS_OFFSET 0x002c
121#define DRA7XX_CM_CLKSEL_MCASP_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x002c)
122#define DRA7XX_CM_CLKSEL_MLBP_MCASP_OFFSET 0x0030
123#define DRA7XX_CM_CLKSEL_MLBP_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0030)
124#define DRA7XX_CM_CLKSEL_MLB_MCASP_OFFSET 0x0034
125#define DRA7XX_CM_CLKSEL_MLB_MCASP DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0034)
126#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX_OFFSET 0x0038
127#define DRA7XX_CM_CLKSEL_PER_ABE_X1_GFCLK_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0038)
128#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K_OFFSET 0x0040
129#define DRA7XX_CM_CLKSEL_SYS_CLK1_32K DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0040)
130#define DRA7XX_CM_CLKSEL_TIMER_SYS_OFFSET 0x0044
131#define DRA7XX_CM_CLKSEL_TIMER_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0044)
132#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX_OFFSET 0x0048
133#define DRA7XX_CM_CLKSEL_VIDEO1_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0048)
134#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER_OFFSET 0x004c
135#define DRA7XX_CM_CLKSEL_VIDEO1_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x004c)
136#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX_OFFSET 0x0050
137#define DRA7XX_CM_CLKSEL_VIDEO2_MCASP_AUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0050)
138#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER_OFFSET 0x0054
139#define DRA7XX_CM_CLKSEL_VIDEO2_TIMER DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0054)
140#define DRA7XX_CM_CLKSEL_CLKOUTMUX0_OFFSET 0x0058
141#define DRA7XX_CM_CLKSEL_CLKOUTMUX0 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0058)
142#define DRA7XX_CM_CLKSEL_CLKOUTMUX1_OFFSET 0x005c
143#define DRA7XX_CM_CLKSEL_CLKOUTMUX1 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x005c)
144#define DRA7XX_CM_CLKSEL_CLKOUTMUX2_OFFSET 0x0060
145#define DRA7XX_CM_CLKSEL_CLKOUTMUX2 DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0060)
146#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS_OFFSET 0x0064
147#define DRA7XX_CM_CLKSEL_HDMI_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0064)
148#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS_OFFSET 0x0068
149#define DRA7XX_CM_CLKSEL_VIDEO1_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0068)
150#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS_OFFSET 0x006c
151#define DRA7XX_CM_CLKSEL_VIDEO2_PLL_SYS DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x006c)
152#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV_OFFSET 0x0070
153#define DRA7XX_CM_CLKSEL_ABE_CLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0070)
154#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV_OFFSET 0x0074
155#define DRA7XX_CM_CLKSEL_ABE_GICLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0074)
156#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV_OFFSET 0x0078
157#define DRA7XX_CM_CLKSEL_AESS_FCLK_DIV DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0078)
158#define DRA7XX_CM_CLKSEL_EVE_CLK_OFFSET 0x0080
159#define DRA7XX_CM_CLKSEL_EVE_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0080)
160#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX_OFFSET 0x0084
161#define DRA7XX_CM_CLKSEL_USB_OTG_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0084)
162#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX_OFFSET 0x0088
163#define DRA7XX_CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0088)
164#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX_OFFSET 0x008c
165#define DRA7XX_CM_CLKSEL_DSP_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x008c)
166#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX_OFFSET 0x0090
167#define DRA7XX_CM_CLKSEL_EMIF_PHY_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0090)
168#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX_OFFSET 0x0094
169#define DRA7XX_CM_CLKSEL_EMU_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0094)
170#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX_OFFSET 0x0098
171#define DRA7XX_CM_CLKSEL_FUNC_96M_AON_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x0098)
172#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX_OFFSET 0x009c
173#define DRA7XX_CM_CLKSEL_GMAC_250M_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x009c)
174#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX_OFFSET 0x00a0
175#define DRA7XX_CM_CLKSEL_GPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a0)
176#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX_OFFSET 0x00a4
177#define DRA7XX_CM_CLKSEL_HDMI_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a4)
178#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX_OFFSET 0x00a8
179#define DRA7XX_CM_CLKSEL_IVA_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00a8)
180#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX_OFFSET 0x00ac
181#define DRA7XX_CM_CLKSEL_L3INIT_480M_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00ac)
182#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX_OFFSET 0x00b0
183#define DRA7XX_CM_CLKSEL_MPU_GCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b0)
184#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX_OFFSET 0x00b4
185#define DRA7XX_CM_CLKSEL_PCIE1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b4)
186#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX_OFFSET 0x00b8
187#define DRA7XX_CM_CLKSEL_PCIE2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00b8)
188#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX_OFFSET 0x00bc
189#define DRA7XX_CM_CLKSEL_PER_ABE_X1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00bc)
190#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX_OFFSET 0x00c0
191#define DRA7XX_CM_CLKSEL_SATA_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c0)
192#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX_OFFSET 0x00c4
193#define DRA7XX_CM_CLKSEL_SECURE_32K_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c4)
194#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX_OFFSET 0x00c8
195#define DRA7XX_CM_CLKSEL_SYS_CLK1_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00c8)
196#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX_OFFSET 0x00cc
197#define DRA7XX_CM_CLKSEL_SYS_CLK2_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00cc)
198#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX_OFFSET 0x00d0
199#define DRA7XX_CM_CLKSEL_VIDEO1_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d0)
200#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX_OFFSET 0x00d4
201#define DRA7XX_CM_CLKSEL_VIDEO2_CLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d4)
202#define DRA7XX_CM_CLKSEL_ABE_LP_CLK_OFFSET 0x00d8
203#define DRA7XX_CM_CLKSEL_ABE_LP_CLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00d8)
204#define DRA7XX_CM_CLKSEL_ADC_GFCLK_OFFSET 0x00dc
205#define DRA7XX_CM_CLKSEL_ADC_GFCLK DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00dc)
206#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX_OFFSET 0x00e0
207#define DRA7XX_CM_CLKSEL_EVE_GFCLK_CLKOUTMUX DRA7XX_PRM_REGADDR(DRA7XX_PRM_CKGEN_INST, 0x00e0)
208
209/* PRM.MPU_PRM register offsets */
210#define DRA7XX_PM_MPU_PWRSTCTRL_OFFSET 0x0000
211#define DRA7XX_PM_MPU_PWRSTST_OFFSET 0x0004
212#define DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET 0x0024
213
214/* PRM.DSP1_PRM register offsets */
215#define DRA7XX_PM_DSP1_PWRSTCTRL_OFFSET 0x0000
216#define DRA7XX_PM_DSP1_PWRSTST_OFFSET 0x0004
217#define DRA7XX_RM_DSP1_RSTCTRL_OFFSET 0x0010
218#define DRA7XX_RM_DSP1_RSTST_OFFSET 0x0014
219#define DRA7XX_RM_DSP1_DSP1_CONTEXT_OFFSET 0x0024
220
221/* PRM.IPU_PRM register offsets */
222#define DRA7XX_PM_IPU_PWRSTCTRL_OFFSET 0x0000
223#define DRA7XX_PM_IPU_PWRSTST_OFFSET 0x0004
224#define DRA7XX_RM_IPU1_RSTCTRL_OFFSET 0x0010
225#define DRA7XX_RM_IPU1_RSTST_OFFSET 0x0014
226#define DRA7XX_RM_IPU1_IPU1_CONTEXT_OFFSET 0x0024
227#define DRA7XX_PM_IPU_MCASP1_WKDEP_OFFSET 0x0050
228#define DRA7XX_RM_IPU_MCASP1_CONTEXT_OFFSET 0x0054
229#define DRA7XX_PM_IPU_TIMER5_WKDEP_OFFSET 0x0058
230#define DRA7XX_RM_IPU_TIMER5_CONTEXT_OFFSET 0x005c
231#define DRA7XX_PM_IPU_TIMER6_WKDEP_OFFSET 0x0060
232#define DRA7XX_RM_IPU_TIMER6_CONTEXT_OFFSET 0x0064
233#define DRA7XX_PM_IPU_TIMER7_WKDEP_OFFSET 0x0068
234#define DRA7XX_RM_IPU_TIMER7_CONTEXT_OFFSET 0x006c
235#define DRA7XX_PM_IPU_TIMER8_WKDEP_OFFSET 0x0070
236#define DRA7XX_RM_IPU_TIMER8_CONTEXT_OFFSET 0x0074
237#define DRA7XX_PM_IPU_I2C5_WKDEP_OFFSET 0x0078
238#define DRA7XX_RM_IPU_I2C5_CONTEXT_OFFSET 0x007c
239#define DRA7XX_PM_IPU_UART6_WKDEP_OFFSET 0x0080
240#define DRA7XX_RM_IPU_UART6_CONTEXT_OFFSET 0x0084
241
242/* PRM.COREAON_PRM register offsets */
243#define DRA7XX_PM_COREAON_SMARTREFLEX_MPU_WKDEP_OFFSET 0x0000
244#define DRA7XX_RM_COREAON_SMARTREFLEX_MPU_CONTEXT_OFFSET 0x0004
245#define DRA7XX_PM_COREAON_SMARTREFLEX_CORE_WKDEP_OFFSET 0x0010
246#define DRA7XX_RM_COREAON_SMARTREFLEX_CORE_CONTEXT_OFFSET 0x0014
247#define DRA7XX_PM_COREAON_SMARTREFLEX_GPU_WKDEP_OFFSET 0x0030
248#define DRA7XX_RM_COREAON_SMARTREFLEX_GPU_CONTEXT_OFFSET 0x0034
249#define DRA7XX_PM_COREAON_SMARTREFLEX_DSPEVE_WKDEP_OFFSET 0x0040
250#define DRA7XX_RM_COREAON_SMARTREFLEX_DSPEVE_CONTEXT_OFFSET 0x0044
251#define DRA7XX_PM_COREAON_SMARTREFLEX_IVAHD_WKDEP_OFFSET 0x0050
252#define DRA7XX_RM_COREAON_SMARTREFLEX_IVAHD_CONTEXT_OFFSET 0x0054
253#define DRA7XX_RM_COREAON_DUMMY_MODULE1_CONTEXT_OFFSET 0x0084
254#define DRA7XX_RM_COREAON_DUMMY_MODULE2_CONTEXT_OFFSET 0x0094
255#define DRA7XX_RM_COREAON_DUMMY_MODULE3_CONTEXT_OFFSET 0x00a4
256#define DRA7XX_RM_COREAON_DUMMY_MODULE4_CONTEXT_OFFSET 0x00b4
257
258/* PRM.CORE_PRM register offsets */
259#define DRA7XX_PM_CORE_PWRSTCTRL_OFFSET 0x0000
260#define DRA7XX_PM_CORE_PWRSTST_OFFSET 0x0004
261#define DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET 0x0024
262#define DRA7XX_RM_L3MAIN1_GPMC_CONTEXT_OFFSET 0x002c
263#define DRA7XX_RM_L3MAIN1_MMU_EDMA_CONTEXT_OFFSET 0x0034
264#define DRA7XX_PM_L3MAIN1_OCMC_RAM1_WKDEP_OFFSET 0x0050
265#define DRA7XX_RM_L3MAIN1_OCMC_RAM1_CONTEXT_OFFSET 0x0054
266#define DRA7XX_PM_L3MAIN1_OCMC_RAM2_WKDEP_OFFSET 0x0058
267#define DRA7XX_RM_L3MAIN1_OCMC_RAM2_CONTEXT_OFFSET 0x005c
268#define DRA7XX_PM_L3MAIN1_OCMC_RAM3_WKDEP_OFFSET 0x0060
269#define DRA7XX_RM_L3MAIN1_OCMC_RAM3_CONTEXT_OFFSET 0x0064
270#define DRA7XX_RM_L3MAIN1_OCMC_ROM_CONTEXT_OFFSET 0x006c
271#define DRA7XX_PM_L3MAIN1_TPCC_WKDEP_OFFSET 0x0070
272#define DRA7XX_RM_L3MAIN1_TPCC_CONTEXT_OFFSET 0x0074
273#define DRA7XX_PM_L3MAIN1_TPTC1_WKDEP_OFFSET 0x0078
274#define DRA7XX_RM_L3MAIN1_TPTC1_CONTEXT_OFFSET 0x007c
275#define DRA7XX_PM_L3MAIN1_TPTC2_WKDEP_OFFSET 0x0080
276#define DRA7XX_RM_L3MAIN1_TPTC2_CONTEXT_OFFSET 0x0084
277#define DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET 0x008c
278#define DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET 0x0094
279#define DRA7XX_RM_L3MAIN1_SPARE_CME_CONTEXT_OFFSET 0x009c
280#define DRA7XX_RM_L3MAIN1_SPARE_HDMI_CONTEXT_OFFSET 0x00a4
281#define DRA7XX_RM_L3MAIN1_SPARE_ICM_CONTEXT_OFFSET 0x00ac
282#define DRA7XX_RM_L3MAIN1_SPARE_IVA2_CONTEXT_OFFSET 0x00b4
283#define DRA7XX_RM_L3MAIN1_SPARE_SATA2_CONTEXT_OFFSET 0x00bc
284#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN4_CONTEXT_OFFSET 0x00c4
285#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN5_CONTEXT_OFFSET 0x00cc
286#define DRA7XX_RM_L3MAIN1_SPARE_UNKNOWN6_CONTEXT_OFFSET 0x00d4
287#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL1_CONTEXT_OFFSET 0x00dc
288#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL2_CONTEXT_OFFSET 0x00f4
289#define DRA7XX_RM_L3MAIN1_SPARE_VIDEOPLL3_CONTEXT_OFFSET 0x00fc
290#define DRA7XX_RM_IPU2_RSTCTRL_OFFSET 0x0210
291#define DRA7XX_RM_IPU2_RSTST_OFFSET 0x0214
292#define DRA7XX_RM_IPU2_IPU2_CONTEXT_OFFSET 0x0224
293#define DRA7XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET 0x0324
294#define DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET 0x0424
295#define DRA7XX_RM_EMIF_EMIF_OCP_FW_CONTEXT_OFFSET 0x042c
296#define DRA7XX_RM_EMIF_EMIF1_CONTEXT_OFFSET 0x0434
297#define DRA7XX_RM_EMIF_EMIF2_CONTEXT_OFFSET 0x043c
298#define DRA7XX_RM_EMIF_EMIF_DLL_CONTEXT_OFFSET 0x0444
299#define DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET 0x0524
300#define DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET 0x0624
301#define DRA7XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET 0x062c
302#define DRA7XX_RM_L4CFG_MAILBOX1_CONTEXT_OFFSET 0x0634
303#define DRA7XX_RM_L4CFG_SAR_ROM_CONTEXT_OFFSET 0x063c
304#define DRA7XX_RM_L4CFG_OCP2SCP2_CONTEXT_OFFSET 0x0644
305#define DRA7XX_RM_L4CFG_MAILBOX2_CONTEXT_OFFSET 0x064c
306#define DRA7XX_RM_L4CFG_MAILBOX3_CONTEXT_OFFSET 0x0654
307#define DRA7XX_RM_L4CFG_MAILBOX4_CONTEXT_OFFSET 0x065c
308#define DRA7XX_RM_L4CFG_MAILBOX5_CONTEXT_OFFSET 0x0664
309#define DRA7XX_RM_L4CFG_MAILBOX6_CONTEXT_OFFSET 0x066c
310#define DRA7XX_RM_L4CFG_MAILBOX7_CONTEXT_OFFSET 0x0674
311#define DRA7XX_RM_L4CFG_MAILBOX8_CONTEXT_OFFSET 0x067c
312#define DRA7XX_RM_L4CFG_MAILBOX9_CONTEXT_OFFSET 0x0684
313#define DRA7XX_RM_L4CFG_MAILBOX10_CONTEXT_OFFSET 0x068c
314#define DRA7XX_RM_L4CFG_MAILBOX11_CONTEXT_OFFSET 0x0694
315#define DRA7XX_RM_L4CFG_MAILBOX12_CONTEXT_OFFSET 0x069c
316#define DRA7XX_RM_L4CFG_MAILBOX13_CONTEXT_OFFSET 0x06a4
317#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_RTC_CONTEXT_OFFSET 0x06ac
318#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_SDRAM_CONTEXT_OFFSET 0x06b4
319#define DRA7XX_RM_L4CFG_SPARE_SMARTREFLEX_WKUP_CONTEXT_OFFSET 0x06bc
320#define DRA7XX_RM_L4CFG_IO_DELAY_BLOCK_CONTEXT_OFFSET 0x06c4
321#define DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET 0x0724
322#define DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET 0x072c
323#define DRA7XX_RM_L3INSTR_OCP_WP_NOC_CONTEXT_OFFSET 0x0744
324
325/* PRM.IVA_PRM register offsets */
326#define DRA7XX_PM_IVA_PWRSTCTRL_OFFSET 0x0000
327#define DRA7XX_PM_IVA_PWRSTST_OFFSET 0x0004
328#define DRA7XX_RM_IVA_RSTCTRL_OFFSET 0x0010
329#define DRA7XX_RM_IVA_RSTST_OFFSET 0x0014
330#define DRA7XX_RM_IVA_IVA_CONTEXT_OFFSET 0x0024
331#define DRA7XX_RM_IVA_SL2_CONTEXT_OFFSET 0x002c
332
333/* PRM.CAM_PRM register offsets */
334#define DRA7XX_PM_CAM_PWRSTCTRL_OFFSET 0x0000
335#define DRA7XX_PM_CAM_PWRSTST_OFFSET 0x0004
336#define DRA7XX_PM_CAM_VIP1_WKDEP_OFFSET 0x0020
337#define DRA7XX_RM_CAM_VIP1_CONTEXT_OFFSET 0x0024
338#define DRA7XX_PM_CAM_VIP2_WKDEP_OFFSET 0x0028
339#define DRA7XX_RM_CAM_VIP2_CONTEXT_OFFSET 0x002c
340#define DRA7XX_PM_CAM_VIP3_WKDEP_OFFSET 0x0030
341#define DRA7XX_RM_CAM_VIP3_CONTEXT_OFFSET 0x0034
342#define DRA7XX_RM_CAM_LVDSRX_CONTEXT_OFFSET 0x003c
343#define DRA7XX_RM_CAM_CSI1_CONTEXT_OFFSET 0x0044
344#define DRA7XX_RM_CAM_CSI2_CONTEXT_OFFSET 0x004c
345
346/* PRM.DSS_PRM register offsets */
347#define DRA7XX_PM_DSS_PWRSTCTRL_OFFSET 0x0000
348#define DRA7XX_PM_DSS_PWRSTST_OFFSET 0x0004
349#define DRA7XX_PM_DSS_DSS_WKDEP_OFFSET 0x0020
350#define DRA7XX_RM_DSS_DSS_CONTEXT_OFFSET 0x0024
351#define DRA7XX_PM_DSS_DSS2_WKDEP_OFFSET 0x0028
352#define DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET 0x0034
353#define DRA7XX_RM_DSS_SDVENC_CONTEXT_OFFSET 0x003c
354
355/* PRM.GPU_PRM register offsets */
356#define DRA7XX_PM_GPU_PWRSTCTRL_OFFSET 0x0000
357#define DRA7XX_PM_GPU_PWRSTST_OFFSET 0x0004
358#define DRA7XX_RM_GPU_GPU_CONTEXT_OFFSET 0x0024
359
360/* PRM.L3INIT_PRM register offsets */
361#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
362#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004
363#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
364#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
365#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
366#define DRA7XX_RM_L3INIT_MMC2_CONTEXT_OFFSET 0x0034
367#define DRA7XX_PM_L3INIT_USB_OTG_SS2_WKDEP_OFFSET 0x0040
368#define DRA7XX_RM_L3INIT_USB_OTG_SS2_CONTEXT_OFFSET 0x0044
369#define DRA7XX_PM_L3INIT_USB_OTG_SS3_WKDEP_OFFSET 0x0048
370#define DRA7XX_RM_L3INIT_USB_OTG_SS3_CONTEXT_OFFSET 0x004c
371#define DRA7XX_PM_L3INIT_USB_OTG_SS4_WKDEP_OFFSET 0x0050
372#define DRA7XX_RM_L3INIT_USB_OTG_SS4_CONTEXT_OFFSET 0x0054
373#define DRA7XX_RM_L3INIT_MLB_SS_CONTEXT_OFFSET 0x005c
374#define DRA7XX_RM_L3INIT_IEEE1500_2_OCP_CONTEXT_OFFSET 0x007c
375#define DRA7XX_PM_L3INIT_SATA_WKDEP_OFFSET 0x0088
376#define DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET 0x008c
377#define DRA7XX_RM_GMAC_GMAC_CONTEXT_OFFSET 0x00d4
378#define DRA7XX_RM_L3INIT_OCP2SCP1_CONTEXT_OFFSET 0x00e4
379#define DRA7XX_RM_L3INIT_OCP2SCP3_CONTEXT_OFFSET 0x00ec
380#define DRA7XX_PM_L3INIT_USB_OTG_SS1_WKDEP_OFFSET 0x00f0
381#define DRA7XX_RM_L3INIT_USB_OTG_SS1_CONTEXT_OFFSET 0x00f4
382
383/* PRM.L4PER_PRM register offsets */
384#define DRA7XX_PM_L4PER_PWRSTCTRL_OFFSET 0x0000
385#define DRA7XX_PM_L4PER_PWRSTST_OFFSET 0x0004
386#define DRA7XX_RM_L4PER2_L4PER2_CONTEXT_OFFSET 0x000c
387#define DRA7XX_RM_L4PER3_L4PER3_CONTEXT_OFFSET 0x0014
388#define DRA7XX_RM_L4PER2_PRUSS1_CONTEXT_OFFSET 0x001c
389#define DRA7XX_RM_L4PER2_PRUSS2_CONTEXT_OFFSET 0x0024
390#define DRA7XX_PM_L4PER_TIMER10_WKDEP_OFFSET 0x0028
391#define DRA7XX_RM_L4PER_TIMER10_CONTEXT_OFFSET 0x002c
392#define DRA7XX_PM_L4PER_TIMER11_WKDEP_OFFSET 0x0030
393#define DRA7XX_RM_L4PER_TIMER11_CONTEXT_OFFSET 0x0034
394#define DRA7XX_PM_L4PER_TIMER2_WKDEP_OFFSET 0x0038
395#define DRA7XX_RM_L4PER_TIMER2_CONTEXT_OFFSET 0x003c
396#define DRA7XX_PM_L4PER_TIMER3_WKDEP_OFFSET 0x0040
397#define DRA7XX_RM_L4PER_TIMER3_CONTEXT_OFFSET 0x0044
398#define DRA7XX_PM_L4PER_TIMER4_WKDEP_OFFSET 0x0048
399#define DRA7XX_RM_L4PER_TIMER4_CONTEXT_OFFSET 0x004c
400#define DRA7XX_PM_L4PER_TIMER9_WKDEP_OFFSET 0x0050
401#define DRA7XX_RM_L4PER_TIMER9_CONTEXT_OFFSET 0x0054
402#define DRA7XX_RM_L4PER_ELM_CONTEXT_OFFSET 0x005c
403#define DRA7XX_PM_L4PER_GPIO2_WKDEP_OFFSET 0x0060
404#define DRA7XX_RM_L4PER_GPIO2_CONTEXT_OFFSET 0x0064
405#define DRA7XX_PM_L4PER_GPIO3_WKDEP_OFFSET 0x0068
406#define DRA7XX_RM_L4PER_GPIO3_CONTEXT_OFFSET 0x006c
407#define DRA7XX_PM_L4PER_GPIO4_WKDEP_OFFSET 0x0070
408#define DRA7XX_RM_L4PER_GPIO4_CONTEXT_OFFSET 0x0074
409#define DRA7XX_PM_L4PER_GPIO5_WKDEP_OFFSET 0x0078
410#define DRA7XX_RM_L4PER_GPIO5_CONTEXT_OFFSET 0x007c
411#define DRA7XX_PM_L4PER_GPIO6_WKDEP_OFFSET 0x0080
412#define DRA7XX_RM_L4PER_GPIO6_CONTEXT_OFFSET 0x0084
413#define DRA7XX_RM_L4PER_HDQ1W_CONTEXT_OFFSET 0x008c
414#define DRA7XX_RM_L4PER2_PWMSS2_CONTEXT_OFFSET 0x0094
415#define DRA7XX_RM_L4PER2_PWMSS3_CONTEXT_OFFSET 0x009c
416#define DRA7XX_PM_L4PER_I2C1_WKDEP_OFFSET 0x00a0
417#define DRA7XX_RM_L4PER_I2C1_CONTEXT_OFFSET 0x00a4
418#define DRA7XX_PM_L4PER_I2C2_WKDEP_OFFSET 0x00a8
419#define DRA7XX_RM_L4PER_I2C2_CONTEXT_OFFSET 0x00ac
420#define DRA7XX_PM_L4PER_I2C3_WKDEP_OFFSET 0x00b0
421#define DRA7XX_RM_L4PER_I2C3_CONTEXT_OFFSET 0x00b4
422#define DRA7XX_PM_L4PER_I2C4_WKDEP_OFFSET 0x00b8
423#define DRA7XX_RM_L4PER_I2C4_CONTEXT_OFFSET 0x00bc
424#define DRA7XX_RM_L4PER_L4PER1_CONTEXT_OFFSET 0x00c0
425#define DRA7XX_RM_L4PER2_PWMSS1_CONTEXT_OFFSET 0x00c4
426#define DRA7XX_PM_L4PER_TIMER13_WKDEP_OFFSET 0x00c8
427#define DRA7XX_RM_L4PER3_TIMER13_CONTEXT_OFFSET 0x00cc
428#define DRA7XX_PM_L4PER_TIMER14_WKDEP_OFFSET 0x00d0
429#define DRA7XX_RM_L4PER3_TIMER14_CONTEXT_OFFSET 0x00d4
430#define DRA7XX_PM_L4PER_TIMER15_WKDEP_OFFSET 0x00d8
431#define DRA7XX_RM_L4PER3_TIMER15_CONTEXT_OFFSET 0x00dc
432#define DRA7XX_PM_L4PER_MCSPI1_WKDEP_OFFSET 0x00f0
433#define DRA7XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET 0x00f4
434#define DRA7XX_PM_L4PER_MCSPI2_WKDEP_OFFSET 0x00f8
435#define DRA7XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET 0x00fc
436#define DRA7XX_PM_L4PER_MCSPI3_WKDEP_OFFSET 0x0100
437#define DRA7XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET 0x0104
438#define DRA7XX_PM_L4PER_MCSPI4_WKDEP_OFFSET 0x0108
439#define DRA7XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET 0x010c
440#define DRA7XX_PM_L4PER_GPIO7_WKDEP_OFFSET 0x0110
441#define DRA7XX_RM_L4PER_GPIO7_CONTEXT_OFFSET 0x0114
442#define DRA7XX_PM_L4PER_GPIO8_WKDEP_OFFSET 0x0118
443#define DRA7XX_RM_L4PER_GPIO8_CONTEXT_OFFSET 0x011c
444#define DRA7XX_PM_L4PER_MMC3_WKDEP_OFFSET 0x0120
445#define DRA7XX_RM_L4PER_MMC3_CONTEXT_OFFSET 0x0124
446#define DRA7XX_PM_L4PER_MMC4_WKDEP_OFFSET 0x0128
447#define DRA7XX_RM_L4PER_MMC4_CONTEXT_OFFSET 0x012c
448#define DRA7XX_PM_L4PER_TIMER16_WKDEP_OFFSET 0x0130
449#define DRA7XX_RM_L4PER3_TIMER16_CONTEXT_OFFSET 0x0134
450#define DRA7XX_PM_L4PER2_QSPI_WKDEP_OFFSET 0x0138
451#define DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET 0x013c
452#define DRA7XX_PM_L4PER_UART1_WKDEP_OFFSET 0x0140
453#define DRA7XX_RM_L4PER_UART1_CONTEXT_OFFSET 0x0144
454#define DRA7XX_PM_L4PER_UART2_WKDEP_OFFSET 0x0148
455#define DRA7XX_RM_L4PER_UART2_CONTEXT_OFFSET 0x014c
456#define DRA7XX_PM_L4PER_UART3_WKDEP_OFFSET 0x0150
457#define DRA7XX_RM_L4PER_UART3_CONTEXT_OFFSET 0x0154
458#define DRA7XX_PM_L4PER_UART4_WKDEP_OFFSET 0x0158
459#define DRA7XX_RM_L4PER_UART4_CONTEXT_OFFSET 0x015c
460#define DRA7XX_PM_L4PER2_MCASP2_WKDEP_OFFSET 0x0160
461#define DRA7XX_RM_L4PER2_MCASP2_CONTEXT_OFFSET 0x0164
462#define DRA7XX_PM_L4PER2_MCASP3_WKDEP_OFFSET 0x0168
463#define DRA7XX_RM_L4PER2_MCASP3_CONTEXT_OFFSET 0x016c
464#define DRA7XX_PM_L4PER_UART5_WKDEP_OFFSET 0x0170
465#define DRA7XX_RM_L4PER_UART5_CONTEXT_OFFSET 0x0174
466#define DRA7XX_PM_L4PER2_MCASP5_WKDEP_OFFSET 0x0178
467#define DRA7XX_RM_L4PER2_MCASP5_CONTEXT_OFFSET 0x017c
468#define DRA7XX_PM_L4PER2_MCASP6_WKDEP_OFFSET 0x0180
469#define DRA7XX_RM_L4PER2_MCASP6_CONTEXT_OFFSET 0x0184
470#define DRA7XX_PM_L4PER2_MCASP7_WKDEP_OFFSET 0x0188
471#define DRA7XX_RM_L4PER2_MCASP7_CONTEXT_OFFSET 0x018c
472#define DRA7XX_PM_L4PER2_MCASP8_WKDEP_OFFSET 0x0190
473#define DRA7XX_RM_L4PER2_MCASP8_CONTEXT_OFFSET 0x0194
474#define DRA7XX_PM_L4PER2_MCASP4_WKDEP_OFFSET 0x0198
475#define DRA7XX_RM_L4PER2_MCASP4_CONTEXT_OFFSET 0x019c
476#define DRA7XX_RM_L4SEC_AES1_CONTEXT_OFFSET 0x01a4
477#define DRA7XX_RM_L4SEC_AES2_CONTEXT_OFFSET 0x01ac
478#define DRA7XX_RM_L4SEC_DES3DES_CONTEXT_OFFSET 0x01b4
479#define DRA7XX_RM_L4SEC_FPKA_CONTEXT_OFFSET 0x01bc
480#define DRA7XX_RM_L4SEC_RNG_CONTEXT_OFFSET 0x01c4
481#define DRA7XX_RM_L4SEC_SHA2MD51_CONTEXT_OFFSET 0x01cc
482#define DRA7XX_PM_L4PER2_UART7_WKDEP_OFFSET 0x01d0
483#define DRA7XX_RM_L4PER2_UART7_CONTEXT_OFFSET 0x01d4
484#define DRA7XX_RM_L4SEC_DMA_CRYPTO_CONTEXT_OFFSET 0x01dc
485#define DRA7XX_PM_L4PER2_UART8_WKDEP_OFFSET 0x01e0
486#define DRA7XX_RM_L4PER2_UART8_CONTEXT_OFFSET 0x01e4
487#define DRA7XX_PM_L4PER2_UART9_WKDEP_OFFSET 0x01e8
488#define DRA7XX_RM_L4PER2_UART9_CONTEXT_OFFSET 0x01ec
489#define DRA7XX_PM_L4PER2_DCAN2_WKDEP_OFFSET 0x01f0
490#define DRA7XX_RM_L4PER2_DCAN2_CONTEXT_OFFSET 0x01f4
491#define DRA7XX_RM_L4SEC_SHA2MD52_CONTEXT_OFFSET 0x01fc
492
493/* PRM.CUSTEFUSE_PRM register offsets */
494#define DRA7XX_PM_CUSTEFUSE_PWRSTCTRL_OFFSET 0x0000
495#define DRA7XX_PM_CUSTEFUSE_PWRSTST_OFFSET 0x0004
496#define DRA7XX_RM_CUSTEFUSE_EFUSE_CTRL_CUST_CONTEXT_OFFSET 0x0024
497
498/* PRM.WKUPAON_PRM register offsets */
499#define DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET 0x0000
500#define DRA7XX_PM_WKUPAON_WD_TIMER1_WKDEP_OFFSET 0x0004
501#define DRA7XX_RM_WKUPAON_WD_TIMER1_CONTEXT_OFFSET 0x0008
502#define DRA7XX_PM_WKUPAON_WD_TIMER2_WKDEP_OFFSET 0x000c
503#define DRA7XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET 0x0010
504#define DRA7XX_PM_WKUPAON_GPIO1_WKDEP_OFFSET 0x0014
505#define DRA7XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET 0x0018
506#define DRA7XX_PM_WKUPAON_TIMER1_WKDEP_OFFSET 0x001c
507#define DRA7XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET 0x0020
508#define DRA7XX_PM_WKUPAON_TIMER12_WKDEP_OFFSET 0x0024
509#define DRA7XX_RM_WKUPAON_TIMER12_CONTEXT_OFFSET 0x0028
510#define DRA7XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET 0x0030
511#define DRA7XX_RM_WKUPAON_SAR_RAM_CONTEXT_OFFSET 0x0040
512#define DRA7XX_PM_WKUPAON_KBD_WKDEP_OFFSET 0x0054
513#define DRA7XX_RM_WKUPAON_KBD_CONTEXT_OFFSET 0x0058
514#define DRA7XX_PM_WKUPAON_UART10_WKDEP_OFFSET 0x005c
515#define DRA7XX_RM_WKUPAON_UART10_CONTEXT_OFFSET 0x0060
516#define DRA7XX_PM_WKUPAON_DCAN1_WKDEP_OFFSET 0x0064
517#define DRA7XX_RM_WKUPAON_DCAN1_CONTEXT_OFFSET 0x0068
518#define DRA7XX_PM_WKUPAON_ADC_WKDEP_OFFSET 0x007c
519#define DRA7XX_RM_WKUPAON_ADC_CONTEXT_OFFSET 0x0080
520#define DRA7XX_RM_WKUPAON_SPARE_SAFETY1_CONTEXT_OFFSET 0x0090
521#define DRA7XX_RM_WKUPAON_SPARE_SAFETY2_CONTEXT_OFFSET 0x0098
522#define DRA7XX_RM_WKUPAON_SPARE_SAFETY3_CONTEXT_OFFSET 0x00a0
523#define DRA7XX_RM_WKUPAON_SPARE_SAFETY4_CONTEXT_OFFSET 0x00a8
524#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN2_CONTEXT_OFFSET 0x00b0
525#define DRA7XX_RM_WKUPAON_SPARE_UNKNOWN3_CONTEXT_OFFSET 0x00b8
526
527/* PRM.WKUPAON_CM register offsets */
528#define DRA7XX_CM_WKUPAON_CLKSTCTRL_OFFSET 0x0000
529#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET 0x0020
530#define DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0020)
531#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL_OFFSET 0x0028
532#define DRA7XX_CM_WKUPAON_WD_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0028)
533#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET 0x0030
534#define DRA7XX_CM_WKUPAON_WD_TIMER2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0030)
535#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET 0x0038
536#define DRA7XX_CM_WKUPAON_GPIO1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0038)
537#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET 0x0040
538#define DRA7XX_CM_WKUPAON_TIMER1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0040)
539#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL_OFFSET 0x0048
540#define DRA7XX_CM_WKUPAON_TIMER12_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0048)
541#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET 0x0050
542#define DRA7XX_CM_WKUPAON_COUNTER_32K_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0050)
543#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL_OFFSET 0x0060
544#define DRA7XX_CM_WKUPAON_SAR_RAM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0060)
545#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET 0x0078
546#define DRA7XX_CM_WKUPAON_KBD_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0078)
547#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL_OFFSET 0x0080
548#define DRA7XX_CM_WKUPAON_UART10_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0080)
549#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL_OFFSET 0x0088
550#define DRA7XX_CM_WKUPAON_DCAN1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0088)
551#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL_OFFSET 0x0090
552#define DRA7XX_CM_WKUPAON_SCRM_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0090)
553#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL_OFFSET 0x0098
554#define DRA7XX_CM_WKUPAON_IO_SRCOMP_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x0098)
555#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL_OFFSET 0x00a0
556#define DRA7XX_CM_WKUPAON_ADC_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00a0)
557#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL_OFFSET 0x00b0
558#define DRA7XX_CM_WKUPAON_SPARE_SAFETY1_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b0)
559#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL_OFFSET 0x00b8
560#define DRA7XX_CM_WKUPAON_SPARE_SAFETY2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00b8)
561#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL_OFFSET 0x00c0
562#define DRA7XX_CM_WKUPAON_SPARE_SAFETY3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c0)
563#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL_OFFSET 0x00c8
564#define DRA7XX_CM_WKUPAON_SPARE_SAFETY4_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00c8)
565#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL_OFFSET 0x00d0
566#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN2_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d0)
567#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL_OFFSET 0x00d8
568#define DRA7XX_CM_WKUPAON_SPARE_UNKNOWN3_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_WKUPAON_CM_INST, 0x00d8)
569
570/* PRM.EMU_PRM register offsets */
571#define DRA7XX_PM_EMU_PWRSTCTRL_OFFSET 0x0000
572#define DRA7XX_PM_EMU_PWRSTST_OFFSET 0x0004
573#define DRA7XX_RM_EMU_DEBUGSS_CONTEXT_OFFSET 0x0024
574
575/* PRM.EMU_CM register offsets */
576#define DRA7XX_CM_EMU_CLKSTCTRL_OFFSET 0x0000
577#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL_OFFSET 0x0004
578#define DRA7XX_CM_EMU_DEBUGSS_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x0004)
579#define DRA7XX_CM_EMU_DYNAMICDEP_OFFSET 0x0008
580#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL_OFFSET 0x000c
581#define DRA7XX_CM_EMU_MPU_EMU_DBG_CLKCTRL DRA7XX_PRM_REGADDR(DRA7XX_PRM_EMU_CM_INST, 0x000c)
582
583/* PRM.DSP2_PRM register offsets */
584#define DRA7XX_PM_DSP2_PWRSTCTRL_OFFSET 0x0000
585#define DRA7XX_PM_DSP2_PWRSTST_OFFSET 0x0004
586#define DRA7XX_RM_DSP2_RSTCTRL_OFFSET 0x0010
587#define DRA7XX_RM_DSP2_RSTST_OFFSET 0x0014
588#define DRA7XX_RM_DSP2_DSP2_CONTEXT_OFFSET 0x0024
589
590/* PRM.EVE1_PRM register offsets */
591#define DRA7XX_PM_EVE1_PWRSTCTRL_OFFSET 0x0000
592#define DRA7XX_PM_EVE1_PWRSTST_OFFSET 0x0004
593#define DRA7XX_RM_EVE1_RSTCTRL_OFFSET 0x0010
594#define DRA7XX_RM_EVE1_RSTST_OFFSET 0x0014
595#define DRA7XX_PM_EVE1_EVE1_WKDEP_OFFSET 0x0020
596#define DRA7XX_RM_EVE1_EVE1_CONTEXT_OFFSET 0x0024
597
598/* PRM.EVE2_PRM register offsets */
599#define DRA7XX_PM_EVE2_PWRSTCTRL_OFFSET 0x0000
600#define DRA7XX_PM_EVE2_PWRSTST_OFFSET 0x0004
601#define DRA7XX_RM_EVE2_RSTCTRL_OFFSET 0x0010
602#define DRA7XX_RM_EVE2_RSTST_OFFSET 0x0014
603#define DRA7XX_PM_EVE2_EVE2_WKDEP_OFFSET 0x0020
604#define DRA7XX_RM_EVE2_EVE2_CONTEXT_OFFSET 0x0024
605
606/* PRM.EVE3_PRM register offsets */
607#define DRA7XX_PM_EVE3_PWRSTCTRL_OFFSET 0x0000
608#define DRA7XX_PM_EVE3_PWRSTST_OFFSET 0x0004
609#define DRA7XX_RM_EVE3_RSTCTRL_OFFSET 0x0010
610#define DRA7XX_RM_EVE3_RSTST_OFFSET 0x0014
611#define DRA7XX_PM_EVE3_EVE3_WKDEP_OFFSET 0x0020
612#define DRA7XX_RM_EVE3_EVE3_CONTEXT_OFFSET 0x0024
613
614/* PRM.EVE4_PRM register offsets */
615#define DRA7XX_PM_EVE4_PWRSTCTRL_OFFSET 0x0000
616#define DRA7XX_PM_EVE4_PWRSTST_OFFSET 0x0004
617#define DRA7XX_RM_EVE4_RSTCTRL_OFFSET 0x0010
618#define DRA7XX_RM_EVE4_RSTST_OFFSET 0x0014
619#define DRA7XX_PM_EVE4_EVE4_WKDEP_OFFSET 0x0020
620#define DRA7XX_RM_EVE4_EVE4_CONTEXT_OFFSET 0x0024
621
622/* PRM.RTC_PRM register offsets */
623#define DRA7XX_PM_RTC_RTCSS_WKDEP_OFFSET 0x0000
624#define DRA7XX_RM_RTC_RTCSS_CONTEXT_OFFSET 0x0004
625
626/* PRM.VPE_PRM register offsets */
627#define DRA7XX_PM_VPE_PWRSTCTRL_OFFSET 0x0000
628#define DRA7XX_PM_VPE_PWRSTST_OFFSET 0x0004
629#define DRA7XX_PM_VPE_VPE_WKDEP_OFFSET 0x0020
630#define DRA7XX_RM_VPE_VPE_CONTEXT_OFFSET 0x0024
631
632/* PRM.DEVICE_PRM register offsets */
633#define DRA7XX_PRM_RSTCTRL_OFFSET 0x0000
634#define DRA7XX_PRM_RSTST_OFFSET 0x0004
635#define DRA7XX_PRM_RSTTIME_OFFSET 0x0008
636#define DRA7XX_PRM_CLKREQCTRL_OFFSET 0x000c
637#define DRA7XX_PRM_VOLTCTRL_OFFSET 0x0010
638#define DRA7XX_PRM_PWRREQCTRL_OFFSET 0x0014
639#define DRA7XX_PRM_PSCON_COUNT_OFFSET 0x0018
640#define DRA7XX_PRM_IO_COUNT_OFFSET 0x001c
641#define DRA7XX_PRM_IO_PMCTRL_OFFSET 0x0020
642#define DRA7XX_PRM_VOLTSETUP_WARMRESET_OFFSET 0x0024
643#define DRA7XX_PRM_VOLTSETUP_CORE_OFF_OFFSET 0x0028
644#define DRA7XX_PRM_VOLTSETUP_MPU_OFF_OFFSET 0x002c
645#define DRA7XX_PRM_VOLTSETUP_MM_OFF_OFFSET 0x0030
646#define DRA7XX_PRM_VOLTSETUP_CORE_RET_SLEEP_OFFSET 0x0034
647#define DRA7XX_PRM_VOLTSETUP_MPU_RET_SLEEP_OFFSET 0x0038
648#define DRA7XX_PRM_VOLTSETUP_MM_RET_SLEEP_OFFSET 0x003c
649#define DRA7XX_PRM_SRAM_COUNT_OFFSET 0x00bc
650#define DRA7XX_PRM_SRAM_WKUP_SETUP_OFFSET 0x00c0
651#define DRA7XX_PRM_SLDO_CORE_SETUP_OFFSET 0x00c4
652#define DRA7XX_PRM_SLDO_CORE_CTRL_OFFSET 0x00c8
653#define DRA7XX_PRM_SLDO_MPU_SETUP_OFFSET 0x00cc
654#define DRA7XX_PRM_SLDO_MPU_CTRL_OFFSET 0x00d0
655#define DRA7XX_PRM_SLDO_GPU_SETUP_OFFSET 0x00d4
656#define DRA7XX_PRM_SLDO_GPU_CTRL_OFFSET 0x00d8
657#define DRA7XX_PRM_ABBLDO_MPU_SETUP_OFFSET 0x00dc
658#define DRA7XX_PRM_ABBLDO_MPU_CTRL_OFFSET 0x00e0
659#define DRA7XX_PRM_ABBLDO_GPU_SETUP_OFFSET 0x00e4
660#define DRA7XX_PRM_ABBLDO_GPU_CTRL_OFFSET 0x00e8
661#define DRA7XX_PRM_BANDGAP_SETUP_OFFSET 0x00ec
662#define DRA7XX_PRM_DEVICE_OFF_CTRL_OFFSET 0x00f0
663#define DRA7XX_PRM_PHASE1_CNDP_OFFSET 0x00f4
664#define DRA7XX_PRM_PHASE2A_CNDP_OFFSET 0x00f8
665#define DRA7XX_PRM_PHASE2B_CNDP_OFFSET 0x00fc
666#define DRA7XX_PRM_MODEM_IF_CTRL_OFFSET 0x0100
667#define DRA7XX_PRM_VOLTST_MPU_OFFSET 0x0110
668#define DRA7XX_PRM_VOLTST_MM_OFFSET 0x0114
669#define DRA7XX_PRM_SLDO_DSPEVE_SETUP_OFFSET 0x0118
670#define DRA7XX_PRM_SLDO_IVA_SETUP_OFFSET 0x011c
671#define DRA7XX_PRM_ABBLDO_DSPEVE_CTRL_OFFSET 0x0120
672#define DRA7XX_PRM_ABBLDO_IVA_CTRL_OFFSET 0x0124
673#define DRA7XX_PRM_SLDO_DSPEVE_CTRL_OFFSET 0x0128
674#define DRA7XX_PRM_SLDO_IVA_CTRL_OFFSET 0x012c
675#define DRA7XX_PRM_ABBLDO_DSPEVE_SETUP_OFFSET 0x0130
676#define DRA7XX_PRM_ABBLDO_IVA_SETUP_OFFSET 0x0134
677
678#endif
diff --git a/arch/arm/mach-omap2/prminst44xx.c b/arch/arm/mach-omap2/prminst44xx.c
index c12320c0ae95..6334b96b4097 100644
--- a/arch/arm/mach-omap2/prminst44xx.c
+++ b/arch/arm/mach-omap2/prminst44xx.c
@@ -20,10 +20,13 @@
20#include "common.h" 20#include "common.h"
21#include "prcm-common.h" 21#include "prcm-common.h"
22#include "prm44xx.h" 22#include "prm44xx.h"
23#include "prm54xx.h"
24#include "prm7xx.h"
23#include "prminst44xx.h" 25#include "prminst44xx.h"
24#include "prm-regbits-44xx.h" 26#include "prm-regbits-44xx.h"
25#include "prcm44xx.h" 27#include "prcm44xx.h"
26#include "prcm_mpu44xx.h" 28#include "prcm_mpu44xx.h"
29#include "soc.h"
27 30
28static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS]; 31static void __iomem *_prm_bases[OMAP4_MAX_PRCM_PARTITIONS];
29 32
@@ -165,10 +168,19 @@ int omap4_prminst_deassert_hardreset(u8 shift, u8 part, s16 inst,
165void omap4_prminst_global_warm_sw_reset(void) 168void omap4_prminst_global_warm_sw_reset(void)
166{ 169{
167 u32 v; 170 u32 v;
168 171 s16 dev_inst;
169 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, 172
170 OMAP4430_PRM_DEVICE_INST, 173 if (cpu_is_omap44xx())
171 OMAP4_PRM_RSTCTRL_OFFSET); 174 dev_inst = OMAP4430_PRM_DEVICE_INST;
175 else if (soc_is_omap54xx())
176 dev_inst = OMAP54XX_PRM_DEVICE_INST;
177 else if (soc_is_dra7xx())
178 dev_inst = DRA7XX_PRM_DEVICE_INST;
179 else
180 return;
181
182 v = omap4_prminst_read_inst_reg(OMAP4430_PRM_PARTITION, dev_inst,
183 OMAP4_PRM_RSTCTRL_OFFSET);
172 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK; 184 v |= OMAP4430_RST_GLOBAL_WARM_SW_MASK;
173 omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION, 185 omap4_prminst_write_inst_reg(v, OMAP4430_PRM_PARTITION,
174 OMAP4430_PRM_DEVICE_INST, 186 OMAP4430_PRM_DEVICE_INST,
diff --git a/arch/arm/mach-ux500/board-mop500-audio.c b/arch/arm/mach-ux500/board-mop500-audio.c
index bfe443daf4b0..ec0807247e60 100644
--- a/arch/arm/mach-ux500/board-mop500-audio.c
+++ b/arch/arm/mach-ux500/board-mop500-audio.c
@@ -17,7 +17,6 @@
17#include "ste-dma40-db8500.h" 17#include "ste-dma40-db8500.h"
18#include "board-mop500.h" 18#include "board-mop500.h"
19#include "devices-db8500.h" 19#include "devices-db8500.h"
20#include "pins-db8500.h"
21 20
22static struct stedma40_chan_cfg msp0_dma_rx = { 21static struct stedma40_chan_cfg msp0_dma_rx = {
23 .high_priority = true, 22 .high_priority = true,
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 7936d40a5c37..0efb1560fc35 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -14,7 +14,6 @@
14 14
15#include <asm/mach-types.h> 15#include <asm/mach-types.h>
16 16
17#include "pins-db8500.h"
18#include "board-mop500.h" 17#include "board-mop500.h"
19 18
20enum custom_pin_cfg_t { 19enum custom_pin_cfg_t {
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 4e7ab3a0dd60..ad0806eff762 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -324,21 +324,19 @@ static struct lp55xx_platform_data __initdata lp5521_sec_data = {
324 .clock_mode = LP55XX_CLOCK_EXT, 324 .clock_mode = LP55XX_CLOCK_EXT,
325}; 325};
326 326
327/* I2C0 devices only available on the first HREF/MOP500 */
327static struct i2c_board_info __initdata mop500_i2c0_devices[] = { 328static struct i2c_board_info __initdata mop500_i2c0_devices[] = {
328 { 329 {
329 I2C_BOARD_INFO("tc3589x", 0x42), 330 I2C_BOARD_INFO("tc3589x", 0x42),
330 .irq = NOMADIK_GPIO_TO_IRQ(217), 331 .irq = NOMADIK_GPIO_TO_IRQ(217),
331 .platform_data = &mop500_tc35892_data, 332 .platform_data = &mop500_tc35892_data,
332 }, 333 },
333 /* I2C0 devices only available prior to HREFv60 */
334 { 334 {
335 I2C_BOARD_INFO("tps61052", 0x33), 335 I2C_BOARD_INFO("tps61052", 0x33),
336 .platform_data = &mop500_tps61052_data, 336 .platform_data = &mop500_tps61052_data,
337 }, 337 },
338}; 338};
339 339
340#define NUM_PRE_V60_I2C0_DEVICES 1
341
342static struct i2c_board_info __initdata mop500_i2c2_devices[] = { 340static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
343 { 341 {
344 /* lp5521 LED driver, 1st device */ 342 /* lp5521 LED driver, 1st device */
@@ -356,6 +354,17 @@ static struct i2c_board_info __initdata mop500_i2c2_devices[] = {
356 }, 354 },
357}; 355};
358 356
357static int __init mop500_i2c_board_init(void)
358{
359 if (machine_is_u8500())
360 mop500_uib_i2c_add(0, mop500_i2c0_devices,
361 ARRAY_SIZE(mop500_i2c0_devices));
362 mop500_uib_i2c_add(2, mop500_i2c2_devices,
363 ARRAY_SIZE(mop500_i2c2_devices));
364 return 0;
365}
366device_initcall(mop500_i2c_board_init);
367
359static void __init mop500_i2c_init(struct device *parent) 368static void __init mop500_i2c_init(struct device *parent)
360{ 369{
361 db8500_add_i2c0(parent, NULL); 370 db8500_add_i2c0(parent, NULL);
@@ -564,7 +573,6 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
564static void __init mop500_init_machine(void) 573static void __init mop500_init_machine(void)
565{ 574{
566 struct device *parent = NULL; 575 struct device *parent = NULL;
567 int i2c0_devs;
568 int i; 576 int i;
569 577
570 platform_device_register(&db8500_prcmu_device); 578 platform_device_register(&db8500_prcmu_device);
@@ -587,19 +595,13 @@ static void __init mop500_init_machine(void)
587 mop500_spi_init(parent); 595 mop500_spi_init(parent);
588 mop500_audio_init(parent); 596 mop500_audio_init(parent);
589 mop500_uart_init(parent); 597 mop500_uart_init(parent);
590
591 u8500_cryp1_hash1_init(parent); 598 u8500_cryp1_hash1_init(parent);
592 599
593 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
594
595 i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
596 i2c_register_board_info(2, mop500_i2c2_devices,
597 ARRAY_SIZE(mop500_i2c2_devices));
598
599 /* This board has full regulator constraints */ 600 /* This board has full regulator constraints */
600 regulator_has_full_constraints(); 601 regulator_has_full_constraints();
601} 602}
602 603
604
603static void __init snowball_init_machine(void) 605static void __init snowball_init_machine(void)
604{ 606{
605 struct device *parent = NULL; 607 struct device *parent = NULL;
@@ -634,7 +636,6 @@ static void __init snowball_init_machine(void)
634static void __init hrefv60_init_machine(void) 636static void __init hrefv60_init_machine(void)
635{ 637{
636 struct device *parent = NULL; 638 struct device *parent = NULL;
637 int i2c0_devs;
638 int i; 639 int i;
639 640
640 platform_device_register(&db8500_prcmu_device); 641 platform_device_register(&db8500_prcmu_device);
@@ -663,14 +664,6 @@ static void __init hrefv60_init_machine(void)
663 mop500_audio_init(parent); 664 mop500_audio_init(parent);
664 mop500_uart_init(parent); 665 mop500_uart_init(parent);
665 666
666 i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
667
668 i2c0_devs -= NUM_PRE_V60_I2C0_DEVICES;
669
670 i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
671 i2c_register_board_info(2, mop500_i2c2_devices,
672 ARRAY_SIZE(mop500_i2c2_devices));
673
674 /* This board has full regulator constraints */ 667 /* This board has full regulator constraints */
675 regulator_has_full_constraints(); 668 regulator_has_full_constraints();
676} 669}
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index bfaf95d22cbb..301c3460d96a 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -156,7 +156,8 @@ static void __init db8500_add_gpios(struct device *parent)
156 .supports_sleepmode = true, 156 .supports_sleepmode = true,
157 }; 157 };
158 158
159 dbx500_add_gpios(parent, ARRAY_AND_SIZE(db8500_gpio_base), 159 dbx500_add_gpios(parent, db8500_gpio_base,
160 ARRAY_SIZE(db8500_gpio_base),
160 IRQ_DB8500_GPIO0, &pdata); 161 IRQ_DB8500_GPIO0, &pdata);
161 dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE); 162 dbx500_add_pinctrl(parent, "pinctrl-db8500", U8500_PRCMU_BASE);
162} 163}
diff --git a/arch/arm/mach-ux500/pins-db8500.h b/arch/arm/mach-ux500/pins-db8500.h
deleted file mode 100644
index 062c7acf4576..000000000000
--- a/arch/arm/mach-ux500/pins-db8500.h
+++ /dev/null
@@ -1,746 +0,0 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License terms: GNU General Public License, version 2
5 * Author: Rabin Vincent <rabin.vincent@stericsson.com>
6 */
7
8#ifndef __MACH_PINS_DB8500_H
9#define __MACH_PINS_DB8500_H
10
11/*
12 * TODO: Eventually encode all non-board specific pull up/down configuration
13 * here.
14 */
15
16#define GPIO0_GPIO PIN_CFG(0, GPIO)
17#define GPIO0_U0_CTSn PIN_CFG(0, ALT_A)
18#define GPIO0_TRIG_OUT PIN_CFG(0, ALT_B)
19#define GPIO0_IP_TDO PIN_CFG(0, ALT_C)
20
21#define GPIO1_GPIO PIN_CFG(1, GPIO)
22#define GPIO1_U0_RTSn PIN_CFG(1, ALT_A)
23#define GPIO1_TRIG_IN PIN_CFG(1, ALT_B)
24#define GPIO1_IP_TDI PIN_CFG(1, ALT_C)
25
26#define GPIO2_GPIO PIN_CFG(2, GPIO)
27#define GPIO2_U0_RXD PIN_CFG(2, ALT_A)
28#define GPIO2_NONE PIN_CFG(2, ALT_B)
29#define GPIO2_IP_TMS PIN_CFG(2, ALT_C)
30
31#define GPIO3_GPIO PIN_CFG(3, GPIO)
32#define GPIO3_U0_TXD PIN_CFG(3, ALT_A)
33#define GPIO3_NONE PIN_CFG(3, ALT_B)
34#define GPIO3_IP_TCK PIN_CFG(3, ALT_C)
35
36#define GPIO4_GPIO PIN_CFG(4, GPIO)
37#define GPIO4_U1_RXD PIN_CFG(4, ALT_A)
38#define GPIO4_I2C4_SCL PIN_CFG(4, ALT_B)
39#define GPIO4_IP_TRSTn PIN_CFG(4, ALT_C)
40
41#define GPIO5_GPIO PIN_CFG(5, GPIO)
42#define GPIO5_U1_TXD PIN_CFG(5, ALT_A)
43#define GPIO5_I2C4_SDA PIN_CFG(5, ALT_B)
44#define GPIO5_IP_GPIO6 PIN_CFG(5, ALT_C)
45
46#define GPIO6_GPIO PIN_CFG(6, GPIO)
47#define GPIO6_U1_CTSn PIN_CFG(6, ALT_A)
48#define GPIO6_I2C1_SCL PIN_CFG(6, ALT_B)
49#define GPIO6_IP_GPIO0 PIN_CFG(6, ALT_C)
50
51#define GPIO7_GPIO PIN_CFG(7, GPIO)
52#define GPIO7_U1_RTSn PIN_CFG(7, ALT_A)
53#define GPIO7_I2C1_SDA PIN_CFG(7, ALT_B)
54#define GPIO7_IP_GPIO1 PIN_CFG(7, ALT_C)
55
56#define GPIO8_GPIO PIN_CFG(8, GPIO)
57#define GPIO8_IPI2C_SDA PIN_CFG(8, ALT_A)
58#define GPIO8_I2C2_SDA PIN_CFG(8, ALT_B)
59
60#define GPIO9_GPIO PIN_CFG(9, GPIO)
61#define GPIO9_IPI2C_SCL PIN_CFG(9, ALT_A)
62#define GPIO9_I2C2_SCL PIN_CFG(9, ALT_B)
63
64#define GPIO10_GPIO PIN_CFG(10, GPIO)
65#define GPIO10_IPI2C_SDA PIN_CFG(10, ALT_A)
66#define GPIO10_I2C2_SDA PIN_CFG(10, ALT_B)
67#define GPIO10_IP_GPIO3 PIN_CFG(10, ALT_C)
68
69#define GPIO11_GPIO PIN_CFG(11, GPIO)
70#define GPIO11_IPI2C_SCL PIN_CFG(11, ALT_A)
71#define GPIO11_I2C2_SCL PIN_CFG(11, ALT_B)
72#define GPIO11_IP_GPIO2 PIN_CFG(11, ALT_C)
73
74#define GPIO12_GPIO PIN_CFG(12, GPIO)
75#define GPIO12_MSP0_TXD PIN_CFG(12, ALT_A)
76#define GPIO12_MSP0_RXD PIN_CFG(12, ALT_B)
77
78#define GPIO13_GPIO PIN_CFG(13, GPIO)
79#define GPIO13_MSP0_TFS PIN_CFG(13, ALT_A)
80
81#define GPIO14_GPIO PIN_CFG(14, GPIO)
82#define GPIO14_MSP0_TCK PIN_CFG(14, ALT_A)
83
84#define GPIO15_GPIO PIN_CFG(15, GPIO)
85#define GPIO15_MSP0_RXD PIN_CFG(15, ALT_A)
86#define GPIO15_MSP0_TXD PIN_CFG(15, ALT_B)
87
88#define GPIO16_GPIO PIN_CFG(16, GPIO)
89#define GPIO16_MSP0_RFS PIN_CFG(16, ALT_A)
90#define GPIO16_I2C1_SCL PIN_CFG(16, ALT_B)
91#define GPIO16_SLIM0_DAT PIN_CFG(16, ALT_C)
92
93#define GPIO17_GPIO PIN_CFG(17, GPIO)
94#define GPIO17_MSP0_RCK PIN_CFG(17, ALT_A)
95#define GPIO17_I2C1_SDA PIN_CFG(17, ALT_B)
96#define GPIO17_SLIM0_CLK PIN_CFG(17, ALT_C)
97
98#define GPIO18_GPIO PIN_CFG(18, GPIO)
99#define GPIO18_MC0_CMDDIR PIN_CFG_INPUT(18, ALT_A, PULLUP)
100#define GPIO18_U2_RXD PIN_CFG(18, ALT_B)
101#define GPIO18_MS_IEP PIN_CFG(18, ALT_C)
102
103#define GPIO19_GPIO PIN_CFG(19, GPIO)
104#define GPIO19_MC0_DAT0DIR PIN_CFG_INPUT(19, ALT_A, PULLUP)
105#define GPIO19_U2_TXD PIN_CFG(19, ALT_B)
106#define GPIO19_MS_DAT0DIR PIN_CFG(19, ALT_C)
107
108#define GPIO20_GPIO PIN_CFG(20, GPIO)
109#define GPIO20_MC0_DAT2DIR PIN_CFG_INPUT(20, ALT_A, PULLUP)
110#define GPIO20_UARTMOD_TXD PIN_CFG(20, ALT_B)
111#define GPIO20_IP_TRIGOUT PIN_CFG(20, ALT_C)
112
113#define GPIO21_GPIO PIN_CFG(21, GPIO)
114#define GPIO21_MC0_DAT31DIR PIN_CFG_INPUT(21, ALT_A, PULLUP)
115#define GPIO21_MSP0_SCK PIN_CFG(21, ALT_B)
116#define GPIO21_MS_DAT31DIR PIN_CFG(21, ALT_C)
117
118#define GPIO22_GPIO PIN_CFG(22, GPIO)
119#define GPIO22_MC0_FBCLK PIN_CFG_INPUT(22, ALT_A, PULLUP)
120#define GPIO22_UARTMOD_RXD PIN_CFG(22, ALT_B)
121#define GPIO22_MS_FBCLK PIN_CFG(22, ALT_C)
122
123#define GPIO23_GPIO PIN_CFG(23, GPIO)
124#define GPIO23_MC0_CLK PIN_CFG_INPUT(23, ALT_A, PULLUP)
125#define GPIO23_STMMOD_CLK PIN_CFG(23, ALT_B)
126#define GPIO23_MS_CLK PIN_CFG(23, ALT_C)
127
128#define GPIO24_GPIO PIN_CFG(24, GPIO)
129#define GPIO24_MC0_CMD PIN_CFG_INPUT(24, ALT_A, PULLUP)
130#define GPIO24_UARTMOD_RXD PIN_CFG(24, ALT_B)
131#define GPIO24_MS_BS PIN_CFG(24, ALT_C)
132
133#define GPIO25_GPIO PIN_CFG(25, GPIO)
134#define GPIO25_MC0_DAT0 PIN_CFG_INPUT(25, ALT_A, PULLUP)
135#define GPIO25_STMMOD_DAT0 PIN_CFG(25, ALT_B)
136#define GPIO25_MS_DAT0 PIN_CFG(25, ALT_C)
137
138#define GPIO26_GPIO PIN_CFG(26, GPIO)
139#define GPIO26_MC0_DAT1 PIN_CFG_INPUT(26, ALT_A, PULLUP)
140#define GPIO26_STMMOD_DAT1 PIN_CFG(26, ALT_B)
141#define GPIO26_MS_DAT1 PIN_CFG(26, ALT_C)
142
143#define GPIO27_GPIO PIN_CFG(27, GPIO)
144#define GPIO27_MC0_DAT2 PIN_CFG_INPUT(27, ALT_A, PULLUP)
145#define GPIO27_STMMOD_DAT2 PIN_CFG(27, ALT_B)
146#define GPIO27_MS_DAT2 PIN_CFG(27, ALT_C)
147
148#define GPIO28_GPIO PIN_CFG(28, GPIO)
149#define GPIO28_MC0_DAT3 PIN_CFG_INPUT(28, ALT_A, PULLUP)
150#define GPIO28_STMMOD_DAT3 PIN_CFG(28, ALT_B)
151#define GPIO28_MS_DAT3 PIN_CFG(28, ALT_C)
152
153#define GPIO29_GPIO PIN_CFG(29, GPIO)
154#define GPIO29_MC0_DAT4 PIN_CFG(29, ALT_A)
155#define GPIO29_SPI3_CLK PIN_CFG(29, ALT_B)
156#define GPIO29_U2_RXD PIN_CFG(29, ALT_C)
157
158#define GPIO30_GPIO PIN_CFG(30, GPIO)
159#define GPIO30_MC0_DAT5 PIN_CFG(30, ALT_A)
160#define GPIO30_SPI3_RXD PIN_CFG(30, ALT_B)
161#define GPIO30_U2_TXD PIN_CFG(30, ALT_C)
162
163#define GPIO31_GPIO PIN_CFG(31, GPIO)
164#define GPIO31_MC0_DAT6 PIN_CFG(31, ALT_A)
165#define GPIO31_SPI3_FRM PIN_CFG(31, ALT_B)
166#define GPIO31_U2_CTSn PIN_CFG(31, ALT_C)
167
168#define GPIO32_GPIO PIN_CFG(32, GPIO)
169#define GPIO32_MC0_DAT7 PIN_CFG(32, ALT_A)
170#define GPIO32_SPI3_TXD PIN_CFG(32, ALT_B)
171#define GPIO32_U2_RTSn PIN_CFG(32, ALT_C)
172
173#define GPIO33_GPIO PIN_CFG(33, GPIO)
174#define GPIO33_MSP1_TXD PIN_CFG(33, ALT_A)
175#define GPIO33_MSP1_RXD PIN_CFG(33, ALT_B)
176#define GPIO33_U0_DTRn PIN_CFG(33, ALT_C)
177
178#define GPIO34_GPIO PIN_CFG(34, GPIO)
179#define GPIO34_MSP1_TFS PIN_CFG(34, ALT_A)
180#define GPIO34_NONE PIN_CFG(34, ALT_B)
181#define GPIO34_U0_DCDn PIN_CFG(34, ALT_C)
182
183#define GPIO35_GPIO PIN_CFG(35, GPIO)
184#define GPIO35_MSP1_TCK PIN_CFG(35, ALT_A)
185#define GPIO35_NONE PIN_CFG(35, ALT_B)
186#define GPIO35_U0_DSRn PIN_CFG(35, ALT_C)
187
188#define GPIO36_GPIO PIN_CFG(36, GPIO)
189#define GPIO36_MSP1_RXD PIN_CFG(36, ALT_A)
190#define GPIO36_MSP1_TXD PIN_CFG(36, ALT_B)
191#define GPIO36_U0_RIn PIN_CFG(36, ALT_C)
192
193#define GPIO64_GPIO PIN_CFG(64, GPIO)
194#define GPIO64_LCDB_DE PIN_CFG(64, ALT_A)
195#define GPIO64_KP_O1 PIN_CFG(64, ALT_B)
196#define GPIO64_IP_GPIO4 PIN_CFG(64, ALT_C)
197
198#define GPIO65_GPIO PIN_CFG(65, GPIO)
199#define GPIO65_LCDB_HSO PIN_CFG(65, ALT_A)
200#define GPIO65_KP_O0 PIN_CFG(65, ALT_B)
201#define GPIO65_IP_GPIO5 PIN_CFG(65, ALT_C)
202
203#define GPIO66_GPIO PIN_CFG(66, GPIO)
204#define GPIO66_LCDB_VSO PIN_CFG(66, ALT_A)
205#define GPIO66_KP_I1 PIN_CFG(66, ALT_B)
206#define GPIO66_IP_GPIO6 PIN_CFG(66, ALT_C)
207
208#define GPIO67_GPIO PIN_CFG(67, GPIO)
209#define GPIO67_LCDB_CLK PIN_CFG(67, ALT_A)
210#define GPIO67_KP_I0 PIN_CFG(67, ALT_B)
211#define GPIO67_IP_GPIO7 PIN_CFG(67, ALT_C)
212
213#define GPIO68_GPIO PIN_CFG(68, GPIO)
214#define GPIO68_LCD_VSI0 PIN_CFG(68, ALT_A)
215#define GPIO68_KP_O7 PIN_CFG(68, ALT_B)
216#define GPIO68_SM_CLE PIN_CFG(68, ALT_C)
217
218#define GPIO69_GPIO PIN_CFG(69, GPIO)
219#define GPIO69_LCD_VSI1 PIN_CFG(69, ALT_A)
220#define GPIO69_KP_I7 PIN_CFG(69, ALT_B)
221#define GPIO69_SM_ALE PIN_CFG(69, ALT_C)
222
223#define GPIO70_GPIO PIN_CFG(70, GPIO)
224#define GPIO70_LCD_D0 PIN_CFG(70, ALT_A)
225#define GPIO70_KP_O5 PIN_CFG(70, ALT_B)
226#define GPIO70_STMAPE_CLK PIN_CFG(70, ALT_C)
227
228#define GPIO71_GPIO PIN_CFG(71, GPIO)
229#define GPIO71_LCD_D1 PIN_CFG(71, ALT_A)
230#define GPIO71_KP_O4 PIN_CFG(71, ALT_B)
231#define GPIO71_STMAPE_DAT3 PIN_CFG(71, ALT_C)
232
233#define GPIO72_GPIO PIN_CFG(72, GPIO)
234#define GPIO72_LCD_D2 PIN_CFG(72, ALT_A)
235#define GPIO72_KP_O3 PIN_CFG(72, ALT_B)
236#define GPIO72_STMAPE_DAT2 PIN_CFG(72, ALT_C)
237
238#define GPIO73_GPIO PIN_CFG(73, GPIO)
239#define GPIO73_LCD_D3 PIN_CFG(73, ALT_A)
240#define GPIO73_KP_O2 PIN_CFG(73, ALT_B)
241#define GPIO73_STMAPE_DAT1 PIN_CFG(73, ALT_C)
242
243#define GPIO74_GPIO PIN_CFG(74, GPIO)
244#define GPIO74_LCD_D4 PIN_CFG(74, ALT_A)
245#define GPIO74_KP_I5 PIN_CFG(74, ALT_B)
246#define GPIO74_STMAPE_DAT0 PIN_CFG(74, ALT_C)
247
248#define GPIO75_GPIO PIN_CFG(75, GPIO)
249#define GPIO75_LCD_D5 PIN_CFG(75, ALT_A)
250#define GPIO75_KP_I4 PIN_CFG(75, ALT_B)
251#define GPIO75_U2_RXD PIN_CFG(75, ALT_C)
252
253#define GPIO76_GPIO PIN_CFG(76, GPIO)
254#define GPIO76_LCD_D6 PIN_CFG(76, ALT_A)
255#define GPIO76_KP_I3 PIN_CFG(76, ALT_B)
256#define GPIO76_U2_TXD PIN_CFG(76, ALT_C)
257
258#define GPIO77_GPIO PIN_CFG(77, GPIO)
259#define GPIO77_LCD_D7 PIN_CFG(77, ALT_A)
260#define GPIO77_KP_I2 PIN_CFG(77, ALT_B)
261#define GPIO77_NONE PIN_CFG(77, ALT_C)
262
263#define GPIO78_GPIO PIN_CFG(78, GPIO)
264#define GPIO78_LCD_D8 PIN_CFG(78, ALT_A)
265#define GPIO78_KP_O6 PIN_CFG(78, ALT_B)
266#define GPIO78_IP_GPIO2 PIN_CFG(78, ALT_C)
267
268#define GPIO79_GPIO PIN_CFG(79, GPIO)
269#define GPIO79_LCD_D9 PIN_CFG(79, ALT_A)
270#define GPIO79_KP_I6 PIN_CFG(79, ALT_B)
271#define GPIO79_IP_GPIO3 PIN_CFG(79, ALT_C)
272
273#define GPIO80_GPIO PIN_CFG(80, GPIO)
274#define GPIO80_LCD_D10 PIN_CFG(80, ALT_A)
275#define GPIO80_KP_SKA0 PIN_CFG(80, ALT_B)
276#define GPIO80_IP_GPIO4 PIN_CFG(80, ALT_C)
277
278#define GPIO81_GPIO PIN_CFG(81, GPIO)
279#define GPIO81_LCD_D11 PIN_CFG(81, ALT_A)
280#define GPIO81_KP_SKB0 PIN_CFG(81, ALT_B)
281#define GPIO81_IP_GPIO5 PIN_CFG(81, ALT_C)
282
283#define GPIO82_GPIO PIN_CFG(82, GPIO)
284#define GPIO82_LCD_D12 PIN_CFG(82, ALT_A)
285#define GPIO82_KP_O5 PIN_CFG(82, ALT_B)
286
287#define GPIO83_GPIO PIN_CFG(83, GPIO)
288#define GPIO83_LCD_D13 PIN_CFG(83, ALT_A)
289#define GPIO83_KP_O4 PIN_CFG(83, ALT_B)
290
291#define GPIO84_GPIO PIN_CFG(84, GPIO)
292#define GPIO84_LCD_D14 PIN_CFG(84, ALT_A)
293#define GPIO84_KP_I5 PIN_CFG(84, ALT_B)
294
295#define GPIO85_GPIO PIN_CFG(85, GPIO)
296#define GPIO85_LCD_D15 PIN_CFG(85, ALT_A)
297#define GPIO85_KP_I4 PIN_CFG(85, ALT_B)
298
299#define GPIO86_GPIO PIN_CFG(86, GPIO)
300#define GPIO86_LCD_D16 PIN_CFG(86, ALT_A)
301#define GPIO86_SM_ADQ0 PIN_CFG(86, ALT_B)
302#define GPIO86_MC5_DAT0 PIN_CFG(86, ALT_C)
303
304#define GPIO87_GPIO PIN_CFG(87, GPIO)
305#define GPIO87_LCD_D17 PIN_CFG(87, ALT_A)
306#define GPIO87_SM_ADQ1 PIN_CFG(87, ALT_B)
307#define GPIO87_MC5_DAT1 PIN_CFG(87, ALT_C)
308
309#define GPIO88_GPIO PIN_CFG(88, GPIO)
310#define GPIO88_LCD_D18 PIN_CFG(88, ALT_A)
311#define GPIO88_SM_ADQ2 PIN_CFG(88, ALT_B)
312#define GPIO88_MC5_DAT2 PIN_CFG(88, ALT_C)
313
314#define GPIO89_GPIO PIN_CFG(89, GPIO)
315#define GPIO89_LCD_D19 PIN_CFG(89, ALT_A)
316#define GPIO89_SM_ADQ3 PIN_CFG(89, ALT_B)
317#define GPIO89_MC5_DAT3 PIN_CFG(89, ALT_C)
318
319#define GPIO90_GPIO PIN_CFG(90, GPIO)
320#define GPIO90_LCD_D20 PIN_CFG(90, ALT_A)
321#define GPIO90_SM_ADQ4 PIN_CFG(90, ALT_B)
322#define GPIO90_MC5_CMD PIN_CFG(90, ALT_C)
323
324#define GPIO91_GPIO PIN_CFG(91, GPIO)
325#define GPIO91_LCD_D21 PIN_CFG(91, ALT_A)
326#define GPIO91_SM_ADQ5 PIN_CFG(91, ALT_B)
327#define GPIO91_MC5_FBCLK PIN_CFG(91, ALT_C)
328
329#define GPIO92_GPIO PIN_CFG(92, GPIO)
330#define GPIO92_LCD_D22 PIN_CFG(92, ALT_A)
331#define GPIO92_SM_ADQ6 PIN_CFG(92, ALT_B)
332#define GPIO92_MC5_CLK PIN_CFG(92, ALT_C)
333
334#define GPIO93_GPIO PIN_CFG(93, GPIO)
335#define GPIO93_LCD_D23 PIN_CFG(93, ALT_A)
336#define GPIO93_SM_ADQ7 PIN_CFG(93, ALT_B)
337#define GPIO93_MC5_DAT4 PIN_CFG(93, ALT_C)
338
339#define GPIO94_GPIO PIN_CFG(94, GPIO)
340#define GPIO94_KP_O7 PIN_CFG(94, ALT_A)
341#define GPIO94_SM_ADVn PIN_CFG(94, ALT_B)
342#define GPIO94_MC5_DAT5 PIN_CFG(94, ALT_C)
343
344#define GPIO95_GPIO PIN_CFG(95, GPIO)
345#define GPIO95_KP_I7 PIN_CFG(95, ALT_A)
346#define GPIO95_SM_CS0n PIN_CFG(95, ALT_B)
347#define GPIO95_SM_PS0n PIN_CFG(95, ALT_C)
348
349#define GPIO96_GPIO PIN_CFG(96, GPIO)
350#define GPIO96_KP_O6 PIN_CFG(96, ALT_A)
351#define GPIO96_SM_OEn PIN_CFG(96, ALT_B)
352#define GPIO96_MC5_DAT6 PIN_CFG(96, ALT_C)
353
354#define GPIO97_GPIO PIN_CFG(97, GPIO)
355#define GPIO97_KP_I6 PIN_CFG(97, ALT_A)
356#define GPIO97_SM_WEn PIN_CFG(97, ALT_B)
357#define GPIO97_MC5_DAT7 PIN_CFG(97, ALT_C)
358
359#define GPIO128_GPIO PIN_CFG(128, GPIO)
360#define GPIO128_MC2_CLK PIN_CFG_INPUT(128, ALT_A, PULLUP)
361#define GPIO128_SM_CKO PIN_CFG(128, ALT_B)
362
363#define GPIO129_GPIO PIN_CFG(129, GPIO)
364#define GPIO129_MC2_CMD PIN_CFG_INPUT(129, ALT_A, PULLUP)
365#define GPIO129_SM_WAIT0n PIN_CFG(129, ALT_B)
366
367#define GPIO130_GPIO PIN_CFG(130, GPIO)
368#define GPIO130_MC2_FBCLK PIN_CFG_INPUT(130, ALT_A, PULLUP)
369#define GPIO130_SM_FBCLK PIN_CFG(130, ALT_B)
370#define GPIO130_MC2_RSTN PIN_CFG(130, ALT_C)
371
372#define GPIO131_GPIO PIN_CFG(131, GPIO)
373#define GPIO131_MC2_DAT0 PIN_CFG_INPUT(131, ALT_A, PULLUP)
374#define GPIO131_SM_ADQ8 PIN_CFG(131, ALT_B)
375
376#define GPIO132_GPIO PIN_CFG(132, GPIO)
377#define GPIO132_MC2_DAT1 PIN_CFG_INPUT(132, ALT_A, PULLUP)
378#define GPIO132_SM_ADQ9 PIN_CFG(132, ALT_B)
379
380#define GPIO133_GPIO PIN_CFG(133, GPIO)
381#define GPIO133_MC2_DAT2 PIN_CFG_INPUT(133, ALT_A, PULLUP)
382#define GPIO133_SM_ADQ10 PIN_CFG(133, ALT_B)
383
384#define GPIO134_GPIO PIN_CFG(134, GPIO)
385#define GPIO134_MC2_DAT3 PIN_CFG_INPUT(134, ALT_A, PULLUP)
386#define GPIO134_SM_ADQ11 PIN_CFG(134, ALT_B)
387
388#define GPIO135_GPIO PIN_CFG(135, GPIO)
389#define GPIO135_MC2_DAT4 PIN_CFG_INPUT(135, ALT_A, PULLUP)
390#define GPIO135_SM_ADQ12 PIN_CFG(135, ALT_B)
391
392#define GPIO136_GPIO PIN_CFG(136, GPIO)
393#define GPIO136_MC2_DAT5 PIN_CFG_INPUT(136, ALT_A, PULLUP)
394#define GPIO136_SM_ADQ13 PIN_CFG(136, ALT_B)
395
396#define GPIO137_GPIO PIN_CFG(137, GPIO)
397#define GPIO137_MC2_DAT6 PIN_CFG_INPUT(137, ALT_A, PULLUP)
398#define GPIO137_SM_ADQ14 PIN_CFG(137, ALT_B)
399
400#define GPIO138_GPIO PIN_CFG(138, GPIO)
401#define GPIO138_MC2_DAT7 PIN_CFG_INPUT(138, ALT_A, PULLUP)
402#define GPIO138_SM_ADQ15 PIN_CFG(138, ALT_B)
403
404#define GPIO139_GPIO PIN_CFG(139, GPIO)
405#define GPIO139_SSP1_RXD PIN_CFG(139, ALT_A)
406#define GPIO139_SM_WAIT1n PIN_CFG(139, ALT_B)
407#define GPIO139_KP_O8 PIN_CFG(139, ALT_C)
408
409#define GPIO140_GPIO PIN_CFG(140, GPIO)
410#define GPIO140_SSP1_TXD PIN_CFG(140, ALT_A)
411#define GPIO140_IP_GPIO7 PIN_CFG(140, ALT_B)
412#define GPIO140_KP_SKA1 PIN_CFG(140, ALT_C)
413
414#define GPIO141_GPIO PIN_CFG(141, GPIO)
415#define GPIO141_SSP1_CLK PIN_CFG(141, ALT_A)
416#define GPIO141_IP_GPIO2 PIN_CFG(141, ALT_B)
417#define GPIO141_KP_O9 PIN_CFG(141, ALT_C)
418
419#define GPIO142_GPIO PIN_CFG(142, GPIO)
420#define GPIO142_SSP1_FRM PIN_CFG(142, ALT_A)
421#define GPIO142_IP_GPIO3 PIN_CFG(142, ALT_B)
422#define GPIO142_KP_SKB1 PIN_CFG(142, ALT_C)
423
424#define GPIO143_GPIO PIN_CFG(143, GPIO)
425#define GPIO143_SSP0_CLK PIN_CFG(143, ALT_A)
426
427#define GPIO144_GPIO PIN_CFG(144, GPIO)
428#define GPIO144_SSP0_FRM PIN_CFG(144, ALT_A)
429
430#define GPIO145_GPIO PIN_CFG(145, GPIO)
431#define GPIO145_SSP0_RXD PIN_CFG(145, ALT_A)
432
433#define GPIO146_GPIO PIN_CFG(146, GPIO)
434#define GPIO146_SSP0_TXD PIN_CFG(146, ALT_A)
435
436#define GPIO147_GPIO PIN_CFG(147, GPIO)
437#define GPIO147_I2C0_SCL PIN_CFG(147, ALT_A)
438
439#define GPIO148_GPIO PIN_CFG(148, GPIO)
440#define GPIO148_I2C0_SDA PIN_CFG(148, ALT_A)
441
442#define GPIO149_GPIO PIN_CFG(149, GPIO)
443#define GPIO149_IP_GPIO0 PIN_CFG(149, ALT_A)
444#define GPIO149_SM_CS1n PIN_CFG(149, ALT_B)
445#define GPIO149_SM_PS1n PIN_CFG(149, ALT_C)
446
447#define GPIO150_GPIO PIN_CFG(150, GPIO)
448#define GPIO150_IP_GPIO1 PIN_CFG(150, ALT_A)
449#define GPIO150_LCDA_CLK PIN_CFG(150, ALT_B)
450
451#define GPIO151_GPIO PIN_CFG(151, GPIO)
452#define GPIO151_KP_SKA0 PIN_CFG(151, ALT_A)
453#define GPIO151_LCD_VSI0 PIN_CFG(151, ALT_B)
454#define GPIO151_KP_O8 PIN_CFG(151, ALT_C)
455
456#define GPIO152_GPIO PIN_CFG(152, GPIO)
457#define GPIO152_KP_SKB0 PIN_CFG(152, ALT_A)
458#define GPIO152_LCD_VSI1 PIN_CFG(152, ALT_B)
459#define GPIO152_KP_O9 PIN_CFG(152, ALT_C)
460
461#define GPIO153_GPIO PIN_CFG(153, GPIO)
462#define GPIO153_KP_I7 PIN_CFG(153, ALT_A)
463#define GPIO153_LCD_D24 PIN_CFG(153, ALT_B)
464#define GPIO153_U2_RXD PIN_CFG(153, ALT_C)
465
466#define GPIO154_GPIO PIN_CFG(154, GPIO)
467#define GPIO154_KP_I6 PIN_CFG(154, ALT_A)
468#define GPIO154_LCD_D25 PIN_CFG(154, ALT_B)
469#define GPIO154_U2_TXD PIN_CFG(154, ALT_C)
470
471#define GPIO155_GPIO PIN_CFG(155, GPIO)
472#define GPIO155_KP_I5 PIN_CFG(155, ALT_A)
473#define GPIO155_LCD_D26 PIN_CFG(155, ALT_B)
474#define GPIO155_STMAPE_CLK PIN_CFG(155, ALT_C)
475
476#define GPIO156_GPIO PIN_CFG(156, GPIO)
477#define GPIO156_KP_I4 PIN_CFG(156, ALT_A)
478#define GPIO156_LCD_D27 PIN_CFG(156, ALT_B)
479#define GPIO156_STMAPE_DAT3 PIN_CFG(156, ALT_C)
480
481#define GPIO157_GPIO PIN_CFG(157, GPIO)
482#define GPIO157_KP_O7 PIN_CFG(157, ALT_A)
483#define GPIO157_LCD_D28 PIN_CFG(157, ALT_B)
484#define GPIO157_STMAPE_DAT2 PIN_CFG(157, ALT_C)
485
486#define GPIO158_GPIO PIN_CFG(158, GPIO)
487#define GPIO158_KP_O6 PIN_CFG(158, ALT_A)
488#define GPIO158_LCD_D29 PIN_CFG(158, ALT_B)
489#define GPIO158_STMAPE_DAT1 PIN_CFG(158, ALT_C)
490
491#define GPIO159_GPIO PIN_CFG(159, GPIO)
492#define GPIO159_KP_O5 PIN_CFG(159, ALT_A)
493#define GPIO159_LCD_D30 PIN_CFG(159, ALT_B)
494#define GPIO159_STMAPE_DAT0 PIN_CFG(159, ALT_C)
495
496#define GPIO160_GPIO PIN_CFG(160, GPIO)
497#define GPIO160_KP_O4 PIN_CFG(160, ALT_A)
498#define GPIO160_LCD_D31 PIN_CFG(160, ALT_B)
499#define GPIO160_NONE PIN_CFG(160, ALT_C)
500
501#define GPIO161_GPIO PIN_CFG(161, GPIO)
502#define GPIO161_KP_I3 PIN_CFG(161, ALT_A)
503#define GPIO161_LCD_D32 PIN_CFG(161, ALT_B)
504#define GPIO161_UARTMOD_RXD PIN_CFG(161, ALT_C)
505
506#define GPIO162_GPIO PIN_CFG(162, GPIO)
507#define GPIO162_KP_I2 PIN_CFG(162, ALT_A)
508#define GPIO162_LCD_D33 PIN_CFG(162, ALT_B)
509#define GPIO162_UARTMOD_TXD PIN_CFG(162, ALT_C)
510
511#define GPIO163_GPIO PIN_CFG(163, GPIO)
512#define GPIO163_KP_I1 PIN_CFG(163, ALT_A)
513#define GPIO163_LCD_D34 PIN_CFG(163, ALT_B)
514#define GPIO163_STMMOD_CLK PIN_CFG(163, ALT_C)
515
516#define GPIO164_GPIO PIN_CFG(164, GPIO)
517#define GPIO164_KP_I0 PIN_CFG(164, ALT_A)
518#define GPIO164_LCD_D35 PIN_CFG(164, ALT_B)
519#define GPIO164_STMMOD_DAT3 PIN_CFG(164, ALT_C)
520
521#define GPIO165_GPIO PIN_CFG(165, GPIO)
522#define GPIO165_KP_O3 PIN_CFG(165, ALT_A)
523#define GPIO165_LCD_D36 PIN_CFG(165, ALT_B)
524#define GPIO165_STMMOD_DAT2 PIN_CFG(165, ALT_C)
525
526#define GPIO166_GPIO PIN_CFG(166, GPIO)
527#define GPIO166_KP_O2 PIN_CFG(166, ALT_A)
528#define GPIO166_LCD_D37 PIN_CFG(166, ALT_B)
529#define GPIO166_STMMOD_DAT1 PIN_CFG(166, ALT_C)
530
531#define GPIO167_GPIO PIN_CFG(167, GPIO)
532#define GPIO167_KP_O1 PIN_CFG(167, ALT_A)
533#define GPIO167_LCD_D38 PIN_CFG(167, ALT_B)
534#define GPIO167_STMMOD_DAT0 PIN_CFG(167, ALT_C)
535
536#define GPIO168_GPIO PIN_CFG(168, GPIO)
537#define GPIO168_KP_O0 PIN_CFG(168, ALT_A)
538#define GPIO168_LCD_D39 PIN_CFG(168, ALT_B)
539#define GPIO168_NONE PIN_CFG(168, ALT_C)
540
541#define GPIO169_GPIO PIN_CFG(169, GPIO)
542#define GPIO169_RF_PURn PIN_CFG(169, ALT_A)
543#define GPIO169_LCDA_DE PIN_CFG(169, ALT_B)
544#define GPIO169_USBSIM_PDC PIN_CFG(169, ALT_C)
545
546#define GPIO170_GPIO PIN_CFG(170, GPIO)
547#define GPIO170_MODEM_STATE PIN_CFG(170, ALT_A)
548#define GPIO170_LCDA_VSO PIN_CFG(170, ALT_B)
549#define GPIO170_KP_SKA1 PIN_CFG(170, ALT_C)
550
551#define GPIO171_GPIO PIN_CFG(171, GPIO)
552#define GPIO171_MODEM_PWREN PIN_CFG(171, ALT_A)
553#define GPIO171_LCDA_HSO PIN_CFG(171, ALT_B)
554#define GPIO171_KP_SKB1 PIN_CFG(171, ALT_C)
555
556#define GPIO192_GPIO PIN_CFG(192, GPIO)
557#define GPIO192_MSP2_SCK PIN_CFG(192, ALT_A)
558
559#define GPIO193_GPIO PIN_CFG(193, GPIO)
560#define GPIO193_MSP2_TXD PIN_CFG(193, ALT_A)
561
562#define GPIO194_GPIO PIN_CFG(194, GPIO)
563#define GPIO194_MSP2_TCK PIN_CFG(194, ALT_A)
564
565#define GPIO195_GPIO PIN_CFG(195, GPIO)
566#define GPIO195_MSP2_TFS PIN_CFG(195, ALT_A)
567
568#define GPIO196_GPIO PIN_CFG(196, GPIO)
569#define GPIO196_MSP2_RXD PIN_CFG(196, ALT_A)
570
571#define GPIO197_GPIO PIN_CFG(197, GPIO)
572#define GPIO197_MC4_DAT3 PIN_CFG_INPUT(197, ALT_A, PULLUP)
573
574#define GPIO198_GPIO PIN_CFG(198, GPIO)
575#define GPIO198_MC4_DAT2 PIN_CFG_INPUT(198, ALT_A, PULLUP)
576
577#define GPIO199_GPIO PIN_CFG(199, GPIO)
578#define GPIO199_MC4_DAT1 PIN_CFG_INPUT(199, ALT_A, PULLUP)
579
580#define GPIO200_GPIO PIN_CFG(200, GPIO)
581#define GPIO200_MC4_DAT0 PIN_CFG_INPUT(200, ALT_A, PULLUP)
582
583#define GPIO201_GPIO PIN_CFG(201, GPIO)
584#define GPIO201_MC4_CMD PIN_CFG_INPUT(201, ALT_A, PULLUP)
585
586#define GPIO202_GPIO PIN_CFG(202, GPIO)
587#define GPIO202_MC4_FBCLK PIN_CFG_INPUT(202, ALT_A, PULLUP)
588#define GPIO202_PWL PIN_CFG(202, ALT_B)
589#define GPIO202_MC4_RSTN PIN_CFG(202, ALT_C)
590
591#define GPIO203_GPIO PIN_CFG(203, GPIO)
592#define GPIO203_MC4_CLK PIN_CFG_INPUT(203, ALT_A, PULLUP)
593
594#define GPIO204_GPIO PIN_CFG(204, GPIO)
595#define GPIO204_MC4_DAT7 PIN_CFG_INPUT(204, ALT_A, PULLUP)
596
597#define GPIO205_GPIO PIN_CFG(205, GPIO)
598#define GPIO205_MC4_DAT6 PIN_CFG_INPUT(205, ALT_A, PULLUP)
599
600#define GPIO206_GPIO PIN_CFG(206, GPIO)
601#define GPIO206_MC4_DAT5 PIN_CFG_INPUT(206, ALT_A, PULLUP)
602
603#define GPIO207_GPIO PIN_CFG(207, GPIO)
604#define GPIO207_MC4_DAT4 PIN_CFG_INPUT(207, ALT_A, PULLUP)
605
606#define GPIO208_GPIO PIN_CFG(208, GPIO)
607#define GPIO208_MC1_CLK PIN_CFG(208, ALT_A)
608
609#define GPIO209_GPIO PIN_CFG(209, GPIO)
610#define GPIO209_MC1_FBCLK PIN_CFG(209, ALT_A)
611#define GPIO209_SPI1_CLK PIN_CFG(209, ALT_B)
612
613#define GPIO210_GPIO PIN_CFG(210, GPIO)
614#define GPIO210_MC1_CMD PIN_CFG(210, ALT_A)
615
616#define GPIO211_GPIO PIN_CFG(211, GPIO)
617#define GPIO211_MC1_DAT0 PIN_CFG(211, ALT_A)
618
619#define GPIO212_GPIO PIN_CFG(212, GPIO)
620#define GPIO212_MC1_DAT1 PIN_CFG(212, ALT_A)
621#define GPIO212_SPI1_FRM PIN_CFG(212, ALT_B)
622
623#define GPIO213_GPIO PIN_CFG(213, GPIO)
624#define GPIO213_MC1_DAT2 PIN_CFG(213, ALT_A)
625#define GPIO213_SPI1_TXD PIN_CFG(213, ALT_B)
626
627#define GPIO214_GPIO PIN_CFG(214, GPIO)
628#define GPIO214_MC1_DAT3 PIN_CFG(214, ALT_A)
629#define GPIO214_SPI1_RXD PIN_CFG(214, ALT_B)
630
631#define GPIO215_GPIO PIN_CFG(215, GPIO)
632#define GPIO215_MC1_CMDDIR PIN_CFG(215, ALT_A)
633#define GPIO215_MC3_DAT2DIR PIN_CFG(215, ALT_B)
634#define GPIO215_CLKOUT1 PIN_CFG(215, ALT_C)
635#define GPIO215_SPI2_TXD PIN_CFG(215, ALT_C)
636
637#define GPIO216_GPIO PIN_CFG(216, GPIO)
638#define GPIO216_MC1_DAT2DIR PIN_CFG(216, ALT_A)
639#define GPIO216_MC3_CMDDIR PIN_CFG(216, ALT_B)
640#define GPIO216_I2C3_SDA PIN_CFG(216, ALT_C)
641#define GPIO216_SPI2_FRM PIN_CFG(216, ALT_C)
642
643#define GPIO217_GPIO PIN_CFG(217, GPIO)
644#define GPIO217_MC1_DAT0DIR PIN_CFG(217, ALT_A)
645#define GPIO217_MC3_DAT31DIR PIN_CFG(217, ALT_B)
646#define GPIO217_CLKOUT2 PIN_CFG(217, ALT_C)
647#define GPIO217_SPI2_CLK PIN_CFG(217, ALT_C)
648
649#define GPIO218_GPIO PIN_CFG(218, GPIO)
650#define GPIO218_MC1_DAT31DIR PIN_CFG(218, ALT_A)
651#define GPIO218_MC3_DAT0DIR PIN_CFG(218, ALT_B)
652#define GPIO218_I2C3_SCL PIN_CFG(218, ALT_C)
653#define GPIO218_SPI2_RXD PIN_CFG(218, ALT_C)
654
655#define GPIO219_GPIO PIN_CFG(219, GPIO)
656#define GPIO219_HSIR_FLA0 PIN_CFG(219, ALT_A)
657#define GPIO219_MC3_CLK PIN_CFG(219, ALT_B)
658
659#define GPIO220_GPIO PIN_CFG(220, GPIO)
660#define GPIO220_HSIR_DAT0 PIN_CFG(220, ALT_A)
661#define GPIO220_MC3_FBCLK PIN_CFG(220, ALT_B)
662#define GPIO220_SPI0_CLK PIN_CFG(220, ALT_C)
663
664#define GPIO221_GPIO PIN_CFG(221, GPIO)
665#define GPIO221_HSIR_RDY0 PIN_CFG(221, ALT_A)
666#define GPIO221_MC3_CMD PIN_CFG(221, ALT_B)
667
668#define GPIO222_GPIO PIN_CFG(222, GPIO)
669#define GPIO222_HSIT_FLA0 PIN_CFG(222, ALT_A)
670#define GPIO222_MC3_DAT0 PIN_CFG(222, ALT_B)
671
672#define GPIO223_GPIO PIN_CFG(223, GPIO)
673#define GPIO223_HSIT_DAT0 PIN_CFG(223, ALT_A)
674#define GPIO223_MC3_DAT1 PIN_CFG(223, ALT_B)
675#define GPIO223_SPI0_FRM PIN_CFG(223, ALT_C)
676
677#define GPIO224_GPIO PIN_CFG(224, GPIO)
678#define GPIO224_HSIT_RDY0 PIN_CFG(224, ALT_A)
679#define GPIO224_MC3_DAT2 PIN_CFG(224, ALT_B)
680#define GPIO224_SPI0_TXD PIN_CFG(224, ALT_C)
681
682#define GPIO225_GPIO PIN_CFG(225, GPIO)
683#define GPIO225_HSIT_CAWAKE0 PIN_CFG(225, ALT_A)
684#define GPIO225_MC3_DAT3 PIN_CFG(225, ALT_B)
685#define GPIO225_SPI0_RXD PIN_CFG(225, ALT_C)
686
687#define GPIO226_GPIO PIN_CFG(226, GPIO)
688#define GPIO226_HSIT_ACWAKE0 PIN_CFG(226, ALT_A)
689#define GPIO226_PWL PIN_CFG(226, ALT_B)
690#define GPIO226_USBSIM_PDC PIN_CFG(226, ALT_C)
691
692#define GPIO227_GPIO PIN_CFG(227, GPIO)
693#define GPIO227_CLKOUT1 PIN_CFG(227, ALT_A)
694
695#define GPIO228_GPIO PIN_CFG(228, GPIO)
696#define GPIO228_CLKOUT2 PIN_CFG(228, ALT_A)
697
698#define GPIO229_GPIO PIN_CFG(229, GPIO)
699#define GPIO229_CLKOUT1 PIN_CFG(229, ALT_A)
700#define GPIO229_PWL PIN_CFG(229, ALT_B)
701#define GPIO229_I2C3_SDA PIN_CFG(229, ALT_C)
702
703#define GPIO230_GPIO PIN_CFG(230, GPIO)
704#define GPIO230_CLKOUT2 PIN_CFG(230, ALT_A)
705#define GPIO230_PWL PIN_CFG(230, ALT_B)
706#define GPIO230_I2C3_SCL PIN_CFG(230, ALT_C)
707
708#define GPIO256_GPIO PIN_CFG(256, GPIO)
709#define GPIO256_USB_NXT PIN_CFG(256, ALT_A)
710
711#define GPIO257_GPIO PIN_CFG(257, GPIO)
712#define GPIO257_USB_STP PIN_CFG(257, ALT_A)
713
714#define GPIO258_GPIO PIN_CFG(258, GPIO)
715#define GPIO258_USB_XCLK PIN_CFG(258, ALT_A)
716#define GPIO258_NONE PIN_CFG(258, ALT_B)
717#define GPIO258_DDR_TRIG PIN_CFG(258, ALT_C)
718
719#define GPIO259_GPIO PIN_CFG(259, GPIO)
720#define GPIO259_USB_DIR PIN_CFG(259, ALT_A)
721
722#define GPIO260_GPIO PIN_CFG(260, GPIO)
723#define GPIO260_USB_DAT7 PIN_CFG(260, ALT_A)
724
725#define GPIO261_GPIO PIN_CFG(261, GPIO)
726#define GPIO261_USB_DAT6 PIN_CFG(261, ALT_A)
727
728#define GPIO262_GPIO PIN_CFG(262, GPIO)
729#define GPIO262_USB_DAT5 PIN_CFG(262, ALT_A)
730
731#define GPIO263_GPIO PIN_CFG(263, GPIO)
732#define GPIO263_USB_DAT4 PIN_CFG(263, ALT_A)
733
734#define GPIO264_GPIO PIN_CFG(264, GPIO)
735#define GPIO264_USB_DAT3 PIN_CFG(264, ALT_A)
736
737#define GPIO265_GPIO PIN_CFG(265, GPIO)
738#define GPIO265_USB_DAT2 PIN_CFG(265, ALT_A)
739
740#define GPIO266_GPIO PIN_CFG(266, GPIO)
741#define GPIO266_USB_DAT1 PIN_CFG(266, ALT_A)
742
743#define GPIO267_GPIO PIN_CFG(267, GPIO)
744#define GPIO267_USB_DAT0 PIN_CFG(267, ALT_A)
745
746#endif
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 7b0cb3b524f1..93cbf566a972 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -208,7 +208,7 @@ static void __init arm_bootmem_init(unsigned long start_pfn,
208 208
209#ifdef CONFIG_ZONE_DMA 209#ifdef CONFIG_ZONE_DMA
210 210
211unsigned long arm_dma_zone_size __read_mostly; 211phys_addr_t arm_dma_zone_size __read_mostly;
212EXPORT_SYMBOL(arm_dma_zone_size); 212EXPORT_SYMBOL(arm_dma_zone_size);
213 213
214/* 214/*
diff --git a/drivers/dma/amba-pl08x.c b/drivers/dma/amba-pl08x.c
index 06fe45c74de5..bff41d4848e5 100644
--- a/drivers/dma/amba-pl08x.c
+++ b/drivers/dma/amba-pl08x.c
@@ -133,6 +133,8 @@ struct pl08x_bus_data {
133 u8 buswidth; 133 u8 buswidth;
134}; 134};
135 135
136#define IS_BUS_ALIGNED(bus) IS_ALIGNED((bus)->addr, (bus)->buswidth)
137
136/** 138/**
137 * struct pl08x_phy_chan - holder for the physical channels 139 * struct pl08x_phy_chan - holder for the physical channels
138 * @id: physical index to this channel 140 * @id: physical index to this channel
@@ -845,10 +847,13 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
845 847
846 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl); 848 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl);
847 849
848 dev_vdbg(&pl08x->adev->dev, "src=0x%08x%s/%u dst=0x%08x%s/%u len=%zu\n", 850 dev_vdbg(&pl08x->adev->dev,
849 bd.srcbus.addr, cctl & PL080_CONTROL_SRC_INCR ? "+" : "", 851 "src=0x%08llx%s/%u dst=0x%08llx%s/%u len=%zu\n",
852 (u64)bd.srcbus.addr,
853 cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
850 bd.srcbus.buswidth, 854 bd.srcbus.buswidth,
851 bd.dstbus.addr, cctl & PL080_CONTROL_DST_INCR ? "+" : "", 855 (u64)bd.dstbus.addr,
856 cctl & PL080_CONTROL_DST_INCR ? "+" : "",
852 bd.dstbus.buswidth, 857 bd.dstbus.buswidth,
853 bd.remainder); 858 bd.remainder);
854 dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n", 859 dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
@@ -886,8 +891,8 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
886 return 0; 891 return 0;
887 } 892 }
888 893
889 if ((bd.srcbus.addr % bd.srcbus.buswidth) || 894 if (!IS_BUS_ALIGNED(&bd.srcbus) ||
890 (bd.dstbus.addr % bd.dstbus.buswidth)) { 895 !IS_BUS_ALIGNED(&bd.dstbus)) {
891 dev_err(&pl08x->adev->dev, 896 dev_err(&pl08x->adev->dev,
892 "%s src & dst address must be aligned to src" 897 "%s src & dst address must be aligned to src"
893 " & dst width if peripheral is flow controller", 898 " & dst width if peripheral is flow controller",
@@ -908,9 +913,9 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
908 */ 913 */
909 if (bd.remainder < mbus->buswidth) 914 if (bd.remainder < mbus->buswidth)
910 early_bytes = bd.remainder; 915 early_bytes = bd.remainder;
911 else if ((mbus->addr) % (mbus->buswidth)) { 916 else if (!IS_BUS_ALIGNED(mbus)) {
912 early_bytes = mbus->buswidth - (mbus->addr) % 917 early_bytes = mbus->buswidth -
913 (mbus->buswidth); 918 (mbus->addr & (mbus->buswidth - 1));
914 if ((bd.remainder - early_bytes) < mbus->buswidth) 919 if ((bd.remainder - early_bytes) < mbus->buswidth)
915 early_bytes = bd.remainder; 920 early_bytes = bd.remainder;
916 } 921 }
@@ -928,7 +933,7 @@ static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
928 * Master now aligned 933 * Master now aligned
929 * - if slave is not then we must set its width down 934 * - if slave is not then we must set its width down
930 */ 935 */
931 if (sbus->addr % sbus->buswidth) { 936 if (!IS_BUS_ALIGNED(sbus)) {
932 dev_dbg(&pl08x->adev->dev, 937 dev_dbg(&pl08x->adev->dev,
933 "%s set down bus width to one byte\n", 938 "%s set down bus width to one byte\n",
934 __func__); 939 __func__);
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 81e8cd49ae76..c60b9010b152 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_IRQCHIP) += irqchip.o
2 2
3obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o 3obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
4obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o 4obj-$(CONFIG_ARCH_EXYNOS) += exynos-combiner.o
5obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
5obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o 6obj-$(CONFIG_ARCH_MVEBU) += irq-armada-370-xp.o
6obj-$(CONFIG_ARCH_MXS) += irq-mxs.o 7obj-$(CONFIG_ARCH_MXS) += irq-mxs.o
7obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o 8obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
diff --git a/arch/arm/mach-mmp/irq.c b/drivers/irqchip/irq-mmp.c
index 3c71246cd994..2cb7cd0bc2f5 100644
--- a/arch/arm/mach-mmp/irq.c
+++ b/drivers/irqchip/irq-mmp.c
@@ -21,19 +21,20 @@
21#include <linux/of_address.h> 21#include <linux/of_address.h>
22#include <linux/of_irq.h> 22#include <linux/of_irq.h>
23 23
24#include <mach/irqs.h> 24#include <asm/exception.h>
25#include <asm/mach/irq.h>
25 26
26#ifdef CONFIG_CPU_MMP2 27#include "irqchip.h"
27#include <mach/pm-mmp2.h>
28#endif
29#ifdef CONFIG_CPU_PXA910
30#include <mach/pm-pxa910.h>
31#endif
32
33#include "common.h"
34 28
35#define MAX_ICU_NR 16 29#define MAX_ICU_NR 16
36 30
31#define PJ1_INT_SEL 0x10c
32#define PJ4_INT_SEL 0x104
33
34/* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */
35#define SEL_INT_PENDING (1 << 6)
36#define SEL_INT_NUM_MASK 0x3f
37
37struct icu_chip_data { 38struct icu_chip_data {
38 int nr_irqs; 39 int nr_irqs;
39 unsigned int virq_base; 40 unsigned int virq_base;
@@ -54,7 +55,7 @@ struct mmp_intc_conf {
54 unsigned int conf_mask; 55 unsigned int conf_mask;
55}; 56};
56 57
57void __iomem *mmp_icu_base; 58static void __iomem *mmp_icu_base;
58static struct icu_chip_data icu_data[MAX_ICU_NR]; 59static struct icu_chip_data icu_data[MAX_ICU_NR];
59static int max_icu_nr; 60static int max_icu_nr;
60 61
@@ -122,7 +123,7 @@ static void icu_unmask_irq(struct irq_data *d)
122 } 123 }
123} 124}
124 125
125static struct irq_chip icu_irq_chip = { 126struct irq_chip icu_irq_chip = {
126 .name = "icu_irq", 127 .name = "icu_irq",
127 .irq_mask = icu_mask_irq, 128 .irq_mask = icu_mask_irq,
128 .irq_mask_ack = icu_mask_ack_irq, 129 .irq_mask_ack = icu_mask_ack_irq,
@@ -193,6 +194,32 @@ static struct mmp_intc_conf mmp2_conf = {
193 .conf_mask = 0x7f, 194 .conf_mask = 0x7f,
194}; 195};
195 196
197static asmlinkage void __exception_irq_entry
198mmp_handle_irq(struct pt_regs *regs)
199{
200 int irq, hwirq;
201
202 hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL);
203 if (!(hwirq & SEL_INT_PENDING))
204 return;
205 hwirq &= SEL_INT_NUM_MASK;
206 irq = irq_find_mapping(icu_data[0].domain, hwirq);
207 handle_IRQ(irq, regs);
208}
209
210static asmlinkage void __exception_irq_entry
211mmp2_handle_irq(struct pt_regs *regs)
212{
213 int irq, hwirq;
214
215 hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL);
216 if (!(hwirq & SEL_INT_PENDING))
217 return;
218 hwirq &= SEL_INT_NUM_MASK;
219 irq = irq_find_mapping(icu_data[0].domain, hwirq);
220 handle_IRQ(irq, regs);
221}
222
196/* MMP (ARMv5) */ 223/* MMP (ARMv5) */
197void __init icu_init_irq(void) 224void __init icu_init_irq(void)
198{ 225{
@@ -214,15 +241,13 @@ void __init icu_init_irq(void)
214 set_irq_flags(irq, IRQF_VALID); 241 set_irq_flags(irq, IRQF_VALID);
215 } 242 }
216 irq_set_default_host(icu_data[0].domain); 243 irq_set_default_host(icu_data[0].domain);
217#ifdef CONFIG_CPU_PXA910 244 set_handle_irq(mmp_handle_irq);
218 icu_irq_chip.irq_set_wake = pxa910_set_wake;
219#endif
220} 245}
221 246
222/* MMP2 (ARMv7) */ 247/* MMP2 (ARMv7) */
223void __init mmp2_init_icu(void) 248void __init mmp2_init_icu(void)
224{ 249{
225 int irq; 250 int irq, end;
226 251
227 max_icu_nr = 8; 252 max_icu_nr = 8;
228 mmp_icu_base = ioremap(0xd4282000, 0x1000); 253 mmp_icu_base = ioremap(0xd4282000, 0x1000);
@@ -236,11 +261,12 @@ void __init mmp2_init_icu(void)
236 &icu_data[0]); 261 &icu_data[0]);
237 icu_data[1].reg_status = mmp_icu_base + 0x150; 262 icu_data[1].reg_status = mmp_icu_base + 0x150;
238 icu_data[1].reg_mask = mmp_icu_base + 0x168; 263 icu_data[1].reg_mask = mmp_icu_base + 0x168;
239 icu_data[1].clr_mfp_irq_base = IRQ_MMP2_PMIC_BASE; 264 icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base +
240 icu_data[1].clr_mfp_hwirq = IRQ_MMP2_PMIC - IRQ_MMP2_PMIC_BASE; 265 icu_data[0].nr_irqs;
266 icu_data[1].clr_mfp_hwirq = 1; /* offset to IRQ_MMP2_PMIC_BASE */
241 icu_data[1].nr_irqs = 2; 267 icu_data[1].nr_irqs = 2;
242 icu_data[1].cascade_irq = 4; 268 icu_data[1].cascade_irq = 4;
243 icu_data[1].virq_base = IRQ_MMP2_PMIC_BASE; 269 icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs;
244 icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs, 270 icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs,
245 icu_data[1].virq_base, 0, 271 icu_data[1].virq_base, 0,
246 &irq_domain_simple_ops, 272 &irq_domain_simple_ops,
@@ -249,7 +275,7 @@ void __init mmp2_init_icu(void)
249 icu_data[2].reg_mask = mmp_icu_base + 0x16c; 275 icu_data[2].reg_mask = mmp_icu_base + 0x16c;
250 icu_data[2].nr_irqs = 2; 276 icu_data[2].nr_irqs = 2;
251 icu_data[2].cascade_irq = 5; 277 icu_data[2].cascade_irq = 5;
252 icu_data[2].virq_base = IRQ_MMP2_RTC_BASE; 278 icu_data[2].virq_base = icu_data[1].virq_base + icu_data[1].nr_irqs;
253 icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs, 279 icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs,
254 icu_data[2].virq_base, 0, 280 icu_data[2].virq_base, 0,
255 &irq_domain_simple_ops, 281 &irq_domain_simple_ops,
@@ -258,7 +284,7 @@ void __init mmp2_init_icu(void)
258 icu_data[3].reg_mask = mmp_icu_base + 0x17c; 284 icu_data[3].reg_mask = mmp_icu_base + 0x17c;
259 icu_data[3].nr_irqs = 3; 285 icu_data[3].nr_irqs = 3;
260 icu_data[3].cascade_irq = 9; 286 icu_data[3].cascade_irq = 9;
261 icu_data[3].virq_base = IRQ_MMP2_KEYPAD_BASE; 287 icu_data[3].virq_base = icu_data[2].virq_base + icu_data[2].nr_irqs;
262 icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs, 288 icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs,
263 icu_data[3].virq_base, 0, 289 icu_data[3].virq_base, 0,
264 &irq_domain_simple_ops, 290 &irq_domain_simple_ops,
@@ -267,7 +293,7 @@ void __init mmp2_init_icu(void)
267 icu_data[4].reg_mask = mmp_icu_base + 0x170; 293 icu_data[4].reg_mask = mmp_icu_base + 0x170;
268 icu_data[4].nr_irqs = 5; 294 icu_data[4].nr_irqs = 5;
269 icu_data[4].cascade_irq = 17; 295 icu_data[4].cascade_irq = 17;
270 icu_data[4].virq_base = IRQ_MMP2_TWSI_BASE; 296 icu_data[4].virq_base = icu_data[3].virq_base + icu_data[3].nr_irqs;
271 icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs, 297 icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs,
272 icu_data[4].virq_base, 0, 298 icu_data[4].virq_base, 0,
273 &irq_domain_simple_ops, 299 &irq_domain_simple_ops,
@@ -276,7 +302,7 @@ void __init mmp2_init_icu(void)
276 icu_data[5].reg_mask = mmp_icu_base + 0x174; 302 icu_data[5].reg_mask = mmp_icu_base + 0x174;
277 icu_data[5].nr_irqs = 15; 303 icu_data[5].nr_irqs = 15;
278 icu_data[5].cascade_irq = 35; 304 icu_data[5].cascade_irq = 35;
279 icu_data[5].virq_base = IRQ_MMP2_MISC_BASE; 305 icu_data[5].virq_base = icu_data[4].virq_base + icu_data[4].nr_irqs;
280 icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs, 306 icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs,
281 icu_data[5].virq_base, 0, 307 icu_data[5].virq_base, 0,
282 &irq_domain_simple_ops, 308 &irq_domain_simple_ops,
@@ -285,7 +311,7 @@ void __init mmp2_init_icu(void)
285 icu_data[6].reg_mask = mmp_icu_base + 0x178; 311 icu_data[6].reg_mask = mmp_icu_base + 0x178;
286 icu_data[6].nr_irqs = 2; 312 icu_data[6].nr_irqs = 2;
287 icu_data[6].cascade_irq = 51; 313 icu_data[6].cascade_irq = 51;
288 icu_data[6].virq_base = IRQ_MMP2_MIPI_HSI1_BASE; 314 icu_data[6].virq_base = icu_data[5].virq_base + icu_data[5].nr_irqs;
289 icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs, 315 icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs,
290 icu_data[6].virq_base, 0, 316 icu_data[6].virq_base, 0,
291 &irq_domain_simple_ops, 317 &irq_domain_simple_ops,
@@ -294,170 +320,176 @@ void __init mmp2_init_icu(void)
294 icu_data[7].reg_mask = mmp_icu_base + 0x184; 320 icu_data[7].reg_mask = mmp_icu_base + 0x184;
295 icu_data[7].nr_irqs = 2; 321 icu_data[7].nr_irqs = 2;
296 icu_data[7].cascade_irq = 55; 322 icu_data[7].cascade_irq = 55;
297 icu_data[7].virq_base = IRQ_MMP2_MIPI_HSI0_BASE; 323 icu_data[7].virq_base = icu_data[6].virq_base + icu_data[6].nr_irqs;
298 icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs, 324 icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs,
299 icu_data[7].virq_base, 0, 325 icu_data[7].virq_base, 0,
300 &irq_domain_simple_ops, 326 &irq_domain_simple_ops,
301 &icu_data[7]); 327 &icu_data[7]);
302 for (irq = 0; irq < IRQ_MMP2_MUX_END; irq++) { 328 end = icu_data[7].virq_base + icu_data[7].nr_irqs;
329 for (irq = 0; irq < end; irq++) {
303 icu_mask_irq(irq_get_irq_data(irq)); 330 icu_mask_irq(irq_get_irq_data(irq));
304 switch (irq) { 331 if (irq == icu_data[1].cascade_irq ||
305 case IRQ_MMP2_PMIC_MUX: 332 irq == icu_data[2].cascade_irq ||
306 case IRQ_MMP2_RTC_MUX: 333 irq == icu_data[3].cascade_irq ||
307 case IRQ_MMP2_KEYPAD_MUX: 334 irq == icu_data[4].cascade_irq ||
308 case IRQ_MMP2_TWSI_MUX: 335 irq == icu_data[5].cascade_irq ||
309 case IRQ_MMP2_MISC_MUX: 336 irq == icu_data[6].cascade_irq ||
310 case IRQ_MMP2_MIPI_HSI1_MUX: 337 irq == icu_data[7].cascade_irq) {
311 case IRQ_MMP2_MIPI_HSI0_MUX:
312 irq_set_chip(irq, &icu_irq_chip); 338 irq_set_chip(irq, &icu_irq_chip);
313 irq_set_chained_handler(irq, icu_mux_irq_demux); 339 irq_set_chained_handler(irq, icu_mux_irq_demux);
314 break; 340 } else {
315 default:
316 irq_set_chip_and_handler(irq, &icu_irq_chip, 341 irq_set_chip_and_handler(irq, &icu_irq_chip,
317 handle_level_irq); 342 handle_level_irq);
318 break;
319 } 343 }
320 set_irq_flags(irq, IRQF_VALID); 344 set_irq_flags(irq, IRQF_VALID);
321 } 345 }
322 irq_set_default_host(icu_data[0].domain); 346 irq_set_default_host(icu_data[0].domain);
323#ifdef CONFIG_CPU_MMP2 347 set_handle_irq(mmp2_handle_irq);
324 icu_irq_chip.irq_set_wake = mmp2_set_wake;
325#endif
326} 348}
327 349
328#ifdef CONFIG_OF 350#ifdef CONFIG_OF
329static const struct of_device_id intc_ids[] __initconst = { 351static int __init mmp_init_bases(struct device_node *node)
330 { .compatible = "mrvl,mmp-intc", .data = &mmp_conf },
331 { .compatible = "mrvl,mmp2-intc", .data = &mmp2_conf },
332 {}
333};
334
335static const struct of_device_id mmp_mux_irq_match[] __initconst = {
336 { .compatible = "mrvl,mmp2-mux-intc" },
337 {}
338};
339
340int __init mmp2_mux_init(struct device_node *parent)
341{ 352{
342 struct device_node *node; 353 int ret, nr_irqs, irq, i = 0;
343 const struct of_device_id *of_id;
344 struct resource res;
345 int i, irq_base, ret, irq;
346 u32 nr_irqs, mfp_irq;
347 354
348 node = parent; 355 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs);
349 max_icu_nr = 1; 356 if (ret) {
350 for (i = 1; i < MAX_ICU_NR; i++) { 357 pr_err("Not found mrvl,intc-nr-irqs property\n");
351 node = of_find_matching_node(node, mmp_mux_irq_match); 358 return ret;
352 if (!node) 359 }
353 break; 360
354 of_id = of_match_node(&mmp_mux_irq_match[0], node); 361 mmp_icu_base = of_iomap(node, 0);
355 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", 362 if (!mmp_icu_base) {
356 &nr_irqs); 363 pr_err("Failed to get interrupt controller register\n");
357 if (ret) { 364 return -ENOMEM;
358 pr_err("Not found mrvl,intc-nr-irqs property\n"); 365 }
359 ret = -EINVAL;
360 goto err;
361 }
362 ret = of_address_to_resource(node, 0, &res);
363 if (ret < 0) {
364 pr_err("Not found reg property\n");
365 ret = -EINVAL;
366 goto err;
367 }
368 icu_data[i].reg_status = mmp_icu_base + res.start;
369 ret = of_address_to_resource(node, 1, &res);
370 if (ret < 0) {
371 pr_err("Not found reg property\n");
372 ret = -EINVAL;
373 goto err;
374 }
375 icu_data[i].reg_mask = mmp_icu_base + res.start;
376 icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
377 if (!icu_data[i].cascade_irq) {
378 ret = -EINVAL;
379 goto err;
380 }
381 366
382 irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0); 367 icu_data[0].virq_base = 0;
383 if (irq_base < 0) { 368 icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,
384 pr_err("Failed to allocate IRQ numbers for mux intc\n"); 369 &mmp_irq_domain_ops,
385 ret = irq_base; 370 &icu_data[0]);
371 for (irq = 0; irq < nr_irqs; irq++) {
372 ret = irq_create_mapping(icu_data[0].domain, irq);
373 if (!ret) {
374 pr_err("Failed to mapping hwirq\n");
386 goto err; 375 goto err;
387 } 376 }
388 if (!of_property_read_u32(node, "mrvl,clr-mfp-irq", 377 if (!irq)
389 &mfp_irq)) { 378 icu_data[0].virq_base = ret;
390 icu_data[i].clr_mfp_irq_base = irq_base;
391 icu_data[i].clr_mfp_hwirq = mfp_irq;
392 }
393 irq_set_chained_handler(icu_data[i].cascade_irq,
394 icu_mux_irq_demux);
395 icu_data[i].nr_irqs = nr_irqs;
396 icu_data[i].virq_base = irq_base;
397 icu_data[i].domain = irq_domain_add_legacy(node, nr_irqs,
398 irq_base, 0,
399 &mmp_irq_domain_ops,
400 &icu_data[i]);
401 for (irq = irq_base; irq < irq_base + nr_irqs; irq++)
402 icu_mask_irq(irq_get_irq_data(irq));
403 } 379 }
404 max_icu_nr = i; 380 icu_data[0].nr_irqs = nr_irqs;
405 return 0; 381 return 0;
406err: 382err:
407 of_node_put(node); 383 if (icu_data[0].virq_base) {
408 max_icu_nr = i; 384 for (i = 0; i < irq; i++)
409 return ret; 385 irq_dispose_mapping(icu_data[0].virq_base + i);
386 }
387 irq_domain_remove(icu_data[0].domain);
388 iounmap(mmp_icu_base);
389 return -EINVAL;
410} 390}
411 391
412void __init mmp_dt_irq_init(void) 392static int __init mmp_of_init(struct device_node *node,
393 struct device_node *parent)
413{ 394{
414 struct device_node *node; 395 int ret;
415 const struct of_device_id *of_id;
416 struct mmp_intc_conf *conf;
417 int nr_irqs, irq_base, ret, irq;
418
419 node = of_find_matching_node(NULL, intc_ids);
420 if (!node) {
421 pr_err("Failed to find interrupt controller in arch-mmp\n");
422 return;
423 }
424 of_id = of_match_node(intc_ids, node);
425 conf = of_id->data;
426 396
427 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs); 397 ret = mmp_init_bases(node);
398 if (ret < 0)
399 return ret;
400
401 icu_data[0].conf_enable = mmp_conf.conf_enable;
402 icu_data[0].conf_disable = mmp_conf.conf_disable;
403 icu_data[0].conf_mask = mmp_conf.conf_mask;
404 irq_set_default_host(icu_data[0].domain);
405 set_handle_irq(mmp_handle_irq);
406 max_icu_nr = 1;
407 return 0;
408}
409IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init);
410
411static int __init mmp2_of_init(struct device_node *node,
412 struct device_node *parent)
413{
414 int ret;
415
416 ret = mmp_init_bases(node);
417 if (ret < 0)
418 return ret;
419
420 icu_data[0].conf_enable = mmp2_conf.conf_enable;
421 icu_data[0].conf_disable = mmp2_conf.conf_disable;
422 icu_data[0].conf_mask = mmp2_conf.conf_mask;
423 irq_set_default_host(icu_data[0].domain);
424 set_handle_irq(mmp2_handle_irq);
425 max_icu_nr = 1;
426 return 0;
427}
428IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init);
429
430static int __init mmp2_mux_of_init(struct device_node *node,
431 struct device_node *parent)
432{
433 struct resource res;
434 int i, ret, irq, j = 0;
435 u32 nr_irqs, mfp_irq;
436
437 if (!parent)
438 return -ENODEV;
439
440 i = max_icu_nr;
441 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs",
442 &nr_irqs);
428 if (ret) { 443 if (ret) {
429 pr_err("Not found mrvl,intc-nr-irqs property\n"); 444 pr_err("Not found mrvl,intc-nr-irqs property\n");
430 return; 445 return -EINVAL;
431 } 446 }
432 447 ret = of_address_to_resource(node, 0, &res);
433 mmp_icu_base = of_iomap(node, 0); 448 if (ret < 0) {
434 if (!mmp_icu_base) { 449 pr_err("Not found reg property\n");
435 pr_err("Failed to get interrupt controller register\n"); 450 return -EINVAL;
436 return;
437 } 451 }
438 452 icu_data[i].reg_status = mmp_icu_base + res.start;
439 irq_base = irq_alloc_descs(-1, 0, nr_irqs - NR_IRQS_LEGACY, 0); 453 ret = of_address_to_resource(node, 1, &res);
440 if (irq_base < 0) { 454 if (ret < 0) {
441 pr_err("Failed to allocate IRQ numbers\n"); 455 pr_err("Not found reg property\n");
442 goto err; 456 return -EINVAL;
443 } else if (irq_base != NR_IRQS_LEGACY) {
444 pr_err("ICU's irqbase should be started from 0\n");
445 goto err;
446 } 457 }
447 icu_data[0].conf_enable = conf->conf_enable; 458 icu_data[i].reg_mask = mmp_icu_base + res.start;
448 icu_data[0].conf_disable = conf->conf_disable; 459 icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);
449 icu_data[0].conf_mask = conf->conf_mask; 460 if (!icu_data[i].cascade_irq)
450 icu_data[0].nr_irqs = nr_irqs; 461 return -EINVAL;
451 icu_data[0].virq_base = 0; 462
452 icu_data[0].domain = irq_domain_add_legacy(node, nr_irqs, 0, 0, 463 icu_data[i].virq_base = 0;
464 icu_data[i].domain = irq_domain_add_linear(node, nr_irqs,
453 &mmp_irq_domain_ops, 465 &mmp_irq_domain_ops,
454 &icu_data[0]); 466 &icu_data[i]);
455 irq_set_default_host(icu_data[0].domain); 467 for (irq = 0; irq < nr_irqs; irq++) {
456 for (irq = 0; irq < nr_irqs; irq++) 468 ret = irq_create_mapping(icu_data[i].domain, irq);
457 icu_mask_irq(irq_get_irq_data(irq)); 469 if (!ret) {
458 mmp2_mux_init(node); 470 pr_err("Failed to mapping hwirq\n");
459 return; 471 goto err;
472 }
473 if (!irq)
474 icu_data[i].virq_base = ret;
475 }
476 icu_data[i].nr_irqs = nr_irqs;
477 if (!of_property_read_u32(node, "mrvl,clr-mfp-irq",
478 &mfp_irq)) {
479 icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base;
480 icu_data[i].clr_mfp_hwirq = mfp_irq;
481 }
482 irq_set_chained_handler(icu_data[i].cascade_irq,
483 icu_mux_irq_demux);
484 max_icu_nr++;
485 return 0;
460err: 486err:
461 iounmap(mmp_icu_base); 487 if (icu_data[i].virq_base) {
488 for (j = 0; j < irq; j++)
489 irq_dispose_mapping(icu_data[i].virq_base + j);
490 }
491 irq_domain_remove(icu_data[i].domain);
492 return -EINVAL;
462} 493}
494IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init);
463#endif 495#endif
diff --git a/include/linux/irqchip/mmp.h b/include/linux/irqchip/mmp.h
new file mode 100644
index 000000000000..c78a8921185d
--- /dev/null
+++ b/include/linux/irqchip/mmp.h
@@ -0,0 +1,6 @@
1#ifndef __IRQCHIP_MMP_H
2#define __IRQCHIP_MMP_H
3
4extern struct irq_chip icu_irq_chip;
5
6#endif /* __IRQCHIP_MMP_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 10:22:41 -0500