diff options
author | sricharan <r.sricharan@ti.com> | 2011-09-07 07:55:16 -0400 |
---|---|---|
committer | Santosh Shilimkar <santosh.shilimkar@ti.com> | 2011-09-24 03:58:57 -0400 |
commit | 551a9fa9b1f01aa16f9007337b3cc12216c732fa (patch) | |
tree | 63e09c9d2ee478b4bb1b71f7cb4448c30cc18de9 | |
parent | 6616aac66d798f3f185d90d9057e47abd7d3c9b3 (diff) |
OMAP: Print Initiator name for l3 custom error.
The initiator id gets logged in the l3 target registers for custom error.
So print it to aid debugging.
Based on a internal patch by Devaraj Rangasamy <dev@ti.com>
Signed-off-by: sricharan <r.sricharan@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
-rw-r--r-- | arch/arm/mach-omap2/omap_l3_noc.c | 26 | ||||
-rw-r--r-- | arch/arm/mach-omap2/omap_l3_noc.h | 34 |
2 files changed, 50 insertions, 10 deletions
diff --git a/arch/arm/mach-omap2/omap_l3_noc.c b/arch/arm/mach-omap2/omap_l3_noc.c index 8f1835711676..07a3d3ede768 100644 --- a/arch/arm/mach-omap2/omap_l3_noc.c +++ b/arch/arm/mach-omap2/omap_l3_noc.c | |||
@@ -56,11 +56,11 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3) | |||
56 | { | 56 | { |
57 | 57 | ||
58 | struct omap4_l3 *l3 = _l3; | 58 | struct omap4_l3 *l3 = _l3; |
59 | int inttype, i; | 59 | int inttype, i, k; |
60 | int err_src = 0; | 60 | int err_src = 0; |
61 | u32 std_err_main, err_reg, clear; | 61 | u32 std_err_main, err_reg, clear, masterid; |
62 | void __iomem *base, *l3_targ_base; | 62 | void __iomem *base, *l3_targ_base; |
63 | char *source_name; | 63 | char *target_name, *master_name = "UN IDENTIFIED"; |
64 | 64 | ||
65 | /* Get the Type of interrupt */ | 65 | /* Get the Type of interrupt */ |
66 | inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; | 66 | inttype = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; |
@@ -83,13 +83,15 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3) | |||
83 | l3_targ_base = base + *(l3_targ[i] + err_src); | 83 | l3_targ_base = base + *(l3_targ[i] + err_src); |
84 | std_err_main = __raw_readl(l3_targ_base + | 84 | std_err_main = __raw_readl(l3_targ_base + |
85 | L3_TARG_STDERRLOG_MAIN); | 85 | L3_TARG_STDERRLOG_MAIN); |
86 | masterid = __raw_readl(l3_targ_base + | ||
87 | L3_TARG_STDERRLOG_MSTADDR); | ||
86 | 88 | ||
87 | switch (std_err_main & CUSTOM_ERROR) { | 89 | switch (std_err_main & CUSTOM_ERROR) { |
88 | case STANDARD_ERROR: | 90 | case STANDARD_ERROR: |
89 | source_name = | 91 | target_name = |
90 | l3_targ_inst_name[i][err_src]; | 92 | l3_targ_inst_name[i][err_src]; |
91 | WARN(true, "L3 standard error: SOURCE:%s at address 0x%x\n", | 93 | WARN(true, "L3 standard error: TARGET:%s at address 0x%x\n", |
92 | source_name, | 94 | target_name, |
93 | __raw_readl(l3_targ_base + | 95 | __raw_readl(l3_targ_base + |
94 | L3_TARG_STDERRLOG_SLVOFSLSB)); | 96 | L3_TARG_STDERRLOG_SLVOFSLSB)); |
95 | /* clear the std error log*/ | 97 | /* clear the std error log*/ |
@@ -99,11 +101,15 @@ static irqreturn_t l3_interrupt_handler(int irq, void *_l3) | |||
99 | break; | 101 | break; |
100 | 102 | ||
101 | case CUSTOM_ERROR: | 103 | case CUSTOM_ERROR: |
102 | source_name = | 104 | target_name = |
103 | l3_targ_inst_name[i][err_src]; | 105 | l3_targ_inst_name[i][err_src]; |
104 | 106 | for (k = 0; k < NUM_OF_L3_MASTERS; k++) { | |
105 | WARN(true, "L3 custom error: SOURCE:%s\n", | 107 | if (masterid == l3_masters[k].id) |
106 | source_name); | 108 | master_name = |
109 | l3_masters[k].name; | ||
110 | } | ||
111 | WARN(true, "L3 custom error: MASTER:%s TARGET:%s\n", | ||
112 | master_name, target_name); | ||
107 | /* clear the std error log*/ | 113 | /* clear the std error log*/ |
108 | clear = std_err_main | CLEAR_STDERR_LOG; | 114 | clear = std_err_main | CLEAR_STDERR_LOG; |
109 | writel(clear, l3_targ_base + | 115 | writel(clear, l3_targ_base + |
diff --git a/arch/arm/mach-omap2/omap_l3_noc.h b/arch/arm/mach-omap2/omap_l3_noc.h index 74c16434f2bc..90b50984cd2e 100644 --- a/arch/arm/mach-omap2/omap_l3_noc.h +++ b/arch/arm/mach-omap2/omap_l3_noc.h | |||
@@ -34,8 +34,11 @@ | |||
34 | /* L3 TARG register offsets */ | 34 | /* L3 TARG register offsets */ |
35 | #define L3_TARG_STDERRLOG_MAIN 0x48 | 35 | #define L3_TARG_STDERRLOG_MAIN 0x48 |
36 | #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c | 36 | #define L3_TARG_STDERRLOG_SLVOFSLSB 0x5c |
37 | #define L3_TARG_STDERRLOG_MSTADDR 0x68 | ||
37 | #define L3_FLAGMUX_REGERR0 0xc | 38 | #define L3_FLAGMUX_REGERR0 0xc |
38 | 39 | ||
40 | #define NUM_OF_L3_MASTERS (sizeof(l3_masters)/sizeof(l3_masters[0])) | ||
41 | |||
39 | static u32 l3_flagmux[L3_MODULES] = { | 42 | static u32 l3_flagmux[L3_MODULES] = { |
40 | 0x500, | 43 | 0x500, |
41 | 0x1000, | 44 | 0x1000, |
@@ -76,6 +79,37 @@ static u32 l3_targ_inst_clk3[] = { | |||
76 | 0x0100 /* EMUSS */ | 79 | 0x0100 /* EMUSS */ |
77 | }; | 80 | }; |
78 | 81 | ||
82 | static struct l3_masters_data { | ||
83 | u32 id; | ||
84 | char name[10]; | ||
85 | } l3_masters[] = { | ||
86 | { 0x0 , "MPU"}, | ||
87 | { 0x10, "CS_ADP"}, | ||
88 | { 0x14, "xxx"}, | ||
89 | { 0x20, "DSP"}, | ||
90 | { 0x30, "IVAHD"}, | ||
91 | { 0x40, "ISS"}, | ||
92 | { 0x44, "DucatiM3"}, | ||
93 | { 0x48, "FaceDetect"}, | ||
94 | { 0x50, "SDMA_Rd"}, | ||
95 | { 0x54, "SDMA_Wr"}, | ||
96 | { 0x58, "xxx"}, | ||
97 | { 0x5C, "xxx"}, | ||
98 | { 0x60, "SGX"}, | ||
99 | { 0x70, "DSS"}, | ||
100 | { 0x80, "C2C"}, | ||
101 | { 0x88, "xxx"}, | ||
102 | { 0x8C, "xxx"}, | ||
103 | { 0x90, "HSI"}, | ||
104 | { 0xA0, "MMC1"}, | ||
105 | { 0xA4, "MMC2"}, | ||
106 | { 0xA8, "MMC6"}, | ||
107 | { 0xB0, "UNIPRO1"}, | ||
108 | { 0xC0, "USBHOSTHS"}, | ||
109 | { 0xC4, "USBOTGHS"}, | ||
110 | { 0xC8, "USBHOSTFS"} | ||
111 | }; | ||
112 | |||
79 | static char *l3_targ_inst_name[L3_MODULES][18] = { | 113 | static char *l3_targ_inst_name[L3_MODULES][18] = { |
80 | { | 114 | { |
81 | "DMM1", | 115 | "DMM1", |