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authorKirill A. Shutemov <kirill.shutemov@linux.intel.com>2015-02-10 17:10:58 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2015-02-10 17:30:33 -0500
commit3824e3cf7e865b2ff0b71de23b16e332fe6a853a (patch)
treee26956b75d5956822852f8fa0a6053052f8ab9c0
parent3ee802ead2de2346dd110e233d14602b2de26b3c (diff)
openrisc: drop _PAGE_FILE and pte_file()-related helpers
We've replaced remap_file_pages(2) implementation with emulation. Nobody creates non-linear mapping anymore. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: Jonas Bonn <jonas@southpole.se> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
-rw-r--r--arch/openrisc/include/asm/pgtable.h8
-rw-r--r--arch/openrisc/kernel/head.S5
2 files changed, 0 insertions, 13 deletions
diff --git a/arch/openrisc/include/asm/pgtable.h b/arch/openrisc/include/asm/pgtable.h
index 37bf6a3ef8f4..18994ccb1185 100644
--- a/arch/openrisc/include/asm/pgtable.h
+++ b/arch/openrisc/include/asm/pgtable.h
@@ -125,7 +125,6 @@ extern void paging_init(void);
125#define _PAGE_CC 0x001 /* software: pte contains a translation */ 125#define _PAGE_CC 0x001 /* software: pte contains a translation */
126#define _PAGE_CI 0x002 /* cache inhibit */ 126#define _PAGE_CI 0x002 /* cache inhibit */
127#define _PAGE_WBC 0x004 /* write back cache */ 127#define _PAGE_WBC 0x004 /* write back cache */
128#define _PAGE_FILE 0x004 /* set: pagecache, unset: swap (when !PRESENT) */
129#define _PAGE_WOM 0x008 /* weakly ordered memory */ 128#define _PAGE_WOM 0x008 /* weakly ordered memory */
130 129
131#define _PAGE_A 0x010 /* accessed */ 130#define _PAGE_A 0x010 /* accessed */
@@ -240,7 +239,6 @@ static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
240static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; } 239static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
241static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 240static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
242static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 241static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
243static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; }
244static inline int pte_special(pte_t pte) { return 0; } 242static inline int pte_special(pte_t pte) { return 0; }
245static inline pte_t pte_mkspecial(pte_t pte) { return pte; } 243static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
246 244
@@ -438,12 +436,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
438#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 436#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
439#define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 437#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
440 438
441/* Encode and decode a nonlinear file mapping entry */
442
443#define PTE_FILE_MAX_BITS 26
444#define pte_to_pgoff(x) (pte_val(x) >> 6)
445#define pgoff_to_pte(x) __pte(((x) << 6) | _PAGE_FILE)
446
447#define kern_addr_valid(addr) (1) 439#define kern_addr_valid(addr) (1)
448 440
449#include <asm-generic/pgtable.h> 441#include <asm-generic/pgtable.h>
diff --git a/arch/openrisc/kernel/head.S b/arch/openrisc/kernel/head.S
index 1d3c9c28ac25..f14793306b03 100644
--- a/arch/openrisc/kernel/head.S
+++ b/arch/openrisc/kernel/head.S
@@ -754,11 +754,6 @@ _dc_enable:
754 754
755/* ===============================================[ page table masks ]=== */ 755/* ===============================================[ page table masks ]=== */
756 756
757/* bit 4 is used in hardware as write back cache bit. we never use this bit
758 * explicitly, so we can reuse it as _PAGE_FILE bit and mask it out when
759 * writing into hardware pte's
760 */
761
762#define DTLB_UP_CONVERT_MASK 0x3fa 757#define DTLB_UP_CONVERT_MASK 0x3fa
763#define ITLB_UP_CONVERT_MASK 0x3a 758#define ITLB_UP_CONVERT_MASK 0x3a
764 759