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authorGeert Uytterhoeven <geert+renesas@linux-m68k.org>2014-01-12 05:27:43 -0500
committerMark Brown <broonie@linaro.org>2014-01-13 12:24:04 -0500
commit348e5153bcf6c6a0a735eeb6f65e1aba8ffe2780 (patch)
treea61802a8d43b1b2654061d3fafb3a546a168f028
parentfbe5072bbeac5362edc8c49435b76e6df75a9d95 (diff)
spi: rspi: Add support for specifying CPHA/CPOL
Add support for specifying the SPI clock phase and polarity, based on the SDK reference code. Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mark Brown <broonie@linaro.org>
-rw-r--r--drivers/spi/spi-rspi.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/drivers/spi/spi-rspi.c b/drivers/spi/spi-rspi.c
index 4a2c7592b5eb..c3227fb44b03 100644
--- a/drivers/spi/spi-rspi.c
+++ b/drivers/spi/spi-rspi.c
@@ -187,6 +187,7 @@ struct rspi_data {
187 spinlock_t lock; 187 spinlock_t lock;
188 struct clk *clk; 188 struct clk *clk;
189 u8 spsr; 189 u8 spsr;
190 u16 spcmd;
190 const struct spi_ops *ops; 191 const struct spi_ops *ops;
191 192
192 /* for dmaengine */ 193 /* for dmaengine */
@@ -261,7 +262,7 @@ static int rspi_set_config_register(const struct rspi_data *rspi,
261 rspi_write8(rspi, 0x00, RSPI_SPCR2); 262 rspi_write8(rspi, 0x00, RSPI_SPCR2);
262 263
263 /* Sets SPCMD */ 264 /* Sets SPCMD */
264 rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | SPCMD_SSLKP, 265 rspi_write16(rspi, SPCMD_SPB_8_TO_16(access_size) | rspi->spcmd,
265 RSPI_SPCMD0); 266 RSPI_SPCMD0);
266 267
267 /* Sets RSPI mode */ 268 /* Sets RSPI mode */
@@ -302,7 +303,7 @@ static int qspi_set_config_register(const struct rspi_data *rspi,
302 else if (access_size == 32) 303 else if (access_size == 32)
303 spcmd = SPCMD_SPB_32BIT; 304 spcmd = SPCMD_SPB_32BIT;
304 305
305 spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SSLKP | SPCMD_SPNDEN; 306 spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | rspi->spcmd | SPCMD_SPNDEN;
306 307
307 /* Resets transfer data length */ 308 /* Resets transfer data length */
308 rspi_write32(rspi, 0, QSPI_SPBMUL0); 309 rspi_write32(rspi, 0, QSPI_SPBMUL0);
@@ -805,6 +806,12 @@ static int rspi_setup(struct spi_device *spi)
805 spi->bits_per_word = 8; 806 spi->bits_per_word = 8;
806 rspi->max_speed_hz = spi->max_speed_hz; 807 rspi->max_speed_hz = spi->max_speed_hz;
807 808
809 rspi->spcmd = SPCMD_SSLKP;
810 if (spi->mode & SPI_CPOL)
811 rspi->spcmd |= SPCMD_CPOL;
812 if (spi->mode & SPI_CPHA)
813 rspi->spcmd |= SPCMD_CPHA;
814
808 set_config_register(rspi, 8); 815 set_config_register(rspi, 8);
809 816
810 return 0; 817 return 0;
@@ -996,6 +1003,7 @@ static int rspi_probe(struct platform_device *pdev)
996 master->setup = rspi_setup; 1003 master->setup = rspi_setup;
997 master->transfer = rspi_transfer; 1004 master->transfer = rspi_transfer;
998 master->cleanup = rspi_cleanup; 1005 master->cleanup = rspi_cleanup;
1006 master->mode_bits = SPI_CPHA | SPI_CPOL;
999 1007
1000 ret = request_irq(irq, rspi_irq, 0, dev_name(&pdev->dev), rspi); 1008 ret = request_irq(irq, rspi_irq, 0, dev_name(&pdev->dev), rspi);
1001 if (ret < 0) { 1009 if (ret < 0) {