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authorPaul Mundt <lethal@linux-sh.org>2011-06-15 05:03:58 -0400
committerPaul Mundt <lethal@linux-sh.org>2011-06-15 05:03:58 -0400
commit1f83812d61de8c09ad6ab6be29e0ebd0817d16f1 (patch)
tree32cc463e07a5efd7ec4702df003780664f543d5c
parent201fbceb258650157fcc4fd746abcdd3a571eada (diff)
parent4b8c59a3d83e9cf2b65b16999a0c704fc72de056 (diff)
Merge branch 'common/serial-rework' into sh-latest
Diffstat
-rw-r--r--arch/sh/Makefile1
-rw-r--r--arch/sh/include/cpu-sh3/cpu/serial.h10
-rw-r--r--arch/sh/include/cpu-sh4a/cpu/serial.h7
-rw-r--r--arch/sh/kernel/cpu/sh3/Makefile18
-rw-r--r--arch/sh/kernel/cpu/sh3/serial-sh770x.c33
-rw-r--r--arch/sh/kernel/cpu/sh3/serial-sh7710.c20
-rw-r--r--arch/sh/kernel/cpu/sh3/serial-sh7720.c36
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7705.c5
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh770x.c9
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh7720.c5
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c4
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c4
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile2
-rw-r--r--arch/sh/kernel/cpu/sh4a/serial-sh7722.c23
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7366.c1
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7722.c6
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c9
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c9
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c3
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c3
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c8
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c8
-rw-r--r--drivers/tty/serial/Kconfig2
-rw-r--r--drivers/tty/serial/sh-sci.c564
-rw-r--r--drivers/tty/serial/sh-sci.h434
-rw-r--r--include/linux/serial_sci.h68
26 files changed, 625 insertions, 667 deletions
diff --git a/arch/sh/Makefile b/arch/sh/Makefile
index e3d8170ad00b..99385d0b3f3b 100644
--- a/arch/sh/Makefile
+++ b/arch/sh/Makefile
@@ -173,6 +173,7 @@ core-$(CONFIG_HD6446X_SERIES) += arch/sh/cchips/hd6446x/
173cpuincdir-$(CONFIG_CPU_SH2A) += cpu-sh2a 173cpuincdir-$(CONFIG_CPU_SH2A) += cpu-sh2a
174cpuincdir-$(CONFIG_CPU_SH2) += cpu-sh2 174cpuincdir-$(CONFIG_CPU_SH2) += cpu-sh2
175cpuincdir-$(CONFIG_CPU_SH3) += cpu-sh3 175cpuincdir-$(CONFIG_CPU_SH3) += cpu-sh3
176cpuincdir-$(CONFIG_CPU_SH4A) += cpu-sh4a
176cpuincdir-$(CONFIG_CPU_SH4) += cpu-sh4 177cpuincdir-$(CONFIG_CPU_SH4) += cpu-sh4
177cpuincdir-$(CONFIG_CPU_SH5) += cpu-sh5 178cpuincdir-$(CONFIG_CPU_SH5) += cpu-sh5
178cpuincdir-y += cpu-common # Must be last 179cpuincdir-y += cpu-common # Must be last
diff --git a/arch/sh/include/cpu-sh3/cpu/serial.h b/arch/sh/include/cpu-sh3/cpu/serial.h
new file mode 100644
index 000000000000..7766329bc103
--- /dev/null
+++ b/arch/sh/include/cpu-sh3/cpu/serial.h
@@ -0,0 +1,10 @@
1#ifndef __CPU_SH3_SERIAL_H
2#define __CPU_SH3_SERIAL_H
3
4#include <linux/serial_sci.h>
5
6extern struct plat_sci_port_ops sh770x_sci_port_ops;
7extern struct plat_sci_port_ops sh7710_sci_port_ops;
8extern struct plat_sci_port_ops sh7720_sci_port_ops;
9
10#endif /* __CPU_SH3_SERIAL_H */
diff --git a/arch/sh/include/cpu-sh4a/cpu/serial.h b/arch/sh/include/cpu-sh4a/cpu/serial.h
new file mode 100644
index 000000000000..ff1bc275d210
--- /dev/null
+++ b/arch/sh/include/cpu-sh4a/cpu/serial.h
@@ -0,0 +1,7 @@
1#ifndef __CPU_SH4A_SERIAL_H
2#define __CPU_SH4A_SERIAL_H
3
4/* arch/sh/kernel/cpu/sh4a/serial-sh7722.c */
5extern struct plat_sci_port_ops sh7722_sci_port_ops;
6
7#endif /* __CPU_SH4A_SERIAL_H */
diff --git a/arch/sh/kernel/cpu/sh3/Makefile b/arch/sh/kernel/cpu/sh3/Makefile
index ecab274141a8..6f13f33a35ff 100644
--- a/arch/sh/kernel/cpu/sh3/Makefile
+++ b/arch/sh/kernel/cpu/sh3/Makefile
@@ -7,15 +7,15 @@ obj-y := ex.o probe.o entry.o setup-sh3.o
7obj-$(CONFIG_HIBERNATION) += swsusp.o 7obj-$(CONFIG_HIBERNATION) += swsusp.o
8 8
9# CPU subtype setup 9# CPU subtype setup
10obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7705) += setup-sh7705.o serial-sh770x.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7706) += setup-sh770x.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7706) += setup-sh770x.o serial-sh770x.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7707) += setup-sh770x.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7707) += setup-sh770x.o serial-sh770x.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7708) += setup-sh770x.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7708) += setup-sh770x.o serial-sh770x.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setup-sh770x.o 14obj-$(CONFIG_CPU_SUBTYPE_SH7709) += setup-sh770x.o serial-sh770x.o
15obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o serial-sh7710.o
16obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o 16obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o serial-sh7710.o
17obj-$(CONFIG_CPU_SUBTYPE_SH7720) += setup-sh7720.o 17obj-$(CONFIG_CPU_SUBTYPE_SH7720) += setup-sh7720.o serial-sh7720.o
18obj-$(CONFIG_CPU_SUBTYPE_SH7721) += setup-sh7720.o 18obj-$(CONFIG_CPU_SUBTYPE_SH7721) += setup-sh7720.o serial-sh7720.o
19 19
20# Primary on-chip clocks (common) 20# Primary on-chip clocks (common)
21clock-$(CONFIG_CPU_SH3) := clock-sh3.o 21clock-$(CONFIG_CPU_SH3) := clock-sh3.o
diff --git a/arch/sh/kernel/cpu/sh3/serial-sh770x.c b/arch/sh/kernel/cpu/sh3/serial-sh770x.c
new file mode 100644
index 000000000000..4f7242c676b3
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/serial-sh770x.c
@@ -0,0 +1,33 @@
1#include <linux/serial_sci.h>
2#include <linux/serial_core.h>
3#include <linux/io.h>
4#include <cpu/serial.h>
5
6#define SCPCR 0xA4000116
7#define SCPDR 0xA4000136
8
9static void sh770x_sci_init_pins(struct uart_port *port, unsigned int cflag)
10{
11 unsigned short data;
12
13 /* We need to set SCPCR to enable RTS/CTS */
14 data = __raw_readw(SCPCR);
15 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
16 __raw_writew(data & 0x0fcf, SCPCR);
17
18 if (!(cflag & CRTSCTS)) {
19 /* We need to set SCPCR to enable RTS/CTS */
20 data = __raw_readw(SCPCR);
21 /* Clear out SCP7MD1,0, SCP4MD1,0,
22 Set SCP6MD1,0 = {01} (output) */
23 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
24
25 data = __raw_readb(SCPDR);
26 /* Set /RTS2 (bit6) = 0 */
27 __raw_writeb(data & 0xbf, SCPDR);
28 }
29}
30
31struct plat_sci_port_ops sh770x_sci_port_ops = {
32 .init_pins = sh770x_sci_init_pins,
33};
diff --git a/arch/sh/kernel/cpu/sh3/serial-sh7710.c b/arch/sh/kernel/cpu/sh3/serial-sh7710.c
new file mode 100644
index 000000000000..42190ef6aebf
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/serial-sh7710.c
@@ -0,0 +1,20 @@
1#include <linux/serial_sci.h>
2#include <linux/serial_core.h>
3#include <linux/io.h>
4#include <cpu/serial.h>
5
6#define PACR 0xa4050100
7#define PBCR 0xa4050102
8
9static void sh7710_sci_init_pins(struct uart_port *port, unsigned int cflag)
10{
11 if (port->mapbase == 0xA4400000) {
12 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
13 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
14 } else if (port->mapbase == 0xA4410000)
15 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
16}
17
18struct plat_sci_port_ops sh7710_sci_port_ops = {
19 .init_pins = sh7710_sci_init_pins,
20};
diff --git a/arch/sh/kernel/cpu/sh3/serial-sh7720.c b/arch/sh/kernel/cpu/sh3/serial-sh7720.c
new file mode 100644
index 000000000000..8234e1e7abd9
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh3/serial-sh7720.c
@@ -0,0 +1,36 @@
1#include <linux/serial_sci.h>
2#include <linux/serial_core.h>
3#include <linux/io.h>
4#include <cpu/serial.h>
5
6static void sh7720_sci_init_pins(struct uart_port *port, unsigned int cflag)
7{
8 unsigned short data;
9
10 if (cflag & CRTSCTS) {
11 /* enable RTS/CTS */
12 if (port->mapbase == 0xa4430000) { /* SCIF0 */
13 /* Clear PTCR bit 9-2; enable all scif pins but sck */
14 data = __raw_readw(PORT_PTCR);
15 __raw_writew((data & 0xfc03), PORT_PTCR);
16 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
17 /* Clear PVCR bit 9-2 */
18 data = __raw_readw(PORT_PVCR);
19 __raw_writew((data & 0xfc03), PORT_PVCR);
20 }
21 } else {
22 if (port->mapbase == 0xa4430000) { /* SCIF0 */
23 /* Clear PTCR bit 5-2; enable only tx and rx */
24 data = __raw_readw(PORT_PTCR);
25 __raw_writew((data & 0xffc3), PORT_PTCR);
26 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
27 /* Clear PVCR bit 5-2 */
28 data = __raw_readw(PORT_PVCR);
29 __raw_writew((data & 0xffc3), PORT_PVCR);
30 }
31 }
32}
33
34struct plat_sci_port_ops sh7720_sci_port_ops = {
35 .init_pins = sh7720_sci_init_pins,
36};
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7705.c b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
index cd2e702feb7e..2309618c015d 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7705.c
@@ -15,6 +15,7 @@
15#include <linux/serial_sci.h> 15#include <linux/serial_sci.h>
16#include <linux/sh_timer.h> 16#include <linux/sh_timer.h>
17#include <asm/rtc.h> 17#include <asm/rtc.h>
18#include <cpu/serial.h>
18 19
19enum { 20enum {
20 UNUSED = 0, 21 UNUSED = 0,
@@ -75,6 +76,8 @@ static struct plat_sci_port scif0_platform_data = {
75 .scbrr_algo_id = SCBRR_ALGO_4, 76 .scbrr_algo_id = SCBRR_ALGO_4,
76 .type = PORT_SCIF, 77 .type = PORT_SCIF,
77 .irqs = { 56, 56, 56 }, 78 .irqs = { 56, 56, 56 },
79 .ops = &sh770x_sci_port_ops,
80 .regtype = SCIx_SH7705_SCIF_REGTYPE,
78}; 81};
79 82
80static struct platform_device scif0_device = { 83static struct platform_device scif0_device = {
@@ -92,6 +95,8 @@ static struct plat_sci_port scif1_platform_data = {
92 .scbrr_algo_id = SCBRR_ALGO_4, 95 .scbrr_algo_id = SCBRR_ALGO_4,
93 .type = PORT_SCIF, 96 .type = PORT_SCIF,
94 .irqs = { 52, 52, 52 }, 97 .irqs = { 52, 52, 52 },
98 .ops = &sh770x_sci_port_ops,
99 .regtype = SCIx_SH7705_SCIF_REGTYPE,
95}; 100};
96 101
97static struct platform_device scif1_device = { 102static struct platform_device scif1_device = {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh770x.c b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
index 4551ad647c2c..3f3d5fe5892d 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh770x.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh770x.c
@@ -19,6 +19,7 @@
19#include <linux/serial.h> 19#include <linux/serial.h>
20#include <linux/serial_sci.h> 20#include <linux/serial_sci.h>
21#include <linux/sh_timer.h> 21#include <linux/sh_timer.h>
22#include <cpu/serial.h>
22 23
23enum { 24enum {
24 UNUSED = 0, 25 UNUSED = 0,
@@ -108,11 +109,14 @@ static struct platform_device rtc_device = {
108 109
109static struct plat_sci_port scif0_platform_data = { 110static struct plat_sci_port scif0_platform_data = {
110 .mapbase = 0xfffffe80, 111 .mapbase = 0xfffffe80,
112 .port_reg = 0xa4000136,
111 .flags = UPF_BOOT_AUTOCONF, 113 .flags = UPF_BOOT_AUTOCONF,
112 .scscr = SCSCR_TE | SCSCR_RE, 114 .scscr = SCSCR_TE | SCSCR_RE,
113 .scbrr_algo_id = SCBRR_ALGO_2, 115 .scbrr_algo_id = SCBRR_ALGO_2,
114 .type = PORT_SCI, 116 .type = PORT_SCI,
115 .irqs = { 23, 23, 23, 0 }, 117 .irqs = { 23, 23, 23, 0 },
118 .ops = &sh770x_sci_port_ops,
119 .regshift = 1,
116}; 120};
117 121
118static struct platform_device scif0_device = { 122static struct platform_device scif0_device = {
@@ -132,6 +136,8 @@ static struct plat_sci_port scif1_platform_data = {
132 .scbrr_algo_id = SCBRR_ALGO_2, 136 .scbrr_algo_id = SCBRR_ALGO_2,
133 .type = PORT_SCIF, 137 .type = PORT_SCIF,
134 .irqs = { 56, 56, 56, 56 }, 138 .irqs = { 56, 56, 56, 56 },
139 .ops = &sh770x_sci_port_ops,
140 .regtype = SCIx_SH3_SCIF_REGTYPE,
135}; 141};
136 142
137static struct platform_device scif1_device = { 143static struct platform_device scif1_device = {
@@ -146,11 +152,14 @@ static struct platform_device scif1_device = {
146 defined(CONFIG_CPU_SUBTYPE_SH7709) 152 defined(CONFIG_CPU_SUBTYPE_SH7709)
147static struct plat_sci_port scif2_platform_data = { 153static struct plat_sci_port scif2_platform_data = {
148 .mapbase = 0xa4000140, 154 .mapbase = 0xa4000140,
155 .port_reg = SCIx_NOT_SUPPORTED,
149 .flags = UPF_BOOT_AUTOCONF, 156 .flags = UPF_BOOT_AUTOCONF,
150 .scscr = SCSCR_TE | SCSCR_RE, 157 .scscr = SCSCR_TE | SCSCR_RE,
151 .scbrr_algo_id = SCBRR_ALGO_2, 158 .scbrr_algo_id = SCBRR_ALGO_2,
152 .type = PORT_IRDA, 159 .type = PORT_IRDA,
153 .irqs = { 52, 52, 52, 52 }, 160 .irqs = { 52, 52, 52, 52 },
161 .ops = &sh770x_sci_port_ops,
162 .regshift = 1,
154}; 163};
155 164
156static struct platform_device scif2_device = { 165static struct platform_device scif2_device = {
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh7720.c b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
index 365b94a6fcb7..94920345c14d 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh7720.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh7720.c
@@ -20,6 +20,7 @@
20#include <linux/serial_sci.h> 20#include <linux/serial_sci.h>
21#include <linux/sh_timer.h> 21#include <linux/sh_timer.h>
22#include <asm/rtc.h> 22#include <asm/rtc.h>
23#include <cpu/serial.h>
23 24
24static struct resource rtc_resources[] = { 25static struct resource rtc_resources[] = {
25 [0] = { 26 [0] = {
@@ -55,6 +56,8 @@ static struct plat_sci_port scif0_platform_data = {
55 .scbrr_algo_id = SCBRR_ALGO_4, 56 .scbrr_algo_id = SCBRR_ALGO_4,
56 .type = PORT_SCIF, 57 .type = PORT_SCIF,
57 .irqs = { 80, 80, 80, 80 }, 58 .irqs = { 80, 80, 80, 80 },
59 .ops = &sh7720_sci_port_ops,
60 .regtype = SCIx_SH7705_SCIF_REGTYPE,
58}; 61};
59 62
60static struct platform_device scif0_device = { 63static struct platform_device scif0_device = {
@@ -72,6 +75,8 @@ static struct plat_sci_port scif1_platform_data = {
72 .scbrr_algo_id = SCBRR_ALGO_4, 75 .scbrr_algo_id = SCBRR_ALGO_4,
73 .type = PORT_SCIF, 76 .type = PORT_SCIF,
74 .irqs = { 81, 81, 81, 81 }, 77 .irqs = { 81, 81, 81, 81 },
78 .ops = &sh7720_sci_port_ops,
79 .regtype = SCIx_SH7705_SCIF_REGTYPE,
75}; 80};
76 81
77static struct platform_device scif1_device = { 82static struct platform_device scif1_device = {
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index e53b4b38bd11..c10db5b96e59 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * SH7750/SH7751 Setup 2 * SH7091/SH7750/SH7750S/SH7750R/SH7751/SH7751R Setup
3 * 3 *
4 * Copyright (C) 2006 Paul Mundt 4 * Copyright (C) 2006 Paul Mundt
5 * Copyright (C) 2006 Jamie Lenehan 5 * Copyright (C) 2006 Jamie Lenehan
@@ -38,11 +38,13 @@ static struct platform_device rtc_device = {
38 38
39static struct plat_sci_port sci_platform_data = { 39static struct plat_sci_port sci_platform_data = {
40 .mapbase = 0xffe00000, 40 .mapbase = 0xffe00000,
41 .port_reg = 0xffe0001C
41 .flags = UPF_BOOT_AUTOCONF, 42 .flags = UPF_BOOT_AUTOCONF,
42 .scscr = SCSCR_TE | SCSCR_RE, 43 .scscr = SCSCR_TE | SCSCR_RE,
43 .scbrr_algo_id = SCBRR_ALGO_2, 44 .scbrr_algo_id = SCBRR_ALGO_2,
44 .type = PORT_SCI, 45 .type = PORT_SCI,
45 .irqs = { 23, 23, 23, 0 }, 46 .irqs = { 23, 23, 23, 0 },
47 .regshift = 2,
46}; 48};
47 49
48static struct platform_device sci_device = { 50static struct platform_device sci_device = {
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 78bbf232e391..c0b4c774700e 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -133,6 +133,7 @@ static struct plat_sci_port scif0_platform_data = {
133 .scbrr_algo_id = SCBRR_ALGO_2, 133 .scbrr_algo_id = SCBRR_ALGO_2,
134 .type = PORT_SCIF, 134 .type = PORT_SCIF,
135 .irqs = { 52, 53, 55, 54 }, 135 .irqs = { 52, 53, 55, 54 },
136 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
136}; 137};
137 138
138static struct platform_device scif0_device = { 139static struct platform_device scif0_device = {
@@ -150,6 +151,7 @@ static struct plat_sci_port scif1_platform_data = {
150 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 151 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
151 .scbrr_algo_id = SCBRR_ALGO_2, 152 .scbrr_algo_id = SCBRR_ALGO_2,
152 .irqs = { 72, 73, 75, 74 }, 153 .irqs = { 72, 73, 75, 74 },
154 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
153}; 155};
154 156
155static struct platform_device scif1_device = { 157static struct platform_device scif1_device = {
@@ -167,6 +169,7 @@ static struct plat_sci_port scif2_platform_data = {
167 .scbrr_algo_id = SCBRR_ALGO_2, 169 .scbrr_algo_id = SCBRR_ALGO_2,
168 .type = PORT_SCIF, 170 .type = PORT_SCIF,
169 .irqs = { 76, 77, 79, 78 }, 171 .irqs = { 76, 77, 79, 78 },
172 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
170}; 173};
171 174
172static struct platform_device scif2_device = { 175static struct platform_device scif2_device = {
@@ -184,6 +187,7 @@ static struct plat_sci_port scif3_platform_data = {
184 .scbrr_algo_id = SCBRR_ALGO_2, 187 .scbrr_algo_id = SCBRR_ALGO_2,
185 .type = PORT_SCI, 188 .type = PORT_SCI,
186 .irqs = { 80, 81, 82, 0 }, 189 .irqs = { 80, 81, 82, 0 },
190 .regshift = 2,
187}; 191};
188 192
189static struct platform_device scif3_device = { 193static struct platform_device scif3_device = {
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index cc122b1d3035..c57fb287011e 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -10,7 +10,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
10obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o 10obj-$(CONFIG_CPU_SUBTYPE_SH7785) += setup-sh7785.o
11obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o intc-shx3.o 11obj-$(CONFIG_CPU_SUBTYPE_SH7786) += setup-sh7786.o intc-shx3.o
12obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o 12obj-$(CONFIG_CPU_SUBTYPE_SH7343) += setup-sh7343.o
13obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o 13obj-$(CONFIG_CPU_SUBTYPE_SH7722) += setup-sh7722.o serial-sh7722.o
14obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o 14obj-$(CONFIG_CPU_SUBTYPE_SH7723) += setup-sh7723.o
15obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o 15obj-$(CONFIG_CPU_SUBTYPE_SH7724) += setup-sh7724.o
16obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o 16obj-$(CONFIG_CPU_SUBTYPE_SH7366) += setup-sh7366.o
diff --git a/arch/sh/kernel/cpu/sh4a/serial-sh7722.c b/arch/sh/kernel/cpu/sh4a/serial-sh7722.c
new file mode 100644
index 000000000000..59bc3a72702e
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/serial-sh7722.c
@@ -0,0 +1,23 @@
1#include <linux/serial_sci.h>
2#include <linux/serial_core.h>
3#include <linux/io.h>
4
5#define PSCR 0xA405011E
6
7static void sh7722_sci_init_pins(struct uart_port *port, unsigned int cflag)
8{
9 unsigned short data;
10
11 if (port->mapbase == 0xffe00000) {
12 data = __raw_readw(PSCR);
13 data &= ~0x03cf;
14 if (!(cflag & CRTSCTS))
15 data |= 0x0340;
16
17 __raw_writew(data, PSCR);
18 }
19}
20
21struct plat_sci_port_ops sh7722_sci_port_ops = {
22 .init_pins = sh7722_sci_init_pins,
23};
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
index 82616af64d62..87773869a2f3 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7366.c
@@ -20,6 +20,7 @@
20 20
21static struct plat_sci_port scif0_platform_data = { 21static struct plat_sci_port scif0_platform_data = {
22 .mapbase = 0xffe00000, 22 .mapbase = 0xffe00000,
23 .port_reg = 0xa405013e,
23 .flags = UPF_BOOT_AUTOCONF, 24 .flags = UPF_BOOT_AUTOCONF,
24 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 25 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
25 .scbrr_algo_id = SCBRR_ALGO_2, 26 .scbrr_algo_id = SCBRR_ALGO_2,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
index 5813d8023619..863249dbf05b 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7722.c
@@ -185,6 +185,8 @@ static struct plat_sci_port scif0_platform_data = {
185 .scbrr_algo_id = SCBRR_ALGO_2, 185 .scbrr_algo_id = SCBRR_ALGO_2,
186 .type = PORT_SCIF, 186 .type = PORT_SCIF,
187 .irqs = { 80, 80, 80, 80 }, 187 .irqs = { 80, 80, 80, 80 },
188 .ops = &sh7722_sci_port_ops,
189 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
188}; 190};
189 191
190static struct platform_device scif0_device = { 192static struct platform_device scif0_device = {
@@ -202,6 +204,8 @@ static struct plat_sci_port scif1_platform_data = {
202 .scbrr_algo_id = SCBRR_ALGO_2, 204 .scbrr_algo_id = SCBRR_ALGO_2,
203 .type = PORT_SCIF, 205 .type = PORT_SCIF,
204 .irqs = { 81, 81, 81, 81 }, 206 .irqs = { 81, 81, 81, 81 },
207 .ops = &sh7722_sci_port_ops,
208 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
205}; 209};
206 210
207static struct platform_device scif1_device = { 211static struct platform_device scif1_device = {
@@ -219,6 +223,8 @@ static struct plat_sci_port scif2_platform_data = {
219 .scbrr_algo_id = SCBRR_ALGO_2, 223 .scbrr_algo_id = SCBRR_ALGO_2,
220 .type = PORT_SCIF, 224 .type = PORT_SCIF,
221 .irqs = { 82, 82, 82, 82 }, 225 .irqs = { 82, 82, 82, 82 },
226 .ops = &sh7722_sci_port_ops,
227 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
222}; 228};
223 229
224static struct platform_device scif2_device = { 230static struct platform_device scif2_device = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 072382280f96..3c2810d8f72e 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -23,11 +23,13 @@
23/* Serial */ 23/* Serial */
24static struct plat_sci_port scif0_platform_data = { 24static struct plat_sci_port scif0_platform_data = {
25 .mapbase = 0xffe00000, 25 .mapbase = 0xffe00000,
26 .port_reg = 0xa4050160,
26 .flags = UPF_BOOT_AUTOCONF, 27 .flags = UPF_BOOT_AUTOCONF,
27 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 28 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
28 .scbrr_algo_id = SCBRR_ALGO_2, 29 .scbrr_algo_id = SCBRR_ALGO_2,
29 .type = PORT_SCIF, 30 .type = PORT_SCIF,
30 .irqs = { 80, 80, 80, 80 }, 31 .irqs = { 80, 80, 80, 80 },
32 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
31}; 33};
32 34
33static struct platform_device scif0_device = { 35static struct platform_device scif0_device = {
@@ -40,11 +42,13 @@ static struct platform_device scif0_device = {
40 42
41static struct plat_sci_port scif1_platform_data = { 43static struct plat_sci_port scif1_platform_data = {
42 .mapbase = 0xffe10000, 44 .mapbase = 0xffe10000,
45 .port_reg = SCIx_NOT_SUPPORTED,
43 .flags = UPF_BOOT_AUTOCONF, 46 .flags = UPF_BOOT_AUTOCONF,
44 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 47 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
45 .scbrr_algo_id = SCBRR_ALGO_2, 48 .scbrr_algo_id = SCBRR_ALGO_2,
46 .type = PORT_SCIF, 49 .type = PORT_SCIF,
47 .irqs = { 81, 81, 81, 81 }, 50 .irqs = { 81, 81, 81, 81 },
51 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
48}; 52};
49 53
50static struct platform_device scif1_device = { 54static struct platform_device scif1_device = {
@@ -57,11 +61,13 @@ static struct platform_device scif1_device = {
57 61
58static struct plat_sci_port scif2_platform_data = { 62static struct plat_sci_port scif2_platform_data = {
59 .mapbase = 0xffe20000, 63 .mapbase = 0xffe20000,
64 .port_reg = SCIx_NOT_SUPPORTED,
60 .flags = UPF_BOOT_AUTOCONF, 65 .flags = UPF_BOOT_AUTOCONF,
61 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 66 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
62 .scbrr_algo_id = SCBRR_ALGO_2, 67 .scbrr_algo_id = SCBRR_ALGO_2,
63 .type = PORT_SCIF, 68 .type = PORT_SCIF,
64 .irqs = { 82, 82, 82, 82 }, 69 .irqs = { 82, 82, 82, 82 },
70 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
65}; 71};
66 72
67static struct platform_device scif2_device = { 73static struct platform_device scif2_device = {
@@ -75,6 +81,7 @@ static struct platform_device scif2_device = {
75static struct plat_sci_port scif3_platform_data = { 81static struct plat_sci_port scif3_platform_data = {
76 .mapbase = 0xa4e30000, 82 .mapbase = 0xa4e30000,
77 .flags = UPF_BOOT_AUTOCONF, 83 .flags = UPF_BOOT_AUTOCONF,
84 .port_reg = SCIx_NOT_SUPPORTED,
78 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 85 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
79 .scbrr_algo_id = SCBRR_ALGO_3, 86 .scbrr_algo_id = SCBRR_ALGO_3,
80 .type = PORT_SCIFA, 87 .type = PORT_SCIFA,
@@ -91,6 +98,7 @@ static struct platform_device scif3_device = {
91 98
92static struct plat_sci_port scif4_platform_data = { 99static struct plat_sci_port scif4_platform_data = {
93 .mapbase = 0xa4e40000, 100 .mapbase = 0xa4e40000,
101 .port_reg = SCIx_NOT_SUPPORTED,
94 .flags = UPF_BOOT_AUTOCONF, 102 .flags = UPF_BOOT_AUTOCONF,
95 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 103 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
96 .scbrr_algo_id = SCBRR_ALGO_3, 104 .scbrr_algo_id = SCBRR_ALGO_3,
@@ -108,6 +116,7 @@ static struct platform_device scif4_device = {
108 116
109static struct plat_sci_port scif5_platform_data = { 117static struct plat_sci_port scif5_platform_data = {
110 .mapbase = 0xa4e50000, 118 .mapbase = 0xa4e50000,
119 .port_reg = SCIx_NOT_SUPPORTED,
111 .flags = UPF_BOOT_AUTOCONF, 120 .flags = UPF_BOOT_AUTOCONF,
112 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 121 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
113 .scbrr_algo_id = SCBRR_ALGO_3, 122 .scbrr_algo_id = SCBRR_ALGO_3,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 0333fe9e3881..8c892887ebd7 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -256,11 +256,13 @@ static struct platform_device dma1_device = {
256/* Serial */ 256/* Serial */
257static struct plat_sci_port scif0_platform_data = { 257static struct plat_sci_port scif0_platform_data = {
258 .mapbase = 0xffe00000, 258 .mapbase = 0xffe00000,
259 .port_reg = SCIx_NOT_SUPPORTED,
259 .flags = UPF_BOOT_AUTOCONF, 260 .flags = UPF_BOOT_AUTOCONF,
260 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 261 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
261 .scbrr_algo_id = SCBRR_ALGO_2, 262 .scbrr_algo_id = SCBRR_ALGO_2,
262 .type = PORT_SCIF, 263 .type = PORT_SCIF,
263 .irqs = { 80, 80, 80, 80 }, 264 .irqs = { 80, 80, 80, 80 },
265 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
264}; 266};
265 267
266static struct platform_device scif0_device = { 268static struct platform_device scif0_device = {
@@ -273,11 +275,13 @@ static struct platform_device scif0_device = {
273 275
274static struct plat_sci_port scif1_platform_data = { 276static struct plat_sci_port scif1_platform_data = {
275 .mapbase = 0xffe10000, 277 .mapbase = 0xffe10000,
278 .port_reg = SCIx_NOT_SUPPORTED,
276 .flags = UPF_BOOT_AUTOCONF, 279 .flags = UPF_BOOT_AUTOCONF,
277 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 280 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
278 .scbrr_algo_id = SCBRR_ALGO_2, 281 .scbrr_algo_id = SCBRR_ALGO_2,
279 .type = PORT_SCIF, 282 .type = PORT_SCIF,
280 .irqs = { 81, 81, 81, 81 }, 283 .irqs = { 81, 81, 81, 81 },
284 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
281}; 285};
282 286
283static struct platform_device scif1_device = { 287static struct platform_device scif1_device = {
@@ -290,11 +294,13 @@ static struct platform_device scif1_device = {
290 294
291static struct plat_sci_port scif2_platform_data = { 295static struct plat_sci_port scif2_platform_data = {
292 .mapbase = 0xffe20000, 296 .mapbase = 0xffe20000,
297 .port_reg = SCIx_NOT_SUPPORTED,
293 .flags = UPF_BOOT_AUTOCONF, 298 .flags = UPF_BOOT_AUTOCONF,
294 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE, 299 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
295 .scbrr_algo_id = SCBRR_ALGO_2, 300 .scbrr_algo_id = SCBRR_ALGO_2,
296 .type = PORT_SCIF, 301 .type = PORT_SCIF,
297 .irqs = { 82, 82, 82, 82 }, 302 .irqs = { 82, 82, 82, 82 },
303 .regtype = SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
298}; 304};
299 305
300static struct platform_device scif2_device = { 306static struct platform_device scif2_device = {
@@ -307,6 +313,7 @@ static struct platform_device scif2_device = {
307 313
308static struct plat_sci_port scif3_platform_data = { 314static struct plat_sci_port scif3_platform_data = {
309 .mapbase = 0xa4e30000, 315 .mapbase = 0xa4e30000,
316 .port_reg = SCIx_NOT_SUPPORTED,
310 .flags = UPF_BOOT_AUTOCONF, 317 .flags = UPF_BOOT_AUTOCONF,
311 .scscr = SCSCR_RE | SCSCR_TE, 318 .scscr = SCSCR_RE | SCSCR_TE,
312 .scbrr_algo_id = SCBRR_ALGO_3, 319 .scbrr_algo_id = SCBRR_ALGO_3,
@@ -324,6 +331,7 @@ static struct platform_device scif3_device = {
324 331
325static struct plat_sci_port scif4_platform_data = { 332static struct plat_sci_port scif4_platform_data = {
326 .mapbase = 0xa4e40000, 333 .mapbase = 0xa4e40000,
334 .port_reg = SCIx_NOT_SUPPORTED,
327 .flags = UPF_BOOT_AUTOCONF, 335 .flags = UPF_BOOT_AUTOCONF,
328 .scscr = SCSCR_RE | SCSCR_TE, 336 .scscr = SCSCR_RE | SCSCR_TE,
329 .scbrr_algo_id = SCBRR_ALGO_3, 337 .scbrr_algo_id = SCBRR_ALGO_3,
@@ -341,6 +349,7 @@ static struct platform_device scif4_device = {
341 349
342static struct plat_sci_port scif5_platform_data = { 350static struct plat_sci_port scif5_platform_data = {
343 .mapbase = 0xa4e50000, 351 .mapbase = 0xa4e50000,
352 .port_reg = SCIx_NOT_SUPPORTED,
344 .flags = UPF_BOOT_AUTOCONF, 353 .flags = UPF_BOOT_AUTOCONF,
345 .scscr = SCSCR_RE | SCSCR_TE, 354 .scscr = SCSCR_RE | SCSCR_TE,
346 .scbrr_algo_id = SCBRR_ALGO_3, 355 .scbrr_algo_id = SCBRR_ALGO_3,
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 593eca6509b5..00113515f233 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -23,6 +23,7 @@ static struct plat_sci_port scif0_platform_data = {
23 .scbrr_algo_id = SCBRR_ALGO_2, 23 .scbrr_algo_id = SCBRR_ALGO_2,
24 .type = PORT_SCIF, 24 .type = PORT_SCIF,
25 .irqs = { 40, 40, 40, 40 }, 25 .irqs = { 40, 40, 40, 40 },
26 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
26}; 27};
27 28
28static struct platform_device scif0_device = { 29static struct platform_device scif0_device = {
@@ -40,6 +41,7 @@ static struct plat_sci_port scif1_platform_data = {
40 .scbrr_algo_id = SCBRR_ALGO_2, 41 .scbrr_algo_id = SCBRR_ALGO_2,
41 .type = PORT_SCIF, 42 .type = PORT_SCIF,
42 .irqs = { 76, 76, 76, 76 }, 43 .irqs = { 76, 76, 76, 76 },
44 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
43}; 45};
44 46
45static struct platform_device scif1_device = { 47static struct platform_device scif1_device = {
@@ -57,6 +59,7 @@ static struct plat_sci_port scif2_platform_data = {
57 .scbrr_algo_id = SCBRR_ALGO_2, 59 .scbrr_algo_id = SCBRR_ALGO_2,
58 .type = PORT_SCIF, 60 .type = PORT_SCIF,
59 .irqs = { 104, 104, 104, 104 }, 61 .irqs = { 104, 104, 104, 104 },
62 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
60}; 63};
61 64
62static struct platform_device scif2_device = { 65static struct platform_device scif2_device = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index 08add7fa6849..3d4d2075c19a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -14,7 +14,6 @@
14#include <linux/serial_sci.h> 14#include <linux/serial_sci.h>
15#include <linux/sh_dma.h> 15#include <linux/sh_dma.h>
16#include <linux/sh_timer.h> 16#include <linux/sh_timer.h>
17
18#include <cpu/dma-register.h> 17#include <cpu/dma-register.h>
19 18
20static struct plat_sci_port scif0_platform_data = { 19static struct plat_sci_port scif0_platform_data = {
@@ -24,6 +23,7 @@ static struct plat_sci_port scif0_platform_data = {
24 .scbrr_algo_id = SCBRR_ALGO_1, 23 .scbrr_algo_id = SCBRR_ALGO_1,
25 .type = PORT_SCIF, 24 .type = PORT_SCIF,
26 .irqs = { 40, 40, 40, 40 }, 25 .irqs = { 40, 40, 40, 40 },
26 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
27}; 27};
28 28
29static struct platform_device scif0_device = { 29static struct platform_device scif0_device = {
@@ -41,6 +41,7 @@ static struct plat_sci_port scif1_platform_data = {
41 .scbrr_algo_id = SCBRR_ALGO_1, 41 .scbrr_algo_id = SCBRR_ALGO_1,
42 .type = PORT_SCIF, 42 .type = PORT_SCIF,
43 .irqs = { 76, 76, 76, 76 }, 43 .irqs = { 76, 76, 76, 76 },
44 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
44}; 45};
45 46
46static struct platform_device scif1_device = { 47static struct platform_device scif1_device = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index 18d8fc136fb2..b29e6340414a 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -15,9 +15,7 @@
15#include <linux/mm.h> 15#include <linux/mm.h>
16#include <linux/sh_dma.h> 16#include <linux/sh_dma.h>
17#include <linux/sh_timer.h> 17#include <linux/sh_timer.h>
18
19#include <asm/mmzone.h> 18#include <asm/mmzone.h>
20
21#include <cpu/dma-register.h> 19#include <cpu/dma-register.h>
22 20
23static struct plat_sci_port scif0_platform_data = { 21static struct plat_sci_port scif0_platform_data = {
@@ -27,6 +25,7 @@ static struct plat_sci_port scif0_platform_data = {
27 .scbrr_algo_id = SCBRR_ALGO_1, 25 .scbrr_algo_id = SCBRR_ALGO_1,
28 .type = PORT_SCIF, 26 .type = PORT_SCIF,
29 .irqs = { 40, 40, 40, 40 }, 27 .irqs = { 40, 40, 40, 40 },
28 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
30}; 29};
31 30
32static struct platform_device scif0_device = { 31static struct platform_device scif0_device = {
@@ -44,6 +43,7 @@ static struct plat_sci_port scif1_platform_data = {
44 .scbrr_algo_id = SCBRR_ALGO_1, 43 .scbrr_algo_id = SCBRR_ALGO_1,
45 .type = PORT_SCIF, 44 .type = PORT_SCIF,
46 .irqs = { 44, 44, 44, 44 }, 45 .irqs = { 44, 44, 44, 44 },
46 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
47}; 47};
48 48
49static struct platform_device scif1_device = { 49static struct platform_device scif1_device = {
@@ -61,6 +61,7 @@ static struct plat_sci_port scif2_platform_data = {
61 .scbrr_algo_id = SCBRR_ALGO_1, 61 .scbrr_algo_id = SCBRR_ALGO_1,
62 .type = PORT_SCIF, 62 .type = PORT_SCIF,
63 .irqs = { 60, 60, 60, 60 }, 63 .irqs = { 60, 60, 60, 60 },
64 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
64}; 65};
65 66
66static struct platform_device scif2_device = { 67static struct platform_device scif2_device = {
@@ -78,6 +79,7 @@ static struct plat_sci_port scif3_platform_data = {
78 .scbrr_algo_id = SCBRR_ALGO_1, 79 .scbrr_algo_id = SCBRR_ALGO_1,
79 .type = PORT_SCIF, 80 .type = PORT_SCIF,
80 .irqs = { 61, 61, 61, 61 }, 81 .irqs = { 61, 61, 61, 61 },
82 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
81}; 83};
82 84
83static struct platform_device scif3_device = { 85static struct platform_device scif3_device = {
@@ -95,6 +97,7 @@ static struct plat_sci_port scif4_platform_data = {
95 .scbrr_algo_id = SCBRR_ALGO_1, 97 .scbrr_algo_id = SCBRR_ALGO_1,
96 .type = PORT_SCIF, 98 .type = PORT_SCIF,
97 .irqs = { 62, 62, 62, 62 }, 99 .irqs = { 62, 62, 62, 62 },
100 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
98}; 101};
99 102
100static struct platform_device scif4_device = { 103static struct platform_device scif4_device = {
@@ -112,6 +115,7 @@ static struct plat_sci_port scif5_platform_data = {
112 .scbrr_algo_id = SCBRR_ALGO_1, 115 .scbrr_algo_id = SCBRR_ALGO_1,
113 .type = PORT_SCIF, 116 .type = PORT_SCIF,
114 .irqs = { 63, 63, 63, 63 }, 117 .irqs = { 63, 63, 63, 63 },
118 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
115}; 119};
116 120
117static struct platform_device scif5_device = { 121static struct platform_device scif5_device = {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index beba32beb6d9..dd5e709f9821 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * SH7786 Setup 2 * SH7786 Setup
3 * 3 *
4 * Copyright (C) 2009 - 2010 Renesas Solutions Corp. 4 * Copyright (C) 2009 - 2011 Renesas Solutions Corp.
5 * Kuninori Morimoto <morimoto.kuninori@renesas.com> 5 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
6 * Paul Mundt <paul.mundt@renesas.com> 6 * Paul Mundt <paul.mundt@renesas.com>
7 * 7 *
@@ -33,6 +33,7 @@ static struct plat_sci_port scif0_platform_data = {
33 .scbrr_algo_id = SCBRR_ALGO_1, 33 .scbrr_algo_id = SCBRR_ALGO_1,
34 .type = PORT_SCIF, 34 .type = PORT_SCIF,
35 .irqs = { 40, 41, 43, 42 }, 35 .irqs = { 40, 41, 43, 42 },
36 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
36}; 37};
37 38
38static struct platform_device scif0_device = { 39static struct platform_device scif0_device = {
@@ -53,6 +54,7 @@ static struct plat_sci_port scif1_platform_data = {
53 .scbrr_algo_id = SCBRR_ALGO_1, 54 .scbrr_algo_id = SCBRR_ALGO_1,
54 .type = PORT_SCIF, 55 .type = PORT_SCIF,
55 .irqs = { 44, 44, 44, 44 }, 56 .irqs = { 44, 44, 44, 44 },
57 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
56}; 58};
57 59
58static struct platform_device scif1_device = { 60static struct platform_device scif1_device = {
@@ -70,6 +72,7 @@ static struct plat_sci_port scif2_platform_data = {
70 .scbrr_algo_id = SCBRR_ALGO_1, 72 .scbrr_algo_id = SCBRR_ALGO_1,
71 .type = PORT_SCIF, 73 .type = PORT_SCIF,
72 .irqs = { 50, 50, 50, 50 }, 74 .irqs = { 50, 50, 50, 50 },
75 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
73}; 76};
74 77
75static struct platform_device scif2_device = { 78static struct platform_device scif2_device = {
@@ -87,6 +90,7 @@ static struct plat_sci_port scif3_platform_data = {
87 .scbrr_algo_id = SCBRR_ALGO_1, 90 .scbrr_algo_id = SCBRR_ALGO_1,
88 .type = PORT_SCIF, 91 .type = PORT_SCIF,
89 .irqs = { 51, 51, 51, 51 }, 92 .irqs = { 51, 51, 51, 51 },
93 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
90}; 94};
91 95
92static struct platform_device scif3_device = { 96static struct platform_device scif3_device = {
@@ -104,6 +108,7 @@ static struct plat_sci_port scif4_platform_data = {
104 .scbrr_algo_id = SCBRR_ALGO_1, 108 .scbrr_algo_id = SCBRR_ALGO_1,
105 .type = PORT_SCIF, 109 .type = PORT_SCIF,
106 .irqs = { 52, 52, 52, 52 }, 110 .irqs = { 52, 52, 52, 52 },
111 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
107}; 112};
108 113
109static struct platform_device scif4_device = { 114static struct platform_device scif4_device = {
@@ -121,6 +126,7 @@ static struct plat_sci_port scif5_platform_data = {
121 .scbrr_algo_id = SCBRR_ALGO_1, 126 .scbrr_algo_id = SCBRR_ALGO_1,
122 .type = PORT_SCIF, 127 .type = PORT_SCIF,
123 .irqs = { 53, 53, 53, 53 }, 128 .irqs = { 53, 53, 53, 53 },
129 .regtype = SCIx_SH4_SCIF_FIFODATA_REGTYPE,
124}; 130};
125 131
126static struct platform_device scif5_device = { 132static struct platform_device scif5_device = {
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 636144cea932..1c0cd2d26d37 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -974,7 +974,7 @@ config SERIAL_IP22_ZILOG_CONSOLE
974 974
975config SERIAL_SH_SCI 975config SERIAL_SH_SCI
976 tristate "SuperH SCI(F) serial port support" 976 tristate "SuperH SCI(F) serial port support"
977 depends on HAVE_CLK && (SUPERH || H8300 || ARCH_SHMOBILE) 977 depends on HAVE_CLK && (SUPERH || ARCH_SHMOBILE)
978 select SERIAL_CORE 978 select SERIAL_CORE
979 979
980config SERIAL_SH_SCI_NR_UARTS 980config SERIAL_SH_SCI_NR_UARTS
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index ebd8629c108d..8e55e0a2733a 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -54,10 +54,6 @@
54#include <asm/sh_bios.h> 54#include <asm/sh_bios.h>
55#endif 55#endif
56 56
57#ifdef CONFIG_H8300
58#include <asm/gpio.h>
59#endif
60
61#include "sh-sci.h" 57#include "sh-sci.h"
62 58
63struct sci_port { 59struct sci_port {
@@ -121,6 +117,255 @@ to_sci_port(struct uart_port *uart)
121 return container_of(uart, struct sci_port, port); 117 return container_of(uart, struct sci_port, port);
122} 118}
123 119
120struct plat_sci_reg {
121 u8 offset, size;
122};
123
124/* Helper for invalidating specific entries of an inherited map. */
125#define sci_reg_invalid { .offset = 0, .size = 0 }
126
127static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
128 [SCIx_PROBE_REGTYPE] = {
129 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
130 },
131
132 /*
133 * Common SCI definitions, dependent on the port's regshift
134 * value.
135 */
136 [SCIx_SCI_REGTYPE] = {
137 [SCSMR] = { 0x00, 8 },
138 [SCBRR] = { 0x01, 8 },
139 [SCSCR] = { 0x02, 8 },
140 [SCxTDR] = { 0x03, 8 },
141 [SCxSR] = { 0x04, 8 },
142 [SCxRDR] = { 0x05, 8 },
143 [SCFCR] = sci_reg_invalid,
144 [SCFDR] = sci_reg_invalid,
145 [SCTFDR] = sci_reg_invalid,
146 [SCRFDR] = sci_reg_invalid,
147 [SCSPTR] = sci_reg_invalid,
148 [SCLSR] = sci_reg_invalid,
149 },
150
151 /*
152 * Common definitions for legacy IrDA ports, dependent on
153 * regshift value.
154 */
155 [SCIx_IRDA_REGTYPE] = {
156 [SCSMR] = { 0x00, 8 },
157 [SCBRR] = { 0x01, 8 },
158 [SCSCR] = { 0x02, 8 },
159 [SCxTDR] = { 0x03, 8 },
160 [SCxSR] = { 0x04, 8 },
161 [SCxRDR] = { 0x05, 8 },
162 [SCFCR] = { 0x06, 8 },
163 [SCFDR] = { 0x07, 16 },
164 [SCTFDR] = sci_reg_invalid,
165 [SCRFDR] = sci_reg_invalid,
166 [SCSPTR] = sci_reg_invalid,
167 [SCLSR] = sci_reg_invalid,
168 },
169
170 /*
171 * Common SCIFA definitions.
172 */
173 [SCIx_SCIFA_REGTYPE] = {
174 [SCSMR] = { 0x00, 16 },
175 [SCBRR] = { 0x04, 8 },
176 [SCSCR] = { 0x08, 16 },
177 [SCxTDR] = { 0x20, 8 },
178 [SCxSR] = { 0x14, 16 },
179 [SCxRDR] = { 0x24, 8 },
180 [SCFCR] = { 0x18, 16 },
181 [SCFDR] = { 0x1c, 16 },
182 [SCTFDR] = sci_reg_invalid,
183 [SCRFDR] = sci_reg_invalid,
184 [SCSPTR] = sci_reg_invalid,
185 [SCLSR] = sci_reg_invalid,
186 },
187
188 /*
189 * Common SCIFB definitions.
190 */
191 [SCIx_SCIFB_REGTYPE] = {
192 [SCSMR] = { 0x00, 16 },
193 [SCBRR] = { 0x04, 8 },
194 [SCSCR] = { 0x08, 16 },
195 [SCxTDR] = { 0x40, 8 },
196 [SCxSR] = { 0x14, 16 },
197 [SCxRDR] = { 0x60, 8 },
198 [SCFCR] = { 0x18, 16 },
199 [SCFDR] = { 0x1c, 16 },
200 [SCTFDR] = sci_reg_invalid,
201 [SCRFDR] = sci_reg_invalid,
202 [SCSPTR] = sci_reg_invalid,
203 [SCLSR] = sci_reg_invalid,
204 },
205
206 /*
207 * Common SH-3 SCIF definitions.
208 */
209 [SCIx_SH3_SCIF_REGTYPE] = {
210 [SCSMR] = { 0x00, 8 },
211 [SCBRR] = { 0x02, 8 },
212 [SCSCR] = { 0x04, 8 },
213 [SCxTDR] = { 0x06, 8 },
214 [SCxSR] = { 0x08, 16 },
215 [SCxRDR] = { 0x0a, 8 },
216 [SCFCR] = { 0x0c, 8 },
217 [SCFDR] = { 0x0e, 16 },
218 [SCTFDR] = sci_reg_invalid,
219 [SCRFDR] = sci_reg_invalid,
220 [SCSPTR] = sci_reg_invalid,
221 [SCLSR] = sci_reg_invalid,
222 },
223
224 /*
225 * Common SH-4(A) SCIF(B) definitions.
226 */
227 [SCIx_SH4_SCIF_REGTYPE] = {
228 [SCSMR] = { 0x00, 16 },
229 [SCBRR] = { 0x04, 8 },
230 [SCSCR] = { 0x08, 16 },
231 [SCxTDR] = { 0x0c, 8 },
232 [SCxSR] = { 0x10, 16 },
233 [SCxRDR] = { 0x14, 8 },
234 [SCFCR] = { 0x18, 16 },
235 [SCFDR] = { 0x1c, 16 },
236 [SCTFDR] = sci_reg_invalid,
237 [SCRFDR] = sci_reg_invalid,
238 [SCSPTR] = { 0x20, 16 },
239 [SCLSR] = { 0x24, 16 },
240 },
241
242 /*
243 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
244 * register.
245 */
246 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
247 [SCSMR] = { 0x00, 16 },
248 [SCBRR] = { 0x04, 8 },
249 [SCSCR] = { 0x08, 16 },
250 [SCxTDR] = { 0x0c, 8 },
251 [SCxSR] = { 0x10, 16 },
252 [SCxRDR] = { 0x14, 8 },
253 [SCFCR] = { 0x18, 16 },
254 [SCFDR] = { 0x1c, 16 },
255 [SCTFDR] = sci_reg_invalid,
256 [SCRFDR] = sci_reg_invalid,
257 [SCSPTR] = sci_reg_invalid,
258 [SCLSR] = { 0x24, 16 },
259 },
260
261 /*
262 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
263 * count registers.
264 */
265 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
266 [SCSMR] = { 0x00, 16 },
267 [SCBRR] = { 0x04, 8 },
268 [SCSCR] = { 0x08, 16 },
269 [SCxTDR] = { 0x0c, 8 },
270 [SCxSR] = { 0x10, 16 },
271 [SCxRDR] = { 0x14, 8 },
272 [SCFCR] = { 0x18, 16 },
273 [SCFDR] = { 0x1c, 16 },
274 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
275 [SCRFDR] = { 0x20, 16 },
276 [SCSPTR] = { 0x24, 16 },
277 [SCLSR] = { 0x28, 16 },
278 },
279
280 /*
281 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
282 * registers.
283 */
284 [SCIx_SH7705_SCIF_REGTYPE] = {
285 [SCSMR] = { 0x00, 16 },
286 [SCBRR] = { 0x04, 8 },
287 [SCSCR] = { 0x08, 16 },
288 [SCxTDR] = { 0x20, 8 },
289 [SCxSR] = { 0x14, 16 },
290 [SCxRDR] = { 0x24, 8 },
291 [SCFCR] = { 0x18, 16 },
292 [SCFDR] = { 0x1c, 16 },
293 [SCTFDR] = sci_reg_invalid,
294 [SCRFDR] = sci_reg_invalid,
295 [SCSPTR] = sci_reg_invalid,
296 [SCLSR] = sci_reg_invalid,
297 },
298};
299
300#define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
301
302/*
303 * The "offset" here is rather misleading, in that it refers to an enum
304 * value relative to the port mapping rather than the fixed offset
305 * itself, which needs to be manually retrieved from the platform's
306 * register map for the given port.
307 */
308static unsigned int sci_serial_in(struct uart_port *p, int offset)
309{
310 struct plat_sci_reg *reg = sci_getreg(p, offset);
311
312 if (reg->size == 8)
313 return ioread8(p->membase + (reg->offset << p->regshift));
314 else if (reg->size == 16)
315 return ioread16(p->membase + (reg->offset << p->regshift));
316 else
317 WARN(1, "Invalid register access\n");
318
319 return 0;
320}
321
322static void sci_serial_out(struct uart_port *p, int offset, int value)
323{
324 struct plat_sci_reg *reg = sci_getreg(p, offset);
325
326 if (reg->size == 8)
327 iowrite8(value, p->membase + (reg->offset << p->regshift));
328 else if (reg->size == 16)
329 iowrite16(value, p->membase + (reg->offset << p->regshift));
330 else
331 WARN(1, "Invalid register access\n");
332}
333
334#define sci_in(up, offset) (up->serial_in(up, offset))
335#define sci_out(up, offset, value) (up->serial_out(up, offset, value))
336
337static int sci_probe_regmap(struct plat_sci_port *cfg)
338{
339 switch (cfg->type) {
340 case PORT_SCI:
341 cfg->regtype = SCIx_SCI_REGTYPE;
342 break;
343 case PORT_IRDA:
344 cfg->regtype = SCIx_IRDA_REGTYPE;
345 break;
346 case PORT_SCIFA:
347 cfg->regtype = SCIx_SCIFA_REGTYPE;
348 break;
349 case PORT_SCIFB:
350 cfg->regtype = SCIx_SCIFB_REGTYPE;
351 break;
352 case PORT_SCIF:
353 /*
354 * The SH-4 is a bit of a misnomer here, although that's
355 * where this particular port layout originated. This
356 * configuration (or some slight variation thereof)
357 * remains the dominant model for all SCIFs.
358 */
359 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
360 break;
361 default:
362 printk(KERN_ERR "Can't probe register map for given port\n");
363 return -EINVAL;
364 }
365
366 return 0;
367}
368
124#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) 369#if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
125 370
126#ifdef CONFIG_CONSOLE_POLL 371#ifdef CONFIG_CONSOLE_POLL
@@ -164,223 +409,76 @@ static void sci_poll_put_char(struct uart_port *port, unsigned char c)
164} 409}
165#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */ 410#endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
166 411
167#if defined(__H8300H__) || defined(__H8300S__)
168static void sci_init_pins(struct uart_port *port, unsigned int cflag) 412static void sci_init_pins(struct uart_port *port, unsigned int cflag)
169{ 413{
170 int ch = (port->mapbase - SMR0) >> 3; 414 struct sci_port *s = to_sci_port(port);
171 415 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
172 /* set DDR regs */
173 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
174 h8300_sci_pins[ch].rx,
175 H8300_GPIO_INPUT);
176 H8300_GPIO_DDR(h8300_sci_pins[ch].port,
177 h8300_sci_pins[ch].tx,
178 H8300_GPIO_OUTPUT);
179
180 /* tx mark output*/
181 H8300_SCI_DR(ch) |= h8300_sci_pins[ch].tx;
182}
183#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
184static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
185{
186 if (port->mapbase == 0xA4400000) {
187 __raw_writew(__raw_readw(PACR) & 0xffc0, PACR);
188 __raw_writew(__raw_readw(PBCR) & 0x0fff, PBCR);
189 } else if (port->mapbase == 0xA4410000)
190 __raw_writew(__raw_readw(PBCR) & 0xf003, PBCR);
191}
192#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
193static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
194{
195 unsigned short data;
196
197 if (cflag & CRTSCTS) {
198 /* enable RTS/CTS */
199 if (port->mapbase == 0xa4430000) { /* SCIF0 */
200 /* Clear PTCR bit 9-2; enable all scif pins but sck */
201 data = __raw_readw(PORT_PTCR);
202 __raw_writew((data & 0xfc03), PORT_PTCR);
203 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
204 /* Clear PVCR bit 9-2 */
205 data = __raw_readw(PORT_PVCR);
206 __raw_writew((data & 0xfc03), PORT_PVCR);
207 }
208 } else {
209 if (port->mapbase == 0xa4430000) { /* SCIF0 */
210 /* Clear PTCR bit 5-2; enable only tx and rx */
211 data = __raw_readw(PORT_PTCR);
212 __raw_writew((data & 0xffc3), PORT_PTCR);
213 } else if (port->mapbase == 0xa4438000) { /* SCIF1 */
214 /* Clear PVCR bit 5-2 */
215 data = __raw_readw(PORT_PVCR);
216 __raw_writew((data & 0xffc3), PORT_PVCR);
217 }
218 }
219}
220#elif defined(CONFIG_CPU_SH3)
221/* For SH7705, SH7706, SH7707, SH7709, SH7709A, SH7729 */
222static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
223{
224 unsigned short data;
225
226 /* We need to set SCPCR to enable RTS/CTS */
227 data = __raw_readw(SCPCR);
228 /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/
229 __raw_writew(data & 0x0fcf, SCPCR);
230
231 if (!(cflag & CRTSCTS)) {
232 /* We need to set SCPCR to enable RTS/CTS */
233 data = __raw_readw(SCPCR);
234 /* Clear out SCP7MD1,0, SCP4MD1,0,
235 Set SCP6MD1,0 = {01} (output) */
236 __raw_writew((data & 0x0fcf) | 0x1000, SCPCR);
237 416
238 data = __raw_readb(SCPDR); 417 /*
239 /* Set /RTS2 (bit6) = 0 */ 418 * Use port-specific handler if provided.
240 __raw_writeb(data & 0xbf, SCPDR); 419 */
420 if (s->cfg->ops && s->cfg->ops->init_pins) {
421 s->cfg->ops->init_pins(port, cflag);
422 return;
241 } 423 }
242}
243#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
244static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
245{
246 unsigned short data;
247 424
248 if (port->mapbase == 0xffe00000) { 425 /*
249 data = __raw_readw(PSCR); 426 * For the generic path SCSPTR is necessary. Bail out if that's
250 data &= ~0x03cf; 427 * unavailable, too.
251 if (!(cflag & CRTSCTS)) 428 */
252 data |= 0x0340; 429 if (!reg->size)
430 return;
253 431
254 __raw_writew(data, PSCR);
255 }
256}
257#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
258 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
259 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
260 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
261 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
262 defined(CONFIG_CPU_SUBTYPE_SHX3)
263static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
264{
265 if (!(cflag & CRTSCTS)) 432 if (!(cflag & CRTSCTS))
266 __raw_writew(0x0080, SCSPTR0); /* Set RTS = 1 */ 433 sci_out(port, SCSPTR, 0x0080); /* Set RTS = 1 */
267} 434}
268#elif defined(CONFIG_CPU_SH4) && !defined(CONFIG_CPU_SH4A)
269static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
270{
271 if (!(cflag & CRTSCTS))
272 __raw_writew(0x0080, SCSPTR2); /* Set RTS = 1 */
273}
274#else
275static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
276{
277 /* Nothing to do */
278}
279#endif
280 435
281#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \ 436static int sci_txfill(struct uart_port *port)
282 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
283 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
284 defined(CONFIG_CPU_SUBTYPE_SH7786)
285static int scif_txfill(struct uart_port *port)
286{
287 return sci_in(port, SCTFDR) & 0xff;
288}
289
290static int scif_txroom(struct uart_port *port)
291{ 437{
292 return SCIF_TXROOM_MAX - scif_txfill(port); 438 struct plat_sci_reg *reg;
293}
294 439
295static int scif_rxfill(struct uart_port *port) 440 reg = sci_getreg(port, SCTFDR);
296{ 441 if (reg->size)
297 return sci_in(port, SCRFDR) & 0xff;
298}
299#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
300static int scif_txfill(struct uart_port *port)
301{
302 if (port->mapbase == 0xffe00000 ||
303 port->mapbase == 0xffe08000)
304 /* SCIF0/1*/
305 return sci_in(port, SCTFDR) & 0xff; 442 return sci_in(port, SCTFDR) & 0xff;
306 else 443
307 /* SCIF2 */ 444 reg = sci_getreg(port, SCFDR);
445 if (reg->size)
308 return sci_in(port, SCFDR) >> 8; 446 return sci_in(port, SCFDR) >> 8;
309}
310 447
311static int scif_txroom(struct uart_port *port) 448 return !(sci_in(port, SCxSR) & SCI_TDRE);
312{
313 if (port->mapbase == 0xffe00000 ||
314 port->mapbase == 0xffe08000)
315 /* SCIF0/1*/
316 return SCIF_TXROOM_MAX - scif_txfill(port);
317 else
318 /* SCIF2 */
319 return SCIF2_TXROOM_MAX - scif_txfill(port);
320} 449}
321 450
322static int scif_rxfill(struct uart_port *port) 451static int sci_txroom(struct uart_port *port)
323{
324 if ((port->mapbase == 0xffe00000) ||
325 (port->mapbase == 0xffe08000)) {
326 /* SCIF0/1*/
327 return sci_in(port, SCRFDR) & 0xff;
328 } else {
329 /* SCIF2 */
330 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK;
331 }
332}
333#elif defined(CONFIG_ARCH_SH7372)
334static int scif_txfill(struct uart_port *port)
335{ 452{
336 if (port->type == PORT_SCIFA) 453 return port->fifosize - sci_txfill(port);
337 return sci_in(port, SCFDR) >> 8;
338 else
339 return sci_in(port, SCTFDR);
340} 454}
341 455
342static int scif_txroom(struct uart_port *port) 456static int sci_rxfill(struct uart_port *port)
343{ 457{
344 return port->fifosize - scif_txfill(port); 458 struct plat_sci_reg *reg;
345}
346 459
347static int scif_rxfill(struct uart_port *port) 460 reg = sci_getreg(port, SCRFDR);
348{ 461 if (reg->size)
349 if (port->type == PORT_SCIFA) 462 return sci_in(port, SCRFDR) & 0xff;
350 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
351 else
352 return sci_in(port, SCRFDR);
353}
354#else
355static int scif_txfill(struct uart_port *port)
356{
357 return sci_in(port, SCFDR) >> 8;
358}
359 463
360static int scif_txroom(struct uart_port *port) 464 reg = sci_getreg(port, SCFDR);
361{ 465 if (reg->size)
362 return SCIF_TXROOM_MAX - scif_txfill(port); 466 return sci_in(port, SCFDR) & ((port->fifosize << 1) - 1);
363}
364 467
365static int scif_rxfill(struct uart_port *port) 468 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
366{
367 return sci_in(port, SCFDR) & SCIF_RFDC_MASK;
368} 469}
369#endif
370 470
371static int sci_txfill(struct uart_port *port) 471/*
472 * SCI helper for checking the state of the muxed port/RXD pins.
473 */
474static inline int sci_rxd_in(struct uart_port *port)
372{ 475{
373 return !(sci_in(port, SCxSR) & SCI_TDRE); 476 struct sci_port *s = to_sci_port(port);
374}
375 477
376static int sci_txroom(struct uart_port *port) 478 if (s->cfg->port_reg <= 0)
377{ 479 return 1;
378 return !sci_txfill(port);
379}
380 480
381static int sci_rxfill(struct uart_port *port) 481 return !!__raw_readb(s->cfg->port_reg);
382{
383 return (sci_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
384} 482}
385 483
386/* ********************************************************************** * 484/* ********************************************************************** *
@@ -406,10 +504,7 @@ static void sci_transmit_chars(struct uart_port *port)
406 return; 504 return;
407 } 505 }
408 506
409 if (port->type == PORT_SCI) 507 count = sci_txroom(port);
410 count = sci_txroom(port);
411 else
412 count = scif_txroom(port);
413 508
414 do { 509 do {
415 unsigned char c; 510 unsigned char c;
@@ -464,13 +559,8 @@ static void sci_receive_chars(struct uart_port *port)
464 return; 559 return;
465 560
466 while (1) { 561 while (1) {
467 if (port->type == PORT_SCI)
468 count = sci_rxfill(port);
469 else
470 count = scif_rxfill(port);
471
472 /* Don't copy more bytes than there is room for in the buffer */ 562 /* Don't copy more bytes than there is room for in the buffer */
473 count = tty_buffer_request_room(tty, count); 563 count = tty_buffer_request_room(tty, sci_rxfill(port));
474 564
475 /* If for any reason we can't copy more data, we're done! */ 565 /* If for any reason we can't copy more data, we're done! */
476 if (count == 0) 566 if (count == 0)
@@ -583,13 +673,19 @@ static int sci_handle_errors(struct uart_port *port)
583 int copied = 0; 673 int copied = 0;
584 unsigned short status = sci_in(port, SCxSR); 674 unsigned short status = sci_in(port, SCxSR);
585 struct tty_struct *tty = port->state->port.tty; 675 struct tty_struct *tty = port->state->port.tty;
676 struct sci_port *s = to_sci_port(port);
586 677
587 if (status & SCxSR_ORER(port)) { 678 /*
588 /* overrun error */ 679 * Handle overruns, if supported.
589 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN)) 680 */
590 copied++; 681 if (s->cfg->overrun_bit != SCIx_NOT_SUPPORTED) {
682 if (status & (1 << s->cfg->overrun_bit)) {
683 /* overrun error */
684 if (tty_insert_flip_char(tty, 0, TTY_OVERRUN))
685 copied++;
591 686
592 dev_notice(port->dev, "overrun error"); 687 dev_notice(port->dev, "overrun error");
688 }
593 } 689 }
594 690
595 if (status & SCxSR_FER(port)) { 691 if (status & SCxSR_FER(port)) {
@@ -637,12 +733,15 @@ static int sci_handle_errors(struct uart_port *port)
637static int sci_handle_fifo_overrun(struct uart_port *port) 733static int sci_handle_fifo_overrun(struct uart_port *port)
638{ 734{
639 struct tty_struct *tty = port->state->port.tty; 735 struct tty_struct *tty = port->state->port.tty;
736 struct sci_port *s = to_sci_port(port);
737 struct plat_sci_reg *reg;
640 int copied = 0; 738 int copied = 0;
641 739
642 if (port->type != PORT_SCIF) 740 reg = sci_getreg(port, SCLSR);
741 if (!reg->size)
643 return 0; 742 return 0;
644 743
645 if ((sci_in(port, SCLSR) & SCIF_ORER) != 0) { 744 if ((sci_in(port, SCLSR) & (1 << s->cfg->overrun_bit))) {
646 sci_out(port, SCLSR, 0); 745 sci_out(port, SCLSR, 0);
647 746
648 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 747 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
@@ -915,7 +1014,7 @@ static void sci_free_irq(struct sci_port *port)
915static unsigned int sci_tx_empty(struct uart_port *port) 1014static unsigned int sci_tx_empty(struct uart_port *port)
916{ 1015{
917 unsigned short status = sci_in(port, SCxSR); 1016 unsigned short status = sci_in(port, SCxSR);
918 unsigned short in_tx_fifo = scif_txfill(port); 1017 unsigned short in_tx_fifo = sci_txfill(port);
919 1018
920 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0; 1019 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
921} 1020}
@@ -1746,6 +1845,9 @@ static int __devinit sci_init_single(struct platform_device *dev,
1746 break; 1845 break;
1747 } 1846 }
1748 1847
1848 if (p->regtype == SCIx_PROBE_REGTYPE)
1849 BUG_ON(sci_probe_regmap(p) != 0);
1850
1749 if (dev) { 1851 if (dev) {
1750 sci_port->iclk = clk_get(&dev->dev, "sci_ick"); 1852 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
1751 if (IS_ERR(sci_port->iclk)) { 1853 if (IS_ERR(sci_port->iclk)) {
@@ -1775,14 +1877,41 @@ static int __devinit sci_init_single(struct platform_device *dev,
1775 sci_port->break_timer.function = sci_break_timer; 1877 sci_port->break_timer.function = sci_break_timer;
1776 init_timer(&sci_port->break_timer); 1878 init_timer(&sci_port->break_timer);
1777 1879
1880 /*
1881 * Establish some sensible defaults for the error detection.
1882 */
1883 if (!p->error_mask)
1884 p->error_mask = (p->type == PORT_SCI) ?
1885 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
1886
1887 /*
1888 * Establish sensible defaults for the overrun detection, unless
1889 * the part has explicitly disabled support for it.
1890 */
1891 if (p->overrun_bit != SCIx_NOT_SUPPORTED) {
1892 if (p->type == PORT_SCI)
1893 p->overrun_bit = 5;
1894 else if (p->scbrr_algo_id == SCBRR_ALGO_4)
1895 p->overrun_bit = 9;
1896 else
1897 p->overrun_bit = 0;
1898
1899 /*
1900 * Make the error mask inclusive of overrun detection, if
1901 * supported.
1902 */
1903 p->error_mask |= (1 << p->overrun_bit);
1904 }
1905
1778 sci_port->cfg = p; 1906 sci_port->cfg = p;
1779 1907
1780 port->mapbase = p->mapbase; 1908 port->mapbase = p->mapbase;
1781 port->type = p->type; 1909 port->type = p->type;
1782 port->flags = p->flags; 1910 port->flags = p->flags;
1911 port->regshift = p->regshift;
1783 1912
1784 /* 1913 /*
1785 * The UART port needs an IRQ value, so we peg this to the TX IRQ 1914 * The UART port needs an IRQ value, so we peg this to the RX IRQ
1786 * for the multi-IRQ ports, which is where we are primarily 1915 * for the multi-IRQ ports, which is where we are primarily
1787 * concerned with the shutdown path synchronization. 1916 * concerned with the shutdown path synchronization.
1788 * 1917 *
@@ -1790,6 +1919,9 @@ static int __devinit sci_init_single(struct platform_device *dev,
1790 */ 1919 */
1791 port->irq = p->irqs[SCIx_RXI_IRQ]; 1920 port->irq = p->irqs[SCIx_RXI_IRQ];
1792 1921
1922 port->serial_in = sci_serial_in;
1923 port->serial_out = sci_serial_out;
1924
1793 if (p->dma_dev) 1925 if (p->dma_dev)
1794 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n", 1926 dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n",
1795 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx); 1927 p->dma_dev, p->dma_slave_tx, p->dma_slave_rx);
@@ -1863,14 +1995,8 @@ static int __devinit serial_console_setup(struct console *co, char *options)
1863 if (options) 1995 if (options)
1864 uart_parse_options(options, &baud, &parity, &bits, &flow); 1996 uart_parse_options(options, &baud, &parity, &bits, &flow);
1865 1997
1866 ret = uart_set_options(port, co, baud, parity, bits, flow);
1867#if defined(__H8300H__) || defined(__H8300S__)
1868 /* disable rx interrupt */
1869 if (ret == 0)
1870 sci_stop_rx(port);
1871#endif
1872 /* TODO: disable clock */ 1998 /* TODO: disable clock */
1873 return ret; 1999 return uart_set_options(port, co, baud, parity, bits, flow);
1874} 2000}
1875 2001
1876static struct console serial_console = { 2002static struct console serial_console = {
diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
index b04d937c9110..e9bed038aa1f 100644
--- a/drivers/tty/serial/sh-sci.h
+++ b/drivers/tty/serial/sh-sci.h
@@ -2,169 +2,14 @@
2#include <linux/io.h> 2#include <linux/io.h>
3#include <linux/gpio.h> 3#include <linux/gpio.h>
4 4
5#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
6#include <asm/regs306x.h>
7#endif
8#if defined(CONFIG_H8S2678)
9#include <asm/regs267x.h>
10#endif
11
12#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
13 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
14 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7709)
16# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
17# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
18#elif defined(CONFIG_CPU_SUBTYPE_SH7705)
19# define SCIF0 0xA4400000
20# define SCIF2 0xA4410000
21# define SCPCR 0xA4000116
22# define SCPDR 0xA4000136
23#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
24 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
25 defined(CONFIG_ARCH_SH73A0) || \
26 defined(CONFIG_ARCH_SH7367) || \
27 defined(CONFIG_ARCH_SH7377) || \
28 defined(CONFIG_ARCH_SH7372)
29# define PORT_PTCR 0xA405011EUL
30# define PORT_PVCR 0xA4050122UL
31# define SCIF_ORER 0x0200 /* overrun error bit */
32#elif defined(CONFIG_SH_RTS7751R2D)
33# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */
34# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
35# define SCIF_ORER 0x0001 /* overrun error bit */
36#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
37 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
38 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
39 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
40 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
41 defined(CONFIG_CPU_SUBTYPE_SH7751R)
42# define SCSPTR1 0xffe0001c /* 8 bit SCI */
43# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
44# define SCIF_ORER 0x0001 /* overrun error bit */
45#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
46# define SCSPTR0 0xfe600024 /* 16 bit SCIF */
47# define SCSPTR1 0xfe610024 /* 16 bit SCIF */
48# define SCSPTR2 0xfe620024 /* 16 bit SCIF */
49# define SCIF_ORER 0x0001 /* overrun error bit */
50#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
51# define SCSPTR0 0xA4400000 /* 16 bit SCIF */
52# define SCIF_ORER 0x0001 /* overrun error bit */
53# define PACR 0xa4050100
54# define PBCR 0xa4050102
55#elif defined(CONFIG_CPU_SUBTYPE_SH7343)
56# define SCSPTR0 0xffe00010 /* 16 bit SCIF */
57#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
58# define PADR 0xA4050120
59# define PSDR 0xA405013e
60# define PWDR 0xA4050166
61# define PSCR 0xA405011E
62# define SCIF_ORER 0x0001 /* overrun error bit */
63#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
64# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
65# define SCSPTR0 SCPDR0
66# define SCIF_ORER 0x0001 /* overrun error bit */
67#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
68# define SCSPTR0 0xa4050160
69# define SCIF_ORER 0x0001 /* overrun error bit */
70#elif defined(CONFIG_CPU_SUBTYPE_SH7724)
71# define SCIF_ORER 0x0001 /* overrun error bit */
72#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
73# define SCSPTR2 0xffe80020 /* 16 bit SCIF */
74# define SCIF_ORER 0x0001 /* overrun error bit */
75#elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
76# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
77#elif defined(CONFIG_H8S2678)
78# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
79#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
80# define SCSPTR0 0xfe4b0020
81# define SCIF_ORER 0x0001
82#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
83# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
84# define SCIF_ORER 0x0001 /* overrun error bit */
85#elif defined(CONFIG_CPU_SUBTYPE_SH7770)
86# define SCSPTR0 0xff923020 /* 16 bit SCIF */
87# define SCIF_ORER 0x0001 /* overrun error bit */
88#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
89# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
90# define SCIF_ORER 0x0001 /* Overrun error bit */
91#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
92 defined(CONFIG_CPU_SUBTYPE_SH7786)
93# define SCSPTR0 0xffea0024 /* 16 bit SCIF */
94# define SCIF_ORER 0x0001 /* Overrun error bit */
95#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \
96 defined(CONFIG_CPU_SUBTYPE_SH7203) || \
97 defined(CONFIG_CPU_SUBTYPE_SH7206) || \
98 defined(CONFIG_CPU_SUBTYPE_SH7263)
99# define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
100#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
101# define SCSPTR0 0xf8400020 /* 16 bit SCIF */
102# define SCIF_ORER 0x0001 /* overrun error bit */
103#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
104# define SCSPTR0 0xffc30020 /* 16 bit SCIF */
105# define SCIF_ORER 0x0001 /* Overrun error bit */
106#else
107# error CPU subtype not defined
108#endif
109
110/* SCxSR SCI */
111#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
112#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
113#define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
114#define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
115#define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
116#define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
117/* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
118/* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
119
120#define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
121
122/* SCxSR SCIF */
123#define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
124#define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
125#define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
126#define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
127#define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
128#define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
129#define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
130#define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
131
132#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
133 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
134 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
135 defined(CONFIG_ARCH_SH73A0) || \
136 defined(CONFIG_ARCH_SH7367) || \
137 defined(CONFIG_ARCH_SH7377) || \
138 defined(CONFIG_ARCH_SH7372)
139# define SCIF_ORER 0x0200
140# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
141# define SCIF_RFDC_MASK 0x007f
142# define SCIF_TXROOM_MAX 64
143#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
144# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK )
145# define SCIF_RFDC_MASK 0x007f
146# define SCIF_TXROOM_MAX 64
147/* SH7763 SCIF2 support */
148# define SCIF2_RFDC_MASK 0x001f
149# define SCIF2_TXROOM_MAX 16
150#else
151# define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
152# define SCIF_RFDC_MASK 0x001f
153# define SCIF_TXROOM_MAX 16
154#endif
155
156#ifndef SCIF_ORER
157#define SCIF_ORER 0x0000
158#endif
159
160#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND) 5#define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
161#define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
162#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF) 6#define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
163#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE) 7#define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
164#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER) 8#define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
165#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER) 9#define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
166#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK) 10#define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
167#define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : SCIF_ORER) 11
12#define SCxSR_ERRORS(port) (to_sci_port(port)->cfg->error_mask)
168 13
169#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 14#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
170 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 15 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
@@ -191,278 +36,3 @@
191 36
192#define SCI_MAJOR 204 37#define SCI_MAJOR 204
193#define SCI_MINOR_START 8 38#define SCI_MINOR_START 8
194
195#define SCI_IN(size, offset) \
196 if ((size) == 8) { \
197 return ioread8(port->membase + (offset)); \
198 } else { \
199 return ioread16(port->membase + (offset)); \
200 }
201#define SCI_OUT(size, offset, value) \
202 if ((size) == 8) { \
203 iowrite8(value, port->membase + (offset)); \
204 } else if ((size) == 16) { \
205 iowrite16(value, port->membase + (offset)); \
206 }
207
208#define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
209 static inline unsigned int sci_##name##_in(struct uart_port *port) \
210 { \
211 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
212 SCI_IN(scif_size, scif_offset) \
213 } else { /* PORT_SCI or PORT_SCIFA */ \
214 SCI_IN(sci_size, sci_offset); \
215 } \
216 } \
217 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
218 { \
219 if (port->type == PORT_SCIF || port->type == PORT_SCIFB) { \
220 SCI_OUT(scif_size, scif_offset, value) \
221 } else { /* PORT_SCI or PORT_SCIFA */ \
222 SCI_OUT(sci_size, sci_offset, value); \
223 } \
224 }
225
226#ifdef CONFIG_H8300
227/* h8300 don't have SCIF */
228#define CPU_SCIF_FNS(name) \
229 static inline unsigned int sci_##name##_in(struct uart_port *port) \
230 { \
231 return 0; \
232 } \
233 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
234 { \
235 }
236#else
237#define CPU_SCIF_FNS(name, scif_offset, scif_size) \
238 static inline unsigned int sci_##name##_in(struct uart_port *port) \
239 { \
240 SCI_IN(scif_size, scif_offset); \
241 } \
242 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
243 { \
244 SCI_OUT(scif_size, scif_offset, value); \
245 }
246#endif
247
248#define CPU_SCI_FNS(name, sci_offset, sci_size) \
249 static inline unsigned int sci_##name##_in(struct uart_port* port) \
250 { \
251 SCI_IN(sci_size, sci_offset); \
252 } \
253 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
254 { \
255 SCI_OUT(sci_size, sci_offset, value); \
256 }
257
258#if defined(CONFIG_CPU_SH3) || \
259 defined(CONFIG_ARCH_SH73A0) || \
260 defined(CONFIG_ARCH_SH7367) || \
261 defined(CONFIG_ARCH_SH7377) || \
262 defined(CONFIG_ARCH_SH7372)
263#if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
264#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
265 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
266 h8_sci_offset, h8_sci_size) \
267 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
268#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
269 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
270#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
271 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
272 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
273 defined(CONFIG_ARCH_SH7367)
274#define SCIF_FNS(name, scif_offset, scif_size) \
275 CPU_SCIF_FNS(name, scif_offset, scif_size)
276#elif defined(CONFIG_ARCH_SH7377) || \
277 defined(CONFIG_ARCH_SH7372) || \
278 defined(CONFIG_ARCH_SH73A0)
279#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \
280 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size)
281#define SCIF_FNS(name, scif_offset, scif_size) \
282 CPU_SCIF_FNS(name, scif_offset, scif_size)
283#else
284#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
285 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
286 h8_sci_offset, h8_sci_size) \
287 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
288#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
289 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
290#endif
291#elif defined(__H8300H__) || defined(__H8300S__)
292#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
293 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
294 h8_sci_offset, h8_sci_size) \
295 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
296#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
297 CPU_SCIF_FNS(name)
298#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
299 defined(CONFIG_CPU_SUBTYPE_SH7724)
300 #define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size) \
301 CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scif_offset, sh4_scif_size)
302 #define SCIF_FNS(name, sh4_scif_offset, sh4_scif_size) \
303 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
304#else
305#define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
306 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
307 h8_sci_offset, h8_sci_size) \
308 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
309#define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
310 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
311#endif
312
313#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
314 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
315 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
316 defined(CONFIG_ARCH_SH7367)
317
318SCIF_FNS(SCSMR, 0x00, 16)
319SCIF_FNS(SCBRR, 0x04, 8)
320SCIF_FNS(SCSCR, 0x08, 16)
321SCIF_FNS(SCxSR, 0x14, 16)
322SCIF_FNS(SCFCR, 0x18, 16)
323SCIF_FNS(SCFDR, 0x1c, 16)
324SCIF_FNS(SCxTDR, 0x20, 8)
325SCIF_FNS(SCxRDR, 0x24, 8)
326SCIF_FNS(SCLSR, 0x00, 0)
327#elif defined(CONFIG_ARCH_SH7377) || \
328 defined(CONFIG_ARCH_SH7372) || \
329 defined(CONFIG_ARCH_SH73A0)
330SCIF_FNS(SCSMR, 0x00, 16)
331SCIF_FNS(SCBRR, 0x04, 8)
332SCIF_FNS(SCSCR, 0x08, 16)
333SCIF_FNS(SCTDSR, 0x0c, 16)
334SCIF_FNS(SCFER, 0x10, 16)
335SCIF_FNS(SCxSR, 0x14, 16)
336SCIF_FNS(SCFCR, 0x18, 16)
337SCIF_FNS(SCFDR, 0x1c, 16)
338SCIF_FNS(SCTFDR, 0x38, 16)
339SCIF_FNS(SCRFDR, 0x3c, 16)
340SCIx_FNS(SCxTDR, 0x20, 8, 0x40, 8)
341SCIx_FNS(SCxRDR, 0x24, 8, 0x60, 8)
342SCIF_FNS(SCLSR, 0x00, 0)
343#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\
344 defined(CONFIG_CPU_SUBTYPE_SH7724)
345SCIx_FNS(SCSMR, 0x00, 16, 0x00, 16)
346SCIx_FNS(SCBRR, 0x04, 8, 0x04, 8)
347SCIx_FNS(SCSCR, 0x08, 16, 0x08, 16)
348SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8)
349SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16)
350SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8)
351SCIx_FNS(SCSPTR, 0, 0, 0, 0)
352SCIF_FNS(SCFCR, 0x18, 16)
353SCIF_FNS(SCFDR, 0x1c, 16)
354SCIF_FNS(SCLSR, 0x24, 16)
355#else
356/* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
357/* name off sz off sz off sz off sz off sz*/
358SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
359SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
360SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
361SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
362SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
363SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
364SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
365#if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
366 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
367 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
368 defined(CONFIG_CPU_SUBTYPE_SH7786)
369SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
370SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
371SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
372SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
373SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
374#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
375SCIF_FNS(SCFDR, 0, 0, 0x1C, 16)
376SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
377SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
378SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
379SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
380#else
381SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
382#if defined(CONFIG_CPU_SUBTYPE_SH7722)
383SCIF_FNS(SCSPTR, 0, 0, 0, 0)
384#else
385SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
386#endif
387SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
388#endif
389#endif
390#define sci_in(port, reg) sci_##reg##_in(port)
391#define sci_out(port, reg, value) sci_##reg##_out(port, value)
392
393/* H8/300 series SCI pins assignment */
394#if defined(__H8300H__) || defined(__H8300S__)
395static const struct __attribute__((packed)) {
396 int port; /* GPIO port no */
397 unsigned short rx,tx; /* GPIO bit no */
398} h8300_sci_pins[] = {
399#if defined(CONFIG_H83007) || defined(CONFIG_H83068)
400 { /* SCI0 */
401 .port = H8300_GPIO_P9,
402 .rx = H8300_GPIO_B2,
403 .tx = H8300_GPIO_B0,
404 },
405 { /* SCI1 */
406 .port = H8300_GPIO_P9,
407 .rx = H8300_GPIO_B3,
408 .tx = H8300_GPIO_B1,
409 },
410 { /* SCI2 */
411 .port = H8300_GPIO_PB,
412 .rx = H8300_GPIO_B7,
413 .tx = H8300_GPIO_B6,
414 }
415#elif defined(CONFIG_H8S2678)
416 { /* SCI0 */
417 .port = H8300_GPIO_P3,
418 .rx = H8300_GPIO_B2,
419 .tx = H8300_GPIO_B0,
420 },
421 { /* SCI1 */
422 .port = H8300_GPIO_P3,
423 .rx = H8300_GPIO_B3,
424 .tx = H8300_GPIO_B1,
425 },
426 { /* SCI2 */
427 .port = H8300_GPIO_P5,
428 .rx = H8300_GPIO_B1,
429 .tx = H8300_GPIO_B0,
430 }
431#endif
432};
433#endif
434
435#if defined(CONFIG_CPU_SUBTYPE_SH7706) || \
436 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
437 defined(CONFIG_CPU_SUBTYPE_SH7708) || \
438 defined(CONFIG_CPU_SUBTYPE_SH7709)
439static inline int sci_rxd_in(struct uart_port *port)
440{
441 if (port->mapbase == 0xfffffe80)
442 return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */
443 return 1;
444}
445#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
446 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
447 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
448 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
449 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
450 defined(CONFIG_CPU_SUBTYPE_SH7091)
451static inline int sci_rxd_in(struct uart_port *port)
452{
453 if (port->mapbase == 0xffe00000)
454 return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
455 return 1;
456}
457#elif defined(__H8300H__) || defined(__H8300S__)
458static inline int sci_rxd_in(struct uart_port *port)
459{
460 int ch = (port->mapbase - SMR0) >> 3;
461 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
462}
463#else /* default case for non-SCI processors */
464static inline int sci_rxd_in(struct uart_port *port)
465{
466 return 1;
467}
468#endif
diff --git a/include/linux/serial_sci.h b/include/linux/serial_sci.h
index a2afc9fbe186..4ca130a90ea5 100644
--- a/include/linux/serial_sci.h
+++ b/include/linux/serial_sci.h
@@ -8,6 +8,8 @@
8 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts) 8 * Generic header for SuperH SCI(F) (used by sh/sh64/h8300 and related parts)
9 */ 9 */
10 10
11#define SCIx_NOT_SUPPORTED (-1)
12
11enum { 13enum {
12 SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */ 14 SCBRR_ALGO_1, /* ((clk + 16 * bps) / (16 * bps) - 1) */
13 SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */ 15 SCBRR_ALGO_2, /* ((clk + 16 * bps) / (32 * bps) - 1) */
@@ -25,6 +27,28 @@ enum {
25#define SCSCR_CKE1 (1 << 1) 27#define SCSCR_CKE1 (1 << 1)
26#define SCSCR_CKE0 (1 << 0) 28#define SCSCR_CKE0 (1 << 0)
27 29
30/* SCxSR SCI */
31#define SCI_TDRE 0x80
32#define SCI_RDRF 0x40
33#define SCI_ORER 0x20
34#define SCI_FER 0x10
35#define SCI_PER 0x08
36#define SCI_TEND 0x04
37
38#define SCI_DEFAULT_ERROR_MASK (SCI_PER | SCI_FER)
39
40/* SCxSR SCIF */
41#define SCIF_ER 0x0080
42#define SCIF_TEND 0x0040
43#define SCIF_TDFE 0x0020
44#define SCIF_BRK 0x0010
45#define SCIF_FER 0x0008
46#define SCIF_PER 0x0004
47#define SCIF_RDF 0x0002
48#define SCIF_DR 0x0001
49
50#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
51
28/* Offsets into the sci_port->irqs array */ 52/* Offsets into the sci_port->irqs array */
29enum { 53enum {
30 SCIx_ERI_IRQ, 54 SCIx_ERI_IRQ,
@@ -34,6 +58,22 @@ enum {
34 SCIx_NR_IRQS, 58 SCIx_NR_IRQS,
35}; 59};
36 60
61enum {
62 SCIx_PROBE_REGTYPE,
63
64 SCIx_SCI_REGTYPE,
65 SCIx_IRDA_REGTYPE,
66 SCIx_SCIFA_REGTYPE,
67 SCIx_SCIFB_REGTYPE,
68 SCIx_SH3_SCIF_REGTYPE,
69 SCIx_SH4_SCIF_REGTYPE,
70 SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE,
71 SCIx_SH4_SCIF_FIFODATA_REGTYPE,
72 SCIx_SH7705_SCIF_REGTYPE,
73
74 SCIx_NR_REGTYPES,
75};
76
37#define SCIx_IRQ_MUXED(irq) \ 77#define SCIx_IRQ_MUXED(irq) \
38{ \ 78{ \
39 [SCIx_ERI_IRQ] = (irq), \ 79 [SCIx_ERI_IRQ] = (irq), \
@@ -42,8 +82,24 @@ enum {
42 [SCIx_BRI_IRQ] = (irq), \ 82 [SCIx_BRI_IRQ] = (irq), \
43} 83}
44 84
85/*
86 * SCI register subset common for all port types.
87 * Not all registers will exist on all parts.
88 */
89enum {
90 SCSMR, SCBRR, SCSCR, SCxSR,
91 SCFCR, SCFDR, SCxTDR, SCxRDR,
92 SCLSR, SCTFDR, SCRFDR, SCSPTR,
93
94 SCIx_NR_REGS,
95};
96
45struct device; 97struct device;
46 98
99struct plat_sci_port_ops {
100 void (*init_pins)(struct uart_port *, unsigned int cflag);
101};
102
47/* 103/*
48 * Platform device specific platform_data struct 104 * Platform device specific platform_data struct
49 */ 105 */
@@ -56,6 +112,18 @@ struct plat_sci_port {
56 unsigned int scbrr_algo_id; /* SCBRR calculation algo */ 112 unsigned int scbrr_algo_id; /* SCBRR calculation algo */
57 unsigned int scscr; /* SCSCR initialization */ 113 unsigned int scscr; /* SCSCR initialization */
58 114
115 /*
116 * Platform overrides if necessary, defaults otherwise.
117 */
118 int overrun_bit;
119 unsigned int error_mask;
120
121 int port_reg;
122 unsigned char regshift;
123 unsigned char regtype;
124
125 struct plat_sci_port_ops *ops;
126
59 struct device *dma_dev; 127 struct device *dma_dev;
60 128
61 unsigned int dma_slave_tx; 129 unsigned int dma_slave_tx;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-20 22:05:09 -0500