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authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-01-22 14:31:11 -0500
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-01-22 14:31:11 -0500
commit19e805cb040a81dcfbcf2aa8dbe5d9454c5faf2d (patch)
treee5f75873ebe7a019ce6b2bd493031d8fcf7fcf00
parentab1127823b757ec945a048c3385eb1f99a459823 (diff)
parent7939aae0c08412138a827e0af6f16fc19c346353 (diff)
Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6
* 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6: sis190: failure to set the MAC address from EEPROM Fix phy_read/write redefinition errors in ucc_geth_phy.c Update ucc_geth.c for new workqueue structure myri10ge: update driver version to 1.2.0 myri10ge: check that we can get an irq myri10ge: make wc_fifo usage load-time tunable 8139cp: Don't blindly enable interrupts [PATCH] bcm43xx: Fix failure to deliver PCI-E interrupts
-rw-r--r--drivers/net/8139cp.c7
-rw-r--r--drivers/net/myri10ge/myri10ge.c23
-rw-r--r--drivers/net/sis190.c2
-rw-r--r--drivers/net/ucc_geth.c12
-rw-r--r--drivers/net/ucc_geth_phy.c134
-rw-r--r--drivers/net/wireless/bcm43xx/bcm43xx_main.c11
6 files changed, 103 insertions, 86 deletions
diff --git a/drivers/net/8139cp.c b/drivers/net/8139cp.c
index e2cb19b582a1..6f93a765e564 100644
--- a/drivers/net/8139cp.c
+++ b/drivers/net/8139cp.c
@@ -765,17 +765,18 @@ static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
765 struct cp_private *cp = netdev_priv(dev); 765 struct cp_private *cp = netdev_priv(dev);
766 unsigned entry; 766 unsigned entry;
767 u32 eor, flags; 767 u32 eor, flags;
768 unsigned long intr_flags;
768#if CP_VLAN_TAG_USED 769#if CP_VLAN_TAG_USED
769 u32 vlan_tag = 0; 770 u32 vlan_tag = 0;
770#endif 771#endif
771 int mss = 0; 772 int mss = 0;
772 773
773 spin_lock_irq(&cp->lock); 774 spin_lock_irqsave(&cp->lock, intr_flags);
774 775
775 /* This is a hard error, log it. */ 776 /* This is a hard error, log it. */
776 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) { 777 if (TX_BUFFS_AVAIL(cp) <= (skb_shinfo(skb)->nr_frags + 1)) {
777 netif_stop_queue(dev); 778 netif_stop_queue(dev);
778 spin_unlock_irq(&cp->lock); 779 spin_unlock_irqrestore(&cp->lock, intr_flags);
779 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n", 780 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
780 dev->name); 781 dev->name);
781 return 1; 782 return 1;
@@ -908,7 +909,7 @@ static int cp_start_xmit (struct sk_buff *skb, struct net_device *dev)
908 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1)) 909 if (TX_BUFFS_AVAIL(cp) <= (MAX_SKB_FRAGS + 1))
909 netif_stop_queue(dev); 910 netif_stop_queue(dev);
910 911
911 spin_unlock_irq(&cp->lock); 912 spin_unlock_irqrestore(&cp->lock, intr_flags);
912 913
913 cpw8(TxPoll, NormalTxPoll); 914 cpw8(TxPoll, NormalTxPoll);
914 dev->trans_start = jiffies; 915 dev->trans_start = jiffies;
diff --git a/drivers/net/myri10ge/myri10ge.c b/drivers/net/myri10ge/myri10ge.c
index 07cf574197e5..61cbd4a60446 100644
--- a/drivers/net/myri10ge/myri10ge.c
+++ b/drivers/net/myri10ge/myri10ge.c
@@ -71,7 +71,7 @@
71#include "myri10ge_mcp.h" 71#include "myri10ge_mcp.h"
72#include "myri10ge_mcp_gen_header.h" 72#include "myri10ge_mcp_gen_header.h"
73 73
74#define MYRI10GE_VERSION_STR "1.1.0" 74#define MYRI10GE_VERSION_STR "1.2.0"
75 75
76MODULE_DESCRIPTION("Myricom 10G driver (10GbE)"); 76MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
77MODULE_AUTHOR("Maintainer: help@myri.com"); 77MODULE_AUTHOR("Maintainer: help@myri.com");
@@ -274,6 +274,10 @@ static int myri10ge_fill_thresh = 256;
274module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR); 274module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
275MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n"); 275MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed\n");
276 276
277static int myri10ge_wcfifo = 1;
278module_param(myri10ge_wcfifo, int, S_IRUGO);
279MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled\n");
280
277#define MYRI10GE_FW_OFFSET 1024*1024 281#define MYRI10GE_FW_OFFSET 1024*1024
278#define MYRI10GE_HIGHPART_TO_U32(X) \ 282#define MYRI10GE_HIGHPART_TO_U32(X) \
279(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0) 283(sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
@@ -1714,7 +1718,7 @@ static int myri10ge_open(struct net_device *dev)
1714 goto abort_with_irq; 1718 goto abort_with_irq;
1715 } 1719 }
1716 1720
1717 if (mgp->mtrr >= 0) { 1721 if (myri10ge_wcfifo && mgp->mtrr >= 0) {
1718 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4; 1722 mgp->tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1719 mgp->rx_small.wc_fifo = 1723 mgp->rx_small.wc_fifo =
1720 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL; 1724 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
@@ -2878,7 +2882,6 @@ static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2878 netdev->hard_start_xmit = myri10ge_xmit; 2882 netdev->hard_start_xmit = myri10ge_xmit;
2879 netdev->get_stats = myri10ge_get_stats; 2883 netdev->get_stats = myri10ge_get_stats;
2880 netdev->base_addr = mgp->iomem_base; 2884 netdev->base_addr = mgp->iomem_base;
2881 netdev->irq = pdev->irq;
2882 netdev->change_mtu = myri10ge_change_mtu; 2885 netdev->change_mtu = myri10ge_change_mtu;
2883 netdev->set_multicast_list = myri10ge_set_multicast_list; 2886 netdev->set_multicast_list = myri10ge_set_multicast_list;
2884 netdev->set_mac_address = myri10ge_set_mac_address; 2887 netdev->set_mac_address = myri10ge_set_mac_address;
@@ -2888,6 +2891,15 @@ static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2888 netdev->poll = myri10ge_poll; 2891 netdev->poll = myri10ge_poll;
2889 netdev->weight = myri10ge_napi_weight; 2892 netdev->weight = myri10ge_napi_weight;
2890 2893
2894 /* make sure we can get an irq, and that MSI can be
2895 * setup (if available). Also ensure netdev->irq
2896 * is set to correct value if MSI is enabled */
2897 status = myri10ge_request_irq(mgp);
2898 if (status != 0)
2899 goto abort_with_firmware;
2900 netdev->irq = pdev->irq;
2901 myri10ge_free_irq(mgp);
2902
2891 /* Save configuration space to be restored if the 2903 /* Save configuration space to be restored if the
2892 * nic resets due to a parity error */ 2904 * nic resets due to a parity error */
2893 pci_save_state(pdev); 2905 pci_save_state(pdev);
@@ -2903,8 +2915,9 @@ static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2903 dev_err(&pdev->dev, "register_netdev failed: %d\n", status); 2915 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
2904 goto abort_with_state; 2916 goto abort_with_state;
2905 } 2917 }
2906 dev_info(dev, "%d, tx bndry %d, fw %s, WC %s\n", 2918 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
2907 pdev->irq, mgp->tx.boundary, mgp->fw_name, 2919 (mgp->msi_enabled ? "MSI" : "xPIC"),
2920 netdev->irq, mgp->tx.boundary, mgp->fw_name,
2908 (mgp->mtrr >= 0 ? "Enabled" : "Disabled")); 2921 (mgp->mtrr >= 0 ? "Enabled" : "Disabled"));
2909 2922
2910 return 0; 2923 return 0;
diff --git a/drivers/net/sis190.c b/drivers/net/sis190.c
index b70ed79d4121..45d91b159100 100644
--- a/drivers/net/sis190.c
+++ b/drivers/net/sis190.c
@@ -1562,7 +1562,7 @@ static int __devinit sis190_get_mac_addr_from_eeprom(struct pci_dev *pdev,
1562 for (i = 0; i < MAC_ADDR_LEN / 2; i++) { 1562 for (i = 0; i < MAC_ADDR_LEN / 2; i++) {
1563 __le16 w = sis190_read_eeprom(ioaddr, EEPROMMACAddr + i); 1563 __le16 w = sis190_read_eeprom(ioaddr, EEPROMMACAddr + i);
1564 1564
1565 ((u16 *)dev->dev_addr)[0] = le16_to_cpu(w); 1565 ((u16 *)dev->dev_addr)[i] = le16_to_cpu(w);
1566 } 1566 }
1567 1567
1568 sis190_set_rgmii(tp, sis190_read_eeprom(ioaddr, EEPROMInfo)); 1568 sis190_set_rgmii(tp, sis190_read_eeprom(ioaddr, EEPROMInfo));
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index 8243150f5b05..7e4b23c7c1ba 100644
--- a/drivers/net/ucc_geth.c
+++ b/drivers/net/ucc_geth.c
@@ -29,6 +29,7 @@
29#include <linux/fsl_devices.h> 29#include <linux/fsl_devices.h>
30#include <linux/ethtool.h> 30#include <linux/ethtool.h>
31#include <linux/mii.h> 31#include <linux/mii.h>
32#include <linux/workqueue.h>
32 33
33#include <asm/of_platform.h> 34#include <asm/of_platform.h>
34#include <asm/uaccess.h> 35#include <asm/uaccess.h>
@@ -472,7 +473,7 @@ static void put_enet_addr_container(struct enet_addr_container *enet_addr_cont)
472 kfree(enet_addr_cont); 473 kfree(enet_addr_cont);
473} 474}
474 475
475static int set_mac_addr(__be16 __iomem *reg, u8 *mac) 476static void set_mac_addr(__be16 __iomem *reg, u8 *mac)
476{ 477{
477 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]); 478 out_be16(&reg[0], ((u16)mac[5] << 8) | mac[4]);
478 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]); 479 out_be16(&reg[1], ((u16)mac[3] << 8) | mac[2]);
@@ -3920,10 +3921,11 @@ static irqreturn_t phy_interrupt(int irq, void *dev_id)
3920} 3921}
3921 3922
3922/* Scheduled by the phy_interrupt/timer to handle PHY changes */ 3923/* Scheduled by the phy_interrupt/timer to handle PHY changes */
3923static void ugeth_phy_change(void *data) 3924static void ugeth_phy_change(struct work_struct *work)
3924{ 3925{
3925 struct net_device *dev = (struct net_device *)data; 3926 struct ucc_geth_private *ugeth =
3926 struct ucc_geth_private *ugeth = netdev_priv(dev); 3927 container_of(work, struct ucc_geth_private, tq);
3928 struct net_device *dev = ugeth->dev;
3927 struct ucc_geth *ug_regs; 3929 struct ucc_geth *ug_regs;
3928 int result = 0; 3930 int result = 0;
3929 3931
@@ -4080,7 +4082,7 @@ static int ucc_geth_open(struct net_device *dev)
4080#endif /* CONFIG_UGETH_NAPI */ 4082#endif /* CONFIG_UGETH_NAPI */
4081 4083
4082 /* Set up the PHY change work queue */ 4084 /* Set up the PHY change work queue */
4083 INIT_WORK(&ugeth->tq, ugeth_phy_change, dev); 4085 INIT_WORK(&ugeth->tq, ugeth_phy_change);
4084 4086
4085 init_timer(&ugeth->phy_info_timer); 4087 init_timer(&ugeth->phy_info_timer);
4086 ugeth->phy_info_timer.function = &ugeth_phy_startup_timer; 4088 ugeth->phy_info_timer.function = &ugeth_phy_startup_timer;
diff --git a/drivers/net/ucc_geth_phy.c b/drivers/net/ucc_geth_phy.c
index 5360ec05eaa3..3c86592ce03c 100644
--- a/drivers/net/ucc_geth_phy.c
+++ b/drivers/net/ucc_geth_phy.c
@@ -68,8 +68,31 @@ static int gbit_config_aneg(struct ugeth_mii_info *mii_info);
68static int genmii_config_aneg(struct ugeth_mii_info *mii_info); 68static int genmii_config_aneg(struct ugeth_mii_info *mii_info);
69static int genmii_update_link(struct ugeth_mii_info *mii_info); 69static int genmii_update_link(struct ugeth_mii_info *mii_info);
70static int genmii_read_status(struct ugeth_mii_info *mii_info); 70static int genmii_read_status(struct ugeth_mii_info *mii_info);
71u16 phy_read(struct ugeth_mii_info *mii_info, u16 regnum); 71
72void phy_write(struct ugeth_mii_info *mii_info, u16 regnum, u16 val); 72static u16 ucc_geth_phy_read(struct ugeth_mii_info *mii_info, u16 regnum)
73{
74 u16 retval;
75 unsigned long flags;
76
77 ugphy_vdbg("%s: IN", __FUNCTION__);
78
79 spin_lock_irqsave(&mii_info->mdio_lock, flags);
80 retval = mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
81 spin_unlock_irqrestore(&mii_info->mdio_lock, flags);
82
83 return retval;
84}
85
86static void ucc_geth_phy_write(struct ugeth_mii_info *mii_info, u16 regnum, u16 val)
87{
88 unsigned long flags;
89
90 ugphy_vdbg("%s: IN", __FUNCTION__);
91
92 spin_lock_irqsave(&mii_info->mdio_lock, flags);
93 mii_info->mdio_write(mii_info->dev, mii_info->mii_id, regnum, val);
94 spin_unlock_irqrestore(&mii_info->mdio_lock, flags);
95}
73 96
74/* Write value to the PHY for this device to the register at regnum, */ 97/* Write value to the PHY for this device to the register at regnum, */
75/* waiting until the write is done before it returns. All PHY */ 98/* waiting until the write is done before it returns. All PHY */
@@ -184,7 +207,7 @@ static void config_genmii_advert(struct ugeth_mii_info *mii_info)
184 advertise = mii_info->advertising; 207 advertise = mii_info->advertising;
185 208
186 /* Setup standard advertisement */ 209 /* Setup standard advertisement */
187 adv = phy_read(mii_info, MII_ADVERTISE); 210 adv = ucc_geth_phy_read(mii_info, MII_ADVERTISE);
188 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); 211 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
189 if (advertise & ADVERTISED_10baseT_Half) 212 if (advertise & ADVERTISED_10baseT_Half)
190 adv |= ADVERTISE_10HALF; 213 adv |= ADVERTISE_10HALF;
@@ -194,7 +217,7 @@ static void config_genmii_advert(struct ugeth_mii_info *mii_info)
194 adv |= ADVERTISE_100HALF; 217 adv |= ADVERTISE_100HALF;
195 if (advertise & ADVERTISED_100baseT_Full) 218 if (advertise & ADVERTISED_100baseT_Full)
196 adv |= ADVERTISE_100FULL; 219 adv |= ADVERTISE_100FULL;
197 phy_write(mii_info, MII_ADVERTISE, adv); 220 ucc_geth_phy_write(mii_info, MII_ADVERTISE, adv);
198} 221}
199 222
200static void genmii_setup_forced(struct ugeth_mii_info *mii_info) 223static void genmii_setup_forced(struct ugeth_mii_info *mii_info)
@@ -204,7 +227,7 @@ static void genmii_setup_forced(struct ugeth_mii_info *mii_info)
204 227
205 ugphy_vdbg("%s: IN", __FUNCTION__); 228 ugphy_vdbg("%s: IN", __FUNCTION__);
206 229
207 ctrl = phy_read(mii_info, MII_BMCR); 230 ctrl = ucc_geth_phy_read(mii_info, MII_BMCR);
208 231
209 ctrl &= 232 ctrl &=
210 ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE); 233 ~(BMCR_FULLDPLX | BMCR_SPEED100 | BMCR_SPEED1000 | BMCR_ANENABLE);
@@ -234,7 +257,7 @@ static void genmii_setup_forced(struct ugeth_mii_info *mii_info)
234 break; 257 break;
235 } 258 }
236 259
237 phy_write(mii_info, MII_BMCR, ctrl); 260 ucc_geth_phy_write(mii_info, MII_BMCR, ctrl);
238} 261}
239 262
240/* Enable and Restart Autonegotiation */ 263/* Enable and Restart Autonegotiation */
@@ -244,9 +267,9 @@ static void genmii_restart_aneg(struct ugeth_mii_info *mii_info)
244 267
245 ugphy_vdbg("%s: IN", __FUNCTION__); 268 ugphy_vdbg("%s: IN", __FUNCTION__);
246 269
247 ctl = phy_read(mii_info, MII_BMCR); 270 ctl = ucc_geth_phy_read(mii_info, MII_BMCR);
248 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); 271 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
249 phy_write(mii_info, MII_BMCR, ctl); 272 ucc_geth_phy_write(mii_info, MII_BMCR, ctl);
250} 273}
251 274
252static int gbit_config_aneg(struct ugeth_mii_info *mii_info) 275static int gbit_config_aneg(struct ugeth_mii_info *mii_info)
@@ -261,14 +284,14 @@ static int gbit_config_aneg(struct ugeth_mii_info *mii_info)
261 config_genmii_advert(mii_info); 284 config_genmii_advert(mii_info);
262 advertise = mii_info->advertising; 285 advertise = mii_info->advertising;
263 286
264 adv = phy_read(mii_info, MII_1000BASETCONTROL); 287 adv = ucc_geth_phy_read(mii_info, MII_1000BASETCONTROL);
265 adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP | 288 adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
266 MII_1000BASETCONTROL_HALFDUPLEXCAP); 289 MII_1000BASETCONTROL_HALFDUPLEXCAP);
267 if (advertise & SUPPORTED_1000baseT_Half) 290 if (advertise & SUPPORTED_1000baseT_Half)
268 adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP; 291 adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
269 if (advertise & SUPPORTED_1000baseT_Full) 292 if (advertise & SUPPORTED_1000baseT_Full)
270 adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP; 293 adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
271 phy_write(mii_info, MII_1000BASETCONTROL, adv); 294 ucc_geth_phy_write(mii_info, MII_1000BASETCONTROL, adv);
272 295
273 /* Start/Restart aneg */ 296 /* Start/Restart aneg */
274 genmii_restart_aneg(mii_info); 297 genmii_restart_aneg(mii_info);
@@ -298,10 +321,10 @@ static int genmii_update_link(struct ugeth_mii_info *mii_info)
298 ugphy_vdbg("%s: IN", __FUNCTION__); 321 ugphy_vdbg("%s: IN", __FUNCTION__);
299 322
300 /* Do a fake read */ 323 /* Do a fake read */
301 phy_read(mii_info, MII_BMSR); 324 ucc_geth_phy_read(mii_info, MII_BMSR);
302 325
303 /* Read link and autonegotiation status */ 326 /* Read link and autonegotiation status */
304 status = phy_read(mii_info, MII_BMSR); 327 status = ucc_geth_phy_read(mii_info, MII_BMSR);
305 if ((status & BMSR_LSTATUS) == 0) 328 if ((status & BMSR_LSTATUS) == 0)
306 mii_info->link = 0; 329 mii_info->link = 0;
307 else 330 else
@@ -329,7 +352,7 @@ static int genmii_read_status(struct ugeth_mii_info *mii_info)
329 return err; 352 return err;
330 353
331 if (mii_info->autoneg) { 354 if (mii_info->autoneg) {
332 status = phy_read(mii_info, MII_LPA); 355 status = ucc_geth_phy_read(mii_info, MII_LPA);
333 356
334 if (status & (LPA_10FULL | LPA_100FULL)) 357 if (status & (LPA_10FULL | LPA_100FULL))
335 mii_info->duplex = DUPLEX_FULL; 358 mii_info->duplex = DUPLEX_FULL;
@@ -352,9 +375,9 @@ static int marvell_init(struct ugeth_mii_info *mii_info)
352{ 375{
353 ugphy_vdbg("%s: IN", __FUNCTION__); 376 ugphy_vdbg("%s: IN", __FUNCTION__);
354 377
355 phy_write(mii_info, 0x14, 0x0cd2); 378 ucc_geth_phy_write(mii_info, 0x14, 0x0cd2);
356 phy_write(mii_info, MII_BMCR, 379 ucc_geth_phy_write(mii_info, MII_BMCR,
357 phy_read(mii_info, MII_BMCR) | BMCR_RESET); 380 ucc_geth_phy_read(mii_info, MII_BMCR) | BMCR_RESET);
358 msleep(4000); 381 msleep(4000);
359 382
360 return 0; 383 return 0;
@@ -367,13 +390,13 @@ static int marvell_config_aneg(struct ugeth_mii_info *mii_info)
367 /* The Marvell PHY has an errata which requires 390 /* The Marvell PHY has an errata which requires
368 * that certain registers get written in order 391 * that certain registers get written in order
369 * to restart autonegotiation */ 392 * to restart autonegotiation */
370 phy_write(mii_info, MII_BMCR, BMCR_RESET); 393 ucc_geth_phy_write(mii_info, MII_BMCR, BMCR_RESET);
371 394
372 phy_write(mii_info, 0x1d, 0x1f); 395 ucc_geth_phy_write(mii_info, 0x1d, 0x1f);
373 phy_write(mii_info, 0x1e, 0x200c); 396 ucc_geth_phy_write(mii_info, 0x1e, 0x200c);
374 phy_write(mii_info, 0x1d, 0x5); 397 ucc_geth_phy_write(mii_info, 0x1d, 0x5);
375 phy_write(mii_info, 0x1e, 0); 398 ucc_geth_phy_write(mii_info, 0x1e, 0);
376 phy_write(mii_info, 0x1e, 0x100); 399 ucc_geth_phy_write(mii_info, 0x1e, 0x100);
377 400
378 gbit_config_aneg(mii_info); 401 gbit_config_aneg(mii_info);
379 402
@@ -398,7 +421,7 @@ static int marvell_read_status(struct ugeth_mii_info *mii_info)
398 * are as set */ 421 * are as set */
399 if (mii_info->autoneg && mii_info->link) { 422 if (mii_info->autoneg && mii_info->link) {
400 int speed; 423 int speed;
401 status = phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS); 424 status = ucc_geth_phy_read(mii_info, MII_M1011_PHY_SPEC_STATUS);
402 425
403 /* Get the duplexity */ 426 /* Get the duplexity */
404 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX) 427 if (status & MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX)
@@ -430,7 +453,7 @@ static int marvell_ack_interrupt(struct ugeth_mii_info *mii_info)
430 ugphy_vdbg("%s: IN", __FUNCTION__); 453 ugphy_vdbg("%s: IN", __FUNCTION__);
431 454
432 /* Clear the interrupts by reading the reg */ 455 /* Clear the interrupts by reading the reg */
433 phy_read(mii_info, MII_M1011_IEVENT); 456 ucc_geth_phy_read(mii_info, MII_M1011_IEVENT);
434 457
435 return 0; 458 return 0;
436} 459}
@@ -440,9 +463,9 @@ static int marvell_config_intr(struct ugeth_mii_info *mii_info)
440 ugphy_vdbg("%s: IN", __FUNCTION__); 463 ugphy_vdbg("%s: IN", __FUNCTION__);
441 464
442 if (mii_info->interrupts == MII_INTERRUPT_ENABLED) 465 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
443 phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT); 466 ucc_geth_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_INIT);
444 else 467 else
445 phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR); 468 ucc_geth_phy_write(mii_info, MII_M1011_IMASK, MII_M1011_IMASK_CLEAR);
446 469
447 return 0; 470 return 0;
448} 471}
@@ -451,9 +474,9 @@ static int cis820x_init(struct ugeth_mii_info *mii_info)
451{ 474{
452 ugphy_vdbg("%s: IN", __FUNCTION__); 475 ugphy_vdbg("%s: IN", __FUNCTION__);
453 476
454 phy_write(mii_info, MII_CIS8201_AUX_CONSTAT, 477 ucc_geth_phy_write(mii_info, MII_CIS8201_AUX_CONSTAT,
455 MII_CIS8201_AUXCONSTAT_INIT); 478 MII_CIS8201_AUXCONSTAT_INIT);
456 phy_write(mii_info, MII_CIS8201_EXT_CON1, MII_CIS8201_EXTCON1_INIT); 479 ucc_geth_phy_write(mii_info, MII_CIS8201_EXT_CON1, MII_CIS8201_EXTCON1_INIT);
457 480
458 return 0; 481 return 0;
459} 482}
@@ -477,7 +500,7 @@ static int cis820x_read_status(struct ugeth_mii_info *mii_info)
477 if (mii_info->autoneg && mii_info->link) { 500 if (mii_info->autoneg && mii_info->link) {
478 int speed; 501 int speed;
479 502
480 status = phy_read(mii_info, MII_CIS8201_AUX_CONSTAT); 503 status = ucc_geth_phy_read(mii_info, MII_CIS8201_AUX_CONSTAT);
481 if (status & MII_CIS8201_AUXCONSTAT_DUPLEX) 504 if (status & MII_CIS8201_AUXCONSTAT_DUPLEX)
482 mii_info->duplex = DUPLEX_FULL; 505 mii_info->duplex = DUPLEX_FULL;
483 else 506 else
@@ -505,7 +528,7 @@ static int cis820x_ack_interrupt(struct ugeth_mii_info *mii_info)
505{ 528{
506 ugphy_vdbg("%s: IN", __FUNCTION__); 529 ugphy_vdbg("%s: IN", __FUNCTION__);
507 530
508 phy_read(mii_info, MII_CIS8201_ISTAT); 531 ucc_geth_phy_read(mii_info, MII_CIS8201_ISTAT);
509 532
510 return 0; 533 return 0;
511} 534}
@@ -515,9 +538,9 @@ static int cis820x_config_intr(struct ugeth_mii_info *mii_info)
515 ugphy_vdbg("%s: IN", __FUNCTION__); 538 ugphy_vdbg("%s: IN", __FUNCTION__);
516 539
517 if (mii_info->interrupts == MII_INTERRUPT_ENABLED) 540 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
518 phy_write(mii_info, MII_CIS8201_IMASK, MII_CIS8201_IMASK_MASK); 541 ucc_geth_phy_write(mii_info, MII_CIS8201_IMASK, MII_CIS8201_IMASK_MASK);
519 else 542 else
520 phy_write(mii_info, MII_CIS8201_IMASK, 0); 543 ucc_geth_phy_write(mii_info, MII_CIS8201_IMASK, 0);
521 544
522 return 0; 545 return 0;
523} 546}
@@ -541,7 +564,7 @@ static int dm9161_read_status(struct ugeth_mii_info *mii_info)
541 /* If we aren't autonegotiating, assume speeds 564 /* If we aren't autonegotiating, assume speeds
542 * are as set */ 565 * are as set */
543 if (mii_info->autoneg && mii_info->link) { 566 if (mii_info->autoneg && mii_info->link) {
544 status = phy_read(mii_info, MII_DM9161_SCSR); 567 status = ucc_geth_phy_read(mii_info, MII_DM9161_SCSR);
545 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H)) 568 if (status & (MII_DM9161_SCSR_100F | MII_DM9161_SCSR_100H))
546 mii_info->speed = SPEED_100; 569 mii_info->speed = SPEED_100;
547 else 570 else
@@ -572,7 +595,7 @@ static void dm9161_timer(unsigned long data)
572{ 595{
573 struct ugeth_mii_info *mii_info = (struct ugeth_mii_info *)data; 596 struct ugeth_mii_info *mii_info = (struct ugeth_mii_info *)data;
574 struct dm9161_private *priv = mii_info->priv; 597 struct dm9161_private *priv = mii_info->priv;
575 u16 status = phy_read(mii_info, MII_BMSR); 598 u16 status = ucc_geth_phy_read(mii_info, MII_BMSR);
576 599
577 ugphy_vdbg("%s: IN", __FUNCTION__); 600 ugphy_vdbg("%s: IN", __FUNCTION__);
578 601
@@ -599,11 +622,11 @@ static int dm9161_init(struct ugeth_mii_info *mii_info)
599 /* Reset is not done yet */ 622 /* Reset is not done yet */
600 priv->resetdone = 0; 623 priv->resetdone = 0;
601 624
602 phy_write(mii_info, MII_BMCR, 625 ucc_geth_phy_write(mii_info, MII_BMCR,
603 phy_read(mii_info, MII_BMCR) | BMCR_RESET); 626 ucc_geth_phy_read(mii_info, MII_BMCR) | BMCR_RESET);
604 627
605 phy_write(mii_info, MII_BMCR, 628 ucc_geth_phy_write(mii_info, MII_BMCR,
606 phy_read(mii_info, MII_BMCR) & ~BMCR_ISOLATE); 629 ucc_geth_phy_read(mii_info, MII_BMCR) & ~BMCR_ISOLATE);
607 630
608 config_genmii_advert(mii_info); 631 config_genmii_advert(mii_info);
609 /* Start/Restart aneg */ 632 /* Start/Restart aneg */
@@ -634,7 +657,7 @@ static int dm9161_ack_interrupt(struct ugeth_mii_info *mii_info)
634 ugphy_vdbg("%s: IN", __FUNCTION__); 657 ugphy_vdbg("%s: IN", __FUNCTION__);
635 658
636 /* Clear the interrupts by reading the reg */ 659 /* Clear the interrupts by reading the reg */
637 phy_read(mii_info, MII_DM9161_INTR); 660 ucc_geth_phy_read(mii_info, MII_DM9161_INTR);
638 661
639 662
640 return 0; 663 return 0;
@@ -645,9 +668,9 @@ static int dm9161_config_intr(struct ugeth_mii_info *mii_info)
645 ugphy_vdbg("%s: IN", __FUNCTION__); 668 ugphy_vdbg("%s: IN", __FUNCTION__);
646 669
647 if (mii_info->interrupts == MII_INTERRUPT_ENABLED) 670 if (mii_info->interrupts == MII_INTERRUPT_ENABLED)
648 phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT); 671 ucc_geth_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_INIT);
649 else 672 else
650 phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP); 673 ucc_geth_phy_write(mii_info, MII_DM9161_INTR, MII_DM9161_INTR_STOP);
651 674
652 return 0; 675 return 0;
653} 676}
@@ -718,31 +741,6 @@ static struct phy_info *phy_info[] = {
718 NULL 741 NULL
719}; 742};
720 743
721u16 phy_read(struct ugeth_mii_info *mii_info, u16 regnum)
722{
723 u16 retval;
724 unsigned long flags;
725
726 ugphy_vdbg("%s: IN", __FUNCTION__);
727
728 spin_lock_irqsave(&mii_info->mdio_lock, flags);
729 retval = mii_info->mdio_read(mii_info->dev, mii_info->mii_id, regnum);
730 spin_unlock_irqrestore(&mii_info->mdio_lock, flags);
731
732 return retval;
733}
734
735void phy_write(struct ugeth_mii_info *mii_info, u16 regnum, u16 val)
736{
737 unsigned long flags;
738
739 ugphy_vdbg("%s: IN", __FUNCTION__);
740
741 spin_lock_irqsave(&mii_info->mdio_lock, flags);
742 mii_info->mdio_write(mii_info->dev, mii_info->mii_id, regnum, val);
743 spin_unlock_irqrestore(&mii_info->mdio_lock, flags);
744}
745
746/* Use the PHY ID registers to determine what type of PHY is attached 744/* Use the PHY ID registers to determine what type of PHY is attached
747 * to device dev. return a struct phy_info structure describing that PHY 745 * to device dev. return a struct phy_info structure describing that PHY
748 */ 746 */
@@ -757,11 +755,11 @@ struct phy_info *get_phy_info(struct ugeth_mii_info *mii_info)
757 ugphy_vdbg("%s: IN", __FUNCTION__); 755 ugphy_vdbg("%s: IN", __FUNCTION__);
758 756
759 /* Grab the bits from PHYIR1, and put them in the upper half */ 757 /* Grab the bits from PHYIR1, and put them in the upper half */
760 phy_reg = phy_read(mii_info, MII_PHYSID1); 758 phy_reg = ucc_geth_phy_read(mii_info, MII_PHYSID1);
761 phy_ID = (phy_reg & 0xffff) << 16; 759 phy_ID = (phy_reg & 0xffff) << 16;
762 760
763 /* Grab the bits from PHYIR2, and put them in the lower half */ 761 /* Grab the bits from PHYIR2, and put them in the lower half */
764 phy_reg = phy_read(mii_info, MII_PHYSID2); 762 phy_reg = ucc_geth_phy_read(mii_info, MII_PHYSID2);
765 phy_ID |= (phy_reg & 0xffff); 763 phy_ID |= (phy_reg & 0xffff);
766 764
767 /* loop through all the known PHY types, and find one that */ 765 /* loop through all the known PHY types, and find one that */
diff --git a/drivers/net/wireless/bcm43xx/bcm43xx_main.c b/drivers/net/wireless/bcm43xx/bcm43xx_main.c
index 2ec2e5afce67..91b752e3d07e 100644
--- a/drivers/net/wireless/bcm43xx/bcm43xx_main.c
+++ b/drivers/net/wireless/bcm43xx/bcm43xx_main.c
@@ -2701,8 +2701,8 @@ static int bcm43xx_probe_cores(struct bcm43xx_private *bcm)
2701 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI); 2701 sb_id_hi = bcm43xx_read32(bcm, BCM43xx_CIR_SB_ID_HI);
2702 2702
2703 /* extract core_id, core_rev, core_vendor */ 2703 /* extract core_id, core_rev, core_vendor */
2704 core_id = (sb_id_hi & 0xFFF0) >> 4; 2704 core_id = (sb_id_hi & 0x8FF0) >> 4;
2705 core_rev = (sb_id_hi & 0xF); 2705 core_rev = ((sb_id_hi & 0xF) | ((sb_id_hi & 0x7000) >> 8));
2706 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16; 2706 core_vendor = (sb_id_hi & 0xFFFF0000) >> 16;
2707 2707
2708 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x\n", 2708 dprintk(KERN_INFO PFX "Core %d: ID 0x%x, rev 0x%x, vendor 0x%x\n",
@@ -2873,7 +2873,10 @@ static int bcm43xx_wireless_core_init(struct bcm43xx_private *bcm,
2873 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW); 2873 sbimconfiglow = bcm43xx_read32(bcm, BCM43xx_CIR_SBIMCONFIGLOW);
2874 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK; 2874 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_REQUEST_TOUT_MASK;
2875 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK; 2875 sbimconfiglow &= ~ BCM43xx_SBIMCONFIGLOW_SERVICE_TOUT_MASK;
2876 sbimconfiglow |= 0x32; 2876 if (bcm->bustype == BCM43xx_BUSTYPE_PCI)
2877 sbimconfiglow |= 0x32;
2878 else
2879 sbimconfiglow |= 0x53;
2877 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow); 2880 bcm43xx_write32(bcm, BCM43xx_CIR_SBIMCONFIGLOW, sbimconfiglow);
2878 } 2881 }
2879 2882
@@ -3077,7 +3080,7 @@ static int bcm43xx_setup_backplane_pci_connection(struct bcm43xx_private *bcm,
3077 if (err) 3080 if (err)
3078 goto out; 3081 goto out;
3079 3082
3080 if (bcm->current_core->rev < 6 || 3083 if (bcm->current_core->rev < 6 &&
3081 bcm->current_core->id == BCM43xx_COREID_PCI) { 3084 bcm->current_core->id == BCM43xx_COREID_PCI) {
3082 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC); 3085 value = bcm43xx_read32(bcm, BCM43xx_CIR_SBINTVEC);
3083 value |= (1 << backplane_flag_nr); 3086 value |= (1 << backplane_flag_nr);