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authorKelly Doran <kel.p.doran@gmail.com>2012-11-06 19:02:04 -0500
committerBen Skeggs <bskeggs@redhat.com>2012-11-08 22:43:05 -0500
commit11d92561c81be2f4a7af37f035e1af294b960abe (patch)
tree5ecc6cf3659c7b2a57ecc84d04c25993ba5c12a0
parent7707b701ebfea64afa6bfb23aa318fd687892754 (diff)
drm/nvc0/disp: fix regression in vblank semaphore release
Signed-off-by: Kelly Doran <kel.p.doran@gmail.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
-rw-r--r--drivers/gpu/drm/nouveau/core/engine/disp/nv50.c20
1 files changed, 12 insertions, 8 deletions
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
index 16a9afb1060b..05a909a17cee 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/nv50.c
@@ -22,6 +22,8 @@
22 * Authors: Ben Skeggs 22 * Authors: Ben Skeggs
23 */ 23 */
24 24
25#include <subdev/bar.h>
26
25#include <engine/software.h> 27#include <engine/software.h>
26#include <engine/disp.h> 28#include <engine/disp.h>
27 29
@@ -37,6 +39,7 @@ nv50_disp_sclass[] = {
37static void 39static void
38nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc) 40nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
39{ 41{
42 struct nouveau_bar *bar = nouveau_bar(priv);
40 struct nouveau_disp *disp = &priv->base; 43 struct nouveau_disp *disp = &priv->base;
41 struct nouveau_software_chan *chan, *temp; 44 struct nouveau_software_chan *chan, *temp;
42 unsigned long flags; 45 unsigned long flags;
@@ -46,18 +49,19 @@ nv50_disp_intr_vblank(struct nv50_disp_priv *priv, int crtc)
46 if (chan->vblank.crtc != crtc) 49 if (chan->vblank.crtc != crtc)
47 continue; 50 continue;
48 51
49 nv_wr32(priv, 0x001704, chan->vblank.channel);
50 nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
51
52 if (nv_device(priv)->chipset == 0x50) { 52 if (nv_device(priv)->chipset == 0x50) {
53 nv_wr32(priv, 0x001704, chan->vblank.channel);
54 nv_wr32(priv, 0x001710, 0x80000000 | chan->vblank.ctxdma);
55 bar->flush(bar);
53 nv_wr32(priv, 0x001570, chan->vblank.offset); 56 nv_wr32(priv, 0x001570, chan->vblank.offset);
54 nv_wr32(priv, 0x001574, chan->vblank.value); 57 nv_wr32(priv, 0x001574, chan->vblank.value);
55 } else { 58 } else {
56 if (nv_device(priv)->chipset >= 0xc0) { 59 nv_wr32(priv, 0x001718, 0x80000000 | chan->vblank.channel);
57 nv_wr32(priv, 0x06000c, 60 bar->flush(bar);
58 upper_32_bits(chan->vblank.offset)); 61 nv_wr32(priv, 0x06000c,
59 } 62 upper_32_bits(chan->vblank.offset));
60 nv_wr32(priv, 0x060010, chan->vblank.offset); 63 nv_wr32(priv, 0x060010,
64 lower_32_bits(chan->vblank.offset));
61 nv_wr32(priv, 0x060014, chan->vblank.value); 65 nv_wr32(priv, 0x060014, chan->vblank.value);
62 } 66 }
63 67