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authorMark Salter <msalter@redhat.com>2011-10-04 12:12:20 -0400
committerMark Salter <msalter@redhat.com>2011-10-06 19:47:33 -0400
commit041cadca7008f08fb4785f2288c8127c16faa529 (patch)
tree19008ae2e32faf489f85e00838a571a5295c79f4
parentc1a144d77a6ca3a14ba3c0fec30bc4fd20b3d817 (diff)
C6X: devicetree support
This is the basic devicetree support for C6X. Currently, four boards are supported. Each one uses a different SoC part. Two of the four supported SoCs are multicore. One with 3 cores and the other with 6 cores. There is no coherency between the core-level caches, so SMP is not an option. It is possible to run separate kernel instances on the various cores. There is currently no C6X bootloader support for device trees so we build in the DTB for now. There are some interesting twists to the hardware which are of note for device tree support. Each core has its own interrupt controller which is controlled by special purpose core registers. This core controller provides 12 general purpose prioritized interrupt sources. Each core is contained within a hardware "module" which provides L1 and L2 caches, power control, and another interrupt controller which cascades into the core interrupt controller. These core module functions are controlled by memory mapped registers. The addresses for these registers are the same for each core. That is, when coreN accesses a module-level MMIO register at a given address, it accesses the register for coreN even though other cores would use the same address to access the register in the module containing those cores. Other hardware modules (timers, enet, etc) which are memory mapped can be accessed by all cores. The timers need some further explanation for multicore SoCs. Even though all timer control registers are visible to all cores, interrupt routing or other considerations may make a given timer more suitable for use by a core than some other timer. Because of this and the desire to have the same image run on more than one core, the timer nodes have a "ti,core-mask" property which is used by the driver to scan for a suitable timer to use. Signed-off-by: Mark Salter <msalter@redhat.com> Signed-off-by: Aurelien Jacquiot <a-jacquiot@ti.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/c6x/clocks.txt40
-rw-r--r--Documentation/devicetree/bindings/c6x/dscr.txt127
-rw-r--r--Documentation/devicetree/bindings/c6x/emifa.txt62
-rw-r--r--Documentation/devicetree/bindings/c6x/interrupt.txt104
-rw-r--r--Documentation/devicetree/bindings/c6x/soc.txt28
-rw-r--r--Documentation/devicetree/bindings/c6x/timer64.txt26
-rw-r--r--arch/c6x/boot/dts/dsk6455.dts62
-rw-r--r--arch/c6x/boot/dts/evmc6457.dts48
-rw-r--r--arch/c6x/boot/dts/evmc6472.dts73
-rw-r--r--arch/c6x/boot/dts/evmc6474.dts58
-rw-r--r--arch/c6x/boot/dts/tms320c6455.dtsi96
-rw-r--r--arch/c6x/boot/dts/tms320c6457.dtsi68
-rw-r--r--arch/c6x/boot/dts/tms320c6472.dtsi134
-rw-r--r--arch/c6x/boot/dts/tms320c6474.dtsi89
-rw-r--r--arch/c6x/boot/linked_dtb.S2
-rw-r--r--arch/c6x/kernel/devicetree.c53
-rw-r--r--arch/c6x/platforms/platform.c17
17 files changed, 1087 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/c6x/clocks.txt b/Documentation/devicetree/bindings/c6x/clocks.txt
new file mode 100644
index 000000000000..a04f5fd30122
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/clocks.txt
@@ -0,0 +1,40 @@
1C6X PLL Clock Controllers
2-------------------------
3
4This is a first-cut support for the SoC clock controllers. This is still
5under development and will probably change as the common device tree
6clock support is added to the kernel.
7
8Required properties:
9
10- compatible: "ti,c64x+pll"
11 May also have SoC-specific value to support SoC-specific initialization
12 in the driver. One of:
13 "ti,c6455-pll"
14 "ti,c6457-pll"
15 "ti,c6472-pll"
16 "ti,c6474-pll"
17
18- reg: base address and size of register area
19- clock-frequency: input clock frequency in hz
20
21
22Optional properties:
23
24- ti,c64x+pll-bypass-delay: CPU cycles to delay when entering bypass mode
25
26- ti,c64x+pll-reset-delay: CPU cycles to delay after PLL reset
27
28- ti,c64x+pll-lock-delay: CPU cycles to delay after PLL frequency change
29
30Example:
31
32 clock-controller@29a0000 {
33 compatible = "ti,c6472-pll", "ti,c64x+pll";
34 reg = <0x029a0000 0x200>;
35 clock-frequency = <25000000>;
36
37 ti,c64x+pll-bypass-delay = <200>;
38 ti,c64x+pll-reset-delay = <12000>;
39 ti,c64x+pll-lock-delay = <80000>;
40 };
diff --git a/Documentation/devicetree/bindings/c6x/dscr.txt b/Documentation/devicetree/bindings/c6x/dscr.txt
new file mode 100644
index 000000000000..d847758f2b20
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/dscr.txt
@@ -0,0 +1,127 @@
1Device State Configuration Registers
2------------------------------------
3
4TI C6X SoCs contain a region of miscellaneous registers which provide various
5function for SoC control or status. Details vary considerably among from SoC
6to SoC with no two being alike.
7
8In general, the Device State Configuraion Registers (DSCR) will provide one or
9more configuration registers often protected by a lock register where one or
10more key values must be written to a lock register in order to unlock the
11configuration register for writes. These configuration register may be used to
12enable (and disable in some cases) SoC pin drivers, select peripheral clock
13sources (internal or pin), etc. In some cases, a configuration register is
14write once or the individual bits are write once. In addition to device config,
15the DSCR block may provide registers which which are used to reset peripherals,
16provide device ID information, provide ethernet MAC addresses, as well as other
17miscellaneous functions.
18
19For device state control (enable/disable), each device control is assigned an
20id which is used by individual device drivers to control the state as needed.
21
22Required properties:
23
24- compatible: must be "ti,c64x+dscr"
25- reg: register area base and size
26
27Optional properties:
28
29 NOTE: These are optional in that not all SoCs will have all properties. For
30 SoCs which do support a given property, leaving the property out of the
31 device tree will result in reduced functionality or possibly driver
32 failure.
33
34- ti,dscr-devstat
35 offset of the devstat register
36
37- ti,dscr-silicon-rev
38 offset, start bit, and bitsize of silicon revision field
39
40- ti,dscr-rmii-resets
41 offset and bitmask of RMII reset field. May have multiple tuples if more
42 than one ethernet port is available.
43
44- ti,dscr-locked-regs
45 possibly multiple tuples describing registers which are write protected by
46 a lock register. Each tuple consists of the register offset, lock register
47 offsset, and the key value used to unlock the register.
48
49- ti,dscr-kick-regs
50 offset and key values of two "kick" registers used to write protect other
51 registers in DSCR. On SoCs using kick registers, the first key must be
52 written to the first kick register and the second key must be written to
53 the second register before other registers in the area are write-enabled.
54
55- ti,dscr-mac-fuse-regs
56 MAC addresses are contained in two registers. Each element of a MAC address
57 is contained in a single byte. This property has two tuples. Each tuple has
58 a register offset and four cells representing bytes in the register from
59 most significant to least. The value of these four cells is the MAC byte
60 index (1-6) of the byte within the register. A value of 0 means the byte
61 is unused in the MAC address.
62
63- ti,dscr-devstate-ctl-regs
64 This property describes the bitfields used to control the state of devices.
65 Each tuple describes a range of identical bitfields used to control one or
66 more devices (one bitfield per device). The layout of each tuple is:
67
68 start_id num_ids reg enable disable start_bit nbits
69
70 Where:
71 start_id is device id for the first device control in the range
72 num_ids is the number of device controls in the range
73 reg is the offset of the register holding the control bits
74 enable is the value to enable a device
75 disable is the value to disable a device (0xffffffff if cannot disable)
76 start_bit is the bit number of the first bit in the range
77 nbits is the number of bits per device control
78
79- ti,dscr-devstate-stat-regs
80 This property describes the bitfields used to provide device state status
81 for device states controlled by the DSCR. Each tuple describes a range of
82 identical bitfields used to provide status for one or more devices (one
83 bitfield per device). The layout of each tuple is:
84
85 start_id num_ids reg enable disable start_bit nbits
86
87 Where:
88 start_id is device id for the first device status in the range
89 num_ids is the number of devices covered by the range
90 reg is the offset of the register holding the status bits
91 enable is the value indicating device is enabled
92 disable is the value indicating device is disabled
93 start_bit is the bit number of the first bit in the range
94 nbits is the number of bits per device status
95
96- ti,dscr-privperm
97 Offset and default value for register used to set access privilege for
98 some SoC devices.
99
100
101Example:
102
103 device-state-config-regs@2a80000 {
104 compatible = "ti,c64x+dscr";
105 reg = <0x02a80000 0x41000>;
106
107 ti,dscr-devstat = <0>;
108 ti,dscr-silicon-rev = <8 28 0xf>;
109 ti,dscr-rmii-resets = <0x40020 0x00040000>;
110
111 ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
112 ti,dscr-devstate-ctl-regs =
113 <0 12 0x40008 1 0 0 2
114 12 1 0x40008 3 0 30 2
115 13 2 0x4002c 1 0xffffffff 0 1>;
116 ti,dscr-devstate-stat-regs =
117 <0 10 0x40014 1 0 0 3
118 10 2 0x40018 1 0 0 3>;
119
120 ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
121 0x704 5 6 0 0>;
122
123 ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
124
125 ti,dscr-kick-regs = <0x38 0x83E70B13
126 0x3c 0x95A4F1E0>;
127 };
diff --git a/Documentation/devicetree/bindings/c6x/emifa.txt b/Documentation/devicetree/bindings/c6x/emifa.txt
new file mode 100644
index 000000000000..0ff6e9b9a13f
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/emifa.txt
@@ -0,0 +1,62 @@
1External Memory Interface
2-------------------------
3
4The emifa node describes a simple external bus controller found on some C6X
5SoCs. This interface provides external busses with a number of chip selects.
6
7Required properties:
8
9- compatible: must be "ti,c64x+emifa", "simple-bus"
10- reg: register area base and size
11- #address-cells: must be 2 (chip-select + offset)
12- #size-cells: must be 1
13- ranges: mapping from EMIFA space to parent space
14
15
16Optional properties:
17
18- ti,dscr-dev-enable: Device ID if EMIF is enabled/disabled from DSCR
19
20- ti,emifa-burst-priority:
21 Number of memory transfers after which the EMIF will elevate the priority
22 of the oldest command in the command FIFO. Setting this field to 255
23 disables this feature, thereby allowing old commands to stay in the FIFO
24 indefinitely.
25
26- ti,emifa-ce-config:
27 Configuration values for each of the supported chip selects.
28
29Example:
30
31 emifa@70000000 {
32 compatible = "ti,c64x+emifa", "simple-bus";
33 #address-cells = <2>;
34 #size-cells = <1>;
35 reg = <0x70000000 0x100>;
36 ranges = <0x2 0x0 0xa0000000 0x00000008
37 0x3 0x0 0xb0000000 0x00400000
38 0x4 0x0 0xc0000000 0x10000000
39 0x5 0x0 0xD0000000 0x10000000>;
40
41 ti,dscr-dev-enable = <13>;
42 ti,emifa-burst-priority = <255>;
43 ti,emifa-ce-config = <0x00240120
44 0x00240120
45 0x00240122
46 0x00240122>;
47
48 flash@3,0 {
49 #address-cells = <1>;
50 #size-cells = <1>;
51 compatible = "cfi-flash";
52 reg = <0x3 0x0 0x400000>;
53 bank-width = <1>;
54 device-width = <1>;
55 partition@0 {
56 reg = <0x0 0x400000>;
57 label = "NOR";
58 };
59 };
60 };
61
62This shows a flash chip attached to chip select 3.
diff --git a/Documentation/devicetree/bindings/c6x/interrupt.txt b/Documentation/devicetree/bindings/c6x/interrupt.txt
new file mode 100644
index 000000000000..42bb796cc4ad
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/interrupt.txt
@@ -0,0 +1,104 @@
1C6X Interrupt Chips
2-------------------
3
4* C64X+ Core Interrupt Controller
5
6 The core interrupt controller provides 16 prioritized interrupts to the
7 C64X+ core. Priority 0 and 1 are used for reset and NMI respectively.
8 Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt
9 sources coming from outside the core.
10
11 Required properties:
12 --------------------
13 - compatible: Should be "ti,c64x+core-pic";
14 - #interrupt-cells: <1>
15
16 Interrupt Specifier Definition
17 ------------------------------
18 Single cell specifying the core interrupt priority level (4-15) where
19 4 is highest priority and 15 is lowest priority.
20
21 Example
22 -------
23 core_pic: interrupt-controller@0 {
24 interrupt-controller;
25 #interrupt-cells = <1>;
26 compatible = "ti,c64x+core-pic";
27 };
28
29
30
31* C64x+ Megamodule Interrupt Controller
32
33 The megamodule PIC consists of four interrupt mupliplexers each of which
34 combine up to 32 interrupt inputs into a single interrupt output which
35 may be cascaded into the core interrupt controller. The megamodule PIC
36 has a total of 12 outputs cascading into the core interrupt controller.
37 One for each core interrupt priority level. In addition to the combined
38 interrupt sources, individual megamodule interrupts may be cascaded to
39 the core interrupt controller. When an individual interrupt is cascaded,
40 it is no longer handled through a megamodule interrupt combiner and is
41 considered to have the core interrupt controller as the parent.
42
43 Required properties:
44 --------------------
45 - compatible: "ti,c64x+megamod-pic"
46 - interrupt-controller
47 - #interrupt-cells: <1>
48 - reg: base address and size of register area
49 - interrupt-parent: must be core interrupt controller
50 - interrupts: This should have four cells; one for each interrupt combiner.
51 The cells contain the core priority interrupt to which the
52 corresponding combiner output is wired.
53
54 Optional properties:
55 --------------------
56 - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core
57 priority interrupts. The first cell corresponds to
58 core priority 4 and the last cell corresponds to
59 core priority 15. The value of each cell is the
60 megamodule interrupt source which is MUXed to
61 the core interrupt corresponding to the cell
62 position. Allowed values are 4 - 127. Mapping for
63 interrupts 0 - 3 (combined interrupt sources) are
64 ignored.
65
66 Interrupt Specifier Definition
67 ------------------------------
68 Single cell specifying the megamodule interrupt source (4-127). Note that
69 interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will
70 use the core interrupt controller as their parent and the specifier will
71 be the core priority level, not the megamodule interrupt number.
72
73 Examples
74 --------
75 megamod_pic: interrupt-controller@1800000 {
76 compatible = "ti,c64x+megamod-pic";
77 interrupt-controller;
78 #interrupt-cells = <1>;
79 reg = <0x1800000 0x1000>;
80 interrupt-parent = <&core_pic>;
81 interrupts = < 12 13 14 15 >;
82 };
83
84 This is a minimal example where all individual interrupts go through a
85 combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped
86 to interrupt 13, etc.
87
88
89 megamod_pic: interrupt-controller@1800000 {
90 compatible = "ti,c64x+megamod-pic";
91 interrupt-controller;
92 #interrupt-cells = <1>;
93 reg = <0x1800000 0x1000>;
94 interrupt-parent = <&core_pic>;
95 interrupts = < 12 13 14 15 >;
96 ti,c64x+megamod-pic-mux = < 0 0 0 0
97 32 0 0 0
98 0 0 0 0 >;
99 };
100
101 This the same as the first example except that megamodule interrupt 32 is
102 mapped directly to core priority interrupt 8. The node using this interrupt
103 must set the core controller as its interrupt parent and use 8 in the
104 interrupt specifier value.
diff --git a/Documentation/devicetree/bindings/c6x/soc.txt b/Documentation/devicetree/bindings/c6x/soc.txt
new file mode 100644
index 000000000000..b1e4973b5769
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/soc.txt
@@ -0,0 +1,28 @@
1C6X System-on-Chip
2------------------
3
4Required properties:
5
6- compatible: "simple-bus"
7- #address-cells: must be 1
8- #size-cells: must be 1
9- ranges
10
11Optional properties:
12
13- model: specific SoC model
14
15- nodes for IP blocks within SoC
16
17
18Example:
19
20 soc {
21 compatible = "simple-bus";
22 model = "tms320c6455";
23 #address-cells = <1>;
24 #size-cells = <1>;
25 ranges;
26
27 ...
28 };
diff --git a/Documentation/devicetree/bindings/c6x/timer64.txt b/Documentation/devicetree/bindings/c6x/timer64.txt
new file mode 100644
index 000000000000..95911fe70224
--- /dev/null
+++ b/Documentation/devicetree/bindings/c6x/timer64.txt
@@ -0,0 +1,26 @@
1Timer64
2-------
3
4The timer64 node describes C6X event timers.
5
6Required properties:
7
8- compatible: must be "ti,c64x+timer64"
9- reg: base address and size of register region
10- interrupt-parent: interrupt controller
11- interrupts: interrupt id
12
13Optional properties:
14
15- ti,dscr-dev-enable: Device ID used to enable timer IP through DSCR interface.
16
17- ti,core-mask: on multi-core SoCs, bitmask of cores allowed to use this timer.
18
19Example:
20 timer0: timer@25e0000 {
21 compatible = "ti,c64x+timer64";
22 ti,core-mask = < 0x01 >;
23 reg = <0x25e0000 0x40>;
24 interrupt-parent = <&megamod_pic>;
25 interrupts = < 16 >;
26 };
diff --git a/arch/c6x/boot/dts/dsk6455.dts b/arch/c6x/boot/dts/dsk6455.dts
new file mode 100644
index 000000000000..2b71f800618d
--- /dev/null
+++ b/arch/c6x/boot/dts/dsk6455.dts
@@ -0,0 +1,62 @@
1/*
2 * arch/c6x/boot/dts/dsk6455.dts
3 *
4 * DSK6455 Evaluation Platform For TMS320C6455
5 * Copyright (C) 2011 Texas Instruments Incorporated
6 *
7 * Author: Mark Salter <msalter@redhat.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 */
15
16/dts-v1/;
17
18/include/ "tms320c6455.dtsi"
19
20/ {
21 model = "Spectrum Digital DSK6455";
22 compatible = "spectrum-digital,dsk6455";
23
24 chosen {
25 bootargs = "root=/dev/nfs ip=dhcp rw";
26 };
27
28 memory {
29 device_type = "memory";
30 reg = <0xE0000000 0x08000000>;
31 };
32
33 soc {
34 megamod_pic: interrupt-controller@1800000 {
35 interrupts = < 12 13 14 15 >;
36 };
37
38 emifa@70000000 {
39 flash@3,0 {
40 #address-cells = <1>;
41 #size-cells = <1>;
42 compatible = "cfi-flash";
43 reg = <0x3 0x0 0x400000>;
44 bank-width = <1>;
45 device-width = <1>;
46 partition@0 {
47 reg = <0x0 0x400000>;
48 label = "NOR";
49 };
50 };
51 };
52
53 timer1: timer@2980000 {
54 interrupt-parent = <&megamod_pic>;
55 interrupts = < 69 >;
56 };
57
58 clock-controller@029a0000 {
59 clock-frequency = <50000000>;
60 };
61 };
62};
diff --git a/arch/c6x/boot/dts/evmc6457.dts b/arch/c6x/boot/dts/evmc6457.dts
new file mode 100644
index 000000000000..0301eb9a8ff8
--- /dev/null
+++ b/arch/c6x/boot/dts/evmc6457.dts
@@ -0,0 +1,48 @@
1/*
2 * arch/c6x/boot/dts/evmc6457.dts
3 *
4 * EVMC6457 Evaluation Platform For TMS320C6457
5 *
6 * Copyright (C) 2011 Texas Instruments Incorporated
7 *
8 * Author: Mark Salter <msalter@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 */
16
17/dts-v1/;
18
19/include/ "tms320c6457.dtsi"
20
21/ {
22 model = "eInfochips EVMC6457";
23 compatible = "einfochips,evmc6457";
24
25 chosen {
26 bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0xE0000000 0x10000000>;
32 };
33
34 soc {
35 megamod_pic: interrupt-controller@1800000 {
36 interrupts = < 12 13 14 15 >;
37 };
38
39 timer0: timer@2940000 {
40 interrupt-parent = <&megamod_pic>;
41 interrupts = < 67 >;
42 };
43
44 clock-controller@29a0000 {
45 clock-frequency = <60000000>;
46 };
47 };
48};
diff --git a/arch/c6x/boot/dts/evmc6472.dts b/arch/c6x/boot/dts/evmc6472.dts
new file mode 100644
index 000000000000..3e207b449a93
--- /dev/null
+++ b/arch/c6x/boot/dts/evmc6472.dts
@@ -0,0 +1,73 @@
1/*
2 * arch/c6x/boot/dts/evmc6472.dts
3 *
4 * EVMC6472 Evaluation Platform For TMS320C6472
5 *
6 * Copyright (C) 2011 Texas Instruments Incorporated
7 *
8 * Author: Mark Salter <msalter@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 */
16
17/dts-v1/;
18
19/include/ "tms320c6472.dtsi"
20
21/ {
22 model = "eInfochips EVMC6472";
23 compatible = "einfochips,evmc6472";
24
25 chosen {
26 bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0xE0000000 0x10000000>;
32 };
33
34 soc {
35 megamod_pic: interrupt-controller@1800000 {
36 interrupts = < 12 13 14 15 >;
37 };
38
39 timer0: timer@25e0000 {
40 interrupt-parent = <&megamod_pic>;
41 interrupts = < 16 >;
42 };
43
44 timer1: timer@25f0000 {
45 interrupt-parent = <&megamod_pic>;
46 interrupts = < 16 >;
47 };
48
49 timer2: timer@2600000 {
50 interrupt-parent = <&megamod_pic>;
51 interrupts = < 16 >;
52 };
53
54 timer3: timer@2610000 {
55 interrupt-parent = <&megamod_pic>;
56 interrupts = < 16 >;
57 };
58
59 timer4: timer@2620000 {
60 interrupt-parent = <&megamod_pic>;
61 interrupts = < 16 >;
62 };
63
64 timer5: timer@2630000 {
65 interrupt-parent = <&megamod_pic>;
66 interrupts = < 16 >;
67 };
68
69 clock-controller@29a0000 {
70 clock-frequency = <25000000>;
71 };
72 };
73};
diff --git a/arch/c6x/boot/dts/evmc6474.dts b/arch/c6x/boot/dts/evmc6474.dts
new file mode 100644
index 000000000000..4dc291292bc4
--- /dev/null
+++ b/arch/c6x/boot/dts/evmc6474.dts
@@ -0,0 +1,58 @@
1/*
2 * arch/c6x/boot/dts/evmc6474.dts
3 *
4 * EVMC6474 Evaluation Platform For TMS320C6474
5 *
6 * Copyright (C) 2011 Texas Instruments Incorporated
7 *
8 * Author: Mark Salter <msalter@redhat.com>
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 *
15 */
16
17/dts-v1/;
18
19/include/ "tms320c6474.dtsi"
20
21/ {
22 model = "Spectrum Digital EVMC6474";
23 compatible = "spectrum-digital,evmc6474";
24
25 chosen {
26 bootargs = "console=hvc root=/dev/nfs ip=dhcp rw";
27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0x80000000 0x08000000>;
32 };
33
34 soc {
35 megamod_pic: interrupt-controller@1800000 {
36 interrupts = < 12 13 14 15 >;
37 };
38
39 timer3: timer@2940000 {
40 interrupt-parent = <&megamod_pic>;
41 interrupts = < 39 >;
42 };
43
44 timer4: timer@2950000 {
45 interrupt-parent = <&megamod_pic>;
46 interrupts = < 41 >;
47 };
48
49 timer5: timer@2960000 {
50 interrupt-parent = <&megamod_pic>;
51 interrupts = < 43 >;
52 };
53
54 clock-controller@29a0000 {
55 clock-frequency = <50000000>;
56 };
57 };
58};
diff --git a/arch/c6x/boot/dts/tms320c6455.dtsi b/arch/c6x/boot/dts/tms320c6455.dtsi
new file mode 100644
index 000000000000..a804ec1e018b
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6455.dtsi
@@ -0,0 +1,96 @@
1
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 cpu@0 {
11 device_type = "cpu";
12 model = "ti,c64x+";
13 reg = <0>;
14 };
15 };
16
17 soc {
18 compatible = "simple-bus";
19 model = "tms320c6455";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
23
24 core_pic: interrupt-controller {
25 interrupt-controller;
26 #interrupt-cells = <1>;
27 compatible = "ti,c64x+core-pic";
28 };
29
30 /*
31 * Megamodule interrupt controller
32 */
33 megamod_pic: interrupt-controller@1800000 {
34 compatible = "ti,c64x+megamod-pic";
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 reg = <0x1800000 0x1000>;
38 interrupt-parent = <&core_pic>;
39 };
40
41 cache-controller@1840000 {
42 compatible = "ti,c64x+cache";
43 reg = <0x01840000 0x8400>;
44 };
45
46 emifa@70000000 {
47 compatible = "ti,c64x+emifa", "simple-bus";
48 #address-cells = <2>;
49 #size-cells = <1>;
50 reg = <0x70000000 0x100>;
51 ranges = <0x2 0x0 0xa0000000 0x00000008
52 0x3 0x0 0xb0000000 0x00400000
53 0x4 0x0 0xc0000000 0x10000000
54 0x5 0x0 0xD0000000 0x10000000>;
55
56 ti,dscr-dev-enable = <13>;
57 ti,emifa-burst-priority = <255>;
58 ti,emifa-ce-config = <0x00240120
59 0x00240120
60 0x00240122
61 0x00240122>;
62 };
63
64 timer1: timer@2980000 {
65 compatible = "ti,c64x+timer64";
66 reg = <0x2980000 0x40>;
67 ti,dscr-dev-enable = <4>;
68 };
69
70 clock-controller@029a0000 {
71 compatible = "ti,c6455-pll", "ti,c64x+pll";
72 reg = <0x029a0000 0x200>;
73 ti,c64x+pll-bypass-delay = <1440>;
74 ti,c64x+pll-reset-delay = <15360>;
75 ti,c64x+pll-lock-delay = <24000>;
76 };
77
78 device-state-config-regs@2a80000 {
79 compatible = "ti,c64x+dscr";
80 reg = <0x02a80000 0x41000>;
81
82 ti,dscr-devstat = <0>;
83 ti,dscr-silicon-rev = <8 28 0xf>;
84 ti,dscr-rmii-resets = <0 0x40020 0x00040000>;
85
86 ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
87 ti,dscr-devstate-ctl-regs =
88 <0 12 0x40008 1 0 0 2
89 12 1 0x40008 3 0 30 2
90 13 2 0x4002c 1 0xffffffff 0 1>;
91 ti,dscr-devstate-stat-regs =
92 <0 10 0x40014 1 0 0 3
93 10 2 0x40018 1 0 0 3>;
94 };
95 };
96};
diff --git a/arch/c6x/boot/dts/tms320c6457.dtsi b/arch/c6x/boot/dts/tms320c6457.dtsi
new file mode 100644
index 000000000000..35f40709a719
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6457.dtsi
@@ -0,0 +1,68 @@
1
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 cpu@0 {
11 device_type = "cpu";
12 model = "ti,c64x+";
13 reg = <0>;
14 };
15 };
16
17 soc {
18 compatible = "simple-bus";
19 model = "tms320c6457";
20 #address-cells = <1>;
21 #size-cells = <1>;
22 ranges;
23
24 core_pic: interrupt-controller {
25 interrupt-controller;
26 #interrupt-cells = <1>;
27 compatible = "ti,c64x+core-pic";
28 };
29
30 megamod_pic: interrupt-controller@1800000 {
31 compatible = "ti,c64x+megamod-pic";
32 interrupt-controller;
33 #interrupt-cells = <1>;
34 interrupt-parent = <&core_pic>;
35 reg = <0x1800000 0x1000>;
36 };
37
38 cache-controller@1840000 {
39 compatible = "ti,c64x+cache";
40 reg = <0x01840000 0x8400>;
41 };
42
43 device-state-controller@2880800 {
44 compatible = "ti,c64x+dscr";
45 reg = <0x02880800 0x400>;
46
47 ti,dscr-devstat = <0x20>;
48 ti,dscr-silicon-rev = <0x18 28 0xf>;
49 ti,dscr-mac-fuse-regs = <0x114 3 4 5 6
50 0x118 0 0 1 2>;
51 ti,dscr-kick-regs = <0x38 0x83E70B13
52 0x3c 0x95A4F1E0>;
53 };
54
55 timer0: timer@2940000 {
56 compatible = "ti,c64x+timer64";
57 reg = <0x2940000 0x40>;
58 };
59
60 clock-controller@29a0000 {
61 compatible = "ti,c6457-pll", "ti,c64x+pll";
62 reg = <0x029a0000 0x200>;
63 ti,c64x+pll-bypass-delay = <300>;
64 ti,c64x+pll-reset-delay = <24000>;
65 ti,c64x+pll-lock-delay = <50000>;
66 };
67 };
68};
diff --git a/arch/c6x/boot/dts/tms320c6472.dtsi b/arch/c6x/boot/dts/tms320c6472.dtsi
new file mode 100644
index 000000000000..b488aaec65c0
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6472.dtsi
@@ -0,0 +1,134 @@
1
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 cpu@0 {
11 device_type = "cpu";
12 reg = <0>;
13 model = "ti,c64x+";
14 };
15 cpu@1 {
16 device_type = "cpu";
17 reg = <1>;
18 model = "ti,c64x+";
19 };
20 cpu@2 {
21 device_type = "cpu";
22 reg = <2>;
23 model = "ti,c64x+";
24 };
25 cpu@3 {
26 device_type = "cpu";
27 reg = <3>;
28 model = "ti,c64x+";
29 };
30 cpu@4 {
31 device_type = "cpu";
32 reg = <4>;
33 model = "ti,c64x+";
34 };
35 cpu@5 {
36 device_type = "cpu";
37 reg = <5>;
38 model = "ti,c64x+";
39 };
40 };
41
42 soc {
43 compatible = "simple-bus";
44 model = "tms320c6472";
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 core_pic: interrupt-controller {
50 compatible = "ti,c64x+core-pic";
51 interrupt-controller;
52 #interrupt-cells = <1>;
53 };
54
55 megamod_pic: interrupt-controller@1800000 {
56 compatible = "ti,c64x+megamod-pic";
57 interrupt-controller;
58 #interrupt-cells = <1>;
59 reg = <0x1800000 0x1000>;
60 interrupt-parent = <&core_pic>;
61 };
62
63 cache-controller@1840000 {
64 compatible = "ti,c64x+cache";
65 reg = <0x01840000 0x8400>;
66 };
67
68 timer0: timer@25e0000 {
69 compatible = "ti,c64x+timer64";
70 ti,core-mask = < 0x01 >;
71 reg = <0x25e0000 0x40>;
72 };
73
74 timer1: timer@25f0000 {
75 compatible = "ti,c64x+timer64";
76 ti,core-mask = < 0x02 >;
77 reg = <0x25f0000 0x40>;
78 };
79
80 timer2: timer@2600000 {
81 compatible = "ti,c64x+timer64";
82 ti,core-mask = < 0x04 >;
83 reg = <0x2600000 0x40>;
84 };
85
86 timer3: timer@2610000 {
87 compatible = "ti,c64x+timer64";
88 ti,core-mask = < 0x08 >;
89 reg = <0x2610000 0x40>;
90 };
91
92 timer4: timer@2620000 {
93 compatible = "ti,c64x+timer64";
94 ti,core-mask = < 0x10 >;
95 reg = <0x2620000 0x40>;
96 };
97
98 timer5: timer@2630000 {
99 compatible = "ti,c64x+timer64";
100 ti,core-mask = < 0x20 >;
101 reg = <0x2630000 0x40>;
102 };
103
104 clock-controller@29a0000 {
105 compatible = "ti,c6472-pll", "ti,c64x+pll";
106 reg = <0x029a0000 0x200>;
107 ti,c64x+pll-bypass-delay = <200>;
108 ti,c64x+pll-reset-delay = <12000>;
109 ti,c64x+pll-lock-delay = <80000>;
110 };
111
112 device-state-controller@2a80000 {
113 compatible = "ti,c64x+dscr";
114 reg = <0x02a80000 0x1000>;
115
116 ti,dscr-devstat = <0>;
117 ti,dscr-silicon-rev = <0x70c 16 0xff>;
118
119 ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
120 0x704 5 6 0 0>;
121
122 ti,dscr-rmii-resets = <0x208 1
123 0x20c 1>;
124
125 ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a
126 0x40c 0x420 0xbea7
127 0x41c 0x420 0xbea7>;
128
129 ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
130
131 ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>;
132 };
133 };
134};
diff --git a/arch/c6x/boot/dts/tms320c6474.dtsi b/arch/c6x/boot/dts/tms320c6474.dtsi
new file mode 100644
index 000000000000..cc601bf348a1
--- /dev/null
+++ b/arch/c6x/boot/dts/tms320c6474.dtsi
@@ -0,0 +1,89 @@
1
2/ {
3 #address-cells = <1>;
4 #size-cells = <1>;
5
6 cpus {
7 #address-cells = <1>;
8 #size-cells = <0>;
9
10 cpu@0 {
11 device_type = "cpu";
12 reg = <0>;
13 model = "ti,c64x+";
14 };
15 cpu@1 {
16 device_type = "cpu";
17 reg = <1>;
18 model = "ti,c64x+";
19 };
20 cpu@2 {
21 device_type = "cpu";
22 reg = <2>;
23 model = "ti,c64x+";
24 };
25 };
26
27 soc {
28 compatible = "simple-bus";
29 model = "tms320c6474";
30 #address-cells = <1>;
31 #size-cells = <1>;
32 ranges;
33
34 core_pic: interrupt-controller {
35 interrupt-controller;
36 #interrupt-cells = <1>;
37 compatible = "ti,c64x+core-pic";
38 };
39
40 megamod_pic: interrupt-controller@1800000 {
41 compatible = "ti,c64x+megamod-pic";
42 interrupt-controller;
43 #interrupt-cells = <1>;
44 reg = <0x1800000 0x1000>;
45 interrupt-parent = <&core_pic>;
46 };
47
48 cache-controller@1840000 {
49 compatible = "ti,c64x+cache";
50 reg = <0x01840000 0x8400>;
51 };
52
53 timer3: timer@2940000 {
54 compatible = "ti,c64x+timer64";
55 ti,core-mask = < 0x04 >;
56 reg = <0x2940000 0x40>;
57 };
58
59 timer4: timer@2950000 {
60 compatible = "ti,c64x+timer64";
61 ti,core-mask = < 0x02 >;
62 reg = <0x2950000 0x40>;
63 };
64
65 timer5: timer@2960000 {
66 compatible = "ti,c64x+timer64";
67 ti,core-mask = < 0x01 >;
68 reg = <0x2960000 0x40>;
69 };
70
71 device-state-controller@2880800 {
72 compatible = "ti,c64x+dscr";
73 reg = <0x02880800 0x400>;
74
75 ti,dscr-devstat = <0x004>;
76 ti,dscr-silicon-rev = <0x014 28 0xf>;
77 ti,dscr-mac-fuse-regs = <0x34 3 4 5 6
78 0x38 0 0 1 2>;
79 };
80
81 clock-controller@29a0000 {
82 compatible = "ti,c6474-pll", "ti,c64x+pll";
83 reg = <0x029a0000 0x200>;
84 ti,c64x+pll-bypass-delay = <120>;
85 ti,c64x+pll-reset-delay = <30000>;
86 ti,c64x+pll-lock-delay = <60000>;
87 };
88 };
89};
diff --git a/arch/c6x/boot/linked_dtb.S b/arch/c6x/boot/linked_dtb.S
new file mode 100644
index 000000000000..57a4454eaec3
--- /dev/null
+++ b/arch/c6x/boot/linked_dtb.S
@@ -0,0 +1,2 @@
1.section __fdt_blob,"a"
2.incbin "arch/c6x/boot/builtin.dtb"
diff --git a/arch/c6x/kernel/devicetree.c b/arch/c6x/kernel/devicetree.c
new file mode 100644
index 000000000000..bdb56f09d0ac
--- /dev/null
+++ b/arch/c6x/kernel/devicetree.c
@@ -0,0 +1,53 @@
1/*
2 * Architecture specific OF callbacks.
3 *
4 * Copyright (C) 2011 Texas Instruments Incorporated
5 * Author: Mark Salter <msalter@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12#include <linux/init.h>
13#include <linux/of.h>
14#include <linux/of_fdt.h>
15#include <linux/initrd.h>
16#include <linux/memblock.h>
17
18void __init early_init_devtree(void *params)
19{
20 /* Setup flat device-tree pointer */
21 initial_boot_params = params;
22
23 /* Retrieve various informations from the /chosen node of the
24 * device-tree, including the platform type, initrd location and
25 * size and more ...
26 */
27 of_scan_flat_dt(early_init_dt_scan_chosen, c6x_command_line);
28
29 /* Scan memory nodes and rebuild MEMBLOCKs */
30 of_scan_flat_dt(early_init_dt_scan_root, NULL);
31 of_scan_flat_dt(early_init_dt_scan_memory, NULL);
32}
33
34
35#ifdef CONFIG_BLK_DEV_INITRD
36void __init early_init_dt_setup_initrd_arch(unsigned long start,
37 unsigned long end)
38{
39 initrd_start = (unsigned long)__va(start);
40 initrd_end = (unsigned long)__va(end);
41 initrd_below_start_ok = 1;
42}
43#endif
44
45void __init early_init_dt_add_memory_arch(u64 base, u64 size)
46{
47 c6x_add_memory(base, size);
48}
49
50void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
51{
52 return __va(memblock_alloc(size, align));
53}
diff --git a/arch/c6x/platforms/platform.c b/arch/c6x/platforms/platform.c
new file mode 100644
index 000000000000..26c1a355d600
--- /dev/null
+++ b/arch/c6x/platforms/platform.c
@@ -0,0 +1,17 @@
1/*
2 * Copyright 2011 Texas Instruments Incorporated
3 *
4 * This file is licensed under the terms of the GNU General Public License
5 * version 2. This program is licensed "as is" without any warranty of any
6 * kind, whether express or implied.
7 */
8
9#include <linux/init.h>
10#include <linux/of_platform.h>
11
12static int __init c6x_device_probe(void)
13{
14 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
15 return 0;
16}
17core_initcall(c6x_device_probe);
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 22:28:59 -0500