diff options
| author | Kenneth Graunke <kenneth@whitecape.org> | 2011-10-11 17:41:08 -0400 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2011-10-20 18:26:40 -0400 |
| commit | fcbc34e4dc9ed43f5b147e95beec56c987c683c5 (patch) | |
| tree | 459f2606b6c25a93bd4e7969d4246f0d9eae196a | |
| parent | b73fe58cafc6954db0170a5d4ef2b4b6316f6709 (diff) | |
drm/i915: Remove implied length of 2 from GFX_OP_PIPE_CONTROL #define.
Not all PIPE_CONTROLs have a length of 2, so remove it from the #define
and make each invocation specify the desired length.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
[danvet: implement style suggestion from Ben Widawsdy]
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Keith Packard <keithp@keithp.com>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 8 |
2 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 28a313a04926..1b07547e26ce 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h | |||
| @@ -242,7 +242,7 @@ | |||
| 242 | #define ASYNC_FLIP (1<<22) | 242 | #define ASYNC_FLIP (1<<22) |
| 243 | #define DISPLAY_PLANE_A (0<<20) | 243 | #define DISPLAY_PLANE_A (0<<20) |
| 244 | #define DISPLAY_PLANE_B (1<<20) | 244 | #define DISPLAY_PLANE_B (1<<20) |
| 245 | #define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2) | 245 | #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2)) |
| 246 | #define PIPE_CONTROL_QW_WRITE (1<<14) | 246 | #define PIPE_CONTROL_QW_WRITE (1<<14) |
| 247 | #define PIPE_CONTROL_DEPTH_STALL (1<<13) | 247 | #define PIPE_CONTROL_DEPTH_STALL (1<<13) |
| 248 | #define PIPE_CONTROL_WC_FLUSH (1<<12) | 248 | #define PIPE_CONTROL_WC_FLUSH (1<<12) |
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 0e99589b54e0..7f188c9caf0d 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c | |||
| @@ -438,8 +438,8 @@ gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter, | |||
| 438 | 438 | ||
| 439 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ | 439 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 440 | do { \ | 440 | do { \ |
| 441 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \ | 441 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
| 442 | PIPE_CONTROL_DEPTH_STALL | 2); \ | 442 | PIPE_CONTROL_DEPTH_STALL); \ |
| 443 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ | 443 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 444 | intel_ring_emit(ring__, 0); \ | 444 | intel_ring_emit(ring__, 0); \ |
| 445 | intel_ring_emit(ring__, 0); \ | 445 | intel_ring_emit(ring__, 0); \ |
| @@ -467,7 +467,7 @@ pc_render_add_request(struct intel_ring_buffer *ring, | |||
| 467 | if (ret) | 467 | if (ret) |
| 468 | return ret; | 468 | return ret; |
| 469 | 469 | ||
| 470 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | | 470 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
| 471 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); | 471 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH); |
| 472 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | 472 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 473 | intel_ring_emit(ring, seqno); | 473 | intel_ring_emit(ring, seqno); |
| @@ -483,7 +483,7 @@ pc_render_add_request(struct intel_ring_buffer *ring, | |||
| 483 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | 483 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 484 | scratch_addr += 128; | 484 | scratch_addr += 128; |
| 485 | PIPE_CONTROL_FLUSH(ring, scratch_addr); | 485 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 486 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | | 486 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
| 487 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | | 487 | PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH | |
| 488 | PIPE_CONTROL_NOTIFY); | 488 | PIPE_CONTROL_NOTIFY); |
| 489 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); | 489 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |