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authorMagnus Damm <damm@opensource.se>2011-12-13 11:01:05 -0500
committerPaul Mundt <lethal@linux-sh.org>2012-01-08 19:33:55 -0500
commitf78a26f55b2438c439609fc90b473f7f08f5b697 (patch)
tree40359c326c23ccbc4c1f014f04aa60b97db6994e
parent18925e118b3b4d55b45711218cd3c3c4360e5cd1 (diff)
sh: pfc: Variable bitfield width config register support
Add support for variable config reg hardware by adding the macro PINMUX_CFG_REG_VAR(). The width of each bitfield needs to be passed to the macro, and the correct space must be consumed by each bitfield in the enum table following the macro. Data registers still need to have fixed bitfields. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--drivers/sh/pfc.c44
-rw-r--r--include/linux/sh_pfc.h9
2 files changed, 41 insertions, 12 deletions
diff --git a/drivers/sh/pfc.c b/drivers/sh/pfc.c
index 5481d19518f9..f975f4a33439 100644
--- a/drivers/sh/pfc.c
+++ b/drivers/sh/pfc.c
@@ -174,10 +174,19 @@ static void config_reg_helper(struct pinmux_info *gpioc,
174 unsigned long *maskp, 174 unsigned long *maskp,
175 unsigned long *posp) 175 unsigned long *posp)
176{ 176{
177 int k;
178
177 *mapped_regp = pfc_phys_to_virt(gpioc, crp->reg); 179 *mapped_regp = pfc_phys_to_virt(gpioc, crp->reg);
178 180
179 *maskp = (1 << crp->field_width) - 1; 181 if (crp->field_width) {
180 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width); 182 *maskp = (1 << crp->field_width) - 1;
183 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
184 } else {
185 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
186 *posp = crp->reg_width;
187 for (k = 0; k <= in_pos; k++)
188 *posp -= crp->var_field_width[k];
189 }
181} 190}
182 191
183static int read_config_reg(struct pinmux_info *gpioc, 192static int read_config_reg(struct pinmux_info *gpioc,
@@ -303,8 +312,8 @@ static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
303 unsigned long **cntp) 312 unsigned long **cntp)
304{ 313{
305 struct pinmux_cfg_reg *config_reg; 314 struct pinmux_cfg_reg *config_reg;
306 unsigned long r_width, f_width; 315 unsigned long r_width, f_width, curr_width, ncomb;
307 int k, n; 316 int k, m, n, pos, bit_pos;
308 317
309 k = 0; 318 k = 0;
310 while (1) { 319 while (1) {
@@ -315,14 +324,27 @@ static int get_config_reg(struct pinmux_info *gpioc, pinmux_enum_t enum_id,
315 324
316 if (!r_width) 325 if (!r_width)
317 break; 326 break;
318 for (n = 0; n < (r_width / f_width) * (1 << f_width); n++) { 327
319 if (config_reg->enum_ids[n] == enum_id) { 328 pos = 0;
320 *crp = config_reg; 329 m = 0;
321 *fieldp = n / (1 << f_width); 330 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
322 *valuep = n % (1 << f_width); 331 if (f_width)
323 *cntp = &config_reg->cnt[n / (1 << f_width)]; 332 curr_width = f_width;
324 return 0; 333 else
334 curr_width = config_reg->var_field_width[m];
335
336 ncomb = 1 << curr_width;
337 for (n = 0; n < ncomb; n++) {
338 if (config_reg->enum_ids[pos + n] == enum_id) {
339 *crp = config_reg;
340 *fieldp = m;
341 *valuep = n;
342 *cntp = &config_reg->cnt[m];
343 return 0;
344 }
325 } 345 }
346 pos += ncomb;
347 m++;
326 } 348 }
327 k++; 349 k++;
328 } 350 }
diff --git a/include/linux/sh_pfc.h b/include/linux/sh_pfc.h
index 91666a58529d..84538c42d64a 100644
--- a/include/linux/sh_pfc.h
+++ b/include/linux/sh_pfc.h
@@ -45,12 +45,19 @@ struct pinmux_cfg_reg {
45 unsigned long reg, reg_width, field_width; 45 unsigned long reg, reg_width, field_width;
46 unsigned long *cnt; 46 unsigned long *cnt;
47 pinmux_enum_t *enum_ids; 47 pinmux_enum_t *enum_ids;
48 unsigned long *var_field_width;
48}; 49};
49 50
50#define PINMUX_CFG_REG(name, r, r_width, f_width) \ 51#define PINMUX_CFG_REG(name, r, r_width, f_width) \
51 .reg = r, .reg_width = r_width, .field_width = f_width, \ 52 .reg = r, .reg_width = r_width, .field_width = f_width, \
52 .cnt = (unsigned long [r_width / f_width]) {}, \ 53 .cnt = (unsigned long [r_width / f_width]) {}, \
53 .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)]) \ 54 .enum_ids = (pinmux_enum_t [(r_width / f_width) * (1 << f_width)])
55
56#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
57 .reg = r, .reg_width = r_width, \
58 .cnt = (unsigned long [r_width]) {}, \
59 .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \
60 .enum_ids = (pinmux_enum_t [])
54 61
55struct pinmux_data_reg { 62struct pinmux_data_reg {
56 unsigned long reg, reg_width, reg_shadow; 63 unsigned long reg, reg_width, reg_shadow;